LLVM  7.0.0svn
PPCISelDAGToDAG.cpp
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1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
12 //
13 //===----------------------------------------------------------------------===//
14 
17 #include "PPC.h"
18 #include "PPCISelLowering.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCSubtarget.h"
21 #include "PPCTargetMachine.h"
22 #include "llvm/ADT/APInt.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallPtrSet.h"
26 #include "llvm/ADT/SmallVector.h"
27 #include "llvm/ADT/Statistic.h"
41 #include "llvm/IR/BasicBlock.h"
42 #include "llvm/IR/DebugLoc.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/IR/GlobalValue.h"
45 #include "llvm/IR/InlineAsm.h"
46 #include "llvm/IR/InstrTypes.h"
47 #include "llvm/IR/Module.h"
48 #include "llvm/Support/Casting.h"
49 #include "llvm/Support/CodeGen.h"
51 #include "llvm/Support/Compiler.h"
52 #include "llvm/Support/Debug.h"
54 #include "llvm/Support/KnownBits.h"
58 #include <algorithm>
59 #include <cassert>
60 #include <cstdint>
61 #include <iterator>
62 #include <limits>
63 #include <memory>
64 #include <new>
65 #include <tuple>
66 #include <utility>
67 
68 using namespace llvm;
69 
70 #define DEBUG_TYPE "ppc-codegen"
71 
72 STATISTIC(NumSextSetcc,
73  "Number of (sext(setcc)) nodes expanded into GPR sequence.");
74 STATISTIC(NumZextSetcc,
75  "Number of (zext(setcc)) nodes expanded into GPR sequence.");
76 STATISTIC(SignExtensionsAdded,
77  "Number of sign extensions for compare inputs added.");
78 STATISTIC(ZeroExtensionsAdded,
79  "Number of zero extensions for compare inputs added.");
80 STATISTIC(NumLogicOpsOnComparison,
81  "Number of logical ops on i1 values calculated in GPR.");
82 STATISTIC(OmittedForNonExtendUses,
83  "Number of compares not eliminated as they have non-extending uses.");
84 
85 // FIXME: Remove this once the bug has been fixed!
86 cl::opt<bool> ANDIGlueBug("expose-ppc-andi-glue-bug",
87 cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden);
88 
89 static cl::opt<bool>
90  UseBitPermRewriter("ppc-use-bit-perm-rewriter", cl::init(true),
91  cl::desc("use aggressive ppc isel for bit permutations"),
92  cl::Hidden);
94  "ppc-bit-perm-rewriter-stress-rotates",
95  cl::desc("stress rotate selection in aggressive ppc isel for "
96  "bit permutations"),
97  cl::Hidden);
98 
100  "ppc-use-branch-hint", cl::init(true),
101  cl::desc("Enable static hinting of branches on ppc"),
102  cl::Hidden);
103 
105  "ppc-tls-opt", cl::init(true),
106  cl::desc("Enable tls optimization peephole"),
107  cl::Hidden);
108 
112 
114  "ppc-gpr-icmps", cl::Hidden, cl::init(ICGPR_All),
115  cl::desc("Specify the types of comparisons to emit GPR-only code for."),
116  cl::values(clEnumValN(ICGPR_None, "none", "Do not modify integer comparisons."),
117  clEnumValN(ICGPR_All, "all", "All possible int comparisons in GPRs."),
118  clEnumValN(ICGPR_I32, "i32", "Only i32 comparisons in GPRs."),
119  clEnumValN(ICGPR_I64, "i64", "Only i64 comparisons in GPRs."),
120  clEnumValN(ICGPR_NonExtIn, "nonextin",
121  "Only comparisons where inputs don't need [sz]ext."),
122  clEnumValN(ICGPR_Zext, "zext", "Only comparisons with zext result."),
123  clEnumValN(ICGPR_ZextI32, "zexti32",
124  "Only i32 comparisons with zext result."),
125  clEnumValN(ICGPR_ZextI64, "zexti64",
126  "Only i64 comparisons with zext result."),
127  clEnumValN(ICGPR_Sext, "sext", "Only comparisons with sext result."),
128  clEnumValN(ICGPR_SextI32, "sexti32",
129  "Only i32 comparisons with sext result."),
130  clEnumValN(ICGPR_SextI64, "sexti64",
131  "Only i64 comparisons with sext result.")));
132 namespace {
133 
134  //===--------------------------------------------------------------------===//
135  /// PPCDAGToDAGISel - PPC specific code to select PPC machine
136  /// instructions for SelectionDAG operations.
137  ///
138  class PPCDAGToDAGISel : public SelectionDAGISel {
139  const PPCTargetMachine &TM;
140  const PPCSubtarget *PPCSubTarget;
141  const PPCTargetLowering *PPCLowering;
142  unsigned GlobalBaseReg;
143 
144  public:
145  explicit PPCDAGToDAGISel(PPCTargetMachine &tm, CodeGenOpt::Level OptLevel)
146  : SelectionDAGISel(tm, OptLevel), TM(tm) {}
147 
148  bool runOnMachineFunction(MachineFunction &MF) override {
149  // Make sure we re-emit a set of the global base reg if necessary
150  GlobalBaseReg = 0;
151  PPCSubTarget = &MF.getSubtarget<PPCSubtarget>();
152  PPCLowering = PPCSubTarget->getTargetLowering();
154 
155  if (!PPCSubTarget->isSVR4ABI())
156  InsertVRSaveCode(MF);
157 
158  return true;
159  }
160 
161  void PreprocessISelDAG() override;
162  void PostprocessISelDAG() override;
163 
164  /// getI16Imm - Return a target constant with the specified value, of type
165  /// i16.
166  inline SDValue getI16Imm(unsigned Imm, const SDLoc &dl) {
167  return CurDAG->getTargetConstant(Imm, dl, MVT::i16);
168  }
169 
170  /// getI32Imm - Return a target constant with the specified value, of type
171  /// i32.
172  inline SDValue getI32Imm(unsigned Imm, const SDLoc &dl) {
173  return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
174  }
175 
176  /// getI64Imm - Return a target constant with the specified value, of type
177  /// i64.
178  inline SDValue getI64Imm(uint64_t Imm, const SDLoc &dl) {
179  return CurDAG->getTargetConstant(Imm, dl, MVT::i64);
180  }
181 
182  /// getSmallIPtrImm - Return a target constant of pointer type.
183  inline SDValue getSmallIPtrImm(unsigned Imm, const SDLoc &dl) {
184  return CurDAG->getTargetConstant(
185  Imm, dl, PPCLowering->getPointerTy(CurDAG->getDataLayout()));
186  }
187 
188  /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
189  /// rotate and mask opcode and mask operation.
190  static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask,
191  unsigned &SH, unsigned &MB, unsigned &ME);
192 
193  /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
194  /// base register. Return the virtual register that holds this value.
195  SDNode *getGlobalBaseReg();
196 
197  void selectFrameIndex(SDNode *SN, SDNode *N, unsigned Offset = 0);
198 
199  // Select - Convert the specified operand from a target-independent to a
200  // target-specific node if it hasn't already been changed.
201  void Select(SDNode *N) override;
202 
203  bool tryBitfieldInsert(SDNode *N);
204  bool tryBitPermutation(SDNode *N);
205  bool tryIntCompareInGPR(SDNode *N);
206 
207  // tryTLSXFormLoad - Convert an ISD::LOAD fed by a PPCISD::ADD_TLS into
208  // an X-Form load instruction with the offset being a relocation coming from
209  // the PPCISD::ADD_TLS.
210  bool tryTLSXFormLoad(LoadSDNode *N);
211  // tryTLSXFormStore - Convert an ISD::STORE fed by a PPCISD::ADD_TLS into
212  // an X-Form store instruction with the offset being a relocation coming from
213  // the PPCISD::ADD_TLS.
214  bool tryTLSXFormStore(StoreSDNode *N);
215  /// SelectCC - Select a comparison of the specified values with the
216  /// specified condition code, returning the CR# of the expression.
217  SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
218  const SDLoc &dl);
219 
220  /// SelectAddrImm - Returns true if the address N can be represented by
221  /// a base register plus a signed 16-bit displacement [r+imm].
222  bool SelectAddrImm(SDValue N, SDValue &Disp,
223  SDValue &Base) {
224  return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, 0);
225  }
226 
227  /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
228  /// immediate field. Note that the operand at this point is already the
229  /// result of a prior SelectAddressRegImm call.
230  bool SelectAddrImmOffs(SDValue N, SDValue &Out) const {
231  if (N.getOpcode() == ISD::TargetConstant ||
233  Out = N;
234  return true;
235  }
236 
237  return false;
238  }
239 
240  /// SelectAddrIdx - Given the specified addressed, check to see if it can be
241  /// represented as an indexed [r+r] operation. Returns false if it can
242  /// be represented by [r+imm], which are preferred.
243  bool SelectAddrIdx(SDValue N, SDValue &Base, SDValue &Index) {
244  return PPCLowering->SelectAddressRegReg(N, Base, Index, *CurDAG);
245  }
246 
247  /// SelectAddrIdxOnly - Given the specified addressed, force it to be
248  /// represented as an indexed [r+r] operation.
249  bool SelectAddrIdxOnly(SDValue N, SDValue &Base, SDValue &Index) {
250  return PPCLowering->SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
251  }
252 
253  /// SelectAddrImmX4 - Returns true if the address N can be represented by
254  /// a base register plus a signed 16-bit displacement that is a multiple of 4.
255  /// Suitable for use by STD and friends.
256  bool SelectAddrImmX4(SDValue N, SDValue &Disp, SDValue &Base) {
257  return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, 4);
258  }
259 
260  bool SelectAddrImmX16(SDValue N, SDValue &Disp, SDValue &Base) {
261  return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, 16);
262  }
263 
264  // Select an address into a single register.
265  bool SelectAddr(SDValue N, SDValue &Base) {
266  Base = N;
267  return true;
268  }
269 
270  /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
271  /// inline asm expressions. It is always correct to compute the value into
272  /// a register. The case of adding a (possibly relocatable) constant to a
273  /// register can be improved, but it is wrong to substitute Reg+Reg for
274  /// Reg in an asm, because the load or store opcode would have to change.
275  bool SelectInlineAsmMemoryOperand(const SDValue &Op,
276  unsigned ConstraintID,
277  std::vector<SDValue> &OutOps) override {
278  switch(ConstraintID) {
279  default:
280  errs() << "ConstraintID: " << ConstraintID << "\n";
281  llvm_unreachable("Unexpected asm memory constraint");
289  // We need to make sure that this one operand does not end up in r0
290  // (because we might end up lowering this as 0(%op)).
291  const TargetRegisterInfo *TRI = PPCSubTarget->getRegisterInfo();
292  const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF, /*Kind=*/1);
293  SDLoc dl(Op);
294  SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32);
295  SDValue NewOp =
296  SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
297  dl, Op.getValueType(),
298  Op, RC), 0);
299 
300  OutOps.push_back(NewOp);
301  return false;
302  }
303  return true;
304  }
305 
306  void InsertVRSaveCode(MachineFunction &MF);
307 
308  StringRef getPassName() const override {
309  return "PowerPC DAG->DAG Pattern Instruction Selection";
310  }
311 
312 // Include the pieces autogenerated from the target description.
313 #include "PPCGenDAGISel.inc"
314 
315 private:
316  bool trySETCC(SDNode *N);
317 
318  void PeepholePPC64();
319  void PeepholePPC64ZExt();
320  void PeepholeCROps();
321 
322  SDValue combineToCMPB(SDNode *N);
323  void foldBoolExts(SDValue &Res, SDNode *&N);
324 
325  bool AllUsersSelectZero(SDNode *N);
326  void SwapAllSelectUsers(SDNode *N);
327 
328  bool isOffsetMultipleOf(SDNode *N, unsigned Val) const;
329  void transferMemOperands(SDNode *N, SDNode *Result);
330  MachineSDNode *flipSignBit(const SDValue &N, SDNode **SignBit = nullptr);
331  };
332 
333 } // end anonymous namespace
334 
335 /// InsertVRSaveCode - Once the entire function has been instruction selected,
336 /// all virtual registers are created and all machine instructions are built,
337 /// check to see if we need to save/restore VRSAVE. If so, do it.
338 void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) {
339  // Check to see if this function uses vector registers, which means we have to
340  // save and restore the VRSAVE register and update it with the regs we use.
341  //
342  // In this case, there will be virtual registers of vector type created
343  // by the scheduler. Detect them now.
344  bool HasVectorVReg = false;
345  for (unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) {
347  if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) {
348  HasVectorVReg = true;
349  break;
350  }
351  }
352  if (!HasVectorVReg) return; // nothing to do.
353 
354  // If we have a vector register, we want to emit code into the entry and exit
355  // blocks to save and restore the VRSAVE register. We do this here (instead
356  // of marking all vector instructions as clobbering VRSAVE) for two reasons:
357  //
358  // 1. This (trivially) reduces the load on the register allocator, by not
359  // having to represent the live range of the VRSAVE register.
360  // 2. This (more significantly) allows us to create a temporary virtual
361  // register to hold the saved VRSAVE value, allowing this temporary to be
362  // register allocated, instead of forcing it to be spilled to the stack.
363 
364  // Create two vregs - one to hold the VRSAVE register that is live-in to the
365  // function and one for the value after having bits or'd into it.
366  unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
367  unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
368 
369  const TargetInstrInfo &TII = *PPCSubTarget->getInstrInfo();
370  MachineBasicBlock &EntryBB = *Fn.begin();
371  DebugLoc dl;
372  // Emit the following code into the entry block:
373  // InVRSAVE = MFVRSAVE
374  // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
375  // MTVRSAVE UpdatedVRSAVE
376  MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
377  BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
378  BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
379  UpdatedVRSAVE).addReg(InVRSAVE);
380  BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
381 
382  // Find all return blocks, outputting a restore in each epilog.
383  for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
384  if (BB->isReturnBlock()) {
385  IP = BB->end(); --IP;
386 
387  // Skip over all terminator instructions, which are part of the return
388  // sequence.
390  while (I2 != BB->begin() && (--I2)->isTerminator())
391  IP = I2;
392 
393  // Emit: MTVRSAVE InVRSave
394  BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
395  }
396  }
397 }
398 
399 /// getGlobalBaseReg - Output the instructions required to put the
400 /// base address to use for accessing globals into a register.
401 ///
402 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
403  if (!GlobalBaseReg) {
404  const TargetInstrInfo &TII = *PPCSubTarget->getInstrInfo();
405  // Insert the set of GlobalBaseReg into the first MBB of the function
406  MachineBasicBlock &FirstMBB = MF->front();
407  MachineBasicBlock::iterator MBBI = FirstMBB.begin();
408  const Module *M = MF->getFunction().getParent();
409  DebugLoc dl;
410 
411  if (PPCLowering->getPointerTy(CurDAG->getDataLayout()) == MVT::i32) {
412  if (PPCSubTarget->isTargetELF()) {
413  GlobalBaseReg = PPC::R30;
414  if (M->getPICLevel() == PICLevel::SmallPIC) {
415  BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MoveGOTtoLR));
416  BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
417  MF->getInfo<PPCFunctionInfo>()->setUsesPICBase(true);
418  } else {
419  BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
420  BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
421  unsigned TempReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
422  BuildMI(FirstMBB, MBBI, dl,
423  TII.get(PPC::UpdateGBR), GlobalBaseReg)
424  .addReg(TempReg, RegState::Define).addReg(GlobalBaseReg);
425  MF->getInfo<PPCFunctionInfo>()->setUsesPICBase(true);
426  }
427  } else {
428  GlobalBaseReg =
429  RegInfo->createVirtualRegister(&PPC::GPRC_and_GPRC_NOR0RegClass);
430  BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
431  BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
432  }
433  } else {
434  // We must ensure that this sequence is dominated by the prologue.
435  // FIXME: This is a bit of a big hammer since we don't get the benefits
436  // of shrink-wrapping whenever we emit this instruction. Considering
437  // this is used in any function where we emit a jump table, this may be
438  // a significant limitation. We should consider inserting this in the
439  // block where it is used and then commoning this sequence up if it
440  // appears in multiple places.
441  // Note: on ISA 3.0 cores, we can use lnia (addpcis) instead of
442  // MovePCtoLR8.
443  MF->getInfo<PPCFunctionInfo>()->setShrinkWrapDisabled(true);
444  GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RC_and_G8RC_NOX0RegClass);
445  BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8));
446  BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
447  }
448  }
449  return CurDAG->getRegister(GlobalBaseReg,
450  PPCLowering->getPointerTy(CurDAG->getDataLayout()))
451  .getNode();
452 }
453 
454 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
455 /// operand. If so Imm will receive the 32-bit value.
456 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
457  if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
458  Imm = cast<ConstantSDNode>(N)->getZExtValue();
459  return true;
460  }
461  return false;
462 }
463 
464 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant
465 /// operand. If so Imm will receive the 64-bit value.
466 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
467  if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
468  Imm = cast<ConstantSDNode>(N)->getZExtValue();
469  return true;
470  }
471  return false;
472 }
473 
474 // isInt32Immediate - This method tests to see if a constant operand.
475 // If so Imm will receive the 32 bit value.
476 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
477  return isInt32Immediate(N.getNode(), Imm);
478 }
479 
480 /// isInt64Immediate - This method tests to see if the value is a 64-bit
481 /// constant operand. If so Imm will receive the 64-bit value.
482 static bool isInt64Immediate(SDValue N, uint64_t &Imm) {
483  return isInt64Immediate(N.getNode(), Imm);
484 }
485 
486 static unsigned getBranchHint(unsigned PCC, FunctionLoweringInfo *FuncInfo,
487  const SDValue &DestMBB) {
488  assert(isa<BasicBlockSDNode>(DestMBB));
489 
490  if (!FuncInfo->BPI) return PPC::BR_NO_HINT;
491 
492  const BasicBlock *BB = FuncInfo->MBB->getBasicBlock();
493  const TerminatorInst *BBTerm = BB->getTerminator();
494 
495  if (BBTerm->getNumSuccessors() != 2) return PPC::BR_NO_HINT;
496 
497  const BasicBlock *TBB = BBTerm->getSuccessor(0);
498  const BasicBlock *FBB = BBTerm->getSuccessor(1);
499 
500  auto TProb = FuncInfo->BPI->getEdgeProbability(BB, TBB);
501  auto FProb = FuncInfo->BPI->getEdgeProbability(BB, FBB);
502 
503  // We only want to handle cases which are easy to predict at static time, e.g.
504  // C++ throw statement, that is very likely not taken, or calling never
505  // returned function, e.g. stdlib exit(). So we set Threshold to filter
506  // unwanted cases.
507  //
508  // Below is LLVM branch weight table, we only want to handle case 1, 2
509  //
510  // Case Taken:Nontaken Example
511  // 1. Unreachable 1048575:1 C++ throw, stdlib exit(),
512  // 2. Invoke-terminating 1:1048575
513  // 3. Coldblock 4:64 __builtin_expect
514  // 4. Loop Branch 124:4 For loop
515  // 5. PH/ZH/FPH 20:12
516  const uint32_t Threshold = 10000;
517 
518  if (std::max(TProb, FProb) / Threshold < std::min(TProb, FProb))
519  return PPC::BR_NO_HINT;
520 
521  LLVM_DEBUG(dbgs() << "Use branch hint for '" << FuncInfo->Fn->getName()
522  << "::" << BB->getName() << "'\n"
523  << " -> " << TBB->getName() << ": " << TProb << "\n"
524  << " -> " << FBB->getName() << ": " << FProb << "\n");
525 
526  const BasicBlockSDNode *BBDN = cast<BasicBlockSDNode>(DestMBB);
527 
528  // If Dest BasicBlock is False-BasicBlock (FBB), swap branch probabilities,
529  // because we want 'TProb' stands for 'branch probability' to Dest BasicBlock
530  if (BBDN->getBasicBlock()->getBasicBlock() != TBB)
531  std::swap(TProb, FProb);
532 
533  return (TProb > FProb) ? PPC::BR_TAKEN_HINT : PPC::BR_NONTAKEN_HINT;
534 }
535 
536 // isOpcWithIntImmediate - This method tests to see if the node is a specific
537 // opcode and that it has a immediate integer right operand.
538 // If so Imm will receive the 32 bit value.
539 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
540  return N->getOpcode() == Opc
541  && isInt32Immediate(N->getOperand(1).getNode(), Imm);
542 }
543 
544 void PPCDAGToDAGISel::selectFrameIndex(SDNode *SN, SDNode *N, unsigned Offset) {
545  SDLoc dl(SN);
546  int FI = cast<FrameIndexSDNode>(N)->getIndex();
547  SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
548  unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
549  if (SN->hasOneUse())
550  CurDAG->SelectNodeTo(SN, Opc, N->getValueType(0), TFI,
551  getSmallIPtrImm(Offset, dl));
552  else
553  ReplaceNode(SN, CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI,
554  getSmallIPtrImm(Offset, dl)));
555 }
556 
557 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
558  bool isShiftMask, unsigned &SH,
559  unsigned &MB, unsigned &ME) {
560  // Don't even go down this path for i64, since different logic will be
561  // necessary for rldicl/rldicr/rldimi.
562  if (N->getValueType(0) != MVT::i32)
563  return false;
564 
565  unsigned Shift = 32;
566  unsigned Indeterminant = ~0; // bit mask marking indeterminant results
567  unsigned Opcode = N->getOpcode();
568  if (N->getNumOperands() != 2 ||
569  !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
570  return false;
571 
572  if (Opcode == ISD::SHL) {
573  // apply shift left to mask if it comes first
574  if (isShiftMask) Mask = Mask << Shift;
575  // determine which bits are made indeterminant by shift
576  Indeterminant = ~(0xFFFFFFFFu << Shift);
577  } else if (Opcode == ISD::SRL) {
578  // apply shift right to mask if it comes first
579  if (isShiftMask) Mask = Mask >> Shift;
580  // determine which bits are made indeterminant by shift
581  Indeterminant = ~(0xFFFFFFFFu >> Shift);
582  // adjust for the left rotate
583  Shift = 32 - Shift;
584  } else if (Opcode == ISD::ROTL) {
585  Indeterminant = 0;
586  } else {
587  return false;
588  }
589 
590  // if the mask doesn't intersect any Indeterminant bits
591  if (Mask && !(Mask & Indeterminant)) {
592  SH = Shift & 31;
593  // make sure the mask is still a mask (wrap arounds may not be)
594  return isRunOfOnes(Mask, MB, ME);
595  }
596  return false;
597 }
598 
599 bool PPCDAGToDAGISel::tryTLSXFormStore(StoreSDNode *ST) {
600  SDValue Base = ST->getBasePtr();
601  if (Base.getOpcode() != PPCISD::ADD_TLS)
602  return false;
603  SDValue Offset = ST->getOffset();
604  if (!Offset.isUndef())
605  return false;
606 
607  SDLoc dl(ST);
608  EVT MemVT = ST->getMemoryVT();
609  EVT RegVT = ST->getValue().getValueType();
610 
611  unsigned Opcode;
612  switch (MemVT.getSimpleVT().SimpleTy) {
613  default:
614  return false;
615  case MVT::i8: {
616  Opcode = (RegVT == MVT::i32) ? PPC::STBXTLS_32 : PPC::STBXTLS;
617  break;
618  }
619  case MVT::i16: {
620  Opcode = (RegVT == MVT::i32) ? PPC::STHXTLS_32 : PPC::STHXTLS;
621  break;
622  }
623  case MVT::i32: {
624  Opcode = (RegVT == MVT::i32) ? PPC::STWXTLS_32 : PPC::STWXTLS;
625  break;
626  }
627  case MVT::i64: {
628  Opcode = PPC::STDXTLS;
629  break;
630  }
631  }
632  SDValue Chain = ST->getChain();
633  SDVTList VTs = ST->getVTList();
634  SDValue Ops[] = {ST->getValue(), Base.getOperand(0), Base.getOperand(1),
635  Chain};
636  SDNode *MN = CurDAG->getMachineNode(Opcode, dl, VTs, Ops);
637  transferMemOperands(ST, MN);
638  ReplaceNode(ST, MN);
639  return true;
640 }
641 
642 bool PPCDAGToDAGISel::tryTLSXFormLoad(LoadSDNode *LD) {
643  SDValue Base = LD->getBasePtr();
644  if (Base.getOpcode() != PPCISD::ADD_TLS)
645  return false;
646  SDValue Offset = LD->getOffset();
647  if (!Offset.isUndef())
648  return false;
649 
650  SDLoc dl(LD);
651  EVT MemVT = LD->getMemoryVT();
652  EVT RegVT = LD->getValueType(0);
653  unsigned Opcode;
654  switch (MemVT.getSimpleVT().SimpleTy) {
655  default:
656  return false;
657  case MVT::i8: {
658  Opcode = (RegVT == MVT::i32) ? PPC::LBZXTLS_32 : PPC::LBZXTLS;
659  break;
660  }
661  case MVT::i16: {
662  Opcode = (RegVT == MVT::i32) ? PPC::LHZXTLS_32 : PPC::LHZXTLS;
663  break;
664  }
665  case MVT::i32: {
666  Opcode = (RegVT == MVT::i32) ? PPC::LWZXTLS_32 : PPC::LWZXTLS;
667  break;
668  }
669  case MVT::i64: {
670  Opcode = PPC::LDXTLS;
671  break;
672  }
673  }
674  SDValue Chain = LD->getChain();
675  SDVTList VTs = LD->getVTList();
676  SDValue Ops[] = {Base.getOperand(0), Base.getOperand(1), Chain};
677  SDNode *MN = CurDAG->getMachineNode(Opcode, dl, VTs, Ops);
678  transferMemOperands(LD, MN);
679  ReplaceNode(LD, MN);
680  return true;
681 }
682 
683 /// Turn an or of two masked values into the rotate left word immediate then
684 /// mask insert (rlwimi) instruction.
685 bool PPCDAGToDAGISel::tryBitfieldInsert(SDNode *N) {
686  SDValue Op0 = N->getOperand(0);
687  SDValue Op1 = N->getOperand(1);
688  SDLoc dl(N);
689 
690  KnownBits LKnown, RKnown;
691  CurDAG->computeKnownBits(Op0, LKnown);
692  CurDAG->computeKnownBits(Op1, RKnown);
693 
694  unsigned TargetMask = LKnown.Zero.getZExtValue();
695  unsigned InsertMask = RKnown.Zero.getZExtValue();
696 
697  if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
698  unsigned Op0Opc = Op0.getOpcode();
699  unsigned Op1Opc = Op1.getOpcode();
700  unsigned Value, SH = 0;
701  TargetMask = ~TargetMask;
702  InsertMask = ~InsertMask;
703 
704  // If the LHS has a foldable shift and the RHS does not, then swap it to the
705  // RHS so that we can fold the shift into the insert.
706  if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
707  if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
708  Op0.getOperand(0).getOpcode() == ISD::SRL) {
709  if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
710  Op1.getOperand(0).getOpcode() != ISD::SRL) {
711  std::swap(Op0, Op1);
712  std::swap(Op0Opc, Op1Opc);
713  std::swap(TargetMask, InsertMask);
714  }
715  }
716  } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
717  if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
718  Op1.getOperand(0).getOpcode() != ISD::SRL) {
719  std::swap(Op0, Op1);
720  std::swap(Op0Opc, Op1Opc);
721  std::swap(TargetMask, InsertMask);
722  }
723  }
724 
725  unsigned MB, ME;
726  if (isRunOfOnes(InsertMask, MB, ME)) {
727  if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
728  isInt32Immediate(Op1.getOperand(1), Value)) {
729  Op1 = Op1.getOperand(0);
730  SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
731  }
732  if (Op1Opc == ISD::AND) {
733  // The AND mask might not be a constant, and we need to make sure that
734  // if we're going to fold the masking with the insert, all bits not
735  // know to be zero in the mask are known to be one.
736  KnownBits MKnown;
737  CurDAG->computeKnownBits(Op1.getOperand(1), MKnown);
738  bool CanFoldMask = InsertMask == MKnown.One.getZExtValue();
739 
740  unsigned SHOpc = Op1.getOperand(0).getOpcode();
741  if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && CanFoldMask &&
742  isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
743  // Note that Value must be in range here (less than 32) because
744  // otherwise there would not be any bits set in InsertMask.
745  Op1 = Op1.getOperand(0).getOperand(0);
746  SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
747  }
748  }
749 
750  SH &= 31;
751  SDValue Ops[] = { Op0, Op1, getI32Imm(SH, dl), getI32Imm(MB, dl),
752  getI32Imm(ME, dl) };
753  ReplaceNode(N, CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops));
754  return true;
755  }
756  }
757  return false;
758 }
759 
760 // Predict the number of instructions that would be generated by calling
761 // selectI64Imm(N).
762 static unsigned selectI64ImmInstrCountDirect(int64_t Imm) {
763  // Assume no remaining bits.
764  unsigned Remainder = 0;
765  // Assume no shift required.
766  unsigned Shift = 0;
767 
768  // If it can't be represented as a 32 bit value.
769  if (!isInt<32>(Imm)) {
770  Shift = countTrailingZeros<uint64_t>(Imm);
771  int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
772 
773  // If the shifted value fits 32 bits.
774  if (isInt<32>(ImmSh)) {
775  // Go with the shifted value.
776  Imm = ImmSh;
777  } else {
778  // Still stuck with a 64 bit value.
779  Remainder = Imm;
780  Shift = 32;
781  Imm >>= 32;
782  }
783  }
784 
785  // Intermediate operand.
786  unsigned Result = 0;
787 
788  // Handle first 32 bits.
789  unsigned Lo = Imm & 0xFFFF;
790 
791  // Simple value.
792  if (isInt<16>(Imm)) {
793  // Just the Lo bits.
794  ++Result;
795  } else if (Lo) {
796  // Handle the Hi bits and Lo bits.
797  Result += 2;
798  } else {
799  // Just the Hi bits.
800  ++Result;
801  }
802 
803  // If no shift, we're done.
804  if (!Shift) return Result;
805 
806  // If Hi word == Lo word,
807  // we can use rldimi to insert the Lo word into Hi word.
808  if ((unsigned)(Imm & 0xFFFFFFFF) == Remainder) {
809  ++Result;
810  return Result;
811  }
812 
813  // Shift for next step if the upper 32-bits were not zero.
814  if (Imm)
815  ++Result;
816 
817  // Add in the last bits as required.
818  if ((Remainder >> 16) & 0xFFFF)
819  ++Result;
820  if (Remainder & 0xFFFF)
821  ++Result;
822 
823  return Result;
824 }
825 
826 static uint64_t Rot64(uint64_t Imm, unsigned R) {
827  return (Imm << R) | (Imm >> (64 - R));
828 }
829 
830 static unsigned selectI64ImmInstrCount(int64_t Imm) {
831  unsigned Count = selectI64ImmInstrCountDirect(Imm);
832 
833  // If the instruction count is 1 or 2, we do not need further analysis
834  // since rotate + load constant requires at least 2 instructions.
835  if (Count <= 2)
836  return Count;
837 
838  for (unsigned r = 1; r < 63; ++r) {
839  uint64_t RImm = Rot64(Imm, r);
840  unsigned RCount = selectI64ImmInstrCountDirect(RImm) + 1;
841  Count = std::min(Count, RCount);
842 
843  // See comments in selectI64Imm for an explanation of the logic below.
844  unsigned LS = findLastSet(RImm);
845  if (LS != r-1)
846  continue;
847 
848  uint64_t OnesMask = -(int64_t) (UINT64_C(1) << (LS+1));
849  uint64_t RImmWithOnes = RImm | OnesMask;
850 
851  RCount = selectI64ImmInstrCountDirect(RImmWithOnes) + 1;
852  Count = std::min(Count, RCount);
853  }
854 
855  return Count;
856 }
857 
858 // Select a 64-bit constant. For cost-modeling purposes, selectI64ImmInstrCount
859 // (above) needs to be kept in sync with this function.
860 static SDNode *selectI64ImmDirect(SelectionDAG *CurDAG, const SDLoc &dl,
861  int64_t Imm) {
862  // Assume no remaining bits.
863  unsigned Remainder = 0;
864  // Assume no shift required.
865  unsigned Shift = 0;
866 
867  // If it can't be represented as a 32 bit value.
868  if (!isInt<32>(Imm)) {
869  Shift = countTrailingZeros<uint64_t>(Imm);
870  int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
871 
872  // If the shifted value fits 32 bits.
873  if (isInt<32>(ImmSh)) {
874  // Go with the shifted value.
875  Imm = ImmSh;
876  } else {
877  // Still stuck with a 64 bit value.
878  Remainder = Imm;
879  Shift = 32;
880  Imm >>= 32;
881  }
882  }
883 
884  // Intermediate operand.
885  SDNode *Result;
886 
887  // Handle first 32 bits.
888  unsigned Lo = Imm & 0xFFFF;
889  unsigned Hi = (Imm >> 16) & 0xFFFF;
890 
891  auto getI32Imm = [CurDAG, dl](unsigned Imm) {
892  return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
893  };
894 
895  // Simple value.
896  if (isInt<16>(Imm)) {
897  uint64_t SextImm = SignExtend64(Lo, 16);
898  SDValue SDImm = CurDAG->getTargetConstant(SextImm, dl, MVT::i64);
899  // Just the Lo bits.
900  Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, SDImm);
901  } else if (Lo) {
902  // Handle the Hi bits.
903  unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
904  Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi));
905  // And Lo bits.
906  Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
907  SDValue(Result, 0), getI32Imm(Lo));
908  } else {
909  // Just the Hi bits.
910  Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
911  }
912 
913  // If no shift, we're done.
914  if (!Shift) return Result;
915 
916  // If Hi word == Lo word,
917  // we can use rldimi to insert the Lo word into Hi word.
918  if ((unsigned)(Imm & 0xFFFFFFFF) == Remainder) {
919  SDValue Ops[] =
920  { SDValue(Result, 0), SDValue(Result, 0), getI32Imm(Shift), getI32Imm(0)};
921  return CurDAG->getMachineNode(PPC::RLDIMI, dl, MVT::i64, Ops);
922  }
923 
924  // Shift for next step if the upper 32-bits were not zero.
925  if (Imm) {
926  Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64,
927  SDValue(Result, 0),
928  getI32Imm(Shift),
929  getI32Imm(63 - Shift));
930  }
931 
932  // Add in the last bits as required.
933  if ((Hi = (Remainder >> 16) & 0xFFFF)) {
934  Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64,
935  SDValue(Result, 0), getI32Imm(Hi));
936  }
937  if ((Lo = Remainder & 0xFFFF)) {
938  Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
939  SDValue(Result, 0), getI32Imm(Lo));
940  }
941 
942  return Result;
943 }
944 
945 static SDNode *selectI64Imm(SelectionDAG *CurDAG, const SDLoc &dl,
946  int64_t Imm) {
947  unsigned Count = selectI64ImmInstrCountDirect(Imm);
948 
949  // If the instruction count is 1 or 2, we do not need further analysis
950  // since rotate + load constant requires at least 2 instructions.
951  if (Count <= 2)
952  return selectI64ImmDirect(CurDAG, dl, Imm);
953 
954  unsigned RMin = 0;
955 
956  int64_t MatImm;
957  unsigned MaskEnd;
958 
959  for (unsigned r = 1; r < 63; ++r) {
960  uint64_t RImm = Rot64(Imm, r);
961  unsigned RCount = selectI64ImmInstrCountDirect(RImm) + 1;
962  if (RCount < Count) {
963  Count = RCount;
964  RMin = r;
965  MatImm = RImm;
966  MaskEnd = 63;
967  }
968 
969  // If the immediate to generate has many trailing zeros, it might be
970  // worthwhile to generate a rotated value with too many leading ones
971  // (because that's free with li/lis's sign-extension semantics), and then
972  // mask them off after rotation.
973 
974  unsigned LS = findLastSet(RImm);
975  // We're adding (63-LS) higher-order ones, and we expect to mask them off
976  // after performing the inverse rotation by (64-r). So we need that:
977  // 63-LS == 64-r => LS == r-1
978  if (LS != r-1)
979  continue;
980 
981  uint64_t OnesMask = -(int64_t) (UINT64_C(1) << (LS+1));
982  uint64_t RImmWithOnes = RImm | OnesMask;
983 
984  RCount = selectI64ImmInstrCountDirect(RImmWithOnes) + 1;
985  if (RCount < Count) {
986  Count = RCount;
987  RMin = r;
988  MatImm = RImmWithOnes;
989  MaskEnd = LS;
990  }
991  }
992 
993  if (!RMin)
994  return selectI64ImmDirect(CurDAG, dl, Imm);
995 
996  auto getI32Imm = [CurDAG, dl](unsigned Imm) {
997  return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
998  };
999 
1000  SDValue Val = SDValue(selectI64ImmDirect(CurDAG, dl, MatImm), 0);
1001  return CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, Val,
1002  getI32Imm(64 - RMin), getI32Imm(MaskEnd));
1003 }
1004 
1005 static unsigned allUsesTruncate(SelectionDAG *CurDAG, SDNode *N) {
1006  unsigned MaxTruncation = 0;
1007  // Cannot use range-based for loop here as we need the actual use (i.e. we
1008  // need the operand number corresponding to the use). A range-based for
1009  // will unbox the use and provide an SDNode*.
1010  for (SDNode::use_iterator Use = N->use_begin(), UseEnd = N->use_end();
1011  Use != UseEnd; ++Use) {
1012  unsigned Opc =
1013  Use->isMachineOpcode() ? Use->getMachineOpcode() : Use->getOpcode();
1014  switch (Opc) {
1015  default: return 0;
1016  case ISD::TRUNCATE:
1017  if (Use->isMachineOpcode())
1018  return 0;
1019  MaxTruncation =
1020  std::max(MaxTruncation, Use->getValueType(0).getSizeInBits());
1021  continue;
1022  case ISD::STORE: {
1023  if (Use->isMachineOpcode())
1024  return 0;
1025  StoreSDNode *STN = cast<StoreSDNode>(*Use);
1026  unsigned MemVTSize = STN->getMemoryVT().getSizeInBits();
1027  if (MemVTSize == 64 || Use.getOperandNo() != 0)
1028  return 0;
1029  MaxTruncation = std::max(MaxTruncation, MemVTSize);
1030  continue;
1031  }
1032  case PPC::STW8:
1033  case PPC::STWX8:
1034  case PPC::STWU8:
1035  case PPC::STWUX8:
1036  if (Use.getOperandNo() != 0)
1037  return 0;
1038  MaxTruncation = std::max(MaxTruncation, 32u);
1039  continue;
1040  case PPC::STH8:
1041  case PPC::STHX8:
1042  case PPC::STHU8:
1043  case PPC::STHUX8:
1044  if (Use.getOperandNo() != 0)
1045  return 0;
1046  MaxTruncation = std::max(MaxTruncation, 16u);
1047  continue;
1048  case PPC::STB8:
1049  case PPC::STBX8:
1050  case PPC::STBU8:
1051  case PPC::STBUX8:
1052  if (Use.getOperandNo() != 0)
1053  return 0;
1054  MaxTruncation = std::max(MaxTruncation, 8u);
1055  continue;
1056  }
1057  }
1058  return MaxTruncation;
1059 }
1060 
1061 // Select a 64-bit constant.
1062 static SDNode *selectI64Imm(SelectionDAG *CurDAG, SDNode *N) {
1063  SDLoc dl(N);
1064 
1065  // Get 64 bit value.
1066  int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
1067  if (unsigned MinSize = allUsesTruncate(CurDAG, N)) {
1068  uint64_t SextImm = SignExtend64(Imm, MinSize);
1069  SDValue SDImm = CurDAG->getTargetConstant(SextImm, dl, MVT::i64);
1070  if (isInt<16>(SextImm))
1071  return CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, SDImm);
1072  }
1073  return selectI64Imm(CurDAG, dl, Imm);
1074 }
1075 
1076 namespace {
1077 
1078 class BitPermutationSelector {
1079  struct ValueBit {
1080  SDValue V;
1081 
1082  // The bit number in the value, using a convention where bit 0 is the
1083  // lowest-order bit.
1084  unsigned Idx;
1085 
1086  enum Kind {
1087  ConstZero,
1088  Variable
1089  } K;
1090 
1091  ValueBit(SDValue V, unsigned I, Kind K = Variable)
1092  : V(V), Idx(I), K(K) {}
1093  ValueBit(Kind K = Variable)
1094  : V(SDValue(nullptr, 0)), Idx(UINT32_MAX), K(K) {}
1095 
1096  bool isZero() const {
1097  return K == ConstZero;
1098  }
1099 
1100  bool hasValue() const {
1101  return K == Variable;
1102  }
1103 
1104  SDValue getValue() const {
1105  assert(hasValue() && "Cannot get the value of a constant bit");
1106  return V;
1107  }
1108 
1109  unsigned getValueBitIndex() const {
1110  assert(hasValue() && "Cannot get the value bit index of a constant bit");
1111  return Idx;
1112  }
1113  };
1114 
1115  // A bit group has the same underlying value and the same rotate factor.
1116  struct BitGroup {
1117  SDValue V;
1118  unsigned RLAmt;
1119  unsigned StartIdx, EndIdx;
1120 
1121  // This rotation amount assumes that the lower 32 bits of the quantity are
1122  // replicated in the high 32 bits by the rotation operator (which is done
1123  // by rlwinm and friends in 64-bit mode).
1124  bool Repl32;
1125  // Did converting to Repl32 == true change the rotation factor? If it did,
1126  // it decreased it by 32.
1127  bool Repl32CR;
1128  // Was this group coalesced after setting Repl32 to true?
1129  bool Repl32Coalesced;
1130 
1131  BitGroup(SDValue V, unsigned R, unsigned S, unsigned E)
1132  : V(V), RLAmt(R), StartIdx(S), EndIdx(E), Repl32(false), Repl32CR(false),
1133  Repl32Coalesced(false) {
1134  LLVM_DEBUG(dbgs() << "\tbit group for " << V.getNode() << " RLAmt = " << R
1135  << " [" << S << ", " << E << "]\n");
1136  }
1137  };
1138 
1139  // Information on each (Value, RLAmt) pair (like the number of groups
1140  // associated with each) used to choose the lowering method.
1141  struct ValueRotInfo {
1142  SDValue V;
1143  unsigned RLAmt = std::numeric_limits<unsigned>::max();
1144  unsigned NumGroups = 0;
1145  unsigned FirstGroupStartIdx = std::numeric_limits<unsigned>::max();
1146  bool Repl32 = false;
1147 
1148  ValueRotInfo() = default;
1149 
1150  // For sorting (in reverse order) by NumGroups, and then by
1151  // FirstGroupStartIdx.
1152  bool operator < (const ValueRotInfo &Other) const {
1153  // We need to sort so that the non-Repl32 come first because, when we're
1154  // doing masking, the Repl32 bit groups might be subsumed into the 64-bit
1155  // masking operation.
1156  if (Repl32 < Other.Repl32)
1157  return true;
1158  else if (Repl32 > Other.Repl32)
1159  return false;
1160  else if (NumGroups > Other.NumGroups)
1161  return true;
1162  else if (NumGroups < Other.NumGroups)
1163  return false;
1164  else if (RLAmt == 0 && Other.RLAmt != 0)
1165  return true;
1166  else if (RLAmt != 0 && Other.RLAmt == 0)
1167  return false;
1168  else if (FirstGroupStartIdx < Other.FirstGroupStartIdx)
1169  return true;
1170  return false;
1171  }
1172  };
1173 
1174  using ValueBitsMemoizedValue = std::pair<bool, SmallVector<ValueBit, 64>>;
1175  using ValueBitsMemoizer =
1177  ValueBitsMemoizer Memoizer;
1178 
1179  // Return a pair of bool and a SmallVector pointer to a memoization entry.
1180  // The bool is true if something interesting was deduced, otherwise if we're
1181  // providing only a generic representation of V (or something else likewise
1182  // uninteresting for instruction selection) through the SmallVector.
1183  std::pair<bool, SmallVector<ValueBit, 64> *> getValueBits(SDValue V,
1184  unsigned NumBits) {
1185  auto &ValueEntry = Memoizer[V];
1186  if (ValueEntry)
1187  return std::make_pair(ValueEntry->first, &ValueEntry->second);
1188  ValueEntry.reset(new ValueBitsMemoizedValue());
1189  bool &Interesting = ValueEntry->first;
1190  SmallVector<ValueBit, 64> &Bits = ValueEntry->second;
1191  Bits.resize(NumBits);
1192 
1193  switch (V.getOpcode()) {
1194  default: break;
1195  case ISD::ROTL:
1196  if (isa<ConstantSDNode>(V.getOperand(1))) {
1197  unsigned RotAmt = V.getConstantOperandVal(1);
1198 
1199  const auto &LHSBits = *getValueBits(V.getOperand(0), NumBits).second;
1200 
1201  for (unsigned i = 0; i < NumBits; ++i)
1202  Bits[i] = LHSBits[i < RotAmt ? i + (NumBits - RotAmt) : i - RotAmt];
1203 
1204  return std::make_pair(Interesting = true, &Bits);
1205  }
1206  break;
1207  case ISD::SHL:
1208  if (isa<ConstantSDNode>(V.getOperand(1))) {
1209  unsigned ShiftAmt = V.getConstantOperandVal(1);
1210 
1211  const auto &LHSBits = *getValueBits(V.getOperand(0), NumBits).second;
1212 
1213  for (unsigned i = ShiftAmt; i < NumBits; ++i)
1214  Bits[i] = LHSBits[i - ShiftAmt];
1215 
1216  for (unsigned i = 0; i < ShiftAmt; ++i)
1217  Bits[i] = ValueBit(ValueBit::ConstZero);
1218 
1219  return std::make_pair(Interesting = true, &Bits);
1220  }
1221  break;
1222  case ISD::SRL:
1223  if (isa<ConstantSDNode>(V.getOperand(1))) {
1224  unsigned ShiftAmt = V.getConstantOperandVal(1);
1225 
1226  const auto &LHSBits = *getValueBits(V.getOperand(0), NumBits).second;
1227 
1228  for (unsigned i = 0; i < NumBits - ShiftAmt; ++i)
1229  Bits[i] = LHSBits[i + ShiftAmt];
1230 
1231  for (unsigned i = NumBits - ShiftAmt; i < NumBits; ++i)
1232  Bits[i] = ValueBit(ValueBit::ConstZero);
1233 
1234  return std::make_pair(Interesting = true, &Bits);
1235  }
1236  break;
1237  case ISD::AND:
1238  if (isa<ConstantSDNode>(V.getOperand(1))) {
1239  uint64_t Mask = V.getConstantOperandVal(1);
1240 
1241  const SmallVector<ValueBit, 64> *LHSBits;
1242  // Mark this as interesting, only if the LHS was also interesting. This
1243  // prevents the overall procedure from matching a single immediate 'and'
1244  // (which is non-optimal because such an and might be folded with other
1245  // things if we don't select it here).
1246  std::tie(Interesting, LHSBits) = getValueBits(V.getOperand(0), NumBits);
1247 
1248  for (unsigned i = 0; i < NumBits; ++i)
1249  if (((Mask >> i) & 1) == 1)
1250  Bits[i] = (*LHSBits)[i];
1251  else
1252  Bits[i] = ValueBit(ValueBit::ConstZero);
1253 
1254  return std::make_pair(Interesting, &Bits);
1255  }
1256  break;
1257  case ISD::OR: {
1258  const auto &LHSBits = *getValueBits(V.getOperand(0), NumBits).second;
1259  const auto &RHSBits = *getValueBits(V.getOperand(1), NumBits).second;
1260 
1261  bool AllDisjoint = true;
1262  for (unsigned i = 0; i < NumBits; ++i)
1263  if (LHSBits[i].isZero())
1264  Bits[i] = RHSBits[i];
1265  else if (RHSBits[i].isZero())
1266  Bits[i] = LHSBits[i];
1267  else {
1268  AllDisjoint = false;
1269  break;
1270  }
1271 
1272  if (!AllDisjoint)
1273  break;
1274 
1275  return std::make_pair(Interesting = true, &Bits);
1276  }
1277  case ISD::ZERO_EXTEND: {
1278  // We support only the case with zero extension from i32 to i64 so far.
1279  if (V.getValueType() != MVT::i64 ||
1280  V.getOperand(0).getValueType() != MVT::i32)
1281  break;
1282 
1283  const SmallVector<ValueBit, 64> *LHSBits;
1284  const unsigned NumOperandBits = 32;
1285  std::tie(Interesting, LHSBits) = getValueBits(V.getOperand(0),
1286  NumOperandBits);
1287 
1288  for (unsigned i = 0; i < NumOperandBits; ++i)
1289  Bits[i] = (*LHSBits)[i];
1290 
1291  for (unsigned i = NumOperandBits; i < NumBits; ++i)
1292  Bits[i] = ValueBit(ValueBit::ConstZero);
1293 
1294  return std::make_pair(Interesting, &Bits);
1295  }
1296  }
1297 
1298  for (unsigned i = 0; i < NumBits; ++i)
1299  Bits[i] = ValueBit(V, i);
1300 
1301  return std::make_pair(Interesting = false, &Bits);
1302  }
1303 
1304  // For each value (except the constant ones), compute the left-rotate amount
1305  // to get it from its original to final position.
1306  void computeRotationAmounts() {
1307  HasZeros = false;
1308  RLAmt.resize(Bits.size());
1309  for (unsigned i = 0; i < Bits.size(); ++i)
1310  if (Bits[i].hasValue()) {
1311  unsigned VBI = Bits[i].getValueBitIndex();
1312  if (i >= VBI)
1313  RLAmt[i] = i - VBI;
1314  else
1315  RLAmt[i] = Bits.size() - (VBI - i);
1316  } else if (Bits[i].isZero()) {
1317  HasZeros = true;
1318  RLAmt[i] = UINT32_MAX;
1319  } else {
1320  llvm_unreachable("Unknown value bit type");
1321  }
1322  }
1323 
1324  // Collect groups of consecutive bits with the same underlying value and
1325  // rotation factor. If we're doing late masking, we ignore zeros, otherwise
1326  // they break up groups.
1327  void collectBitGroups(bool LateMask) {
1328  BitGroups.clear();
1329 
1330  unsigned LastRLAmt = RLAmt[0];
1331  SDValue LastValue = Bits[0].hasValue() ? Bits[0].getValue() : SDValue();
1332  unsigned LastGroupStartIdx = 0;
1333  for (unsigned i = 1; i < Bits.size(); ++i) {
1334  unsigned ThisRLAmt = RLAmt[i];
1335  SDValue ThisValue = Bits[i].hasValue() ? Bits[i].getValue() : SDValue();
1336  if (LateMask && !ThisValue) {
1337  ThisValue = LastValue;
1338  ThisRLAmt = LastRLAmt;
1339  // If we're doing late masking, then the first bit group always starts
1340  // at zero (even if the first bits were zero).
1341  if (BitGroups.empty())
1342  LastGroupStartIdx = 0;
1343  }
1344 
1345  // If this bit has the same underlying value and the same rotate factor as
1346  // the last one, then they're part of the same group.
1347  if (ThisRLAmt == LastRLAmt && ThisValue == LastValue)
1348  continue;
1349 
1350  if (LastValue.getNode())
1351  BitGroups.push_back(BitGroup(LastValue, LastRLAmt, LastGroupStartIdx,
1352  i-1));
1353  LastRLAmt = ThisRLAmt;
1354  LastValue = ThisValue;
1355  LastGroupStartIdx = i;
1356  }
1357  if (LastValue.getNode())
1358  BitGroups.push_back(BitGroup(LastValue, LastRLAmt, LastGroupStartIdx,
1359  Bits.size()-1));
1360 
1361  if (BitGroups.empty())
1362  return;
1363 
1364  // We might be able to combine the first and last groups.
1365  if (BitGroups.size() > 1) {
1366  // If the first and last groups are the same, then remove the first group
1367  // in favor of the last group, making the ending index of the last group
1368  // equal to the ending index of the to-be-removed first group.
1369  if (BitGroups[0].StartIdx == 0 &&
1370  BitGroups[BitGroups.size()-1].EndIdx == Bits.size()-1 &&
1371  BitGroups[0].V == BitGroups[BitGroups.size()-1].V &&
1372  BitGroups[0].RLAmt == BitGroups[BitGroups.size()-1].RLAmt) {
1373  LLVM_DEBUG(dbgs() << "\tcombining final bit group with initial one\n");
1374  BitGroups[BitGroups.size()-1].EndIdx = BitGroups[0].EndIdx;
1375  BitGroups.erase(BitGroups.begin());
1376  }
1377  }
1378  }
1379 
1380  // Take all (SDValue, RLAmt) pairs and sort them by the number of groups
1381  // associated with each. If the number of groups are same, we prefer a group
1382  // which does not require rotate, i.e. RLAmt is 0, to avoid the first rotate
1383  // instruction. If there is a degeneracy, pick the one that occurs
1384  // first (in the final value).
1385  void collectValueRotInfo() {
1386  ValueRots.clear();
1387 
1388  for (auto &BG : BitGroups) {
1389  unsigned RLAmtKey = BG.RLAmt + (BG.Repl32 ? 64 : 0);
1390  ValueRotInfo &VRI = ValueRots[std::make_pair(BG.V, RLAmtKey)];
1391  VRI.V = BG.V;
1392  VRI.RLAmt = BG.RLAmt;
1393  VRI.Repl32 = BG.Repl32;
1394  VRI.NumGroups += 1;
1395  VRI.FirstGroupStartIdx = std::min(VRI.FirstGroupStartIdx, BG.StartIdx);
1396  }
1397 
1398  // Now that we've collected the various ValueRotInfo instances, we need to
1399  // sort them.
1400  ValueRotsVec.clear();
1401  for (auto &I : ValueRots) {
1402  ValueRotsVec.push_back(I.second);
1403  }
1404  llvm::sort(ValueRotsVec.begin(), ValueRotsVec.end());
1405  }
1406 
1407  // In 64-bit mode, rlwinm and friends have a rotation operator that
1408  // replicates the low-order 32 bits into the high-order 32-bits. The mask
1409  // indices of these instructions can only be in the lower 32 bits, so they
1410  // can only represent some 64-bit bit groups. However, when they can be used,
1411  // the 32-bit replication can be used to represent, as a single bit group,
1412  // otherwise separate bit groups. We'll convert to replicated-32-bit bit
1413  // groups when possible. Returns true if any of the bit groups were
1414  // converted.
1415  void assignRepl32BitGroups() {
1416  // If we have bits like this:
1417  //
1418  // Indices: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1419  // V bits: ... 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24
1420  // Groups: | RLAmt = 8 | RLAmt = 40 |
1421  //
1422  // But, making use of a 32-bit operation that replicates the low-order 32
1423  // bits into the high-order 32 bits, this can be one bit group with a RLAmt
1424  // of 8.
1425 
1426  auto IsAllLow32 = [this](BitGroup & BG) {
1427  if (BG.StartIdx <= BG.EndIdx) {
1428  for (unsigned i = BG.StartIdx; i <= BG.EndIdx; ++i) {
1429  if (!Bits[i].hasValue())
1430  continue;
1431  if (Bits[i].getValueBitIndex() >= 32)
1432  return false;
1433  }
1434  } else {
1435  for (unsigned i = BG.StartIdx; i < Bits.size(); ++i) {
1436  if (!Bits[i].hasValue())
1437  continue;
1438  if (Bits[i].getValueBitIndex() >= 32)
1439  return false;
1440  }
1441  for (unsigned i = 0; i <= BG.EndIdx; ++i) {
1442  if (!Bits[i].hasValue())
1443  continue;
1444  if (Bits[i].getValueBitIndex() >= 32)
1445  return false;
1446  }
1447  }
1448 
1449  return true;
1450  };
1451 
1452  for (auto &BG : BitGroups) {
1453  // If this bit group has RLAmt of 0 and will not be merged with
1454  // another bit group, we don't benefit from Repl32. We don't mark
1455  // such group to give more freedom for later instruction selection.
1456  if (BG.RLAmt == 0) {
1457  auto PotentiallyMerged = [this](BitGroup & BG) {
1458  for (auto &BG2 : BitGroups)
1459  if (&BG != &BG2 && BG.V == BG2.V &&
1460  (BG2.RLAmt == 0 || BG2.RLAmt == 32))
1461  return true;
1462  return false;
1463  };
1464  if (!PotentiallyMerged(BG))
1465  continue;
1466  }
1467  if (BG.StartIdx < 32 && BG.EndIdx < 32) {
1468  if (IsAllLow32(BG)) {
1469  if (BG.RLAmt >= 32) {
1470  BG.RLAmt -= 32;
1471  BG.Repl32CR = true;
1472  }
1473 
1474  BG.Repl32 = true;
1475 
1476  LLVM_DEBUG(dbgs() << "\t32-bit replicated bit group for "
1477  << BG.V.getNode() << " RLAmt = " << BG.RLAmt << " ["
1478  << BG.StartIdx << ", " << BG.EndIdx << "]\n");
1479  }
1480  }
1481  }
1482 
1483  // Now walk through the bit groups, consolidating where possible.
1484  for (auto I = BitGroups.begin(); I != BitGroups.end();) {
1485  // We might want to remove this bit group by merging it with the previous
1486  // group (which might be the ending group).
1487  auto IP = (I == BitGroups.begin()) ?
1488  std::prev(BitGroups.end()) : std::prev(I);
1489  if (I->Repl32 && IP->Repl32 && I->V == IP->V && I->RLAmt == IP->RLAmt &&
1490  I->StartIdx == (IP->EndIdx + 1) % 64 && I != IP) {
1491 
1492  LLVM_DEBUG(dbgs() << "\tcombining 32-bit replicated bit group for "
1493  << I->V.getNode() << " RLAmt = " << I->RLAmt << " ["
1494  << I->StartIdx << ", " << I->EndIdx
1495  << "] with group with range [" << IP->StartIdx << ", "
1496  << IP->EndIdx << "]\n");
1497 
1498  IP->EndIdx = I->EndIdx;
1499  IP->Repl32CR = IP->Repl32CR || I->Repl32CR;
1500  IP->Repl32Coalesced = true;
1501  I = BitGroups.erase(I);
1502  continue;
1503  } else {
1504  // There is a special case worth handling: If there is a single group
1505  // covering the entire upper 32 bits, and it can be merged with both
1506  // the next and previous groups (which might be the same group), then
1507  // do so. If it is the same group (so there will be only one group in
1508  // total), then we need to reverse the order of the range so that it
1509  // covers the entire 64 bits.
1510  if (I->StartIdx == 32 && I->EndIdx == 63) {
1511  assert(std::next(I) == BitGroups.end() &&
1512  "bit group ends at index 63 but there is another?");
1513  auto IN = BitGroups.begin();
1514 
1515  if (IP->Repl32 && IN->Repl32 && I->V == IP->V && I->V == IN->V &&
1516  (I->RLAmt % 32) == IP->RLAmt && (I->RLAmt % 32) == IN->RLAmt &&
1517  IP->EndIdx == 31 && IN->StartIdx == 0 && I != IP &&
1518  IsAllLow32(*I)) {
1519 
1520  LLVM_DEBUG(dbgs() << "\tcombining bit group for " << I->V.getNode()
1521  << " RLAmt = " << I->RLAmt << " [" << I->StartIdx
1522  << ", " << I->EndIdx
1523  << "] with 32-bit replicated groups with ranges ["
1524  << IP->StartIdx << ", " << IP->EndIdx << "] and ["
1525  << IN->StartIdx << ", " << IN->EndIdx << "]\n");
1526 
1527  if (IP == IN) {
1528  // There is only one other group; change it to cover the whole
1529  // range (backward, so that it can still be Repl32 but cover the
1530  // whole 64-bit range).
1531  IP->StartIdx = 31;
1532  IP->EndIdx = 30;
1533  IP->Repl32CR = IP->Repl32CR || I->RLAmt >= 32;
1534  IP->Repl32Coalesced = true;
1535  I = BitGroups.erase(I);
1536  } else {
1537  // There are two separate groups, one before this group and one
1538  // after us (at the beginning). We're going to remove this group,
1539  // but also the group at the very beginning.
1540  IP->EndIdx = IN->EndIdx;
1541  IP->Repl32CR = IP->Repl32CR || IN->Repl32CR || I->RLAmt >= 32;
1542  IP->Repl32Coalesced = true;
1543  I = BitGroups.erase(I);
1544  BitGroups.erase(BitGroups.begin());
1545  }
1546 
1547  // This must be the last group in the vector (and we might have
1548  // just invalidated the iterator above), so break here.
1549  break;
1550  }
1551  }
1552  }
1553 
1554  ++I;
1555  }
1556  }
1557 
1558  SDValue getI32Imm(unsigned Imm, const SDLoc &dl) {
1559  return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
1560  }
1561 
1562  uint64_t getZerosMask() {
1563  uint64_t Mask = 0;
1564  for (unsigned i = 0; i < Bits.size(); ++i) {
1565  if (Bits[i].hasValue())
1566  continue;
1567  Mask |= (UINT64_C(1) << i);
1568  }
1569 
1570  return ~Mask;
1571  }
1572 
1573  // This method extends an input value to 64 bit if input is 32-bit integer.
1574  // While selecting instructions in BitPermutationSelector in 64-bit mode,
1575  // an input value can be a 32-bit integer if a ZERO_EXTEND node is included.
1576  // In such case, we extend it to 64 bit to be consistent with other values.
1577  SDValue ExtendToInt64(SDValue V, const SDLoc &dl) {
1578  if (V.getValueSizeInBits() == 64)
1579  return V;
1580 
1581  assert(V.getValueSizeInBits() == 32);
1582  SDValue SubRegIdx = CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32);
1583  SDValue ImDef = SDValue(CurDAG->getMachineNode(PPC::IMPLICIT_DEF, dl,
1584  MVT::i64), 0);
1585  SDValue ExtVal = SDValue(CurDAG->getMachineNode(PPC::INSERT_SUBREG, dl,
1586  MVT::i64, ImDef, V,
1587  SubRegIdx), 0);
1588  return ExtVal;
1589  }
1590 
1591  // Depending on the number of groups for a particular value, it might be
1592  // better to rotate, mask explicitly (using andi/andis), and then or the
1593  // result. Select this part of the result first.
1594  void SelectAndParts32(const SDLoc &dl, SDValue &Res, unsigned *InstCnt) {
1596  return;
1597 
1598  for (ValueRotInfo &VRI : ValueRotsVec) {
1599  unsigned Mask = 0;
1600  for (unsigned i = 0; i < Bits.size(); ++i) {
1601  if (!Bits[i].hasValue() || Bits[i].getValue() != VRI.V)
1602  continue;
1603  if (RLAmt[i] != VRI.RLAmt)
1604  continue;
1605  Mask |= (1u << i);
1606  }
1607 
1608  // Compute the masks for andi/andis that would be necessary.
1609  unsigned ANDIMask = (Mask & UINT16_MAX), ANDISMask = Mask >> 16;
1610  assert((ANDIMask != 0 || ANDISMask != 0) &&
1611  "No set bits in mask for value bit groups");
1612  bool NeedsRotate = VRI.RLAmt != 0;
1613 
1614  // We're trying to minimize the number of instructions. If we have one
1615  // group, using one of andi/andis can break even. If we have three
1616  // groups, we can use both andi and andis and break even (to use both
1617  // andi and andis we also need to or the results together). We need four
1618  // groups if we also need to rotate. To use andi/andis we need to do more
1619  // than break even because rotate-and-mask instructions tend to be easier
1620  // to schedule.
1621 
1622  // FIXME: We've biased here against using andi/andis, which is right for
1623  // POWER cores, but not optimal everywhere. For example, on the A2,
1624  // andi/andis have single-cycle latency whereas the rotate-and-mask
1625  // instructions take two cycles, and it would be better to bias toward
1626  // andi/andis in break-even cases.
1627 
1628  unsigned NumAndInsts = (unsigned) NeedsRotate +
1629  (unsigned) (ANDIMask != 0) +
1630  (unsigned) (ANDISMask != 0) +
1631  (unsigned) (ANDIMask != 0 && ANDISMask != 0) +
1632  (unsigned) (bool) Res;
1633 
1634  LLVM_DEBUG(dbgs() << "\t\trotation groups for " << VRI.V.getNode()
1635  << " RL: " << VRI.RLAmt << ":"
1636  << "\n\t\t\tisel using masking: " << NumAndInsts
1637  << " using rotates: " << VRI.NumGroups << "\n");
1638 
1639  if (NumAndInsts >= VRI.NumGroups)
1640  continue;
1641 
1642  LLVM_DEBUG(dbgs() << "\t\t\t\tusing masking\n");
1643 
1644  if (InstCnt) *InstCnt += NumAndInsts;
1645 
1646  SDValue VRot;
1647  if (VRI.RLAmt) {
1648  SDValue Ops[] =
1649  { VRI.V, getI32Imm(VRI.RLAmt, dl), getI32Imm(0, dl),
1650  getI32Imm(31, dl) };
1651  VRot = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
1652  Ops), 0);
1653  } else {
1654  VRot = VRI.V;
1655  }
1656 
1657  SDValue ANDIVal, ANDISVal;
1658  if (ANDIMask != 0)
1659  ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo, dl, MVT::i32,
1660  VRot, getI32Imm(ANDIMask, dl)), 0);
1661  if (ANDISMask != 0)
1662  ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo, dl, MVT::i32,
1663  VRot, getI32Imm(ANDISMask, dl)), 0);
1664 
1665  SDValue TotalVal;
1666  if (!ANDIVal)
1667  TotalVal = ANDISVal;
1668  else if (!ANDISVal)
1669  TotalVal = ANDIVal;
1670  else
1671  TotalVal = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
1672  ANDIVal, ANDISVal), 0);
1673 
1674  if (!Res)
1675  Res = TotalVal;
1676  else
1677  Res = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
1678  Res, TotalVal), 0);
1679 
1680  // Now, remove all groups with this underlying value and rotation
1681  // factor.
1682  eraseMatchingBitGroups([VRI](const BitGroup &BG) {
1683  return BG.V == VRI.V && BG.RLAmt == VRI.RLAmt;
1684  });
1685  }
1686  }
1687 
1688  // Instruction selection for the 32-bit case.
1689  SDNode *Select32(SDNode *N, bool LateMask, unsigned *InstCnt) {
1690  SDLoc dl(N);
1691  SDValue Res;
1692 
1693  if (InstCnt) *InstCnt = 0;
1694 
1695  // Take care of cases that should use andi/andis first.
1696  SelectAndParts32(dl, Res, InstCnt);
1697 
1698  // If we've not yet selected a 'starting' instruction, and we have no zeros
1699  // to fill in, select the (Value, RLAmt) with the highest priority (largest
1700  // number of groups), and start with this rotated value.
1701  if ((!HasZeros || LateMask) && !Res) {
1702  ValueRotInfo &VRI = ValueRotsVec[0];
1703  if (VRI.RLAmt) {
1704  if (InstCnt) *InstCnt += 1;
1705  SDValue Ops[] =
1706  { VRI.V, getI32Imm(VRI.RLAmt, dl), getI32Imm(0, dl),
1707  getI32Imm(31, dl) };
1708  Res = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops),
1709  0);
1710  } else {
1711  Res = VRI.V;
1712  }
1713 
1714  // Now, remove all groups with this underlying value and rotation factor.
1715  eraseMatchingBitGroups([VRI](const BitGroup &BG) {
1716  return BG.V == VRI.V && BG.RLAmt == VRI.RLAmt;
1717  });
1718  }
1719 
1720  if (InstCnt) *InstCnt += BitGroups.size();
1721 
1722  // Insert the other groups (one at a time).
1723  for (auto &BG : BitGroups) {
1724  if (!Res) {
1725  SDValue Ops[] =
1726  { BG.V, getI32Imm(BG.RLAmt, dl),
1727  getI32Imm(Bits.size() - BG.EndIdx - 1, dl),
1728  getI32Imm(Bits.size() - BG.StartIdx - 1, dl) };
1729  Res = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
1730  } else {
1731  SDValue Ops[] =
1732  { Res, BG.V, getI32Imm(BG.RLAmt, dl),
1733  getI32Imm(Bits.size() - BG.EndIdx - 1, dl),
1734  getI32Imm(Bits.size() - BG.StartIdx - 1, dl) };
1735  Res = SDValue(CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops), 0);
1736  }
1737  }
1738 
1739  if (LateMask) {
1740  unsigned Mask = (unsigned) getZerosMask();
1741 
1742  unsigned ANDIMask = (Mask & UINT16_MAX), ANDISMask = Mask >> 16;
1743  assert((ANDIMask != 0 || ANDISMask != 0) &&
1744  "No set bits in zeros mask?");
1745 
1746  if (InstCnt) *InstCnt += (unsigned) (ANDIMask != 0) +
1747  (unsigned) (ANDISMask != 0) +
1748  (unsigned) (ANDIMask != 0 && ANDISMask != 0);
1749 
1750  SDValue ANDIVal, ANDISVal;
1751  if (ANDIMask != 0)
1752  ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo, dl, MVT::i32,
1753  Res, getI32Imm(ANDIMask, dl)), 0);
1754  if (ANDISMask != 0)
1755  ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo, dl, MVT::i32,
1756  Res, getI32Imm(ANDISMask, dl)), 0);
1757 
1758  if (!ANDIVal)
1759  Res = ANDISVal;
1760  else if (!ANDISVal)
1761  Res = ANDIVal;
1762  else
1763  Res = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
1764  ANDIVal, ANDISVal), 0);
1765  }
1766 
1767  return Res.getNode();
1768  }
1769 
1770  unsigned SelectRotMask64Count(unsigned RLAmt, bool Repl32,
1771  unsigned MaskStart, unsigned MaskEnd,
1772  bool IsIns) {
1773  // In the notation used by the instructions, 'start' and 'end' are reversed
1774  // because bits are counted from high to low order.
1775  unsigned InstMaskStart = 64 - MaskEnd - 1,
1776  InstMaskEnd = 64 - MaskStart - 1;
1777 
1778  if (Repl32)
1779  return 1;
1780 
1781  if ((!IsIns && (InstMaskEnd == 63 || InstMaskStart == 0)) ||
1782  InstMaskEnd == 63 - RLAmt)
1783  return 1;
1784 
1785  return 2;
1786  }
1787 
1788  // For 64-bit values, not all combinations of rotates and masks are
1789  // available. Produce one if it is available.
1790  SDValue SelectRotMask64(SDValue V, const SDLoc &dl, unsigned RLAmt,
1791  bool Repl32, unsigned MaskStart, unsigned MaskEnd,
1792  unsigned *InstCnt = nullptr) {
1793  // In the notation used by the instructions, 'start' and 'end' are reversed
1794  // because bits are counted from high to low order.
1795  unsigned InstMaskStart = 64 - MaskEnd - 1,
1796  InstMaskEnd = 64 - MaskStart - 1;
1797 
1798  if (InstCnt) *InstCnt += 1;
1799 
1800  if (Repl32) {
1801  // This rotation amount assumes that the lower 32 bits of the quantity
1802  // are replicated in the high 32 bits by the rotation operator (which is
1803  // done by rlwinm and friends).
1804  assert(InstMaskStart >= 32 && "Mask cannot start out of range");
1805  assert(InstMaskEnd >= 32 && "Mask cannot end out of range");
1806  SDValue Ops[] =
1807  { ExtendToInt64(V, dl), getI32Imm(RLAmt, dl),
1808  getI32Imm(InstMaskStart - 32, dl), getI32Imm(InstMaskEnd - 32, dl) };
1809  return SDValue(CurDAG->getMachineNode(PPC::RLWINM8, dl, MVT::i64,
1810  Ops), 0);
1811  }
1812 
1813  if (InstMaskEnd == 63) {
1814  SDValue Ops[] =
1815  { ExtendToInt64(V, dl), getI32Imm(RLAmt, dl),
1816  getI32Imm(InstMaskStart, dl) };
1817  return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Ops), 0);
1818  }
1819 
1820  if (InstMaskStart == 0) {
1821  SDValue Ops[] =
1822  { ExtendToInt64(V, dl), getI32Imm(RLAmt, dl),
1823  getI32Imm(InstMaskEnd, dl) };
1824  return SDValue(CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, Ops), 0);
1825  }
1826 
1827  if (InstMaskEnd == 63 - RLAmt) {
1828  SDValue Ops[] =
1829  { ExtendToInt64(V, dl), getI32Imm(RLAmt, dl),
1830  getI32Imm(InstMaskStart, dl) };
1831  return SDValue(CurDAG->getMachineNode(PPC::RLDIC, dl, MVT::i64, Ops), 0);
1832  }
1833 
1834  // We cannot do this with a single instruction, so we'll use two. The
1835  // problem is that we're not free to choose both a rotation amount and mask
1836  // start and end independently. We can choose an arbitrary mask start and
1837  // end, but then the rotation amount is fixed. Rotation, however, can be
1838  // inverted, and so by applying an "inverse" rotation first, we can get the
1839  // desired result.
1840  if (InstCnt) *InstCnt += 1;
1841 
1842  // The rotation mask for the second instruction must be MaskStart.
1843  unsigned RLAmt2 = MaskStart;
1844  // The first instruction must rotate V so that the overall rotation amount
1845  // is RLAmt.
1846  unsigned RLAmt1 = (64 + RLAmt - RLAmt2) % 64;
1847  if (RLAmt1)
1848  V = SelectRotMask64(V, dl, RLAmt1, false, 0, 63);
1849  return SelectRotMask64(V, dl, RLAmt2, false, MaskStart, MaskEnd);
1850  }
1851 
1852  // For 64-bit values, not all combinations of rotates and masks are
1853  // available. Produce a rotate-mask-and-insert if one is available.
1854  SDValue SelectRotMaskIns64(SDValue Base, SDValue V, const SDLoc &dl,
1855  unsigned RLAmt, bool Repl32, unsigned MaskStart,
1856  unsigned MaskEnd, unsigned *InstCnt = nullptr) {
1857  // In the notation used by the instructions, 'start' and 'end' are reversed
1858  // because bits are counted from high to low order.
1859  unsigned InstMaskStart = 64 - MaskEnd - 1,
1860  InstMaskEnd = 64 - MaskStart - 1;
1861 
1862  if (InstCnt) *InstCnt += 1;
1863 
1864  if (Repl32) {
1865  // This rotation amount assumes that the lower 32 bits of the quantity
1866  // are replicated in the high 32 bits by the rotation operator (which is
1867  // done by rlwinm and friends).
1868  assert(InstMaskStart >= 32 && "Mask cannot start out of range");
1869  assert(InstMaskEnd >= 32 && "Mask cannot end out of range");
1870  SDValue Ops[] =
1871  { ExtendToInt64(Base, dl), ExtendToInt64(V, dl), getI32Imm(RLAmt, dl),
1872  getI32Imm(InstMaskStart - 32, dl), getI32Imm(InstMaskEnd - 32, dl) };
1873  return SDValue(CurDAG->getMachineNode(PPC::RLWIMI8, dl, MVT::i64,
1874  Ops), 0);
1875  }
1876 
1877  if (InstMaskEnd == 63 - RLAmt) {
1878  SDValue Ops[] =
1879  { ExtendToInt64(Base, dl), ExtendToInt64(V, dl), getI32Imm(RLAmt, dl),
1880  getI32Imm(InstMaskStart, dl) };
1881  return SDValue(CurDAG->getMachineNode(PPC::RLDIMI, dl, MVT::i64, Ops), 0);
1882  }
1883 
1884  // We cannot do this with a single instruction, so we'll use two. The
1885  // problem is that we're not free to choose both a rotation amount and mask
1886  // start and end independently. We can choose an arbitrary mask start and
1887  // end, but then the rotation amount is fixed. Rotation, however, can be
1888  // inverted, and so by applying an "inverse" rotation first, we can get the
1889  // desired result.
1890  if (InstCnt) *InstCnt += 1;
1891 
1892  // The rotation mask for the second instruction must be MaskStart.
1893  unsigned RLAmt2 = MaskStart;
1894  // The first instruction must rotate V so that the overall rotation amount
1895  // is RLAmt.
1896  unsigned RLAmt1 = (64 + RLAmt - RLAmt2) % 64;
1897  if (RLAmt1)
1898  V = SelectRotMask64(V, dl, RLAmt1, false, 0, 63);
1899  return SelectRotMaskIns64(Base, V, dl, RLAmt2, false, MaskStart, MaskEnd);
1900  }
1901 
1902  void SelectAndParts64(const SDLoc &dl, SDValue &Res, unsigned *InstCnt) {
1904  return;
1905 
1906  // The idea here is the same as in the 32-bit version, but with additional
1907  // complications from the fact that Repl32 might be true. Because we
1908  // aggressively convert bit groups to Repl32 form (which, for small
1909  // rotation factors, involves no other change), and then coalesce, it might
1910  // be the case that a single 64-bit masking operation could handle both
1911  // some Repl32 groups and some non-Repl32 groups. If converting to Repl32
1912  // form allowed coalescing, then we must use a 32-bit rotaton in order to
1913  // completely capture the new combined bit group.
1914 
1915  for (ValueRotInfo &VRI : ValueRotsVec) {
1916  uint64_t Mask = 0;
1917 
1918  // We need to add to the mask all bits from the associated bit groups.
1919  // If Repl32 is false, we need to add bits from bit groups that have
1920  // Repl32 true, but are trivially convertable to Repl32 false. Such a
1921  // group is trivially convertable if it overlaps only with the lower 32
1922  // bits, and the group has not been coalesced.
1923  auto MatchingBG = [VRI](const BitGroup &BG) {
1924  if (VRI.V != BG.V)
1925  return false;
1926 
1927  unsigned EffRLAmt = BG.RLAmt;
1928  if (!VRI.Repl32 && BG.Repl32) {
1929  if (BG.StartIdx < 32 && BG.EndIdx < 32 && BG.StartIdx <= BG.EndIdx &&
1930  !BG.Repl32Coalesced) {
1931  if (BG.Repl32CR)
1932  EffRLAmt += 32;
1933  } else {
1934  return false;
1935  }
1936  } else if (VRI.Repl32 != BG.Repl32) {
1937  return false;
1938  }
1939 
1940  return VRI.RLAmt == EffRLAmt;
1941  };
1942 
1943  for (auto &BG : BitGroups) {
1944  if (!MatchingBG(BG))
1945  continue;
1946 
1947  if (BG.StartIdx <= BG.EndIdx) {
1948  for (unsigned i = BG.StartIdx; i <= BG.EndIdx; ++i)
1949  Mask |= (UINT64_C(1) << i);
1950  } else {
1951  for (unsigned i = BG.StartIdx; i < Bits.size(); ++i)
1952  Mask |= (UINT64_C(1) << i);
1953  for (unsigned i = 0; i <= BG.EndIdx; ++i)
1954  Mask |= (UINT64_C(1) << i);
1955  }
1956  }
1957 
1958  // We can use the 32-bit andi/andis technique if the mask does not
1959  // require any higher-order bits. This can save an instruction compared
1960  // to always using the general 64-bit technique.
1961  bool Use32BitInsts = isUInt<32>(Mask);
1962  // Compute the masks for andi/andis that would be necessary.
1963  unsigned ANDIMask = (Mask & UINT16_MAX),
1964  ANDISMask = (Mask >> 16) & UINT16_MAX;
1965 
1966  bool NeedsRotate = VRI.RLAmt || (VRI.Repl32 && !isUInt<32>(Mask));
1967 
1968  unsigned NumAndInsts = (unsigned) NeedsRotate +
1969  (unsigned) (bool) Res;
1970  if (Use32BitInsts)
1971  NumAndInsts += (unsigned) (ANDIMask != 0) + (unsigned) (ANDISMask != 0) +
1972  (unsigned) (ANDIMask != 0 && ANDISMask != 0);
1973  else
1974  NumAndInsts += selectI64ImmInstrCount(Mask) + /* and */ 1;
1975 
1976  unsigned NumRLInsts = 0;
1977  bool FirstBG = true;
1978  bool MoreBG = false;
1979  for (auto &BG : BitGroups) {
1980  if (!MatchingBG(BG)) {
1981  MoreBG = true;
1982  continue;
1983  }
1984  NumRLInsts +=
1985  SelectRotMask64Count(BG.RLAmt, BG.Repl32, BG.StartIdx, BG.EndIdx,
1986  !FirstBG);
1987  FirstBG = false;
1988  }
1989 
1990  LLVM_DEBUG(dbgs() << "\t\trotation groups for " << VRI.V.getNode()
1991  << " RL: " << VRI.RLAmt << (VRI.Repl32 ? " (32):" : ":")
1992  << "\n\t\t\tisel using masking: " << NumAndInsts
1993  << " using rotates: " << NumRLInsts << "\n");
1994 
1995  // When we'd use andi/andis, we bias toward using the rotates (andi only
1996  // has a record form, and is cracked on POWER cores). However, when using
1997  // general 64-bit constant formation, bias toward the constant form,
1998  // because that exposes more opportunities for CSE.
1999  if (NumAndInsts > NumRLInsts)
2000  continue;
2001  // When merging multiple bit groups, instruction or is used.
2002  // But when rotate is used, rldimi can inert the rotated value into any
2003  // register, so instruction or can be avoided.
2004  if ((Use32BitInsts || MoreBG) && NumAndInsts == NumRLInsts)
2005  continue;
2006 
2007  LLVM_DEBUG(dbgs() << "\t\t\t\tusing masking\n");
2008 
2009  if (InstCnt) *InstCnt += NumAndInsts;
2010 
2011  SDValue VRot;
2012  // We actually need to generate a rotation if we have a non-zero rotation
2013  // factor or, in the Repl32 case, if we care about any of the
2014  // higher-order replicated bits. In the latter case, we generate a mask
2015  // backward so that it actually includes the entire 64 bits.
2016  if (VRI.RLAmt || (VRI.Repl32 && !isUInt<32>(Mask)))
2017  VRot = SelectRotMask64(VRI.V, dl, VRI.RLAmt, VRI.Repl32,
2018  VRI.Repl32 ? 31 : 0, VRI.Repl32 ? 30 : 63);
2019  else
2020  VRot = VRI.V;
2021 
2022  SDValue TotalVal;
2023  if (Use32BitInsts) {
2024  assert((ANDIMask != 0 || ANDISMask != 0) &&
2025  "No set bits in mask when using 32-bit ands for 64-bit value");
2026 
2027  SDValue ANDIVal, ANDISVal;
2028  if (ANDIMask != 0)
2029  ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64,
2030  ExtendToInt64(VRot, dl),
2031  getI32Imm(ANDIMask, dl)),
2032  0);
2033  if (ANDISMask != 0)
2034  ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64,
2035  ExtendToInt64(VRot, dl),
2036  getI32Imm(ANDISMask, dl)),
2037  0);
2038 
2039  if (!ANDIVal)
2040  TotalVal = ANDISVal;
2041  else if (!ANDISVal)
2042  TotalVal = ANDIVal;
2043  else
2044  TotalVal = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
2045  ExtendToInt64(ANDIVal, dl), ANDISVal), 0);
2046  } else {
2047  TotalVal = SDValue(selectI64Imm(CurDAG, dl, Mask), 0);
2048  TotalVal =
2049  SDValue(CurDAG->getMachineNode(PPC::AND8, dl, MVT::i64,
2050  ExtendToInt64(VRot, dl), TotalVal),
2051  0);
2052  }
2053 
2054  if (!Res)
2055  Res = TotalVal;
2056  else
2057  Res = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
2058  ExtendToInt64(Res, dl), TotalVal),
2059  0);
2060 
2061  // Now, remove all groups with this underlying value and rotation
2062  // factor.
2063  eraseMatchingBitGroups(MatchingBG);
2064  }
2065  }
2066 
2067  // Instruction selection for the 64-bit case.
2068  SDNode *Select64(SDNode *N, bool LateMask, unsigned *InstCnt) {
2069  SDLoc dl(N);
2070  SDValue Res;
2071 
2072  if (InstCnt) *InstCnt = 0;
2073 
2074  // Take care of cases that should use andi/andis first.
2075  SelectAndParts64(dl, Res, InstCnt);
2076 
2077  // If we've not yet selected a 'starting' instruction, and we have no zeros
2078  // to fill in, select the (Value, RLAmt) with the highest priority (largest
2079  // number of groups), and start with this rotated value.
2080  if ((!HasZeros || LateMask) && !Res) {
2081  // If we have both Repl32 groups and non-Repl32 groups, the non-Repl32
2082  // groups will come first, and so the VRI representing the largest number
2083  // of groups might not be first (it might be the first Repl32 groups).
2084  unsigned MaxGroupsIdx = 0;
2085  if (!ValueRotsVec[0].Repl32) {
2086  for (unsigned i = 0, ie = ValueRotsVec.size(); i < ie; ++i)
2087  if (ValueRotsVec[i].Repl32) {
2088  if (ValueRotsVec[i].NumGroups > ValueRotsVec[0].NumGroups)
2089  MaxGroupsIdx = i;
2090  break;
2091  }
2092  }
2093 
2094  ValueRotInfo &VRI = ValueRotsVec[MaxGroupsIdx];
2095  bool NeedsRotate = false;
2096  if (VRI.RLAmt) {
2097  NeedsRotate = true;
2098  } else if (VRI.Repl32) {
2099  for (auto &BG : BitGroups) {
2100  if (BG.V != VRI.V || BG.RLAmt != VRI.RLAmt ||
2101  BG.Repl32 != VRI.Repl32)
2102  continue;
2103 
2104  // We don't need a rotate if the bit group is confined to the lower
2105  // 32 bits.
2106  if (BG.StartIdx < 32 && BG.EndIdx < 32 && BG.StartIdx < BG.EndIdx)
2107  continue;
2108 
2109  NeedsRotate = true;
2110  break;
2111  }
2112  }
2113 
2114  if (NeedsRotate)
2115  Res = SelectRotMask64(VRI.V, dl, VRI.RLAmt, VRI.Repl32,
2116  VRI.Repl32 ? 31 : 0, VRI.Repl32 ? 30 : 63,
2117  InstCnt);
2118  else
2119  Res = VRI.V;
2120 
2121  // Now, remove all groups with this underlying value and rotation factor.
2122  if (Res)
2123  eraseMatchingBitGroups([VRI](const BitGroup &BG) {
2124  return BG.V == VRI.V && BG.RLAmt == VRI.RLAmt &&
2125  BG.Repl32 == VRI.Repl32;
2126  });
2127  }
2128 
2129  // Because 64-bit rotates are more flexible than inserts, we might have a
2130  // preference regarding which one we do first (to save one instruction).
2131  if (!Res)
2132  for (auto I = BitGroups.begin(), IE = BitGroups.end(); I != IE; ++I) {
2133  if (SelectRotMask64Count(I->RLAmt, I->Repl32, I->StartIdx, I->EndIdx,
2134  false) <
2135  SelectRotMask64Count(I->RLAmt, I->Repl32, I->StartIdx, I->EndIdx,
2136  true)) {
2137  if (I != BitGroups.begin()) {
2138  BitGroup BG = *I;
2139  BitGroups.erase(I);
2140  BitGroups.insert(BitGroups.begin(), BG);
2141  }
2142 
2143  break;
2144  }
2145  }
2146 
2147  // Insert the other groups (one at a time).
2148  for (auto &BG : BitGroups) {
2149  if (!Res)
2150  Res = SelectRotMask64(BG.V, dl, BG.RLAmt, BG.Repl32, BG.StartIdx,
2151  BG.EndIdx, InstCnt);
2152  else
2153  Res = SelectRotMaskIns64(Res, BG.V, dl, BG.RLAmt, BG.Repl32,
2154  BG.StartIdx, BG.EndIdx, InstCnt);
2155  }
2156 
2157  if (LateMask) {
2158  uint64_t Mask = getZerosMask();
2159 
2160  // We can use the 32-bit andi/andis technique if the mask does not
2161  // require any higher-order bits. This can save an instruction compared
2162  // to always using the general 64-bit technique.
2163  bool Use32BitInsts = isUInt<32>(Mask);
2164  // Compute the masks for andi/andis that would be necessary.
2165  unsigned ANDIMask = (Mask & UINT16_MAX),
2166  ANDISMask = (Mask >> 16) & UINT16_MAX;
2167 
2168  if (Use32BitInsts) {
2169  assert((ANDIMask != 0 || ANDISMask != 0) &&
2170  "No set bits in mask when using 32-bit ands for 64-bit value");
2171 
2172  if (InstCnt) *InstCnt += (unsigned) (ANDIMask != 0) +
2173  (unsigned) (ANDISMask != 0) +
2174  (unsigned) (ANDIMask != 0 && ANDISMask != 0);
2175 
2176  SDValue ANDIVal, ANDISVal;
2177  if (ANDIMask != 0)
2178  ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64,
2179  ExtendToInt64(Res, dl), getI32Imm(ANDIMask, dl)), 0);
2180  if (ANDISMask != 0)
2181  ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64,
2182  ExtendToInt64(Res, dl), getI32Imm(ANDISMask, dl)), 0);
2183 
2184  if (!ANDIVal)
2185  Res = ANDISVal;
2186  else if (!ANDISVal)
2187  Res = ANDIVal;
2188  else
2189  Res = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
2190  ExtendToInt64(ANDIVal, dl), ANDISVal), 0);
2191  } else {
2192  if (InstCnt) *InstCnt += selectI64ImmInstrCount(Mask) + /* and */ 1;
2193 
2194  SDValue MaskVal = SDValue(selectI64Imm(CurDAG, dl, Mask), 0);
2195  Res =
2196  SDValue(CurDAG->getMachineNode(PPC::AND8, dl, MVT::i64,
2197  ExtendToInt64(Res, dl), MaskVal), 0);
2198  }
2199  }
2200 
2201  return Res.getNode();
2202  }
2203 
2204  SDNode *Select(SDNode *N, bool LateMask, unsigned *InstCnt = nullptr) {
2205  // Fill in BitGroups.
2206  collectBitGroups(LateMask);
2207  if (BitGroups.empty())
2208  return nullptr;
2209 
2210  // For 64-bit values, figure out when we can use 32-bit instructions.
2211  if (Bits.size() == 64)
2212  assignRepl32BitGroups();
2213 
2214  // Fill in ValueRotsVec.
2215  collectValueRotInfo();
2216 
2217  if (Bits.size() == 32) {
2218  return Select32(N, LateMask, InstCnt);
2219  } else {
2220  assert(Bits.size() == 64 && "Not 64 bits here?");
2221  return Select64(N, LateMask, InstCnt);
2222  }
2223 
2224  return nullptr;
2225  }
2226 
2227  void eraseMatchingBitGroups(function_ref<bool(const BitGroup &)> F) {
2228  BitGroups.erase(remove_if(BitGroups, F), BitGroups.end());
2229  }
2230 
2232 
2233  bool HasZeros;
2235 
2236  SmallVector<BitGroup, 16> BitGroups;
2237 
2238  DenseMap<std::pair<SDValue, unsigned>, ValueRotInfo> ValueRots;
2239  SmallVector<ValueRotInfo, 16> ValueRotsVec;
2240 
2241  SelectionDAG *CurDAG;
2242 
2243 public:
2244  BitPermutationSelector(SelectionDAG *DAG)
2245  : CurDAG(DAG) {}
2246 
2247  // Here we try to match complex bit permutations into a set of
2248  // rotate-and-shift/shift/and/or instructions, using a set of heuristics
2249  // known to produce optimial code for common cases (like i32 byte swapping).
2250  SDNode *Select(SDNode *N) {
2251  Memoizer.clear();
2252  auto Result =
2253  getValueBits(SDValue(N, 0), N->getValueType(0).getSizeInBits());
2254  if (!Result.first)
2255  return nullptr;
2256  Bits = std::move(*Result.second);
2257 
2258  LLVM_DEBUG(dbgs() << "Considering bit-permutation-based instruction"
2259  " selection for: ");
2260  LLVM_DEBUG(N->dump(CurDAG));
2261 
2262  // Fill it RLAmt and set HasZeros.
2263  computeRotationAmounts();
2264 
2265  if (!HasZeros)
2266  return Select(N, false);
2267 
2268  // We currently have two techniques for handling results with zeros: early
2269  // masking (the default) and late masking. Late masking is sometimes more
2270  // efficient, but because the structure of the bit groups is different, it
2271  // is hard to tell without generating both and comparing the results. With
2272  // late masking, we ignore zeros in the resulting value when inserting each
2273  // set of bit groups, and then mask in the zeros at the end. With early
2274  // masking, we only insert the non-zero parts of the result at every step.
2275 
2276  unsigned InstCnt = 0, InstCntLateMask = 0;
2277  LLVM_DEBUG(dbgs() << "\tEarly masking:\n");
2278  SDNode *RN = Select(N, false, &InstCnt);
2279  LLVM_DEBUG(dbgs() << "\t\tisel would use " << InstCnt << " instructions\n");
2280 
2281  LLVM_DEBUG(dbgs() << "\tLate masking:\n");
2282  SDNode *RNLM = Select(N, true, &InstCntLateMask);
2283  LLVM_DEBUG(dbgs() << "\t\tisel would use " << InstCntLateMask
2284  << " instructions\n");
2285 
2286  if (InstCnt <= InstCntLateMask) {
2287  LLVM_DEBUG(dbgs() << "\tUsing early-masking for isel\n");
2288  return RN;
2289  }
2290 
2291  LLVM_DEBUG(dbgs() << "\tUsing late-masking for isel\n");
2292  return RNLM;
2293  }
2294 };
2295 
2296 class IntegerCompareEliminator {
2297  SelectionDAG *CurDAG;
2298  PPCDAGToDAGISel *S;
2299  // Conversion type for interpreting results of a 32-bit instruction as
2300  // a 64-bit value or vice versa.
2301  enum ExtOrTruncConversion { Ext, Trunc };
2302 
2303  // Modifiers to guide how an ISD::SETCC node's result is to be computed
2304  // in a GPR.
2305  // ZExtOrig - use the original condition code, zero-extend value
2306  // ZExtInvert - invert the condition code, zero-extend value
2307  // SExtOrig - use the original condition code, sign-extend value
2308  // SExtInvert - invert the condition code, sign-extend value
2309  enum SetccInGPROpts { ZExtOrig, ZExtInvert, SExtOrig, SExtInvert };
2310 
2311  // Comparisons against zero to emit GPR code sequences for. Each of these
2312  // sequences may need to be emitted for two or more equivalent patterns.
2313  // For example (a >= 0) == (a > -1). The direction of the comparison (</>)
2314  // matters as well as the extension type: sext (-1/0), zext (1/0).
2315  // GEZExt - (zext (LHS >= 0))
2316  // GESExt - (sext (LHS >= 0))
2317  // LEZExt - (zext (LHS <= 0))
2318  // LESExt - (sext (LHS <= 0))
2319  enum ZeroCompare { GEZExt, GESExt, LEZExt, LESExt };
2320 
2321  SDNode *tryEXTEND(SDNode *N);
2322  SDNode *tryLogicOpOfCompares(SDNode *N);
2323  SDValue computeLogicOpInGPR(SDValue LogicOp);
2324  SDValue signExtendInputIfNeeded(SDValue Input);
2325  SDValue zeroExtendInputIfNeeded(SDValue Input);
2326  SDValue addExtOrTrunc(SDValue NatWidthRes, ExtOrTruncConversion Conv);
2327  SDValue getCompoundZeroComparisonInGPR(SDValue LHS, SDLoc dl,
2328  ZeroCompare CmpTy);
2329  SDValue get32BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2330  int64_t RHSValue, SDLoc dl);
2331  SDValue get32BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2332  int64_t RHSValue, SDLoc dl);
2333  SDValue get64BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2334  int64_t RHSValue, SDLoc dl);
2335  SDValue get64BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2336  int64_t RHSValue, SDLoc dl);
2337  SDValue getSETCCInGPR(SDValue Compare, SetccInGPROpts ConvOpts);
2338 
2339 public:
2340  IntegerCompareEliminator(SelectionDAG *DAG,
2341  PPCDAGToDAGISel *Sel) : CurDAG(DAG), S(Sel) {
2342  assert(CurDAG->getTargetLoweringInfo()
2343  .getPointerTy(CurDAG->getDataLayout()).getSizeInBits() == 64 &&
2344  "Only expecting to use this on 64 bit targets.");
2345  }
2346  SDNode *Select(SDNode *N) {
2347  if (CmpInGPR == ICGPR_None)
2348  return nullptr;
2349  switch (N->getOpcode()) {
2350  default: break;
2351  case ISD::ZERO_EXTEND:
2352  if (CmpInGPR == ICGPR_Sext || CmpInGPR == ICGPR_SextI32 ||
2353  CmpInGPR == ICGPR_SextI64)
2354  return nullptr;
2356  case ISD::SIGN_EXTEND:
2357  if (CmpInGPR == ICGPR_Zext || CmpInGPR == ICGPR_ZextI32 ||
2359  return nullptr;
2360  return tryEXTEND(N);
2361  case ISD::AND:
2362  case ISD::OR:
2363  case ISD::XOR:
2364  return tryLogicOpOfCompares(N);
2365  }
2366  return nullptr;
2367  }
2368 };
2369 
2370 static bool isLogicOp(unsigned Opc) {
2371  return Opc == ISD::AND || Opc == ISD::OR || Opc == ISD::XOR;
2372 }
2373 // The obvious case for wanting to keep the value in a GPR. Namely, the
2374 // result of the comparison is actually needed in a GPR.
2375 SDNode *IntegerCompareEliminator::tryEXTEND(SDNode *N) {
2376  assert((N->getOpcode() == ISD::ZERO_EXTEND ||
2377  N->getOpcode() == ISD::SIGN_EXTEND) &&
2378  "Expecting a zero/sign extend node!");
2379  SDValue WideRes;
2380  // If we are zero-extending the result of a logical operation on i1
2381  // values, we can keep the values in GPRs.
2382  if (isLogicOp(N->getOperand(0).getOpcode()) &&
2383  N->getOperand(0).getValueType() == MVT::i1 &&
2384  N->getOpcode() == ISD::ZERO_EXTEND)
2385  WideRes = computeLogicOpInGPR(N->getOperand(0));
2386  else if (N->getOperand(0).getOpcode() != ISD::SETCC)
2387  return nullptr;
2388  else
2389  WideRes =
2390  getSETCCInGPR(N->getOperand(0),
2391  N->getOpcode() == ISD::SIGN_EXTEND ?
2392  SetccInGPROpts::SExtOrig : SetccInGPROpts::ZExtOrig);
2393 
2394  if (!WideRes)
2395  return nullptr;
2396 
2397  SDLoc dl(N);
2398  bool Input32Bit = WideRes.getValueType() == MVT::i32;
2399  bool Output32Bit = N->getValueType(0) == MVT::i32;
2400 
2401  NumSextSetcc += N->getOpcode() == ISD::SIGN_EXTEND ? 1 : 0;
2402  NumZextSetcc += N->getOpcode() == ISD::SIGN_EXTEND ? 0 : 1;
2403 
2404  SDValue ConvOp = WideRes;
2405  if (Input32Bit != Output32Bit)
2406  ConvOp = addExtOrTrunc(WideRes, Input32Bit ? ExtOrTruncConversion::Ext :
2407  ExtOrTruncConversion::Trunc);
2408  return ConvOp.getNode();
2409 }
2410 
2411 // Attempt to perform logical operations on the results of comparisons while
2412 // keeping the values in GPRs. Without doing so, these would end up being
2413 // lowered to CR-logical operations which suffer from significant latency and
2414 // low ILP.
2415 SDNode *IntegerCompareEliminator::tryLogicOpOfCompares(SDNode *N) {
2416  if (N->getValueType(0) != MVT::i1)
2417  return nullptr;
2418  assert(isLogicOp(N->getOpcode()) &&
2419  "Expected a logic operation on setcc results.");
2420  SDValue LoweredLogical = computeLogicOpInGPR(SDValue(N, 0));
2421  if (!LoweredLogical)
2422  return nullptr;
2423 
2424  SDLoc dl(N);
2425  bool IsBitwiseNegate = LoweredLogical.getMachineOpcode() == PPC::XORI8;
2426  unsigned SubRegToExtract = IsBitwiseNegate ? PPC::sub_eq : PPC::sub_gt;
2427  SDValue CR0Reg = CurDAG->getRegister(PPC::CR0, MVT::i32);
2428  SDValue LHS = LoweredLogical.getOperand(0);
2429  SDValue RHS = LoweredLogical.getOperand(1);
2430  SDValue WideOp;
2431  SDValue OpToConvToRecForm;
2432 
2433  // Look through any 32-bit to 64-bit implicit extend nodes to find the
2434  // opcode that is input to the XORI.
2435  if (IsBitwiseNegate &&
2436  LoweredLogical.getOperand(0).getMachineOpcode() == PPC::INSERT_SUBREG)
2437  OpToConvToRecForm = LoweredLogical.getOperand(0).getOperand(1);
2438  else if (IsBitwiseNegate)
2439  // If the input to the XORI isn't an extension, that's what we're after.
2440  OpToConvToRecForm = LoweredLogical.getOperand(0);
2441  else
2442  // If this is not an XORI, it is a reg-reg logical op and we can convert
2443  // it to record-form.
2444  OpToConvToRecForm = LoweredLogical;
2445 
2446  // Get the record-form version of the node we're looking to use to get the
2447  // CR result from.
2448  uint16_t NonRecOpc = OpToConvToRecForm.getMachineOpcode();
2449  int NewOpc = PPCInstrInfo::getRecordFormOpcode(NonRecOpc);
2450 
2451  // Convert the right node to record-form. This is either the logical we're
2452  // looking at or it is the input node to the negation (if we're looking at
2453  // a bitwise negation).
2454  if (NewOpc != -1 && IsBitwiseNegate) {
2455  // The input to the XORI has a record-form. Use it.
2456  assert(LoweredLogical.getConstantOperandVal(1) == 1 &&
2457  "Expected a PPC::XORI8 only for bitwise negation.");
2458  // Emit the record-form instruction.
2459  std::vector<SDValue> Ops;
2460  for (int i = 0, e = OpToConvToRecForm.getNumOperands(); i < e; i++)
2461  Ops.push_back(OpToConvToRecForm.getOperand(i));
2462 
2463  WideOp =
2464  SDValue(CurDAG->getMachineNode(NewOpc, dl,
2465  OpToConvToRecForm.getValueType(),
2466  MVT::Glue, Ops), 0);
2467  } else {
2468  assert((NewOpc != -1 || !IsBitwiseNegate) &&
2469  "No record form available for AND8/OR8/XOR8?");
2470  WideOp =
2471  SDValue(CurDAG->getMachineNode(NewOpc == -1 ? PPC::ANDIo8 : NewOpc, dl,
2472  MVT::i64, MVT::Glue, LHS, RHS), 0);
2473  }
2474 
2475  // Select this node to a single bit from CR0 set by the record-form node
2476  // just created. For bitwise negation, use the EQ bit which is the equivalent
2477  // of negating the result (i.e. it is a bit set when the result of the
2478  // operation is zero).
2479  SDValue SRIdxVal =
2480  CurDAG->getTargetConstant(SubRegToExtract, dl, MVT::i32);
2481  SDValue CRBit =
2482  SDValue(CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl,
2483  MVT::i1, CR0Reg, SRIdxVal,
2484  WideOp.getValue(1)), 0);
2485  return CRBit.getNode();
2486 }
2487 
2488 // Lower a logical operation on i1 values into a GPR sequence if possible.
2489 // The result can be kept in a GPR if requested.
2490 // Three types of inputs can be handled:
2491 // - SETCC
2492 // - TRUNCATE
2493 // - Logical operation (AND/OR/XOR)
2494 // There is also a special case that is handled (namely a complement operation
2495 // achieved with xor %a, -1).
2496 SDValue IntegerCompareEliminator::computeLogicOpInGPR(SDValue LogicOp) {
2497  assert(isLogicOp(LogicOp.getOpcode()) &&
2498  "Can only handle logic operations here.");
2499  assert(LogicOp.getValueType() == MVT::i1 &&
2500  "Can only handle logic operations on i1 values here.");
2501  SDLoc dl(LogicOp);
2502  SDValue LHS, RHS;
2503 
2504  // Special case: xor %a, -1
2505  bool IsBitwiseNegation = isBitwiseNot(LogicOp);
2506 
2507  // Produces a GPR sequence for each operand of the binary logic operation.
2508  // For SETCC, it produces the respective comparison, for TRUNCATE it truncates
2509  // the value in a GPR and for logic operations, it will recursively produce
2510  // a GPR sequence for the operation.
2511  auto getLogicOperand = [&] (SDValue Operand) -> SDValue {
2512  unsigned OperandOpcode = Operand.getOpcode();
2513  if (OperandOpcode == ISD::SETCC)
2514  return getSETCCInGPR(Operand, SetccInGPROpts::ZExtOrig);
2515  else if (OperandOpcode == ISD::TRUNCATE) {
2516  SDValue InputOp = Operand.getOperand(0);
2517  EVT InVT = InputOp.getValueType();
2518  return SDValue(CurDAG->getMachineNode(InVT == MVT::i32 ? PPC::RLDICL_32 :
2519  PPC::RLDICL, dl, InVT, InputOp,
2520  S->getI64Imm(0, dl),
2521  S->getI64Imm(63, dl)), 0);
2522  } else if (isLogicOp(OperandOpcode))
2523  return computeLogicOpInGPR(Operand);
2524  return SDValue();
2525  };
2526  LHS = getLogicOperand(LogicOp.getOperand(0));
2527  RHS = getLogicOperand(LogicOp.getOperand(1));
2528 
2529  // If a GPR sequence can't be produced for the LHS we can't proceed.
2530  // Not producing a GPR sequence for the RHS is only a problem if this isn't
2531  // a bitwise negation operation.
2532  if (!LHS || (!RHS && !IsBitwiseNegation))
2533  return SDValue();
2534 
2535  NumLogicOpsOnComparison++;
2536 
2537  // We will use the inputs as 64-bit values.
2538  if (LHS.getValueType() == MVT::i32)
2539  LHS = addExtOrTrunc(LHS, ExtOrTruncConversion::Ext);
2540  if (!IsBitwiseNegation && RHS.getValueType() == MVT::i32)
2541  RHS = addExtOrTrunc(RHS, ExtOrTruncConversion::Ext);
2542 
2543  unsigned NewOpc;
2544  switch (LogicOp.getOpcode()) {
2545  default: llvm_unreachable("Unknown logic operation.");
2546  case ISD::AND: NewOpc = PPC::AND8; break;
2547  case ISD::OR: NewOpc = PPC::OR8; break;
2548  case ISD::XOR: NewOpc = PPC::XOR8; break;
2549  }
2550 
2551  if (IsBitwiseNegation) {
2552  RHS = S->getI64Imm(1, dl);
2553  NewOpc = PPC::XORI8;
2554  }
2555 
2556  return SDValue(CurDAG->getMachineNode(NewOpc, dl, MVT::i64, LHS, RHS), 0);
2557 
2558 }
2559 
2560 /// If the value isn't guaranteed to be sign-extended to 64-bits, extend it.
2561 /// Otherwise just reinterpret it as a 64-bit value.
2562 /// Useful when emitting comparison code for 32-bit values without using
2563 /// the compare instruction (which only considers the lower 32-bits).
2564 SDValue IntegerCompareEliminator::signExtendInputIfNeeded(SDValue Input) {
2565  assert(Input.getValueType() == MVT::i32 &&
2566  "Can only sign-extend 32-bit values here.");
2567  unsigned Opc = Input.getOpcode();
2568 
2569  // The value was sign extended and then truncated to 32-bits. No need to
2570  // sign extend it again.
2571  if (Opc == ISD::TRUNCATE &&
2572  (Input.getOperand(0).getOpcode() == ISD::AssertSext ||
2573  Input.getOperand(0).getOpcode() == ISD::SIGN_EXTEND))
2574  return addExtOrTrunc(Input, ExtOrTruncConversion::Ext);
2575 
2576  LoadSDNode *InputLoad = dyn_cast<LoadSDNode>(Input);
2577  // The input is a sign-extending load. All ppc sign-extending loads
2578  // sign-extend to the full 64-bits.
2579  if (InputLoad && InputLoad->getExtensionType() == ISD::SEXTLOAD)
2580  return addExtOrTrunc(Input, ExtOrTruncConversion::Ext);
2581 
2582  ConstantSDNode *InputConst = dyn_cast<ConstantSDNode>(Input);
2583  // We don't sign-extend constants.
2584  if (InputConst)
2585  return addExtOrTrunc(Input, ExtOrTruncConversion::Ext);
2586 
2587  SDLoc dl(Input);
2588  SignExtensionsAdded++;
2589  return SDValue(CurDAG->getMachineNode(PPC::EXTSW_32_64, dl,
2590  MVT::i64, Input), 0);
2591 }
2592 
2593 /// If the value isn't guaranteed to be zero-extended to 64-bits, extend it.
2594 /// Otherwise just reinterpret it as a 64-bit value.
2595 /// Useful when emitting comparison code for 32-bit values without using
2596 /// the compare instruction (which only considers the lower 32-bits).
2597 SDValue IntegerCompareEliminator::zeroExtendInputIfNeeded(SDValue Input) {
2598  assert(Input.getValueType() == MVT::i32 &&
2599  "Can only zero-extend 32-bit values here.");
2600  unsigned Opc = Input.getOpcode();
2601 
2602  // The only condition under which we can omit the actual extend instruction:
2603  // - The value is a positive constant
2604  // - The value comes from a load that isn't a sign-extending load
2605  // An ISD::TRUNCATE needs to be zero-extended unless it is fed by a zext.
2606  bool IsTruncateOfZExt = Opc == ISD::TRUNCATE &&
2607  (Input.getOperand(0).getOpcode() == ISD::AssertZext ||
2608  Input.getOperand(0).getOpcode() == ISD::ZERO_EXTEND);
2609  if (IsTruncateOfZExt)
2610  return addExtOrTrunc(Input, ExtOrTruncConversion::Ext);
2611 
2612  ConstantSDNode *InputConst = dyn_cast<ConstantSDNode>(Input);
2613  if (InputConst && InputConst->getSExtValue() >= 0)
2614  return addExtOrTrunc(Input, ExtOrTruncConversion::Ext);
2615 
2616  LoadSDNode *InputLoad = dyn_cast<LoadSDNode>(Input);
2617  // The input is a load that doesn't sign-extend (it will be zero-extended).
2618  if (InputLoad && InputLoad->getExtensionType() != ISD::SEXTLOAD)
2619  return addExtOrTrunc(Input, ExtOrTruncConversion::Ext);
2620 
2621  // None of the above, need to zero-extend.
2622  SDLoc dl(Input);
2623  ZeroExtensionsAdded++;
2624  return SDValue(CurDAG->getMachineNode(PPC::RLDICL_32_64, dl, MVT::i64, Input,
2625  S->getI64Imm(0, dl),
2626  S->getI64Imm(32, dl)), 0);
2627 }
2628 
2629 // Handle a 32-bit value in a 64-bit register and vice-versa. These are of
2630 // course not actual zero/sign extensions that will generate machine code,
2631 // they're just a way to reinterpret a 32 bit value in a register as a
2632 // 64 bit value and vice-versa.
2633 SDValue IntegerCompareEliminator::addExtOrTrunc(SDValue NatWidthRes,
2634  ExtOrTruncConversion Conv) {
2635  SDLoc dl(NatWidthRes);
2636 
2637  // For reinterpreting 32-bit values as 64 bit values, we generate
2638  // INSERT_SUBREG IMPLICIT_DEF:i64, <input>, TargetConstant:i32<1>
2639  if (Conv == ExtOrTruncConversion::Ext) {
2640  SDValue ImDef(CurDAG->getMachineNode(PPC::IMPLICIT_DEF, dl, MVT::i64), 0);
2641  SDValue SubRegIdx =
2642  CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32);
2643  return SDValue(CurDAG->getMachineNode(PPC::INSERT_SUBREG, dl, MVT::i64,
2644  ImDef, NatWidthRes, SubRegIdx), 0);
2645  }
2646 
2647  assert(Conv == ExtOrTruncConversion::Trunc &&
2648  "Unknown convertion between 32 and 64 bit values.");
2649  // For reinterpreting 64-bit values as 32-bit values, we just need to
2650  // EXTRACT_SUBREG (i.e. extract the low word).
2651  SDValue SubRegIdx =
2652  CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32);
2653  return SDValue(CurDAG->getMachineNode(PPC::EXTRACT_SUBREG, dl, MVT::i32,
2654  NatWidthRes, SubRegIdx), 0);
2655 }
2656 
2657 // Produce a GPR sequence for compound comparisons (<=, >=) against zero.
2658 // Handle both zero-extensions and sign-extensions.
2659 SDValue
2660 IntegerCompareEliminator::getCompoundZeroComparisonInGPR(SDValue LHS, SDLoc dl,
2661  ZeroCompare CmpTy) {
2662  EVT InVT = LHS.getValueType();
2663  bool Is32Bit = InVT == MVT::i32;
2664  SDValue ToExtend;
2665 
2666  // Produce the value that needs to be either zero or sign extended.
2667  switch (CmpTy) {
2668  case ZeroCompare::GEZExt:
2669  case ZeroCompare::GESExt:
2670  ToExtend = SDValue(CurDAG->getMachineNode(Is32Bit ? PPC::NOR : PPC::NOR8,
2671  dl, InVT, LHS, LHS), 0);
2672  break;
2673  case ZeroCompare::LEZExt:
2674  case ZeroCompare::LESExt: {
2675  if (Is32Bit) {
2676  // Upper 32 bits cannot be undefined for this sequence.
2677  LHS = signExtendInputIfNeeded(LHS);
2678  SDValue Neg =
2679  SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, LHS), 0);
2680  ToExtend =
2681  SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
2682  Neg, S->getI64Imm(1, dl),
2683  S->getI64Imm(63, dl)), 0);
2684  } else {
2685  SDValue Addi =
2686  SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, LHS,
2687  S->getI64Imm(~0ULL, dl)), 0);
2688  ToExtend = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
2689  Addi, LHS), 0);
2690  }
2691  break;
2692  }
2693  }
2694 
2695  // For 64-bit sequences, the extensions are the same for the GE/LE cases.
2696  if (!Is32Bit &&
2697  (CmpTy == ZeroCompare::GEZExt || CmpTy == ZeroCompare::LEZExt))
2698  return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
2699  ToExtend, S->getI64Imm(1, dl),
2700  S->getI64Imm(63, dl)), 0);
2701  if (!Is32Bit &&
2702  (CmpTy == ZeroCompare::GESExt || CmpTy == ZeroCompare::LESExt))
2703  return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, ToExtend,
2704  S->getI64Imm(63, dl)), 0);
2705 
2706  assert(Is32Bit && "Should have handled the 32-bit sequences above.");
2707  // For 32-bit sequences, the extensions differ between GE/LE cases.
2708  switch (CmpTy) {
2709  case ZeroCompare::GEZExt: {
2710  SDValue ShiftOps[] = { ToExtend, S->getI32Imm(1, dl), S->getI32Imm(31, dl),
2711  S->getI32Imm(31, dl) };
2712  return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
2713  ShiftOps), 0);
2714  }
2715  case ZeroCompare::GESExt:
2716  return SDValue(CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, ToExtend,
2717  S->getI32Imm(31, dl)), 0);
2718  case ZeroCompare::LEZExt:
2719  return SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64, ToExtend,
2720  S->getI32Imm(1, dl)), 0);
2721  case ZeroCompare::LESExt:
2722  return SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, ToExtend,
2723  S->getI32Imm(-1, dl)), 0);
2724  }
2725 
2726  // The above case covers all the enumerators so it can't have a default clause
2727  // to avoid compiler warnings.
2728  llvm_unreachable("Unknown zero-comparison type.");
2729 }
2730 
2731 /// Produces a zero-extended result of comparing two 32-bit values according to
2732 /// the passed condition code.
2733 SDValue
2734 IntegerCompareEliminator::get32BitZExtCompare(SDValue LHS, SDValue RHS,
2735  ISD::CondCode CC,
2736  int64_t RHSValue, SDLoc dl) {
2737  if (CmpInGPR == ICGPR_I64 || CmpInGPR == ICGPR_SextI64 ||
2739  return SDValue();
2740  bool IsRHSZero = RHSValue == 0;
2741  bool IsRHSOne = RHSValue == 1;
2742  bool IsRHSNegOne = RHSValue == -1LL;
2743  switch (CC) {
2744  default: return SDValue();
2745  case ISD::SETEQ: {
2746  // (zext (setcc %a, %b, seteq)) -> (lshr (cntlzw (xor %a, %b)), 5)
2747  // (zext (setcc %a, 0, seteq)) -> (lshr (cntlzw %a), 5)
2748  SDValue Xor = IsRHSZero ? LHS :
2749  SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
2750  SDValue Clz =
2751  SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0);
2752  SDValue ShiftOps[] = { Clz, S->getI32Imm(27, dl), S->getI32Imm(5, dl),
2753  S->getI32Imm(31, dl) };
2754  return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
2755  ShiftOps), 0);
2756  }
2757  case ISD::SETNE: {
2758  // (zext (setcc %a, %b, setne)) -> (xor (lshr (cntlzw (xor %a, %b)), 5), 1)
2759  // (zext (setcc %a, 0, setne)) -> (xor (lshr (cntlzw %a), 5), 1)
2760  SDValue Xor = IsRHSZero ? LHS :
2761  SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
2762  SDValue Clz =
2763  SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0);
2764  SDValue ShiftOps[] = { Clz, S->getI32Imm(27, dl), S->getI32Imm(5, dl),
2765  S->getI32Imm(31, dl) };
2766  SDValue Shift =
2767  SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, ShiftOps), 0);
2768  return SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Shift,
2769  S->getI32Imm(1, dl)), 0);
2770  }
2771  case ISD::SETGE: {
2772  // (zext (setcc %a, %b, setge)) -> (xor (lshr (sub %a, %b), 63), 1)
2773  // (zext (setcc %a, 0, setge)) -> (lshr (~ %a), 31)
2774  if(IsRHSZero)
2775  return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt);
2776 
2777  // Not a special case (i.e. RHS == 0). Handle (%a >= %b) as (%b <= %a)
2778  // by swapping inputs and falling through.
2779  std::swap(LHS, RHS);
2780  ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
2781  IsRHSZero = RHSConst && RHSConst->isNullValue();
2783  }
2784  case ISD::SETLE: {
2785  if (CmpInGPR == ICGPR_NonExtIn)
2786  return SDValue();
2787  // (zext (setcc %a, %b, setle)) -> (xor (lshr (sub %b, %a), 63), 1)
2788  // (zext (setcc %a, 0, setle)) -> (xor (lshr (- %a), 63), 1)
2789  if(IsRHSZero) {
2790  if (CmpInGPR == ICGPR_NonExtIn)
2791  return SDValue();
2792  return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt);
2793  }
2794 
2795  // The upper 32-bits of the register can't be undefined for this sequence.
2796  LHS = signExtendInputIfNeeded(LHS);
2797  RHS = signExtendInputIfNeeded(RHS);
2798  SDValue Sub =
2799  SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, LHS, RHS), 0);
2800  SDValue Shift =
2801  SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Sub,
2802  S->getI64Imm(1, dl), S->getI64Imm(63, dl)),
2803  0);
2804  return
2805  SDValue(CurDAG->getMachineNode(PPC::XORI8, dl,
2806  MVT::i64, Shift, S->getI32Imm(1, dl)), 0);
2807  }
2808  case ISD::SETGT: {
2809  // (zext (setcc %a, %b, setgt)) -> (lshr (sub %b, %a), 63)
2810  // (zext (setcc %a, -1, setgt)) -> (lshr (~ %a), 31)
2811  // (zext (setcc %a, 0, setgt)) -> (lshr (- %a), 63)
2812  // Handle SETLT -1 (which is equivalent to SETGE 0).
2813  if (IsRHSNegOne)
2814  return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt);
2815 
2816  if (IsRHSZero) {
2817  if (CmpInGPR == ICGPR_NonExtIn)
2818  return SDValue();
2819  // The upper 32-bits of the register can't be undefined for this sequence.
2820  LHS = signExtendInputIfNeeded(LHS);
2821  RHS = signExtendInputIfNeeded(RHS);
2822  SDValue Neg =
2823  SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, LHS), 0);
2824  return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
2825  Neg, S->getI32Imm(1, dl), S->getI32Imm(63, dl)), 0);
2826  }
2827  // Not a special case (i.e. RHS == 0 or RHS == -1). Handle (%a > %b) as
2828  // (%b < %a) by swapping inputs and falling through.
2829  std::swap(LHS, RHS);
2830  ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
2831  IsRHSZero = RHSConst && RHSConst->isNullValue();
2832  IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1;
2834  }
2835  case ISD::SETLT: {
2836  // (zext (setcc %a, %b, setlt)) -> (lshr (sub %a, %b), 63)
2837  // (zext (setcc %a, 1, setlt)) -> (xor (lshr (- %a), 63), 1)
2838  // (zext (setcc %a, 0, setlt)) -> (lshr %a, 31)
2839  // Handle SETLT 1 (which is equivalent to SETLE 0).
2840  if (IsRHSOne) {
2841  if (CmpInGPR == ICGPR_NonExtIn)
2842  return SDValue();
2843  return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt);
2844  }
2845 
2846  if (IsRHSZero) {
2847  SDValue ShiftOps[] = { LHS, S->getI32Imm(1, dl), S->getI32Imm(31, dl),
2848  S->getI32Imm(31, dl) };
2849  return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
2850  ShiftOps), 0);
2851  }
2852 
2853  if (CmpInGPR == ICGPR_NonExtIn)
2854  return SDValue();
2855  // The upper 32-bits of the register can't be undefined for this sequence.
2856  LHS = signExtendInputIfNeeded(LHS);
2857  RHS = signExtendInputIfNeeded(RHS);
2858  SDValue SUBFNode =
2859  SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, RHS, LHS), 0);
2860  return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
2861  SUBFNode, S->getI64Imm(1, dl),
2862  S->getI64Imm(63, dl)), 0);
2863  }
2864  case ISD::SETUGE:
2865  // (zext (setcc %a, %b, setuge)) -> (xor (lshr (sub %b, %a), 63), 1)
2866  // (zext (setcc %a, %b, setule)) -> (xor (lshr (sub %a, %b), 63), 1)
2867  std::swap(LHS, RHS);
2869  case ISD::SETULE: {
2870  if (CmpInGPR == ICGPR_NonExtIn)
2871  return SDValue();
2872  // The upper 32-bits of the register can't be undefined for this sequence.
2873  LHS = zeroExtendInputIfNeeded(LHS);
2874  RHS = zeroExtendInputIfNeeded(RHS);
2875  SDValue Subtract =
2876  SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, LHS, RHS), 0);
2877  SDValue SrdiNode =
2878  SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
2879  Subtract, S->getI64Imm(1, dl),
2880  S->getI64Imm(63, dl)), 0);
2881  return SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64, SrdiNode,
2882  S->getI32Imm(1, dl)), 0);
2883  }
2884  case ISD::SETUGT:
2885  // (zext (setcc %a, %b, setugt)) -> (lshr (sub %b, %a), 63)
2886  // (zext (setcc %a, %b, setult)) -> (lshr (sub %a, %b), 63)
2887  std::swap(LHS, RHS);
2889  case ISD::SETULT: {
2890  if (CmpInGPR == ICGPR_NonExtIn)
2891  return SDValue();
2892  // The upper 32-bits of the register can't be undefined for this sequence.
2893  LHS = zeroExtendInputIfNeeded(LHS);
2894  RHS = zeroExtendInputIfNeeded(RHS);
2895  SDValue Subtract =
2896  SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, RHS, LHS), 0);
2897  return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
2898  Subtract, S->getI64Imm(1, dl),
2899  S->getI64Imm(63, dl)), 0);
2900  }
2901  }
2902 }
2903 
2904 /// Produces a sign-extended result of comparing two 32-bit values according to
2905 /// the passed condition code.
2906 SDValue
2907 IntegerCompareEliminator::get32BitSExtCompare(SDValue LHS, SDValue RHS,
2908  ISD::CondCode CC,
2909  int64_t RHSValue, SDLoc dl) {
2910  if (CmpInGPR == ICGPR_I64 || CmpInGPR == ICGPR_SextI64 ||
2912  return SDValue();
2913  bool IsRHSZero = RHSValue == 0;
2914  bool IsRHSOne = RHSValue == 1;
2915  bool IsRHSNegOne = RHSValue == -1LL;
2916 
2917  switch (CC) {
2918  default: return SDValue();
2919  case ISD::SETEQ: {
2920  // (sext (setcc %a, %b, seteq)) ->
2921  // (ashr (shl (ctlz (xor %a, %b)), 58), 63)
2922  // (sext (setcc %a, 0, seteq)) ->
2923  // (ashr (shl (ctlz %a), 58), 63)
2924  SDValue CountInput = IsRHSZero ? LHS :
2925  SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
2926  SDValue Cntlzw =
2927  SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, CountInput), 0);
2928  SDValue SHLOps[] = { Cntlzw, S->getI32Imm(27, dl),
2929  S->getI32Imm(5, dl), S->getI32Imm(31, dl) };
2930  SDValue Slwi =
2931  SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, SHLOps), 0);
2932  return SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Slwi), 0);
2933  }
2934  case ISD::SETNE: {
2935  // Bitwise xor the operands, count leading zeros, shift right by 5 bits and
2936  // flip the bit, finally take 2's complement.
2937  // (sext (setcc %a, %b, setne)) ->
2938  // (neg (xor (lshr (ctlz (xor %a, %b)), 5), 1))
2939  // Same as above, but the first xor is not needed.
2940  // (sext (setcc %a, 0, setne)) ->
2941  // (neg (xor (lshr (ctlz %a), 5), 1))
2942  SDValue Xor = IsRHSZero ? LHS :
2943  SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
2944  SDValue Clz =
2945  SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0);
2946  SDValue ShiftOps[] =
2947  { Clz, S->getI32Imm(27, dl), S->getI32Imm(5, dl), S->getI32Imm(31, dl) };
2948  SDValue Shift =
2949  SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, ShiftOps), 0);
2950  SDValue Xori =
2951  SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Shift,
2952  S->getI32Imm(1, dl)), 0);
2953  return SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Xori), 0);
2954  }
2955  case ISD::SETGE: {
2956  // (sext (setcc %a, %b, setge)) -> (add (lshr (sub %a, %b), 63), -1)
2957  // (sext (setcc %a, 0, setge)) -> (ashr (~ %a), 31)
2958  if (IsRHSZero)
2959  return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt);
2960 
2961  // Not a special case (i.e. RHS == 0). Handle (%a >= %b) as (%b <= %a)
2962  // by swapping inputs and falling through.
2963  std::swap(LHS, RHS);
2964  ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
2965  IsRHSZero = RHSConst && RHSConst->isNullValue();
2967  }
2968  case ISD::SETLE: {
2969  if (CmpInGPR == ICGPR_NonExtIn)
2970  return SDValue();
2971  // (sext (setcc %a, %b, setge)) -> (add (lshr (sub %b, %a), 63), -1)
2972  // (sext (setcc %a, 0, setle)) -> (add (lshr (- %a), 63), -1)
2973  if (IsRHSZero)
2974  return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt);
2975 
2976  // The upper 32-bits of the register can't be undefined for this sequence.
2977  LHS = signExtendInputIfNeeded(LHS);
2978  RHS = signExtendInputIfNeeded(RHS);
2979  SDValue SUBFNode =
2980  SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, MVT::Glue,
2981  LHS, RHS), 0);
2982  SDValue Srdi =
2983  SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
2984  SUBFNode, S->getI64Imm(1, dl),
2985  S->getI64Imm(63, dl)), 0);
2986  return SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, Srdi,
2987  S->getI32Imm(-1, dl)), 0);
2988  }
2989  case ISD::SETGT: {
2990  // (sext (setcc %a, %b, setgt)) -> (ashr (sub %b, %a), 63)
2991  // (sext (setcc %a, -1, setgt)) -> (ashr (~ %a), 31)
2992  // (sext (setcc %a, 0, setgt)) -> (ashr (- %a), 63)
2993  if (IsRHSNegOne)
2994  return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt);
2995  if (IsRHSZero) {
2996  if (CmpInGPR == ICGPR_NonExtIn)
2997  return SDValue();
2998  // The upper 32-bits of the register can't be undefined for this sequence.
2999  LHS = signExtendInputIfNeeded(LHS);
3000  RHS = signExtendInputIfNeeded(RHS);
3001  SDValue Neg =
3002  SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, LHS), 0);
3003  return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, Neg,
3004  S->getI64Imm(63, dl)), 0);
3005  }
3006  // Not a special case (i.e. RHS == 0 or RHS == -1). Handle (%a > %b) as
3007  // (%b < %a) by swapping inputs and falling through.
3008  std::swap(LHS, RHS);
3009  ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
3010  IsRHSZero = RHSConst && RHSConst->isNullValue();
3011  IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1;
3013  }
3014  case ISD::SETLT: {
3015  // (sext (setcc %a, %b, setgt)) -> (ashr (sub %a, %b), 63)
3016  // (sext (setcc %a, 1, setgt)) -> (add (lshr (- %a), 63), -1)
3017  // (sext (setcc %a, 0, setgt)) -> (ashr %a, 31)
3018  if (IsRHSOne) {
3019  if (CmpInGPR == ICGPR_NonExtIn)
3020  return SDValue();
3021  return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt);
3022  }
3023  if (IsRHSZero)
3024  return SDValue(CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, LHS,
3025  S->getI32Imm(31, dl)), 0);
3026 
3027  if (CmpInGPR == ICGPR_NonExtIn)
3028  return SDValue();
3029  // The upper 32-bits of the register can't be undefined for this sequence.
3030  LHS = signExtendInputIfNeeded(LHS);
3031  RHS = signExtendInputIfNeeded(RHS);
3032  SDValue SUBFNode =
3033  SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, RHS, LHS), 0);
3034  return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64,
3035  SUBFNode, S->getI64Imm(63, dl)), 0);
3036  }
3037  case ISD::SETUGE:
3038  // (sext (setcc %a, %b, setuge)) -> (add (lshr (sub %a, %b), 63), -1)
3039  // (sext (setcc %a, %b, setule)) -> (add (lshr (sub %b, %a), 63), -1)
3040  std::swap(LHS, RHS);
3042  case ISD::SETULE: {
3043  if (CmpInGPR == ICGPR_NonExtIn)
3044  return SDValue();
3045  // The upper 32-bits of the register can't be undefined for this sequence.
3046  LHS = zeroExtendInputIfNeeded(LHS);
3047  RHS = zeroExtendInputIfNeeded(RHS);
3048  SDValue Subtract =
3049  SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, LHS, RHS), 0);
3050  SDValue Shift =
3051  SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Subtract,
3052  S->getI32Imm(1, dl), S->getI32Imm(63,dl)),
3053  0);
3054  return SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, Shift,
3055  S->getI32Imm(-1, dl)), 0);
3056  }
3057  case ISD::SETUGT:
3058  // (sext (setcc %a, %b, setugt)) -> (ashr (sub %b, %a), 63)
3059  // (sext (setcc %a, %b, setugt)) -> (ashr (sub %a, %b), 63)
3060  std::swap(LHS, RHS);
3062  case ISD::SETULT: {
3063  if (CmpInGPR == ICGPR_NonExtIn)
3064  return SDValue();
3065  // The upper 32-bits of the register can't be undefined for this sequence.
3066  LHS = zeroExtendInputIfNeeded(LHS);
3067  RHS = zeroExtendInputIfNeeded(RHS);
3068  SDValue Subtract =
3069  SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, RHS, LHS), 0);
3070  return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64,
3071  Subtract, S->getI64Imm(63, dl)), 0);
3072  }
3073  }
3074 }
3075 
3076 /// Produces a zero-extended result of comparing two 64-bit values according to
3077 /// the passed condition code.
3078 SDValue
3079 IntegerCompareEliminator::get64BitZExtCompare(SDValue LHS, SDValue RHS,
3080  ISD::CondCode CC,
3081  int64_t RHSValue, SDLoc dl) {
3082  if (CmpInGPR == ICGPR_I32 || CmpInGPR == ICGPR_SextI32 ||
3084  return SDValue();
3085  bool IsRHSZero = RHSValue == 0;
3086  bool IsRHSOne = RHSValue == 1;
3087  bool IsRHSNegOne = RHSValue == -1LL;
3088  switch (CC) {
3089  default: return SDValue();
3090  case ISD::SETEQ: {
3091  // (zext (setcc %a, %b, seteq)) -> (lshr (ctlz (xor %a, %b)), 6)
3092  // (zext (setcc %a, 0, seteq)) -> (lshr (ctlz %a), 6)
3093  SDValue Xor = IsRHSZero ? LHS :
3094  SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0);
3095  SDValue Clz =
3096  SDValue(CurDAG->getMachineNode(PPC::CNTLZD, dl, MVT::i64, Xor), 0);
3097  return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Clz,
3098  S->getI64Imm(58, dl),
3099  S->getI64Imm(63, dl)), 0);
3100  }
3101  case ISD::SETNE: {
3102  // {addc.reg, addc.CA} = (addcarry (xor %a, %b), -1)
3103  // (zext (setcc %a, %b, setne)) -> (sube addc.reg, addc.reg, addc.CA)
3104  // {addcz.reg, addcz.CA} = (addcarry %a, -1)
3105  // (zext (setcc %a, 0, setne)) -> (sube addcz.reg, addcz.reg, addcz.CA)
3106  SDValue Xor = IsRHSZero ? LHS :
3107  SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0);
3108  SDValue AC =
3109  SDValue(CurDAG->getMachineNode(PPC::ADDIC8, dl, MVT::i64, MVT::Glue,
3110  Xor, S->getI32Imm(~0U, dl)), 0);
3111  return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, AC,
3112  Xor, AC.getValue(1)), 0);
3113  }
3114  case ISD::SETGE: {
3115  // {subc.reg, subc.CA} = (subcarry %a, %b)
3116  // (zext (setcc %a, %b, setge)) ->
3117  // (adde (lshr %b, 63), (ashr %a, 63), subc.CA)
3118  // (zext (setcc %a, 0, setge)) -> (lshr (~ %a), 63)
3119  if (IsRHSZero)
3120  return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt);
3121  std::swap(LHS, RHS);
3122  ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
3123  IsRHSZero = RHSConst && RHSConst->isNullValue();
3125  }
3126  case ISD::SETLE: {
3127  // {subc.reg, subc.CA} = (subcarry %b, %a)
3128  // (zext (setcc %a, %b, setge)) ->
3129  // (adde (lshr %a, 63), (ashr %b, 63), subc.CA)
3130  // (zext (setcc %a, 0, setge)) -> (lshr (or %a, (add %a, -1)), 63)
3131  if (IsRHSZero)
3132  return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt);
3133  SDValue ShiftL =
3134  SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, LHS,
3135  S->getI64Imm(1, dl),
3136  S->getI64Imm(63, dl)), 0);
3137  SDValue ShiftR =
3138  SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, RHS,
3139  S->getI64Imm(63, dl)), 0);
3140  SDValue SubtractCarry =
3141  SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
3142  LHS, RHS), 1);
3143  return SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64, MVT::Glue,
3144  ShiftR, ShiftL, SubtractCarry), 0);
3145  }
3146  case ISD::SETGT: {
3147  // {subc.reg, subc.CA} = (subcarry %b, %a)
3148  // (zext (setcc %a, %b, setgt)) ->
3149  // (xor (adde (lshr %a, 63), (ashr %b, 63), subc.CA), 1)
3150  // (zext (setcc %a, 0, setgt)) -> (lshr (nor (add %a, -1), %a), 63)
3151  if (IsRHSNegOne)
3152  return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt);
3153  if (IsRHSZero) {
3154  SDValue Addi =
3155  SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, LHS,
3156  S->getI64Imm(~0ULL, dl)), 0);
3157  SDValue Nor =
3158  SDValue(CurDAG->getMachineNode(PPC::NOR8, dl, MVT::i64, Addi, LHS), 0);
3159  return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Nor,
3160  S->getI64Imm(1, dl),
3161  S->getI64Imm(63, dl)), 0);
3162  }
3163  std::swap(LHS, RHS);
3164  ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
3165  IsRHSZero = RHSConst && RHSConst->isNullValue();
3166  IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1;
3168  }
3169  case ISD::SETLT: {
3170  // {subc.reg, subc.CA} = (subcarry %a, %b)
3171  // (zext (setcc %a, %b, setlt)) ->
3172  // (xor (adde (lshr %b, 63), (ashr %a, 63), subc.CA), 1)
3173  // (zext (setcc %a, 0, setlt)) -> (lshr %a, 63)
3174  if (IsRHSOne)
3175  return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt);
3176  if (IsRHSZero)
3177  return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, LHS,
3178  S->getI64Imm(1, dl),
3179  S->getI64Imm(63, dl)), 0);
3180  SDValue SRADINode =
3181  SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64,
3182  LHS, S->getI64Imm(63, dl)), 0);
3183  SDValue SRDINode =
3184  SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
3185  RHS, S->getI64Imm(1, dl),
3186  S->getI64Imm(63, dl)), 0);
3187  SDValue SUBFC8Carry =
3188  SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
3189  RHS, LHS), 1);
3190  SDValue ADDE8Node =
3191  SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64, MVT::Glue,
3192  SRDINode, SRADINode, SUBFC8Carry), 0);
3193  return SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64,
3194  ADDE8Node, S->getI64Imm(1, dl)), 0);
3195  }
3196  case ISD::SETUGE:
3197  // {subc.reg, subc.CA} = (subcarry %a, %b)
3198  // (zext (setcc %a, %b, setuge)) -> (add (sube %b, %b, subc.CA), 1)
3199  std::swap(LHS, RHS);
3201  case ISD::SETULE: {
3202  // {subc.reg, subc.CA} = (subcarry %b, %a)
3203  // (zext (setcc %a, %b, setule)) -> (add (sube %a, %a, subc.CA), 1)
3204  SDValue SUBFC8Carry =
3205  SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
3206  LHS, RHS), 1);
3207  SDValue SUBFE8Node =
3208  SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, MVT::Glue,
3209  LHS, LHS, SUBFC8Carry), 0);
3210  return SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64,
3211  SUBFE8Node, S->getI64Imm(1, dl)), 0);
3212  }
3213  case ISD::SETUGT:
3214  // {subc.reg, subc.CA} = (subcarry %b, %a)
3215  // (zext (setcc %a, %b, setugt)) -> -(sube %b, %b, subc.CA)
3216  std::swap(LHS, RHS);
3218  case ISD::SETULT: {
3219  // {subc.reg, subc.CA} = (subcarry %a, %b)
3220  // (zext (setcc %a, %b, setult)) -> -(sube %a, %a, subc.CA)
3221  SDValue SubtractCarry =
3222  SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
3223  RHS, LHS), 1);
3224  SDValue ExtSub =
3225  SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64,
3226  LHS, LHS, SubtractCarry), 0);
3227  return SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64,
3228  ExtSub), 0);
3229  }
3230  }
3231 }
3232 
3233 /// Produces a sign-extended result of comparing two 64-bit values according to
3234 /// the passed condition code.
3235 SDValue
3236 IntegerCompareEliminator::get64BitSExtCompare(SDValue LHS, SDValue RHS,
3237  ISD::CondCode CC,
3238  int64_t RHSValue, SDLoc dl) {
3239  if (CmpInGPR == ICGPR_I32 || CmpInGPR == ICGPR_SextI32 ||
3241  return SDValue();
3242  bool IsRHSZero = RHSValue == 0;
3243  bool IsRHSOne = RHSValue == 1;
3244  bool IsRHSNegOne = RHSValue == -1LL;
3245  switch (CC) {
3246  default: return SDValue();
3247  case ISD::SETEQ: {
3248  // {addc.reg, addc.CA} = (addcarry (xor %a, %b), -1)
3249  // (sext (setcc %a, %b, seteq)) -> (sube addc.reg, addc.reg, addc.CA)
3250  // {addcz.reg, addcz.CA} = (addcarry %a, -1)
3251  // (sext (setcc %a, 0, seteq)) -> (sube addcz.reg, addcz.reg, addcz.CA)
3252  SDValue AddInput = IsRHSZero ? LHS :
3253  SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0);
3254  SDValue Addic =
3255  SDValue(CurDAG->getMachineNode(PPC::ADDIC8, dl, MVT::i64, MVT::Glue,
3256  AddInput, S->getI32Imm(~0U, dl)), 0);
3257  return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, Addic,
3258  Addic, Addic.getValue(1)), 0);
3259  }
3260  case ISD::SETNE: {
3261  // {subfc.reg, subfc.CA} = (subcarry 0, (xor %a, %b))
3262  // (sext (setcc %a, %b, setne)) -> (sube subfc.reg, subfc.reg, subfc.CA)
3263  // {subfcz.reg, subfcz.CA} = (subcarry 0, %a)
3264  // (sext (setcc %a, 0, setne)) -> (sube subfcz.reg, subfcz.reg, subfcz.CA)
3265  SDValue Xor = IsRHSZero ? LHS :
3266  SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0);
3267  SDValue SC =
3268  SDValue(CurDAG->getMachineNode(PPC::SUBFIC8, dl, MVT::i64, MVT::Glue,
3269  Xor, S->getI32Imm(0, dl)), 0);
3270  return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, SC,
3271  SC, SC.getValue(1)), 0);
3272  }
3273  case ISD::SETGE: {
3274  // {subc.reg, subc.CA} = (subcarry %a, %b)
3275  // (zext (setcc %a, %b, setge)) ->
3276  // (- (adde (lshr %b, 63), (ashr %a, 63), subc.CA))
3277  // (zext (setcc %a, 0, setge)) -> (~ (ashr %a, 63))
3278  if (IsRHSZero)
3279  return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt);
3280  std::swap(LHS, RHS);
3281  ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
3282  IsRHSZero = RHSConst && RHSConst->isNullValue();
3284  }
3285  case ISD::SETLE: {
3286  // {subc.reg, subc.CA} = (subcarry %b, %a)
3287  // (zext (setcc %a, %b, setge)) ->
3288  // (- (adde (lshr %a, 63), (ashr %b, 63), subc.CA))
3289  // (zext (setcc %a, 0, setge)) -> (ashr (or %a, (add %a, -1)), 63)
3290  if (IsRHSZero)
3291  return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt);
3292  SDValue ShiftR =
3293  SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, RHS,
3294  S->getI64Imm(63, dl)), 0);
3295  SDValue ShiftL =
3296  SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, LHS,
3297  S->getI64Imm(1, dl),
3298  S->getI64Imm(63, dl)), 0);
3299  SDValue SubtractCarry =
3300  SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
3301  LHS, RHS), 1);
3302  SDValue Adde =
3303  SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64, MVT::Glue,
3304  ShiftR, ShiftL, SubtractCarry), 0);
3305  return SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, Adde), 0);
3306  }
3307  case ISD::SETGT: {
3308  // {subc.reg, subc.CA} = (subcarry %b, %a)
3309  // (zext (setcc %a, %b, setgt)) ->
3310  // -(xor (adde (lshr %a, 63), (ashr %b, 63), subc.CA), 1)
3311  // (zext (setcc %a, 0, setgt)) -> (ashr (nor (add %a, -1), %a), 63)
3312  if (IsRHSNegOne)
3313  return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt);
3314  if (IsRHSZero) {
3315  SDValue Add =
3316  SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, LHS,
3317  S->getI64Imm(-1, dl)), 0);
3318  SDValue Nor =
3319  SDValue(CurDAG->getMachineNode(PPC::NOR8, dl, MVT::i64, Add, LHS), 0);
3320  return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, Nor,
3321  S->getI64Imm(63, dl)), 0);
3322  }
3323  std::swap(LHS, RHS);
3324  ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
3325  IsRHSZero = RHSConst && RHSConst->isNullValue();
3326  IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1;
3328  }
3329  case ISD::SETLT: {
3330  // {subc.reg, subc.CA} = (subcarry %a, %b)
3331  // (zext (setcc %a, %b, setlt)) ->
3332  // -(xor (adde (lshr %b, 63), (ashr %a, 63), subc.CA), 1)
3333  // (zext (setcc %a, 0, setlt)) -> (ashr %a, 63)
3334  if (IsRHSOne)
3335  return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt);
3336  if (IsRHSZero) {
3337  return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, LHS,
3338  S->getI64Imm(63, dl)), 0);
3339  }
3340  SDValue SRADINode =
3341  SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64,
3342  LHS, S->getI64Imm(63, dl)), 0);
3343  SDValue SRDINode =
3344  SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
3345  RHS, S->getI64Imm(1, dl),
3346  S->getI64Imm(63, dl)), 0);
3347  SDValue SUBFC8Carry =
3348  SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
3349  RHS, LHS), 1);
3350  SDValue ADDE8Node =
3351  SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64,
3352  SRDINode, SRADINode, SUBFC8Carry), 0);
3353  SDValue XORI8Node =
3354  SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64,
3355  ADDE8Node, S->getI64Imm(1, dl)), 0);
3356  return SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64,
3357  XORI8Node), 0);
3358  }
3359  case ISD::SETUGE:
3360  // {subc.reg, subc.CA} = (subcarry %a, %b)
3361  // (sext (setcc %a, %b, setuge)) -> ~(sube %b, %b, subc.CA)
3362  std::swap(LHS, RHS);
3364  case ISD::SETULE: {
3365  // {subc.reg, subc.CA} = (subcarry %b, %a)
3366  // (sext (setcc %a, %b, setule)) -> ~(sube %a, %a, subc.CA)
3367  SDValue SubtractCarry =
3368  SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
3369  LHS, RHS), 1);
3370  SDValue ExtSub =
3371  SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, MVT::Glue, LHS,
3372  LHS, SubtractCarry), 0);
3373  return SDValue(CurDAG->getMachineNode(PPC::NOR8, dl, MVT::i64,
3374  ExtSub, ExtSub), 0);
3375  }
3376  case ISD::SETUGT:
3377  // {subc.reg, subc.CA} = (subcarry %b, %a)
3378  // (sext (setcc %a, %b, setugt)) -> (sube %b, %b, subc.CA)
3379  std::swap(LHS, RHS);
3381  case ISD::SETULT: {
3382  // {subc.reg, subc.CA} = (subcarry %a, %b)
3383  // (sext (setcc %a, %b, setult)) -> (sube %a, %a, subc.CA)
3384  SDValue SubCarry =
3385  SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
3386  RHS, LHS), 1);
3387  return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64,
3388  LHS, LHS, SubCarry), 0);
3389  }
3390  }
3391 }
3392 
3393 /// Do all uses of this SDValue need the result in a GPR?
3394 /// This is meant to be used on values that have type i1 since
3395 /// it is somewhat meaningless to ask if values of other types
3396 /// should be kept in GPR's.
3397 static bool allUsesExtend(SDValue Compare, SelectionDAG *CurDAG) {
3398  assert(Compare.getOpcode() == ISD::SETCC &&
3399  "An ISD::SETCC node required here.");
3400 
3401  // For values that have a single use, the caller should obviously already have
3402  // checked if that use is an extending use. We check the other uses here.
3403  if (Compare.hasOneUse())
3404  return true;
3405  // We want the value in a GPR if it is being extended, used for a select, or
3406  // used in logical operations.
3407  for (auto CompareUse : Compare.getNode()->uses())
3408  if (CompareUse->getOpcode() != ISD::SIGN_EXTEND &&
3409  CompareUse->getOpcode() != ISD::ZERO_EXTEND &&
3410  CompareUse->getOpcode() != ISD::SELECT &&
3411  !isLogicOp(CompareUse->getOpcode())) {
3412  OmittedForNonExtendUses++;
3413  return false;
3414  }
3415  return true;
3416 }
3417 
3418 /// Returns an equivalent of a SETCC node but with the result the same width as
3419 /// the inputs. This can also be used for SELECT_CC if either the true or false
3420 /// values is a power of two while the other is zero.
3421 SDValue IntegerCompareEliminator::getSETCCInGPR(SDValue Compare,
3422  SetccInGPROpts ConvOpts) {
3423  assert((Compare.getOpcode() == ISD::SETCC ||
3424  Compare.getOpcode() == ISD::SELECT_CC) &&
3425  "An ISD::SETCC node required here.");
3426 
3427  // Don't convert this comparison to a GPR sequence because there are uses
3428  // of the i1 result (i.e. uses that require the result in the CR).
3429  if ((Compare.getOpcode() == ISD::SETCC) && !allUsesExtend(Compare, CurDAG))
3430  return SDValue();
3431 
3432  SDValue LHS = Compare.getOperand(0);
3433  SDValue RHS = Compare.getOperand(1);
3434 
3435  // The condition code is operand 2 for SETCC and operand 4 for SELECT_CC.
3436  int CCOpNum = Compare.getOpcode() == ISD::SELECT_CC ? 4 : 2;
3437  ISD::CondCode CC =
3438  cast<CondCodeSDNode>(Compare.getOperand(CCOpNum))->get();
3439  EVT InputVT = LHS.getValueType();
3440  if (InputVT != MVT::i32 && InputVT != MVT::i64)
3441  return SDValue();
3442 
3443  if (ConvOpts == SetccInGPROpts::ZExtInvert ||
3444  ConvOpts == SetccInGPROpts::SExtInvert)
3445  CC = ISD::getSetCCInverse(CC, true);
3446 
3447  bool Inputs32Bit = InputVT == MVT::i32;
3448 
3449  SDLoc dl(Compare);
3450  ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
3451  int64_t RHSValue = RHSConst ? RHSConst->getSExtValue() : INT64_MAX;
3452  bool IsSext = ConvOpts == SetccInGPROpts::SExtOrig ||
3453  ConvOpts == SetccInGPROpts::SExtInvert;
3454 
3455  if (IsSext && Inputs32Bit)
3456  return get32BitSExtCompare(LHS, RHS, CC, RHSValue, dl);
3457  else if (Inputs32Bit)
3458  return get32BitZExtCompare(LHS, RHS, CC, RHSValue, dl);
3459  else if (IsSext)
3460  return get64BitSExtCompare(LHS, RHS, CC, RHSValue, dl);
3461  return get64BitZExtCompare(LHS, RHS, CC, RHSValue, dl);
3462 }
3463 
3464 } // end anonymous namespace
3465 
3466 bool PPCDAGToDAGISel::tryIntCompareInGPR(SDNode *N) {
3467  if (N->getValueType(0) != MVT::i32 &&
3468  N->getValueType(0) != MVT::i64)
3469  return false;
3470 
3471  // This optimization will emit code that assumes 64-bit registers
3472  // so we don't want to run it in 32-bit mode. Also don't run it
3473  // on functions that are not to be optimized.
3474  if (TM.getOptLevel() == CodeGenOpt::None || !TM.isPPC64())
3475  return false;
3476 
3477  switch (N->getOpcode()) {
3478  default: break;
3479  case ISD::ZERO_EXTEND:
3480  case ISD::SIGN_EXTEND:
3481  case ISD::AND:
3482  case ISD::OR:
3483  case ISD::XOR: {
3484  IntegerCompareEliminator ICmpElim(CurDAG, this);
3485  if (SDNode *New = ICmpElim.Select(N)) {
3486  ReplaceNode(N, New);
3487  return true;
3488  }
3489  }
3490  }
3491  return false;
3492 }
3493 
3494 bool PPCDAGToDAGISel::tryBitPermutation(SDNode *N) {
3495  if (N->getValueType(0) != MVT::i32 &&
3496  N->getValueType(0) != MVT::i64)
3497  return false;
3498 
3499  if (!UseBitPermRewriter)
3500  return false;
3501 
3502  switch (N->getOpcode()) {
3503  default: break;
3504  case ISD::ROTL:
3505  case ISD::SHL:
3506  case ISD::SRL:
3507  case ISD::AND:
3508  case ISD::OR: {
3509  BitPermutationSelector BPS(CurDAG);
3510  if (SDNode *New = BPS.Select(N)) {
3511  ReplaceNode(N, New);
3512  return true;
3513  }
3514  return false;
3515  }
3516  }
3517 
3518  return false;
3519 }
3520 
3521 /// SelectCC - Select a comparison of the specified values with the specified
3522 /// condition code, returning the CR# of the expression.
3523 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
3524  const SDLoc &dl) {
3525  // Always select the LHS.
3526  unsigned Opc;
3527 
3528  if (LHS.getValueType() == MVT::i32) {
3529  unsigned Imm;
3530  if (CC == ISD::SETEQ || CC == ISD::SETNE) {
3531  if (isInt32Immediate(RHS, Imm)) {
3532  // SETEQ/SETNE comparison with 16-bit immediate, fold it.
3533  if (isUInt<16>(Imm))
3534  return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
3535  getI32Imm(Imm & 0xFFFF, dl)),
3536  0);
3537  // If this is a 16-bit signed immediate, fold it.
3538  if (isInt<16>((int)Imm))
3539  return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
3540  getI32Imm(Imm & 0xFFFF, dl)),
3541  0);
3542 
3543  // For non-equality comparisons, the default code would materialize the
3544  // constant, then compare against it, like this:
3545  // lis r2, 4660
3546  // ori r2, r2, 22136
3547  // cmpw cr0, r3, r2
3548  // Since we are just comparing for equality, we can emit this instead:
3549  // xoris r0,r3,0x1234
3550  // cmplwi cr0,r0,0x5678
3551  // beq cr0,L6
3552  SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS,
3553  getI32Imm(Imm >> 16, dl)), 0);
3554  return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor,
3555  getI32Imm(Imm & 0xFFFF, dl)), 0);
3556  }
3557  Opc = PPC::CMPLW;
3558  } else if (ISD::isUnsignedIntSetCC(CC)) {
3559  if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm))
3560  return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
3561  getI32Imm(Imm & 0xFFFF, dl)), 0);
3562  Opc = PPC::CMPLW;
3563  } else {
3564  int16_t SImm;
3565  if (isIntS16Immediate(RHS, SImm))
3566  return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
3567  getI32Imm((int)SImm & 0xFFFF,
3568  dl)),
3569  0);
3570  Opc = PPC::CMPW;
3571  }
3572  } else if (LHS.getValueType() == MVT::i64) {
3573  uint64_t Imm;
3574  if (CC == ISD::SETEQ || CC == ISD::SETNE) {
3575  if (isInt64Immediate(RHS.getNode(), Imm)) {
3576  // SETEQ/SETNE comparison with 16-bit immediate, fold it.
3577  if (isUInt<16>(Imm))
3578  return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
3579  getI32Imm(Imm & 0xFFFF, dl)),
3580  0);
3581  // If this is a 16-bit signed immediate, fold it.
3582  if (isInt<16>(Imm))
3583  return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
3584  getI32Imm(Imm & 0xFFFF, dl)),
3585  0);
3586 
3587  // For non-equality comparisons, the default code would materialize the
3588  // constant, then compare against it, like this:
3589  // lis r2, 4660
3590  // ori r2, r2, 22136
3591  // cmpd cr0, r3, r2
3592  // Since we are just comparing for equality, we can emit this instead:
3593  // xoris r0,r3,0x1234
3594  // cmpldi cr0,r0,0x5678
3595  // beq cr0,L6
3596  if (isUInt<32>(Imm)) {
3597  SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS,
3598  getI64Imm(Imm >> 16, dl)), 0);
3599  return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor,
3600  getI64Imm(Imm & 0xFFFF, dl)),
3601  0);
3602  }
3603  }
3604  Opc = PPC::CMPLD;
3605  } else if (ISD::isUnsignedIntSetCC(CC)) {
3606  if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm))
3607  return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
3608  getI64Imm(Imm & 0xFFFF, dl)), 0);
3609  Opc = PPC::CMPLD;
3610  } else {
3611  int16_t SImm;
3612  if (isIntS16Immediate(RHS, SImm))
3613  return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
3614  getI64Imm(SImm & 0xFFFF, dl)),
3615  0);
3616  Opc = PPC::CMPD;
3617  }
3618  } else if (LHS.getValueType() == MVT::f32) {
3619  Opc = PPC::FCMPUS;
3620  } else if (LHS.getValueType() == MVT::f64) {
3621  Opc = PPCSubTarget->hasVSX() ? PPC::XSCMPUDP : PPC::FCMPUD;
3622  } else {
3623  assert(LHS.getValueType() == MVT::f128 && "Unknown vt!");
3624  assert(PPCSubTarget->hasVSX() && "__float128 requires VSX");
3625  Opc = PPC::XSCMPUQP;
3626  }
3627  return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0);
3628 }
3629 
3631  switch (CC) {
3632  case ISD::SETUEQ:
3633  case ISD::SETONE:
3634  case ISD::SETOLE:
3635  case ISD::SETOGE:
3636  llvm_unreachable("Should be lowered by legalize!");
3637  default: llvm_unreachable("Unknown condition!");
3638  case ISD::SETOEQ:
3639  case ISD::SETEQ: return PPC::PRED_EQ;
3640  case ISD::SETUNE:
3641  case ISD::SETNE: return PPC::PRED_NE;
3642  case ISD::SETOLT:
3643  case ISD::SETLT: return PPC::PRED_LT;
3644  case ISD::SETULE:
3645  case ISD::SETLE: return PPC::PRED_LE;
3646  case ISD::SETOGT:
3647  case ISD::SETGT: return PPC::PRED_GT;
3648  case ISD::SETUGE:
3649  case ISD::SETGE: return PPC::PRED_GE;
3650  case ISD::SETO: return PPC::PRED_NU;
3651  case ISD::SETUO: return PPC::PRED_UN;
3652  // These two are invalid for floating point. Assume we have int.
3653  case ISD::SETULT: return PPC::PRED_LT;
3654  case ISD::SETUGT: return PPC::PRED_GT;
3655  }
3656 }
3657 
3658 /// getCRIdxForSetCC - Return the index of the condition register field
3659 /// associated with the SetCC condition, and whether or not the field is
3660 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
3661 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) {
3662  Invert = false;
3663  switch (CC) {
3664  default: llvm_unreachable("Unknown condition!");
3665  case ISD::SETOLT:
3666  case ISD::SETLT: return 0; // Bit #0 = SETOLT
3667  case ISD::SETOGT:
3668  case ISD::SETGT: return 1; // Bit #1 = SETOGT
3669  case ISD::SETOEQ:
3670  case ISD::SETEQ: return 2; // Bit #2 = SETOEQ
3671  case ISD::SETUO: return 3; // Bit #3 = SETUO
3672  case ISD::SETUGE:
3673  case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
3674  case ISD::SETULE:
3675  case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
3676  case ISD::SETUNE:
3677  case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE
3678  case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO
3679  case ISD::SETUEQ:
3680  case ISD::SETOGE:
3681  case ISD::SETOLE:
3682  case ISD::SETONE:
3683  llvm_unreachable("Invalid branch code: should be expanded by legalize");
3684  // These are invalid for floating point. Assume integer.
3685  case ISD::SETULT: return 0;
3686  case ISD::SETUGT: return 1;
3687  }
3688 }
3689 
3690 // getVCmpInst: return the vector compare instruction for the specified
3691 // vector type and condition code. Since this is for altivec specific code,
3692 // only support the altivec types (v16i8, v8i16, v4i32, v2i64, and v4f32).
3693 static unsigned int getVCmpInst(MVT VecVT, ISD::CondCode CC,
3694  bool HasVSX, bool &Swap, bool &Negate) {
3695  Swap = false;
3696  Negate = false;
3697 
3698  if (VecVT.isFloatingPoint()) {
3699  /* Handle some cases by swapping input operands. */
3700  switch (CC) {
3701  case ISD::SETLE: CC = ISD::SETGE; Swap = true; break;
3702  case ISD::SETLT: CC = ISD::SETGT; Swap = true; break;
3703  case ISD::SETOLE: CC = ISD::SETOGE; Swap = true; break;
3704  case ISD::SETOLT: CC = ISD::SETOGT; Swap = true; break;
3705  case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break;
3706  case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break;
3707  default: break;
3708  }
3709  /* Handle some cases by negating the result. */
3710  switch (CC) {
3711  case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break;
3712  case ISD::SETUNE: CC = ISD::SETOEQ; Negate = true; break;
3713  case ISD::SETULE: CC = ISD::SETOGT; Negate = true; break;
3714  case ISD::SETULT: CC = ISD::SETOGE; Negate = true; break;
3715  default: break;
3716  }
3717  /* We have instructions implementing the remaining cases. */
3718  switch (CC) {
3719  case ISD::SETEQ:
3720  case ISD::SETOEQ:
3721  if (VecVT == MVT::v4f32)
3722  return HasVSX ? PPC::XVCMPEQSP : PPC::VCMPEQFP;
3723  else if (VecVT == MVT::v2f64)
3724  return PPC::XVCMPEQDP;
3725  break;
3726  case ISD::SETGT:
3727  case ISD::SETOGT:
3728  if (VecVT == MVT::v4f32)
3729  return HasVSX ? PPC::XVCMPGTSP : PPC::VCMPGTFP;
3730  else if (VecVT == MVT::v2f64)
3731  return PPC::XVCMPGTDP;
3732  break;
3733  case ISD::SETGE:
3734  case ISD::SETOGE:
3735  if (VecVT == MVT::v4f32)
3736  return HasVSX ? PPC::XVCMPGESP : PPC::VCMPGEFP;
3737  else if (VecVT == MVT::v2f64)
3738  return PPC::XVCMPGEDP;
3739  break;
3740  default:
3741  break;
3742  }
3743  llvm_unreachable("Invalid floating-point vector compare condition");
3744  } else {
3745  /* Handle some cases by swapping input operands. */
3746  switch (CC) {
3747  case ISD::SETGE: CC = ISD::SETLE; Swap = true; break;
3748  case ISD::SETLT: CC = ISD::SETGT; Swap = true; break;
3749  case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break;
3750  case ISD::SETULT: CC = ISD::SETUGT; Swap = true; break;
3751  default: break;
3752  }
3753  /* Handle some cases by negating the result. */
3754  switch (CC) {
3755  case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break;
3756  case ISD::SETUNE: CC = ISD::SETUEQ; Negate = true; break;
3757  case ISD::SETLE: CC = ISD::SETGT; Negate = true; break;
3758  case ISD::SETULE: CC = ISD::SETUGT; Negate = true; break;
3759  default: break;
3760  }
3761  /* We have instructions implementing the remaining cases. */
3762  switch (CC) {
3763  case ISD::SETEQ:
3764  case ISD::SETUEQ:
3765  if (VecVT == MVT::v16i8)
3766  return PPC::VCMPEQUB;
3767  else if (VecVT == MVT::v8i16)
3768  return PPC::VCMPEQUH;
3769  else if (VecVT == MVT::v4i32)
3770  return PPC::VCMPEQUW;
3771  else if (VecVT == MVT::v2i64)
3772  return PPC::VCMPEQUD;
3773  break;
3774  case ISD::SETGT:
3775  if (VecVT == MVT::v16i8)
3776  return PPC::VCMPGTSB;
3777  else if (VecVT == MVT::v8i16)
3778  return PPC::VCMPGTSH;
3779  else if (VecVT == MVT::v4i32)
3780  return PPC::VCMPGTSW;
3781  else if (VecVT == MVT::v2i64)
3782  return PPC::VCMPGTSD;
3783  break;
3784  case ISD::SETUGT:
3785  if (VecVT == MVT::v16i8)
3786  return PPC::VCMPGTUB;
3787  else if (VecVT == MVT::v8i16)
3788  return PPC::VCMPGTUH;
3789  else if (VecVT == MVT::v4i32)
3790  return PPC::VCMPGTUW;
3791  else if (VecVT == MVT::v2i64)
3792  return PPC::VCMPGTUD;
3793  break;
3794  default:
3795  break;
3796  }
3797  llvm_unreachable("Invalid integer vector compare condition");
3798  }
3799 }
3800 
3801 bool PPCDAGToDAGISel::trySETCC(SDNode *N) {
3802  SDLoc dl(N);
3803  unsigned Imm;
3804  ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
3805  EVT PtrVT =
3806  CurDAG->getTargetLoweringInfo().getPointerTy(CurDAG->getDataLayout());
3807  bool isPPC64 = (PtrVT == MVT::i64);
3808 
3809  if (!PPCSubTarget->useCRBits() &&
3810  isInt32Immediate(N->getOperand(1), Imm)) {
3811  // We can codegen setcc op, imm very efficiently compared to a brcond.
3812  // Check for those cases here.
3813  // setcc op, 0
3814  if (Imm == 0) {
3815  SDValue Op = N->getOperand(0);
3816  switch (CC) {
3817  default: break;
3818  case ISD::SETEQ: {
3819  Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
3820  SDValue Ops[] = { Op, getI32Imm(27, dl), getI32Imm(5, dl),
3821  getI32Imm(31, dl) };
3822  CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
3823  return true;
3824  }
3825  case ISD::SETNE: {
3826  if (isPPC64) break;
3827  SDValue AD =
3828  SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
3829  Op, getI32Imm(~0U, dl)), 0);
3830  CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1));
3831  return true;
3832  }
3833  case ISD::SETLT: {
3834  SDValue Ops[] = { Op, getI32Imm(1, dl), getI32Imm(31, dl),
3835  getI32Imm(31, dl) };
3836  CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
3837  return true;
3838  }
3839  case ISD::SETGT: {
3840  SDValue T =
3841  SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0);
3842  T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
3843  SDValue Ops[] = { T, getI32Imm(1, dl), getI32Imm(31, dl),
3844  getI32Imm(31, dl) };
3845  CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
3846  return true;
3847  }
3848  }
3849  } else if (Imm == ~0U) { // setcc op, -1
3850  SDValue Op = N->getOperand(0);
3851  switch (CC) {
3852  default: break;
3853  case ISD::SETEQ:
3854  if (isPPC64) break;
3855  Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
3856  Op, getI32Imm(1, dl)), 0);
3857  CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
3858  SDValue(CurDAG->getMachineNode(PPC::LI, dl,
3859  MVT::i32,
3860  getI32Imm(0, dl)),
3861  0), Op.getValue(1));
3862  return true;
3863  case ISD::SETNE: {
3864  if (isPPC64) break;
3865  Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
3866  SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
3867  Op, getI32Imm(~0U, dl));
3868  CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0), Op,
3869  SDValue(AD, 1));
3870  return true;
3871  }
3872  case ISD::SETLT: {
3873  SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op,
3874  getI32Imm(1, dl)), 0);
3875  SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD,
3876  Op), 0);
3877  SDValue Ops[] = { AN, getI32Imm(1, dl), getI32Imm(31, dl),
3878  getI32Imm(31, dl) };
3879  CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
3880  return true;
3881  }
3882  case ISD::SETGT: {
3883  SDValue Ops[] = { Op, getI32Imm(1, dl), getI32Imm(31, dl),
3884  getI32Imm(31, dl) };
3885  Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
3886  CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1, dl));
3887  return true;
3888  }
3889  }
3890  }
3891  }
3892 
3893  SDValue LHS = N->getOperand(0);
3894  SDValue RHS = N->getOperand(1);
3895 
3896  // Altivec Vector compare instructions do not set any CR register by default and
3897  // vector compare operations return the same type as the operands.
3898  if (LHS.getValueType().isVector()) {
3899  if (PPCSubTarget->hasQPX())
3900  return false;
3901 
3902  EVT VecVT = LHS.getValueType();
3903  bool Swap, Negate;
3904  unsigned int VCmpInst = getVCmpInst(VecVT.getSimpleVT(), CC,
3905  PPCSubTarget->hasVSX(), Swap, Negate);
3906  if (Swap)
3907  std::swap(LHS, RHS);
3908 
3909  EVT ResVT = VecVT.changeVectorElementTypeToInteger();
3910  if (Negate) {
3911  SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, ResVT, LHS, RHS), 0);
3912  CurDAG->SelectNodeTo(N, PPCSubTarget->hasVSX() ? PPC::XXLNOR : PPC::VNOR,
3913  ResVT, VCmp, VCmp);
3914  return true;
3915  }
3916 
3917  CurDAG->SelectNodeTo(N, VCmpInst, ResVT, LHS, RHS);
3918  return true;
3919  }
3920 
3921  if (PPCSubTarget->useCRBits())
3922  return false;
3923 
3924  bool Inv;
3925  unsigned Idx = getCRIdxForSetCC(CC, Inv);
3926  SDValue CCReg = SelectCC(LHS, RHS, CC, dl);
3927  SDValue IntCR;
3928 
3929  // Force the ccreg into CR7.
3930  SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
3931 
3932  SDValue InFlag(nullptr, 0); // Null incoming flag value.
3933  CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg,
3934  InFlag).getValue(1);
3935 
3936  IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
3937  CCReg), 0);
3938 
3939  SDValue Ops[] = { IntCR, getI32Imm((32 - (3 - Idx)) & 31, dl),
3940  getI32Imm(31, dl), getI32Imm(31, dl) };
3941  if (!Inv) {
3942  CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
3943  return true;
3944  }
3945 
3946  // Get the specified bit.
3947  SDValue Tmp =
3948  SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
3949  CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1, dl));
3950  return true;
3951 }
3952 
3953 /// Does this node represent a load/store node whose address can be represented
3954 /// with a register plus an immediate that's a multiple of \p Val:
3955 bool PPCDAGToDAGISel::isOffsetMultipleOf(SDNode *N, unsigned Val) const {
3956  LoadSDNode *LDN = dyn_cast<LoadSDNode>(N);
3957  StoreSDNode *STN = dyn_cast<StoreSDNode>(N);
3958  SDValue AddrOp;
3959  if (LDN)
3960  AddrOp = LDN->getOperand(1);
3961  else if (STN)
3962  AddrOp = STN->getOperand(2);
3963 
3964  // If the address points a frame object or a frame object with an offset,
3965  // we need to check the object alignment.
3966  short Imm = 0;
3967  if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(
3968  AddrOp.getOpcode() == ISD::ADD ? AddrOp.getOperand(0) :
3969  AddrOp)) {
3970  // If op0 is a frame index that is under aligned, we can't do it either,
3971  // because it is translated to r31 or r1 + slot + offset. We won't know the
3972  // slot number until the stack frame is finalized.
3973  const MachineFrameInfo &MFI = CurDAG->getMachineFunction().getFrameInfo();
3974  unsigned SlotAlign = MFI.getObjectAlignment(FI->getIndex());
3975  if ((SlotAlign % Val) != 0)
3976  return false;
3977 
3978  // If we have an offset, we need further check on the offset.
3979  if (AddrOp.getOpcode() != ISD::ADD)
3980  return true;
3981  }
3982 
3983  if (AddrOp.getOpcode() == ISD::ADD)
3984  return isIntS16Immediate(AddrOp.getOperand(1), Imm) && !(Imm % Val);
3985 
3986  // If the address comes from the outside, the offset will be zero.
3987  return AddrOp.getOpcode() == ISD::CopyFromReg;
3988 }
3989 
3990 void PPCDAGToDAGISel::transferMemOperands(SDNode *N, SDNode *Result) {
3991  // Transfer memoperands.
3993  MemOp[0] = cast<MemSDNode>(N)->getMemOperand();
3994  cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
3995 }
3996 
3997 /// This method returns a node after flipping the MSB of each element
3998 /// of vector integer type. Additionally, if SignBitVec is non-null,
3999 /// this method sets a node with one at MSB of all elements
4000 /// and zero at other bits in SignBitVec.
4001 MachineSDNode *
4002 PPCDAGToDAGISel::flipSignBit(const SDValue &N, SDNode **SignBitVec) {
4003  SDLoc dl(N);
4004  EVT VecVT = N.getValueType();
4005  if (VecVT == MVT::v4i32) {
4006  if (SignBitVec) {
4007  SDNode *ZV = CurDAG->getMachineNode(PPC::V_SET0, dl, MVT::v4i32);
4008  *SignBitVec = CurDAG->getMachineNode(PPC::XVNEGSP, dl, VecVT,
4009  SDValue(ZV, 0));
4010  }
4011  return CurDAG->getMachineNode(PPC::XVNEGSP, dl, VecVT, N);
4012  }
4013  else if (VecVT == MVT::v8i16) {
4014  SDNode *Hi = CurDAG->getMachineNode(PPC::LIS, dl, MVT::i32,
4015  getI32Imm(0x8000, dl));
4016  SDNode *ScaImm = CurDAG->getMachineNode(PPC::ORI, dl, MVT::i32,
4017  SDValue(Hi, 0),
4018  getI32Imm(0x8000, dl));
4019  SDNode *VecImm = CurDAG->getMachineNode(PPC::MTVSRWS, dl, VecVT,
4020  SDValue(ScaImm, 0));
4021  /*
4022  Alternatively, we can do this as follow to use VRF instead of GPR.
4023  vspltish 5, 1
4024  vspltish 6, 15
4025  vslh 5, 6, 5
4026  */
4027  if (SignBitVec) *SignBitVec = VecImm;
4028  return CurDAG->getMachineNode(PPC::VADDUHM, dl, VecVT, N,
4029  SDValue(VecImm, 0));
4030  }
4031  else if (VecVT == MVT::v16i8) {
4032  SDNode *VecImm = CurDAG->getMachineNode(PPC::XXSPLTIB, dl, MVT::i32,
4033  getI32Imm(0x80, dl));
4034  if (SignBitVec) *SignBitVec = VecImm;
4035  return CurDAG->getMachineNode(PPC::VADDUBM, dl, VecVT, N,
4036  SDValue(VecImm, 0));
4037  }
4038  else
4039  llvm_unreachable("Unsupported vector data type for flipSignBit");
4040 }
4041 
4042 // Select - Convert the specified operand from a target-independent to a
4043 // target-specific node if it hasn't already been changed.
4045  SDLoc dl(N);
4046  if (N->isMachineOpcode()) {
4047  N->setNodeId(-1);
4048  return; // Already selected.
4049  }
4050 
4051  // In case any misguided DAG-level optimizations form an ADD with a
4052  // TargetConstant operand, crash here instead of miscompiling (by selecting
4053  // an r+r add instead of some kind of r+i add).
4054  if (N->getOpcode() == ISD::ADD &&
4056  llvm_unreachable("Invalid ADD with TargetConstant operand");
4057 
4058  // Try matching complex bit permutations before doing anything else.
4059  if (tryBitPermutation(N))
4060  return;
4061 
4062  // Try to emit integer compares as GPR-only sequences (i.e. no use of CR).
4063  if (tryIntCompareInGPR(N))
4064  return;
4065 
4066  switch (N->getOpcode()) {
4067  default: break;
4068 
4069  case ISD::Constant:
4070  if (N->getValueType(0) == MVT::i64) {
4071  ReplaceNode(N, selectI64Imm(CurDAG, N));
4072  return;
4073  }
4074  break;
4075 
4076  case ISD::SETCC:
4077  if (trySETCC(N))
4078  return;
4079  break;
4080 
4081  case PPCISD::CALL: {
4082  const Module *M = MF->getFunction().getParent();
4083 
4084  if (PPCLowering->getPointerTy(CurDAG->getDataLayout()) != MVT::i32 ||
4085  !PPCSubTarget->isSecurePlt() || !PPCSubTarget->isTargetELF() ||
4087  break;
4088 
4089  SDValue Op = N->getOperand(1);
4090 
4091  if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) {
4092  if (GA->getTargetFlags() == PPCII::MO_PLT)
4093  getGlobalBaseReg();
4094  }
4095  else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
4096  if (ES->getTargetFlags() == PPCII::MO_PLT)
4097  getGlobalBaseReg();
4098  }
4099  }
4100  break;
4101 
4102  case PPCISD::GlobalBaseReg:
4103  ReplaceNode(N, getGlobalBaseReg());
4104  return;
4105 
4106  case ISD::FrameIndex:
4107  selectFrameIndex(N, N);
4108  return;
4109 
4110  case PPCISD::MFOCRF: {
4111  SDValue InFlag = N->getOperand(1);
4112  ReplaceNode(N, CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32,
4113  N->getOperand(0), InFlag));
4114  return;
4115  }
4116 
4118  ReplaceNode(N, CurDAG->getMachineNode(PPC::ReadTB, dl, MVT::i32, MVT::i32,
4119  MVT::Other, N->getOperand(0)));
4120  return;
4121 
4122  case PPCISD::SRA_ADDZE: {
4123  SDValue N0 = N->getOperand(0);
4124  SDValue ShiftAmt =
4125  CurDAG->getTargetConstant(*cast<ConstantSDNode>(N->getOperand(1))->
4126  getConstantIntValue(), dl,
4127  N->getValueType(0));
4128  if (N->getValueType(0) == MVT::i64) {
4129  SDNode *Op =
4130  CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, MVT::Glue,
4131  N0, ShiftAmt);
4132  CurDAG->SelectNodeTo(N, PPC::ADDZE8, MVT::i64, SDValue(Op, 0),
4133  SDValue(Op, 1));
4134  return;
4135  } else {
4136  assert(N->getValueType(0) == MVT::i32 &&
4137  "Expecting i64 or i32 in PPCISD::SRA_ADDZE");
4138  SDNode *Op =
4139  CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue,
4140  N0, ShiftAmt);
4141  CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, SDValue(Op, 0),
4142  SDValue(Op, 1));
4143  return;
4144  }
4145  }
4146 
4147  case ISD::STORE: {
4148  // Change TLS initial-exec D-form stores to X-form stores.
4149  StoreSDNode *ST = cast<StoreSDNode>(N);
4150  if (EnableTLSOpt && PPCSubTarget->isELFv2ABI() &&
4152  if (tryTLSXFormStore(ST))
4153  return;
4154  break;
4155  }
4156  case ISD::LOAD: {
4157  // Handle preincrement loads.
4158  LoadSDNode *LD = cast<LoadSDNode>(N);
4159  EVT LoadedVT = LD->getMemoryVT();
4160 
4161  // Normal loads are handled by code generated from the .td file.
4162  if (LD->getAddressingMode() != ISD::PRE_INC) {
4163  // Change TLS initial-exec D-form loads to X-form loads.
4164  if (EnableTLSOpt && PPCSubTarget->isELFv2ABI())
4165  if (tryTLSXFormLoad(LD))
4166  return;
4167  break;
4168  }
4169 
4170  SDValue Offset = LD->getOffset();
4171  if (Offset.getOpcode() == ISD::TargetConstant ||
4172  Offset.getOpcode() == ISD::TargetGlobalAddress) {
4173 
4174  unsigned Opcode;
4175  bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
4176  if (LD->getValueType(0) != MVT::i64) {
4177  // Handle PPC32 integer and normal FP loads.
4178  assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
4179  switch (LoadedVT.getSimpleVT().SimpleTy) {
4180  default: llvm_unreachable("Invalid PPC load type!");
4181  case MVT::f64: Opcode = PPC::LFDU; break;
4182  case MVT::f32: Opcode = PPC::LFSU; break;
4183  case MVT::i32: Opcode = PPC::LWZU; break;
4184  case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
4185  case MVT::i1:
4186  case MVT::i8: Opcode = PPC::LBZU; break;
4187  }
4188  } else {
4189  assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
4190  assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
4191  switch (LoadedVT.getSimpleVT().SimpleTy) {
4192  default: llvm_unreachable("Invalid PPC load type!");
4193  case MVT::i64: Opcode = PPC::LDU; break;
4194  case MVT::i32: Opcode = PPC::LWZU8; break;
4195  case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
4196  case MVT::i1:
4197  case MVT::i8: Opcode = PPC::LBZU8; break;
4198  }
4199  }
4200 
4201  SDValue Chain = LD->getChain();
4202  SDValue Base = LD->getBasePtr();
4203  SDValue Ops[] = { Offset, Base, Chain };
4204  SDNode *MN = CurDAG->getMachineNode(
4205  Opcode, dl, LD->getValueType(0),
4206  PPCLowering->getPointerTy(CurDAG->getDataLayout()), MVT::Other, Ops);
4207  transferMemOperands(N, MN);
4208  ReplaceNode(N, MN);
4209  return;
4210  } else {
4211  unsigned Opcode;
4212  bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
4213  if (LD->getValueType(0) != MVT::i64) {
4214  // Handle PPC32 integer and normal FP loads.
4215  assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
4216  switch (LoadedVT.getSimpleVT().SimpleTy) {
4217  default: llvm_unreachable("Invalid PPC load type!");
4218  case MVT::v4f64: Opcode = PPC::QVLFDUX; break; // QPX
4219  case MVT::v4f32: Opcode = PPC::QVLFSUX; break; // QPX
4220  case MVT::f64: Opcode = PPC::LFDUX; break;
4221  case MVT::f32: Opcode = PPC::LFSUX; break;
4222  case MVT::i32: Opcode = PPC::LWZUX; break;
4223  case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break;
4224  case MVT::i1:
4225  case MVT::i8: Opcode = PPC::LBZUX; break;
4226  }
4227  } else {
4228  assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
4229  assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) &&
4230  "Invalid sext update load");
4231  switch (LoadedVT.getSimpleVT().SimpleTy) {
4232  default: llvm_unreachable("Invalid PPC load type!");
4233  case MVT::i64: Opcode = PPC::LDUX; break;
4234  case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break;
4235  case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; break;
4236  case MVT::i1:
4237  case MVT::i8: Opcode = PPC::LBZUX8; break;
4238  }
4239  }
4240 
4241  SDValue Chain = LD->getChain();
4242  SDValue Base = LD->getBasePtr();
4243  SDValue Ops[] = { Base, Offset, Chain };
4244  SDNode *MN = CurDAG->getMachineNode(
4245  Opcode, dl, LD->getValueType(0),
4246  PPCLowering->getPointerTy(CurDAG->getDataLayout()), MVT::Other, Ops);
4247  transferMemOperands(N, MN);
4248  ReplaceNode(N, MN);
4249  return;
4250  }
4251  }
4252 
4253  case ISD::AND: {
4254  unsigned Imm, Imm2, SH, MB, ME;
4255  uint64_t Imm64;
4256 
4257  // If this is an and of a value rotated between 0 and 31 bits and then and'd
4258  // with a mask, emit rlwinm
4259  if (isInt32Immediate(N->getOperand(1), Imm) &&
4260  isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
4261  SDValue Val = N->getOperand(0).getOperand(0);
4262  SDValue Ops[] = { Val, getI32Imm(SH, dl), getI32Imm(MB, dl),
4263  getI32Imm(ME, dl) };
4264  CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
4265  return;
4266  }
4267  // If this is just a masked value where the input is not handled above, and
4268  // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
4269  if (isInt32Immediate(N->getOperand(1), Imm) &&
4270  isRunOfOnes(Imm, MB, ME) &&
4271  N->getOperand(0).getOpcode() != ISD::ROTL) {
4272  SDValue Val = N->getOperand(0);
4273  SDValue Ops[] = { Val, getI32Imm(0, dl), getI32Imm(MB, dl),
4274  getI32Imm(ME, dl) };
4275  CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
4276  return;
4277  }
4278  // If this is a 64-bit zero-extension mask, emit rldicl.
4279  if (isInt64Immediate(N->getOperand(1).getNode(), Imm64) &&
4280  isMask_64(Imm64)) {
4281  SDValue Val = N->getOperand(0);
4282  MB = 64 - countTrailingOnes(Imm64);
4283  SH = 0;
4284 
4285  if (Val.getOpcode() == ISD::ANY_EXTEND) {
4286  auto Op0 = Val.getOperand(0);
4287  if ( Op0.getOpcode() == ISD::SRL &&
4288  isInt32Immediate(Op0.getOperand(1).getNode(), Imm) && Imm <= MB) {
4289 
4290  auto ResultType = Val.getNode()->getValueType(0);
4291  auto ImDef = CurDAG->getMachineNode(PPC::IMPLICIT_DEF, dl,
4292  ResultType);
4293  SDValue IDVal (ImDef, 0);
4294 
4295  Val = SDValue(CurDAG->getMachineNode(PPC::INSERT_SUBREG, dl,
4296  ResultType, IDVal, Op0.getOperand(0),
4297  getI32Imm(1, dl)), 0);
4298  SH = 64 - Imm;
4299  }
4300  }
4301 
4302  // If the operand is a logical right shift, we can fold it into this
4303  // instruction: rldicl(rldicl(x, 64-n, n), 0, mb) -> rldicl(x, 64-n, mb)
4304  // for n <= mb. The right shift is really a left rotate followed by a
4305  // mask, and this mask is a more-restrictive sub-mask of the mask implied
4306  // by the shift.
4307  if (Val.getOpcode() == ISD::SRL &&
4308  isInt32Immediate(Val.getOperand(1).getNode(), Imm) && Imm <= MB) {
4309  assert(Imm < 64 && "Illegal shift amount");
4310  Val = Val.getOperand(0);
4311  SH = 64 - Imm;
4312  }
4313 
4314  SDValue Ops[] = { Val, getI32Imm(SH, dl), getI32Imm(MB, dl) };
4315  CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops);
4316  return;
4317  }
4318  // If this is a negated 64-bit zero-extension mask,
4319  // i.e. the immediate is a sequence of ones from most significant side
4320  // and all zero for reminder, we should use rldicr.
4321  if (isInt64Immediate(N->getOperand(1).getNode(), Imm64) &&
4322  isMask_64(~Imm64)) {
4323  SDValue Val = N->getOperand(0);
4324  MB = 63 - countTrailingOnes(~Imm64);
4325  SH = 0;
4326  SDValue Ops[] = { Val, getI32Imm(SH, dl), getI32Imm(MB, dl) };
4327  CurDAG->SelectNodeTo(N, PPC::RLDICR, MVT::i64, Ops);
4328  return;
4329  }
4330 
4331  // AND X, 0 -> 0, not "rlwinm 32".
4332  if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
4333  ReplaceUses(SDValue(N, 0), N->getOperand(1));
4334  return;
4335  }
4336  // ISD::OR doesn't get all the bitfield insertion fun.
4337  // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) might be a
4338  // bitfield insert.
4339  if (isInt32Immediate(N->getOperand(1), Imm) &&
4340  N->getOperand(0).getOpcode() == ISD::OR &&
4341  isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
4342  // The idea here is to check whether this is equivalent to:
4343  // (c1 & m) | (x & ~m)
4344  // where m is a run-of-ones mask. The logic here is that, for each bit in
4345  // c1 and c2:
4346  // - if both are 1, then the output will be 1.
4347  // - if both are 0, then the output will be 0.
4348  // - if the bit in c1 is 0, and the bit in c2 is 1, then the output will
4349  // come from x.
4350  // - if the bit in c1 is 1, and the bit in c2 is 0, then the output will
4351  // be 0.
4352  // If that last condition is never the case, then we can form m from the
4353  // bits that are the same between c1 and c2.
4354  unsigned MB, ME;
4355  if (isRunOfOnes(~(Imm^Imm2), MB, ME) && !(~Imm & Imm2)) {
4356  SDValue Ops[] = { N->getOperand(0).getOperand(0),
4357  N->getOperand(0).getOperand(1),
4358  getI32Imm(0, dl), getI32Imm(MB, dl),
4359  getI32Imm(ME, dl) };
4360  ReplaceNode(N, CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops));
4361  return;
4362  }
4363  }
4364 
4365  // Other cases are autogenerated.
4366  break;
4367  }
4368  case ISD::OR: {
4369  if (N->getValueType(0) == MVT::i32)
4370  if (tryBitfieldInsert(N))
4371  return;
4372 
4373  int16_t Imm;
4374  if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
4375  isIntS16Immediate(N->getOperand(1), Imm)) {
4376  KnownBits LHSKnown;
4377  CurDAG->computeKnownBits(N->getOperand(0), LHSKnown);
4378 
4379  // If this is equivalent to an add, then we can fold it with the
4380  // FrameIndex calculation.
4381  if ((LHSKnown.Zero.getZExtValue()|~(uint64_t)Imm) == ~0ULL) {
4382  selectFrameIndex(N, N->getOperand(0).getNode(), (int)Imm);
4383  return;
4384  }
4385  }
4386 
4387  // OR with a 32-bit immediate can be handled by ori + oris
4388  // without creating an immediate in a GPR.
4389  uint64_t Imm64 = 0;
4390  bool IsPPC64 = PPCSubTarget->isPPC64();
4391  if (IsPPC64 && isInt64Immediate(N->getOperand(1), Imm64) &&
4392  (Imm64 & ~0xFFFFFFFFuLL) == 0) {
4393  // If ImmHi (ImmHi) is zero, only one ori (oris) is generated later.
4394  uint64_t ImmHi = Imm64 >> 16;
4395  uint64_t ImmLo = Imm64 & 0xFFFF;
4396  if (ImmHi != 0 && ImmLo != 0) {
4397  SDNode *Lo = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
4398  N->getOperand(0),
4399  getI16Imm(ImmLo, dl));
4400  SDValue Ops1[] = { SDValue(Lo, 0), getI16Imm(ImmHi, dl)};
4401  CurDAG->SelectNodeTo(N, PPC::ORIS8, MVT::i64, Ops1);
4402  return;
4403  }
4404  }
4405 
4406  // Other cases are autogenerated.
4407  break;
4408  }
4409  case ISD::XOR: {
4410  // XOR with a 32-bit immediate can be handled by xori + xoris
4411  // without creating an immediate in a GPR.
4412  uint64_t Imm64 = 0;
4413  bool IsPPC64 = PPCSubTarget->isPPC64();
4414  if (IsPPC64 && isInt64Immediate(N->getOperand(1), Imm64) &&
4415  (Imm64 & ~0xFFFFFFFFuLL) == 0) {
4416  // If ImmHi (ImmHi) is zero, only one xori (xoris) is generated later.
4417  uint64_t ImmHi = Imm64 >> 16;
4418  uint64_t ImmLo = Imm64 & 0xFFFF;
4419  if (ImmHi != 0 && ImmLo != 0) {
4420  SDNode *Lo = CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64,
4421  N->getOperand(0),
4422  getI16Imm(ImmLo, dl));
4423  SDValue Ops1[] = { SDValue(Lo, 0), getI16Imm(ImmHi, dl)};
4424  CurDAG->SelectNodeTo(N, PPC::XORIS8, MVT::i64, Ops1);
4425  return;
4426  }
4427  }
4428 
4429  break;
4430  }
4431  case ISD::ADD: {
4432  int16_t Imm;
4433  if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
4434  isIntS16Immediate(N->getOperand(1), Imm)) {
4435  selectFrameIndex(N, N->getOperand(0).getNode(), (int)Imm);
4436  return;
4437  }
4438 
4439  break;
4440  }
4441  case ISD::SHL: {
4442  unsigned Imm, SH, MB, ME;
4443  if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
4444  isRotateAndMask(N, Imm, true, SH, MB, ME)) {
4445  SDValue Ops[] = { N->getOperand(0).getOperand(0),
4446  getI32Imm(SH, dl), getI32Imm(MB, dl),
4447  getI32Imm(ME, dl) };
4448  CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
4449  return;
4450  }
4451 
4452  // Other cases are autogenerated.
4453  break;
4454  }
4455  case ISD::SRL: {
4456  unsigned Imm, SH, MB, ME;
4457  if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
4458  isRotateAndMask(N, Imm, true, SH, MB, ME)) {
4459  SDValue Ops[] = { N->getOperand(0).getOperand(0),
4460  getI32Imm(SH, dl), getI32Imm(MB, dl),
4461  getI32Imm(ME, dl) };
4462  CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
4463  return;
4464  }
4465 
4466  // Other cases are autogenerated.
4467  break;
4468  }
4469  // FIXME: Remove this once the ANDI glue bug is fixed:
4471  case PPCISD::ANDIo_1_GT_BIT: {
4472  if (!ANDIGlueBug)
4473  break;
4474 
4475  EVT InVT = N->getOperand(0).getValueType();
4476  assert((InVT == MVT::i64 || InVT == MVT::i32) &&
4477  "Invalid input type for ANDIo_1_EQ_BIT");
4478 
4479  unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDIo8 : PPC::ANDIo;
4480  SDValue AndI(CurDAG->getMachineNode(Opcode, dl, InVT, MVT::Glue,
4481  N->getOperand(0),
4482  CurDAG->getTargetConstant(1, dl, InVT)),
4483  0);
4484  SDValue CR0Reg = CurDAG->getRegister(PPC::CR0, MVT::i32);
4485  SDValue SRIdxVal =
4486  CurDAG->getTargetConstant(N->getOpcode() == PPCISD::ANDIo_1_EQ_BIT ?
4487  PPC::sub_eq : PPC::sub_gt, dl, MVT::i32);
4488 
4489  CurDAG->SelectNodeTo(N, TargetOpcode::EXTRACT_SUBREG, MVT::i1, CR0Reg,
4490  SRIdxVal, SDValue(AndI.getNode(), 1) /* glue */);
4491  return;
4492  }
4493  case ISD::SELECT_CC: {
4494  ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
4495  EVT PtrVT =
4496  CurDAG->getTargetLoweringInfo().getPointerTy(CurDAG->getDataLayout());
4497  bool isPPC64 = (PtrVT == MVT::i64);
4498 
4499  // If this is a select of i1 operands, we'll pattern match it.
4500  if (PPCSubTarget->useCRBits() &&
4501  N->getOperand(0).getValueType() == MVT::i1)
4502  break;
4503 
4504  // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
4505  if (!isPPC64)
4506  if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
4507  if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
4508  if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
4509  if (N1C->isNullValue() && N3C->isNullValue() &&
4510  N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
4511  // FIXME: Implement this optzn for PPC64.
4512  N->getValueType(0) == MVT::i32) {
4513  SDNode *Tmp =
4514  CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
4515  N->getOperand(0), getI32Imm(~0U, dl));
4516  CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(Tmp, 0),
4517  N->getOperand(0), SDValue(Tmp, 1));
4518  return;
4519  }
4520 
4521  SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
4522 
4523  if (N->getValueType(0) == MVT::i1) {
4524  // An i1 select is: (c & t) | (!c & f).
4525  bool Inv;
4526  unsigned Idx = getCRIdxForSetCC(CC, Inv);
4527 
4528  unsigned SRI;
4529  switch (Idx) {
4530  default: llvm_unreachable("Invalid CC index");
4531  case 0: SRI = PPC::sub_lt; break;
4532  case 1: SRI = PPC::sub_gt; break;
4533  case 2: SRI = PPC::sub_eq; break;
4534  case 3: SRI = PPC::sub_un; break;
4535  }
4536 
4537  SDValue CCBit = CurDAG->getTargetExtractSubreg(SRI, dl, MVT::i1, CCReg);
4538 
4539  SDValue NotCCBit(CurDAG->getMachineNode(PPC::CRNOR, dl, MVT::i1,
4540  CCBit, CCBit), 0);
4541  SDValue C = Inv ? NotCCBit : CCBit,
4542  NotC = Inv ? CCBit : NotCCBit;
4543 
4544  SDValue CAndT(CurDAG->getMachineNode(PPC::CRAND, dl, MVT::i1,
4545  C, N->getOperand(2)), 0);
4546  SDValue NotCAndF(CurDAG->getMachineNode(PPC::CRAND, dl, MVT::i1,
4547  NotC, N->getOperand(3)), 0);
4548 
4549  CurDAG->SelectNodeTo(N, PPC::CROR, MVT::i1, CAndT, NotCAndF);
4550  return;
4551  }
4552 
4553  unsigned BROpc = getPredicateForSetCC(CC);
4554 
4555  unsigned SelectCCOp;
4556  if (N->getValueType(0) == MVT::i32)
4557  SelectCCOp = PPC::SELECT_CC_I4;
4558  else if (N->getValueType(0) == MVT::i64)
4559  SelectCCOp = PPC::SELECT_CC_I8;
4560  else if (N->getValueType(0) == MVT::f32)
4561  if (PPCSubTarget->hasP8Vector())
4562  SelectCCOp = PPC::SELECT_CC_VSSRC;
4563  else
4564  SelectCCOp = PPC::SELECT_CC_F4;
4565  else if (N->getValueType(0) == MVT::f64)
4566  if (PPCSubTarget->hasVSX())
4567  SelectCCOp = PPC::SELECT_CC_VSFRC;
4568  else
4569  SelectCCOp = PPC::SELECT_CC_F8;
4570  else if (N->getValueType(0) == MVT::f128)
4571  SelectCCOp = PPC::SELECT_CC_F16;
4572  else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4f64)
4573  SelectCCOp = PPC::SELECT_CC_QFRC;
4574  else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4f32)
4575  SelectCCOp = PPC::SELECT_CC_QSRC;
4576  else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4i1)
4577  SelectCCOp = PPC::SELECT_CC_QBRC;
4578  else if (N->getValueType(0) == MVT::v2f64 ||
4579  N->getValueType(0) == MVT::v2i64)
4580  SelectCCOp = PPC::SELECT_CC_VSRC;
4581  else
4582  SelectCCOp = PPC::SELECT_CC_VRRC;
4583 
4584  SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
4585  getI32Imm(BROpc, dl) };
4586  CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops);
4587  return;
4588  }
4589  case ISD::VSELECT:
4590  if (PPCSubTarget->hasVSX()) {
4591  SDValue Ops[] = { N->getOperand(2), N->getOperand(1), N->getOperand(0) };
4592  CurDAG->SelectNodeTo(N, PPC::XXSEL, N->getValueType(0), Ops);
4593  return;
4594  }
4595  break;
4596 
4597  case ISD::VECTOR_SHUFFLE:
4598  if (PPCSubTarget->hasVSX() && (N->getValueType(0) == MVT::v2f64 ||
4599  N->getValueType(0) == MVT::v2i64)) {
4600  ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
4601 
4602  SDValue Op1 = N->getOperand(SVN->getMaskElt(0) < 2 ? 0 : 1),
4603  Op2 = N->getOperand(SVN->getMaskElt(1) < 2 ? 0 : 1);
4604  unsigned DM[2];
4605 
4606  for (int i = 0; i < 2; ++i)
4607  if (SVN->getMaskElt(i) <= 0 || SVN->getMaskElt(i) == 2)
4608  DM[i] = 0;
4609  else
4610  DM[i] = 1;
4611 
4612  if (Op1 == Op2 && DM[0] == 0 && DM[1] == 0 &&
4613  Op1.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4614  isa<LoadSDNode>(Op1.getOperand(0))) {
4615  LoadSDNode *LD = cast<LoadSDNode>(Op1.getOperand(0));
4616  SDValue Base, Offset;
4617 
4618  if (LD->isUnindexed() && LD->hasOneUse() && Op1.hasOneUse() &&
4619  (LD->getMemoryVT() == MVT::f64 ||
4620  LD->getMemoryVT() == MVT::i64) &&
4621  SelectAddrIdxOnly(LD->getBasePtr(), Base, Offset)) {
4622  SDValue Chain = LD->getChain();
4623  SDValue Ops[] = { Base, Offset, Chain };
4625  MemOp[0] = LD->getMemOperand();
4626  SDNode *NewN = CurDAG->SelectNodeTo(N, PPC::LXVDSX,
4627  N->getValueType(0), Ops);
4628  cast<MachineSDNode>(NewN)->setMemRefs(MemOp, MemOp + 1);
4629  return;
4630  }
4631  }
4632 
4633  // For little endian, we must swap the input operands and adjust
4634  // the mask elements (reverse and invert them).
4635  if (PPCSubTarget->isLittleEndian()) {
4636  std::swap(Op1, Op2);
4637  unsigned tmp = DM[0];
4638  DM[0] = 1 - DM[1];
4639  DM[1] = 1 - tmp;
4640  }
4641 
4642  SDValue DMV = CurDAG->getTargetConstant(DM[1] | (DM[0] << 1), dl,
4643  MVT::i32);
4644  SDValue Ops[] = { Op1, Op2, DMV };
4645  CurDAG->SelectNodeTo(N, PPC::XXPERMDI, N->getValueType(0), Ops);
4646  return;
4647  }
4648 
4649  break;
4650  case PPCISD::BDNZ:
4651  case PPCISD::BDZ: {
4652  bool IsPPC64 = PPCSubTarget->isPPC64();
4653  SDValue Ops[] = { N->getOperand(1), N->getOperand(0) };
4654  CurDAG->SelectNodeTo(N, N->getOpcode() == PPCISD::BDNZ
4655  ? (IsPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
4656  : (IsPPC64 ? PPC::BDZ8 : PPC::BDZ),
4657  MVT::Other, Ops);
4658  return;
4659  }
4660  case PPCISD::COND_BRANCH: {
4661  // Op #0 is the Chain.
4662  // Op #1 is the PPC::PRED_* number.
4663  // Op #2 is the CR#
4664  // Op #3 is the Dest MBB
4665  // Op #4 is the Flag.
4666  // Prevent PPC::PRED_* from being selected into LI.
4667  unsigned PCC = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
4668  if (EnableBranchHint)
4669  PCC |= getBranchHint(PCC, FuncInfo, N->getOperand(3));
4670 
4671  SDValue Pred = getI32Imm(PCC, dl);
4672  SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
4673  N->getOperand(0), N->getOperand(4) };
4674  CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
4675  return;
4676  }
4677  case ISD::BR_CC: {
4678  ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
4679  unsigned PCC = getPredicateForSetCC(CC);
4680 
4681  if (N->getOperand(2).getValueType() == MVT::i1) {
4682  unsigned Opc;
4683  bool Swap;
4684  switch (PCC) {
4685  default: llvm_unreachable("Unexpected Boolean-operand predicate");
4686  case PPC::PRED_LT: Opc = PPC::CRANDC; Swap = true; break;
4687  case PPC::PRED_LE: Opc = PPC::CRORC; Swap = true; break;
4688  case PPC::PRED_EQ: Opc = PPC::CREQV; Swap = false; break;
4689  case PPC::PRED_GE: Opc = PPC::CRORC; Swap = false; break;
4690  case PPC::PRED_GT: Opc = PPC::CRANDC; Swap = false; break;
4691  case PPC::PRED_NE: Opc = PPC::CRXOR; Swap = false; break;
4692  }
4693 
4694  SDValue BitComp(CurDAG->getMachineNode(Opc, dl, MVT::i1,
4695  N->getOperand(Swap ? 3 : 2),
4696  N->getOperand(Swap ? 2 : 3)), 0);
4697  CurDAG->SelectNodeTo(N, PPC::BC, MVT::Other, BitComp, N->getOperand(4),
4698  N->getOperand(0));
4699  return;
4700  }
4701 
4702  if (EnableBranchHint)
4703  PCC |= getBranchHint(PCC, FuncInfo, N->getOperand(4));
4704 
4705  SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
4706  SDValue Ops[] = { getI32Imm(PCC, dl), CondCode,
4707  N->getOperand(4), N->getOperand(0) };
4708  CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
4709  return;
4710  }
4711  case ISD::BRIND: {
4712  // FIXME: Should custom lower this.
4713  SDValue Chain = N->getOperand(0);
4714  SDValue Target = N->getOperand(1);
4715  unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
4716  unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8;
4717  Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, Target,
4718  Chain), 0);
4719  CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);
4720  return;
4721  }
4722  case PPCISD::TOC_ENTRY: {
4723  assert ((PPCSubTarget->isPPC64() || PPCSubTarget->isSVR4ABI()) &&
4724  "Only supported for 64-bit ABI and 32-bit SVR4");
4725  if (PPCSubTarget->isSVR4ABI() && !PPCSubTarget->isPPC64()) {
4726  SDValue GA = N->getOperand(0);
4727  SDNode *MN = CurDAG->getMachineNode(PPC::LWZtoc, dl, MVT::i32, GA,
4728  N->getOperand(1));
4729  transferMemOperands(N, MN);
4730  ReplaceNode(N, MN);
4731  return;
4732  }
4733 
4734  // For medium and large code model, we generate two instructions as
4735  // described below. Otherwise we allow SelectCodeCommon to handle this,
4736  // selecting one of LDtoc, LDtocJTI, LDtocCPT, and LDtocBA.
4737  CodeModel::Model CModel = TM.getCodeModel();
4738  if (CModel != CodeModel::Medium && CModel != CodeModel::Large)
4739  break;
4740 
4741  // The first source operand is a TargetGlobalAddress or a TargetJumpTable.
4742  // If it must be toc-referenced according to PPCSubTarget, we generate:
4743  // LDtocL(@sym, ADDIStocHA(%x2, @sym))
4744  // Otherwise we generate:
4745  // ADDItocL(ADDIStocHA(%x2, @sym), @sym)
4746  SDValue GA = N->getOperand(0);
4747  SDValue TOCbase = N->getOperand(1);
4748  SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA, dl, MVT::i64,
4749  TOCbase, GA);
4750 
4751  if (isa<JumpTableSDNode>(GA) || isa<BlockAddressSDNode>(GA) ||
4752  CModel == CodeModel::Large) {
4753  SDNode *MN = CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
4754  SDValue(Tmp, 0));
4755  transferMemOperands(N, MN);
4756  ReplaceNode(N, MN);
4757  return;
4758  }
4759 
4760  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(GA)) {
4761  const GlobalValue *GV = G->getGlobal();
4762  unsigned char GVFlags = PPCSubTarget->classifyGlobalReference(GV);
4763  if (GVFlags & PPCII::MO_NLP_FLAG) {
4764  SDNode *MN = CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
4765  SDValue(Tmp, 0));
4766  transferMemOperands(N, MN);
4767  ReplaceNode(N, MN);
4768  return;
4769  }
4770  }
4771 
4772  ReplaceNode(N, CurDAG->getMachineNode(PPC::ADDItocL, dl, MVT::i64,
4773  SDValue(Tmp, 0), GA));
4774  return;
4775  }
4776  case PPCISD::PPC32_PICGOT:
4777  // Generate a PIC-safe GOT reference.
4778  assert(!PPCSubTarget->isPPC64() && PPCSubTarget->isSVR4ABI() &&
4779  "PPCISD::PPC32_PICGOT is only supported for 32-bit SVR4");
4780  CurDAG->SelectNodeTo(N, PPC::PPC32PICGOT,
4781  PPCLowering->getPointerTy(CurDAG->getDataLayout()),
4782  MVT::i32);
4783  return;
4784 
4785  case PPCISD::VADD_SPLAT: {
4786  // This expands into one of three sequences, depending on whether
4787  // the first operand is odd or even, positive or negative.
4788  assert(isa<ConstantSDNode>(N->getOperand(0)) &&
4789  isa<ConstantSDNode>(N->getOperand(1)) &&
4790  "Invalid operand on VADD_SPLAT!");
4791 
4792  int Elt = N->getConstantOperandVal(0);
4793  int EltSize = N->getConstantOperandVal(1);
4794  unsigned Opc1, Opc2, Opc3;
4795  EVT VT;
4796 
4797  if (EltSize == 1) {
4798  Opc1 = PPC::VSPLTISB;
4799  Opc2 = PPC::VADDUBM;
4800  Opc3 = PPC::VSUBUBM;
4801  VT = MVT::v16i8;
4802  } else if (EltSize == 2) {
4803  Opc1 = PPC::VSPLTISH;
4804  Opc2 = PPC::VADDUHM;
4805  Opc3 = PPC::VSUBUHM;
4806  VT = MVT::v8i16;
4807  } else {
4808  assert(EltSize == 4 && "Invalid element size on VADD_SPLAT!");
4809  Opc1 = PPC::VSPLTISW;
4810  Opc2 = PPC::VADDUWM;
4811  Opc3 = PPC::VSUBUWM;
4812  VT = MVT::v4i32;
4813  }
4814 
4815  if ((Elt & 1) == 0) {
4816  // Elt is even, in the range [-32,-18] + [16,30].
4817  //
4818  // Convert: VADD_SPLAT elt, size
4819  // Into: tmp = VSPLTIS[BHW] elt
4820  // VADDU[BHW]M tmp, tmp
4821  // Where: [BHW] = B for size = 1, H for size = 2, W for size = 4
4822  SDValue EltVal = getI32Imm(Elt >> 1, dl);
4823  SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
4824  SDValue TmpVal = SDValue(Tmp, 0);
4825  ReplaceNode(N, CurDAG->getMachineNode(Opc2, dl, VT, TmpVal, TmpVal));
4826  return;
4827  } else if (Elt > 0) {
4828  // Elt is odd and positive, in the range [17,31].
4829  //
4830  // Convert: VADD_SPLAT elt, size
4831  // Into: tmp1 = VSPLTIS[BHW] elt-16
4832  // tmp2 = VSPLTIS[BHW] -16
4833  // VSUBU[BHW]M tmp1, tmp2
4834  SDValue EltVal = getI32Imm(Elt - 16, dl);
4835  SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
4836  EltVal = getI32Imm(-16, dl);
4837  SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
4838  ReplaceNode(N, CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0),
4839  SDValue(Tmp2, 0)));
4840  return;
4841  } else {
4842  // Elt is odd and negative, in the range [-31,-17].
4843  //
4844  // Convert: VADD_SPLAT elt, size
4845  // Into: tmp1 = VSPLTIS[BHW] elt+16
4846  // tmp2 = VSPLTIS[BHW] -16
4847  // VADDU[BHW]M tmp1, tmp2
4848  SDValue EltVal = getI32Imm(Elt + 16, dl);
4849  SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
4850  EltVal = getI32Imm(-16, dl);
4851  SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
4852  ReplaceNode(N, CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0),
4853  SDValue(Tmp2, 0)));
4854  return;
4855  }
4856  }
4857  case ISD::ABS: {
4858  assert(PPCSubTarget->hasP9Vector() && "ABS is supported with P9 Vector");
4859 
4860  // For vector absolute difference, we use VABSDUW instruction of POWER9.
4861  // Since VABSDU instructions are for unsigned integers, we need adjustment
4862  // for signed integers.
4863  // For abs(sub(a, b)), we generate VABSDUW(a+0x80000000, b+0x80000000).
4864  // Otherwise, abs(sub(-1, 0)) returns 0xFFFFFFFF(=-1) instead of 1.
4865  // For abs(a), we generate VABSDUW(a+0x80000000, 0x80000000).
4866  EVT VecVT = N->getOperand(0).getValueType();
4867  SDNode *AbsOp = nullptr;
4868  unsigned AbsOpcode;
4869 
4870  if (VecVT == MVT::v4i32)
4871  AbsOpcode = PPC::VABSDUW;
4872  else if (VecVT == MVT::v8i16)
4873  AbsOpcode = PPC::VABSDUH;
4874  else if (VecVT == MVT::v16i8)
4875  AbsOpcode = PPC::VABSDUB;
4876  else
4877  llvm_unreachable("Unsupported vector data type for ISD::ABS");
4878 
4879  // Even for signed integers, we can skip adjustment if all values are
4880  // known to be positive (as signed integer) due to zero-extended inputs.
4881  if (N->getOperand(0).getOpcode() == ISD::SUB &&
4884  AbsOp = CurDAG->getMachineNode(AbsOpcode, dl, VecVT,
4885  SDValue(N->getOperand(0)->getOperand(0)),
4886  SDValue(N->getOperand(0)->getOperand(1)));
4887  ReplaceNode(N, AbsOp);
4888  return;
4889  }
4890  if (N->getOperand(0).getOpcode() == ISD::SUB) {
4891  SDValue SubVal = N->getOperand(0);
4892  SDNode *Op0 = flipSignBit(SubVal->getOperand(0));
4893  SDNode *Op1 = flipSignBit(SubVal->getOperand(1));
4894  AbsOp = CurDAG->getMachineNode(AbsOpcode, dl, VecVT,
4895  SDValue(Op0, 0), SDValue(Op1, 0));
4896  }
4897  else {
4898  SDNode *Op1 = nullptr;
4899  SDNode *Op0 = flipSignBit(N->getOperand(0), &Op1);
4900  AbsOp = CurDAG->getMachineNode(AbsOpcode, dl, VecVT, SDValue(Op0, 0),
4901  SDValue(Op1, 0));
4902  }
4903  ReplaceNode(N, AbsOp);
4904  return;
4905  }
4906  }
4907 
4908  SelectCode(N);
4909 }
4910 
4911 // If the target supports the cmpb instruction, do the idiom recognition here.
4912 // We don't do this as a DAG combine because we don't want to do it as nodes
4913 // are being combined (because we might miss part of the eventual idiom). We
4914 // don't want to do it during instruction selection because we want to reuse
4915 // the logic for lowering the masking operations already part of the
4916 // instruction selector.
4917 SDValue PPCDAGToDAGISel::combineToCMPB(SDNode *N) {
4918  SDLoc dl(N);
4919 
4920  assert(N->getOpcode() == ISD::OR &&
4921  "Only OR nodes are supported for CMPB");
4922 
4923  SDValue Res;
4924  if (!PPCSubTarget->hasCMPB())
4925  return Res;
4926 
4927  if (N->getValueType(0) != MVT::i32 &&
4928  N->getValueType(0) != MVT::i64)
4929  return Res;
4930 
4931  EVT VT = N->getValueType(0);
4932 
4933  SDValue RHS, LHS;
4934  bool BytesFound[8] = {false, false, false, false, false, false, false, false};
4935  uint64_t Mask = 0, Alt = 0;
4936 
4937  auto IsByteSelectCC = [this](SDValue O, unsigned &b,
4938  uint64_t &Mask, uint64_t &Alt,
4939  SDValue &LHS, SDValue &RHS) {
4940  if (O.getOpcode() != ISD::SELECT_CC)
4941  return false;
4942  ISD::CondCode CC = cast<CondCodeSDNode>(O.getOperand(4))->get();
4943 
4944  if (!isa<ConstantSDNode>(O.getOperand(2)) ||
4945  !isa<ConstantSDNode>(O.getOperand(3)))
4946  return false;
4947 
4948  uint64_t PM = O.getConstantOperandVal(2);
4949  uint64_t PAlt = O.getConstantOperandVal(3);
4950  for (b = 0; b < 8; ++b) {
4951  uint64_t Mask = UINT64_C(0xFF) << (8*b);
4952  if (PM && (PM & Mask) == PM && (PAlt & Mask) == PAlt)
4953  break;
4954  }
4955 
4956  if (b == 8)
4957  return false;
4958  Mask |= PM;
4959  Alt |= PAlt;
4960 
4961  if (!isa<ConstantSDNode>(O.getOperand(1)) ||
4962  O.getConstantOperandVal(1) != 0) {
4963  SDValue Op0 = O.getOperand(0), Op1 = O.getOperand(1);
4964  if (Op0.getOpcode() == ISD::TRUNCATE)
4965  Op0 = Op0.getOperand(0);
4966  if (Op1.getOpcode() == ISD::TRUNCATE)
4967  Op1 = Op1.getOperand(0);
4968 
4969  if (Op0.getOpcode() == ISD::SRL && Op1.getOpcode() == ISD::SRL &&
4970  Op0.getOperand(1) == Op1.getOperand(1) && CC == ISD::SETEQ &&
4971  isa<ConstantSDNode>(Op0.getOperand(1))) {
4972 
4973  unsigned Bits = Op0.getValueSizeInBits();
4974  if (b != Bits/8-1)
4975  return false;
4976  if (Op0.getConstantOperandVal(1) != Bits-8)
4977  return false;
4978 
4979  LHS = Op0.getOperand(0);
4980  RHS = Op1.getOperand(0);
4981  return true;
4982  }
4983 
4984  // When we have small integers (i16 to be specific), the form present
4985  // post-legalization uses SETULT in the SELECT_CC for the
4986  // higher-order byte, depending on the fact that the
4987  // even-higher-order bytes are known to all be zero, for example:
4988  // select_cc (xor $lhs, $rhs), 256, 65280, 0, setult
4989  // (so when the second byte is the same, because all higher-order
4990  // bits from bytes 3 and 4 are known to be zero, the result of the
4991  // xor can be at most 255)
4992  if (Op0.getOpcode() == ISD::XOR && CC == ISD::SETULT &&
4993  isa<ConstantSDNode>(O.getOperand(1))) {
4994 
4995  uint64_t ULim = O.getConstantOperandVal(1);
4996  if (ULim != (UINT64_C(1) << b*8))
4997  return false;
4998 
4999  // Now we need to make sure that the upper bytes are known to be
5000  // zero.
5001  unsigned Bits = Op0.getValueSizeInBits();
5002  if (!CurDAG->MaskedValueIsZero(
5003  Op0, APInt::getHighBitsSet(Bits, Bits - (b + 1) * 8)))
5004  return false;
5005 
5006  LHS = Op0.getOperand(0);
5007  RHS = Op0.getOperand(1);
5008  return true;
5009  }
5010 
5011  return false;
5012  }
5013 
5014  if (CC != ISD::SETEQ)
5015  return false;
5016 
5017  SDValue Op = O.getOperand(0);
5018  if (Op.getOpcode() == ISD::AND) {
5019  if (!isa<ConstantSDNode>(Op.getOperand(1)))
5020  return false;
5021  if (Op.getConstantOperandVal(1) != (UINT64_C(0xFF) << (8*b)))
5022  return false;
5023 
5024  SDValue XOR = Op.getOperand(0);
5025  if (XOR.getOpcode() == ISD::TRUNCATE)
5026  XOR = XOR.getOperand(0);
5027  if (XOR.getOpcode() != ISD::XOR)
5028  return false;
5029 
5030  LHS = XOR.getOperand(0);
5031  RHS = XOR.getOperand(1);
5032  return true;
5033  } else if (Op.getOpcode() == ISD::SRL) {
5034  if (!isa<ConstantSDNode>(Op.getOperand(1)))
5035  return false;
5036  unsigned Bits = Op.getValueSizeInBits();
5037  if (b != Bits/8-1)
5038  return false;
5039  if (Op.getConstantOperandVal(1) != Bits-8)
5040  return false;
5041 
5042  SDValue XOR = Op.getOperand(0);
5043  if (XOR.getOpcode() == ISD::TRUNCATE)
5044  XOR = XOR.getOperand(0);
5045  if (XOR.getOpcode() != ISD::XOR)
5046  return false;
5047 
5048  LHS = XOR.getOperand(0);
5049  RHS = XOR.getOperand(1);
5050  return true;
5051  }
5052 
5053  return false;
5054  };
5055 
5056  SmallVector<SDValue, 8> Queue(1, SDValue(N, 0));
5057  while (!Queue.empty()) {
5058  SDValue V = Queue.pop_back_val();
5059 
5060  for (const SDValue &O : V.getNode()->ops()) {
5061  unsigned b;
5062  uint64_t M = 0, A = 0;
5063  SDValue OLHS, ORHS;
5064  if (O.getOpcode() == ISD::OR) {
5065  Queue.push_back(O);
5066  } else if (IsByteSelectCC(O, b, M, A, OLHS, ORHS)) {
5067  if (!LHS) {
5068  LHS = OLHS;
5069  RHS = ORHS;
5070  BytesFound[b] = true;
5071  Mask |= M;
5072  Alt |= A;
5073  } else if ((LHS == ORHS && RHS == OLHS) ||
5074  (RHS == ORHS && LHS == OLHS)) {
5075  BytesFound[b] = true;
5076  Mask |= M;
5077  Alt |= A;
5078  } else {
5079  return Res;
5080  }
5081  } else {
5082  return Res;
5083  }
5084  }
5085  }
5086 
5087  unsigned LastB = 0, BCnt = 0;
5088  for (unsigned i = 0; i < 8; ++i)
5089  if (BytesFound[LastB]) {
5090  ++BCnt;
5091  LastB = i;
5092  }
5093 
5094  if (!LastB || BCnt < 2)
5095  return Res;
5096 
5097  // Because we'll be zero-extending the output anyway if don't have a specific
5098  // value for each input byte (via the Mask), we can 'anyext' the inputs.
5099  if (LHS.getValueType() != VT) {
5100  LHS = CurDAG->getAnyExtOrTrunc(LHS, dl, VT);
5101  RHS = CurDAG->getAnyExtOrTrunc(RHS, dl, VT);
5102  }
5103 
5104  Res = CurDAG->getNode(PPCISD::CMPB, dl, VT, LHS, RHS);
5105 
5106  bool NonTrivialMask = ((int64_t) Mask) != INT64_C(-1);
5107  if (NonTrivialMask && !Alt) {
5108  // Res = Mask & CMPB
5109  Res = CurDAG->getNode(ISD::AND, dl, VT, Res,
5110  CurDAG->getConstant(Mask, dl, VT));
5111  } else if (Alt) {
5112  // Res = (CMPB & Mask) | (~CMPB & Alt)
5113  // Which, as suggested here:
5114  // https://graphics.stanford.edu/~seander/bithacks.html#MaskedMerge
5115  // can be written as:
5116  // Res = Alt ^ ((Alt ^ Mask) & CMPB)
5117  // useful because the (Alt ^ Mask) can be pre-computed.
5118  Res = CurDAG->getNode(ISD::AND, dl, VT, Res,
5119  CurDAG->getConstant(Mask ^ Alt, dl, VT));
5120  Res = CurDAG->getNode(ISD::XOR, dl, VT, Res,
5121  CurDAG->getConstant(Alt, dl, VT));
5122  }
5123 
5124  return Res;
5125 }
5126 
5127 // When CR bit registers are enabled, an extension of an i1 variable to a i32
5128 // or i64 value is lowered in terms of a SELECT_I[48] operation, and thus
5129 // involves constant materialization of a 0 or a 1 or both. If the result of
5130 // the extension is then operated upon by some operator that can be constant
5131 // folded with a constant 0 or 1, and that constant can be materialized using
5132 // only one instruction (like a zero or one), then we should fold in those
5133 // operations with the select.
5134 void PPCDAGToDAGISel::foldBoolExts(SDValue &Res, SDNode *&N) {
5135  if (!PPCSubTarget->useCRBits())
5136  return;
5137 
5138  if (N->getOpcode() != ISD::ZERO_EXTEND &&
5139  N->getOpcode() != ISD::SIGN_EXTEND &&
5140  N->getOpcode() != ISD::ANY_EXTEND)
5141  return;
5142 
5143  if (N->getOperand(0).getValueType() != MVT::i1)
5144  return;
5145 
5146  if (!N->hasOneUse())
5147  return;
5148 
5149  SDLoc dl(N);
5150  EVT VT = N->getValueType(0);
5151  SDValue Cond = N->getOperand(0);
5152  SDValue ConstTrue =
5153  CurDAG->getConstant(N->getOpcode() == ISD::SIGN_EXTEND ? -1 : 1, dl, VT);
5154  SDValue ConstFalse = CurDAG->getConstant(0, dl, VT);
5155 
5156  do {
5157  SDNode *User = *N->use_begin();
5158  if (User->getNumOperands() != 2)
5159  break;
5160 
5161  auto TryFold = [this, N, User, dl](SDValue Val) {
5162  SDValue UserO0 = User->getOperand(0), UserO1 = User->getOperand(1);
5163  SDValue O0 = UserO0.getNode() == N ? Val : UserO0;
5164  SDValue O1 = UserO1.getNode() == N ? Val : UserO1;
5165 
5166  return CurDAG->FoldConstantArithmetic(User->getOpcode(), dl,
5167  User->getValueType(0),
5168  O0.getNode(), O1.getNode());
5169  };
5170 
5171  // FIXME: When the semantics of the interaction between select and undef
5172  // are clearly defined, it may turn out to be unnecessary to break here.
5173  SDValue TrueRes = TryFold(ConstTrue);
5174  if (!TrueRes || TrueRes.isUndef())
5175  break;
5176  SDValue FalseRes = TryFold(ConstFalse);
5177  if (!FalseRes || FalseRes.isUndef())
5178  break;
5179 
5180  // For us to materialize these using one instruction, we must be able to
5181  // represent them as signed 16-bit integers.
5182  uint64_t True = cast<ConstantSDNode>(TrueRes)->getZExtValue(),
5183  False = cast<ConstantSDNode>(FalseRes)->getZExtValue();
5184  if (!isInt<16>(True) || !isInt<16>(False))
5185  break;
5186 
5187  // We can replace User with a new SELECT node, and try again to see if we
5188  // can fold the select with its user.
5189  Res = CurDAG->getSelect(dl, User->getValueType(0), Cond, TrueRes, FalseRes);
5190  N = User;
5191  ConstTrue = TrueRes;
5192  ConstFalse = FalseRes;
5193  } while (N->hasOneUse());
5194 }
5195 
5196 void PPCDAGToDAGISel::PreprocessISelDAG() {
5197  SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_end();
5198 
5199  bool MadeChange = false;
5200  while (Position != CurDAG->allnodes_begin()) {
5201  SDNode *N = &*--Position;
5202  if (N->use_empty())
5203  continue;
5204 
5205  SDValue Res;
5206  switch (N->getOpcode()) {
5207  default: break;
5208  case ISD::OR:
5209  Res = combineToCMPB(N);
5210  break;
5211  }
5212 
5213  if (!Res)
5214  foldBoolExts(Res, N);
5215 
5216  if (Res) {
5217  LLVM_DEBUG(dbgs() << "PPC DAG preprocessing replacing:\nOld: ");
5218  LLVM_DEBUG(N->dump(CurDAG));
5219  LLVM_DEBUG(dbgs() << "\nNew: ");
5220  LLVM_DEBUG(Res.getNode()->dump(CurDAG));
5221  LLVM_DEBUG(dbgs() << "\n");
5222 
5223  CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Res);
5224  MadeChange = true;
5225  }
5226  }
5227 
5228  if (MadeChange)
5229  CurDAG->RemoveDeadNodes();
5230 }
5231 
5232 /// PostprocessISelDAG - Perform some late peephole optimizations
5233 /// on the DAG representation.
5234 void PPCDAGToDAGISel::PostprocessISelDAG() {
5235  // Skip peepholes at -O0.
5236  if (TM.getOptLevel() == CodeGenOpt::None)
5237  return;
5238 
5239  PeepholePPC64();
5240  PeepholeCROps();
5241  PeepholePPC64ZExt();
5242 }
5243 
5244 // Check if all users of this node will become isel where the second operand
5245 // is the constant zero. If this is so, and if we can negate the condition,
5246 // then we can flip the true and false operands. This will allow the zero to
5247 // be folded with the isel so that we don't need to materialize a register
5248 // containing zero.
5249 bool PPCDAGToDAGISel::AllUsersSelectZero(SDNode *N) {
5250  for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
5251  UI != UE; ++UI) {
5252  SDNode *User = *UI;
5253  if (!User->isMachineOpcode())
5254  return false;
5255  if (User->getMachineOpcode() != PPC::SELECT_I4 &&
5256  User->getMachineOpcode() != PPC::SELECT_I8)
5257  return false;
5258 
5259  SDNode *Op2 = User->getOperand(2).getNode();
5260  if (!Op2->isMachineOpcode())
5261  return false;
5262 
5263  if (Op2->getMachineOpcode() != PPC::LI &&
5264  Op2->getMachineOpcode() != PPC::LI8)
5265  return false;
5266 
5268  if (!C)
5269  return false;
5270 
5271  if (!C->isNullValue())
5272  return false;
5273  }
5274 
5275  return true;
5276 }
5277 
5278 void PPCDAGToDAGISel::SwapAllSelectUsers(SDNode *N) {
5279  SmallVector<SDNode *, 4> ToReplace;
5280  for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
5281  UI != UE; ++UI) {
5282  SDNode *User = *UI;
5283  assert((User->getMachineOpcode() == PPC::SELECT_I4 ||
5284  User->getMachineOpcode() == PPC::SELECT_I8) &&
5285  "Must have all select users");
5286  ToReplace.push_back(User);
5287  }
5288 
5289  for (SmallVector<SDNode *, 4>::iterator UI = ToReplace.begin(),
5290  UE = ToReplace.end(); UI != UE; ++UI) {
5291  SDNode *User = *UI;
5292  SDNode *ResNode =
5293  CurDAG->getMachineNode(User->getMachineOpcode(), SDLoc(User),
5294  User->getValueType(0), User->getOperand(0),
5295  User->getOperand(2),
5296  User->getOperand(1));
5297 
5298  LLVM_DEBUG(dbgs() << "CR Peephole replacing:\nOld: ");
5299  LLVM_DEBUG(User->dump(CurDAG));
5300  LLVM_DEBUG(dbgs() << "\nNew: ");
5301  LLVM_DEBUG(ResNode->dump(CurDAG));
5302  LLVM_DEBUG(dbgs() << "\n");
5303 
5304  ReplaceUses(User, ResNode);
5305  }
5306 }
5307 
5308 void PPCDAGToDAGISel::PeepholeCROps() {
5309  bool IsModified;
5310  do {
5311  IsModified = false;
5312  for (SDNode &Node : CurDAG->allnodes()) {
5313  MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(&Node);
5314  if (!MachineNode || MachineNode->use_empty())
5315  continue;
5316  SDNode *ResNode = MachineNode;
5317 
5318  bool Op1Set = false, Op1Unset = false,
5319  Op1Not = false,
5320  Op2Set = false, Op2Unset = false,
5321  Op2Not = false;
5322 
5323  unsigned Opcode = MachineNode->getMachineOpcode();
5324  switch (Opcode) {
5325  default: break;
5326  case PPC::CRAND:
5327  case PPC::CRNAND:
5328  case PPC::CROR:
5329  case PPC::CRXOR:
5330  case PPC::CRNOR:
5331  case PPC::CREQV:
5332  case PPC::CRANDC:
5333  case PPC::CRORC: {
5334  SDValue Op = MachineNode->getOperand(1);
5335  if (Op.isMachineOpcode()) {
5336  if (Op.getMachineOpcode() == PPC::CRSET)
5337  Op2Set = true;
5338  else if (Op.getMachineOpcode() == PPC::CRUNSET)
5339  Op2Unset = true;
5340  else if (Op.getMachineOpcode() == PPC::CRNOR &&
5341  Op.getOperand(0) == Op.getOperand(1))
5342  Op2Not = true;
5343  }
5345  }
5346  case PPC::BC:
5347  case PPC::BCn:
5348  case PPC::SELECT_I4:
5349  case PPC::SELECT_I8:
5350  case PPC::SELECT_F4:
5351  case PPC::SELECT_F8:
5352  case PPC::SELECT_QFRC:
5353  case PPC::SELECT_QSRC:
5354  case PPC::SELECT_QBRC:
5355  case PPC::SELECT_VRRC:
5356  case PPC::SELECT_VSFRC:
5357  case PPC::SELECT_VSSRC:
5358  case PPC::SELECT_VSRC: {
5359  SDValue Op = MachineNode->getOperand(0);
5360  if (Op.isMachineOpcode()) {
5361  if (Op.getMachineOpcode() == PPC::CRSET)
5362  Op1Set = true;
5363  else if (Op.getMachineOpcode() == PPC::CRUNSET)
5364  Op1Unset = true;
5365  else if (Op.getMachineOpcode() == PPC::CRNOR &&
5366  Op.getOperand(0) == Op.getOperand(1))
5367  Op1Not = true;
5368  }
5369  }
5370  break;
5371  }
5372 
5373  bool SelectSwap = false;
5374  switch (Opcode) {
5375  default: break;
5376  case PPC::CRAND:
5377  if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
5378  // x & x = x
5379  ResNode = MachineNode->getOperand(0).getNode();
5380  else if (Op1Set)
5381  // 1 & y = y
5382  ResNode = MachineNode->getOperand(1).getNode();
5383  else if (Op2Set)
5384  // x & 1 = x
5385  ResNode = MachineNode->getOperand(0).getNode();
5386  else if (Op1Unset || Op2Unset)
5387  // x & 0 = 0 & y = 0
5388  ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
5389  MVT::i1);
5390  else if (Op1Not)
5391  // ~x & y = andc(y, x)
5392  ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
5393  MVT::i1, MachineNode->getOperand(1),
5394  MachineNode->getOperand(0).
5395  getOperand(0));
5396  else if (Op2Not)
5397  // x & ~y = andc(x, y)
5398  ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
5399  MVT::i1, MachineNode->getOperand(0),
5400  MachineNode->getOperand(1).
5401  getOperand(0));
5402  else if (AllUsersSelectZero(MachineNode)) {
5403  ResNode = CurDAG->getMachineNode(PPC::CRNAND, SDLoc(MachineNode),
5404  MVT::i1, MachineNode->getOperand(0),
5405  MachineNode->getOperand(1));
5406  SelectSwap = true;
5407  }
5408