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SelectionDAGISel.h
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1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the SelectionDAGISel class, which is used as the common
10 // base class for SelectionDAG-based instruction selectors.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_SELECTIONDAGISEL_H
15 #define LLVM_CODEGEN_SELECTIONDAGISEL_H
16 
20 #include "llvm/IR/BasicBlock.h"
21 #include "llvm/Pass.h"
22 #include <memory>
23 
24 namespace llvm {
25  class FastISel;
26  class SelectionDAGBuilder;
27  class SDValue;
28  class MachineRegisterInfo;
29  class MachineBasicBlock;
30  class MachineFunction;
31  class MachineInstr;
32  class OptimizationRemarkEmitter;
33  class TargetLowering;
34  class TargetLibraryInfo;
35  class FunctionLoweringInfo;
36  class ScheduleHazardRecognizer;
37  class SwiftErrorValueTracking;
38  class GCFunctionInfo;
39  class ScheduleDAGSDNodes;
40  class LoadInst;
41 
42 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
43 /// pattern-matching instruction selectors.
45 public:
61 
62  /// Current optimization remark emitter.
63  /// Used to report things like combines and FastISel failures.
64  std::unique_ptr<OptimizationRemarkEmitter> ORE;
65 
66  static char ID;
67 
68  explicit SelectionDAGISel(TargetMachine &tm,
70  ~SelectionDAGISel() override;
71 
72  const TargetLowering *getTargetLowering() const { return TLI; }
73 
74  void getAnalysisUsage(AnalysisUsage &AU) const override;
75 
76  bool runOnMachineFunction(MachineFunction &MF) override;
77 
78  virtual void EmitFunctionEntryCode() {}
79 
80  /// PreprocessISelDAG - This hook allows targets to hack on the graph before
81  /// instruction selection starts.
82  virtual void PreprocessISelDAG() {}
83 
84  /// PostprocessISelDAG() - This hook allows the target to hack on the graph
85  /// right after selection.
86  virtual void PostprocessISelDAG() {}
87 
88  /// Main hook for targets to transform nodes into machine nodes.
89  virtual void Select(SDNode *N) = 0;
90 
91  /// SelectInlineAsmMemoryOperand - Select the specified address as a target
92  /// addressing mode, according to the specified constraint. If this does
93  /// not match or is not implemented, return true. The resultant operands
94  /// (which will appear in the machine instruction) should be added to the
95  /// OutOps vector.
97  unsigned ConstraintID,
98  std::vector<SDValue> &OutOps) {
99  return true;
100  }
101 
102  /// IsProfitableToFold - Returns true if it's profitable to fold the specific
103  /// operand node N of U during instruction selection that starts at Root.
104  virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
105 
106  /// IsLegalToFold - Returns true if the specific operand node N of
107  /// U can be folded during instruction selection that starts at Root.
108  /// FIXME: This is a static member function because the MSP430/X86
109  /// targets, which uses it during isel. This could become a proper member.
110  static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
111  CodeGenOpt::Level OptLevel,
112  bool IgnoreChains = false);
113 
114  static void InvalidateNodeId(SDNode *N);
115  static int getUninvalidatedNodeId(SDNode *N);
116 
117  static void EnforceNodeIdInvariant(SDNode *N);
118 
119  // Opcodes used by the DAG state machine:
155 
167  // Space-optimized forms that implicitly encode number of result VTs.
170  // Space-optimized forms that implicitly encode number of result VTs.
173  // Contains offset in table for pattern being selected
175  };
176 
177  enum {
178  OPFL_None = 0, // Node has no chain or glue input and isn't variadic.
179  OPFL_Chain = 1, // Node has a chain input.
180  OPFL_GlueInput = 2, // Node has a glue input.
181  OPFL_GlueOutput = 4, // Node has a glue output.
182  OPFL_MemRefs = 8, // Node gets accumulated MemRefs.
183  OPFL_Variadic0 = 1<<4, // Node is variadic, root has 0 fixed inputs.
184  OPFL_Variadic1 = 2<<4, // Node is variadic, root has 1 fixed inputs.
185  OPFL_Variadic2 = 3<<4, // Node is variadic, root has 2 fixed inputs.
186  OPFL_Variadic3 = 4<<4, // Node is variadic, root has 3 fixed inputs.
187  OPFL_Variadic4 = 5<<4, // Node is variadic, root has 4 fixed inputs.
188  OPFL_Variadic5 = 6<<4, // Node is variadic, root has 5 fixed inputs.
189  OPFL_Variadic6 = 7<<4, // Node is variadic, root has 6 fixed inputs.
190 
192  };
193 
194  /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the
195  /// number of fixed arity values that should be skipped when copying from the
196  /// root.
197  static inline int getNumFixedFromVariadicInfo(unsigned Flags) {
198  return ((Flags&OPFL_VariadicInfo) >> 4)-1;
199  }
200 
201 
202 protected:
203  /// DAGSize - Size of DAG being instruction selected.
204  ///
205  unsigned DAGSize;
206 
207  /// ReplaceUses - replace all uses of the old node F with the use
208  /// of the new node T.
210  CurDAG->ReplaceAllUsesOfValueWith(F, T);
212  }
213 
214  /// ReplaceUses - replace all uses of the old nodes F with the use
215  /// of the new nodes T.
216  void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) {
217  CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num);
218  for (unsigned i = 0; i < Num; ++i)
219  EnforceNodeIdInvariant(T[i].getNode());
220  }
221 
222  /// ReplaceUses - replace all uses of the old node F with the use
223  /// of the new node T.
225  CurDAG->ReplaceAllUsesWith(F, T);
227  }
228 
229  /// Replace all uses of \c F with \c T, then remove \c F from the DAG.
231  CurDAG->ReplaceAllUsesWith(F, T);
233  CurDAG->RemoveDeadNode(F);
234  }
235 
236  /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
237  /// by tblgen. Others should not call it.
238  void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
239  const SDLoc &DL);
240 
241  /// getPatternForIndex - Patterns selected by tablegen during ISEL
242  virtual StringRef getPatternForIndex(unsigned index) {
243  llvm_unreachable("Tblgen should generate the implementation of this!");
244  }
245 
246  /// getIncludePathForIndex - get the td source location of pattern instantiation
247  virtual StringRef getIncludePathForIndex(unsigned index) {
248  llvm_unreachable("Tblgen should generate the implementation of this!");
249  }
250 public:
251  // Calls to these predicates are generated by tblgen.
252  bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
253  int64_t DesiredMaskS) const;
254  bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
255  int64_t DesiredMaskS) const;
256 
257 
258  /// CheckPatternPredicate - This function is generated by tblgen in the
259  /// target. It runs the specified pattern predicate and returns true if it
260  /// succeeds or false if it fails. The number is a private implementation
261  /// detail to the code tblgen produces.
262  virtual bool CheckPatternPredicate(unsigned PredNo) const {
263  llvm_unreachable("Tblgen should generate the implementation of this!");
264  }
265 
266  /// CheckNodePredicate - This function is generated by tblgen in the target.
267  /// It runs node predicate number PredNo and returns true if it succeeds or
268  /// false if it fails. The number is a private implementation
269  /// detail to the code tblgen produces.
270  virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const {
271  llvm_unreachable("Tblgen should generate the implementation of this!");
272  }
273 
274  /// CheckNodePredicateWithOperands - This function is generated by tblgen in
275  /// the target.
276  /// It runs node predicate number PredNo and returns true if it succeeds or
277  /// false if it fails. The number is a private implementation detail to the
278  /// code tblgen produces.
280  SDNode *N, unsigned PredNo,
281  const SmallVectorImpl<SDValue> &Operands) const {
282  llvm_unreachable("Tblgen should generate the implementation of this!");
283  }
284 
285  virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N,
286  unsigned PatternNo,
287  SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) {
288  llvm_unreachable("Tblgen should generate the implementation of this!");
289  }
290 
291  virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
292  llvm_unreachable("Tblgen should generate this!");
293  }
294 
295  void SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
296  unsigned TableSize);
297 
298  /// Return true if complex patterns for this target can mutate the
299  /// DAG.
300  virtual bool ComplexPatternFuncMutatesDAG() const {
301  return false;
302  }
303 
304  bool isOrEquivalentToAdd(const SDNode *N) const;
305 
306 private:
307 
308  // Calls to these functions are generated by tblgen.
309  void Select_INLINEASM(SDNode *N, bool Branch);
310  void Select_READ_REGISTER(SDNode *Op);
311  void Select_WRITE_REGISTER(SDNode *Op);
312  void Select_UNDEF(SDNode *N);
313  void CannotYetSelect(SDNode *N);
314 
315 private:
316  void DoInstructionSelection();
317  SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
318  ArrayRef<SDValue> Ops, unsigned EmitNodeInfo);
319 
320  SDNode *MutateStrictFPToFP(SDNode *Node, unsigned NewOpc);
321 
322  /// Prepares the landing pad to take incoming values or do other EH
323  /// personality specific tasks. Returns true if the block should be
324  /// instruction selected, false if no code should be emitted for it.
325  bool PrepareEHLandingPad();
326 
327  /// Perform instruction selection on all basic blocks in the function.
328  void SelectAllBasicBlocks(const Function &Fn);
329 
330  /// Perform instruction selection on a single basic block, for
331  /// instructions between \p Begin and \p End. \p HadTailCall will be set
332  /// to true if a call in the block was translated as a tail call.
333  void SelectBasicBlock(BasicBlock::const_iterator Begin,
335  bool &HadTailCall);
336  void FinishBasicBlock();
337 
338  void CodeGenAndEmitDAG();
339 
340  /// Generate instructions for lowering the incoming arguments of the
341  /// given function.
342  void LowerArguments(const Function &F);
343 
344  void ComputeLiveOutVRegInfo();
345 
346  /// Create the scheduler. If a specific scheduler was specified
347  /// via the SchedulerRegistry, use it, otherwise select the
348  /// one preferred by the target.
349  ///
350  ScheduleDAGSDNodes *CreateScheduler();
351 
352  /// OpcodeOffset - This is a cache used to dispatch efficiently into isel
353  /// state machines that start with a OPC_SwitchOpcode node.
354  std::vector<unsigned> OpcodeOffset;
355 
356  void UpdateChains(SDNode *NodeToMatch, SDValue InputChain,
357  SmallVectorImpl<SDNode *> &ChainNodesMatched,
358  bool isMorphNodeTo);
359 };
360 
361 }
362 
363 #endif /* LLVM_CODEGEN_SELECTIONDAGISEL_H */
void ReplaceUses(SDNode *F, SDNode *T)
ReplaceUses - replace all uses of the old node F with the use of the new node T.
SelectionDAGBuilder * SDB
static int getNumFixedFromVariadicInfo(unsigned Flags)
getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the number of fixed arity values ...
GCFunctionInfo * GFI
virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const
IsProfitableToFold - Returns true if it&#39;s profitable to fold the specific operand node N of U during ...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void ReplaceUses(SDValue F, SDValue T)
ReplaceUses - replace all uses of the old node F with the use of the new node T.
bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
CheckAndMask - The isel is trying to match something like (and X, 255).
SelectionDAGBuilder - This is the common target-independent lowering implementation that is parameter...
virtual bool CheckNodePredicateWithOperands(SDNode *N, unsigned PredNo, const SmallVectorImpl< SDValue > &Operands) const
CheckNodePredicateWithOperands - This function is generated by tblgen in the target.
F(f)
SDNode * getNode() const
get the SDNode which holds the desired result
MachineFunction * MF
void ReplaceAllUsesOfValuesWith(const SDValue *From, const SDValue *To, unsigned Num)
Like ReplaceAllUsesOfValueWith, but for multiple values at once.
const TargetLibraryInfo * LibInfo
InstListType::const_iterator const_iterator
Definition: BasicBlock.h:90
SwiftErrorValueTracking * SwiftError
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual bool ComplexPatternFuncMutatesDAG() const
Return true if complex patterns for this target can mutate the DAG.
static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, CodeGenOpt::Level OptLevel, bool IgnoreChains=false)
IsLegalToFold - Returns true if the specific operand node N of U can be folded during instruction sel...
const TargetLowering * TLI
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
virtual void Select(SDNode *N)=0
Main hook for targets to transform nodes into machine nodes.
static void EnforceNodeIdInvariant(SDNode *N)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
unsigned DAGSize
DAGSize - Size of DAG being instruction selected.
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual StringRef getPatternForIndex(unsigned index)
getPatternForIndex - Patterns selected by tablegen during ISEL
static void InvalidateNodeId(SDNode *N)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
TargetInstrInfo - Interface to description of machine instruction set.
MachineRegisterInfo * RegInfo
virtual bool CheckPatternPredicate(unsigned PredNo) const
CheckPatternPredicate - This function is generated by tblgen in the target.
SmallPtrSet< const Instruction *, 4 > ElidedArgCopyInstrs
CodeGenOpt::Level OptLevel
ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
Represent the analysis usage information of a pass.
virtual void EmitFunctionEntryCode()
void ReplaceAllUsesWith(SDValue From, SDValue To)
Modify anything using &#39;From&#39; to use &#39;To&#39; instead.
virtual void PostprocessISelDAG()
PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection...
void RemoveDeadNode(SDNode *N)
Remove the specified node from the system.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isOrEquivalentToAdd(const SDNode *N) const
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Definition: SmallPtrSet.h:417
virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N, unsigned PatternNo, SmallVectorImpl< std::pair< SDValue, SDNode *> > &Result)
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
Provides information about what library functions are available for the current target.
SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL=CodeGenOpt::Default)
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const
CheckNodePredicate - This function is generated by tblgen in the target.
std::unique_ptr< OptimizationRemarkEmitter > ORE
Current optimization remark emitter.
const TargetLowering * getTargetLowering() const
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector< SDValue > &OutOps)
SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode...
bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
CheckOrMask - The isel is trying to match something like (or X, 255).
void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num)
ReplaceUses - replace all uses of the old nodes F with the use of the new nodes T.
void SelectInlineAsmMemoryOperands(std::vector< SDValue > &Ops, const SDLoc &DL)
SelectInlineAsmMemoryOperands - Calls to this are automatically generated by tblgen.
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
void ReplaceNode(SDNode *F, SDNode *T)
Replace all uses of F with T, then remove F from the DAG.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
Garbage collection metadata for a single function.
Definition: GCMetadata.h:77
virtual void PreprocessISelDAG()
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
virtual StringRef getIncludePathForIndex(unsigned index)
getIncludePathForIndex - get the td source location of pattern instantiation
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const TargetInstrInfo * TII
FunctionLoweringInfo * FuncInfo
virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo)
void SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, unsigned TableSize)
static int getUninvalidatedNodeId(SDNode *N)