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SelectionDAGISel.h
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1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the SelectionDAGISel class, which is used as the common
11 // base class for SelectionDAG-based instruction selectors.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_SELECTIONDAGISEL_H
16 #define LLVM_CODEGEN_SELECTIONDAGISEL_H
17 
21 #include "llvm/IR/BasicBlock.h"
22 #include "llvm/Pass.h"
23 #include <memory>
24 
25 namespace llvm {
26  class FastISel;
27  class SelectionDAGBuilder;
28  class SDValue;
29  class MachineRegisterInfo;
30  class MachineBasicBlock;
31  class MachineFunction;
32  class MachineInstr;
33  class OptimizationRemarkEmitter;
34  class TargetLowering;
35  class TargetLibraryInfo;
36  class FunctionLoweringInfo;
37  class ScheduleHazardRecognizer;
38  class GCFunctionInfo;
39  class ScheduleDAGSDNodes;
40  class LoadInst;
41 
42 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
43 /// pattern-matching instruction selectors.
45 public:
60 
61  /// Current optimization remark emitter.
62  /// Used to report things like combines and FastISel failures.
63  std::unique_ptr<OptimizationRemarkEmitter> ORE;
64 
65  static char ID;
66 
67  explicit SelectionDAGISel(TargetMachine &tm,
69  ~SelectionDAGISel() override;
70 
71  const TargetLowering *getTargetLowering() const { return TLI; }
72 
73  void getAnalysisUsage(AnalysisUsage &AU) const override;
74 
75  bool runOnMachineFunction(MachineFunction &MF) override;
76 
77  virtual void EmitFunctionEntryCode() {}
78 
79  /// PreprocessISelDAG - This hook allows targets to hack on the graph before
80  /// instruction selection starts.
81  virtual void PreprocessISelDAG() {}
82 
83  /// PostprocessISelDAG() - This hook allows the target to hack on the graph
84  /// right after selection.
85  virtual void PostprocessISelDAG() {}
86 
87  /// Main hook for targets to transform nodes into machine nodes.
88  virtual void Select(SDNode *N) = 0;
89 
90  /// SelectInlineAsmMemoryOperand - Select the specified address as a target
91  /// addressing mode, according to the specified constraint. If this does
92  /// not match or is not implemented, return true. The resultant operands
93  /// (which will appear in the machine instruction) should be added to the
94  /// OutOps vector.
96  unsigned ConstraintID,
97  std::vector<SDValue> &OutOps) {
98  return true;
99  }
100 
101  /// IsProfitableToFold - Returns true if it's profitable to fold the specific
102  /// operand node N of U during instruction selection that starts at Root.
103  virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
104 
105  /// IsLegalToFold - Returns true if the specific operand node N of
106  /// U can be folded during instruction selection that starts at Root.
107  /// FIXME: This is a static member function because the MSP430/X86
108  /// targets, which uses it during isel. This could become a proper member.
109  static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
110  CodeGenOpt::Level OptLevel,
111  bool IgnoreChains = false);
112 
113  static void InvalidateNodeId(SDNode *N);
114  static int getUninvalidatedNodeId(SDNode *N);
115 
116  static void EnforceNodeIdInvariant(SDNode *N);
117 
118  // Opcodes used by the DAG state machine:
152 
164  // Space-optimized forms that implicitly encode number of result VTs.
167  // Space-optimized forms that implicitly encode number of result VTs.
170  // Contains offset in table for pattern being selected
172  };
173 
174  enum {
175  OPFL_None = 0, // Node has no chain or glue input and isn't variadic.
176  OPFL_Chain = 1, // Node has a chain input.
177  OPFL_GlueInput = 2, // Node has a glue input.
178  OPFL_GlueOutput = 4, // Node has a glue output.
179  OPFL_MemRefs = 8, // Node gets accumulated MemRefs.
180  OPFL_Variadic0 = 1<<4, // Node is variadic, root has 0 fixed inputs.
181  OPFL_Variadic1 = 2<<4, // Node is variadic, root has 1 fixed inputs.
182  OPFL_Variadic2 = 3<<4, // Node is variadic, root has 2 fixed inputs.
183  OPFL_Variadic3 = 4<<4, // Node is variadic, root has 3 fixed inputs.
184  OPFL_Variadic4 = 5<<4, // Node is variadic, root has 4 fixed inputs.
185  OPFL_Variadic5 = 6<<4, // Node is variadic, root has 5 fixed inputs.
186  OPFL_Variadic6 = 7<<4, // Node is variadic, root has 6 fixed inputs.
187 
189  };
190 
191  /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the
192  /// number of fixed arity values that should be skipped when copying from the
193  /// root.
194  static inline int getNumFixedFromVariadicInfo(unsigned Flags) {
195  return ((Flags&OPFL_VariadicInfo) >> 4)-1;
196  }
197 
198 
199 protected:
200  /// DAGSize - Size of DAG being instruction selected.
201  ///
202  unsigned DAGSize;
203 
204  /// ReplaceUses - replace all uses of the old node F with the use
205  /// of the new node T.
207  CurDAG->ReplaceAllUsesOfValueWith(F, T);
209  }
210 
211  /// ReplaceUses - replace all uses of the old nodes F with the use
212  /// of the new nodes T.
213  void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) {
214  CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num);
215  for (unsigned i = 0; i < Num; ++i)
216  EnforceNodeIdInvariant(T[i].getNode());
217  }
218 
219  /// ReplaceUses - replace all uses of the old node F with the use
220  /// of the new node T.
222  CurDAG->ReplaceAllUsesWith(F, T);
224  }
225 
226  /// Replace all uses of \c F with \c T, then remove \c F from the DAG.
228  CurDAG->ReplaceAllUsesWith(F, T);
230  CurDAG->RemoveDeadNode(F);
231  }
232 
233  /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
234  /// by tblgen. Others should not call it.
235  void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
236  const SDLoc &DL);
237 
238  /// getPatternForIndex - Patterns selected by tablegen during ISEL
239  virtual StringRef getPatternForIndex(unsigned index) {
240  llvm_unreachable("Tblgen should generate the implementation of this!");
241  }
242 
243  /// getIncludePathForIndex - get the td source location of pattern instantiation
244  virtual StringRef getIncludePathForIndex(unsigned index) {
245  llvm_unreachable("Tblgen should generate the implementation of this!");
246  }
247 public:
248  // Calls to these predicates are generated by tblgen.
249  bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
250  int64_t DesiredMaskS) const;
251  bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
252  int64_t DesiredMaskS) const;
253 
254 
255  /// CheckPatternPredicate - This function is generated by tblgen in the
256  /// target. It runs the specified pattern predicate and returns true if it
257  /// succeeds or false if it fails. The number is a private implementation
258  /// detail to the code tblgen produces.
259  virtual bool CheckPatternPredicate(unsigned PredNo) const {
260  llvm_unreachable("Tblgen should generate the implementation of this!");
261  }
262 
263  /// CheckNodePredicate - This function is generated by tblgen in the target.
264  /// It runs node predicate number PredNo and returns true if it succeeds or
265  /// false if it fails. The number is a private implementation
266  /// detail to the code tblgen produces.
267  virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const {
268  llvm_unreachable("Tblgen should generate the implementation of this!");
269  }
270 
271  /// CheckNodePredicateWithOperands - This function is generated by tblgen in
272  /// the target.
273  /// It runs node predicate number PredNo and returns true if it succeeds or
274  /// false if it fails. The number is a private implementation detail to the
275  /// code tblgen produces.
277  SDNode *N, unsigned PredNo,
278  const SmallVectorImpl<SDValue> &Operands) const {
279  llvm_unreachable("Tblgen should generate the implementation of this!");
280  }
281 
282  virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N,
283  unsigned PatternNo,
284  SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) {
285  llvm_unreachable("Tblgen should generate the implementation of this!");
286  }
287 
288  virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
289  llvm_unreachable("Tblgen should generate this!");
290  }
291 
292  void SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
293  unsigned TableSize);
294 
295  /// Return true if complex patterns for this target can mutate the
296  /// DAG.
297  virtual bool ComplexPatternFuncMutatesDAG() const {
298  return false;
299  }
300 
301  bool isOrEquivalentToAdd(const SDNode *N) const;
302 
303 private:
304 
305  // Calls to these functions are generated by tblgen.
306  void Select_INLINEASM(SDNode *N);
307  void Select_READ_REGISTER(SDNode *Op);
308  void Select_WRITE_REGISTER(SDNode *Op);
309  void Select_UNDEF(SDNode *N);
310  void CannotYetSelect(SDNode *N);
311 
312 private:
313  void DoInstructionSelection();
314  SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
315  ArrayRef<SDValue> Ops, unsigned EmitNodeInfo);
316 
317  SDNode *MutateStrictFPToFP(SDNode *Node, unsigned NewOpc);
318 
319  /// Prepares the landing pad to take incoming values or do other EH
320  /// personality specific tasks. Returns true if the block should be
321  /// instruction selected, false if no code should be emitted for it.
322  bool PrepareEHLandingPad();
323 
324  /// Perform instruction selection on all basic blocks in the function.
325  void SelectAllBasicBlocks(const Function &Fn);
326 
327  /// Perform instruction selection on a single basic block, for
328  /// instructions between \p Begin and \p End. \p HadTailCall will be set
329  /// to true if a call in the block was translated as a tail call.
330  void SelectBasicBlock(BasicBlock::const_iterator Begin,
332  bool &HadTailCall);
333  void FinishBasicBlock();
334 
335  void CodeGenAndEmitDAG();
336 
337  /// Generate instructions for lowering the incoming arguments of the
338  /// given function.
339  void LowerArguments(const Function &F);
340 
341  void ComputeLiveOutVRegInfo();
342 
343  /// Create the scheduler. If a specific scheduler was specified
344  /// via the SchedulerRegistry, use it, otherwise select the
345  /// one preferred by the target.
346  ///
347  ScheduleDAGSDNodes *CreateScheduler();
348 
349  /// OpcodeOffset - This is a cache used to dispatch efficiently into isel
350  /// state machines that start with a OPC_SwitchOpcode node.
351  std::vector<unsigned> OpcodeOffset;
352 
353  void UpdateChains(SDNode *NodeToMatch, SDValue InputChain,
354  SmallVectorImpl<SDNode *> &ChainNodesMatched,
355  bool isMorphNodeTo);
356 };
357 
358 }
359 
360 #endif /* LLVM_CODEGEN_SELECTIONDAGISEL_H */
void ReplaceUses(SDNode *F, SDNode *T)
ReplaceUses - replace all uses of the old node F with the use of the new node T.
SelectionDAGBuilder * SDB
static int getNumFixedFromVariadicInfo(unsigned Flags)
getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the number of fixed arity values ...
GCFunctionInfo * GFI
virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const
IsProfitableToFold - Returns true if it&#39;s profitable to fold the specific operand node N of U during ...
This class represents lattice values for constants.
Definition: AllocatorList.h:24
void ReplaceUses(SDValue F, SDValue T)
ReplaceUses - replace all uses of the old node F with the use of the new node T.
bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
CheckAndMask - The isel is trying to match something like (and X, 255).
SelectionDAGBuilder - This is the common target-independent lowering implementation that is parameter...
virtual bool CheckNodePredicateWithOperands(SDNode *N, unsigned PredNo, const SmallVectorImpl< SDValue > &Operands) const
CheckNodePredicateWithOperands - This function is generated by tblgen in the target.
F(f)
SDNode * getNode() const
get the SDNode which holds the desired result
MachineFunction * MF
void ReplaceAllUsesOfValuesWith(const SDValue *From, const SDValue *To, unsigned Num)
Like ReplaceAllUsesOfValueWith, but for multiple values at once.
const TargetLibraryInfo * LibInfo
InstListType::const_iterator const_iterator
Definition: BasicBlock.h:91
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual bool ComplexPatternFuncMutatesDAG() const
Return true if complex patterns for this target can mutate the DAG.
static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, CodeGenOpt::Level OptLevel, bool IgnoreChains=false)
IsLegalToFold - Returns true if the specific operand node N of U can be folded during instruction sel...
const TargetLowering * TLI
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
virtual void Select(SDNode *N)=0
Main hook for targets to transform nodes into machine nodes.
static void EnforceNodeIdInvariant(SDNode *N)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
unsigned DAGSize
DAGSize - Size of DAG being instruction selected.
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual StringRef getPatternForIndex(unsigned index)
getPatternForIndex - Patterns selected by tablegen during ISEL
static void InvalidateNodeId(SDNode *N)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
TargetInstrInfo - Interface to description of machine instruction set.
MachineRegisterInfo * RegInfo
virtual bool CheckPatternPredicate(unsigned PredNo) const
CheckPatternPredicate - This function is generated by tblgen in the target.
SmallPtrSet< const Instruction *, 4 > ElidedArgCopyInstrs
CodeGenOpt::Level OptLevel
ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
Represent the analysis usage information of a pass.
virtual void EmitFunctionEntryCode()
void ReplaceAllUsesWith(SDValue From, SDValue To)
Modify anything using &#39;From&#39; to use &#39;To&#39; instead.
virtual void PostprocessISelDAG()
PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection...
void RemoveDeadNode(SDNode *N)
Remove the specified node from the system.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isOrEquivalentToAdd(const SDNode *N) const
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Definition: SmallPtrSet.h:418
virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N, unsigned PatternNo, SmallVectorImpl< std::pair< SDValue, SDNode *> > &Result)
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:222
Provides information about what library functions are available for the current target.
SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL=CodeGenOpt::Default)
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const
CheckNodePredicate - This function is generated by tblgen in the target.
std::unique_ptr< OptimizationRemarkEmitter > ORE
Current optimization remark emitter.
const TargetLowering * getTargetLowering() const
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector< SDValue > &OutOps)
SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode...
bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
CheckOrMask - The isel is trying to match something like (or X, 255).
void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num)
ReplaceUses - replace all uses of the old nodes F with the use of the new nodes T.
void SelectInlineAsmMemoryOperands(std::vector< SDValue > &Ops, const SDLoc &DL)
SelectInlineAsmMemoryOperands - Calls to this are automatically generated by tblgen.
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
void ReplaceNode(SDNode *F, SDNode *T)
Replace all uses of F with T, then remove F from the DAG.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
Garbage collection metadata for a single function.
Definition: GCMetadata.h:78
virtual void PreprocessISelDAG()
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
virtual StringRef getIncludePathForIndex(unsigned index)
getIncludePathForIndex - get the td source location of pattern instantiation
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const TargetInstrInfo * TII
FunctionLoweringInfo * FuncInfo
virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo)
void SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, unsigned TableSize)
static int getUninvalidatedNodeId(SDNode *N)