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SelectionDAGISel.h
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1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the SelectionDAGISel class, which is used as the common
10 // base class for SelectionDAG-based instruction selectors.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_SELECTIONDAGISEL_H
15 #define LLVM_CODEGEN_SELECTIONDAGISEL_H
16 
20 #include "llvm/IR/BasicBlock.h"
21 #include "llvm/Pass.h"
22 #include <memory>
23 
24 namespace llvm {
25  class FastISel;
26  class SelectionDAGBuilder;
27  class SDValue;
28  class MachineRegisterInfo;
29  class MachineBasicBlock;
30  class MachineFunction;
31  class MachineInstr;
32  class OptimizationRemarkEmitter;
33  class TargetLowering;
34  class TargetLibraryInfo;
35  class FunctionLoweringInfo;
36  class ScheduleHazardRecognizer;
37  class GCFunctionInfo;
38  class ScheduleDAGSDNodes;
39  class LoadInst;
40 
41 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
42 /// pattern-matching instruction selectors.
44 public:
59 
60  /// Current optimization remark emitter.
61  /// Used to report things like combines and FastISel failures.
62  std::unique_ptr<OptimizationRemarkEmitter> ORE;
63 
64  static char ID;
65 
66  explicit SelectionDAGISel(TargetMachine &tm,
68  ~SelectionDAGISel() override;
69 
70  const TargetLowering *getTargetLowering() const { return TLI; }
71 
72  void getAnalysisUsage(AnalysisUsage &AU) const override;
73 
74  bool runOnMachineFunction(MachineFunction &MF) override;
75 
76  virtual void EmitFunctionEntryCode() {}
77 
78  /// PreprocessISelDAG - This hook allows targets to hack on the graph before
79  /// instruction selection starts.
80  virtual void PreprocessISelDAG() {}
81 
82  /// PostprocessISelDAG() - This hook allows the target to hack on the graph
83  /// right after selection.
84  virtual void PostprocessISelDAG() {}
85 
86  /// Main hook for targets to transform nodes into machine nodes.
87  virtual void Select(SDNode *N) = 0;
88 
89  /// SelectInlineAsmMemoryOperand - Select the specified address as a target
90  /// addressing mode, according to the specified constraint. If this does
91  /// not match or is not implemented, return true. The resultant operands
92  /// (which will appear in the machine instruction) should be added to the
93  /// OutOps vector.
95  unsigned ConstraintID,
96  std::vector<SDValue> &OutOps) {
97  return true;
98  }
99 
100  /// IsProfitableToFold - Returns true if it's profitable to fold the specific
101  /// operand node N of U during instruction selection that starts at Root.
102  virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
103 
104  /// IsLegalToFold - Returns true if the specific operand node N of
105  /// U can be folded during instruction selection that starts at Root.
106  /// FIXME: This is a static member function because the MSP430/X86
107  /// targets, which uses it during isel. This could become a proper member.
108  static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
109  CodeGenOpt::Level OptLevel,
110  bool IgnoreChains = false);
111 
112  static void InvalidateNodeId(SDNode *N);
113  static int getUninvalidatedNodeId(SDNode *N);
114 
115  static void EnforceNodeIdInvariant(SDNode *N);
116 
117  // Opcodes used by the DAG state machine:
153 
165  // Space-optimized forms that implicitly encode number of result VTs.
168  // Space-optimized forms that implicitly encode number of result VTs.
171  // Contains offset in table for pattern being selected
173  };
174 
175  enum {
176  OPFL_None = 0, // Node has no chain or glue input and isn't variadic.
177  OPFL_Chain = 1, // Node has a chain input.
178  OPFL_GlueInput = 2, // Node has a glue input.
179  OPFL_GlueOutput = 4, // Node has a glue output.
180  OPFL_MemRefs = 8, // Node gets accumulated MemRefs.
181  OPFL_Variadic0 = 1<<4, // Node is variadic, root has 0 fixed inputs.
182  OPFL_Variadic1 = 2<<4, // Node is variadic, root has 1 fixed inputs.
183  OPFL_Variadic2 = 3<<4, // Node is variadic, root has 2 fixed inputs.
184  OPFL_Variadic3 = 4<<4, // Node is variadic, root has 3 fixed inputs.
185  OPFL_Variadic4 = 5<<4, // Node is variadic, root has 4 fixed inputs.
186  OPFL_Variadic5 = 6<<4, // Node is variadic, root has 5 fixed inputs.
187  OPFL_Variadic6 = 7<<4, // Node is variadic, root has 6 fixed inputs.
188 
190  };
191 
192  /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the
193  /// number of fixed arity values that should be skipped when copying from the
194  /// root.
195  static inline int getNumFixedFromVariadicInfo(unsigned Flags) {
196  return ((Flags&OPFL_VariadicInfo) >> 4)-1;
197  }
198 
199 
200 protected:
201  /// DAGSize - Size of DAG being instruction selected.
202  ///
203  unsigned DAGSize;
204 
205  /// ReplaceUses - replace all uses of the old node F with the use
206  /// of the new node T.
208  CurDAG->ReplaceAllUsesOfValueWith(F, T);
210  }
211 
212  /// ReplaceUses - replace all uses of the old nodes F with the use
213  /// of the new nodes T.
214  void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) {
215  CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num);
216  for (unsigned i = 0; i < Num; ++i)
217  EnforceNodeIdInvariant(T[i].getNode());
218  }
219 
220  /// ReplaceUses - replace all uses of the old node F with the use
221  /// of the new node T.
223  CurDAG->ReplaceAllUsesWith(F, T);
225  }
226 
227  /// Replace all uses of \c F with \c T, then remove \c F from the DAG.
229  CurDAG->ReplaceAllUsesWith(F, T);
231  CurDAG->RemoveDeadNode(F);
232  }
233 
234  /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
235  /// by tblgen. Others should not call it.
236  void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
237  const SDLoc &DL);
238 
239  /// getPatternForIndex - Patterns selected by tablegen during ISEL
240  virtual StringRef getPatternForIndex(unsigned index) {
241  llvm_unreachable("Tblgen should generate the implementation of this!");
242  }
243 
244  /// getIncludePathForIndex - get the td source location of pattern instantiation
245  virtual StringRef getIncludePathForIndex(unsigned index) {
246  llvm_unreachable("Tblgen should generate the implementation of this!");
247  }
248 public:
249  // Calls to these predicates are generated by tblgen.
250  bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
251  int64_t DesiredMaskS) const;
252  bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
253  int64_t DesiredMaskS) const;
254 
255 
256  /// CheckPatternPredicate - This function is generated by tblgen in the
257  /// target. It runs the specified pattern predicate and returns true if it
258  /// succeeds or false if it fails. The number is a private implementation
259  /// detail to the code tblgen produces.
260  virtual bool CheckPatternPredicate(unsigned PredNo) const {
261  llvm_unreachable("Tblgen should generate the implementation of this!");
262  }
263 
264  /// CheckNodePredicate - This function is generated by tblgen in the target.
265  /// It runs node predicate number PredNo and returns true if it succeeds or
266  /// false if it fails. The number is a private implementation
267  /// detail to the code tblgen produces.
268  virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const {
269  llvm_unreachable("Tblgen should generate the implementation of this!");
270  }
271 
272  /// CheckNodePredicateWithOperands - This function is generated by tblgen in
273  /// the target.
274  /// It runs node predicate number PredNo and returns true if it succeeds or
275  /// false if it fails. The number is a private implementation detail to the
276  /// code tblgen produces.
278  SDNode *N, unsigned PredNo,
279  const SmallVectorImpl<SDValue> &Operands) const {
280  llvm_unreachable("Tblgen should generate the implementation of this!");
281  }
282 
283  virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N,
284  unsigned PatternNo,
285  SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) {
286  llvm_unreachable("Tblgen should generate the implementation of this!");
287  }
288 
289  virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
290  llvm_unreachable("Tblgen should generate this!");
291  }
292 
293  void SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
294  unsigned TableSize);
295 
296  /// Return true if complex patterns for this target can mutate the
297  /// DAG.
298  virtual bool ComplexPatternFuncMutatesDAG() const {
299  return false;
300  }
301 
302  bool isOrEquivalentToAdd(const SDNode *N) const;
303 
304 private:
305 
306  // Calls to these functions are generated by tblgen.
307  void Select_INLINEASM(SDNode *N, bool Branch);
308  void Select_READ_REGISTER(SDNode *Op);
309  void Select_WRITE_REGISTER(SDNode *Op);
310  void Select_UNDEF(SDNode *N);
311  void CannotYetSelect(SDNode *N);
312 
313 private:
314  void DoInstructionSelection();
315  SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
316  ArrayRef<SDValue> Ops, unsigned EmitNodeInfo);
317 
318  SDNode *MutateStrictFPToFP(SDNode *Node, unsigned NewOpc);
319 
320  /// Prepares the landing pad to take incoming values or do other EH
321  /// personality specific tasks. Returns true if the block should be
322  /// instruction selected, false if no code should be emitted for it.
323  bool PrepareEHLandingPad();
324 
325  /// Perform instruction selection on all basic blocks in the function.
326  void SelectAllBasicBlocks(const Function &Fn);
327 
328  /// Perform instruction selection on a single basic block, for
329  /// instructions between \p Begin and \p End. \p HadTailCall will be set
330  /// to true if a call in the block was translated as a tail call.
331  void SelectBasicBlock(BasicBlock::const_iterator Begin,
333  bool &HadTailCall);
334  void FinishBasicBlock();
335 
336  void CodeGenAndEmitDAG();
337 
338  /// Generate instructions for lowering the incoming arguments of the
339  /// given function.
340  void LowerArguments(const Function &F);
341 
342  void ComputeLiveOutVRegInfo();
343 
344  /// Create the scheduler. If a specific scheduler was specified
345  /// via the SchedulerRegistry, use it, otherwise select the
346  /// one preferred by the target.
347  ///
348  ScheduleDAGSDNodes *CreateScheduler();
349 
350  /// OpcodeOffset - This is a cache used to dispatch efficiently into isel
351  /// state machines that start with a OPC_SwitchOpcode node.
352  std::vector<unsigned> OpcodeOffset;
353 
354  void UpdateChains(SDNode *NodeToMatch, SDValue InputChain,
355  SmallVectorImpl<SDNode *> &ChainNodesMatched,
356  bool isMorphNodeTo);
357 };
358 
359 }
360 
361 #endif /* LLVM_CODEGEN_SELECTIONDAGISEL_H */
void ReplaceUses(SDNode *F, SDNode *T)
ReplaceUses - replace all uses of the old node F with the use of the new node T.
SelectionDAGBuilder * SDB
static int getNumFixedFromVariadicInfo(unsigned Flags)
getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the number of fixed arity values ...
GCFunctionInfo * GFI
virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const
IsProfitableToFold - Returns true if it&#39;s profitable to fold the specific operand node N of U during ...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void ReplaceUses(SDValue F, SDValue T)
ReplaceUses - replace all uses of the old node F with the use of the new node T.
bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
CheckAndMask - The isel is trying to match something like (and X, 255).
SelectionDAGBuilder - This is the common target-independent lowering implementation that is parameter...
virtual bool CheckNodePredicateWithOperands(SDNode *N, unsigned PredNo, const SmallVectorImpl< SDValue > &Operands) const
CheckNodePredicateWithOperands - This function is generated by tblgen in the target.
F(f)
SDNode * getNode() const
get the SDNode which holds the desired result
MachineFunction * MF
void ReplaceAllUsesOfValuesWith(const SDValue *From, const SDValue *To, unsigned Num)
Like ReplaceAllUsesOfValueWith, but for multiple values at once.
const TargetLibraryInfo * LibInfo
InstListType::const_iterator const_iterator
Definition: BasicBlock.h:90
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual bool ComplexPatternFuncMutatesDAG() const
Return true if complex patterns for this target can mutate the DAG.
static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, CodeGenOpt::Level OptLevel, bool IgnoreChains=false)
IsLegalToFold - Returns true if the specific operand node N of U can be folded during instruction sel...
const TargetLowering * TLI
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
virtual void Select(SDNode *N)=0
Main hook for targets to transform nodes into machine nodes.
static void EnforceNodeIdInvariant(SDNode *N)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
unsigned DAGSize
DAGSize - Size of DAG being instruction selected.
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual StringRef getPatternForIndex(unsigned index)
getPatternForIndex - Patterns selected by tablegen during ISEL
static void InvalidateNodeId(SDNode *N)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
TargetInstrInfo - Interface to description of machine instruction set.
MachineRegisterInfo * RegInfo
virtual bool CheckPatternPredicate(unsigned PredNo) const
CheckPatternPredicate - This function is generated by tblgen in the target.
SmallPtrSet< const Instruction *, 4 > ElidedArgCopyInstrs
CodeGenOpt::Level OptLevel
ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
Represent the analysis usage information of a pass.
virtual void EmitFunctionEntryCode()
void ReplaceAllUsesWith(SDValue From, SDValue To)
Modify anything using &#39;From&#39; to use &#39;To&#39; instead.
virtual void PostprocessISelDAG()
PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection...
void RemoveDeadNode(SDNode *N)
Remove the specified node from the system.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isOrEquivalentToAdd(const SDNode *N) const
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Definition: SmallPtrSet.h:417
virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N, unsigned PatternNo, SmallVectorImpl< std::pair< SDValue, SDNode *> > &Result)
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
Provides information about what library functions are available for the current target.
SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL=CodeGenOpt::Default)
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const
CheckNodePredicate - This function is generated by tblgen in the target.
std::unique_ptr< OptimizationRemarkEmitter > ORE
Current optimization remark emitter.
const TargetLowering * getTargetLowering() const
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector< SDValue > &OutOps)
SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode...
bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
CheckOrMask - The isel is trying to match something like (or X, 255).
void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num)
ReplaceUses - replace all uses of the old nodes F with the use of the new nodes T.
void SelectInlineAsmMemoryOperands(std::vector< SDValue > &Ops, const SDLoc &DL)
SelectInlineAsmMemoryOperands - Calls to this are automatically generated by tblgen.
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
void ReplaceNode(SDNode *F, SDNode *T)
Replace all uses of F with T, then remove F from the DAG.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
Garbage collection metadata for a single function.
Definition: GCMetadata.h:77
virtual void PreprocessISelDAG()
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
virtual StringRef getIncludePathForIndex(unsigned index)
getIncludePathForIndex - get the td source location of pattern instantiation
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const TargetInstrInfo * TII
FunctionLoweringInfo * FuncInfo
virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo)
void SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, unsigned TableSize)
static int getUninvalidatedNodeId(SDNode *N)