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llvm::ScheduleDAGSDNodes Class Referenceabstract

ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs. More...

#include "CodeGen/SelectionDAG/ScheduleDAGSDNodes.h"

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Classes

class  RegDefIter
 RegDefIter - In place iteration over the values defined by an SUnit. More...
 

Public Member Functions

 ScheduleDAGSDNodes (MachineFunction &mf)
 
 ~ScheduleDAGSDNodes () override=default
 
void Run (SelectionDAG *dag, MachineBasicBlock *bb)
 Run - perform scheduling. More...
 
SUnitnewSUnit (SDNode *N)
 NewSUnit - Creates a new SUnit and return a ptr to it. More...
 
SUnitClone (SUnit *N)
 Clone - Creates a clone of the specified SUnit. More...
 
void BuildSchedGraph (AliasAnalysis *AA)
 BuildSchedGraph - Build the SUnit graph from the selection dag that we are input. More...
 
void InitNumRegDefsLeft (SUnit *SU)
 InitNumRegDefsLeft - Determine the # of regs defined by this node. More...
 
virtual void computeLatency (SUnit *SU)
 computeLatency - Compute node latency. More...
 
virtual void computeOperandLatency (SDNode *Def, SDNode *Use, unsigned OpIdx, SDep &dep) const
 
virtual void Schedule ()=0
 Schedule - Order nodes according to selected style, filling in the Sequence member. More...
 
void VerifyScheduledSequence (bool isBottomUp)
 VerifyScheduledSequence - Verify that all SUnits are scheduled and consistent with the Sequence of scheduled instructions. More...
 
virtual MachineBasicBlockEmitSchedule (MachineBasicBlock::iterator &InsertPos)
 EmitSchedule - Insert MachineInstrs into the MachineBasicBlock according to the order specified in Sequence. More...
 
void dumpNode (const SUnit *SU) const override
 
void dumpSchedule () const
 
std::string getGraphNodeLabel (const SUnit *SU) const override
 Returns a label for an SUnit node in a visualization of the ScheduleDAG. More...
 
std::string getDAGName () const override
 Return the basic block label. More...
 
virtual void getCustomGraphFeatures (GraphWriter< ScheduleDAG *> &GW) const
 
- Public Member Functions inherited from llvm::ScheduleDAG
 ScheduleDAG (MachineFunction &mf)
 
virtual ~ScheduleDAG ()
 
void clearDAG ()
 Clears the DAG state (between regions). More...
 
const MCInstrDescgetInstrDesc (const SUnit *SU) const
 Returns the MCInstrDesc of this SUnit. More...
 
virtual void viewGraph (const Twine &Name, const Twine &Title)
 Pops up a GraphViz/gv window with the ScheduleDAG rendered using 'dot'. More...
 
virtual void viewGraph ()
 Out-of-line implementation with no arguments is handy for gdb. More...
 
virtual void addCustomGraphFeatures (GraphWriter< ScheduleDAG *> &) const
 Adds custom features for a visualization of the ScheduleDAG. More...
 
unsigned VerifyScheduledDAG (bool isBottomUp)
 Verifies that all SUnits were scheduled and that their state is consistent. More...
 

Static Public Member Functions

static bool isPassiveNode (SDNode *Node)
 isPassiveNode - Return true if the node is a non-scheduled leaf. More...
 

Public Attributes

MachineBasicBlockBB
 
SelectionDAGDAG
 
const InstrItineraryDataInstrItins
 
std::vector< SUnit * > Sequence
 The schedule. Null SUnit*'s represent noop instructions. More...
 
- Public Attributes inherited from llvm::ScheduleDAG
const TargetMachineTM
 Target processor. More...
 
const TargetInstrInfoTII
 Target instruction information. More...
 
const TargetRegisterInfoTRI
 Target processor register info. More...
 
MachineFunctionMF
 Machine function. More...
 
MachineRegisterInfoMRI
 Virtual/real register map. More...
 
std::vector< SUnitSUnits
 The scheduling units. More...
 
SUnit EntrySU
 Special node for the region entry. More...
 
SUnit ExitSU
 Special node for the region exit. More...
 
bool StressSched
 

Protected Member Functions

virtual bool forceUnitLatencies () const
 ForceUnitLatencies - Return true if all scheduling edges should be given a latency value of one. More...
 

Detailed Description

ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.

Edges between SUnits are initially based on edges in the SelectionDAG, and additional edges can be added by the schedulers as heuristics. SDNodes such as Constants, Registers, and a few others that are not interesting to schedulers are not allocated SUnits.

SDNodes with MVT::Glue operands are grouped along with the flagged nodes into a single SUnit so that they are scheduled together.

SDNode-based scheduling graphs do not use SDep::Anti or SDep::Output edges. Physical register dependence information is not carried in the DAG and must be handled explicitly by schedulers.

Definition at line 46 of file ScheduleDAGSDNodes.h.

Constructor & Destructor Documentation

◆ ScheduleDAGSDNodes()

ScheduleDAGSDNodes::ScheduleDAGSDNodes ( MachineFunction mf)
explicit

Definition at line 48 of file ScheduleDAGSDNodes.cpp.

◆ ~ScheduleDAGSDNodes()

llvm::ScheduleDAGSDNodes::~ScheduleDAGSDNodes ( )
overridedefault

Member Function Documentation

◆ BuildSchedGraph()

void ScheduleDAGSDNodes::BuildSchedGraph ( AliasAnalysis AA)

BuildSchedGraph - Build the SUnit graph from the selection dag that we are input.

This SUnit graph is similar to the SelectionDAG, but excludes nodes that aren't interesting to scheduling, and represents flagged together nodes with a single SUnit.

This SUnit graph is similar to the SelectionDAG, but excludes nodes that aren't interesting to scheduling, and represents glued together nodes with a single SUnit.

Definition at line 514 of file ScheduleDAGSDNodes.cpp.

References llvm::ISD::CopyFromReg, llvm::SDNode::getMachineOpcode(), llvm::SDNode::getNumValues(), llvm::SDNode::getOpcode(), llvm::SDNode::getValueType(), llvm::SDNode::isMachineOpcode(), and llvm::MVT::Other.

Referenced by isPassiveNode().

◆ Clone()

SUnit * ScheduleDAGSDNodes::Clone ( SUnit N)

◆ computeLatency()

void ScheduleDAGSDNodes::computeLatency ( SUnit SU)
virtual

◆ computeOperandLatency()

void ScheduleDAGSDNodes::computeOperandLatency ( SDNode Def,
SDNode Use,
unsigned  OpIdx,
SDep dep 
) const
virtual

◆ dumpNode()

void ScheduleDAGSDNodes::dumpNode ( const SUnit SU) const
overridevirtual

◆ dumpSchedule()

void ScheduleDAGSDNodes::dumpSchedule ( ) const

Definition at line 675 of file ScheduleDAGSDNodes.cpp.

References llvm::dbgs(), and Sequence.

Referenced by isPassiveNode().

◆ EmitSchedule()

MachineBasicBlock * ScheduleDAGSDNodes::EmitSchedule ( MachineBasicBlock::iterator InsertPos)
virtual

EmitSchedule - Insert MachineInstrs into the MachineBasicBlock according to the order specified in Sequence.

EmitSchedule - Emit the machine code in scheduled order.

Return the new InsertPos and MachineBasicBlock that contains this insertion point. ScheduleDAGSDNodes holds a BB pointer for convenience, but this does not necessarily refer to returned BB. The emitter may split blocks.

Definition at line 799 of file ScheduleDAGSDNodes.cpp.

References assert(), llvm::SmallVectorTemplateCommon< T >::back(), BB, llvm::SmallVectorTemplateCommon< T >::begin(), llvm::MachineFunction::begin(), llvm::SelectionDAG::ByvalParmDbgBegin(), llvm::SelectionDAG::ByvalParmDbgEnd(), DAG, llvm::SelectionDAG::DbgBegin(), llvm::SelectionDAG::DbgEnd(), llvm::InstrEmitter::EmitDbgValue(), llvm::InstrEmitter::EmitNode(), llvm::SmallVectorBase::empty(), llvm::SmallVectorTemplateCommon< T >::end(), llvm::InstrEmitter::getBlock(), llvm::MachineBasicBlock::getFirstNonPHI(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::SDNode::getGluedNode(), llvm::InstrEmitter::getInsertPos(), llvm::SUnit::getNode(), llvm::SDDbgValue::getOrder(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::SelectionDAG::hasDebugValues(), llvm::MachineBasicBlock::insert(), llvm::TargetInstrInfo::insertNoop(), llvm::SUnit::isCloned, MI, N, llvm::SUnit::OrigNode, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::pop_back(), ProcessSourceNode(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), Sequence, llvm::SmallVectorTemplateCommon< T >::size(), and llvm::ScheduleDAG::TII.

Referenced by isPassiveNode(), ProcessSourceNode(), and reportFastISelFailure().

◆ forceUnitLatencies()

virtual bool llvm::ScheduleDAGSDNodes::forceUnitLatencies ( ) const
inlineprotectedvirtual

ForceUnitLatencies - Return true if all scheduling edges should be given a latency value of one.

The default is to return false; schedulers may override this as needed.

Definition at line 173 of file ScheduleDAGSDNodes.h.

Referenced by computeLatency(), computeOperandLatency(), and RemoveUnusedGlue().

◆ getCustomGraphFeatures()

void ScheduleDAGSDNodes::getCustomGraphFeatures ( GraphWriter< ScheduleDAG *> &  GW) const
virtual

◆ getDAGName()

std::string ScheduleDAGSDNodes::getDAGName ( ) const
overridevirtual

Return the basic block label.

Implements llvm::ScheduleDAG.

Definition at line 920 of file ScheduleDAGSDNodes.cpp.

References BB, and llvm::MachineBasicBlock::getFullName().

Referenced by isPassiveNode().

◆ getGraphNodeLabel()

std::string ScheduleDAGSDNodes::getGraphNodeLabel ( const SUnit SU) const
overridevirtual

◆ InitNumRegDefsLeft()

void ScheduleDAGSDNodes::InitNumRegDefsLeft ( SUnit SU)

InitNumRegDefsLeft - Determine the # of regs defined by this node.

Definition at line 583 of file ScheduleDAGSDNodes.cpp.

References assert(), I, and llvm::SUnit::NumRegDefsLeft.

Referenced by isPassiveNode(), and RemoveUnusedGlue().

◆ isPassiveNode()

static bool llvm::ScheduleDAGSDNodes::isPassiveNode ( SDNode Node)
inlinestatic

◆ newSUnit()

SUnit * ScheduleDAGSDNodes::newSUnit ( SDNode N)

◆ Run()

void ScheduleDAGSDNodes::Run ( SelectionDAG dag,
MachineBasicBlock bb 
)

Run - perform scheduling.

Definition at line 54 of file ScheduleDAGSDNodes.cpp.

References BB, llvm::ScheduleDAG::clearDAG(), DAG, Schedule(), and Sequence.

Referenced by reportFastISelFailure().

◆ Schedule()

virtual void llvm::ScheduleDAGSDNodes::Schedule ( )
pure virtual

Schedule - Order nodes according to selected style, filling in the Sequence member.

Referenced by isPassiveNode(), and Run().

◆ VerifyScheduledSequence()

void ScheduleDAGSDNodes::VerifyScheduledSequence ( bool  isBottomUp)

VerifyScheduledSequence - Verify that all SUnits are scheduled and consistent with the Sequence of scheduled instructions.

VerifyScheduledSequence - Verify that all SUnits were scheduled and that their state is consistent with the nodes listed in Sequence.

Definition at line 689 of file ScheduleDAGSDNodes.cpp.

References assert(), Sequence, and llvm::ScheduleDAG::VerifyScheduledDAG().

Referenced by isPassiveNode().

Member Data Documentation

◆ BB

MachineBasicBlock* llvm::ScheduleDAGSDNodes::BB

◆ DAG

SelectionDAG* llvm::ScheduleDAGSDNodes::DAG

Definition at line 49 of file ScheduleDAGSDNodes.h.

Referenced by EmitSchedule(), newSUnit(), RemoveUnusedGlue(), and Run().

◆ InstrItins

const InstrItineraryData* llvm::ScheduleDAGSDNodes::InstrItins

Definition at line 50 of file ScheduleDAGSDNodes.h.

Referenced by computeLatency(), and computeOperandLatency().

◆ Sequence

std::vector<SUnit*> llvm::ScheduleDAGSDNodes::Sequence

The schedule. Null SUnit*'s represent noop instructions.

Definition at line 53 of file ScheduleDAGSDNodes.h.

Referenced by dumpSchedule(), EmitSchedule(), Run(), and VerifyScheduledSequence().


The documentation for this class was generated from the following files: