LLVM  6.0.0svn
Public Types | Public Member Functions | List of all members
llvm::SDep Class Reference

Scheduling dependency. More...

#include "llvm/CodeGen/ScheduleDAG.h"

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Public Types

enum  Kind { Data, Anti, Output, Order }
 These are the different kinds of scheduling dependencies. More...
 
enum  OrderKind {
  Barrier, MayAliasMem, MustAliasMem, Artificial,
  Weak, Cluster
}
 

Public Member Functions

 SDep ()
 Constructs a null SDep. More...
 
 SDep (SUnit *S, Kind kind, unsigned Reg)
 Constructs an SDep with the specified values. More...
 
 SDep (SUnit *S, OrderKind kind)
 
bool overlaps (const SDep &Other) const
 Returns true if the specified SDep is equivalent except for latency. More...
 
bool operator== (const SDep &Other) const
 
bool operator!= (const SDep &Other) const
 
unsigned getLatency () const
 Returns the latency value for this edge, which roughly means the minimum number of cycles that must elapse between the predecessor and the successor, given that they have this edge between them. More...
 
void setLatency (unsigned Lat)
 Sets the latency for this edge. More...
 
SUnitgetSUnit () const
 
void setSUnit (SUnit *SU)
 
Kind getKind () const
 Returns an enum value representing the kind of the dependence. More...
 
bool isCtrl () const
 Shorthand for getKind() != SDep::Data. More...
 
bool isNormalMemory () const
 Tests if this is an Order dependence between two memory accesses where both sides of the dependence access memory in non-volatile and fully modeled ways. More...
 
bool isBarrier () const
 Tests if this is an Order dependence that is marked as a barrier. More...
 
bool isNormalMemoryOrBarrier () const
 Tests if this is could be any kind of memory dependence. More...
 
bool isMustAlias () const
 Tests if this is an Order dependence that is marked as "must alias", meaning that the SUnits at either end of the edge have a memory dependence on a known memory location. More...
 
bool isWeak () const
 Tests if this a weak dependence. More...
 
bool isArtificial () const
 Tests if this is an Order dependence that is marked as "artificial", meaning it isn't necessary for correctness. More...
 
bool isCluster () const
 Tests if this is an Order dependence that is marked as "cluster", meaning it is artificial and wants to be adjacent. More...
 
bool isAssignedRegDep () const
 Tests if this is a Data dependence that is associated with a register. More...
 
unsigned getReg () const
 Returns the register associated with this edge. More...
 
void setReg (unsigned Reg)
 Assigns the associated register for this edge. More...
 
raw_ostreamprint (raw_ostream &O, const TargetRegisterInfo *TRI=nullptr) const
 

Detailed Description

Scheduling dependency.

This represents one direction of an edge in the scheduling DAG.

Definition at line 50 of file ScheduleDAG.h.

Member Enumeration Documentation

◆ Kind

These are the different kinds of scheduling dependencies.

Enumerator
Data 

Regular data dependence (aka true-dependence).

Anti 

A register anti-dependence (aka WAR).

Output 

A register output-dependence (aka WAW).

Order 

Any other ordering dependency.

Definition at line 53 of file ScheduleDAG.h.

◆ OrderKind

Enumerator
Barrier 

An unknown scheduling barrier.

MayAliasMem 

Nonvolatile load/Store instructions that may alias.

MustAliasMem 

Nonvolatile load/Store instructions that must alias.

Artificial 

Arbitrary strong DAG edge (no real dependence).

Weak 

Arbitrary weak DAG edge.

Cluster 

Weak DAG edge linking a chain of clustered instrs.

Definition at line 69 of file ScheduleDAG.h.

Constructor & Destructor Documentation

◆ SDep() [1/3]

llvm::SDep::SDep ( )
inline

Constructs a null SDep.

This is only for use by container classes which require default constructors. SUnits may not/ have null SDep edges.

Definition at line 102 of file ScheduleDAG.h.

◆ SDep() [2/3]

llvm::SDep::SDep ( SUnit S,
Kind  kind,
unsigned  Reg 
)
inline

Constructs an SDep with the specified values.

Definition at line 105 of file ScheduleDAG.h.

References Anti, assert(), Data, llvm_unreachable, Output, and Reg.

◆ SDep() [3/3]

llvm::SDep::SDep ( SUnit S,
OrderKind  kind 
)
inline

Definition at line 124 of file ScheduleDAG.h.

References Other, and overlaps().

Member Function Documentation

◆ getKind()

SDep::Kind llvm::SDep::getKind ( ) const
inline

◆ getLatency()

unsigned llvm::SDep::getLatency ( ) const
inline

Returns the latency value for this edge, which roughly means the minimum number of cycles that must elapse between the predecessor and the successor, given that they have this edge between them.

Definition at line 143 of file ScheduleDAG.h.

Referenced by llvm::SUnit::addPred(), llvm::HexagonSubtarget::HVXMemLatencyMutation::apply(), GetCostForDef(), llvm::ScheduleDAGMI::releasePred(), llvm::ScheduleDAGMI::releaseSucc(), llvm::ConvergingVLIWScheduler::releaseTopNode(), llvm::ConvergingVLIWScheduler::SchedulingCost(), llvm::SUnit::setHeightToAtLeast(), swapAntiDependences(), and llvm::HexagonSubtarget::usePredicatedCalls().

◆ getReg()

unsigned llvm::SDep::getReg ( ) const
inline

Returns the register associated with this edge.

This is only valid on Data, Anti, and Output edges. On Data edges, this value may be zero, meaning there is no associated register.

Definition at line 219 of file ScheduleDAG.h.

References Anti, assert(), Data, getKind(), and Output.

Referenced by llvm::AggressiveAntiDepBreaker::BreakAntiDependencies(), canClobberReachingPhysRegUse(), CheckForLiveRegDef(), llvm::createCopyConstrainDAGMutation(), FindCallSeqStart(), getNodeRegMask(), and swapAntiDependences().

◆ getSUnit()

SUnit * llvm::SDep::getSUnit ( ) const
inline

Definition at line 490 of file ScheduleDAG.h.

Referenced by llvm::ScheduleDAGMI::addEdge(), llvm::SUnit::addPred(), llvm::HexagonSubtarget::HVXMemLatencyMutation::apply(), llvm::AggressiveAntiDepBreaker::BreakAntiDependencies(), CalcNodeSethiUllmanNumber(), canClobberPhysRegDefs(), canClobberReachingPhysRegUse(), CheckForLiveRegDef(), closestSucc(), llvm::SchedDFSResult::compute(), llvm::createCopyConstrainDAGMutation(), llvm::createStoreClusterDAGMutation(), CriticalPathStep(), FindCallSeqStart(), fuseInstructionPair(), GetCostForDef(), llvm::SISubtarget::getMaxNumVGPRs(), getNodeRegMask(), hasDataDependencyPred(), hasDataSucc(), hasOnlyLiveInOpers(), hasOnlyLiveOutUses(), hasVRegCycleUse(), llvm::ScheduleDAGTopologicalSort::InitDAGTopologicalSorting(), INITIALIZE_PASS(), initVRegCycle(), isOperandOf(), llvm::SchedDFSImpl::joinPredSubtree(), multipleIterations(), llvm::resource_sort::operator()(), llvm::ResourcePriorityQueue::push(), llvm::ScheduleDAGMI::releasePred(), llvm::ScheduleDAGMI::releaseSucc(), llvm::ConvergingVLIWScheduler::releaseTopNode(), removePhis(), llvm::SUnit::removePred(), resetVRegCycle(), llvm::ResourcePriorityQueue::ResourcePriorityQueue(), llvm::SIScheduleBlock::schedule(), llvm::ResourcePriorityQueue::scheduledNode(), llvm::ConvergingVLIWScheduler::SchedulingCost(), llvm::SUnit::setDepthDirty(), llvm::SUnit::setHeightDirty(), llvm::SUnit::setHeightToAtLeast(), setLatency(), llvm::SIScheduleDAGMI::SIScheduleDAGMI(), swapAntiDependences(), llvm::SchedDFSImpl::visitCrossEdge(), llvm::SchedDFSImpl::visitPostorderEdge(), llvm::SchedDFSImpl::visitPostorderNode(), and llvm::ScheduleDAGTopologicalSort::WillCreateCycle().

◆ isArtificial()

bool llvm::SDep::isArtificial ( ) const
inline

Tests if this is an Order dependence that is marked as "artificial", meaning it isn't necessary for correctness.

Definition at line 201 of file ScheduleDAG.h.

References Artificial, getKind(), and Order.

Referenced by llvm::ScheduleDAGMI::addEdge(), ignoreDependence(), isOperandOf(), removePhis(), and llvm::HexagonSubtarget::usePredicatedCalls().

◆ isAssignedRegDep()

bool llvm::SDep::isAssignedRegDep ( ) const
inline

◆ isBarrier()

bool llvm::SDep::isBarrier ( ) const
inline

Tests if this is an Order dependence that is marked as a barrier.

Definition at line 175 of file ScheduleDAG.h.

References Barrier, getKind(), and Order.

Referenced by isNormalMemoryOrBarrier().

◆ isCluster()

bool llvm::SDep::isCluster ( ) const
inline

Tests if this is an Order dependence that is marked as "cluster", meaning it is artificial and wants to be adjacent.

Definition at line 207 of file ScheduleDAG.h.

References Cluster, getKind(), and Order.

Referenced by llvm::ScheduleDAGMI::releasePred(), and llvm::ScheduleDAGMI::releaseSucc().

◆ isCtrl()

bool llvm::SDep::isCtrl ( ) const
inline

◆ isMustAlias()

bool llvm::SDep::isMustAlias ( ) const
inline

Tests if this is an Order dependence that is marked as "must alias", meaning that the SUnits at either end of the edge have a memory dependence on a known memory location.

Definition at line 187 of file ScheduleDAG.h.

References getKind(), MustAliasMem, and Order.

◆ isNormalMemory()

bool llvm::SDep::isNormalMemory ( ) const
inline

Tests if this is an Order dependence between two memory accesses where both sides of the dependence access memory in non-volatile and fully modeled ways.

Definition at line 169 of file ScheduleDAG.h.

References getKind(), MayAliasMem, MustAliasMem, and Order.

Referenced by isNormalMemoryOrBarrier().

◆ isNormalMemoryOrBarrier()

bool llvm::SDep::isNormalMemoryOrBarrier ( ) const
inline

Tests if this is could be any kind of memory dependence.

Definition at line 180 of file ScheduleDAG.h.

References isBarrier(), and isNormalMemory().

◆ isWeak()

bool llvm::SDep::isWeak ( ) const
inline

Tests if this a weak dependence.

Weak dependencies are considered DAG edges for height computation and other heuristics, but do not force ordering. Breaking a weak edge may require the scheduler to compensate, for example by inserting a copy.

Definition at line 195 of file ScheduleDAG.h.

References getKind(), Order, and Weak.

Referenced by llvm::SUnit::addPred(), fuseInstructionPair(), hasDataDependencyPred(), INITIALIZE_PASS(), llvm::ScheduleDAGMI::releasePred(), llvm::ScheduleDAGMI::releaseSucc(), llvm::SUnit::removePred(), and llvm::SIScheduleBlock::schedule().

◆ operator!=()

bool llvm::SDep::operator!= ( const SDep Other) const
inline

Definition at line 136 of file ScheduleDAG.h.

References operator==().

◆ operator==()

bool llvm::SDep::operator== ( const SDep Other) const
inline

Definition at line 132 of file ScheduleDAG.h.

References overlaps().

Referenced by operator!=(), and llvm::SUnitIterator::operator!=().

◆ overlaps()

bool llvm::SDep::overlaps ( const SDep Other) const
inline

Returns true if the specified SDep is equivalent except for latency.

Definition at line 475 of file ScheduleDAG.h.

References Anti, Data, llvm_unreachable, Order, OrdKind, Output, and Reg.

Referenced by operator==(), and SDep().

◆ print()

LLVM_DUMP_METHOD raw_ostream & SDep::print ( raw_ostream O,
const TargetRegisterInfo TRI = nullptr 
) const

◆ setLatency()

void llvm::SDep::setLatency ( unsigned  Lat)
inline

◆ setReg()

void llvm::SDep::setReg ( unsigned  Reg)
inline

Assigns the associated register for this edge.

This is only valid on Data, Anti, and Output edges. On Anti and Output edges, this value must not be zero. On Data edges, the value may be zero, which would mean that no specific register is associated with this edge.

Definition at line 229 of file ScheduleDAG.h.

References Anti, assert(), Data, getKind(), llvm::RISCVFenceField::O, Output, print(), and Reg.

◆ setSUnit()

void llvm::SDep::setSUnit ( SUnit SU)
inline

Member Data Documentation

◆ OrdKind

unsigned llvm::SDep::OrdKind

Additional information about Order dependencies.

Definition at line 91 of file ScheduleDAG.h.

Referenced by overlaps().

◆ Reg

unsigned llvm::SDep::Reg

For Data, Anti, and Output dependencies, the associated register.

For Data dependencies that don't currently have a register/ assigned, this is set to zero.

Definition at line 88 of file ScheduleDAG.h.

Referenced by overlaps(), SDep(), and setReg().


The documentation for this class was generated from the following files: