LLVM  8.0.0svn
AggressiveAntiDepBreaker.cpp
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1 //===- AggressiveAntiDepBreaker.cpp - Anti-dep breaker --------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the AggressiveAntiDepBreaker class, which
11 // implements register anti-dependence breaking during post-RA
12 // scheduling. It attempts to break all anti-dependencies within a
13 // block.
14 //
15 //===----------------------------------------------------------------------===//
16 
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/SmallSet.h"
33 #include "llvm/MC/MCInstrDesc.h"
34 #include "llvm/MC/MCRegisterInfo.h"
36 #include "llvm/Support/Debug.h"
39 #include <cassert>
40 #include <map>
41 #include <set>
42 #include <utility>
43 #include <vector>
44 
45 using namespace llvm;
46 
47 #define DEBUG_TYPE "post-RA-sched"
48 
49 // If DebugDiv > 0 then only break antidep with (ID % DebugDiv) == DebugMod
50 static cl::opt<int>
51 DebugDiv("agg-antidep-debugdiv",
52  cl::desc("Debug control for aggressive anti-dep breaker"),
53  cl::init(0), cl::Hidden);
54 
55 static cl::opt<int>
56 DebugMod("agg-antidep-debugmod",
57  cl::desc("Debug control for aggressive anti-dep breaker"),
58  cl::init(0), cl::Hidden);
59 
62  : NumTargetRegs(TargetRegs), GroupNodes(TargetRegs, 0),
63  GroupNodeIndices(TargetRegs, 0), KillIndices(TargetRegs, 0),
64  DefIndices(TargetRegs, 0) {
65  const unsigned BBSize = BB->size();
66  for (unsigned i = 0; i < NumTargetRegs; ++i) {
67  // Initialize all registers to be in their own group. Initially we
68  // assign the register to the same-indexed GroupNode.
69  GroupNodeIndices[i] = i;
70  // Initialize the indices to indicate that no registers are live.
71  KillIndices[i] = ~0u;
72  DefIndices[i] = BBSize;
73  }
74 }
75 
77  unsigned Node = GroupNodeIndices[Reg];
78  while (GroupNodes[Node] != Node)
79  Node = GroupNodes[Node];
80 
81  return Node;
82 }
83 
85  unsigned Group,
86  std::vector<unsigned> &Regs,
87  std::multimap<unsigned, AggressiveAntiDepState::RegisterReference> *RegRefs)
88 {
89  for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
90  if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
91  Regs.push_back(Reg);
92  }
93 }
94 
95 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) {
96  assert(GroupNodes[0] == 0 && "GroupNode 0 not parent!");
97  assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
98 
99  // find group for each register
100  unsigned Group1 = GetGroup(Reg1);
101  unsigned Group2 = GetGroup(Reg2);
102 
103  // if either group is 0, then that must become the parent
104  unsigned Parent = (Group1 == 0) ? Group1 : Group2;
105  unsigned Other = (Parent == Group1) ? Group2 : Group1;
106  GroupNodes.at(Other) = Parent;
107  return Parent;
108 }
109 
111  // Create a new GroupNode for Reg. Reg's existing GroupNode must
112  // stay as is because there could be other GroupNodes referring to
113  // it.
114  unsigned idx = GroupNodes.size();
115  GroupNodes.push_back(idx);
116  GroupNodeIndices[Reg] = idx;
117  return idx;
118 }
119 
121  // KillIndex must be defined and DefIndex not defined for a register
122  // to be live.
123  return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u));
124 }
125 
127  MachineFunction &MFi, const RegisterClassInfo &RCI,
128  TargetSubtargetInfo::RegClassVector &CriticalPathRCs)
129  : AntiDepBreaker(), MF(MFi), MRI(MF.getRegInfo()),
130  TII(MF.getSubtarget().getInstrInfo()),
131  TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI) {
132  /* Collect a bitset of all registers that are only broken if they
133  are on the critical path. */
134  for (unsigned i = 0, e = CriticalPathRCs.size(); i < e; ++i) {
135  BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]);
136  if (CriticalPathSet.none())
137  CriticalPathSet = CPSet;
138  else
139  CriticalPathSet |= CPSet;
140  }
141 
142  LLVM_DEBUG(dbgs() << "AntiDep Critical-Path Registers:");
143  LLVM_DEBUG(for (unsigned r
144  : CriticalPathSet.set_bits()) dbgs()
145  << " " << printReg(r, TRI));
146  LLVM_DEBUG(dbgs() << '\n');
147 }
148 
150  delete State;
151 }
152 
154  assert(!State);
155  State = new AggressiveAntiDepState(TRI->getNumRegs(), BB);
156 
157  bool IsReturnBlock = BB->isReturnBlock();
158  std::vector<unsigned> &KillIndices = State->GetKillIndices();
159  std::vector<unsigned> &DefIndices = State->GetDefIndices();
160 
161  // Examine the live-in regs of all successors.
163  SE = BB->succ_end(); SI != SE; ++SI)
164  for (const auto &LI : (*SI)->liveins()) {
165  for (MCRegAliasIterator AI(LI.PhysReg, TRI, true); AI.isValid(); ++AI) {
166  unsigned Reg = *AI;
167  State->UnionGroups(Reg, 0);
168  KillIndices[Reg] = BB->size();
169  DefIndices[Reg] = ~0u;
170  }
171  }
172 
173  // Mark live-out callee-saved registers. In a return block this is
174  // all callee-saved registers. In non-return this is any
175  // callee-saved register that is not saved in the prolog.
176  const MachineFrameInfo &MFI = MF.getFrameInfo();
177  BitVector Pristine = MFI.getPristineRegs(MF);
178  for (const MCPhysReg *I = MF.getRegInfo().getCalleeSavedRegs(); *I;
179  ++I) {
180  unsigned Reg = *I;
181  if (!IsReturnBlock && !Pristine.test(Reg))
182  continue;
183  for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
184  unsigned AliasReg = *AI;
185  State->UnionGroups(AliasReg, 0);
186  KillIndices[AliasReg] = BB->size();
187  DefIndices[AliasReg] = ~0u;
188  }
189  }
190 }
191 
193  delete State;
194  State = nullptr;
195 }
196 
198  unsigned InsertPosIndex) {
199  assert(Count < InsertPosIndex && "Instruction index out of expected range!");
200 
201  std::set<unsigned> PassthruRegs;
202  GetPassthruRegs(MI, PassthruRegs);
203  PrescanInstruction(MI, Count, PassthruRegs);
204  ScanInstruction(MI, Count);
205 
206  LLVM_DEBUG(dbgs() << "Observe: ");
207  LLVM_DEBUG(MI.dump());
208  LLVM_DEBUG(dbgs() << "\tRegs:");
209 
210  std::vector<unsigned> &DefIndices = State->GetDefIndices();
211  for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
212  // If Reg is current live, then mark that it can't be renamed as
213  // we don't know the extent of its live-range anymore (now that it
214  // has been scheduled). If it is not live but was defined in the
215  // previous schedule region, then set its def index to the most
216  // conservative location (i.e. the beginning of the previous
217  // schedule region).
218  if (State->IsLive(Reg)) {
219  LLVM_DEBUG(if (State->GetGroup(Reg) != 0) dbgs()
220  << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg)
221  << "->g0(region live-out)");
222  State->UnionGroups(Reg, 0);
223  } else if ((DefIndices[Reg] < InsertPosIndex)
224  && (DefIndices[Reg] >= Count)) {
225  DefIndices[Reg] = Count;
226  }
227  }
228  LLVM_DEBUG(dbgs() << '\n');
229 }
230 
231 bool AggressiveAntiDepBreaker::IsImplicitDefUse(MachineInstr &MI,
232  MachineOperand &MO) {
233  if (!MO.isReg() || !MO.isImplicit())
234  return false;
235 
236  unsigned Reg = MO.getReg();
237  if (Reg == 0)
238  return false;
239 
240  MachineOperand *Op = nullptr;
241  if (MO.isDef())
242  Op = MI.findRegisterUseOperand(Reg, true);
243  else
244  Op = MI.findRegisterDefOperand(Reg);
245 
246  return(Op && Op->isImplicit());
247 }
248 
249 void AggressiveAntiDepBreaker::GetPassthruRegs(
250  MachineInstr &MI, std::set<unsigned> &PassthruRegs) {
251  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
252  MachineOperand &MO = MI.getOperand(i);
253  if (!MO.isReg()) continue;
254  if ((MO.isDef() && MI.isRegTiedToUseOperand(i)) ||
255  IsImplicitDefUse(MI, MO)) {
256  const unsigned Reg = MO.getReg();
257  for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
258  SubRegs.isValid(); ++SubRegs)
259  PassthruRegs.insert(*SubRegs);
260  }
261  }
262 }
263 
264 /// AntiDepEdges - Return in Edges the anti- and output- dependencies
265 /// in SU that we want to consider for breaking.
266 static void AntiDepEdges(const SUnit *SU, std::vector<const SDep *> &Edges) {
267  SmallSet<unsigned, 4> RegSet;
268  for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
269  P != PE; ++P) {
270  if ((P->getKind() == SDep::Anti) || (P->getKind() == SDep::Output)) {
271  if (RegSet.insert(P->getReg()).second)
272  Edges.push_back(&*P);
273  }
274  }
275 }
276 
277 /// CriticalPathStep - Return the next SUnit after SU on the bottom-up
278 /// critical path.
279 static const SUnit *CriticalPathStep(const SUnit *SU) {
280  const SDep *Next = nullptr;
281  unsigned NextDepth = 0;
282  // Find the predecessor edge with the greatest depth.
283  if (SU) {
284  for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
285  P != PE; ++P) {
286  const SUnit *PredSU = P->getSUnit();
287  unsigned PredLatency = P->getLatency();
288  unsigned PredTotalLatency = PredSU->getDepth() + PredLatency;
289  // In the case of a latency tie, prefer an anti-dependency edge over
290  // other types of edges.
291  if (NextDepth < PredTotalLatency ||
292  (NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) {
293  NextDepth = PredTotalLatency;
294  Next = &*P;
295  }
296  }
297  }
298 
299  return (Next) ? Next->getSUnit() : nullptr;
300 }
301 
302 void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx,
303  const char *tag,
304  const char *header,
305  const char *footer) {
306  std::vector<unsigned> &KillIndices = State->GetKillIndices();
307  std::vector<unsigned> &DefIndices = State->GetDefIndices();
308  std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
309  RegRefs = State->GetRegRefs();
310 
311  // FIXME: We must leave subregisters of live super registers as live, so that
312  // we don't clear out the register tracking information for subregisters of
313  // super registers we're still tracking (and with which we're unioning
314  // subregister definitions).
315  for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
316  if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI)) {
317  LLVM_DEBUG(if (!header && footer) dbgs() << footer);
318  return;
319  }
320 
321  if (!State->IsLive(Reg)) {
322  KillIndices[Reg] = KillIdx;
323  DefIndices[Reg] = ~0u;
324  RegRefs.erase(Reg);
325  State->LeaveGroup(Reg);
326  LLVM_DEBUG(if (header) {
327  dbgs() << header << printReg(Reg, TRI);
328  header = nullptr;
329  });
330  LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag);
331  // Repeat for subregisters. Note that we only do this if the superregister
332  // was not live because otherwise, regardless whether we have an explicit
333  // use of the subregister, the subregister's contents are needed for the
334  // uses of the superregister.
335  for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
336  unsigned SubregReg = *SubRegs;
337  if (!State->IsLive(SubregReg)) {
338  KillIndices[SubregReg] = KillIdx;
339  DefIndices[SubregReg] = ~0u;
340  RegRefs.erase(SubregReg);
341  State->LeaveGroup(SubregReg);
342  LLVM_DEBUG(if (header) {
343  dbgs() << header << printReg(Reg, TRI);
344  header = nullptr;
345  });
346  LLVM_DEBUG(dbgs() << " " << printReg(SubregReg, TRI) << "->g"
347  << State->GetGroup(SubregReg) << tag);
348  }
349  }
350  }
351 
352  LLVM_DEBUG(if (!header && footer) dbgs() << footer);
353 }
354 
355 void AggressiveAntiDepBreaker::PrescanInstruction(
356  MachineInstr &MI, unsigned Count, std::set<unsigned> &PassthruRegs) {
357  std::vector<unsigned> &DefIndices = State->GetDefIndices();
358  std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
359  RegRefs = State->GetRegRefs();
360 
361  // Handle dead defs by simulating a last-use of the register just
362  // after the def. A dead def can occur because the def is truly
363  // dead, or because only a subregister is live at the def. If we
364  // don't do this the dead def will be incorrectly merged into the
365  // previous def.
366  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
367  MachineOperand &MO = MI.getOperand(i);
368  if (!MO.isReg() || !MO.isDef()) continue;
369  unsigned Reg = MO.getReg();
370  if (Reg == 0) continue;
371 
372  HandleLastUse(Reg, Count + 1, "", "\tDead Def: ", "\n");
373  }
374 
375  LLVM_DEBUG(dbgs() << "\tDef Groups:");
376  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
377  MachineOperand &MO = MI.getOperand(i);
378  if (!MO.isReg() || !MO.isDef()) continue;
379  unsigned Reg = MO.getReg();
380  if (Reg == 0) continue;
381 
382  LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g"
383  << State->GetGroup(Reg));
384 
385  // If MI's defs have a special allocation requirement, don't allow
386  // any def registers to be changed. Also assume all registers
387  // defined in a call must not be changed (ABI). Inline assembly may
388  // reference either system calls or the register directly. Skip it until we
389  // can tell user specified registers from compiler-specified.
390  if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI) ||
391  MI.isInlineAsm()) {
392  LLVM_DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
393  State->UnionGroups(Reg, 0);
394  }
395 
396  // Any aliased that are live at this point are completely or
397  // partially defined here, so group those aliases with Reg.
398  for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) {
399  unsigned AliasReg = *AI;
400  if (State->IsLive(AliasReg)) {
401  State->UnionGroups(Reg, AliasReg);
402  LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via "
403  << printReg(AliasReg, TRI) << ")");
404  }
405  }
406 
407  // Note register reference...
408  const TargetRegisterClass *RC = nullptr;
409  if (i < MI.getDesc().getNumOperands())
410  RC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
412  RegRefs.insert(std::make_pair(Reg, RR));
413  }
414 
415  LLVM_DEBUG(dbgs() << '\n');
416 
417  // Scan the register defs for this instruction and update
418  // live-ranges.
419  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
420  MachineOperand &MO = MI.getOperand(i);
421  if (!MO.isReg() || !MO.isDef()) continue;
422  unsigned Reg = MO.getReg();
423  if (Reg == 0) continue;
424  // Ignore KILLs and passthru registers for liveness...
425  if (MI.isKill() || (PassthruRegs.count(Reg) != 0))
426  continue;
427 
428  // Update def for Reg and aliases.
429  for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
430  // We need to be careful here not to define already-live super registers.
431  // If the super register is already live, then this definition is not
432  // a definition of the whole super register (just a partial insertion
433  // into it). Earlier subregister definitions (which we've not yet visited
434  // because we're iterating bottom-up) need to be linked to the same group
435  // as this definition.
436  if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI))
437  continue;
438 
439  DefIndices[*AI] = Count;
440  }
441  }
442 }
443 
444 void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI,
445  unsigned Count) {
446  LLVM_DEBUG(dbgs() << "\tUse Groups:");
447  std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
448  RegRefs = State->GetRegRefs();
449 
450  // If MI's uses have special allocation requirement, don't allow
451  // any use registers to be changed. Also assume all registers
452  // used in a call must not be changed (ABI).
453  // Inline Assembly register uses also cannot be safely changed.
454  // FIXME: The issue with predicated instruction is more complex. We are being
455  // conservatively here because the kill markers cannot be trusted after
456  // if-conversion:
457  // %r6 = LDR %sp, %reg0, 92, 14, %reg0; mem:LD4[FixedStack14]
458  // ...
459  // STR %r0, killed %r6, %reg0, 0, 0, %cpsr; mem:ST4[%395]
460  // %r6 = LDR %sp, %reg0, 100, 0, %cpsr; mem:LD4[FixedStack12]
461  // STR %r0, killed %r6, %reg0, 0, 14, %reg0; mem:ST4[%396](align=8)
462  //
463  // The first R6 kill is not really a kill since it's killed by a predicated
464  // instruction which may not be executed. The second R6 def may or may not
465  // re-define R6 so it's not safe to change it since the last R6 use cannot be
466  // changed.
467  bool Special = MI.isCall() || MI.hasExtraSrcRegAllocReq() ||
468  TII->isPredicated(MI) || MI.isInlineAsm();
469 
470  // Scan the register uses for this instruction and update
471  // live-ranges, groups and RegRefs.
472  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
473  MachineOperand &MO = MI.getOperand(i);
474  if (!MO.isReg() || !MO.isUse()) continue;
475  unsigned Reg = MO.getReg();
476  if (Reg == 0) continue;
477 
478  LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g"
479  << State->GetGroup(Reg));
480 
481  // It wasn't previously live but now it is, this is a kill. Forget
482  // the previous live-range information and start a new live-range
483  // for the register.
484  HandleLastUse(Reg, Count, "(last-use)");
485 
486  if (Special) {
487  LLVM_DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
488  State->UnionGroups(Reg, 0);
489  }
490 
491  // Note register reference...
492  const TargetRegisterClass *RC = nullptr;
493  if (i < MI.getDesc().getNumOperands())
494  RC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
496  RegRefs.insert(std::make_pair(Reg, RR));
497  }
498 
499  LLVM_DEBUG(dbgs() << '\n');
500 
501  // Form a group of all defs and uses of a KILL instruction to ensure
502  // that all registers are renamed as a group.
503  if (MI.isKill()) {
504  LLVM_DEBUG(dbgs() << "\tKill Group:");
505 
506  unsigned FirstReg = 0;
507  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
508  MachineOperand &MO = MI.getOperand(i);
509  if (!MO.isReg()) continue;
510  unsigned Reg = MO.getReg();
511  if (Reg == 0) continue;
512 
513  if (FirstReg != 0) {
514  LLVM_DEBUG(dbgs() << "=" << printReg(Reg, TRI));
515  State->UnionGroups(FirstReg, Reg);
516  } else {
517  LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI));
518  FirstReg = Reg;
519  }
520  }
521 
522  LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n');
523  }
524 }
525 
526 BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) {
527  BitVector BV(TRI->getNumRegs(), false);
528  bool first = true;
529 
530  // Check all references that need rewriting for Reg. For each, use
531  // the corresponding register class to narrow the set of registers
532  // that are appropriate for renaming.
533  for (const auto &Q : make_range(State->GetRegRefs().equal_range(Reg))) {
534  const TargetRegisterClass *RC = Q.second.RC;
535  if (!RC) continue;
536 
537  BitVector RCBV = TRI->getAllocatableSet(MF, RC);
538  if (first) {
539  BV |= RCBV;
540  first = false;
541  } else {
542  BV &= RCBV;
543  }
544 
545  LLVM_DEBUG(dbgs() << " " << TRI->getRegClassName(RC));
546  }
547 
548  return BV;
549 }
550 
551 bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
552  unsigned AntiDepGroupIndex,
553  RenameOrderType& RenameOrder,
554  std::map<unsigned, unsigned> &RenameMap) {
555  std::vector<unsigned> &KillIndices = State->GetKillIndices();
556  std::vector<unsigned> &DefIndices = State->GetDefIndices();
557  std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
558  RegRefs = State->GetRegRefs();
559 
560  // Collect all referenced registers in the same group as
561  // AntiDepReg. These all need to be renamed together if we are to
562  // break the anti-dependence.
563  std::vector<unsigned> Regs;
564  State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs);
565  assert(!Regs.empty() && "Empty register group!");
566  if (Regs.empty())
567  return false;
568 
569  // Find the "superest" register in the group. At the same time,
570  // collect the BitVector of registers that can be used to rename
571  // each register.
572  LLVM_DEBUG(dbgs() << "\tRename Candidates for Group g" << AntiDepGroupIndex
573  << ":\n");
574  std::map<unsigned, BitVector> RenameRegisterMap;
575  unsigned SuperReg = 0;
576  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
577  unsigned Reg = Regs[i];
578  if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg))
579  SuperReg = Reg;
580 
581  // If Reg has any references, then collect possible rename regs
582  if (RegRefs.count(Reg) > 0) {
583  LLVM_DEBUG(dbgs() << "\t\t" << printReg(Reg, TRI) << ":");
584 
585  BitVector &BV = RenameRegisterMap[Reg];
586  assert(BV.empty());
587  BV = GetRenameRegisters(Reg);
588 
589  LLVM_DEBUG({
590  dbgs() << " ::";
591  for (unsigned r : BV.set_bits())
592  dbgs() << " " << printReg(r, TRI);
593  dbgs() << "\n";
594  });
595  }
596  }
597 
598  // All group registers should be a subreg of SuperReg.
599  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
600  unsigned Reg = Regs[i];
601  if (Reg == SuperReg) continue;
602  bool IsSub = TRI->isSubRegister(SuperReg, Reg);
603  // FIXME: remove this once PR18663 has been properly fixed. For now,
604  // return a conservative answer:
605  // assert(IsSub && "Expecting group subregister");
606  if (!IsSub)
607  return false;
608  }
609 
610 #ifndef NDEBUG
611  // If DebugDiv > 0 then only rename (renamecnt % DebugDiv) == DebugMod
612  if (DebugDiv > 0) {
613  static int renamecnt = 0;
614  if (renamecnt++ % DebugDiv != DebugMod)
615  return false;
616 
617  dbgs() << "*** Performing rename " << printReg(SuperReg, TRI)
618  << " for debug ***\n";
619  }
620 #endif
621 
622  // Check each possible rename register for SuperReg in round-robin
623  // order. If that register is available, and the corresponding
624  // registers are available for the other group subregisters, then we
625  // can use those registers to rename.
626 
627  // FIXME: Using getMinimalPhysRegClass is very conservative. We should
628  // check every use of the register and find the largest register class
629  // that can be used in all of them.
630  const TargetRegisterClass *SuperRC =
631  TRI->getMinimalPhysRegClass(SuperReg, MVT::Other);
632 
633  ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC);
634  if (Order.empty()) {
635  LLVM_DEBUG(dbgs() << "\tEmpty Super Regclass!!\n");
636  return false;
637  }
638 
639  LLVM_DEBUG(dbgs() << "\tFind Registers:");
640 
641  RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size()));
642 
643  unsigned OrigR = RenameOrder[SuperRC];
644  unsigned EndR = ((OrigR == Order.size()) ? 0 : OrigR);
645  unsigned R = OrigR;
646  do {
647  if (R == 0) R = Order.size();
648  --R;
649  const unsigned NewSuperReg = Order[R];
650  // Don't consider non-allocatable registers
651  if (!MRI.isAllocatable(NewSuperReg)) continue;
652  // Don't replace a register with itself.
653  if (NewSuperReg == SuperReg) continue;
654 
655  LLVM_DEBUG(dbgs() << " [" << printReg(NewSuperReg, TRI) << ':');
656  RenameMap.clear();
657 
658  // For each referenced group register (which must be a SuperReg or
659  // a subregister of SuperReg), find the corresponding subregister
660  // of NewSuperReg and make sure it is free to be renamed.
661  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
662  unsigned Reg = Regs[i];
663  unsigned NewReg = 0;
664  if (Reg == SuperReg) {
665  NewReg = NewSuperReg;
666  } else {
667  unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg);
668  if (NewSubRegIdx != 0)
669  NewReg = TRI->getSubReg(NewSuperReg, NewSubRegIdx);
670  }
671 
672  LLVM_DEBUG(dbgs() << " " << printReg(NewReg, TRI));
673 
674  // Check if Reg can be renamed to NewReg.
675  if (!RenameRegisterMap[Reg].test(NewReg)) {
676  LLVM_DEBUG(dbgs() << "(no rename)");
677  goto next_super_reg;
678  }
679 
680  // If NewReg is dead and NewReg's most recent def is not before
681  // Regs's kill, it's safe to replace Reg with NewReg. We
682  // must also check all aliases of NewReg, because we can't define a
683  // register when any sub or super is already live.
684  if (State->IsLive(NewReg) || (KillIndices[Reg] > DefIndices[NewReg])) {
685  LLVM_DEBUG(dbgs() << "(live)");
686  goto next_super_reg;
687  } else {
688  bool found = false;
689  for (MCRegAliasIterator AI(NewReg, TRI, false); AI.isValid(); ++AI) {
690  unsigned AliasReg = *AI;
691  if (State->IsLive(AliasReg) ||
692  (KillIndices[Reg] > DefIndices[AliasReg])) {
693  LLVM_DEBUG(dbgs()
694  << "(alias " << printReg(AliasReg, TRI) << " live)");
695  found = true;
696  break;
697  }
698  }
699  if (found)
700  goto next_super_reg;
701  }
702 
703  // We cannot rename 'Reg' to 'NewReg' if one of the uses of 'Reg' also
704  // defines 'NewReg' via an early-clobber operand.
705  for (const auto &Q : make_range(RegRefs.equal_range(Reg))) {
706  MachineInstr *UseMI = Q.second.Operand->getParent();
707  int Idx = UseMI->findRegisterDefOperandIdx(NewReg, false, true, TRI);
708  if (Idx == -1)
709  continue;
710 
711  if (UseMI->getOperand(Idx).isEarlyClobber()) {
712  LLVM_DEBUG(dbgs() << "(ec)");
713  goto next_super_reg;
714  }
715  }
716 
717  // Also, we cannot rename 'Reg' to 'NewReg' if the instruction defining
718  // 'Reg' is an early-clobber define and that instruction also uses
719  // 'NewReg'.
720  for (const auto &Q : make_range(RegRefs.equal_range(Reg))) {
721  if (!Q.second.Operand->isDef() || !Q.second.Operand->isEarlyClobber())
722  continue;
723 
724  MachineInstr *DefMI = Q.second.Operand->getParent();
725  if (DefMI->readsRegister(NewReg, TRI)) {
726  LLVM_DEBUG(dbgs() << "(ec)");
727  goto next_super_reg;
728  }
729  }
730 
731  // Record that 'Reg' can be renamed to 'NewReg'.
732  RenameMap.insert(std::pair<unsigned, unsigned>(Reg, NewReg));
733  }
734 
735  // If we fall-out here, then every register in the group can be
736  // renamed, as recorded in RenameMap.
737  RenameOrder.erase(SuperRC);
738  RenameOrder.insert(RenameOrderType::value_type(SuperRC, R));
739  LLVM_DEBUG(dbgs() << "]\n");
740  return true;
741 
742  next_super_reg:
743  LLVM_DEBUG(dbgs() << ']');
744  } while (R != EndR);
745 
746  LLVM_DEBUG(dbgs() << '\n');
747 
748  // No registers are free and available!
749  return false;
750 }
751 
752 /// BreakAntiDependencies - Identifiy anti-dependencies within the
753 /// ScheduleDAG and break them by renaming registers.
755  const std::vector<SUnit> &SUnits,
758  unsigned InsertPosIndex,
759  DbgValueVector &DbgValues) {
760  std::vector<unsigned> &KillIndices = State->GetKillIndices();
761  std::vector<unsigned> &DefIndices = State->GetDefIndices();
762  std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
763  RegRefs = State->GetRegRefs();
764 
765  // The code below assumes that there is at least one instruction,
766  // so just duck out immediately if the block is empty.
767  if (SUnits.empty()) return 0;
768 
769  // For each regclass the next register to use for renaming.
770  RenameOrderType RenameOrder;
771 
772  // ...need a map from MI to SUnit.
773  std::map<MachineInstr *, const SUnit *> MISUnitMap;
774  for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
775  const SUnit *SU = &SUnits[i];
776  MISUnitMap.insert(std::pair<MachineInstr *, const SUnit *>(SU->getInstr(),
777  SU));
778  }
779 
780  // Track progress along the critical path through the SUnit graph as
781  // we walk the instructions. This is needed for regclasses that only
782  // break critical-path anti-dependencies.
783  const SUnit *CriticalPathSU = nullptr;
784  MachineInstr *CriticalPathMI = nullptr;
785  if (CriticalPathSet.any()) {
786  for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
787  const SUnit *SU = &SUnits[i];
788  if (!CriticalPathSU ||
789  ((SU->getDepth() + SU->Latency) >
790  (CriticalPathSU->getDepth() + CriticalPathSU->Latency))) {
791  CriticalPathSU = SU;
792  }
793  }
794 
795  CriticalPathMI = CriticalPathSU->getInstr();
796  }
797 
798 #ifndef NDEBUG
799  LLVM_DEBUG(dbgs() << "\n===== Aggressive anti-dependency breaking\n");
800  LLVM_DEBUG(dbgs() << "Available regs:");
801  for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
802  if (!State->IsLive(Reg))
803  LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI));
804  }
805  LLVM_DEBUG(dbgs() << '\n');
806 #endif
807 
808  BitVector RegAliases(TRI->getNumRegs());
809 
810  // Attempt to break anti-dependence edges. Walk the instructions
811  // from the bottom up, tracking information about liveness as we go
812  // to help determine which registers are available.
813  unsigned Broken = 0;
814  unsigned Count = InsertPosIndex - 1;
815  for (MachineBasicBlock::iterator I = End, E = Begin;
816  I != E; --Count) {
817  MachineInstr &MI = *--I;
818 
819  if (MI.isDebugInstr())
820  continue;
821 
822  LLVM_DEBUG(dbgs() << "Anti: ");
823  LLVM_DEBUG(MI.dump());
824 
825  std::set<unsigned> PassthruRegs;
826  GetPassthruRegs(MI, PassthruRegs);
827 
828  // Process the defs in MI...
829  PrescanInstruction(MI, Count, PassthruRegs);
830 
831  // The dependence edges that represent anti- and output-
832  // dependencies that are candidates for breaking.
833  std::vector<const SDep *> Edges;
834  const SUnit *PathSU = MISUnitMap[&MI];
835  AntiDepEdges(PathSU, Edges);
836 
837  // If MI is not on the critical path, then we don't rename
838  // registers in the CriticalPathSet.
839  BitVector *ExcludeRegs = nullptr;
840  if (&MI == CriticalPathMI) {
841  CriticalPathSU = CriticalPathStep(CriticalPathSU);
842  CriticalPathMI = (CriticalPathSU) ? CriticalPathSU->getInstr() : nullptr;
843  } else if (CriticalPathSet.any()) {
844  ExcludeRegs = &CriticalPathSet;
845  }
846 
847  // Ignore KILL instructions (they form a group in ScanInstruction
848  // but don't cause any anti-dependence breaking themselves)
849  if (!MI.isKill()) {
850  // Attempt to break each anti-dependency...
851  for (unsigned i = 0, e = Edges.size(); i != e; ++i) {
852  const SDep *Edge = Edges[i];
853  SUnit *NextSU = Edge->getSUnit();
854 
855  if ((Edge->getKind() != SDep::Anti) &&
856  (Edge->getKind() != SDep::Output)) continue;
857 
858  unsigned AntiDepReg = Edge->getReg();
859  LLVM_DEBUG(dbgs() << "\tAntidep reg: " << printReg(AntiDepReg, TRI));
860  assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
861 
862  if (!MRI.isAllocatable(AntiDepReg)) {
863  // Don't break anti-dependencies on non-allocatable registers.
864  LLVM_DEBUG(dbgs() << " (non-allocatable)\n");
865  continue;
866  } else if (ExcludeRegs && ExcludeRegs->test(AntiDepReg)) {
867  // Don't break anti-dependencies for critical path registers
868  // if not on the critical path
869  LLVM_DEBUG(dbgs() << " (not critical-path)\n");
870  continue;
871  } else if (PassthruRegs.count(AntiDepReg) != 0) {
872  // If the anti-dep register liveness "passes-thru", then
873  // don't try to change it. It will be changed along with
874  // the use if required to break an earlier antidep.
875  LLVM_DEBUG(dbgs() << " (passthru)\n");
876  continue;
877  } else {
878  // No anti-dep breaking for implicit deps
879  MachineOperand *AntiDepOp = MI.findRegisterDefOperand(AntiDepReg);
880  assert(AntiDepOp && "Can't find index for defined register operand");
881  if (!AntiDepOp || AntiDepOp->isImplicit()) {
882  LLVM_DEBUG(dbgs() << " (implicit)\n");
883  continue;
884  }
885 
886  // If the SUnit has other dependencies on the SUnit that
887  // it anti-depends on, don't bother breaking the
888  // anti-dependency since those edges would prevent such
889  // units from being scheduled past each other
890  // regardless.
891  //
892  // Also, if there are dependencies on other SUnits with the
893  // same register as the anti-dependency, don't attempt to
894  // break it.
895  for (SUnit::const_pred_iterator P = PathSU->Preds.begin(),
896  PE = PathSU->Preds.end(); P != PE; ++P) {
897  if (P->getSUnit() == NextSU ?
898  (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) :
899  (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {
900  AntiDepReg = 0;
901  break;
902  }
903  }
904  for (SUnit::const_pred_iterator P = PathSU->Preds.begin(),
905  PE = PathSU->Preds.end(); P != PE; ++P) {
906  if ((P->getSUnit() == NextSU) && (P->getKind() != SDep::Anti) &&
907  (P->getKind() != SDep::Output)) {
908  LLVM_DEBUG(dbgs() << " (real dependency)\n");
909  AntiDepReg = 0;
910  break;
911  } else if ((P->getSUnit() != NextSU) &&
912  (P->getKind() == SDep::Data) &&
913  (P->getReg() == AntiDepReg)) {
914  LLVM_DEBUG(dbgs() << " (other dependency)\n");
915  AntiDepReg = 0;
916  break;
917  }
918  }
919 
920  if (AntiDepReg == 0) continue;
921 
922  // If the definition of the anti-dependency register does not start
923  // a new live range, bail out. This can happen if the anti-dep
924  // register is a sub-register of another register whose live range
925  // spans over PathSU. In such case, PathSU defines only a part of
926  // the larger register.
927  RegAliases.reset();
928  for (MCRegAliasIterator AI(AntiDepReg, TRI, true); AI.isValid(); ++AI)
929  RegAliases.set(*AI);
930  for (SDep S : PathSU->Succs) {
931  SDep::Kind K = S.getKind();
932  if (K != SDep::Data && K != SDep::Output && K != SDep::Anti)
933  continue;
934  unsigned R = S.getReg();
935  if (!RegAliases[R])
936  continue;
937  if (R == AntiDepReg || TRI->isSubRegister(AntiDepReg, R))
938  continue;
939  AntiDepReg = 0;
940  break;
941  }
942 
943  if (AntiDepReg == 0) continue;
944  }
945 
946  assert(AntiDepReg != 0);
947  if (AntiDepReg == 0) continue;
948 
949  // Determine AntiDepReg's register group.
950  const unsigned GroupIndex = State->GetGroup(AntiDepReg);
951  if (GroupIndex == 0) {
952  LLVM_DEBUG(dbgs() << " (zero group)\n");
953  continue;
954  }
955 
956  LLVM_DEBUG(dbgs() << '\n');
957 
958  // Look for a suitable register to use to break the anti-dependence.
959  std::map<unsigned, unsigned> RenameMap;
960  if (FindSuitableFreeRegisters(GroupIndex, RenameOrder, RenameMap)) {
961  LLVM_DEBUG(dbgs() << "\tBreaking anti-dependence edge on "
962  << printReg(AntiDepReg, TRI) << ":");
963 
964  // Handle each group register...
965  for (std::map<unsigned, unsigned>::iterator
966  S = RenameMap.begin(), E = RenameMap.end(); S != E; ++S) {
967  unsigned CurrReg = S->first;
968  unsigned NewReg = S->second;
969 
970  LLVM_DEBUG(dbgs() << " " << printReg(CurrReg, TRI) << "->"
971  << printReg(NewReg, TRI) << "("
972  << RegRefs.count(CurrReg) << " refs)");
973 
974  // Update the references to the old register CurrReg to
975  // refer to the new register NewReg.
976  for (const auto &Q : make_range(RegRefs.equal_range(CurrReg))) {
977  Q.second.Operand->setReg(NewReg);
978  // If the SU for the instruction being updated has debug
979  // information related to the anti-dependency register, make
980  // sure to update that as well.
981  const SUnit *SU = MISUnitMap[Q.second.Operand->getParent()];
982  if (!SU) continue;
983  UpdateDbgValues(DbgValues, Q.second.Operand->getParent(),
984  AntiDepReg, NewReg);
985  }
986 
987  // We just went back in time and modified history; the
988  // liveness information for CurrReg is now inconsistent. Set
989  // the state as if it were dead.
990  State->UnionGroups(NewReg, 0);
991  RegRefs.erase(NewReg);
992  DefIndices[NewReg] = DefIndices[CurrReg];
993  KillIndices[NewReg] = KillIndices[CurrReg];
994 
995  State->UnionGroups(CurrReg, 0);
996  RegRefs.erase(CurrReg);
997  DefIndices[CurrReg] = KillIndices[CurrReg];
998  KillIndices[CurrReg] = ~0u;
999  assert(((KillIndices[CurrReg] == ~0u) !=
1000  (DefIndices[CurrReg] == ~0u)) &&
1001  "Kill and Def maps aren't consistent for AntiDepReg!");
1002  }
1003 
1004  ++Broken;
1005  LLVM_DEBUG(dbgs() << '\n');
1006  }
1007  }
1008  }
1009 
1010  ScanInstruction(MI, Count);
1011  }
1012 
1013  return Broken;
1014 }
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not...
ArrayRef< MCPhysReg > getOrder(const TargetRegisterClass *RC) const
getOrder - Returns the preferred allocation order for RC.
Information about a register reference within a liverange.
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:485
bool isAllocatable(unsigned PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn&#39;t been...
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
MachineOperand * findRegisterDefOperand(unsigned Reg, bool isDead=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
bool empty() const
empty - Tests whether there are no bits in this bitvector.
Definition: BitVector.h:167
bool hasExtraDefRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction def operands have special register allocation requirements that are ...
Definition: MachineInstr.h:779
unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const
For a given register pair, return the sub-register index if the second register is a sub-register of ...
unsigned getDepth() const
Returns the depth of this node, which is the length of the maximum path up to any node which has no p...
Definition: ScheduleDAG.h:403
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
AggressiveAntiDepState(const unsigned TargetRegs, MachineBasicBlock *BB)
unsigned getReg() const
getReg - Returns the register number.
MachineOperand * findRegisterUseOperand(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
unsigned Reg
bool isInlineAsm() const
Definition: MachineInstr.h:867
bool test(unsigned Idx) const
Definition: BitVector.h:502
unsigned second
unsigned const TargetRegisterInfo * TRI
unsigned getReg() const
Returns the register associated with this edge.
Definition: ScheduleDAG.h:219
Kind
These are the different kinds of scheduling dependencies.
Definition: ScheduleDAG.h:53
SmallVector< SDep, 4 > Preds
All sunit predecessors.
Definition: ScheduleDAG.h:261
A register anti-dependence (aka WAR).
Definition: ScheduleDAG.h:55
void StartBlock(MachineBasicBlock *BB) override
Initialize anti-dep breaking for a new basic block.
bool isEarlyClobber() const
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
AggressiveAntiDepBreaker(MachineFunction &MFi, const RegisterClassInfo &RCI, TargetSubtargetInfo::RegClassVector &CriticalPathRCs)
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction. ...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:209
const HexagonInstrInfo * TII
This class works in conjunction with the post-RA scheduler to rename registers to break register anti...
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:314
const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
SmallVectorImpl< SDep >::const_iterator const_pred_iterator
Definition: ScheduleDAG.h:266
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
Regular data dependence (aka true-dependence).
Definition: ScheduleDAG.h:54
bool isSubRegister(unsigned RegA, unsigned RegB) const
Returns true if RegB is a sub-register of RegA.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
ELFYAML::ELF_STO Other
Definition: ELFYAML.cpp:773
A register output-dependence (aka WAW).
Definition: ScheduleDAG.h:56
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:308
const RegList & Regs
void GetGroupRegs(unsigned Group, std::vector< unsigned > &Regs, std::multimap< unsigned, AggressiveAntiDepState::RegisterReference > *RegRefs)
unsigned UnionGroups(unsigned Reg1, unsigned Reg2)
SUnit * getSUnit() const
Definition: ScheduleDAG.h:490
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool isSuperRegister(unsigned RegA, unsigned RegB) const
Returns true if RegB is a super-register of RegA.
Scheduling dependency.
Definition: ScheduleDAG.h:50
#define P(N)
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:410
std::vector< std::pair< MachineInstr *, MachineInstr * > > DbgValueVector
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
Definition: ScheduleDAG.h:378
unsigned BreakAntiDependencies(const std::vector< SUnit > &SUnits, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, unsigned InsertPosIndex, DbgValueVector &DbgValues) override
Identifiy anti-dependencies along the critical path of the ScheduleDAG and break them by renaming reg...
unsigned const MachineRegisterInfo * MRI
unsigned short Latency
Node latency.
Definition: ScheduleDAG.h:278
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineInstrBuilder & UseMI
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:135
bool any() const
any - Returns true if any bit is set.
Definition: BitVector.h:181
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
void FinishBlock() override
Finish anti-dep breaking for a basic block.
MCRegAliasIterator enumerates all registers aliasing Reg.
static const SUnit * CriticalPathStep(const SUnit *SU)
CriticalPathStep - Return the next SUnit after SU on the bottom-up critical path. ...
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:181
void Observe(MachineInstr &MI, unsigned Count, unsigned InsertPosIndex) override
Update liveness information to account for the current instruction, which will not be scheduled...
MCSubRegIterator enumerates all sub-registers of Reg.
size_t size() const
Definition: SmallVector.h:53
virtual bool isPredicated(const MachineInstr &MI) const
Returns true if the instruction is already predicated.
bool isDebugInstr() const
Definition: MachineInstr.h:851
unsigned first
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
std::vector< unsigned > & GetDefIndices()
Return the define indices.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
int findRegisterDefOperandIdx(unsigned Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found...
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:965
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:156
bool none() const
none - Returns true if none of the bits are set.
Definition: BitVector.h:202
Representation of each machine instruction.
Definition: MachineInstr.h:60
std::multimap< unsigned, RegisterReference > & GetRegRefs()
Return the RegRefs map.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
#define I(x, y, z)
Definition: MD5.cpp:58
bool hasExtraSrcRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction source operands have special register allocation requirements that a...
Definition: MachineInstr.h:769
Kind getKind() const
Returns an enum value representing the kind of the dependence.
Definition: ScheduleDAG.h:496
bool isKill() const
Definition: MachineInstr.h:865
bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx=nullptr) const
Given the index of a register def operand, check if the register def is tied to a source operand...
static cl::opt< int > DebugDiv("agg-antidep-debugdiv", cl::desc("Debug control for aggressive anti-dep breaker"), cl::init(0), cl::Hidden)
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void UpdateDbgValues(const DbgValueVector &DbgValues, MachineInstr *ParentMI, unsigned OldReg, unsigned NewReg)
Update all DBG_VALUE instructions that may be affected by the dependency breaker&#39;s update of ParentMI...
static void AntiDepEdges(const SUnit *SU, std::vector< const SDep *> &Edges)
AntiDepEdges - Return in Edges the anti- and output- dependencies in SU that we want to consider for ...
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:130
SmallVector< SDep, 4 > Succs
All sunit successors.
Definition: ScheduleDAG.h:262
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
IRTranslator LLVM IR MI
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
Contains all the state necessary for anti-dep breaking.
static cl::opt< int > DebugMod("agg-antidep-debugmod", cl::desc("Debug control for aggressive anti-dep breaker"), cl::init(0), cl::Hidden)
#define LLVM_DEBUG(X)
Definition: Debug.h:123
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:316
bool IsLive(unsigned Reg)
Return true if Reg is live.
std::vector< unsigned > & GetKillIndices()
Return the kill indices.
std::vector< MachineBasicBlock * >::iterator succ_iterator
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:247
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:144
bool isImplicit() const