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AggressiveAntiDepBreaker.cpp
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1 //===- AggressiveAntiDepBreaker.cpp - Anti-dep breaker --------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the AggressiveAntiDepBreaker class, which
11 // implements register anti-dependence breaking during post-RA
12 // scheduling. It attempts to break all anti-dependencies within a
13 // block.
14 //
15 //===----------------------------------------------------------------------===//
16 
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/SmallSet.h"
34 #include "llvm/MC/MCInstrDesc.h"
35 #include "llvm/MC/MCRegisterInfo.h"
37 #include "llvm/Support/Debug.h"
39 #include <cassert>
40 #include <map>
41 #include <set>
42 #include <utility>
43 #include <vector>
44 
45 using namespace llvm;
46 
47 #define DEBUG_TYPE "post-RA-sched"
48 
49 // If DebugDiv > 0 then only break antidep with (ID % DebugDiv) == DebugMod
50 static cl::opt<int>
51 DebugDiv("agg-antidep-debugdiv",
52  cl::desc("Debug control for aggressive anti-dep breaker"),
53  cl::init(0), cl::Hidden);
54 
55 static cl::opt<int>
56 DebugMod("agg-antidep-debugmod",
57  cl::desc("Debug control for aggressive anti-dep breaker"),
58  cl::init(0), cl::Hidden);
59 
62  : NumTargetRegs(TargetRegs), GroupNodes(TargetRegs, 0),
63  GroupNodeIndices(TargetRegs, 0), KillIndices(TargetRegs, 0),
64  DefIndices(TargetRegs, 0) {
65  const unsigned BBSize = BB->size();
66  for (unsigned i = 0; i < NumTargetRegs; ++i) {
67  // Initialize all registers to be in their own group. Initially we
68  // assign the register to the same-indexed GroupNode.
69  GroupNodeIndices[i] = i;
70  // Initialize the indices to indicate that no registers are live.
71  KillIndices[i] = ~0u;
72  DefIndices[i] = BBSize;
73  }
74 }
75 
77  unsigned Node = GroupNodeIndices[Reg];
78  while (GroupNodes[Node] != Node)
79  Node = GroupNodes[Node];
80 
81  return Node;
82 }
83 
85  unsigned Group,
86  std::vector<unsigned> &Regs,
87  std::multimap<unsigned, AggressiveAntiDepState::RegisterReference> *RegRefs)
88 {
89  for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
90  if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
91  Regs.push_back(Reg);
92  }
93 }
94 
95 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) {
96  assert(GroupNodes[0] == 0 && "GroupNode 0 not parent!");
97  assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
98 
99  // find group for each register
100  unsigned Group1 = GetGroup(Reg1);
101  unsigned Group2 = GetGroup(Reg2);
102 
103  // if either group is 0, then that must become the parent
104  unsigned Parent = (Group1 == 0) ? Group1 : Group2;
105  unsigned Other = (Parent == Group1) ? Group2 : Group1;
106  GroupNodes.at(Other) = Parent;
107  return Parent;
108 }
109 
111  // Create a new GroupNode for Reg. Reg's existing GroupNode must
112  // stay as is because there could be other GroupNodes referring to
113  // it.
114  unsigned idx = GroupNodes.size();
115  GroupNodes.push_back(idx);
116  GroupNodeIndices[Reg] = idx;
117  return idx;
118 }
119 
121  // KillIndex must be defined and DefIndex not defined for a register
122  // to be live.
123  return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u));
124 }
125 
127  MachineFunction &MFi, const RegisterClassInfo &RCI,
128  TargetSubtargetInfo::RegClassVector &CriticalPathRCs)
129  : AntiDepBreaker(), MF(MFi), MRI(MF.getRegInfo()),
130  TII(MF.getSubtarget().getInstrInfo()),
131  TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI) {
132  /* Collect a bitset of all registers that are only broken if they
133  are on the critical path. */
134  for (unsigned i = 0, e = CriticalPathRCs.size(); i < e; ++i) {
135  BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]);
136  if (CriticalPathSet.none())
137  CriticalPathSet = CPSet;
138  else
139  CriticalPathSet |= CPSet;
140  }
141 
142  DEBUG(dbgs() << "AntiDep Critical-Path Registers:");
143  DEBUG(for (unsigned r : CriticalPathSet.set_bits())
144  dbgs() << " " << TRI->getName(r));
145  DEBUG(dbgs() << '\n');
146 }
147 
149  delete State;
150 }
151 
153  assert(!State);
154  State = new AggressiveAntiDepState(TRI->getNumRegs(), BB);
155 
156  bool IsReturnBlock = BB->isReturnBlock();
157  std::vector<unsigned> &KillIndices = State->GetKillIndices();
158  std::vector<unsigned> &DefIndices = State->GetDefIndices();
159 
160  // Examine the live-in regs of all successors.
162  SE = BB->succ_end(); SI != SE; ++SI)
163  for (const auto &LI : (*SI)->liveins()) {
164  for (MCRegAliasIterator AI(LI.PhysReg, TRI, true); AI.isValid(); ++AI) {
165  unsigned Reg = *AI;
166  State->UnionGroups(Reg, 0);
167  KillIndices[Reg] = BB->size();
168  DefIndices[Reg] = ~0u;
169  }
170  }
171 
172  // Mark live-out callee-saved registers. In a return block this is
173  // all callee-saved registers. In non-return this is any
174  // callee-saved register that is not saved in the prolog.
175  const MachineFrameInfo &MFI = MF.getFrameInfo();
176  BitVector Pristine = MFI.getPristineRegs(MF);
177  for (const MCPhysReg *I = MF.getRegInfo().getCalleeSavedRegs(); *I;
178  ++I) {
179  unsigned Reg = *I;
180  if (!IsReturnBlock && !Pristine.test(Reg))
181  continue;
182  for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
183  unsigned AliasReg = *AI;
184  State->UnionGroups(AliasReg, 0);
185  KillIndices[AliasReg] = BB->size();
186  DefIndices[AliasReg] = ~0u;
187  }
188  }
189 }
190 
192  delete State;
193  State = nullptr;
194 }
195 
197  unsigned InsertPosIndex) {
198  assert(Count < InsertPosIndex && "Instruction index out of expected range!");
199 
200  std::set<unsigned> PassthruRegs;
201  GetPassthruRegs(MI, PassthruRegs);
202  PrescanInstruction(MI, Count, PassthruRegs);
203  ScanInstruction(MI, Count);
204 
205  DEBUG(dbgs() << "Observe: ");
206  DEBUG(MI.dump());
207  DEBUG(dbgs() << "\tRegs:");
208 
209  std::vector<unsigned> &DefIndices = State->GetDefIndices();
210  for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
211  // If Reg is current live, then mark that it can't be renamed as
212  // we don't know the extent of its live-range anymore (now that it
213  // has been scheduled). If it is not live but was defined in the
214  // previous schedule region, then set its def index to the most
215  // conservative location (i.e. the beginning of the previous
216  // schedule region).
217  if (State->IsLive(Reg)) {
218  DEBUG(if (State->GetGroup(Reg) != 0)
219  dbgs() << " " << TRI->getName(Reg) << "=g" <<
220  State->GetGroup(Reg) << "->g0(region live-out)");
221  State->UnionGroups(Reg, 0);
222  } else if ((DefIndices[Reg] < InsertPosIndex)
223  && (DefIndices[Reg] >= Count)) {
224  DefIndices[Reg] = Count;
225  }
226  }
227  DEBUG(dbgs() << '\n');
228 }
229 
230 bool AggressiveAntiDepBreaker::IsImplicitDefUse(MachineInstr &MI,
231  MachineOperand &MO) {
232  if (!MO.isReg() || !MO.isImplicit())
233  return false;
234 
235  unsigned Reg = MO.getReg();
236  if (Reg == 0)
237  return false;
238 
239  MachineOperand *Op = nullptr;
240  if (MO.isDef())
241  Op = MI.findRegisterUseOperand(Reg, true);
242  else
243  Op = MI.findRegisterDefOperand(Reg);
244 
245  return(Op && Op->isImplicit());
246 }
247 
248 void AggressiveAntiDepBreaker::GetPassthruRegs(
249  MachineInstr &MI, std::set<unsigned> &PassthruRegs) {
250  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
251  MachineOperand &MO = MI.getOperand(i);
252  if (!MO.isReg()) continue;
253  if ((MO.isDef() && MI.isRegTiedToUseOperand(i)) ||
254  IsImplicitDefUse(MI, MO)) {
255  const unsigned Reg = MO.getReg();
256  for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
257  SubRegs.isValid(); ++SubRegs)
258  PassthruRegs.insert(*SubRegs);
259  }
260  }
261 }
262 
263 /// AntiDepEdges - Return in Edges the anti- and output- dependencies
264 /// in SU that we want to consider for breaking.
265 static void AntiDepEdges(const SUnit *SU, std::vector<const SDep *> &Edges) {
266  SmallSet<unsigned, 4> RegSet;
267  for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
268  P != PE; ++P) {
269  if ((P->getKind() == SDep::Anti) || (P->getKind() == SDep::Output)) {
270  if (RegSet.insert(P->getReg()).second)
271  Edges.push_back(&*P);
272  }
273  }
274 }
275 
276 /// CriticalPathStep - Return the next SUnit after SU on the bottom-up
277 /// critical path.
278 static const SUnit *CriticalPathStep(const SUnit *SU) {
279  const SDep *Next = nullptr;
280  unsigned NextDepth = 0;
281  // Find the predecessor edge with the greatest depth.
282  if (SU) {
283  for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
284  P != PE; ++P) {
285  const SUnit *PredSU = P->getSUnit();
286  unsigned PredLatency = P->getLatency();
287  unsigned PredTotalLatency = PredSU->getDepth() + PredLatency;
288  // In the case of a latency tie, prefer an anti-dependency edge over
289  // other types of edges.
290  if (NextDepth < PredTotalLatency ||
291  (NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) {
292  NextDepth = PredTotalLatency;
293  Next = &*P;
294  }
295  }
296  }
297 
298  return (Next) ? Next->getSUnit() : nullptr;
299 }
300 
301 void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx,
302  const char *tag,
303  const char *header,
304  const char *footer) {
305  std::vector<unsigned> &KillIndices = State->GetKillIndices();
306  std::vector<unsigned> &DefIndices = State->GetDefIndices();
307  std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
308  RegRefs = State->GetRegRefs();
309 
310  // FIXME: We must leave subregisters of live super registers as live, so that
311  // we don't clear out the register tracking information for subregisters of
312  // super registers we're still tracking (and with which we're unioning
313  // subregister definitions).
314  for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
315  if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI)) {
316  DEBUG(if (!header && footer) dbgs() << footer);
317  return;
318  }
319 
320  if (!State->IsLive(Reg)) {
321  KillIndices[Reg] = KillIdx;
322  DefIndices[Reg] = ~0u;
323  RegRefs.erase(Reg);
324  State->LeaveGroup(Reg);
325  DEBUG(if (header) {
326  dbgs() << header << TRI->getName(Reg); header = nullptr; });
327  DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag);
328  // Repeat for subregisters. Note that we only do this if the superregister
329  // was not live because otherwise, regardless whether we have an explicit
330  // use of the subregister, the subregister's contents are needed for the
331  // uses of the superregister.
332  for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
333  unsigned SubregReg = *SubRegs;
334  if (!State->IsLive(SubregReg)) {
335  KillIndices[SubregReg] = KillIdx;
336  DefIndices[SubregReg] = ~0u;
337  RegRefs.erase(SubregReg);
338  State->LeaveGroup(SubregReg);
339  DEBUG(if (header) {
340  dbgs() << header << TRI->getName(Reg); header = nullptr; });
341  DEBUG(dbgs() << " " << TRI->getName(SubregReg) << "->g" <<
342  State->GetGroup(SubregReg) << tag);
343  }
344  }
345  }
346 
347  DEBUG(if (!header && footer) dbgs() << footer);
348 }
349 
350 void AggressiveAntiDepBreaker::PrescanInstruction(
351  MachineInstr &MI, unsigned Count, std::set<unsigned> &PassthruRegs) {
352  std::vector<unsigned> &DefIndices = State->GetDefIndices();
353  std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
354  RegRefs = State->GetRegRefs();
355 
356  // Handle dead defs by simulating a last-use of the register just
357  // after the def. A dead def can occur because the def is truly
358  // dead, or because only a subregister is live at the def. If we
359  // don't do this the dead def will be incorrectly merged into the
360  // previous def.
361  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
362  MachineOperand &MO = MI.getOperand(i);
363  if (!MO.isReg() || !MO.isDef()) continue;
364  unsigned Reg = MO.getReg();
365  if (Reg == 0) continue;
366 
367  HandleLastUse(Reg, Count + 1, "", "\tDead Def: ", "\n");
368  }
369 
370  DEBUG(dbgs() << "\tDef Groups:");
371  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
372  MachineOperand &MO = MI.getOperand(i);
373  if (!MO.isReg() || !MO.isDef()) continue;
374  unsigned Reg = MO.getReg();
375  if (Reg == 0) continue;
376 
377  DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" << State->GetGroup(Reg));
378 
379  // If MI's defs have a special allocation requirement, don't allow
380  // any def registers to be changed. Also assume all registers
381  // defined in a call must not be changed (ABI). Inline assembly may
382  // reference either system calls or the register directly. Skip it until we
383  // can tell user specified registers from compiler-specified.
384  if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI) ||
385  MI.isInlineAsm()) {
386  DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
387  State->UnionGroups(Reg, 0);
388  }
389 
390  // Any aliased that are live at this point are completely or
391  // partially defined here, so group those aliases with Reg.
392  for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) {
393  unsigned AliasReg = *AI;
394  if (State->IsLive(AliasReg)) {
395  State->UnionGroups(Reg, AliasReg);
396  DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via " <<
397  TRI->getName(AliasReg) << ")");
398  }
399  }
400 
401  // Note register reference...
402  const TargetRegisterClass *RC = nullptr;
403  if (i < MI.getDesc().getNumOperands())
404  RC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
406  RegRefs.insert(std::make_pair(Reg, RR));
407  }
408 
409  DEBUG(dbgs() << '\n');
410 
411  // Scan the register defs for this instruction and update
412  // live-ranges.
413  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
414  MachineOperand &MO = MI.getOperand(i);
415  if (!MO.isReg() || !MO.isDef()) continue;
416  unsigned Reg = MO.getReg();
417  if (Reg == 0) continue;
418  // Ignore KILLs and passthru registers for liveness...
419  if (MI.isKill() || (PassthruRegs.count(Reg) != 0))
420  continue;
421 
422  // Update def for Reg and aliases.
423  for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
424  // We need to be careful here not to define already-live super registers.
425  // If the super register is already live, then this definition is not
426  // a definition of the whole super register (just a partial insertion
427  // into it). Earlier subregister definitions (which we've not yet visited
428  // because we're iterating bottom-up) need to be linked to the same group
429  // as this definition.
430  if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI))
431  continue;
432 
433  DefIndices[*AI] = Count;
434  }
435  }
436 }
437 
438 void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI,
439  unsigned Count) {
440  DEBUG(dbgs() << "\tUse Groups:");
441  std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
442  RegRefs = State->GetRegRefs();
443 
444  // If MI's uses have special allocation requirement, don't allow
445  // any use registers to be changed. Also assume all registers
446  // used in a call must not be changed (ABI).
447  // Inline Assembly register uses also cannot be safely changed.
448  // FIXME: The issue with predicated instruction is more complex. We are being
449  // conservatively here because the kill markers cannot be trusted after
450  // if-conversion:
451  // %R6<def> = LDR %SP, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14]
452  // ...
453  // STR %R0, %R6<kill>, %reg0, 0, pred:0, pred:%CPSR; mem:ST4[%395]
454  // %R6<def> = LDR %SP, %reg0, 100, pred:0, pred:%CPSR; mem:LD4[FixedStack12]
455  // STR %R0, %R6<kill>, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8)
456  //
457  // The first R6 kill is not really a kill since it's killed by a predicated
458  // instruction which may not be executed. The second R6 def may or may not
459  // re-define R6 so it's not safe to change it since the last R6 use cannot be
460  // changed.
461  bool Special = MI.isCall() || MI.hasExtraSrcRegAllocReq() ||
462  TII->isPredicated(MI) || MI.isInlineAsm();
463 
464  // Scan the register uses for this instruction and update
465  // live-ranges, groups and RegRefs.
466  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
467  MachineOperand &MO = MI.getOperand(i);
468  if (!MO.isReg() || !MO.isUse()) continue;
469  unsigned Reg = MO.getReg();
470  if (Reg == 0) continue;
471 
472  DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" <<
473  State->GetGroup(Reg));
474 
475  // It wasn't previously live but now it is, this is a kill. Forget
476  // the previous live-range information and start a new live-range
477  // for the register.
478  HandleLastUse(Reg, Count, "(last-use)");
479 
480  if (Special) {
481  DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
482  State->UnionGroups(Reg, 0);
483  }
484 
485  // Note register reference...
486  const TargetRegisterClass *RC = nullptr;
487  if (i < MI.getDesc().getNumOperands())
488  RC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
490  RegRefs.insert(std::make_pair(Reg, RR));
491  }
492 
493  DEBUG(dbgs() << '\n');
494 
495  // Form a group of all defs and uses of a KILL instruction to ensure
496  // that all registers are renamed as a group.
497  if (MI.isKill()) {
498  DEBUG(dbgs() << "\tKill Group:");
499 
500  unsigned FirstReg = 0;
501  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
502  MachineOperand &MO = MI.getOperand(i);
503  if (!MO.isReg()) continue;
504  unsigned Reg = MO.getReg();
505  if (Reg == 0) continue;
506 
507  if (FirstReg != 0) {
508  DEBUG(dbgs() << "=" << TRI->getName(Reg));
509  State->UnionGroups(FirstReg, Reg);
510  } else {
511  DEBUG(dbgs() << " " << TRI->getName(Reg));
512  FirstReg = Reg;
513  }
514  }
515 
516  DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n');
517  }
518 }
519 
520 BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) {
521  BitVector BV(TRI->getNumRegs(), false);
522  bool first = true;
523 
524  // Check all references that need rewriting for Reg. For each, use
525  // the corresponding register class to narrow the set of registers
526  // that are appropriate for renaming.
527  for (const auto &Q : make_range(State->GetRegRefs().equal_range(Reg))) {
528  const TargetRegisterClass *RC = Q.second.RC;
529  if (!RC) continue;
530 
531  BitVector RCBV = TRI->getAllocatableSet(MF, RC);
532  if (first) {
533  BV |= RCBV;
534  first = false;
535  } else {
536  BV &= RCBV;
537  }
538 
539  DEBUG(dbgs() << " " << TRI->getRegClassName(RC));
540  }
541 
542  return BV;
543 }
544 
545 bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
546  unsigned AntiDepGroupIndex,
547  RenameOrderType& RenameOrder,
548  std::map<unsigned, unsigned> &RenameMap) {
549  std::vector<unsigned> &KillIndices = State->GetKillIndices();
550  std::vector<unsigned> &DefIndices = State->GetDefIndices();
551  std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
552  RegRefs = State->GetRegRefs();
553 
554  // Collect all referenced registers in the same group as
555  // AntiDepReg. These all need to be renamed together if we are to
556  // break the anti-dependence.
557  std::vector<unsigned> Regs;
558  State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs);
559  assert(!Regs.empty() && "Empty register group!");
560  if (Regs.empty())
561  return false;
562 
563  // Find the "superest" register in the group. At the same time,
564  // collect the BitVector of registers that can be used to rename
565  // each register.
566  DEBUG(dbgs() << "\tRename Candidates for Group g" << AntiDepGroupIndex
567  << ":\n");
568  std::map<unsigned, BitVector> RenameRegisterMap;
569  unsigned SuperReg = 0;
570  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
571  unsigned Reg = Regs[i];
572  if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg))
573  SuperReg = Reg;
574 
575  // If Reg has any references, then collect possible rename regs
576  if (RegRefs.count(Reg) > 0) {
577  DEBUG(dbgs() << "\t\t" << TRI->getName(Reg) << ":");
578 
579  BitVector &BV = RenameRegisterMap[Reg];
580  assert(BV.empty());
581  BV = GetRenameRegisters(Reg);
582 
583  DEBUG({
584  dbgs() << " ::";
585  for (unsigned r : BV.set_bits())
586  dbgs() << " " << TRI->getName(r);
587  dbgs() << "\n";
588  });
589  }
590  }
591 
592  // All group registers should be a subreg of SuperReg.
593  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
594  unsigned Reg = Regs[i];
595  if (Reg == SuperReg) continue;
596  bool IsSub = TRI->isSubRegister(SuperReg, Reg);
597  // FIXME: remove this once PR18663 has been properly fixed. For now,
598  // return a conservative answer:
599  // assert(IsSub && "Expecting group subregister");
600  if (!IsSub)
601  return false;
602  }
603 
604 #ifndef NDEBUG
605  // If DebugDiv > 0 then only rename (renamecnt % DebugDiv) == DebugMod
606  if (DebugDiv > 0) {
607  static int renamecnt = 0;
608  if (renamecnt++ % DebugDiv != DebugMod)
609  return false;
610 
611  dbgs() << "*** Performing rename " << TRI->getName(SuperReg) <<
612  " for debug ***\n";
613  }
614 #endif
615 
616  // Check each possible rename register for SuperReg in round-robin
617  // order. If that register is available, and the corresponding
618  // registers are available for the other group subregisters, then we
619  // can use those registers to rename.
620 
621  // FIXME: Using getMinimalPhysRegClass is very conservative. We should
622  // check every use of the register and find the largest register class
623  // that can be used in all of them.
624  const TargetRegisterClass *SuperRC =
625  TRI->getMinimalPhysRegClass(SuperReg, MVT::Other);
626 
627  ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC);
628  if (Order.empty()) {
629  DEBUG(dbgs() << "\tEmpty Super Regclass!!\n");
630  return false;
631  }
632 
633  DEBUG(dbgs() << "\tFind Registers:");
634 
635  RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size()));
636 
637  unsigned OrigR = RenameOrder[SuperRC];
638  unsigned EndR = ((OrigR == Order.size()) ? 0 : OrigR);
639  unsigned R = OrigR;
640  do {
641  if (R == 0) R = Order.size();
642  --R;
643  const unsigned NewSuperReg = Order[R];
644  // Don't consider non-allocatable registers
645  if (!MRI.isAllocatable(NewSuperReg)) continue;
646  // Don't replace a register with itself.
647  if (NewSuperReg == SuperReg) continue;
648 
649  DEBUG(dbgs() << " [" << TRI->getName(NewSuperReg) << ':');
650  RenameMap.clear();
651 
652  // For each referenced group register (which must be a SuperReg or
653  // a subregister of SuperReg), find the corresponding subregister
654  // of NewSuperReg and make sure it is free to be renamed.
655  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
656  unsigned Reg = Regs[i];
657  unsigned NewReg = 0;
658  if (Reg == SuperReg) {
659  NewReg = NewSuperReg;
660  } else {
661  unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg);
662  if (NewSubRegIdx != 0)
663  NewReg = TRI->getSubReg(NewSuperReg, NewSubRegIdx);
664  }
665 
666  DEBUG(dbgs() << " " << TRI->getName(NewReg));
667 
668  // Check if Reg can be renamed to NewReg.
669  if (!RenameRegisterMap[Reg].test(NewReg)) {
670  DEBUG(dbgs() << "(no rename)");
671  goto next_super_reg;
672  }
673 
674  // If NewReg is dead and NewReg's most recent def is not before
675  // Regs's kill, it's safe to replace Reg with NewReg. We
676  // must also check all aliases of NewReg, because we can't define a
677  // register when any sub or super is already live.
678  if (State->IsLive(NewReg) || (KillIndices[Reg] > DefIndices[NewReg])) {
679  DEBUG(dbgs() << "(live)");
680  goto next_super_reg;
681  } else {
682  bool found = false;
683  for (MCRegAliasIterator AI(NewReg, TRI, false); AI.isValid(); ++AI) {
684  unsigned AliasReg = *AI;
685  if (State->IsLive(AliasReg) ||
686  (KillIndices[Reg] > DefIndices[AliasReg])) {
687  DEBUG(dbgs() << "(alias " << TRI->getName(AliasReg) << " live)");
688  found = true;
689  break;
690  }
691  }
692  if (found)
693  goto next_super_reg;
694  }
695 
696  // We cannot rename 'Reg' to 'NewReg' if one of the uses of 'Reg' also
697  // defines 'NewReg' via an early-clobber operand.
698  for (const auto &Q : make_range(RegRefs.equal_range(Reg))) {
699  MachineInstr *UseMI = Q.second.Operand->getParent();
700  int Idx = UseMI->findRegisterDefOperandIdx(NewReg, false, true, TRI);
701  if (Idx == -1)
702  continue;
703 
704  if (UseMI->getOperand(Idx).isEarlyClobber()) {
705  DEBUG(dbgs() << "(ec)");
706  goto next_super_reg;
707  }
708  }
709 
710  // Also, we cannot rename 'Reg' to 'NewReg' if the instruction defining
711  // 'Reg' is an early-clobber define and that instruction also uses
712  // 'NewReg'.
713  for (const auto &Q : make_range(RegRefs.equal_range(Reg))) {
714  if (!Q.second.Operand->isDef() || !Q.second.Operand->isEarlyClobber())
715  continue;
716 
717  MachineInstr *DefMI = Q.second.Operand->getParent();
718  if (DefMI->readsRegister(NewReg, TRI)) {
719  DEBUG(dbgs() << "(ec)");
720  goto next_super_reg;
721  }
722  }
723 
724  // Record that 'Reg' can be renamed to 'NewReg'.
725  RenameMap.insert(std::pair<unsigned, unsigned>(Reg, NewReg));
726  }
727 
728  // If we fall-out here, then every register in the group can be
729  // renamed, as recorded in RenameMap.
730  RenameOrder.erase(SuperRC);
731  RenameOrder.insert(RenameOrderType::value_type(SuperRC, R));
732  DEBUG(dbgs() << "]\n");
733  return true;
734 
735  next_super_reg:
736  DEBUG(dbgs() << ']');
737  } while (R != EndR);
738 
739  DEBUG(dbgs() << '\n');
740 
741  // No registers are free and available!
742  return false;
743 }
744 
745 /// BreakAntiDependencies - Identifiy anti-dependencies within the
746 /// ScheduleDAG and break them by renaming registers.
748  const std::vector<SUnit> &SUnits,
751  unsigned InsertPosIndex,
752  DbgValueVector &DbgValues) {
753  std::vector<unsigned> &KillIndices = State->GetKillIndices();
754  std::vector<unsigned> &DefIndices = State->GetDefIndices();
755  std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
756  RegRefs = State->GetRegRefs();
757 
758  // The code below assumes that there is at least one instruction,
759  // so just duck out immediately if the block is empty.
760  if (SUnits.empty()) return 0;
761 
762  // For each regclass the next register to use for renaming.
763  RenameOrderType RenameOrder;
764 
765  // ...need a map from MI to SUnit.
766  std::map<MachineInstr *, const SUnit *> MISUnitMap;
767  for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
768  const SUnit *SU = &SUnits[i];
769  MISUnitMap.insert(std::pair<MachineInstr *, const SUnit *>(SU->getInstr(),
770  SU));
771  }
772 
773  // Track progress along the critical path through the SUnit graph as
774  // we walk the instructions. This is needed for regclasses that only
775  // break critical-path anti-dependencies.
776  const SUnit *CriticalPathSU = nullptr;
777  MachineInstr *CriticalPathMI = nullptr;
778  if (CriticalPathSet.any()) {
779  for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
780  const SUnit *SU = &SUnits[i];
781  if (!CriticalPathSU ||
782  ((SU->getDepth() + SU->Latency) >
783  (CriticalPathSU->getDepth() + CriticalPathSU->Latency))) {
784  CriticalPathSU = SU;
785  }
786  }
787 
788  CriticalPathMI = CriticalPathSU->getInstr();
789  }
790 
791 #ifndef NDEBUG
792  DEBUG(dbgs() << "\n===== Aggressive anti-dependency breaking\n");
793  DEBUG(dbgs() << "Available regs:");
794  for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
795  if (!State->IsLive(Reg))
796  DEBUG(dbgs() << " " << TRI->getName(Reg));
797  }
798  DEBUG(dbgs() << '\n');
799 #endif
800 
801  BitVector RegAliases(TRI->getNumRegs());
802 
803  // Attempt to break anti-dependence edges. Walk the instructions
804  // from the bottom up, tracking information about liveness as we go
805  // to help determine which registers are available.
806  unsigned Broken = 0;
807  unsigned Count = InsertPosIndex - 1;
808  for (MachineBasicBlock::iterator I = End, E = Begin;
809  I != E; --Count) {
810  MachineInstr &MI = *--I;
811 
812  if (MI.isDebugValue())
813  continue;
814 
815  DEBUG(dbgs() << "Anti: ");
816  DEBUG(MI.dump());
817 
818  std::set<unsigned> PassthruRegs;
819  GetPassthruRegs(MI, PassthruRegs);
820 
821  // Process the defs in MI...
822  PrescanInstruction(MI, Count, PassthruRegs);
823 
824  // The dependence edges that represent anti- and output-
825  // dependencies that are candidates for breaking.
826  std::vector<const SDep *> Edges;
827  const SUnit *PathSU = MISUnitMap[&MI];
828  AntiDepEdges(PathSU, Edges);
829 
830  // If MI is not on the critical path, then we don't rename
831  // registers in the CriticalPathSet.
832  BitVector *ExcludeRegs = nullptr;
833  if (&MI == CriticalPathMI) {
834  CriticalPathSU = CriticalPathStep(CriticalPathSU);
835  CriticalPathMI = (CriticalPathSU) ? CriticalPathSU->getInstr() : nullptr;
836  } else if (CriticalPathSet.any()) {
837  ExcludeRegs = &CriticalPathSet;
838  }
839 
840  // Ignore KILL instructions (they form a group in ScanInstruction
841  // but don't cause any anti-dependence breaking themselves)
842  if (!MI.isKill()) {
843  // Attempt to break each anti-dependency...
844  for (unsigned i = 0, e = Edges.size(); i != e; ++i) {
845  const SDep *Edge = Edges[i];
846  SUnit *NextSU = Edge->getSUnit();
847 
848  if ((Edge->getKind() != SDep::Anti) &&
849  (Edge->getKind() != SDep::Output)) continue;
850 
851  unsigned AntiDepReg = Edge->getReg();
852  DEBUG(dbgs() << "\tAntidep reg: " << TRI->getName(AntiDepReg));
853  assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
854 
855  if (!MRI.isAllocatable(AntiDepReg)) {
856  // Don't break anti-dependencies on non-allocatable registers.
857  DEBUG(dbgs() << " (non-allocatable)\n");
858  continue;
859  } else if (ExcludeRegs && ExcludeRegs->test(AntiDepReg)) {
860  // Don't break anti-dependencies for critical path registers
861  // if not on the critical path
862  DEBUG(dbgs() << " (not critical-path)\n");
863  continue;
864  } else if (PassthruRegs.count(AntiDepReg) != 0) {
865  // If the anti-dep register liveness "passes-thru", then
866  // don't try to change it. It will be changed along with
867  // the use if required to break an earlier antidep.
868  DEBUG(dbgs() << " (passthru)\n");
869  continue;
870  } else {
871  // No anti-dep breaking for implicit deps
872  MachineOperand *AntiDepOp = MI.findRegisterDefOperand(AntiDepReg);
873  assert(AntiDepOp && "Can't find index for defined register operand");
874  if (!AntiDepOp || AntiDepOp->isImplicit()) {
875  DEBUG(dbgs() << " (implicit)\n");
876  continue;
877  }
878 
879  // If the SUnit has other dependencies on the SUnit that
880  // it anti-depends on, don't bother breaking the
881  // anti-dependency since those edges would prevent such
882  // units from being scheduled past each other
883  // regardless.
884  //
885  // Also, if there are dependencies on other SUnits with the
886  // same register as the anti-dependency, don't attempt to
887  // break it.
888  for (SUnit::const_pred_iterator P = PathSU->Preds.begin(),
889  PE = PathSU->Preds.end(); P != PE; ++P) {
890  if (P->getSUnit() == NextSU ?
891  (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) :
892  (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {
893  AntiDepReg = 0;
894  break;
895  }
896  }
897  for (SUnit::const_pred_iterator P = PathSU->Preds.begin(),
898  PE = PathSU->Preds.end(); P != PE; ++P) {
899  if ((P->getSUnit() == NextSU) && (P->getKind() != SDep::Anti) &&
900  (P->getKind() != SDep::Output)) {
901  DEBUG(dbgs() << " (real dependency)\n");
902  AntiDepReg = 0;
903  break;
904  } else if ((P->getSUnit() != NextSU) &&
905  (P->getKind() == SDep::Data) &&
906  (P->getReg() == AntiDepReg)) {
907  DEBUG(dbgs() << " (other dependency)\n");
908  AntiDepReg = 0;
909  break;
910  }
911  }
912 
913  if (AntiDepReg == 0) continue;
914 
915  // If the definition of the anti-dependency register does not start
916  // a new live range, bail out. This can happen if the anti-dep
917  // register is a sub-register of another register whose live range
918  // spans over PathSU. In such case, PathSU defines only a part of
919  // the larger register.
920  RegAliases.reset();
921  for (MCRegAliasIterator AI(AntiDepReg, TRI, true); AI.isValid(); ++AI)
922  RegAliases.set(*AI);
923  for (SDep S : PathSU->Succs) {
924  SDep::Kind K = S.getKind();
925  if (K != SDep::Data && K != SDep::Output && K != SDep::Anti)
926  continue;
927  unsigned R = S.getReg();
928  if (!RegAliases[R])
929  continue;
930  if (R == AntiDepReg || TRI->isSubRegister(AntiDepReg, R))
931  continue;
932  AntiDepReg = 0;
933  break;
934  }
935 
936  if (AntiDepReg == 0) continue;
937  }
938 
939  assert(AntiDepReg != 0);
940  if (AntiDepReg == 0) continue;
941 
942  // Determine AntiDepReg's register group.
943  const unsigned GroupIndex = State->GetGroup(AntiDepReg);
944  if (GroupIndex == 0) {
945  DEBUG(dbgs() << " (zero group)\n");
946  continue;
947  }
948 
949  DEBUG(dbgs() << '\n');
950 
951  // Look for a suitable register to use to break the anti-dependence.
952  std::map<unsigned, unsigned> RenameMap;
953  if (FindSuitableFreeRegisters(GroupIndex, RenameOrder, RenameMap)) {
954  DEBUG(dbgs() << "\tBreaking anti-dependence edge on "
955  << TRI->getName(AntiDepReg) << ":");
956 
957  // Handle each group register...
958  for (std::map<unsigned, unsigned>::iterator
959  S = RenameMap.begin(), E = RenameMap.end(); S != E; ++S) {
960  unsigned CurrReg = S->first;
961  unsigned NewReg = S->second;
962 
963  DEBUG(dbgs() << " " << TRI->getName(CurrReg) << "->" <<
964  TRI->getName(NewReg) << "(" <<
965  RegRefs.count(CurrReg) << " refs)");
966 
967  // Update the references to the old register CurrReg to
968  // refer to the new register NewReg.
969  for (const auto &Q : make_range(RegRefs.equal_range(CurrReg))) {
970  Q.second.Operand->setReg(NewReg);
971  // If the SU for the instruction being updated has debug
972  // information related to the anti-dependency register, make
973  // sure to update that as well.
974  const SUnit *SU = MISUnitMap[Q.second.Operand->getParent()];
975  if (!SU) continue;
976  UpdateDbgValues(DbgValues, Q.second.Operand->getParent(),
977  AntiDepReg, NewReg);
978  }
979 
980  // We just went back in time and modified history; the
981  // liveness information for CurrReg is now inconsistent. Set
982  // the state as if it were dead.
983  State->UnionGroups(NewReg, 0);
984  RegRefs.erase(NewReg);
985  DefIndices[NewReg] = DefIndices[CurrReg];
986  KillIndices[NewReg] = KillIndices[CurrReg];
987 
988  State->UnionGroups(CurrReg, 0);
989  RegRefs.erase(CurrReg);
990  DefIndices[CurrReg] = KillIndices[CurrReg];
991  KillIndices[CurrReg] = ~0u;
992  assert(((KillIndices[CurrReg] == ~0u) !=
993  (DefIndices[CurrReg] == ~0u)) &&
994  "Kill and Def maps aren't consistent for AntiDepReg!");
995  }
996 
997  ++Broken;
998  DEBUG(dbgs() << '\n');
999  }
1000  }
1001  }
1002 
1003  ScanInstruction(MI, Count);
1004  }
1005 
1006  return Broken;
1007 }
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not...
ArrayRef< MCPhysReg > getOrder(const TargetRegisterClass *RC) const
getOrder - Returns the preferred allocation order for RC.
Information about a register reference within a liverange.
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:458
bool isAllocatable(unsigned PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn&#39;t been...
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
MachineOperand * findRegisterDefOperand(unsigned Reg, bool isDead=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
bool hasExtraDefRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction def operands have special register allocation requirements that are ...
Definition: MachineInstr.h:746
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const
For a given register pair, return the sub-register index if the second register is a sub-register of ...
unsigned getDepth() const
Returns the depth of this node, which is the length of the maximum path up to any node which has no p...
Definition: ScheduleDAG.h:403
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
AggressiveAntiDepState(const unsigned TargetRegs, MachineBasicBlock *BB)
unsigned getReg() const
getReg - Returns the register number.
MachineOperand * findRegisterUseOperand(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:989
bool isInlineAsm() const
Definition: MachineInstr.h:832
bool test(unsigned Idx) const
Definition: BitVector.h:502
unsigned second
unsigned getReg() const
Returns the register associated with this edge.
Definition: ScheduleDAG.h:219
Kind
These are the different kinds of scheduling dependencies.
Definition: ScheduleDAG.h:53
SmallVector< SDep, 4 > Preds
All sunit predecessors.
Definition: ScheduleDAG.h:261
A register anti-dependence (aka WAR).
Definition: ScheduleDAG.h:55
void StartBlock(MachineBasicBlock *BB) override
Initialize anti-dep breaking for a new basic block.
bool isEarlyClobber() const
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
AggressiveAntiDepBreaker(MachineFunction &MFi, const RegisterClassInfo &RCI, TargetSubtargetInfo::RegClassVector &CriticalPathRCs)
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction. ...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
const HexagonInstrInfo * TII
This class works in conjunction with the post-RA scheduler to rename registers to break register anti...
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:293
SmallVectorImpl< SDep >::const_iterator const_pred_iterator
Definition: ScheduleDAG.h:266
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
Regular data dependence (aka true-dependence).
Definition: ScheduleDAG.h:54
bool isSubRegister(unsigned RegA, unsigned RegB) const
Returns true if RegB is a sub-register of RegA.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
ELFYAML::ELF_STO Other
Definition: ELFYAML.cpp:736
A register output-dependence (aka WAW).
Definition: ScheduleDAG.h:56
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:287
const RegList & Regs
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
void GetGroupRegs(unsigned Group, std::vector< unsigned > &Regs, std::multimap< unsigned, AggressiveAntiDepState::RegisterReference > *RegRefs)
unsigned UnionGroups(unsigned Reg1, unsigned Reg2)
SUnit * getSUnit() const
Definition: ScheduleDAG.h:490
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
const char * getName(unsigned RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register...
bool isSuperRegister(unsigned RegA, unsigned RegB) const
Returns true if RegB is a super-register of RegA.
Scheduling dependency.
Definition: ScheduleDAG.h:50
#define P(N)
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:406
std::vector< std::pair< MachineInstr *, MachineInstr * > > DbgValueVector
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
Definition: ScheduleDAG.h:378
unsigned BreakAntiDependencies(const std::vector< SUnit > &SUnits, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, unsigned InsertPosIndex, DbgValueVector &DbgValues) override
Identifiy anti-dependencies along the critical path of the ScheduleDAG and break them by renaming reg...
unsigned const MachineRegisterInfo * MRI
unsigned short Latency
Node latency.
Definition: ScheduleDAG.h:278
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineInstrBuilder & UseMI
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:36
bool any() const
any - Returns true if any bit is set.
Definition: BitVector.h:181
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
void FinishBlock() override
Finish anti-dep breaking for a basic block.
MCRegAliasIterator enumerates all registers aliasing Reg.
static const unsigned End
static const SUnit * CriticalPathStep(const SUnit *SU)
CriticalPathStep - Return the next SUnit after SU on the bottom-up critical path. ...
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:81
void Observe(MachineInstr &MI, unsigned Count, unsigned InsertPosIndex) override
Update liveness information to account for the current instruction, which will not be scheduled...
MCSubRegIterator enumerates all sub-registers of Reg.
virtual bool isPredicated(const MachineInstr &MI) const
Returns true if the instruction is already predicated.
unsigned first
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
bool isDebugValue() const
Definition: MachineInstr.h:816
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
std::vector< unsigned > & GetDefIndices()
Return the define indices.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
int findRegisterDefOperandIdx(unsigned Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found...
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:927
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
bool none() const
none - Returns true if none of the bits are set.
Definition: BitVector.h:202
Representation of each machine instruction.
Definition: MachineInstr.h:59
std::multimap< unsigned, RegisterReference > & GetRegRefs()
Return the RegRefs map.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
#define I(x, y, z)
Definition: MD5.cpp:58
bool hasExtraSrcRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction source operands have special register allocation requirements that a...
Definition: MachineInstr.h:736
Kind getKind() const
Returns an enum value representing the kind of the dependence.
Definition: ScheduleDAG.h:496
bool isKill() const
Definition: MachineInstr.h:830
bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx=nullptr) const
Given the index of a register def operand, check if the register def is tied to a source operand...
static cl::opt< int > DebugDiv("agg-antidep-debugdiv", cl::desc("Debug control for aggressive anti-dep breaker"), cl::init(0), cl::Hidden)
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void UpdateDbgValues(const DbgValueVector &DbgValues, MachineInstr *ParentMI, unsigned OldReg, unsigned NewReg)
Update all DBG_VALUE instructions that may be affected by the dependency breaker&#39;s update of ParentMI...
static void AntiDepEdges(const SUnit *SU, std::vector< const SDep *> &Edges)
AntiDepEdges - Return in Edges the anti- and output- dependencies in SU that we want to consider for ...
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:130
SmallVector< SDep, 4 > Succs
All sunit successors.
Definition: ScheduleDAG.h:262
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
#define DEBUG(X)
Definition: Debug.h:118
IRTranslator LLVM IR MI
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
Contains all the state necessary for anti-dep breaking.
static cl::opt< int > DebugMod("agg-antidep-debugmod", cl::desc("Debug control for aggressive anti-dep breaker"), cl::init(0), cl::Hidden)
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
bool IsLive(unsigned Reg)
Return true if Reg is live.
std::vector< unsigned > & GetKillIndices()
Return the kill indices.
std::vector< MachineBasicBlock * >::iterator succ_iterator
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:247
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:144
bool isImplicit() const