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PPCInstrInfo.cpp
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1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCInstrInfo.h"
16 #include "PPC.h"
17 #include "PPCHazardRecognizers.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCTargetMachine.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Statistic.h"
32 #include "llvm/CodeGen/StackMaps.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCInst.h"
36 #include "llvm/Support/Debug.h"
40 
41 using namespace llvm;
42 
43 #define DEBUG_TYPE "ppc-instr-info"
44 
45 #define GET_INSTRMAP_INFO
46 #define GET_INSTRINFO_CTOR_DTOR
47 #include "PPCGenInstrInfo.inc"
48 
49 static cl::
50 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
51  cl::desc("Disable analysis for CTR loops"));
52 
53 static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
54 cl::desc("Disable compare instruction optimization"), cl::Hidden);
55 
56 static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
57 cl::desc("Causes the backend to crash instead of generating a nop VSX copy"),
58 cl::Hidden);
59 
60 static cl::opt<bool>
61 UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
62  cl::desc("Use the old (incorrect) instruction latency calculation"));
63 
64 // Pin the vtable to this file.
65 void PPCInstrInfo::anchor() {}
66 
68  : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP,
69  /* CatchRetOpcode */ -1,
70  STI.isPPC64() ? PPC::BLR8 : PPC::BLR),
71  Subtarget(STI), RI(STI.getTargetMachine()) {}
72 
73 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
74 /// this target when scheduling the DAG.
77  const ScheduleDAG *DAG) const {
78  unsigned Directive =
79  static_cast<const PPCSubtarget *>(STI)->getDarwinDirective();
80  if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
81  Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
82  const InstrItineraryData *II =
83  static_cast<const PPCSubtarget *>(STI)->getInstrItineraryData();
84  return new ScoreboardHazardRecognizer(II, DAG);
85  }
86 
88 }
89 
90 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
91 /// to use for this target when scheduling the DAG.
94  const ScheduleDAG *DAG) const {
95  unsigned Directive =
96  DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
97 
98  // FIXME: Leaving this as-is until we have POWER9 scheduling info
99  if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8)
100  return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
101 
102  // Most subtargets use a PPC970 recognizer.
103  if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
104  Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
105  assert(DAG->TII && "No InstrInfo?");
106 
107  return new PPCHazardRecognizer970(*DAG);
108  }
109 
110  return new ScoreboardHazardRecognizer(II, DAG);
111 }
112 
114  const MachineInstr &MI,
115  unsigned *PredCost) const {
116  if (!ItinData || UseOldLatencyCalc)
117  return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
118 
119  // The default implementation of getInstrLatency calls getStageLatency, but
120  // getStageLatency does not do the right thing for us. While we have
121  // itinerary, most cores are fully pipelined, and so the itineraries only
122  // express the first part of the pipeline, not every stage. Instead, we need
123  // to use the listed output operand cycle number (using operand 0 here, which
124  // is an output).
125 
126  unsigned Latency = 1;
127  unsigned DefClass = MI.getDesc().getSchedClass();
128  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
129  const MachineOperand &MO = MI.getOperand(i);
130  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
131  continue;
132 
133  int Cycle = ItinData->getOperandCycle(DefClass, i);
134  if (Cycle < 0)
135  continue;
136 
137  Latency = std::max(Latency, (unsigned) Cycle);
138  }
139 
140  return Latency;
141 }
142 
144  const MachineInstr &DefMI, unsigned DefIdx,
145  const MachineInstr &UseMI,
146  unsigned UseIdx) const {
147  int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
148  UseMI, UseIdx);
149 
150  if (!DefMI.getParent())
151  return Latency;
152 
153  const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
154  unsigned Reg = DefMO.getReg();
155 
156  bool IsRegCR;
158  const MachineRegisterInfo *MRI =
159  &DefMI.getParent()->getParent()->getRegInfo();
160  IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
161  MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
162  } else {
163  IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
164  PPC::CRBITRCRegClass.contains(Reg);
165  }
166 
167  if (UseMI.isBranch() && IsRegCR) {
168  if (Latency < 0)
169  Latency = getInstrLatency(ItinData, DefMI);
170 
171  // On some cores, there is an additional delay between writing to a condition
172  // register, and using it from a branch.
173  unsigned Directive = Subtarget.getDarwinDirective();
174  switch (Directive) {
175  default: break;
176  case PPC::DIR_7400:
177  case PPC::DIR_750:
178  case PPC::DIR_970:
179  case PPC::DIR_E5500:
180  case PPC::DIR_PWR4:
181  case PPC::DIR_PWR5:
182  case PPC::DIR_PWR5X:
183  case PPC::DIR_PWR6:
184  case PPC::DIR_PWR6X:
185  case PPC::DIR_PWR7:
186  case PPC::DIR_PWR8:
187  // FIXME: Is this needed for POWER9?
188  Latency += 2;
189  break;
190  }
191  }
192 
193  return Latency;
194 }
195 
196 // This function does not list all associative and commutative operations, but
197 // only those worth feeding through the machine combiner in an attempt to
198 // reduce the critical path. Mostly, this means floating-point operations,
199 // because they have high latencies (compared to other operations, such and
200 // and/or, which are also associative and commutative, but have low latencies).
202  switch (Inst.getOpcode()) {
203  // FP Add:
204  case PPC::FADD:
205  case PPC::FADDS:
206  // FP Multiply:
207  case PPC::FMUL:
208  case PPC::FMULS:
209  // Altivec Add:
210  case PPC::VADDFP:
211  // VSX Add:
212  case PPC::XSADDDP:
213  case PPC::XVADDDP:
214  case PPC::XVADDSP:
215  case PPC::XSADDSP:
216  // VSX Multiply:
217  case PPC::XSMULDP:
218  case PPC::XVMULDP:
219  case PPC::XVMULSP:
220  case PPC::XSMULSP:
221  // QPX Add:
222  case PPC::QVFADD:
223  case PPC::QVFADDS:
224  case PPC::QVFADDSs:
225  // QPX Multiply:
226  case PPC::QVFMUL:
227  case PPC::QVFMULS:
228  case PPC::QVFMULSs:
229  return true;
230  default:
231  return false;
232  }
233 }
234 
236  MachineInstr &Root,
237  SmallVectorImpl<MachineCombinerPattern> &Patterns) const {
238  // Using the machine combiner in this way is potentially expensive, so
239  // restrict to when aggressive optimizations are desired.
241  return false;
242 
243  // FP reassociation is only legal when we don't need strict IEEE semantics.
245  return false;
246 
247  return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns);
248 }
249 
250 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
252  unsigned &SrcReg, unsigned &DstReg,
253  unsigned &SubIdx) const {
254  switch (MI.getOpcode()) {
255  default: return false;
256  case PPC::EXTSW:
257  case PPC::EXTSW_32_64:
258  SrcReg = MI.getOperand(1).getReg();
259  DstReg = MI.getOperand(0).getReg();
260  SubIdx = PPC::sub_32;
261  return true;
262  }
263 }
264 
266  int &FrameIndex) const {
267  // Note: This list must be kept consistent with LoadRegFromStackSlot.
268  switch (MI.getOpcode()) {
269  default: break;
270  case PPC::LD:
271  case PPC::LWZ:
272  case PPC::LFS:
273  case PPC::LFD:
274  case PPC::RESTORE_CR:
275  case PPC::RESTORE_CRBIT:
276  case PPC::LVX:
277  case PPC::LXVD2X:
278  case PPC::LXVX:
279  case PPC::QVLFDX:
280  case PPC::QVLFSXs:
281  case PPC::QVLFDXb:
282  case PPC::RESTORE_VRSAVE:
283  // Check for the operands added by addFrameReference (the immediate is the
284  // offset which defaults to 0).
285  if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
286  MI.getOperand(2).isFI()) {
287  FrameIndex = MI.getOperand(2).getIndex();
288  return MI.getOperand(0).getReg();
289  }
290  break;
291  }
292  return 0;
293 }
294 
295 // For opcodes with the ReMaterializable flag set, this function is called to
296 // verify the instruction is really rematable.
298  AliasAnalysis *AA) const {
299  switch (MI.getOpcode()) {
300  default:
301  // This function should only be called for opcodes with the ReMaterializable
302  // flag set.
303  llvm_unreachable("Unknown rematerializable operation!");
304  break;
305  case PPC::LI:
306  case PPC::LI8:
307  case PPC::LIS:
308  case PPC::LIS8:
309  case PPC::QVGPCI:
310  case PPC::ADDIStocHA:
311  case PPC::ADDItocL:
312  case PPC::LOAD_STACK_GUARD:
313  return true;
314  }
315  return false;
316 }
317 
319  int &FrameIndex) const {
320  // Note: This list must be kept consistent with StoreRegToStackSlot.
321  switch (MI.getOpcode()) {
322  default: break;
323  case PPC::STD:
324  case PPC::STW:
325  case PPC::STFS:
326  case PPC::STFD:
327  case PPC::SPILL_CR:
328  case PPC::SPILL_CRBIT:
329  case PPC::STVX:
330  case PPC::STXVD2X:
331  case PPC::STXVX:
332  case PPC::QVSTFDX:
333  case PPC::QVSTFSXs:
334  case PPC::QVSTFDXb:
335  case PPC::SPILL_VRSAVE:
336  // Check for the operands added by addFrameReference (the immediate is the
337  // offset which defaults to 0).
338  if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
339  MI.getOperand(2).isFI()) {
340  FrameIndex = MI.getOperand(2).getIndex();
341  return MI.getOperand(0).getReg();
342  }
343  break;
344  }
345  return 0;
346 }
347 
349  unsigned OpIdx1,
350  unsigned OpIdx2) const {
351  MachineFunction &MF = *MI.getParent()->getParent();
352 
353  // Normal instructions can be commuted the obvious way.
354  if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMIo)
355  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
356  // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
357  // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
358  // changing the relative order of the mask operands might change what happens
359  // to the high-bits of the mask (and, thus, the result).
360 
361  // Cannot commute if it has a non-zero rotate count.
362  if (MI.getOperand(3).getImm() != 0)
363  return nullptr;
364 
365  // If we have a zero rotate count, we have:
366  // M = mask(MB,ME)
367  // Op0 = (Op1 & ~M) | (Op2 & M)
368  // Change this to:
369  // M = mask((ME+1)&31, (MB-1)&31)
370  // Op0 = (Op2 & ~M) | (Op1 & M)
371 
372  // Swap op1/op2
373  assert(((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) &&
374  "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo.");
375  unsigned Reg0 = MI.getOperand(0).getReg();
376  unsigned Reg1 = MI.getOperand(1).getReg();
377  unsigned Reg2 = MI.getOperand(2).getReg();
378  unsigned SubReg1 = MI.getOperand(1).getSubReg();
379  unsigned SubReg2 = MI.getOperand(2).getSubReg();
380  bool Reg1IsKill = MI.getOperand(1).isKill();
381  bool Reg2IsKill = MI.getOperand(2).isKill();
382  bool ChangeReg0 = false;
383  // If machine instrs are no longer in two-address forms, update
384  // destination register as well.
385  if (Reg0 == Reg1) {
386  // Must be two address instruction!
388  "Expecting a two-address instruction!");
389  assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
390  Reg2IsKill = false;
391  ChangeReg0 = true;
392  }
393 
394  // Masks.
395  unsigned MB = MI.getOperand(4).getImm();
396  unsigned ME = MI.getOperand(5).getImm();
397 
398  // We can't commute a trivial mask (there is no way to represent an all-zero
399  // mask).
400  if (MB == 0 && ME == 31)
401  return nullptr;
402 
403  if (NewMI) {
404  // Create a new instruction.
405  unsigned Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg();
406  bool Reg0IsDead = MI.getOperand(0).isDead();
407  return BuildMI(MF, MI.getDebugLoc(), MI.getDesc())
408  .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
409  .addReg(Reg2, getKillRegState(Reg2IsKill))
410  .addReg(Reg1, getKillRegState(Reg1IsKill))
411  .addImm((ME + 1) & 31)
412  .addImm((MB - 1) & 31);
413  }
414 
415  if (ChangeReg0) {
416  MI.getOperand(0).setReg(Reg2);
417  MI.getOperand(0).setSubReg(SubReg2);
418  }
419  MI.getOperand(2).setReg(Reg1);
420  MI.getOperand(1).setReg(Reg2);
421  MI.getOperand(2).setSubReg(SubReg1);
422  MI.getOperand(1).setSubReg(SubReg2);
423  MI.getOperand(2).setIsKill(Reg1IsKill);
424  MI.getOperand(1).setIsKill(Reg2IsKill);
425 
426  // Swap the mask around.
427  MI.getOperand(4).setImm((ME + 1) & 31);
428  MI.getOperand(5).setImm((MB - 1) & 31);
429  return &MI;
430 }
431 
433  unsigned &SrcOpIdx2) const {
434  // For VSX A-Type FMA instructions, it is the first two operands that can be
435  // commuted, however, because the non-encoded tied input operand is listed
436  // first, the operands to swap are actually the second and third.
437 
438  int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode());
439  if (AltOpc == -1)
440  return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
441 
442  // The commutable operand indices are 2 and 3. Return them in SrcOpIdx1
443  // and SrcOpIdx2.
444  return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
445 }
446 
449  // This function is used for scheduling, and the nop wanted here is the type
450  // that terminates dispatch groups on the POWER cores.
451  unsigned Directive = Subtarget.getDarwinDirective();
452  unsigned Opcode;
453  switch (Directive) {
454  default: Opcode = PPC::NOP; break;
455  case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
456  case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
457  case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */
458  // FIXME: Update when POWER9 scheduling model is ready.
459  case PPC::DIR_PWR9: Opcode = PPC::NOP_GT_PWR7; break;
460  }
461 
462  DebugLoc DL;
463  BuildMI(MBB, MI, DL, get(Opcode));
464 }
465 
466 /// Return the noop instruction to use for a noop.
467 void PPCInstrInfo::getNoop(MCInst &NopInst) const {
468  NopInst.setOpcode(PPC::NOP);
469 }
470 
471 // Branch analysis.
472 // Note: If the condition register is set to CTR or CTR8 then this is a
473 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
475  MachineBasicBlock *&TBB,
476  MachineBasicBlock *&FBB,
478  bool AllowModify) const {
479  bool isPPC64 = Subtarget.isPPC64();
480 
481  // If the block has no terminators, it just falls into the block after it.
483  if (I == MBB.end())
484  return false;
485 
486  if (!isUnpredicatedTerminator(*I))
487  return false;
488 
489  // Get the last instruction in the block.
490  MachineInstr &LastInst = *I;
491 
492  // If there is only one terminator instruction, process it.
493  if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
494  if (LastInst.getOpcode() == PPC::B) {
495  if (!LastInst.getOperand(0).isMBB())
496  return true;
497  TBB = LastInst.getOperand(0).getMBB();
498  return false;
499  } else if (LastInst.getOpcode() == PPC::BCC) {
500  if (!LastInst.getOperand(2).isMBB())
501  return true;
502  // Block ends with fall-through condbranch.
503  TBB = LastInst.getOperand(2).getMBB();
504  Cond.push_back(LastInst.getOperand(0));
505  Cond.push_back(LastInst.getOperand(1));
506  return false;
507  } else if (LastInst.getOpcode() == PPC::BC) {
508  if (!LastInst.getOperand(1).isMBB())
509  return true;
510  // Block ends with fall-through condbranch.
511  TBB = LastInst.getOperand(1).getMBB();
513  Cond.push_back(LastInst.getOperand(0));
514  return false;
515  } else if (LastInst.getOpcode() == PPC::BCn) {
516  if (!LastInst.getOperand(1).isMBB())
517  return true;
518  // Block ends with fall-through condbranch.
519  TBB = LastInst.getOperand(1).getMBB();
521  Cond.push_back(LastInst.getOperand(0));
522  return false;
523  } else if (LastInst.getOpcode() == PPC::BDNZ8 ||
524  LastInst.getOpcode() == PPC::BDNZ) {
525  if (!LastInst.getOperand(0).isMBB())
526  return true;
527  if (DisableCTRLoopAnal)
528  return true;
529  TBB = LastInst.getOperand(0).getMBB();
531  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
532  true));
533  return false;
534  } else if (LastInst.getOpcode() == PPC::BDZ8 ||
535  LastInst.getOpcode() == PPC::BDZ) {
536  if (!LastInst.getOperand(0).isMBB())
537  return true;
538  if (DisableCTRLoopAnal)
539  return true;
540  TBB = LastInst.getOperand(0).getMBB();
542  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
543  true));
544  return false;
545  }
546 
547  // Otherwise, don't know what this is.
548  return true;
549  }
550 
551  // Get the instruction before it if it's a terminator.
552  MachineInstr &SecondLastInst = *I;
553 
554  // If there are three terminators, we don't know what sort of block this is.
555  if (I != MBB.begin() && isUnpredicatedTerminator(*--I))
556  return true;
557 
558  // If the block ends with PPC::B and PPC:BCC, handle it.
559  if (SecondLastInst.getOpcode() == PPC::BCC &&
560  LastInst.getOpcode() == PPC::B) {
561  if (!SecondLastInst.getOperand(2).isMBB() ||
562  !LastInst.getOperand(0).isMBB())
563  return true;
564  TBB = SecondLastInst.getOperand(2).getMBB();
565  Cond.push_back(SecondLastInst.getOperand(0));
566  Cond.push_back(SecondLastInst.getOperand(1));
567  FBB = LastInst.getOperand(0).getMBB();
568  return false;
569  } else if (SecondLastInst.getOpcode() == PPC::BC &&
570  LastInst.getOpcode() == PPC::B) {
571  if (!SecondLastInst.getOperand(1).isMBB() ||
572  !LastInst.getOperand(0).isMBB())
573  return true;
574  TBB = SecondLastInst.getOperand(1).getMBB();
576  Cond.push_back(SecondLastInst.getOperand(0));
577  FBB = LastInst.getOperand(0).getMBB();
578  return false;
579  } else if (SecondLastInst.getOpcode() == PPC::BCn &&
580  LastInst.getOpcode() == PPC::B) {
581  if (!SecondLastInst.getOperand(1).isMBB() ||
582  !LastInst.getOperand(0).isMBB())
583  return true;
584  TBB = SecondLastInst.getOperand(1).getMBB();
586  Cond.push_back(SecondLastInst.getOperand(0));
587  FBB = LastInst.getOperand(0).getMBB();
588  return false;
589  } else if ((SecondLastInst.getOpcode() == PPC::BDNZ8 ||
590  SecondLastInst.getOpcode() == PPC::BDNZ) &&
591  LastInst.getOpcode() == PPC::B) {
592  if (!SecondLastInst.getOperand(0).isMBB() ||
593  !LastInst.getOperand(0).isMBB())
594  return true;
595  if (DisableCTRLoopAnal)
596  return true;
597  TBB = SecondLastInst.getOperand(0).getMBB();
599  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
600  true));
601  FBB = LastInst.getOperand(0).getMBB();
602  return false;
603  } else if ((SecondLastInst.getOpcode() == PPC::BDZ8 ||
604  SecondLastInst.getOpcode() == PPC::BDZ) &&
605  LastInst.getOpcode() == PPC::B) {
606  if (!SecondLastInst.getOperand(0).isMBB() ||
607  !LastInst.getOperand(0).isMBB())
608  return true;
609  if (DisableCTRLoopAnal)
610  return true;
611  TBB = SecondLastInst.getOperand(0).getMBB();
613  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
614  true));
615  FBB = LastInst.getOperand(0).getMBB();
616  return false;
617  }
618 
619  // If the block ends with two PPC:Bs, handle it. The second one is not
620  // executed, so remove it.
621  if (SecondLastInst.getOpcode() == PPC::B && LastInst.getOpcode() == PPC::B) {
622  if (!SecondLastInst.getOperand(0).isMBB())
623  return true;
624  TBB = SecondLastInst.getOperand(0).getMBB();
625  I = LastInst;
626  if (AllowModify)
627  I->eraseFromParent();
628  return false;
629  }
630 
631  // Otherwise, can't handle this.
632  return true;
633 }
634 
636  int *BytesRemoved) const {
637  assert(!BytesRemoved && "code size not handled");
638 
640  if (I == MBB.end())
641  return 0;
642 
643  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
644  I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
645  I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
646  I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
647  return 0;
648 
649  // Remove the branch.
650  I->eraseFromParent();
651 
652  I = MBB.end();
653 
654  if (I == MBB.begin()) return 1;
655  --I;
656  if (I->getOpcode() != PPC::BCC &&
657  I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
658  I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
659  I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
660  return 1;
661 
662  // Remove the branch.
663  I->eraseFromParent();
664  return 2;
665 }
666 
668  MachineBasicBlock *TBB,
669  MachineBasicBlock *FBB,
671  const DebugLoc &DL,
672  int *BytesAdded) const {
673  // Shouldn't be a fall through.
674  assert(TBB && "insertBranch must not be told to insert a fallthrough");
675  assert((Cond.size() == 2 || Cond.size() == 0) &&
676  "PPC branch conditions have two components!");
677  assert(!BytesAdded && "code size not handled");
678 
679  bool isPPC64 = Subtarget.isPPC64();
680 
681  // One-way branch.
682  if (!FBB) {
683  if (Cond.empty()) // Unconditional branch
684  BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
685  else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
686  BuildMI(&MBB, DL, get(Cond[0].getImm() ?
687  (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
688  (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
689  else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
690  BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
691  else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
692  BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
693  else // Conditional branch
694  BuildMI(&MBB, DL, get(PPC::BCC))
695  .addImm(Cond[0].getImm())
696  .add(Cond[1])
697  .addMBB(TBB);
698  return 1;
699  }
700 
701  // Two-way Conditional Branch.
702  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
703  BuildMI(&MBB, DL, get(Cond[0].getImm() ?
704  (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
705  (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
706  else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
707  BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
708  else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
709  BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
710  else
711  BuildMI(&MBB, DL, get(PPC::BCC))
712  .addImm(Cond[0].getImm())
713  .add(Cond[1])
714  .addMBB(TBB);
715  BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
716  return 2;
717 }
718 
719 // Select analysis.
722  unsigned TrueReg, unsigned FalseReg,
723  int &CondCycles, int &TrueCycles, int &FalseCycles) const {
724  if (Cond.size() != 2)
725  return false;
726 
727  // If this is really a bdnz-like condition, then it cannot be turned into a
728  // select.
729  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
730  return false;
731 
732  // Check register classes.
733  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
734  const TargetRegisterClass *RC =
735  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
736  if (!RC)
737  return false;
738 
739  // isel is for regular integer GPRs only.
740  if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
741  !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
742  !PPC::G8RCRegClass.hasSubClassEq(RC) &&
743  !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
744  return false;
745 
746  // FIXME: These numbers are for the A2, how well they work for other cores is
747  // an open question. On the A2, the isel instruction has a 2-cycle latency
748  // but single-cycle throughput. These numbers are used in combination with
749  // the MispredictPenalty setting from the active SchedMachineModel.
750  CondCycles = 1;
751  TrueCycles = 1;
752  FalseCycles = 1;
753 
754  return true;
755 }
756 
759  const DebugLoc &dl, unsigned DestReg,
760  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
761  unsigned FalseReg) const {
762  assert(Cond.size() == 2 &&
763  "PPC branch conditions have two components!");
764 
765  // Get the register classes.
767  const TargetRegisterClass *RC =
768  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
769  assert(RC && "TrueReg and FalseReg must have overlapping register classes");
770 
771  bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
772  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
773  assert((Is64Bit ||
774  PPC::GPRCRegClass.hasSubClassEq(RC) ||
775  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
776  "isel is for regular integer GPRs only");
777 
778  unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
779  auto SelectPred = static_cast<PPC::Predicate>(Cond[0].getImm());
780 
781  unsigned SubIdx = 0;
782  bool SwapOps = false;
783  switch (SelectPred) {
784  case PPC::PRED_EQ:
785  case PPC::PRED_EQ_MINUS:
786  case PPC::PRED_EQ_PLUS:
787  SubIdx = PPC::sub_eq; SwapOps = false; break;
788  case PPC::PRED_NE:
789  case PPC::PRED_NE_MINUS:
790  case PPC::PRED_NE_PLUS:
791  SubIdx = PPC::sub_eq; SwapOps = true; break;
792  case PPC::PRED_LT:
793  case PPC::PRED_LT_MINUS:
794  case PPC::PRED_LT_PLUS:
795  SubIdx = PPC::sub_lt; SwapOps = false; break;
796  case PPC::PRED_GE:
797  case PPC::PRED_GE_MINUS:
798  case PPC::PRED_GE_PLUS:
799  SubIdx = PPC::sub_lt; SwapOps = true; break;
800  case PPC::PRED_GT:
801  case PPC::PRED_GT_MINUS:
802  case PPC::PRED_GT_PLUS:
803  SubIdx = PPC::sub_gt; SwapOps = false; break;
804  case PPC::PRED_LE:
805  case PPC::PRED_LE_MINUS:
806  case PPC::PRED_LE_PLUS:
807  SubIdx = PPC::sub_gt; SwapOps = true; break;
808  case PPC::PRED_UN:
809  case PPC::PRED_UN_MINUS:
810  case PPC::PRED_UN_PLUS:
811  SubIdx = PPC::sub_un; SwapOps = false; break;
812  case PPC::PRED_NU:
813  case PPC::PRED_NU_MINUS:
814  case PPC::PRED_NU_PLUS:
815  SubIdx = PPC::sub_un; SwapOps = true; break;
816  case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break;
817  case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break;
818  }
819 
820  unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
821  SecondReg = SwapOps ? TrueReg : FalseReg;
822 
823  // The first input register of isel cannot be r0. If it is a member
824  // of a register class that can be r0, then copy it first (the
825  // register allocator should eliminate the copy).
826  if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
827  MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
828  const TargetRegisterClass *FirstRC =
829  MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
830  &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
831  unsigned OldFirstReg = FirstReg;
832  FirstReg = MRI.createVirtualRegister(FirstRC);
833  BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
834  .addReg(OldFirstReg);
835  }
836 
837  BuildMI(MBB, MI, dl, get(OpCode), DestReg)
838  .addReg(FirstReg).addReg(SecondReg)
839  .addReg(Cond[1].getReg(), 0, SubIdx);
840 }
841 
842 static unsigned getCRBitValue(unsigned CRBit) {
843  unsigned Ret = 4;
844  if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT ||
845  CRBit == PPC::CR2LT || CRBit == PPC::CR3LT ||
846  CRBit == PPC::CR4LT || CRBit == PPC::CR5LT ||
847  CRBit == PPC::CR6LT || CRBit == PPC::CR7LT)
848  Ret = 3;
849  if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT ||
850  CRBit == PPC::CR2GT || CRBit == PPC::CR3GT ||
851  CRBit == PPC::CR4GT || CRBit == PPC::CR5GT ||
852  CRBit == PPC::CR6GT || CRBit == PPC::CR7GT)
853  Ret = 2;
854  if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ ||
855  CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ ||
856  CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ ||
857  CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ)
858  Ret = 1;
859  if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN ||
860  CRBit == PPC::CR2UN || CRBit == PPC::CR3UN ||
861  CRBit == PPC::CR4UN || CRBit == PPC::CR5UN ||
862  CRBit == PPC::CR6UN || CRBit == PPC::CR7UN)
863  Ret = 0;
864 
865  assert(Ret != 4 && "Invalid CR bit register");
866  return Ret;
867 }
868 
871  const DebugLoc &DL, unsigned DestReg,
872  unsigned SrcReg, bool KillSrc) const {
873  // We can end up with self copies and similar things as a result of VSX copy
874  // legalization. Promote them here.
875  const TargetRegisterInfo *TRI = &getRegisterInfo();
876  if (PPC::F8RCRegClass.contains(DestReg) &&
877  PPC::VSRCRegClass.contains(SrcReg)) {
878  unsigned SuperReg =
879  TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
880 
881  if (VSXSelfCopyCrash && SrcReg == SuperReg)
882  llvm_unreachable("nop VSX copy");
883 
884  DestReg = SuperReg;
885  } else if (PPC::F8RCRegClass.contains(SrcReg) &&
886  PPC::VSRCRegClass.contains(DestReg)) {
887  unsigned SuperReg =
888  TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
889 
890  if (VSXSelfCopyCrash && DestReg == SuperReg)
891  llvm_unreachable("nop VSX copy");
892 
893  SrcReg = SuperReg;
894  }
895 
896  // Different class register copy
897  if (PPC::CRBITRCRegClass.contains(SrcReg) &&
898  PPC::GPRCRegClass.contains(DestReg)) {
899  unsigned CRReg = getCRFromCRBit(SrcReg);
900  BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg);
901  getKillRegState(KillSrc);
902  // Rotate the CR bit in the CR fields to be the least significant bit and
903  // then mask with 0x1 (MB = ME = 31).
904  BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
905  .addReg(DestReg, RegState::Kill)
906  .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
907  .addImm(31)
908  .addImm(31);
909  return;
910  } else if (PPC::CRRCRegClass.contains(SrcReg) &&
911  PPC::G8RCRegClass.contains(DestReg)) {
912  BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg).addReg(SrcReg);
913  getKillRegState(KillSrc);
914  return;
915  } else if (PPC::CRRCRegClass.contains(SrcReg) &&
916  PPC::GPRCRegClass.contains(DestReg)) {
917  BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(SrcReg);
918  getKillRegState(KillSrc);
919  return;
920  }
921 
922  unsigned Opc;
923  if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
924  Opc = PPC::OR;
925  else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
926  Opc = PPC::OR8;
927  else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
928  Opc = PPC::FMR;
929  else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
930  Opc = PPC::MCRF;
931  else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
932  Opc = PPC::VOR;
933  else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
934  // There are two different ways this can be done:
935  // 1. xxlor : This has lower latency (on the P7), 2 cycles, but can only
936  // issue in VSU pipeline 0.
937  // 2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
938  // can go to either pipeline.
939  // We'll always use xxlor here, because in practically all cases where
940  // copies are generated, they are close enough to some use that the
941  // lower-latency form is preferable.
942  Opc = PPC::XXLOR;
943  else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) ||
944  PPC::VSSRCRegClass.contains(DestReg, SrcReg))
945  Opc = PPC::XXLORf;
946  else if (PPC::QFRCRegClass.contains(DestReg, SrcReg))
947  Opc = PPC::QVFMR;
948  else if (PPC::QSRCRegClass.contains(DestReg, SrcReg))
949  Opc = PPC::QVFMRs;
950  else if (PPC::QBRCRegClass.contains(DestReg, SrcReg))
951  Opc = PPC::QVFMRb;
952  else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
953  Opc = PPC::CROR;
954  else
955  llvm_unreachable("Impossible reg-to-reg copy");
956 
957  const MCInstrDesc &MCID = get(Opc);
958  if (MCID.getNumOperands() == 3)
959  BuildMI(MBB, I, DL, MCID, DestReg)
960  .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
961  else
962  BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
963 }
964 
965 // This function returns true if a CR spill is necessary and false otherwise.
966 bool
967 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
968  unsigned SrcReg, bool isKill,
969  int FrameIdx,
970  const TargetRegisterClass *RC,
972  bool &NonRI, bool &SpillsVRS) const{
973  // Note: If additional store instructions are added here,
974  // update isStoreToStackSlot.
975 
976  DebugLoc DL;
977  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
978  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
979  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
980  .addReg(SrcReg,
981  getKillRegState(isKill)),
982  FrameIdx));
983  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
984  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
985  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
986  .addReg(SrcReg,
987  getKillRegState(isKill)),
988  FrameIdx));
989  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
990  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
991  .addReg(SrcReg,
992  getKillRegState(isKill)),
993  FrameIdx));
994  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
995  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
996  .addReg(SrcReg,
997  getKillRegState(isKill)),
998  FrameIdx));
999  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1000  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
1001  .addReg(SrcReg,
1002  getKillRegState(isKill)),
1003  FrameIdx));
1004  return true;
1005  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1006  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CRBIT))
1007  .addReg(SrcReg,
1008  getKillRegState(isKill)),
1009  FrameIdx));
1010  return true;
1011  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1012  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX))
1013  .addReg(SrcReg,
1014  getKillRegState(isKill)),
1015  FrameIdx));
1016  NonRI = true;
1017  } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1018  unsigned Op = Subtarget.hasP9Vector() ? PPC::STXVX : PPC::STXVD2X;
1019  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Op))
1020  .addReg(SrcReg,
1021  getKillRegState(isKill)),
1022  FrameIdx));
1023  NonRI = true;
1024  } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1025  unsigned Opc = Subtarget.hasP9Vector() ? PPC::DFSTOREf64 : PPC::STXSDX;
1026  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opc))
1027  .addReg(SrcReg,
1028  getKillRegState(isKill)),
1029  FrameIdx));
1030  NonRI = true;
1031  } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1032  unsigned Opc = Subtarget.hasP9Vector() ? PPC::DFSTOREf32 : PPC::STXSSPX;
1033  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opc))
1034  .addReg(SrcReg,
1035  getKillRegState(isKill)),
1036  FrameIdx));
1037  NonRI = true;
1038  } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1039  assert(Subtarget.isDarwin() &&
1040  "VRSAVE only needs spill/restore on Darwin");
1041  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE))
1042  .addReg(SrcReg,
1043  getKillRegState(isKill)),
1044  FrameIdx));
1045  SpillsVRS = true;
1046  } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1047  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDX))
1048  .addReg(SrcReg,
1049  getKillRegState(isKill)),
1050  FrameIdx));
1051  NonRI = true;
1052  } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1053  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFSXs))
1054  .addReg(SrcReg,
1055  getKillRegState(isKill)),
1056  FrameIdx));
1057  NonRI = true;
1058  } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1059  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDXb))
1060  .addReg(SrcReg,
1061  getKillRegState(isKill)),
1062  FrameIdx));
1063  NonRI = true;
1064  } else {
1065  llvm_unreachable("Unknown regclass!");
1066  }
1067 
1068  return false;
1069 }
1070 
1071 void
1074  unsigned SrcReg, bool isKill, int FrameIdx,
1075  const TargetRegisterClass *RC,
1076  const TargetRegisterInfo *TRI) const {
1077  MachineFunction &MF = *MBB.getParent();
1079 
1080  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1081  FuncInfo->setHasSpills();
1082 
1083  // We need to avoid a situation in which the value from a VRRC register is
1084  // spilled using an Altivec instruction and reloaded into a VSRC register
1085  // using a VSX instruction. The issue with this is that the VSX
1086  // load/store instructions swap the doublewords in the vector and the Altivec
1087  // ones don't. The register classes on the spill/reload may be different if
1088  // the register is defined using an Altivec instruction and is then used by a
1089  // VSX instruction.
1090  RC = updatedRC(RC);
1091 
1092  bool NonRI = false, SpillsVRS = false;
1093  if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs,
1094  NonRI, SpillsVRS))
1095  FuncInfo->setSpillsCR();
1096 
1097  if (SpillsVRS)
1098  FuncInfo->setSpillsVRSAVE();
1099 
1100  if (NonRI)
1101  FuncInfo->setHasNonRISpills();
1102 
1103  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1104  MBB.insert(MI, NewMIs[i]);
1105 
1106  const MachineFrameInfo &MFI = MF.getFrameInfo();
1108  MachinePointerInfo::getFixedStack(MF, FrameIdx),
1110  MFI.getObjectAlignment(FrameIdx));
1111  NewMIs.back()->addMemOperand(MF, MMO);
1112 }
1113 
1114 bool PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
1115  unsigned DestReg, int FrameIdx,
1116  const TargetRegisterClass *RC,
1118  bool &NonRI, bool &SpillsVRS) const {
1119  // Note: If additional load instructions are added here,
1120  // update isLoadFromStackSlot.
1121 
1122  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1123  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1124  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
1125  DestReg), FrameIdx));
1126  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1127  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1128  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
1129  FrameIdx));
1130  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1131  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
1132  FrameIdx));
1133  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1134  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
1135  FrameIdx));
1136  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1137  NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1138  get(PPC::RESTORE_CR), DestReg),
1139  FrameIdx));
1140  return true;
1141  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1142  NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1143  get(PPC::RESTORE_CRBIT), DestReg),
1144  FrameIdx));
1145  return true;
1146  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1147  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LVX), DestReg),
1148  FrameIdx));
1149  NonRI = true;
1150  } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1151  unsigned Op = Subtarget.hasP9Vector() ? PPC::LXVX : PPC::LXVD2X;
1152  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Op), DestReg),
1153  FrameIdx));
1154  NonRI = true;
1155  } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1156  unsigned Opc = Subtarget.hasP9Vector() ? PPC::DFLOADf64 : PPC::LXSDX;
1157  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opc),
1158  DestReg), FrameIdx));
1159  NonRI = true;
1160  } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1161  unsigned Opc = Subtarget.hasP9Vector() ? PPC::DFLOADf32 : PPC::LXSSPX;
1162  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opc),
1163  DestReg), FrameIdx));
1164  NonRI = true;
1165  } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1166  assert(Subtarget.isDarwin() &&
1167  "VRSAVE only needs spill/restore on Darwin");
1168  NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1169  get(PPC::RESTORE_VRSAVE),
1170  DestReg),
1171  FrameIdx));
1172  SpillsVRS = true;
1173  } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1174  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFDX), DestReg),
1175  FrameIdx));
1176  NonRI = true;
1177  } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1178  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFSXs), DestReg),
1179  FrameIdx));
1180  NonRI = true;
1181  } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1182  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFDXb), DestReg),
1183  FrameIdx));
1184  NonRI = true;
1185  } else {
1186  llvm_unreachable("Unknown regclass!");
1187  }
1188 
1189  return false;
1190 }
1191 
1192 void
1195  unsigned DestReg, int FrameIdx,
1196  const TargetRegisterClass *RC,
1197  const TargetRegisterInfo *TRI) const {
1198  MachineFunction &MF = *MBB.getParent();
1200  DebugLoc DL;
1201  if (MI != MBB.end()) DL = MI->getDebugLoc();
1202 
1203  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1204  FuncInfo->setHasSpills();
1205 
1206  // We need to avoid a situation in which the value from a VRRC register is
1207  // spilled using an Altivec instruction and reloaded into a VSRC register
1208  // using a VSX instruction. The issue with this is that the VSX
1209  // load/store instructions swap the doublewords in the vector and the Altivec
1210  // ones don't. The register classes on the spill/reload may be different if
1211  // the register is defined using an Altivec instruction and is then used by a
1212  // VSX instruction.
1213  if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
1214  RC = &PPC::VSRCRegClass;
1215 
1216  bool NonRI = false, SpillsVRS = false;
1217  if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs,
1218  NonRI, SpillsVRS))
1219  FuncInfo->setSpillsCR();
1220 
1221  if (SpillsVRS)
1222  FuncInfo->setSpillsVRSAVE();
1223 
1224  if (NonRI)
1225  FuncInfo->setHasNonRISpills();
1226 
1227  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1228  MBB.insert(MI, NewMIs[i]);
1229 
1230  const MachineFrameInfo &MFI = MF.getFrameInfo();
1232  MachinePointerInfo::getFixedStack(MF, FrameIdx),
1234  MFI.getObjectAlignment(FrameIdx));
1235  NewMIs.back()->addMemOperand(MF, MMO);
1236 }
1237 
1238 bool PPCInstrInfo::
1240  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
1241  if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
1242  Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
1243  else
1244  // Leave the CR# the same, but invert the condition.
1245  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
1246  return false;
1247 }
1248 
1250  unsigned Reg, MachineRegisterInfo *MRI) const {
1251  // For some instructions, it is legal to fold ZERO into the RA register field.
1252  // A zero immediate should always be loaded with a single li.
1253  unsigned DefOpc = DefMI.getOpcode();
1254  if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
1255  return false;
1256  if (!DefMI.getOperand(1).isImm())
1257  return false;
1258  if (DefMI.getOperand(1).getImm() != 0)
1259  return false;
1260 
1261  // Note that we cannot here invert the arguments of an isel in order to fold
1262  // a ZERO into what is presented as the second argument. All we have here
1263  // is the condition bit, and that might come from a CR-logical bit operation.
1264 
1265  const MCInstrDesc &UseMCID = UseMI.getDesc();
1266 
1267  // Only fold into real machine instructions.
1268  if (UseMCID.isPseudo())
1269  return false;
1270 
1271  unsigned UseIdx;
1272  for (UseIdx = 0; UseIdx < UseMI.getNumOperands(); ++UseIdx)
1273  if (UseMI.getOperand(UseIdx).isReg() &&
1274  UseMI.getOperand(UseIdx).getReg() == Reg)
1275  break;
1276 
1277  assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI");
1278  assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
1279 
1280  const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
1281 
1282  // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
1283  // register (which might also be specified as a pointer class kind).
1284  if (UseInfo->isLookupPtrRegClass()) {
1285  if (UseInfo->RegClass /* Kind */ != 1)
1286  return false;
1287  } else {
1288  if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
1289  UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
1290  return false;
1291  }
1292 
1293  // Make sure this is not tied to an output register (or otherwise
1294  // constrained). This is true for ST?UX registers, for example, which
1295  // are tied to their output registers.
1296  if (UseInfo->Constraints != 0)
1297  return false;
1298 
1299  unsigned ZeroReg;
1300  if (UseInfo->isLookupPtrRegClass()) {
1301  bool isPPC64 = Subtarget.isPPC64();
1302  ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
1303  } else {
1304  ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
1305  PPC::ZERO8 : PPC::ZERO;
1306  }
1307 
1308  bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1309  UseMI.getOperand(UseIdx).setReg(ZeroReg);
1310 
1311  if (DeleteDef)
1312  DefMI.eraseFromParent();
1313 
1314  return true;
1315 }
1316 
1318  for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
1319  I != IE; ++I)
1320  if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
1321  return true;
1322  return false;
1323 }
1324 
1325 // We should make sure that, if we're going to predicate both sides of a
1326 // condition (a diamond), that both sides don't define the counter register. We
1327 // can predicate counter-decrement-based branches, but while that predicates
1328 // the branching, it does not predicate the counter decrement. If we tried to
1329 // merge the triangle into one predicated block, we'd decrement the counter
1330 // twice.
1332  unsigned NumT, unsigned ExtraT,
1333  MachineBasicBlock &FMBB,
1334  unsigned NumF, unsigned ExtraF,
1335  BranchProbability Probability) const {
1336  return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
1337 }
1338 
1339 
1341  // The predicated branches are identified by their type, not really by the
1342  // explicit presence of a predicate. Furthermore, some of them can be
1343  // predicated more than once. Because if conversion won't try to predicate
1344  // any instruction which already claims to be predicated (by returning true
1345  // here), always return false. In doing so, we let isPredicable() be the
1346  // final word on whether not the instruction can be (further) predicated.
1347 
1348  return false;
1349 }
1350 
1352  if (!MI.isTerminator())
1353  return false;
1354 
1355  // Conditional branch is a special case.
1356  if (MI.isBranch() && !MI.isBarrier())
1357  return true;
1358 
1359  return !isPredicated(MI);
1360 }
1361 
1363  ArrayRef<MachineOperand> Pred) const {
1364  unsigned OpC = MI.getOpcode();
1365  if (OpC == PPC::BLR || OpC == PPC::BLR8) {
1366  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1367  bool isPPC64 = Subtarget.isPPC64();
1368  MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR)
1369  : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
1370  } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1371  MI.setDesc(get(PPC::BCLR));
1373  .addReg(Pred[1].getReg());
1374  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1375  MI.setDesc(get(PPC::BCLRn));
1377  .addReg(Pred[1].getReg());
1378  } else {
1379  MI.setDesc(get(PPC::BCCLR));
1381  .addImm(Pred[0].getImm())
1382  .addReg(Pred[1].getReg());
1383  }
1384 
1385  return true;
1386  } else if (OpC == PPC::B) {
1387  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1388  bool isPPC64 = Subtarget.isPPC64();
1389  MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
1390  : (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
1391  } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1392  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1393  MI.RemoveOperand(0);
1394 
1395  MI.setDesc(get(PPC::BC));
1397  .addReg(Pred[1].getReg())
1398  .addMBB(MBB);
1399  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1400  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1401  MI.RemoveOperand(0);
1402 
1403  MI.setDesc(get(PPC::BCn));
1405  .addReg(Pred[1].getReg())
1406  .addMBB(MBB);
1407  } else {
1408  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1409  MI.RemoveOperand(0);
1410 
1411  MI.setDesc(get(PPC::BCC));
1413  .addImm(Pred[0].getImm())
1414  .addReg(Pred[1].getReg())
1415  .addMBB(MBB);
1416  }
1417 
1418  return true;
1419  } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 ||
1420  OpC == PPC::BCTRL || OpC == PPC::BCTRL8) {
1421  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
1422  llvm_unreachable("Cannot predicate bctr[l] on the ctr register");
1423 
1424  bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
1425  bool isPPC64 = Subtarget.isPPC64();
1426 
1427  if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1428  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8)
1429  : (setLR ? PPC::BCCTRL : PPC::BCCTR)));
1431  .addReg(Pred[1].getReg());
1432  return true;
1433  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1434  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n)
1435  : (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
1437  .addReg(Pred[1].getReg());
1438  return true;
1439  }
1440 
1441  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8)
1442  : (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
1444  .addImm(Pred[0].getImm())
1445  .addReg(Pred[1].getReg());
1446  return true;
1447  }
1448 
1449  return false;
1450 }
1451 
1453  ArrayRef<MachineOperand> Pred2) const {
1454  assert(Pred1.size() == 2 && "Invalid PPC first predicate");
1455  assert(Pred2.size() == 2 && "Invalid PPC second predicate");
1456 
1457  if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1458  return false;
1459  if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
1460  return false;
1461 
1462  // P1 can only subsume P2 if they test the same condition register.
1463  if (Pred1[1].getReg() != Pred2[1].getReg())
1464  return false;
1465 
1466  PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
1467  PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
1468 
1469  if (P1 == P2)
1470  return true;
1471 
1472  // Does P1 subsume P2, e.g. GE subsumes GT.
1473  if (P1 == PPC::PRED_LE &&
1474  (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
1475  return true;
1476  if (P1 == PPC::PRED_GE &&
1477  (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
1478  return true;
1479 
1480  return false;
1481 }
1482 
1484  std::vector<MachineOperand> &Pred) const {
1485  // Note: At the present time, the contents of Pred from this function is
1486  // unused by IfConversion. This implementation follows ARM by pushing the
1487  // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
1488  // predicate, instructions defining CTR or CTR8 are also included as
1489  // predicate-defining instructions.
1490 
1491  const TargetRegisterClass *RCs[] =
1492  { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1493  &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1494 
1495  bool Found = false;
1496  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1497  const MachineOperand &MO = MI.getOperand(i);
1498  for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
1499  const TargetRegisterClass *RC = RCs[c];
1500  if (MO.isReg()) {
1501  if (MO.isDef() && RC->contains(MO.getReg())) {
1502  Pred.push_back(MO);
1503  Found = true;
1504  }
1505  } else if (MO.isRegMask()) {
1506  for (TargetRegisterClass::iterator I = RC->begin(),
1507  IE = RC->end(); I != IE; ++I)
1508  if (MO.clobbersPhysReg(*I)) {
1509  Pred.push_back(MO);
1510  Found = true;
1511  }
1512  }
1513  }
1514  }
1515 
1516  return Found;
1517 }
1518 
1520  unsigned OpC = MI.getOpcode();
1521  switch (OpC) {
1522  default:
1523  return false;
1524  case PPC::B:
1525  case PPC::BLR:
1526  case PPC::BLR8:
1527  case PPC::BCTR:
1528  case PPC::BCTR8:
1529  case PPC::BCTRL:
1530  case PPC::BCTRL8:
1531  return true;
1532  }
1533 }
1534 
1535 bool PPCInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1536  unsigned &SrcReg2, int &Mask,
1537  int &Value) const {
1538  unsigned Opc = MI.getOpcode();
1539 
1540  switch (Opc) {
1541  default: return false;
1542  case PPC::CMPWI:
1543  case PPC::CMPLWI:
1544  case PPC::CMPDI:
1545  case PPC::CMPLDI:
1546  SrcReg = MI.getOperand(1).getReg();
1547  SrcReg2 = 0;
1548  Value = MI.getOperand(2).getImm();
1549  Mask = 0xFFFF;
1550  return true;
1551  case PPC::CMPW:
1552  case PPC::CMPLW:
1553  case PPC::CMPD:
1554  case PPC::CMPLD:
1555  case PPC::FCMPUS:
1556  case PPC::FCMPUD:
1557  SrcReg = MI.getOperand(1).getReg();
1558  SrcReg2 = MI.getOperand(2).getReg();
1559  Value = 0;
1560  Mask = 0;
1561  return true;
1562  }
1563 }
1564 
1565 bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1566  unsigned SrcReg2, int Mask, int Value,
1567  const MachineRegisterInfo *MRI) const {
1568  if (DisableCmpOpt)
1569  return false;
1570 
1571  int OpC = CmpInstr.getOpcode();
1572  unsigned CRReg = CmpInstr.getOperand(0).getReg();
1573 
1574  // FP record forms set CR1 based on the execption status bits, not a
1575  // comparison with zero.
1576  if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
1577  return false;
1578 
1579  // The record forms set the condition register based on a signed comparison
1580  // with zero (so says the ISA manual). This is not as straightforward as it
1581  // seems, however, because this is always a 64-bit comparison on PPC64, even
1582  // for instructions that are 32-bit in nature (like slw for example).
1583  // So, on PPC32, for unsigned comparisons, we can use the record forms only
1584  // for equality checks (as those don't depend on the sign). On PPC64,
1585  // we are restricted to equality for unsigned 64-bit comparisons and for
1586  // signed 32-bit comparisons the applicability is more restricted.
1587  bool isPPC64 = Subtarget.isPPC64();
1588  bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
1589  bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
1590  bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
1591 
1592  // Get the unique definition of SrcReg.
1593  MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1594  if (!MI) return false;
1595  int MIOpC = MI->getOpcode();
1596 
1597  bool equalityOnly = false;
1598  bool noSub = false;
1599  if (isPPC64) {
1600  if (is32BitSignedCompare) {
1601  // We can perform this optimization only if MI is sign-extending.
1602  if (MIOpC == PPC::SRAW || MIOpC == PPC::SRAWo ||
1603  MIOpC == PPC::SRAWI || MIOpC == PPC::SRAWIo ||
1604  MIOpC == PPC::EXTSB || MIOpC == PPC::EXTSBo ||
1605  MIOpC == PPC::EXTSH || MIOpC == PPC::EXTSHo ||
1606  MIOpC == PPC::EXTSW || MIOpC == PPC::EXTSWo) {
1607  noSub = true;
1608  } else
1609  return false;
1610  } else if (is32BitUnsignedCompare) {
1611  // 32-bit rotate and mask instructions are zero extending only if MB <= ME
1612  bool isZeroExtendingRotate =
1613  (MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINMo ||
1614  MIOpC == PPC::RLWNM || MIOpC == PPC::RLWNMo)
1615  && MI->getOperand(3).getImm() <= MI->getOperand(4).getImm();
1616 
1617  // We can perform this optimization, equality only, if MI is
1618  // zero-extending.
1619  // FIXME: Other possible target instructions include ANDISo and
1620  // RLWINM aliases, such as ROTRWI, EXTLWI, SLWI and SRWI.
1621  if (MIOpC == PPC::CNTLZW || MIOpC == PPC::CNTLZWo ||
1622  MIOpC == PPC::SLW || MIOpC == PPC::SLWo ||
1623  MIOpC == PPC::SRW || MIOpC == PPC::SRWo ||
1624  MIOpC == PPC::ANDIo ||
1625  isZeroExtendingRotate) {
1626  noSub = true;
1627  equalityOnly = true;
1628  } else
1629  return false;
1630  } else
1631  equalityOnly = is64BitUnsignedCompare;
1632  } else
1633  equalityOnly = is32BitUnsignedCompare;
1634 
1635  if (equalityOnly) {
1636  // We need to check the uses of the condition register in order to reject
1637  // non-equality comparisons.
1639  I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1640  I != IE; ++I) {
1641  MachineInstr *UseMI = &*I;
1642  if (UseMI->getOpcode() == PPC::BCC) {
1643  unsigned Pred = UseMI->getOperand(0).getImm();
1644  if (Pred != PPC::PRED_EQ && Pred != PPC::PRED_NE)
1645  return false;
1646  } else if (UseMI->getOpcode() == PPC::ISEL ||
1647  UseMI->getOpcode() == PPC::ISEL8) {
1648  unsigned SubIdx = UseMI->getOperand(3).getSubReg();
1649  if (SubIdx != PPC::sub_eq)
1650  return false;
1651  } else
1652  return false;
1653  }
1654  }
1655 
1656  MachineBasicBlock::iterator I = CmpInstr;
1657 
1658  // Scan forward to find the first use of the compare.
1659  for (MachineBasicBlock::iterator EL = CmpInstr.getParent()->end(); I != EL;
1660  ++I) {
1661  bool FoundUse = false;
1663  J = MRI->use_instr_begin(CRReg), JE = MRI->use_instr_end();
1664  J != JE; ++J)
1665  if (&*J == &*I) {
1666  FoundUse = true;
1667  break;
1668  }
1669 
1670  if (FoundUse)
1671  break;
1672  }
1673 
1676 
1677  // There are two possible candidates which can be changed to set CR[01].
1678  // One is MI, the other is a SUB instruction.
1679  // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
1680  MachineInstr *Sub = nullptr;
1681  if (SrcReg2 != 0)
1682  // MI is not a candidate for CMPrr.
1683  MI = nullptr;
1684  // FIXME: Conservatively refuse to convert an instruction which isn't in the
1685  // same BB as the comparison. This is to allow the check below to avoid calls
1686  // (and other explicit clobbers); instead we should really check for these
1687  // more explicitly (in at least a few predecessors).
1688  else if (MI->getParent() != CmpInstr.getParent())
1689  return false;
1690  else if (Value != 0) {
1691  // The record-form instructions set CR bit based on signed comparison against 0.
1692  // We try to convert a compare against 1 or -1 into a compare against 0.
1693  bool Success = false;
1694  if (!equalityOnly && MRI->hasOneUse(CRReg)) {
1695  MachineInstr *UseMI = &*MRI->use_instr_begin(CRReg);
1696  if (UseMI->getOpcode() == PPC::BCC) {
1697  PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
1698  int16_t Immed = (int16_t)Value;
1699 
1700  if (Immed == -1 && Pred == PPC::PRED_GT) {
1701  // We convert "greater than -1" into "greater than or equal to 0",
1702  // since we are assuming signed comparison by !equalityOnly
1703  PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1704  PPC::PRED_GE));
1705  Success = true;
1706  }
1707  else if (Immed == 1 && Pred == PPC::PRED_LT) {
1708  // We convert "less than 1" into "less than or equal to 0".
1709  PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1710  PPC::PRED_LE));
1711  Success = true;
1712  }
1713  }
1714  }
1715 
1716  // PPC does not have a record-form SUBri.
1717  if (!Success)
1718  return false;
1719  }
1720 
1721  // Search for Sub.
1722  const TargetRegisterInfo *TRI = &getRegisterInfo();
1723  --I;
1724 
1725  // Get ready to iterate backward from CmpInstr.
1726  MachineBasicBlock::iterator E = MI, B = CmpInstr.getParent()->begin();
1727 
1728  for (; I != E && !noSub; --I) {
1729  const MachineInstr &Instr = *I;
1730  unsigned IOpC = Instr.getOpcode();
1731 
1732  if (&*I != &CmpInstr && (Instr.modifiesRegister(PPC::CR0, TRI) ||
1733  Instr.readsRegister(PPC::CR0, TRI)))
1734  // This instruction modifies or uses the record condition register after
1735  // the one we want to change. While we could do this transformation, it
1736  // would likely not be profitable. This transformation removes one
1737  // instruction, and so even forcing RA to generate one move probably
1738  // makes it unprofitable.
1739  return false;
1740 
1741  // Check whether CmpInstr can be made redundant by the current instruction.
1742  if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
1743  OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
1744  (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
1745  ((Instr.getOperand(1).getReg() == SrcReg &&
1746  Instr.getOperand(2).getReg() == SrcReg2) ||
1747  (Instr.getOperand(1).getReg() == SrcReg2 &&
1748  Instr.getOperand(2).getReg() == SrcReg))) {
1749  Sub = &*I;
1750  break;
1751  }
1752 
1753  if (I == B)
1754  // The 'and' is below the comparison instruction.
1755  return false;
1756  }
1757 
1758  // Return false if no candidates exist.
1759  if (!MI && !Sub)
1760  return false;
1761 
1762  // The single candidate is called MI.
1763  if (!MI) MI = Sub;
1764 
1765  int NewOpC = -1;
1766  MIOpC = MI->getOpcode();
1767  if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8)
1768  NewOpC = MIOpC;
1769  else {
1770  NewOpC = PPC::getRecordFormOpcode(MIOpC);
1771  if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
1772  NewOpC = MIOpC;
1773  }
1774 
1775  // FIXME: On the non-embedded POWER architectures, only some of the record
1776  // forms are fast, and we should use only the fast ones.
1777 
1778  // The defining instruction has a record form (or is already a record
1779  // form). It is possible, however, that we'll need to reverse the condition
1780  // code of the users.
1781  if (NewOpC == -1)
1782  return false;
1783 
1784  // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
1785  // needs to be updated to be based on SUB. Push the condition code
1786  // operands to OperandsToUpdate. If it is safe to remove CmpInstr, the
1787  // condition code of these operands will be modified.
1788  // Here, Value == 0 means we haven't converted comparison against 1 or -1 to
1789  // comparison against 0, which may modify predicate.
1790  bool ShouldSwap = false;
1791  if (Sub && Value == 0) {
1792  ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1793  Sub->getOperand(2).getReg() == SrcReg;
1794 
1795  // The operands to subf are the opposite of sub, so only in the fixed-point
1796  // case, invert the order.
1797  ShouldSwap = !ShouldSwap;
1798  }
1799 
1800  if (ShouldSwap)
1802  I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1803  I != IE; ++I) {
1804  MachineInstr *UseMI = &*I;
1805  if (UseMI->getOpcode() == PPC::BCC) {
1806  PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
1807  assert((!equalityOnly ||
1808  Pred == PPC::PRED_EQ || Pred == PPC::PRED_NE) &&
1809  "Invalid predicate for equality-only optimization");
1810  PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1811  PPC::getSwappedPredicate(Pred)));
1812  } else if (UseMI->getOpcode() == PPC::ISEL ||
1813  UseMI->getOpcode() == PPC::ISEL8) {
1814  unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
1815  assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
1816  "Invalid CR bit for equality-only optimization");
1817 
1818  if (NewSubReg == PPC::sub_lt)
1819  NewSubReg = PPC::sub_gt;
1820  else if (NewSubReg == PPC::sub_gt)
1821  NewSubReg = PPC::sub_lt;
1822 
1823  SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)),
1824  NewSubReg));
1825  } else // We need to abort on a user we don't understand.
1826  return false;
1827  }
1828  assert(!(Value != 0 && ShouldSwap) &&
1829  "Non-zero immediate support and ShouldSwap"
1830  "may conflict in updating predicate");
1831 
1832  // Create a new virtual register to hold the value of the CR set by the
1833  // record-form instruction. If the instruction was not previously in
1834  // record form, then set the kill flag on the CR.
1835  CmpInstr.eraseFromParent();
1836 
1838  BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
1839  get(TargetOpcode::COPY), CRReg)
1840  .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
1841 
1842  // Even if CR0 register were dead before, it is alive now since the
1843  // instruction we just built uses it.
1844  MI->clearRegisterDeads(PPC::CR0);
1845 
1846  if (MIOpC != NewOpC) {
1847  // We need to be careful here: we're replacing one instruction with
1848  // another, and we need to make sure that we get all of the right
1849  // implicit uses and defs. On the other hand, the caller may be holding
1850  // an iterator to this instruction, and so we can't delete it (this is
1851  // specifically the case if this is the instruction directly after the
1852  // compare).
1853 
1854  const MCInstrDesc &NewDesc = get(NewOpC);
1855  MI->setDesc(NewDesc);
1856 
1857  if (NewDesc.ImplicitDefs)
1858  for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs();
1859  *ImpDefs; ++ImpDefs)
1860  if (!MI->definesRegister(*ImpDefs))
1861  MI->addOperand(*MI->getParent()->getParent(),
1862  MachineOperand::CreateReg(*ImpDefs, true, true));
1863  if (NewDesc.ImplicitUses)
1864  for (const MCPhysReg *ImpUses = NewDesc.getImplicitUses();
1865  *ImpUses; ++ImpUses)
1866  if (!MI->readsRegister(*ImpUses))
1867  MI->addOperand(*MI->getParent()->getParent(),
1868  MachineOperand::CreateReg(*ImpUses, false, true));
1869  }
1870  assert(MI->definesRegister(PPC::CR0) &&
1871  "Record-form instruction does not define cr0?");
1872 
1873  // Modify the condition code of operands in OperandsToUpdate.
1874  // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
1875  // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
1876  for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
1877  PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
1878 
1879  for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
1880  SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
1881 
1882  return true;
1883 }
1884 
1885 /// GetInstSize - Return the number of bytes of code the specified
1886 /// instruction may be. This returns the maximum number of bytes.
1887 ///
1889  unsigned Opcode = MI.getOpcode();
1890 
1891  if (Opcode == PPC::INLINEASM) {
1892  const MachineFunction *MF = MI.getParent()->getParent();
1893  const char *AsmStr = MI.getOperand(0).getSymbolName();
1894  return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1895  } else if (Opcode == TargetOpcode::STACKMAP) {
1896  StackMapOpers Opers(&MI);
1897  return Opers.getNumPatchBytes();
1898  } else if (Opcode == TargetOpcode::PATCHPOINT) {
1899  PatchPointOpers Opers(&MI);
1900  return Opers.getNumPatchBytes();
1901  } else {
1902  return get(Opcode).getSize();
1903  }
1904 }
1905 
1906 std::pair<unsigned, unsigned>
1908  const unsigned Mask = PPCII::MO_ACCESS_MASK;
1909  return std::make_pair(TF & Mask, TF & ~Mask);
1910 }
1911 
1914  using namespace PPCII;
1915  static const std::pair<unsigned, const char *> TargetFlags[] = {
1916  {MO_LO, "ppc-lo"},
1917  {MO_HA, "ppc-ha"},
1918  {MO_TPREL_LO, "ppc-tprel-lo"},
1919  {MO_TPREL_HA, "ppc-tprel-ha"},
1920  {MO_DTPREL_LO, "ppc-dtprel-lo"},
1921  {MO_TLSLD_LO, "ppc-tlsld-lo"},
1922  {MO_TOC_LO, "ppc-toc-lo"},
1923  {MO_TLS, "ppc-tls"}};
1924  return makeArrayRef(TargetFlags);
1925 }
1926 
1929  using namespace PPCII;
1930  static const std::pair<unsigned, const char *> TargetFlags[] = {
1931  {MO_PLT, "ppc-plt"},
1932  {MO_PIC_FLAG, "ppc-pic"},
1933  {MO_NLP_FLAG, "ppc-nlp"},
1934  {MO_NLP_HIDDEN_FLAG, "ppc-nlp-hidden"}};
1935  return makeArrayRef(TargetFlags);
1936 }
1937 
1939  auto &MBB = *MI.getParent();
1940  auto DL = MI.getDebugLoc();
1941  switch (MI.getOpcode()) {
1942  case TargetOpcode::LOAD_STACK_GUARD: {
1943  assert(Subtarget.isTargetLinux() &&
1944  "Only Linux target is expected to contain LOAD_STACK_GUARD");
1945  const int64_t Offset = Subtarget.isPPC64() ? -0x7010 : -0x7008;
1946  const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2;
1947  MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ));
1949  .addImm(Offset)
1950  .addReg(Reg);
1951  return true;
1952  }
1953  case PPC::DFLOADf32:
1954  case PPC::DFLOADf64:
1955  case PPC::DFSTOREf32:
1956  case PPC::DFSTOREf64: {
1957  assert(Subtarget.hasP9Vector() &&
1958  "Invalid D-Form Pseudo-ops on non-P9 target.");
1959  assert(MI.getOperand(2).isReg() && MI.getOperand(1).isImm() &&
1960  "D-form op must have register and immediate operands");
1961  unsigned UpperOpcode, LowerOpcode;
1962  switch (MI.getOpcode()) {
1963  case PPC::DFLOADf32:
1964  UpperOpcode = PPC::LXSSP;
1965  LowerOpcode = PPC::LFS;
1966  break;
1967  case PPC::DFLOADf64:
1968  UpperOpcode = PPC::LXSD;
1969  LowerOpcode = PPC::LFD;
1970  break;
1971  case PPC::DFSTOREf32:
1972  UpperOpcode = PPC::STXSSP;
1973  LowerOpcode = PPC::STFS;
1974  break;
1975  case PPC::DFSTOREf64:
1976  UpperOpcode = PPC::STXSD;
1977  LowerOpcode = PPC::STFD;
1978  break;
1979  }
1980  unsigned TargetReg = MI.getOperand(0).getReg();
1981  unsigned Opcode;
1982  if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) ||
1983  (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31))
1984  Opcode = LowerOpcode;
1985  else
1986  Opcode = UpperOpcode;
1987  MI.setDesc(get(Opcode));
1988  return true;
1989  }
1990  case PPC::CFENCE8: {
1991  auto Val = MI.getOperand(0).getReg();
1992  BuildMI(MBB, MI, DL, get(PPC::CMPD), PPC::CR7).addReg(Val).addReg(Val);
1993  BuildMI(MBB, MI, DL, get(PPC::CTRL_DEP))
1995  .addReg(PPC::CR7)
1996  .addImm(1);
1997  MI.setDesc(get(PPC::ISYNC));
1998  MI.RemoveOperand(0);
1999  return true;
2000  }
2001  }
2002  return false;
2003 }
2004 
2005 const TargetRegisterClass *
2007  if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
2008  return &PPC::VSRCRegClass;
2009  return RC;
2010 }
2011 
2013  return PPC::getRecordFormOpcode(Opcode);
2014 }
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
Definition: MachineInstr.h:927
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
int getNonRecordFormOpcode(uint16_t)
MachineBasicBlock * getMBB() const
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
iterator begin() const
begin/end - Return all of the registers in this class.
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:257
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:512
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
static int getRecordFormOpcode(unsigned Opcode)
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned getSubReg() const
bool hasVSX() const
Definition: PPCSubtarget.h:242
static cl::opt< bool > DisableCmpOpt("disable-ppc-cmp-opt", cl::desc("Disable compare instruction optimization"), cl::Hidden)
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
A debug info location.
Definition: DebugLoc.h:34
bool isPseudo() const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MCInstrDesc.h:242
CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
#define R2(n)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
return AArch64::GPR64RegClass contains(Reg)
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling th...
MachineFunction & MF
Machine function.
Definition: ScheduleDAG.h:570
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
PPCDispatchGroupSBHazardRecognizer - This class implements a scoreboard-based hazard recognizer for P...
A description of a memory reference used in the backend.
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:451
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:282
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
Reg
All possible values of the reg field in the ModR/M byte.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:445
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:279
const TargetRegisterClass * updatedRC(const TargetRegisterClass *RC) const
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const override
const char * getSymbolName() const
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:633
defusechain_iterator - This class provides iterator support for machine operands in the function that...
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
PPCInstrInfo(PPCSubtarget &STI)
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:276
CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based loops.
bool hasP9Vector() const
Definition: PPCSubtarget.h:246
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const override
MO_NLP_HIDDEN_FLAG - If this bit is set, the symbol reference is to a symbol with hidden visibility...
Definition: PPC.h:82
virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns) const
Return true when there is potentially a faster code sequence for an instruction chain ending in Root...
CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
Itinerary data supplied by a subtarget to be used by a target.
const PPCTargetMachine & getTargetMachine() const
Definition: PPCSubtarget.h:189
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:453
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:159
unsigned getKillRegState(bool B)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
unsigned getDeadRegState(bool B)
VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:565
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:534
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
unsigned const MachineRegisterInfo * MRI
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
int getAltVSXFMAOpcode(uint16_t Opcode)
Simple binary floating point operators.
Definition: ISDOpcodes.h:259
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void clearRegisterDeads(unsigned Reg)
Clear all dead flags on operands defining register Reg.
MachineInstrBuilder & UseMI
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
MO_NLP_FLAG - If this bit is set, the symbol reference is actually to the non_lazy_ptr for the global...
Definition: PPC.h:77
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:31
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:173
use_instr_iterator use_instr_begin(unsigned RegNo) const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
void setImm(int64_t immVal)
bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
Definition: MachineInstr.h:919
MI-level patchpoint operands.
Definition: StackMaps.h:77
PPCHazardRecognizer970 - This class defines a finite state automata that models the dispatch logic on...
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned getDarwinDirective() const
getDarwinDirective - Returns the -m directive specified for the cpu.
Definition: PPCSubtarget.h:168
static unsigned getCRFromCRBit(unsigned SrcReg)
MO_TLS - Indicates that the operand being accessed is some kind of thread-local symbol.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
unsigned first
void setIsKill(bool Val=true)
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
The next are not flags but distinct values.
Definition: PPC.h:85
The memory access writes data.
static bool MBBDefinesCTR(MachineBasicBlock &MBB)
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:187
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given stackmap should emit.
Definition: StackMaps.h:51
void setOpcode(unsigned Op)
Definition: MCInst.h:167
bool isUnpredicatedTerminator(const MachineInstr &MI) const override
#define E
Definition: LargeTest.cpp:27
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
#define B
Definition: LargeTest.cpp:24
void getNoop(MCInst &NopInst) const override
Return the noop instruction to use for a noop.
static unsigned getCRBitValue(unsigned CRBit)
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
Predicate getSwappedPredicate(Predicate Opcode)
Assume the condition register is set by MI(a,b), return the predicate if we modify the instructions s...
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:731
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:27
static cl::opt< bool > VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy", cl::desc("Causes the backend to crash instead of generating a nop VSX copy"), cl::Hidden)
static cl::opt< bool > UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden, cl::desc("Use the old (incorrect) instruction latency calculation"))
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
int64_t getImm() const
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction...
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
QVGPCI = This corresponds to the QPX qvgpci instruction.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Predicate InvertPredicate(Predicate Opcode)
Invert the specified predicate. != -> ==, < -> >=.
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:889
On a symbol operand, this represents the lo part.
Definition: AVRInstrInfo.h:53
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
TargetSubtargetInfo - Generic base class for all target subtargets.
#define Success
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in <Root...
bool isPredicated(const MachineInstr &MI) const override
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Representation of each machine instruction.
Definition: MachineInstr.h:59
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
bool hasOneUse(unsigned RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MI-level stackmap operands.
Definition: StackMaps.h:36
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
TargetOptions Options
Definition: TargetMachine.h:95
void setReg(unsigned Reg)
Change the register this operand corresponds to.
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:58
void setSubReg(unsigned subReg)
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given patchpoint should emit.
Definition: StackMaps.h:105
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:568
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
bool isDarwin() const
isDarwin - True if this is any darwin platform.
Definition: PPCSubtarget.h:296
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
LLVM Value Representation.
Definition: Value.h:73
static use_instr_iterator use_instr_end()
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when ...
IRTranslator LLVM IR MI
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:436
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
bool isPredicable(const MachineInstr &MI) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:70
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:284
On a symbol operand "FOO", this indicates that the reference is actually to "FOO@plt".
Definition: PPC.h:69
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: PPCInstrInfo.h:114
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:222
static cl::opt< bool > DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden, cl::desc("Disable analysis for CTR loops"))
MO_PIC_FLAG - If this bit is set, the symbol reference is relative to the function&#39;s picbase...
Definition: PPC.h:73
bool expandPostRAPseudo(MachineInstr &MI) const override
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:144
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:172
bool isImplicit() const