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PPCInstrInfo.cpp
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1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCInstrInfo.h"
16 #include "PPC.h"
17 #include "PPCHazardRecognizers.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCTargetMachine.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Statistic.h"
32 #include "llvm/CodeGen/StackMaps.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCInst.h"
36 #include "llvm/Support/Debug.h"
40 
41 using namespace llvm;
42 
43 #define DEBUG_TYPE "ppc-instr-info"
44 
45 #define GET_INSTRMAP_INFO
46 #define GET_INSTRINFO_CTOR_DTOR
47 #include "PPCGenInstrInfo.inc"
48 
49 STATISTIC(NumStoreSPILLVSRRCAsVec,
50  "Number of spillvsrrc spilled to stack as vec");
51 STATISTIC(NumStoreSPILLVSRRCAsGpr,
52  "Number of spillvsrrc spilled to stack as gpr");
53 STATISTIC(NumGPRtoVSRSpill, "Number of gpr spills to spillvsrrc");
54 STATISTIC(CmpIselsConverted,
55  "Number of ISELs that depend on comparison of constants converted");
56 STATISTIC(MissedConvertibleImmediateInstrs,
57  "Number of compare-immediate instructions fed by constants");
58 STATISTIC(NumRcRotatesConvertedToRcAnd,
59  "Number of record-form rotates converted to record-form andi");
60 
61 static cl::
62 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
63  cl::desc("Disable analysis for CTR loops"));
64 
65 static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
66 cl::desc("Disable compare instruction optimization"), cl::Hidden);
67 
68 static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
69 cl::desc("Causes the backend to crash instead of generating a nop VSX copy"),
70 cl::Hidden);
71 
72 static cl::opt<bool>
73 UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
74  cl::desc("Use the old (incorrect) instruction latency calculation"));
75 
76 // Index into the OpcodesForSpill array.
93  SOK_LastOpcodeSpill // This must be last on the enum.
94 };
95 
96 // Pin the vtable to this file.
97 void PPCInstrInfo::anchor() {}
98 
100  : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP,
101  /* CatchRetOpcode */ -1,
102  STI.isPPC64() ? PPC::BLR8 : PPC::BLR),
103  Subtarget(STI), RI(STI.getTargetMachine()) {}
104 
105 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
106 /// this target when scheduling the DAG.
109  const ScheduleDAG *DAG) const {
110  unsigned Directive =
111  static_cast<const PPCSubtarget *>(STI)->getDarwinDirective();
112  if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
113  Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
114  const InstrItineraryData *II =
115  static_cast<const PPCSubtarget *>(STI)->getInstrItineraryData();
116  return new ScoreboardHazardRecognizer(II, DAG);
117  }
118 
120 }
121 
122 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
123 /// to use for this target when scheduling the DAG.
126  const ScheduleDAG *DAG) const {
127  unsigned Directive =
128  DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
129 
130  // FIXME: Leaving this as-is until we have POWER9 scheduling info
131  if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8)
132  return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
133 
134  // Most subtargets use a PPC970 recognizer.
135  if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
136  Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
137  assert(DAG->TII && "No InstrInfo?");
138 
139  return new PPCHazardRecognizer970(*DAG);
140  }
141 
142  return new ScoreboardHazardRecognizer(II, DAG);
143 }
144 
146  const MachineInstr &MI,
147  unsigned *PredCost) const {
148  if (!ItinData || UseOldLatencyCalc)
149  return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
150 
151  // The default implementation of getInstrLatency calls getStageLatency, but
152  // getStageLatency does not do the right thing for us. While we have
153  // itinerary, most cores are fully pipelined, and so the itineraries only
154  // express the first part of the pipeline, not every stage. Instead, we need
155  // to use the listed output operand cycle number (using operand 0 here, which
156  // is an output).
157 
158  unsigned Latency = 1;
159  unsigned DefClass = MI.getDesc().getSchedClass();
160  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
161  const MachineOperand &MO = MI.getOperand(i);
162  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
163  continue;
164 
165  int Cycle = ItinData->getOperandCycle(DefClass, i);
166  if (Cycle < 0)
167  continue;
168 
169  Latency = std::max(Latency, (unsigned) Cycle);
170  }
171 
172  return Latency;
173 }
174 
176  const MachineInstr &DefMI, unsigned DefIdx,
177  const MachineInstr &UseMI,
178  unsigned UseIdx) const {
179  int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
180  UseMI, UseIdx);
181 
182  if (!DefMI.getParent())
183  return Latency;
184 
185  const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
186  unsigned Reg = DefMO.getReg();
187 
188  bool IsRegCR;
190  const MachineRegisterInfo *MRI =
191  &DefMI.getParent()->getParent()->getRegInfo();
192  IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
193  MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
194  } else {
195  IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
196  PPC::CRBITRCRegClass.contains(Reg);
197  }
198 
199  if (UseMI.isBranch() && IsRegCR) {
200  if (Latency < 0)
201  Latency = getInstrLatency(ItinData, DefMI);
202 
203  // On some cores, there is an additional delay between writing to a condition
204  // register, and using it from a branch.
205  unsigned Directive = Subtarget.getDarwinDirective();
206  switch (Directive) {
207  default: break;
208  case PPC::DIR_7400:
209  case PPC::DIR_750:
210  case PPC::DIR_970:
211  case PPC::DIR_E5500:
212  case PPC::DIR_PWR4:
213  case PPC::DIR_PWR5:
214  case PPC::DIR_PWR5X:
215  case PPC::DIR_PWR6:
216  case PPC::DIR_PWR6X:
217  case PPC::DIR_PWR7:
218  case PPC::DIR_PWR8:
219  // FIXME: Is this needed for POWER9?
220  Latency += 2;
221  break;
222  }
223  }
224 
225  return Latency;
226 }
227 
228 // This function does not list all associative and commutative operations, but
229 // only those worth feeding through the machine combiner in an attempt to
230 // reduce the critical path. Mostly, this means floating-point operations,
231 // because they have high latencies (compared to other operations, such and
232 // and/or, which are also associative and commutative, but have low latencies).
234  switch (Inst.getOpcode()) {
235  // FP Add:
236  case PPC::FADD:
237  case PPC::FADDS:
238  // FP Multiply:
239  case PPC::FMUL:
240  case PPC::FMULS:
241  // Altivec Add:
242  case PPC::VADDFP:
243  // VSX Add:
244  case PPC::XSADDDP:
245  case PPC::XVADDDP:
246  case PPC::XVADDSP:
247  case PPC::XSADDSP:
248  // VSX Multiply:
249  case PPC::XSMULDP:
250  case PPC::XVMULDP:
251  case PPC::XVMULSP:
252  case PPC::XSMULSP:
253  // QPX Add:
254  case PPC::QVFADD:
255  case PPC::QVFADDS:
256  case PPC::QVFADDSs:
257  // QPX Multiply:
258  case PPC::QVFMUL:
259  case PPC::QVFMULS:
260  case PPC::QVFMULSs:
261  return true;
262  default:
263  return false;
264  }
265 }
266 
268  MachineInstr &Root,
269  SmallVectorImpl<MachineCombinerPattern> &Patterns) const {
270  // Using the machine combiner in this way is potentially expensive, so
271  // restrict to when aggressive optimizations are desired.
273  return false;
274 
275  // FP reassociation is only legal when we don't need strict IEEE semantics.
277  return false;
278 
279  return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns);
280 }
281 
282 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
284  unsigned &SrcReg, unsigned &DstReg,
285  unsigned &SubIdx) const {
286  switch (MI.getOpcode()) {
287  default: return false;
288  case PPC::EXTSW:
289  case PPC::EXTSW_32:
290  case PPC::EXTSW_32_64:
291  SrcReg = MI.getOperand(1).getReg();
292  DstReg = MI.getOperand(0).getReg();
293  SubIdx = PPC::sub_32;
294  return true;
295  }
296 }
297 
299  int &FrameIndex) const {
300  unsigned Opcode = MI.getOpcode();
301  const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
302  const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill;
303 
304  if (End != std::find(OpcodesForSpill, End, Opcode)) {
305  // Check for the operands added by addFrameReference (the immediate is the
306  // offset which defaults to 0).
307  if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
308  MI.getOperand(2).isFI()) {
309  FrameIndex = MI.getOperand(2).getIndex();
310  return MI.getOperand(0).getReg();
311  }
312  }
313  return 0;
314 }
315 
316 // For opcodes with the ReMaterializable flag set, this function is called to
317 // verify the instruction is really rematable.
319  AliasAnalysis *AA) const {
320  switch (MI.getOpcode()) {
321  default:
322  // This function should only be called for opcodes with the ReMaterializable
323  // flag set.
324  llvm_unreachable("Unknown rematerializable operation!");
325  break;
326  case PPC::LI:
327  case PPC::LI8:
328  case PPC::LIS:
329  case PPC::LIS8:
330  case PPC::QVGPCI:
331  case PPC::ADDIStocHA:
332  case PPC::ADDItocL:
333  case PPC::LOAD_STACK_GUARD:
334  return true;
335  }
336  return false;
337 }
338 
340  int &FrameIndex) const {
341  unsigned Opcode = MI.getOpcode();
342  const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
343  const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill;
344 
345  if (End != std::find(OpcodesForSpill, End, Opcode)) {
346  if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
347  MI.getOperand(2).isFI()) {
348  FrameIndex = MI.getOperand(2).getIndex();
349  return MI.getOperand(0).getReg();
350  }
351  }
352  return 0;
353 }
354 
356  unsigned OpIdx1,
357  unsigned OpIdx2) const {
358  MachineFunction &MF = *MI.getParent()->getParent();
359 
360  // Normal instructions can be commuted the obvious way.
361  if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMIo)
362  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
363  // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
364  // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
365  // changing the relative order of the mask operands might change what happens
366  // to the high-bits of the mask (and, thus, the result).
367 
368  // Cannot commute if it has a non-zero rotate count.
369  if (MI.getOperand(3).getImm() != 0)
370  return nullptr;
371 
372  // If we have a zero rotate count, we have:
373  // M = mask(MB,ME)
374  // Op0 = (Op1 & ~M) | (Op2 & M)
375  // Change this to:
376  // M = mask((ME+1)&31, (MB-1)&31)
377  // Op0 = (Op2 & ~M) | (Op1 & M)
378 
379  // Swap op1/op2
380  assert(((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) &&
381  "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo.");
382  unsigned Reg0 = MI.getOperand(0).getReg();
383  unsigned Reg1 = MI.getOperand(1).getReg();
384  unsigned Reg2 = MI.getOperand(2).getReg();
385  unsigned SubReg1 = MI.getOperand(1).getSubReg();
386  unsigned SubReg2 = MI.getOperand(2).getSubReg();
387  bool Reg1IsKill = MI.getOperand(1).isKill();
388  bool Reg2IsKill = MI.getOperand(2).isKill();
389  bool ChangeReg0 = false;
390  // If machine instrs are no longer in two-address forms, update
391  // destination register as well.
392  if (Reg0 == Reg1) {
393  // Must be two address instruction!
395  "Expecting a two-address instruction!");
396  assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
397  Reg2IsKill = false;
398  ChangeReg0 = true;
399  }
400 
401  // Masks.
402  unsigned MB = MI.getOperand(4).getImm();
403  unsigned ME = MI.getOperand(5).getImm();
404 
405  // We can't commute a trivial mask (there is no way to represent an all-zero
406  // mask).
407  if (MB == 0 && ME == 31)
408  return nullptr;
409 
410  if (NewMI) {
411  // Create a new instruction.
412  unsigned Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg();
413  bool Reg0IsDead = MI.getOperand(0).isDead();
414  return BuildMI(MF, MI.getDebugLoc(), MI.getDesc())
415  .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
416  .addReg(Reg2, getKillRegState(Reg2IsKill))
417  .addReg(Reg1, getKillRegState(Reg1IsKill))
418  .addImm((ME + 1) & 31)
419  .addImm((MB - 1) & 31);
420  }
421 
422  if (ChangeReg0) {
423  MI.getOperand(0).setReg(Reg2);
424  MI.getOperand(0).setSubReg(SubReg2);
425  }
426  MI.getOperand(2).setReg(Reg1);
427  MI.getOperand(1).setReg(Reg2);
428  MI.getOperand(2).setSubReg(SubReg1);
429  MI.getOperand(1).setSubReg(SubReg2);
430  MI.getOperand(2).setIsKill(Reg1IsKill);
431  MI.getOperand(1).setIsKill(Reg2IsKill);
432 
433  // Swap the mask around.
434  MI.getOperand(4).setImm((ME + 1) & 31);
435  MI.getOperand(5).setImm((MB - 1) & 31);
436  return &MI;
437 }
438 
440  unsigned &SrcOpIdx2) const {
441  // For VSX A-Type FMA instructions, it is the first two operands that can be
442  // commuted, however, because the non-encoded tied input operand is listed
443  // first, the operands to swap are actually the second and third.
444 
445  int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode());
446  if (AltOpc == -1)
447  return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
448 
449  // The commutable operand indices are 2 and 3. Return them in SrcOpIdx1
450  // and SrcOpIdx2.
451  return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
452 }
453 
456  // This function is used for scheduling, and the nop wanted here is the type
457  // that terminates dispatch groups on the POWER cores.
458  unsigned Directive = Subtarget.getDarwinDirective();
459  unsigned Opcode;
460  switch (Directive) {
461  default: Opcode = PPC::NOP; break;
462  case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
463  case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
464  case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */
465  // FIXME: Update when POWER9 scheduling model is ready.
466  case PPC::DIR_PWR9: Opcode = PPC::NOP_GT_PWR7; break;
467  }
468 
469  DebugLoc DL;
470  BuildMI(MBB, MI, DL, get(Opcode));
471 }
472 
473 /// Return the noop instruction to use for a noop.
474 void PPCInstrInfo::getNoop(MCInst &NopInst) const {
475  NopInst.setOpcode(PPC::NOP);
476 }
477 
478 // Branch analysis.
479 // Note: If the condition register is set to CTR or CTR8 then this is a
480 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
482  MachineBasicBlock *&TBB,
483  MachineBasicBlock *&FBB,
485  bool AllowModify) const {
486  bool isPPC64 = Subtarget.isPPC64();
487 
488  // If the block has no terminators, it just falls into the block after it.
490  if (I == MBB.end())
491  return false;
492 
493  if (!isUnpredicatedTerminator(*I))
494  return false;
495 
496  if (AllowModify) {
497  // If the BB ends with an unconditional branch to the fallthrough BB,
498  // we eliminate the branch instruction.
499  if (I->getOpcode() == PPC::B &&
500  MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
501  I->eraseFromParent();
502 
503  // We update iterator after deleting the last branch.
504  I = MBB.getLastNonDebugInstr();
505  if (I == MBB.end() || !isUnpredicatedTerminator(*I))
506  return false;
507  }
508  }
509 
510  // Get the last instruction in the block.
511  MachineInstr &LastInst = *I;
512 
513  // If there is only one terminator instruction, process it.
514  if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
515  if (LastInst.getOpcode() == PPC::B) {
516  if (!LastInst.getOperand(0).isMBB())
517  return true;
518  TBB = LastInst.getOperand(0).getMBB();
519  return false;
520  } else if (LastInst.getOpcode() == PPC::BCC) {
521  if (!LastInst.getOperand(2).isMBB())
522  return true;
523  // Block ends with fall-through condbranch.
524  TBB = LastInst.getOperand(2).getMBB();
525  Cond.push_back(LastInst.getOperand(0));
526  Cond.push_back(LastInst.getOperand(1));
527  return false;
528  } else if (LastInst.getOpcode() == PPC::BC) {
529  if (!LastInst.getOperand(1).isMBB())
530  return true;
531  // Block ends with fall-through condbranch.
532  TBB = LastInst.getOperand(1).getMBB();
534  Cond.push_back(LastInst.getOperand(0));
535  return false;
536  } else if (LastInst.getOpcode() == PPC::BCn) {
537  if (!LastInst.getOperand(1).isMBB())
538  return true;
539  // Block ends with fall-through condbranch.
540  TBB = LastInst.getOperand(1).getMBB();
542  Cond.push_back(LastInst.getOperand(0));
543  return false;
544  } else if (LastInst.getOpcode() == PPC::BDNZ8 ||
545  LastInst.getOpcode() == PPC::BDNZ) {
546  if (!LastInst.getOperand(0).isMBB())
547  return true;
548  if (DisableCTRLoopAnal)
549  return true;
550  TBB = LastInst.getOperand(0).getMBB();
552  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
553  true));
554  return false;
555  } else if (LastInst.getOpcode() == PPC::BDZ8 ||
556  LastInst.getOpcode() == PPC::BDZ) {
557  if (!LastInst.getOperand(0).isMBB())
558  return true;
559  if (DisableCTRLoopAnal)
560  return true;
561  TBB = LastInst.getOperand(0).getMBB();
563  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
564  true));
565  return false;
566  }
567 
568  // Otherwise, don't know what this is.
569  return true;
570  }
571 
572  // Get the instruction before it if it's a terminator.
573  MachineInstr &SecondLastInst = *I;
574 
575  // If there are three terminators, we don't know what sort of block this is.
576  if (I != MBB.begin() && isUnpredicatedTerminator(*--I))
577  return true;
578 
579  // If the block ends with PPC::B and PPC:BCC, handle it.
580  if (SecondLastInst.getOpcode() == PPC::BCC &&
581  LastInst.getOpcode() == PPC::B) {
582  if (!SecondLastInst.getOperand(2).isMBB() ||
583  !LastInst.getOperand(0).isMBB())
584  return true;
585  TBB = SecondLastInst.getOperand(2).getMBB();
586  Cond.push_back(SecondLastInst.getOperand(0));
587  Cond.push_back(SecondLastInst.getOperand(1));
588  FBB = LastInst.getOperand(0).getMBB();
589  return false;
590  } else if (SecondLastInst.getOpcode() == PPC::BC &&
591  LastInst.getOpcode() == PPC::B) {
592  if (!SecondLastInst.getOperand(1).isMBB() ||
593  !LastInst.getOperand(0).isMBB())
594  return true;
595  TBB = SecondLastInst.getOperand(1).getMBB();
597  Cond.push_back(SecondLastInst.getOperand(0));
598  FBB = LastInst.getOperand(0).getMBB();
599  return false;
600  } else if (SecondLastInst.getOpcode() == PPC::BCn &&
601  LastInst.getOpcode() == PPC::B) {
602  if (!SecondLastInst.getOperand(1).isMBB() ||
603  !LastInst.getOperand(0).isMBB())
604  return true;
605  TBB = SecondLastInst.getOperand(1).getMBB();
607  Cond.push_back(SecondLastInst.getOperand(0));
608  FBB = LastInst.getOperand(0).getMBB();
609  return false;
610  } else if ((SecondLastInst.getOpcode() == PPC::BDNZ8 ||
611  SecondLastInst.getOpcode() == PPC::BDNZ) &&
612  LastInst.getOpcode() == PPC::B) {
613  if (!SecondLastInst.getOperand(0).isMBB() ||
614  !LastInst.getOperand(0).isMBB())
615  return true;
616  if (DisableCTRLoopAnal)
617  return true;
618  TBB = SecondLastInst.getOperand(0).getMBB();
620  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
621  true));
622  FBB = LastInst.getOperand(0).getMBB();
623  return false;
624  } else if ((SecondLastInst.getOpcode() == PPC::BDZ8 ||
625  SecondLastInst.getOpcode() == PPC::BDZ) &&
626  LastInst.getOpcode() == PPC::B) {
627  if (!SecondLastInst.getOperand(0).isMBB() ||
628  !LastInst.getOperand(0).isMBB())
629  return true;
630  if (DisableCTRLoopAnal)
631  return true;
632  TBB = SecondLastInst.getOperand(0).getMBB();
634  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
635  true));
636  FBB = LastInst.getOperand(0).getMBB();
637  return false;
638  }
639 
640  // If the block ends with two PPC:Bs, handle it. The second one is not
641  // executed, so remove it.
642  if (SecondLastInst.getOpcode() == PPC::B && LastInst.getOpcode() == PPC::B) {
643  if (!SecondLastInst.getOperand(0).isMBB())
644  return true;
645  TBB = SecondLastInst.getOperand(0).getMBB();
646  I = LastInst;
647  if (AllowModify)
648  I->eraseFromParent();
649  return false;
650  }
651 
652  // Otherwise, can't handle this.
653  return true;
654 }
655 
657  int *BytesRemoved) const {
658  assert(!BytesRemoved && "code size not handled");
659 
661  if (I == MBB.end())
662  return 0;
663 
664  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
665  I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
666  I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
667  I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
668  return 0;
669 
670  // Remove the branch.
671  I->eraseFromParent();
672 
673  I = MBB.end();
674 
675  if (I == MBB.begin()) return 1;
676  --I;
677  if (I->getOpcode() != PPC::BCC &&
678  I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
679  I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
680  I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
681  return 1;
682 
683  // Remove the branch.
684  I->eraseFromParent();
685  return 2;
686 }
687 
689  MachineBasicBlock *TBB,
690  MachineBasicBlock *FBB,
692  const DebugLoc &DL,
693  int *BytesAdded) const {
694  // Shouldn't be a fall through.
695  assert(TBB && "insertBranch must not be told to insert a fallthrough");
696  assert((Cond.size() == 2 || Cond.size() == 0) &&
697  "PPC branch conditions have two components!");
698  assert(!BytesAdded && "code size not handled");
699 
700  bool isPPC64 = Subtarget.isPPC64();
701 
702  // One-way branch.
703  if (!FBB) {
704  if (Cond.empty()) // Unconditional branch
705  BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
706  else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
707  BuildMI(&MBB, DL, get(Cond[0].getImm() ?
708  (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
709  (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
710  else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
711  BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
712  else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
713  BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
714  else // Conditional branch
715  BuildMI(&MBB, DL, get(PPC::BCC))
716  .addImm(Cond[0].getImm())
717  .add(Cond[1])
718  .addMBB(TBB);
719  return 1;
720  }
721 
722  // Two-way Conditional Branch.
723  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
724  BuildMI(&MBB, DL, get(Cond[0].getImm() ?
725  (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
726  (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
727  else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
728  BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
729  else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
730  BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
731  else
732  BuildMI(&MBB, DL, get(PPC::BCC))
733  .addImm(Cond[0].getImm())
734  .add(Cond[1])
735  .addMBB(TBB);
736  BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
737  return 2;
738 }
739 
740 // Select analysis.
743  unsigned TrueReg, unsigned FalseReg,
744  int &CondCycles, int &TrueCycles, int &FalseCycles) const {
745  if (Cond.size() != 2)
746  return false;
747 
748  // If this is really a bdnz-like condition, then it cannot be turned into a
749  // select.
750  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
751  return false;
752 
753  // Check register classes.
754  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
755  const TargetRegisterClass *RC =
756  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
757  if (!RC)
758  return false;
759 
760  // isel is for regular integer GPRs only.
761  if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
762  !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
763  !PPC::G8RCRegClass.hasSubClassEq(RC) &&
764  !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
765  return false;
766 
767  // FIXME: These numbers are for the A2, how well they work for other cores is
768  // an open question. On the A2, the isel instruction has a 2-cycle latency
769  // but single-cycle throughput. These numbers are used in combination with
770  // the MispredictPenalty setting from the active SchedMachineModel.
771  CondCycles = 1;
772  TrueCycles = 1;
773  FalseCycles = 1;
774 
775  return true;
776 }
777 
780  const DebugLoc &dl, unsigned DestReg,
781  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
782  unsigned FalseReg) const {
783  assert(Cond.size() == 2 &&
784  "PPC branch conditions have two components!");
785 
786  // Get the register classes.
788  const TargetRegisterClass *RC =
789  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
790  assert(RC && "TrueReg and FalseReg must have overlapping register classes");
791 
792  bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
793  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
794  assert((Is64Bit ||
795  PPC::GPRCRegClass.hasSubClassEq(RC) ||
796  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
797  "isel is for regular integer GPRs only");
798 
799  unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
800  auto SelectPred = static_cast<PPC::Predicate>(Cond[0].getImm());
801 
802  unsigned SubIdx = 0;
803  bool SwapOps = false;
804  switch (SelectPred) {
805  case PPC::PRED_EQ:
806  case PPC::PRED_EQ_MINUS:
807  case PPC::PRED_EQ_PLUS:
808  SubIdx = PPC::sub_eq; SwapOps = false; break;
809  case PPC::PRED_NE:
810  case PPC::PRED_NE_MINUS:
811  case PPC::PRED_NE_PLUS:
812  SubIdx = PPC::sub_eq; SwapOps = true; break;
813  case PPC::PRED_LT:
814  case PPC::PRED_LT_MINUS:
815  case PPC::PRED_LT_PLUS:
816  SubIdx = PPC::sub_lt; SwapOps = false; break;
817  case PPC::PRED_GE:
818  case PPC::PRED_GE_MINUS:
819  case PPC::PRED_GE_PLUS:
820  SubIdx = PPC::sub_lt; SwapOps = true; break;
821  case PPC::PRED_GT:
822  case PPC::PRED_GT_MINUS:
823  case PPC::PRED_GT_PLUS:
824  SubIdx = PPC::sub_gt; SwapOps = false; break;
825  case PPC::PRED_LE:
826  case PPC::PRED_LE_MINUS:
827  case PPC::PRED_LE_PLUS:
828  SubIdx = PPC::sub_gt; SwapOps = true; break;
829  case PPC::PRED_UN:
830  case PPC::PRED_UN_MINUS:
831  case PPC::PRED_UN_PLUS:
832  SubIdx = PPC::sub_un; SwapOps = false; break;
833  case PPC::PRED_NU:
834  case PPC::PRED_NU_MINUS:
835  case PPC::PRED_NU_PLUS:
836  SubIdx = PPC::sub_un; SwapOps = true; break;
837  case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break;
838  case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break;
839  }
840 
841  unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
842  SecondReg = SwapOps ? TrueReg : FalseReg;
843 
844  // The first input register of isel cannot be r0. If it is a member
845  // of a register class that can be r0, then copy it first (the
846  // register allocator should eliminate the copy).
847  if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
848  MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
849  const TargetRegisterClass *FirstRC =
850  MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
851  &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
852  unsigned OldFirstReg = FirstReg;
853  FirstReg = MRI.createVirtualRegister(FirstRC);
854  BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
855  .addReg(OldFirstReg);
856  }
857 
858  BuildMI(MBB, MI, dl, get(OpCode), DestReg)
859  .addReg(FirstReg).addReg(SecondReg)
860  .addReg(Cond[1].getReg(), 0, SubIdx);
861 }
862 
863 static unsigned getCRBitValue(unsigned CRBit) {
864  unsigned Ret = 4;
865  if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT ||
866  CRBit == PPC::CR2LT || CRBit == PPC::CR3LT ||
867  CRBit == PPC::CR4LT || CRBit == PPC::CR5LT ||
868  CRBit == PPC::CR6LT || CRBit == PPC::CR7LT)
869  Ret = 3;
870  if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT ||
871  CRBit == PPC::CR2GT || CRBit == PPC::CR3GT ||
872  CRBit == PPC::CR4GT || CRBit == PPC::CR5GT ||
873  CRBit == PPC::CR6GT || CRBit == PPC::CR7GT)
874  Ret = 2;
875  if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ ||
876  CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ ||
877  CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ ||
878  CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ)
879  Ret = 1;
880  if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN ||
881  CRBit == PPC::CR2UN || CRBit == PPC::CR3UN ||
882  CRBit == PPC::CR4UN || CRBit == PPC::CR5UN ||
883  CRBit == PPC::CR6UN || CRBit == PPC::CR7UN)
884  Ret = 0;
885 
886  assert(Ret != 4 && "Invalid CR bit register");
887  return Ret;
888 }
889 
892  const DebugLoc &DL, unsigned DestReg,
893  unsigned SrcReg, bool KillSrc) const {
894  // We can end up with self copies and similar things as a result of VSX copy
895  // legalization. Promote them here.
897  if (PPC::F8RCRegClass.contains(DestReg) &&
898  PPC::VSRCRegClass.contains(SrcReg)) {
899  unsigned SuperReg =
900  TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
901 
902  if (VSXSelfCopyCrash && SrcReg == SuperReg)
903  llvm_unreachable("nop VSX copy");
904 
905  DestReg = SuperReg;
906  } else if (PPC::F8RCRegClass.contains(SrcReg) &&
907  PPC::VSRCRegClass.contains(DestReg)) {
908  unsigned SuperReg =
909  TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
910 
911  if (VSXSelfCopyCrash && DestReg == SuperReg)
912  llvm_unreachable("nop VSX copy");
913 
914  SrcReg = SuperReg;
915  }
916 
917  // Different class register copy
918  if (PPC::CRBITRCRegClass.contains(SrcReg) &&
919  PPC::GPRCRegClass.contains(DestReg)) {
920  unsigned CRReg = getCRFromCRBit(SrcReg);
921  BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg);
922  getKillRegState(KillSrc);
923  // Rotate the CR bit in the CR fields to be the least significant bit and
924  // then mask with 0x1 (MB = ME = 31).
925  BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
926  .addReg(DestReg, RegState::Kill)
927  .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
928  .addImm(31)
929  .addImm(31);
930  return;
931  } else if (PPC::CRRCRegClass.contains(SrcReg) &&
932  PPC::G8RCRegClass.contains(DestReg)) {
933  BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg).addReg(SrcReg);
934  getKillRegState(KillSrc);
935  return;
936  } else if (PPC::CRRCRegClass.contains(SrcReg) &&
937  PPC::GPRCRegClass.contains(DestReg)) {
938  BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(SrcReg);
939  getKillRegState(KillSrc);
940  return;
941  } else if (PPC::G8RCRegClass.contains(SrcReg) &&
942  PPC::VSFRCRegClass.contains(DestReg)) {
943  BuildMI(MBB, I, DL, get(PPC::MTVSRD), DestReg).addReg(SrcReg);
944  NumGPRtoVSRSpill++;
945  getKillRegState(KillSrc);
946  return;
947  } else if (PPC::VSFRCRegClass.contains(SrcReg) &&
948  PPC::G8RCRegClass.contains(DestReg)) {
949  BuildMI(MBB, I, DL, get(PPC::MFVSRD), DestReg).addReg(SrcReg);
950  getKillRegState(KillSrc);
951  return;
952  }
953 
954  unsigned Opc;
955  if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
956  Opc = PPC::OR;
957  else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
958  Opc = PPC::OR8;
959  else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
960  Opc = PPC::FMR;
961  else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
962  Opc = PPC::MCRF;
963  else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
964  Opc = PPC::VOR;
965  else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
966  // There are two different ways this can be done:
967  // 1. xxlor : This has lower latency (on the P7), 2 cycles, but can only
968  // issue in VSU pipeline 0.
969  // 2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
970  // can go to either pipeline.
971  // We'll always use xxlor here, because in practically all cases where
972  // copies are generated, they are close enough to some use that the
973  // lower-latency form is preferable.
974  Opc = PPC::XXLOR;
975  else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) ||
976  PPC::VSSRCRegClass.contains(DestReg, SrcReg))
977  Opc = PPC::XXLORf;
978  else if (PPC::QFRCRegClass.contains(DestReg, SrcReg))
979  Opc = PPC::QVFMR;
980  else if (PPC::QSRCRegClass.contains(DestReg, SrcReg))
981  Opc = PPC::QVFMRs;
982  else if (PPC::QBRCRegClass.contains(DestReg, SrcReg))
983  Opc = PPC::QVFMRb;
984  else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
985  Opc = PPC::CROR;
986  else
987  llvm_unreachable("Impossible reg-to-reg copy");
988 
989  const MCInstrDesc &MCID = get(Opc);
990  if (MCID.getNumOperands() == 3)
991  BuildMI(MBB, I, DL, MCID, DestReg)
992  .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
993  else
994  BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
995 }
996 
998  const TargetRegisterClass *RC)
999  const {
1000  const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
1001  int OpcodeIndex = 0;
1002 
1003  if (RC != nullptr) {
1004  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1005  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1006  OpcodeIndex = SOK_Int4Spill;
1007  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1008  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1009  OpcodeIndex = SOK_Int8Spill;
1010  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1011  OpcodeIndex = SOK_Float8Spill;
1012  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1013  OpcodeIndex = SOK_Float4Spill;
1014  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1015  OpcodeIndex = SOK_CRSpill;
1016  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1017  OpcodeIndex = SOK_CRBitSpill;
1018  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1019  OpcodeIndex = SOK_VRVectorSpill;
1020  } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1021  OpcodeIndex = SOK_VSXVectorSpill;
1022  } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1023  OpcodeIndex = SOK_VectorFloat8Spill;
1024  } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1025  OpcodeIndex = SOK_VectorFloat4Spill;
1026  } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1027  OpcodeIndex = SOK_VRSaveSpill;
1028  } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1029  OpcodeIndex = SOK_QuadFloat8Spill;
1030  } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1031  OpcodeIndex = SOK_QuadFloat4Spill;
1032  } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1033  OpcodeIndex = SOK_QuadBitSpill;
1034  } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1035  OpcodeIndex = SOK_SpillToVSR;
1036  } else {
1037  llvm_unreachable("Unknown regclass!");
1038  }
1039  } else {
1040  if (PPC::GPRCRegClass.contains(Reg) ||
1041  PPC::GPRC_NOR0RegClass.contains(Reg)) {
1042  OpcodeIndex = SOK_Int4Spill;
1043  } else if (PPC::G8RCRegClass.contains(Reg) ||
1044  PPC::G8RC_NOX0RegClass.contains(Reg)) {
1045  OpcodeIndex = SOK_Int8Spill;
1046  } else if (PPC::F8RCRegClass.contains(Reg)) {
1047  OpcodeIndex = SOK_Float8Spill;
1048  } else if (PPC::F4RCRegClass.contains(Reg)) {
1049  OpcodeIndex = SOK_Float4Spill;
1050  } else if (PPC::CRRCRegClass.contains(Reg)) {
1051  OpcodeIndex = SOK_CRSpill;
1052  } else if (PPC::CRBITRCRegClass.contains(Reg)) {
1053  OpcodeIndex = SOK_CRBitSpill;
1054  } else if (PPC::VRRCRegClass.contains(Reg)) {
1055  OpcodeIndex = SOK_VRVectorSpill;
1056  } else if (PPC::VSRCRegClass.contains(Reg)) {
1057  OpcodeIndex = SOK_VSXVectorSpill;
1058  } else if (PPC::VSFRCRegClass.contains(Reg)) {
1059  OpcodeIndex = SOK_VectorFloat8Spill;
1060  } else if (PPC::VSSRCRegClass.contains(Reg)) {
1061  OpcodeIndex = SOK_VectorFloat4Spill;
1062  } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1063  OpcodeIndex = SOK_VRSaveSpill;
1064  } else if (PPC::QFRCRegClass.contains(Reg)) {
1065  OpcodeIndex = SOK_QuadFloat8Spill;
1066  } else if (PPC::QSRCRegClass.contains(Reg)) {
1067  OpcodeIndex = SOK_QuadFloat4Spill;
1068  } else if (PPC::QBRCRegClass.contains(Reg)) {
1069  OpcodeIndex = SOK_QuadBitSpill;
1070  } else if (PPC::SPILLTOVSRRCRegClass.contains(Reg)) {
1071  OpcodeIndex = SOK_SpillToVSR;
1072  } else {
1073  llvm_unreachable("Unknown regclass!");
1074  }
1075  }
1076  return OpcodesForSpill[OpcodeIndex];
1077 }
1078 
1079 unsigned
1081  const TargetRegisterClass *RC) const {
1082  const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
1083  int OpcodeIndex = 0;
1084 
1085  if (RC != nullptr) {
1086  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1087  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1088  OpcodeIndex = SOK_Int4Spill;
1089  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1090  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1091  OpcodeIndex = SOK_Int8Spill;
1092  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1093  OpcodeIndex = SOK_Float8Spill;
1094  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1095  OpcodeIndex = SOK_Float4Spill;
1096  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1097  OpcodeIndex = SOK_CRSpill;
1098  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1099  OpcodeIndex = SOK_CRBitSpill;
1100  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1101  OpcodeIndex = SOK_VRVectorSpill;
1102  } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1103  OpcodeIndex = SOK_VSXVectorSpill;
1104  } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1105  OpcodeIndex = SOK_VectorFloat8Spill;
1106  } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1107  OpcodeIndex = SOK_VectorFloat4Spill;
1108  } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1109  OpcodeIndex = SOK_VRSaveSpill;
1110  } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1111  OpcodeIndex = SOK_QuadFloat8Spill;
1112  } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1113  OpcodeIndex = SOK_QuadFloat4Spill;
1114  } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1115  OpcodeIndex = SOK_QuadBitSpill;
1116  } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1117  OpcodeIndex = SOK_SpillToVSR;
1118  } else {
1119  llvm_unreachable("Unknown regclass!");
1120  }
1121  } else {
1122  if (PPC::GPRCRegClass.contains(Reg) ||
1123  PPC::GPRC_NOR0RegClass.contains(Reg)) {
1124  OpcodeIndex = SOK_Int4Spill;
1125  } else if (PPC::G8RCRegClass.contains(Reg) ||
1126  PPC::G8RC_NOX0RegClass.contains(Reg)) {
1127  OpcodeIndex = SOK_Int8Spill;
1128  } else if (PPC::F8RCRegClass.contains(Reg)) {
1129  OpcodeIndex = SOK_Float8Spill;
1130  } else if (PPC::F4RCRegClass.contains(Reg)) {
1131  OpcodeIndex = SOK_Float4Spill;
1132  } else if (PPC::CRRCRegClass.contains(Reg)) {
1133  OpcodeIndex = SOK_CRSpill;
1134  } else if (PPC::CRBITRCRegClass.contains(Reg)) {
1135  OpcodeIndex = SOK_CRBitSpill;
1136  } else if (PPC::VRRCRegClass.contains(Reg)) {
1137  OpcodeIndex = SOK_VRVectorSpill;
1138  } else if (PPC::VSRCRegClass.contains(Reg)) {
1139  OpcodeIndex = SOK_VSXVectorSpill;
1140  } else if (PPC::VSFRCRegClass.contains(Reg)) {
1141  OpcodeIndex = SOK_VectorFloat8Spill;
1142  } else if (PPC::VSSRCRegClass.contains(Reg)) {
1143  OpcodeIndex = SOK_VectorFloat4Spill;
1144  } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1145  OpcodeIndex = SOK_VRSaveSpill;
1146  } else if (PPC::QFRCRegClass.contains(Reg)) {
1147  OpcodeIndex = SOK_QuadFloat8Spill;
1148  } else if (PPC::QSRCRegClass.contains(Reg)) {
1149  OpcodeIndex = SOK_QuadFloat4Spill;
1150  } else if (PPC::QBRCRegClass.contains(Reg)) {
1151  OpcodeIndex = SOK_QuadBitSpill;
1152  } else if (PPC::SPILLTOVSRRCRegClass.contains(Reg)) {
1153  OpcodeIndex = SOK_SpillToVSR;
1154  } else {
1155  llvm_unreachable("Unknown regclass!");
1156  }
1157  }
1158  return OpcodesForSpill[OpcodeIndex];
1159 }
1160 
1161 void PPCInstrInfo::StoreRegToStackSlot(
1162  MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx,
1163  const TargetRegisterClass *RC,
1164  SmallVectorImpl<MachineInstr *> &NewMIs) const {
1165  unsigned Opcode = getStoreOpcodeForSpill(PPC::NoRegister, RC);
1166  DebugLoc DL;
1167 
1168  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1169  FuncInfo->setHasSpills();
1170 
1172  BuildMI(MF, DL, get(Opcode)).addReg(SrcReg, getKillRegState(isKill)),
1173  FrameIdx));
1174 
1175  if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1176  PPC::CRBITRCRegClass.hasSubClassEq(RC))
1177  FuncInfo->setSpillsCR();
1178 
1179  if (PPC::VRSAVERCRegClass.hasSubClassEq(RC))
1180  FuncInfo->setSpillsVRSAVE();
1181 
1182  if (isXFormMemOp(Opcode))
1183  FuncInfo->setHasNonRISpills();
1184 }
1185 
1188  unsigned SrcReg, bool isKill,
1189  int FrameIdx,
1190  const TargetRegisterClass *RC,
1191  const TargetRegisterInfo *TRI) const {
1192  MachineFunction &MF = *MBB.getParent();
1194 
1195  // We need to avoid a situation in which the value from a VRRC register is
1196  // spilled using an Altivec instruction and reloaded into a VSRC register
1197  // using a VSX instruction. The issue with this is that the VSX
1198  // load/store instructions swap the doublewords in the vector and the Altivec
1199  // ones don't. The register classes on the spill/reload may be different if
1200  // the register is defined using an Altivec instruction and is then used by a
1201  // VSX instruction.
1202  RC = updatedRC(RC);
1203 
1204  StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs);
1205 
1206  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1207  MBB.insert(MI, NewMIs[i]);
1208 
1209  const MachineFrameInfo &MFI = MF.getFrameInfo();
1211  MachinePointerInfo::getFixedStack(MF, FrameIdx),
1213  MFI.getObjectAlignment(FrameIdx));
1214  NewMIs.back()->addMemOperand(MF, MMO);
1215 }
1216 
1217 void PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
1218  unsigned DestReg, int FrameIdx,
1219  const TargetRegisterClass *RC,
1221  const {
1222  unsigned Opcode = getLoadOpcodeForSpill(PPC::NoRegister, RC);
1223  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opcode), DestReg),
1224  FrameIdx));
1225  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1226 
1227  if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1228  PPC::CRBITRCRegClass.hasSubClassEq(RC))
1229  FuncInfo->setSpillsCR();
1230 
1231  if (PPC::VRSAVERCRegClass.hasSubClassEq(RC))
1232  FuncInfo->setSpillsVRSAVE();
1233 
1234  if (isXFormMemOp(Opcode))
1235  FuncInfo->setHasNonRISpills();
1236 }
1237 
1238 void
1241  unsigned DestReg, int FrameIdx,
1242  const TargetRegisterClass *RC,
1243  const TargetRegisterInfo *TRI) const {
1244  MachineFunction &MF = *MBB.getParent();
1246  DebugLoc DL;
1247  if (MI != MBB.end()) DL = MI->getDebugLoc();
1248 
1249  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1250  FuncInfo->setHasSpills();
1251 
1252  // We need to avoid a situation in which the value from a VRRC register is
1253  // spilled using an Altivec instruction and reloaded into a VSRC register
1254  // using a VSX instruction. The issue with this is that the VSX
1255  // load/store instructions swap the doublewords in the vector and the Altivec
1256  // ones don't. The register classes on the spill/reload may be different if
1257  // the register is defined using an Altivec instruction and is then used by a
1258  // VSX instruction.
1259  if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
1260  RC = &PPC::VSRCRegClass;
1261 
1262  LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
1263 
1264  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1265  MBB.insert(MI, NewMIs[i]);
1266 
1267  const MachineFrameInfo &MFI = MF.getFrameInfo();
1269  MachinePointerInfo::getFixedStack(MF, FrameIdx),
1271  MFI.getObjectAlignment(FrameIdx));
1272  NewMIs.back()->addMemOperand(MF, MMO);
1273 }
1274 
1275 bool PPCInstrInfo::
1277  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
1278  if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
1279  Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
1280  else
1281  // Leave the CR# the same, but invert the condition.
1282  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
1283  return false;
1284 }
1285 
1287  unsigned Reg, MachineRegisterInfo *MRI) const {
1288  // For some instructions, it is legal to fold ZERO into the RA register field.
1289  // A zero immediate should always be loaded with a single li.
1290  unsigned DefOpc = DefMI.getOpcode();
1291  if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
1292  return false;
1293  if (!DefMI.getOperand(1).isImm())
1294  return false;
1295  if (DefMI.getOperand(1).getImm() != 0)
1296  return false;
1297 
1298  // Note that we cannot here invert the arguments of an isel in order to fold
1299  // a ZERO into what is presented as the second argument. All we have here
1300  // is the condition bit, and that might come from a CR-logical bit operation.
1301 
1302  const MCInstrDesc &UseMCID = UseMI.getDesc();
1303 
1304  // Only fold into real machine instructions.
1305  if (UseMCID.isPseudo())
1306  return false;
1307 
1308  unsigned UseIdx;
1309  for (UseIdx = 0; UseIdx < UseMI.getNumOperands(); ++UseIdx)
1310  if (UseMI.getOperand(UseIdx).isReg() &&
1311  UseMI.getOperand(UseIdx).getReg() == Reg)
1312  break;
1313 
1314  assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI");
1315  assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
1316 
1317  const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
1318 
1319  // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
1320  // register (which might also be specified as a pointer class kind).
1321  if (UseInfo->isLookupPtrRegClass()) {
1322  if (UseInfo->RegClass /* Kind */ != 1)
1323  return false;
1324  } else {
1325  if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
1326  UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
1327  return false;
1328  }
1329 
1330  // Make sure this is not tied to an output register (or otherwise
1331  // constrained). This is true for ST?UX registers, for example, which
1332  // are tied to their output registers.
1333  if (UseInfo->Constraints != 0)
1334  return false;
1335 
1336  unsigned ZeroReg;
1337  if (UseInfo->isLookupPtrRegClass()) {
1338  bool isPPC64 = Subtarget.isPPC64();
1339  ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
1340  } else {
1341  ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
1342  PPC::ZERO8 : PPC::ZERO;
1343  }
1344 
1345  bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1346  UseMI.getOperand(UseIdx).setReg(ZeroReg);
1347 
1348  if (DeleteDef)
1349  DefMI.eraseFromParent();
1350 
1351  return true;
1352 }
1353 
1355  for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
1356  I != IE; ++I)
1357  if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
1358  return true;
1359  return false;
1360 }
1361 
1362 // We should make sure that, if we're going to predicate both sides of a
1363 // condition (a diamond), that both sides don't define the counter register. We
1364 // can predicate counter-decrement-based branches, but while that predicates
1365 // the branching, it does not predicate the counter decrement. If we tried to
1366 // merge the triangle into one predicated block, we'd decrement the counter
1367 // twice.
1369  unsigned NumT, unsigned ExtraT,
1370  MachineBasicBlock &FMBB,
1371  unsigned NumF, unsigned ExtraF,
1372  BranchProbability Probability) const {
1373  return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
1374 }
1375 
1376 
1378  // The predicated branches are identified by their type, not really by the
1379  // explicit presence of a predicate. Furthermore, some of them can be
1380  // predicated more than once. Because if conversion won't try to predicate
1381  // any instruction which already claims to be predicated (by returning true
1382  // here), always return false. In doing so, we let isPredicable() be the
1383  // final word on whether not the instruction can be (further) predicated.
1384 
1385  return false;
1386 }
1387 
1389  if (!MI.isTerminator())
1390  return false;
1391 
1392  // Conditional branch is a special case.
1393  if (MI.isBranch() && !MI.isBarrier())
1394  return true;
1395 
1396  return !isPredicated(MI);
1397 }
1398 
1400  ArrayRef<MachineOperand> Pred) const {
1401  unsigned OpC = MI.getOpcode();
1402  if (OpC == PPC::BLR || OpC == PPC::BLR8) {
1403  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1404  bool isPPC64 = Subtarget.isPPC64();
1405  MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR)
1406  : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
1407  } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1408  MI.setDesc(get(PPC::BCLR));
1410  .addReg(Pred[1].getReg());
1411  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1412  MI.setDesc(get(PPC::BCLRn));
1414  .addReg(Pred[1].getReg());
1415  } else {
1416  MI.setDesc(get(PPC::BCCLR));
1418  .addImm(Pred[0].getImm())
1419  .addReg(Pred[1].getReg());
1420  }
1421 
1422  return true;
1423  } else if (OpC == PPC::B) {
1424  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1425  bool isPPC64 = Subtarget.isPPC64();
1426  MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
1427  : (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
1428  } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1429  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1430  MI.RemoveOperand(0);
1431 
1432  MI.setDesc(get(PPC::BC));
1434  .addReg(Pred[1].getReg())
1435  .addMBB(MBB);
1436  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1437  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1438  MI.RemoveOperand(0);
1439 
1440  MI.setDesc(get(PPC::BCn));
1442  .addReg(Pred[1].getReg())
1443  .addMBB(MBB);
1444  } else {
1445  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1446  MI.RemoveOperand(0);
1447 
1448  MI.setDesc(get(PPC::BCC));
1450  .addImm(Pred[0].getImm())
1451  .addReg(Pred[1].getReg())
1452  .addMBB(MBB);
1453  }
1454 
1455  return true;
1456  } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 ||
1457  OpC == PPC::BCTRL || OpC == PPC::BCTRL8) {
1458  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
1459  llvm_unreachable("Cannot predicate bctr[l] on the ctr register");
1460 
1461  bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
1462  bool isPPC64 = Subtarget.isPPC64();
1463 
1464  if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1465  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8)
1466  : (setLR ? PPC::BCCTRL : PPC::BCCTR)));
1468  .addReg(Pred[1].getReg());
1469  return true;
1470  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1471  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n)
1472  : (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
1474  .addReg(Pred[1].getReg());
1475  return true;
1476  }
1477 
1478  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8)
1479  : (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
1481  .addImm(Pred[0].getImm())
1482  .addReg(Pred[1].getReg());
1483  return true;
1484  }
1485 
1486  return false;
1487 }
1488 
1490  ArrayRef<MachineOperand> Pred2) const {
1491  assert(Pred1.size() == 2 && "Invalid PPC first predicate");
1492  assert(Pred2.size() == 2 && "Invalid PPC second predicate");
1493 
1494  if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1495  return false;
1496  if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
1497  return false;
1498 
1499  // P1 can only subsume P2 if they test the same condition register.
1500  if (Pred1[1].getReg() != Pred2[1].getReg())
1501  return false;
1502 
1503  PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
1504  PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
1505 
1506  if (P1 == P2)
1507  return true;
1508 
1509  // Does P1 subsume P2, e.g. GE subsumes GT.
1510  if (P1 == PPC::PRED_LE &&
1511  (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
1512  return true;
1513  if (P1 == PPC::PRED_GE &&
1514  (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
1515  return true;
1516 
1517  return false;
1518 }
1519 
1521  std::vector<MachineOperand> &Pred) const {
1522  // Note: At the present time, the contents of Pred from this function is
1523  // unused by IfConversion. This implementation follows ARM by pushing the
1524  // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
1525  // predicate, instructions defining CTR or CTR8 are also included as
1526  // predicate-defining instructions.
1527 
1528  const TargetRegisterClass *RCs[] =
1529  { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1530  &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1531 
1532  bool Found = false;
1533  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1534  const MachineOperand &MO = MI.getOperand(i);
1535  for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
1536  const TargetRegisterClass *RC = RCs[c];
1537  if (MO.isReg()) {
1538  if (MO.isDef() && RC->contains(MO.getReg())) {
1539  Pred.push_back(MO);
1540  Found = true;
1541  }
1542  } else if (MO.isRegMask()) {
1543  for (TargetRegisterClass::iterator I = RC->begin(),
1544  IE = RC->end(); I != IE; ++I)
1545  if (MO.clobbersPhysReg(*I)) {
1546  Pred.push_back(MO);
1547  Found = true;
1548  }
1549  }
1550  }
1551  }
1552 
1553  return Found;
1554 }
1555 
1557  unsigned OpC = MI.getOpcode();
1558  switch (OpC) {
1559  default:
1560  return false;
1561  case PPC::B:
1562  case PPC::BLR:
1563  case PPC::BLR8:
1564  case PPC::BCTR:
1565  case PPC::BCTR8:
1566  case PPC::BCTRL:
1567  case PPC::BCTRL8:
1568  return true;
1569  }
1570 }
1571 
1572 bool PPCInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1573  unsigned &SrcReg2, int &Mask,
1574  int &Value) const {
1575  unsigned Opc = MI.getOpcode();
1576 
1577  switch (Opc) {
1578  default: return false;
1579  case PPC::CMPWI:
1580  case PPC::CMPLWI:
1581  case PPC::CMPDI:
1582  case PPC::CMPLDI:
1583  SrcReg = MI.getOperand(1).getReg();
1584  SrcReg2 = 0;
1585  Value = MI.getOperand(2).getImm();
1586  Mask = 0xFFFF;
1587  return true;
1588  case PPC::CMPW:
1589  case PPC::CMPLW:
1590  case PPC::CMPD:
1591  case PPC::CMPLD:
1592  case PPC::FCMPUS:
1593  case PPC::FCMPUD:
1594  SrcReg = MI.getOperand(1).getReg();
1595  SrcReg2 = MI.getOperand(2).getReg();
1596  Value = 0;
1597  Mask = 0;
1598  return true;
1599  }
1600 }
1601 
1602 bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1603  unsigned SrcReg2, int Mask, int Value,
1604  const MachineRegisterInfo *MRI) const {
1605  if (DisableCmpOpt)
1606  return false;
1607 
1608  int OpC = CmpInstr.getOpcode();
1609  unsigned CRReg = CmpInstr.getOperand(0).getReg();
1610 
1611  // FP record forms set CR1 based on the execption status bits, not a
1612  // comparison with zero.
1613  if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
1614  return false;
1615 
1616  // The record forms set the condition register based on a signed comparison
1617  // with zero (so says the ISA manual). This is not as straightforward as it
1618  // seems, however, because this is always a 64-bit comparison on PPC64, even
1619  // for instructions that are 32-bit in nature (like slw for example).
1620  // So, on PPC32, for unsigned comparisons, we can use the record forms only
1621  // for equality checks (as those don't depend on the sign). On PPC64,
1622  // we are restricted to equality for unsigned 64-bit comparisons and for
1623  // signed 32-bit comparisons the applicability is more restricted.
1624  bool isPPC64 = Subtarget.isPPC64();
1625  bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
1626  bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
1627  bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
1628 
1629  // Get the unique definition of SrcReg.
1630  MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1631  if (!MI) return false;
1632 
1633  bool equalityOnly = false;
1634  bool noSub = false;
1635  if (isPPC64) {
1636  if (is32BitSignedCompare) {
1637  // We can perform this optimization only if MI is sign-extending.
1638  if (isSignExtended(*MI))
1639  noSub = true;
1640  else
1641  return false;
1642  } else if (is32BitUnsignedCompare) {
1643  // We can perform this optimization, equality only, if MI is
1644  // zero-extending.
1645  if (isZeroExtended(*MI)) {
1646  noSub = true;
1647  equalityOnly = true;
1648  } else
1649  return false;
1650  } else
1651  equalityOnly = is64BitUnsignedCompare;
1652  } else
1653  equalityOnly = is32BitUnsignedCompare;
1654 
1655  if (equalityOnly) {
1656  // We need to check the uses of the condition register in order to reject
1657  // non-equality comparisons.
1659  I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1660  I != IE; ++I) {
1661  MachineInstr *UseMI = &*I;
1662  if (UseMI->getOpcode() == PPC::BCC) {
1663  PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
1664  unsigned PredCond = PPC::getPredicateCondition(Pred);
1665  // We ignore hint bits when checking for non-equality comparisons.
1666  if (PredCond != PPC::PRED_EQ && PredCond != PPC::PRED_NE)
1667  return false;
1668  } else if (UseMI->getOpcode() == PPC::ISEL ||
1669  UseMI->getOpcode() == PPC::ISEL8) {
1670  unsigned SubIdx = UseMI->getOperand(3).getSubReg();
1671  if (SubIdx != PPC::sub_eq)
1672  return false;
1673  } else
1674  return false;
1675  }
1676  }
1677 
1678  MachineBasicBlock::iterator I = CmpInstr;
1679 
1680  // Scan forward to find the first use of the compare.
1681  for (MachineBasicBlock::iterator EL = CmpInstr.getParent()->end(); I != EL;
1682  ++I) {
1683  bool FoundUse = false;
1685  J = MRI->use_instr_begin(CRReg), JE = MRI->use_instr_end();
1686  J != JE; ++J)
1687  if (&*J == &*I) {
1688  FoundUse = true;
1689  break;
1690  }
1691 
1692  if (FoundUse)
1693  break;
1694  }
1695 
1698 
1699  // There are two possible candidates which can be changed to set CR[01].
1700  // One is MI, the other is a SUB instruction.
1701  // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
1702  MachineInstr *Sub = nullptr;
1703  if (SrcReg2 != 0)
1704  // MI is not a candidate for CMPrr.
1705  MI = nullptr;
1706  // FIXME: Conservatively refuse to convert an instruction which isn't in the
1707  // same BB as the comparison. This is to allow the check below to avoid calls
1708  // (and other explicit clobbers); instead we should really check for these
1709  // more explicitly (in at least a few predecessors).
1710  else if (MI->getParent() != CmpInstr.getParent())
1711  return false;
1712  else if (Value != 0) {
1713  // The record-form instructions set CR bit based on signed comparison
1714  // against 0. We try to convert a compare against 1 or -1 into a compare
1715  // against 0 to exploit record-form instructions. For example, we change
1716  // the condition "greater than -1" into "greater than or equal to 0"
1717  // and "less than 1" into "less than or equal to 0".
1718 
1719  // Since we optimize comparison based on a specific branch condition,
1720  // we don't optimize if condition code is used by more than once.
1721  if (equalityOnly || !MRI->hasOneUse(CRReg))
1722  return false;
1723 
1724  MachineInstr *UseMI = &*MRI->use_instr_begin(CRReg);
1725  if (UseMI->getOpcode() != PPC::BCC)
1726  return false;
1727 
1728  PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
1729  PPC::Predicate NewPred = Pred;
1730  unsigned PredCond = PPC::getPredicateCondition(Pred);
1731  unsigned PredHint = PPC::getPredicateHint(Pred);
1732  int16_t Immed = (int16_t)Value;
1733 
1734  // When modyfing the condition in the predicate, we propagate hint bits
1735  // from the original predicate to the new one.
1736  if (Immed == -1 && PredCond == PPC::PRED_GT)
1737  // We convert "greater than -1" into "greater than or equal to 0",
1738  // since we are assuming signed comparison by !equalityOnly
1739  NewPred = PPC::getPredicate(PPC::PRED_GE, PredHint);
1740  else if (Immed == -1 && PredCond == PPC::PRED_LE)
1741  // We convert "less than or equal to -1" into "less than 0".
1742  NewPred = PPC::getPredicate(PPC::PRED_LT, PredHint);
1743  else if (Immed == 1 && PredCond == PPC::PRED_LT)
1744  // We convert "less than 1" into "less than or equal to 0".
1745  NewPred = PPC::getPredicate(PPC::PRED_LE, PredHint);
1746  else if (Immed == 1 && PredCond == PPC::PRED_GE)
1747  // We convert "greater than or equal to 1" into "greater than 0".
1748  NewPred = PPC::getPredicate(PPC::PRED_GT, PredHint);
1749  else
1750  return false;
1751 
1752  PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1753  NewPred));
1754  }
1755 
1756  // Search for Sub.
1758  --I;
1759 
1760  // Get ready to iterate backward from CmpInstr.
1761  MachineBasicBlock::iterator E = MI, B = CmpInstr.getParent()->begin();
1762 
1763  for (; I != E && !noSub; --I) {
1764  const MachineInstr &Instr = *I;
1765  unsigned IOpC = Instr.getOpcode();
1766 
1767  if (&*I != &CmpInstr && (Instr.modifiesRegister(PPC::CR0, TRI) ||
1768  Instr.readsRegister(PPC::CR0, TRI)))
1769  // This instruction modifies or uses the record condition register after
1770  // the one we want to change. While we could do this transformation, it
1771  // would likely not be profitable. This transformation removes one
1772  // instruction, and so even forcing RA to generate one move probably
1773  // makes it unprofitable.
1774  return false;
1775 
1776  // Check whether CmpInstr can be made redundant by the current instruction.
1777  if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
1778  OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
1779  (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
1780  ((Instr.getOperand(1).getReg() == SrcReg &&
1781  Instr.getOperand(2).getReg() == SrcReg2) ||
1782  (Instr.getOperand(1).getReg() == SrcReg2 &&
1783  Instr.getOperand(2).getReg() == SrcReg))) {
1784  Sub = &*I;
1785  break;
1786  }
1787 
1788  if (I == B)
1789  // The 'and' is below the comparison instruction.
1790  return false;
1791  }
1792 
1793  // Return false if no candidates exist.
1794  if (!MI && !Sub)
1795  return false;
1796 
1797  // The single candidate is called MI.
1798  if (!MI) MI = Sub;
1799 
1800  int NewOpC = -1;
1801  int MIOpC = MI->getOpcode();
1802  if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8)
1803  NewOpC = MIOpC;
1804  else {
1805  NewOpC = PPC::getRecordFormOpcode(MIOpC);
1806  if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
1807  NewOpC = MIOpC;
1808  }
1809 
1810  // FIXME: On the non-embedded POWER architectures, only some of the record
1811  // forms are fast, and we should use only the fast ones.
1812 
1813  // The defining instruction has a record form (or is already a record
1814  // form). It is possible, however, that we'll need to reverse the condition
1815  // code of the users.
1816  if (NewOpC == -1)
1817  return false;
1818 
1819  // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
1820  // needs to be updated to be based on SUB. Push the condition code
1821  // operands to OperandsToUpdate. If it is safe to remove CmpInstr, the
1822  // condition code of these operands will be modified.
1823  // Here, Value == 0 means we haven't converted comparison against 1 or -1 to
1824  // comparison against 0, which may modify predicate.
1825  bool ShouldSwap = false;
1826  if (Sub && Value == 0) {
1827  ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1828  Sub->getOperand(2).getReg() == SrcReg;
1829 
1830  // The operands to subf are the opposite of sub, so only in the fixed-point
1831  // case, invert the order.
1832  ShouldSwap = !ShouldSwap;
1833  }
1834 
1835  if (ShouldSwap)
1837  I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1838  I != IE; ++I) {
1839  MachineInstr *UseMI = &*I;
1840  if (UseMI->getOpcode() == PPC::BCC) {
1841  PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
1842  unsigned PredCond = PPC::getPredicateCondition(Pred);
1843  assert((!equalityOnly ||
1844  PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE) &&
1845  "Invalid predicate for equality-only optimization");
1846  (void)PredCond; // To suppress warning in release build.
1847  PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1848  PPC::getSwappedPredicate(Pred)));
1849  } else if (UseMI->getOpcode() == PPC::ISEL ||
1850  UseMI->getOpcode() == PPC::ISEL8) {
1851  unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
1852  assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
1853  "Invalid CR bit for equality-only optimization");
1854 
1855  if (NewSubReg == PPC::sub_lt)
1856  NewSubReg = PPC::sub_gt;
1857  else if (NewSubReg == PPC::sub_gt)
1858  NewSubReg = PPC::sub_lt;
1859 
1860  SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)),
1861  NewSubReg));
1862  } else // We need to abort on a user we don't understand.
1863  return false;
1864  }
1865  assert(!(Value != 0 && ShouldSwap) &&
1866  "Non-zero immediate support and ShouldSwap"
1867  "may conflict in updating predicate");
1868 
1869  // Create a new virtual register to hold the value of the CR set by the
1870  // record-form instruction. If the instruction was not previously in
1871  // record form, then set the kill flag on the CR.
1872  CmpInstr.eraseFromParent();
1873 
1875  BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
1876  get(TargetOpcode::COPY), CRReg)
1877  .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
1878 
1879  // Even if CR0 register were dead before, it is alive now since the
1880  // instruction we just built uses it.
1881  MI->clearRegisterDeads(PPC::CR0);
1882 
1883  if (MIOpC != NewOpC) {
1884  // We need to be careful here: we're replacing one instruction with
1885  // another, and we need to make sure that we get all of the right
1886  // implicit uses and defs. On the other hand, the caller may be holding
1887  // an iterator to this instruction, and so we can't delete it (this is
1888  // specifically the case if this is the instruction directly after the
1889  // compare).
1890 
1891  // Rotates are expensive instructions. If we're emitting a record-form
1892  // rotate that can just be an andi, we should just emit the andi.
1893  if ((MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINM8) &&
1894  MI->getOperand(2).getImm() == 0) {
1895  int64_t MB = MI->getOperand(3).getImm();
1896  int64_t ME = MI->getOperand(4).getImm();
1897  if (MB < ME && MB >= 16) {
1898  uint64_t Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
1899  NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDIo : PPC::ANDIo8;
1900  MI->RemoveOperand(4);
1901  MI->RemoveOperand(3);
1902  MI->getOperand(2).setImm(Mask);
1903  NumRcRotatesConvertedToRcAnd++;
1904  }
1905  } else if (MIOpC == PPC::RLDICL && MI->getOperand(2).getImm() == 0) {
1906  int64_t MB = MI->getOperand(3).getImm();
1907  if (MB >= 48) {
1908  uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
1909  NewOpC = PPC::ANDIo8;
1910  MI->RemoveOperand(3);
1911  MI->getOperand(2).setImm(Mask);
1912  NumRcRotatesConvertedToRcAnd++;
1913  }
1914  }
1915 
1916  const MCInstrDesc &NewDesc = get(NewOpC);
1917  MI->setDesc(NewDesc);
1918 
1919  if (NewDesc.ImplicitDefs)
1920  for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs();
1921  *ImpDefs; ++ImpDefs)
1922  if (!MI->definesRegister(*ImpDefs))
1923  MI->addOperand(*MI->getParent()->getParent(),
1924  MachineOperand::CreateReg(*ImpDefs, true, true));
1925  if (NewDesc.ImplicitUses)
1926  for (const MCPhysReg *ImpUses = NewDesc.getImplicitUses();
1927  *ImpUses; ++ImpUses)
1928  if (!MI->readsRegister(*ImpUses))
1929  MI->addOperand(*MI->getParent()->getParent(),
1930  MachineOperand::CreateReg(*ImpUses, false, true));
1931  }
1932  assert(MI->definesRegister(PPC::CR0) &&
1933  "Record-form instruction does not define cr0?");
1934 
1935  // Modify the condition code of operands in OperandsToUpdate.
1936  // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
1937  // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
1938  for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
1939  PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
1940 
1941  for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
1942  SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
1943 
1944  return true;
1945 }
1946 
1947 /// GetInstSize - Return the number of bytes of code the specified
1948 /// instruction may be. This returns the maximum number of bytes.
1949 ///
1951  unsigned Opcode = MI.getOpcode();
1952 
1953  if (Opcode == PPC::INLINEASM) {
1954  const MachineFunction *MF = MI.getParent()->getParent();
1955  const char *AsmStr = MI.getOperand(0).getSymbolName();
1956  return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1957  } else if (Opcode == TargetOpcode::STACKMAP) {
1958  StackMapOpers Opers(&MI);
1959  return Opers.getNumPatchBytes();
1960  } else if (Opcode == TargetOpcode::PATCHPOINT) {
1961  PatchPointOpers Opers(&MI);
1962  return Opers.getNumPatchBytes();
1963  } else {
1964  return get(Opcode).getSize();
1965  }
1966 }
1967 
1968 std::pair<unsigned, unsigned>
1970  const unsigned Mask = PPCII::MO_ACCESS_MASK;
1971  return std::make_pair(TF & Mask, TF & ~Mask);
1972 }
1973 
1976  using namespace PPCII;
1977  static const std::pair<unsigned, const char *> TargetFlags[] = {
1978  {MO_LO, "ppc-lo"},
1979  {MO_HA, "ppc-ha"},
1980  {MO_TPREL_LO, "ppc-tprel-lo"},
1981  {MO_TPREL_HA, "ppc-tprel-ha"},
1982  {MO_DTPREL_LO, "ppc-dtprel-lo"},
1983  {MO_TLSLD_LO, "ppc-tlsld-lo"},
1984  {MO_TOC_LO, "ppc-toc-lo"},
1985  {MO_TLS, "ppc-tls"}};
1986  return makeArrayRef(TargetFlags);
1987 }
1988 
1991  using namespace PPCII;
1992  static const std::pair<unsigned, const char *> TargetFlags[] = {
1993  {MO_PLT, "ppc-plt"},
1994  {MO_PIC_FLAG, "ppc-pic"},
1995  {MO_NLP_FLAG, "ppc-nlp"},
1996  {MO_NLP_HIDDEN_FLAG, "ppc-nlp-hidden"}};
1997  return makeArrayRef(TargetFlags);
1998 }
1999 
2000 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
2001 // The VSX versions have the advantage of a full 64-register target whereas
2002 // the FP ones have the advantage of lower latency and higher throughput. So
2003 // what we are after is using the faster instructions in low register pressure
2004 // situations and using the larger register file in high register pressure
2005 // situations.
2007  unsigned UpperOpcode, LowerOpcode;
2008  switch (MI.getOpcode()) {
2009  case PPC::DFLOADf32:
2010  UpperOpcode = PPC::LXSSP;
2011  LowerOpcode = PPC::LFS;
2012  break;
2013  case PPC::DFLOADf64:
2014  UpperOpcode = PPC::LXSD;
2015  LowerOpcode = PPC::LFD;
2016  break;
2017  case PPC::DFSTOREf32:
2018  UpperOpcode = PPC::STXSSP;
2019  LowerOpcode = PPC::STFS;
2020  break;
2021  case PPC::DFSTOREf64:
2022  UpperOpcode = PPC::STXSD;
2023  LowerOpcode = PPC::STFD;
2024  break;
2025  case PPC::XFLOADf32:
2026  UpperOpcode = PPC::LXSSPX;
2027  LowerOpcode = PPC::LFSX;
2028  break;
2029  case PPC::XFLOADf64:
2030  UpperOpcode = PPC::LXSDX;
2031  LowerOpcode = PPC::LFDX;
2032  break;
2033  case PPC::XFSTOREf32:
2034  UpperOpcode = PPC::STXSSPX;
2035  LowerOpcode = PPC::STFSX;
2036  break;
2037  case PPC::XFSTOREf64:
2038  UpperOpcode = PPC::STXSDX;
2039  LowerOpcode = PPC::STFDX;
2040  break;
2041  case PPC::LIWAX:
2042  UpperOpcode = PPC::LXSIWAX;
2043  LowerOpcode = PPC::LFIWAX;
2044  break;
2045  case PPC::LIWZX:
2046  UpperOpcode = PPC::LXSIWZX;
2047  LowerOpcode = PPC::LFIWZX;
2048  break;
2049  case PPC::STIWX:
2050  UpperOpcode = PPC::STXSIWX;
2051  LowerOpcode = PPC::STFIWX;
2052  break;
2053  default:
2054  llvm_unreachable("Unknown Operation!");
2055  }
2056 
2057  unsigned TargetReg = MI.getOperand(0).getReg();
2058  unsigned Opcode;
2059  if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) ||
2060  (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31))
2061  Opcode = LowerOpcode;
2062  else
2063  Opcode = UpperOpcode;
2064  MI.setDesc(get(Opcode));
2065  return true;
2066 }
2067 
2069  auto &MBB = *MI.getParent();
2070  auto DL = MI.getDebugLoc();
2071 
2072  switch (MI.getOpcode()) {
2073  case TargetOpcode::LOAD_STACK_GUARD: {
2074  assert(Subtarget.isTargetLinux() &&
2075  "Only Linux target is expected to contain LOAD_STACK_GUARD");
2076  const int64_t Offset = Subtarget.isPPC64() ? -0x7010 : -0x7008;
2077  const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2;
2078  MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ));
2080  .addImm(Offset)
2081  .addReg(Reg);
2082  return true;
2083  }
2084  case PPC::DFLOADf32:
2085  case PPC::DFLOADf64:
2086  case PPC::DFSTOREf32:
2087  case PPC::DFSTOREf64: {
2088  assert(Subtarget.hasP9Vector() &&
2089  "Invalid D-Form Pseudo-ops on Pre-P9 target.");
2090  assert(MI.getOperand(2).isReg() && MI.getOperand(1).isImm() &&
2091  "D-form op must have register and immediate operands");
2092  return expandVSXMemPseudo(MI);
2093  }
2094  case PPC::XFLOADf32:
2095  case PPC::XFSTOREf32:
2096  case PPC::LIWAX:
2097  case PPC::LIWZX:
2098  case PPC::STIWX: {
2099  assert(Subtarget.hasP8Vector() &&
2100  "Invalid X-Form Pseudo-ops on Pre-P8 target.");
2101  assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
2102  "X-form op must have register and register operands");
2103  return expandVSXMemPseudo(MI);
2104  }
2105  case PPC::XFLOADf64:
2106  case PPC::XFSTOREf64: {
2107  assert(Subtarget.hasVSX() &&
2108  "Invalid X-Form Pseudo-ops on target that has no VSX.");
2109  assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
2110  "X-form op must have register and register operands");
2111  return expandVSXMemPseudo(MI);
2112  }
2113  case PPC::SPILLTOVSR_LD: {
2114  unsigned TargetReg = MI.getOperand(0).getReg();
2115  if (PPC::VSFRCRegClass.contains(TargetReg)) {
2116  MI.setDesc(get(PPC::DFLOADf64));
2117  return expandPostRAPseudo(MI);
2118  }
2119  else
2120  MI.setDesc(get(PPC::LD));
2121  return true;
2122  }
2123  case PPC::SPILLTOVSR_ST: {
2124  unsigned SrcReg = MI.getOperand(0).getReg();
2125  if (PPC::VSFRCRegClass.contains(SrcReg)) {
2126  NumStoreSPILLVSRRCAsVec++;
2127  MI.setDesc(get(PPC::DFSTOREf64));
2128  return expandPostRAPseudo(MI);
2129  } else {
2130  NumStoreSPILLVSRRCAsGpr++;
2131  MI.setDesc(get(PPC::STD));
2132  }
2133  return true;
2134  }
2135  case PPC::SPILLTOVSR_LDX: {
2136  unsigned TargetReg = MI.getOperand(0).getReg();
2137  if (PPC::VSFRCRegClass.contains(TargetReg))
2138  MI.setDesc(get(PPC::LXSDX));
2139  else
2140  MI.setDesc(get(PPC::LDX));
2141  return true;
2142  }
2143  case PPC::SPILLTOVSR_STX: {
2144  unsigned SrcReg = MI.getOperand(0).getReg();
2145  if (PPC::VSFRCRegClass.contains(SrcReg)) {
2146  NumStoreSPILLVSRRCAsVec++;
2147  MI.setDesc(get(PPC::STXSDX));
2148  } else {
2149  NumStoreSPILLVSRRCAsGpr++;
2150  MI.setDesc(get(PPC::STDX));
2151  }
2152  return true;
2153  }
2154 
2155  case PPC::CFENCE8: {
2156  auto Val = MI.getOperand(0).getReg();
2157  BuildMI(MBB, MI, DL, get(PPC::CMPD), PPC::CR7).addReg(Val).addReg(Val);
2158  BuildMI(MBB, MI, DL, get(PPC::CTRL_DEP))
2160  .addReg(PPC::CR7)
2161  .addImm(1);
2162  MI.setDesc(get(PPC::ISYNC));
2163  MI.RemoveOperand(0);
2164  return true;
2165  }
2166  }
2167  return false;
2168 }
2169 
2170 // Essentially a compile-time implementation of a compare->isel sequence.
2171 // It takes two constants to compare, along with the true/false registers
2172 // and the comparison type (as a subreg to a CR field) and returns one
2173 // of the true/false registers, depending on the comparison results.
2174 static unsigned selectReg(int64_t Imm1, int64_t Imm2, unsigned CompareOpc,
2175  unsigned TrueReg, unsigned FalseReg,
2176  unsigned CRSubReg) {
2177  // Signed comparisons. The immediates are assumed to be sign-extended.
2178  if (CompareOpc == PPC::CMPWI || CompareOpc == PPC::CMPDI) {
2179  switch (CRSubReg) {
2180  default: llvm_unreachable("Unknown integer comparison type.");
2181  case PPC::sub_lt:
2182  return Imm1 < Imm2 ? TrueReg : FalseReg;
2183  case PPC::sub_gt:
2184  return Imm1 > Imm2 ? TrueReg : FalseReg;
2185  case PPC::sub_eq:
2186  return Imm1 == Imm2 ? TrueReg : FalseReg;
2187  }
2188  }
2189  // Unsigned comparisons.
2190  else if (CompareOpc == PPC::CMPLWI || CompareOpc == PPC::CMPLDI) {
2191  switch (CRSubReg) {
2192  default: llvm_unreachable("Unknown integer comparison type.");
2193  case PPC::sub_lt:
2194  return (uint64_t)Imm1 < (uint64_t)Imm2 ? TrueReg : FalseReg;
2195  case PPC::sub_gt:
2196  return (uint64_t)Imm1 > (uint64_t)Imm2 ? TrueReg : FalseReg;
2197  case PPC::sub_eq:
2198  return Imm1 == Imm2 ? TrueReg : FalseReg;
2199  }
2200  }
2201  return PPC::NoRegister;
2202 }
2203 
2204 // Replace an instruction with one that materializes a constant (and sets
2205 // CR0 if the original instruction was a record-form instruction).
2207  const LoadImmediateInfo &LII) const {
2208  // Remove existing operands.
2209  int OperandToKeep = LII.SetCR ? 1 : 0;
2210  for (int i = MI.getNumOperands() - 1; i > OperandToKeep; i--)
2211  MI.RemoveOperand(i);
2212 
2213  // Replace the instruction.
2214  if (LII.SetCR) {
2215  MI.setDesc(get(LII.Is64Bit ? PPC::ANDIo8 : PPC::ANDIo));
2216  // Set the immediate.
2218  .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine);
2219  return;
2220  }
2221  else
2222  MI.setDesc(get(LII.Is64Bit ? PPC::LI8 : PPC::LI));
2223 
2224  // Set the immediate.
2226  .addImm(LII.Imm);
2227 }
2228 
2229 MachineInstr *PPCInstrInfo::getConstantDefMI(MachineInstr &MI,
2230  unsigned &ConstOp,
2231  bool &SeenIntermediateUse) const {
2232  ConstOp = ~0U;
2233  MachineInstr *DefMI = nullptr;
2236  // If we'ere in SSA, get the defs through the MRI. Otherwise, only look
2237  // within the basic block to see if the register is defined using an LI/LI8.
2238  if (MRI->isSSA()) {
2239  for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
2240  if (!MI.getOperand(i).isReg())
2241  continue;
2242  unsigned Reg = MI.getOperand(i).getReg();
2244  continue;
2245  unsigned TrueReg = TRI->lookThruCopyLike(Reg, MRI);
2247  DefMI = MRI->getVRegDef(TrueReg);
2248  if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8) {
2249  ConstOp = i;
2250  break;
2251  }
2252  }
2253  }
2254  } else {
2255  // Looking back through the definition for each operand could be expensive,
2256  // so exit early if this isn't an instruction that either has an immediate
2257  // form or is already an immediate form that we can handle.
2258  ImmInstrInfo III;
2259  unsigned Opc = MI.getOpcode();
2260  bool ConvertibleImmForm =
2261  Opc == PPC::CMPWI || Opc == PPC::CMPLWI ||
2262  Opc == PPC::CMPDI || Opc == PPC::CMPLDI ||
2263  Opc == PPC::ADDI || Opc == PPC::ADDI8 ||
2264  Opc == PPC::ORI || Opc == PPC::ORI8 ||
2265  Opc == PPC::XORI || Opc == PPC::XORI8 ||
2266  Opc == PPC::RLDICL || Opc == PPC::RLDICLo ||
2267  Opc == PPC::RLDICL_32 || Opc == PPC::RLDICL_32_64 ||
2268  Opc == PPC::RLWINM || Opc == PPC::RLWINMo ||
2269  Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
2270  if (!instrHasImmForm(MI, III) && !ConvertibleImmForm)
2271  return nullptr;
2272 
2273  // Don't convert or %X, %Y, %Y since that's just a register move.
2274  if ((Opc == PPC::OR || Opc == PPC::OR8) &&
2275  MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
2276  return nullptr;
2277  for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
2278  MachineOperand &MO = MI.getOperand(i);
2279  SeenIntermediateUse = false;
2280  if (MO.isReg() && MO.isUse() && !MO.isImplicit()) {
2282  It++;
2283  unsigned Reg = MI.getOperand(i).getReg();
2284  // MachineInstr::readsRegister only returns true if the machine
2285  // instruction reads the exact register or its super-register. It
2286  // does not consider uses of sub-registers which seems like strange
2287  // behaviour. Nonetheless, if we end up with a 64-bit register here,
2288  // get the corresponding 32-bit register to check.
2289  if (PPC::G8RCRegClass.contains(Reg))
2290  Reg = Reg - PPC::X0 + PPC::R0;
2291 
2292  // Is this register defined by a load-immediate in this block?
2293  for ( ; It != E; ++It) {
2294  if (It->modifiesRegister(Reg, &getRegisterInfo())) {
2295  if (It->getOpcode() == PPC::LI || It->getOpcode() == PPC::LI8) {
2296  ConstOp = i;
2297  return &*It;
2298  } else
2299  break;
2300  } else if (It->readsRegister(Reg, &getRegisterInfo()))
2301  // If we see another use of this reg between the def and the MI,
2302  // we want to flat it so the def isn't deleted.
2303  SeenIntermediateUse = true;
2304  }
2305  }
2306  }
2307  }
2308  return ConstOp == ~0U ? nullptr : DefMI;
2309 }
2310 
2311 const unsigned *PPCInstrInfo::getStoreOpcodesForSpillArray() const {
2312  static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = {
2313  // Power 8
2314  {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
2315  PPC::SPILL_CRBIT, PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX,
2316  PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb,
2317  PPC::SPILLTOVSR_ST},
2318  // Power 9
2319  {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
2320  PPC::SPILL_CRBIT, PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32,
2321  PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb,
2322  PPC::SPILLTOVSR_ST}};
2323 
2324  return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0];
2325 }
2326 
2327 const unsigned *PPCInstrInfo::getLoadOpcodesForSpillArray() const {
2328  static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = {
2329  // Power 8
2330  {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
2331  PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX,
2332  PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
2333  PPC::SPILLTOVSR_LD},
2334  // Power 9
2335  {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
2336  PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, PPC::DFLOADf32,
2337  PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
2338  PPC::SPILLTOVSR_LD}};
2339 
2340  return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0];
2341 }
2342 
2343 // If this instruction has an immediate form and one of its operands is a
2344 // result of a load-immediate, convert it to the immediate form if the constant
2345 // is in range.
2347  MachineInstr **KilledDef) const {
2348  MachineFunction *MF = MI.getParent()->getParent();
2350  bool PostRA = !MRI->isSSA();
2351  bool SeenIntermediateUse = true;
2352  unsigned ConstantOperand = ~0U;
2353  MachineInstr *DefMI = getConstantDefMI(MI, ConstantOperand,
2354  SeenIntermediateUse);
2355  if (!DefMI || !DefMI->getOperand(1).isImm())
2356  return false;
2357  assert(ConstantOperand < MI.getNumOperands() &&
2358  "The constant operand needs to be valid at this point");
2359 
2360  int64_t Immediate = DefMI->getOperand(1).getImm();
2361  // Sign-extend to 64-bits.
2362  int64_t SExtImm = ((uint64_t)Immediate & ~0x7FFFuLL) != 0 ?
2363  (Immediate | 0xFFFFFFFFFFFF0000) : Immediate;
2364 
2365  if (KilledDef && MI.getOperand(ConstantOperand).isKill() &&
2366  !SeenIntermediateUse)
2367  *KilledDef = DefMI;
2368 
2369  // If this is a reg+reg instruction that has a reg+imm form, convert it now.
2370  ImmInstrInfo III;
2371  if (instrHasImmForm(MI, III))
2372  return transformToImmForm(MI, III, ConstantOperand, SExtImm);
2373 
2374  bool ReplaceWithLI = false;
2375  bool Is64BitLI = false;
2376  int64_t NewImm = 0;
2377  bool SetCR = false;
2378  unsigned Opc = MI.getOpcode();
2379  switch (Opc) {
2380  default: return false;
2381 
2382  // FIXME: Any branches conditional on such a comparison can be made
2383  // unconditional. At this time, this happens too infrequently to be worth
2384  // the implementation effort, but if that ever changes, we could convert
2385  // such a pattern here.
2386  case PPC::CMPWI:
2387  case PPC::CMPLWI:
2388  case PPC::CMPDI:
2389  case PPC::CMPLDI: {
2390  // Doing this post-RA would require dataflow analysis to reliably find uses
2391  // of the CR register set by the compare.
2392  if (PostRA)
2393  return false;
2394  // If a compare-immediate is fed by an immediate and is itself an input of
2395  // an ISEL (the most common case) into a COPY of the correct register.
2396  bool Changed = false;
2397  unsigned DefReg = MI.getOperand(0).getReg();
2398  int64_t Comparand = MI.getOperand(2).getImm();
2399  int64_t SExtComparand = ((uint64_t)Comparand & ~0x7FFFuLL) != 0 ?
2400  (Comparand | 0xFFFFFFFFFFFF0000) : Comparand;
2401 
2402  for (auto &CompareUseMI : MRI->use_instructions(DefReg)) {
2403  unsigned UseOpc = CompareUseMI.getOpcode();
2404  if (UseOpc != PPC::ISEL && UseOpc != PPC::ISEL8)
2405  continue;
2406  unsigned CRSubReg = CompareUseMI.getOperand(3).getSubReg();
2407  unsigned TrueReg = CompareUseMI.getOperand(1).getReg();
2408  unsigned FalseReg = CompareUseMI.getOperand(2).getReg();
2409  unsigned RegToCopy = selectReg(SExtImm, SExtComparand, Opc, TrueReg,
2410  FalseReg, CRSubReg);
2411  if (RegToCopy == PPC::NoRegister)
2412  continue;
2413  // Can't use PPC::COPY to copy PPC::ZERO[8]. Convert it to LI[8] 0.
2414  if (RegToCopy == PPC::ZERO || RegToCopy == PPC::ZERO8) {
2415  CompareUseMI.setDesc(get(UseOpc == PPC::ISEL8 ? PPC::LI8 : PPC::LI));
2416  CompareUseMI.getOperand(1).ChangeToImmediate(0);
2417  CompareUseMI.RemoveOperand(3);
2418  CompareUseMI.RemoveOperand(2);
2419  continue;
2420  }
2421  LLVM_DEBUG(
2422  dbgs() << "Found LI -> CMPI -> ISEL, replacing with a copy.\n");
2423  LLVM_DEBUG(DefMI->dump(); MI.dump(); CompareUseMI.dump());
2424  LLVM_DEBUG(dbgs() << "Is converted to:\n");
2425  // Convert to copy and remove unneeded operands.
2426  CompareUseMI.setDesc(get(PPC::COPY));
2427  CompareUseMI.RemoveOperand(3);
2428  CompareUseMI.RemoveOperand(RegToCopy == TrueReg ? 2 : 1);
2429  CmpIselsConverted++;
2430  Changed = true;
2431  LLVM_DEBUG(CompareUseMI.dump());
2432  }
2433  if (Changed)
2434  return true;
2435  // This may end up incremented multiple times since this function is called
2436  // during a fixed-point transformation, but it is only meant to indicate the
2437  // presence of this opportunity.
2438  MissedConvertibleImmediateInstrs++;
2439  return false;
2440  }
2441 
2442  // Immediate forms - may simply be convertable to an LI.
2443  case PPC::ADDI:
2444  case PPC::ADDI8: {
2445  // Does the sum fit in a 16-bit signed field?
2446  int64_t Addend = MI.getOperand(2).getImm();
2447  if (isInt<16>(Addend + SExtImm)) {
2448  ReplaceWithLI = true;
2449  Is64BitLI = Opc == PPC::ADDI8;
2450  NewImm = Addend + SExtImm;
2451  break;
2452  }
2453  return false;
2454  }
2455  case PPC::RLDICL:
2456  case PPC::RLDICLo:
2457  case PPC::RLDICL_32:
2458  case PPC::RLDICL_32_64: {
2459  // Use APInt's rotate function.
2460  int64_t SH = MI.getOperand(2).getImm();
2461  int64_t MB = MI.getOperand(3).getImm();
2462  APInt InVal((Opc == PPC::RLDICL || Opc == PPC::RLDICLo) ?
2463  64 : 32, SExtImm, true);
2464  InVal = InVal.rotl(SH);
2465  uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
2466  InVal &= Mask;
2467  // Can't replace negative values with an LI as that will sign-extend
2468  // and not clear the left bits. If we're setting the CR bit, we will use
2469  // ANDIo which won't sign extend, so that's safe.
2470  if (isUInt<15>(InVal.getSExtValue()) ||
2471  (Opc == PPC::RLDICLo && isUInt<16>(InVal.getSExtValue()))) {
2472  ReplaceWithLI = true;
2473  Is64BitLI = Opc != PPC::RLDICL_32;
2474  NewImm = InVal.getSExtValue();
2475  SetCR = Opc == PPC::RLDICLo;
2476  if (SetCR && (SExtImm & NewImm) != NewImm)
2477  return false;
2478  break;
2479  }
2480  return false;
2481  }
2482  case PPC::RLWINM:
2483  case PPC::RLWINM8:
2484  case PPC::RLWINMo:
2485  case PPC::RLWINM8o: {
2486  int64_t SH = MI.getOperand(2).getImm();
2487  int64_t MB = MI.getOperand(3).getImm();
2488  int64_t ME = MI.getOperand(4).getImm();
2489  APInt InVal(32, SExtImm, true);
2490  InVal = InVal.rotl(SH);
2491  // Set the bits ( MB + 32 ) to ( ME + 32 ).
2492  uint64_t Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
2493  InVal &= Mask;
2494  // Can't replace negative values with an LI as that will sign-extend
2495  // and not clear the left bits. If we're setting the CR bit, we will use
2496  // ANDIo which won't sign extend, so that's safe.
2497  bool ValueFits = isUInt<15>(InVal.getSExtValue());
2498  ValueFits |= ((Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o) &&
2499  isUInt<16>(InVal.getSExtValue()));
2500  if (ValueFits) {
2501  ReplaceWithLI = true;
2502  Is64BitLI = Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
2503  NewImm = InVal.getSExtValue();
2504  SetCR = Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o;
2505  if (SetCR && (SExtImm & NewImm) != NewImm)
2506  return false;
2507  break;
2508  }
2509  return false;
2510  }
2511  case PPC::ORI:
2512  case PPC::ORI8:
2513  case PPC::XORI:
2514  case PPC::XORI8: {
2515  int64_t LogicalImm = MI.getOperand(2).getImm();
2516  int64_t Result = 0;
2517  if (Opc == PPC::ORI || Opc == PPC::ORI8)
2518  Result = LogicalImm | SExtImm;
2519  else
2520  Result = LogicalImm ^ SExtImm;
2521  if (isInt<16>(Result)) {
2522  ReplaceWithLI = true;
2523  Is64BitLI = Opc == PPC::ORI8 || Opc == PPC::XORI8;
2524  NewImm = Result;
2525  break;
2526  }
2527  return false;
2528  }
2529  }
2530 
2531  if (ReplaceWithLI) {
2532  LLVM_DEBUG(dbgs() << "Replacing instruction:\n");
2533  LLVM_DEBUG(MI.dump());
2534  LLVM_DEBUG(dbgs() << "Fed by:\n");
2535  LLVM_DEBUG(DefMI->dump());
2536  LoadImmediateInfo LII;
2537  LII.Imm = NewImm;
2538  LII.Is64Bit = Is64BitLI;
2539  LII.SetCR = SetCR;
2540  // If we're setting the CR, the original load-immediate must be kept (as an
2541  // operand to ANDIo/ANDI8o).
2542  if (KilledDef && SetCR)
2543  *KilledDef = nullptr;
2544  replaceInstrWithLI(MI, LII);
2545  LLVM_DEBUG(dbgs() << "With:\n");
2546  LLVM_DEBUG(MI.dump());
2547  return true;
2548  }
2549  return false;
2550 }
2551 
2553  ImmInstrInfo &III) const {
2554  unsigned Opc = MI.getOpcode();
2555  // The vast majority of the instructions would need their operand 2 replaced
2556  // with an immediate when switching to the reg+imm form. A marked exception
2557  // are the update form loads/stores for which a constant operand 2 would need
2558  // to turn into a displacement and move operand 1 to the operand 2 position.
2559  III.ImmOpNo = 2;
2560  III.ConstantOpNo = 2;
2561  III.ImmWidth = 16;
2562  III.ImmMustBeMultipleOf = 1;
2563  III.TruncateImmTo = 0;
2564  switch (Opc) {
2565  default: return false;
2566  case PPC::ADD4:
2567  case PPC::ADD8:
2568  III.SignedImm = true;
2569  III.ZeroIsSpecialOrig = 0;
2570  III.ZeroIsSpecialNew = 1;
2571  III.IsCommutative = true;
2572  III.ImmOpcode = Opc == PPC::ADD4 ? PPC::ADDI : PPC::ADDI8;
2573  break;
2574  case PPC::ADDC:
2575  case PPC::ADDC8:
2576  III.SignedImm = true;
2577  III.ZeroIsSpecialOrig = 0;
2578  III.ZeroIsSpecialNew = 0;
2579  III.IsCommutative = true;
2580  III.ImmOpcode = Opc == PPC::ADDC ? PPC::ADDIC : PPC::ADDIC8;
2581  break;
2582  case PPC::ADDCo:
2583  III.SignedImm = true;
2584  III.ZeroIsSpecialOrig = 0;
2585  III.ZeroIsSpecialNew = 0;
2586  III.IsCommutative = true;
2587  III.ImmOpcode = PPC::ADDICo;
2588  break;
2589  case PPC::SUBFC:
2590  case PPC::SUBFC8:
2591  III.SignedImm = true;
2592  III.ZeroIsSpecialOrig = 0;
2593  III.ZeroIsSpecialNew = 0;
2594  III.IsCommutative = false;
2595  III.ImmOpcode = Opc == PPC::SUBFC ? PPC::SUBFIC : PPC::SUBFIC8;
2596  break;
2597  case PPC::CMPW:
2598  case PPC::CMPD:
2599  III.SignedImm = true;
2600  III.ZeroIsSpecialOrig = 0;
2601  III.ZeroIsSpecialNew = 0;
2602  III.IsCommutative = false;
2603  III.ImmOpcode = Opc == PPC::CMPW ? PPC::CMPWI : PPC::CMPDI;
2604  break;
2605  case PPC::CMPLW:
2606  case PPC::CMPLD:
2607  III.SignedImm = false;
2608  III.ZeroIsSpecialOrig = 0;
2609  III.ZeroIsSpecialNew = 0;
2610  III.IsCommutative = false;
2611  III.ImmOpcode = Opc == PPC::CMPLW ? PPC::CMPLWI : PPC::CMPLDI;
2612  break;
2613  case PPC::ANDo:
2614  case PPC::AND8o:
2615  case PPC::OR:
2616  case PPC::OR8:
2617  case PPC::XOR:
2618  case PPC::XOR8:
2619  III.SignedImm = false;
2620  III.ZeroIsSpecialOrig = 0;
2621  III.ZeroIsSpecialNew = 0;
2622  III.IsCommutative = true;
2623  switch(Opc) {
2624  default: llvm_unreachable("Unknown opcode");
2625  case PPC::ANDo: III.ImmOpcode = PPC::ANDIo; break;
2626  case PPC::AND8o: III.ImmOpcode = PPC::ANDIo8; break;
2627  case PPC::OR: III.ImmOpcode = PPC::ORI; break;
2628  case PPC::OR8: III.ImmOpcode = PPC::ORI8; break;
2629  case PPC::XOR: III.ImmOpcode = PPC::XORI; break;
2630  case PPC::XOR8: III.ImmOpcode = PPC::XORI8; break;
2631  }
2632  break;
2633  case PPC::RLWNM:
2634  case PPC::RLWNM8:
2635  case PPC::RLWNMo:
2636  case PPC::RLWNM8o:
2637  case PPC::SLW:
2638  case PPC::SLW8:
2639  case PPC::SLWo:
2640  case PPC::SLW8o:
2641  case PPC::SRW:
2642  case PPC::SRW8:
2643  case PPC::SRWo:
2644  case PPC::SRW8o:
2645  case PPC::SRAW:
2646  case PPC::SRAWo:
2647  III.SignedImm = false;
2648  III.ZeroIsSpecialOrig = 0;
2649  III.ZeroIsSpecialNew = 0;
2650  III.IsCommutative = false;
2651  // This isn't actually true, but the instructions ignore any of the
2652  // upper bits, so any immediate loaded with an LI is acceptable.
2653  // This does not apply to shift right algebraic because a value
2654  // out of range will produce a -1/0.
2655  III.ImmWidth = 16;
2656  if (Opc == PPC::RLWNM || Opc == PPC::RLWNM8 ||
2657  Opc == PPC::RLWNMo || Opc == PPC::RLWNM8o)
2658  III.TruncateImmTo = 5;
2659  else
2660  III.TruncateImmTo = 6;
2661  switch(Opc) {
2662  default: llvm_unreachable("Unknown opcode");
2663  case PPC::RLWNM: III.ImmOpcode = PPC::RLWINM; break;
2664  case PPC::RLWNM8: III.ImmOpcode = PPC::RLWINM8; break;
2665  case PPC::RLWNMo: III.ImmOpcode = PPC::RLWINMo; break;
2666  case PPC::RLWNM8o: III.ImmOpcode = PPC::RLWINM8o; break;
2667  case PPC::SLW: III.ImmOpcode = PPC::RLWINM; break;
2668  case PPC::SLW8: III.ImmOpcode = PPC::RLWINM8; break;
2669  case PPC::SLWo: III.ImmOpcode = PPC::RLWINMo; break;
2670  case PPC::SLW8o: III.ImmOpcode = PPC::RLWINM8o; break;
2671  case PPC::SRW: III.ImmOpcode = PPC::RLWINM; break;
2672  case PPC::SRW8: III.ImmOpcode = PPC::RLWINM8; break;
2673  case PPC::SRWo: III.ImmOpcode = PPC::RLWINMo; break;
2674  case PPC::SRW8o: III.ImmOpcode = PPC::RLWINM8o; break;
2675  case PPC::SRAW:
2676  III.ImmWidth = 5;
2677  III.TruncateImmTo = 0;
2678  III.ImmOpcode = PPC::SRAWI;
2679  break;
2680  case PPC::SRAWo:
2681  III.ImmWidth = 5;
2682  III.TruncateImmTo = 0;
2683  III.ImmOpcode = PPC::SRAWIo;
2684  break;
2685  }
2686  break;
2687  case PPC::RLDCL:
2688  case PPC::RLDCLo:
2689  case PPC::RLDCR:
2690  case PPC::RLDCRo:
2691  case PPC::SLD:
2692  case PPC::SLDo:
2693  case PPC::SRD:
2694  case PPC::SRDo:
2695  case PPC::SRAD:
2696  case PPC::SRADo:
2697  III.SignedImm = false;
2698  III.ZeroIsSpecialOrig = 0;
2699  III.ZeroIsSpecialNew = 0;
2700  III.IsCommutative = false;
2701  // This isn't actually true, but the instructions ignore any of the
2702  // upper bits, so any immediate loaded with an LI is acceptable.
2703  // This does not apply to shift right algebraic because a value
2704  // out of range will produce a -1/0.
2705  III.ImmWidth = 16;
2706  if (Opc == PPC::RLDCL || Opc == PPC::RLDCLo ||
2707  Opc == PPC::RLDCR || Opc == PPC::RLDCRo)
2708  III.TruncateImmTo = 6;
2709  else
2710  III.TruncateImmTo = 7;
2711  switch(Opc) {
2712  default: llvm_unreachable("Unknown opcode");
2713  case PPC::RLDCL: III.ImmOpcode = PPC::RLDICL; break;
2714  case PPC::RLDCLo: III.ImmOpcode = PPC::RLDICLo; break;
2715  case PPC::RLDCR: III.ImmOpcode = PPC::RLDICR; break;
2716  case PPC::RLDCRo: III.ImmOpcode = PPC::RLDICRo; break;
2717  case PPC::SLD: III.ImmOpcode = PPC::RLDICR; break;
2718  case PPC::SLDo: III.ImmOpcode = PPC::RLDICRo; break;
2719  case PPC::SRD: III.ImmOpcode = PPC::RLDICL; break;
2720  case PPC::SRDo: III.ImmOpcode = PPC::RLDICLo; break;
2721  case PPC::SRAD:
2722  III.ImmWidth = 6;
2723  III.TruncateImmTo = 0;
2724  III.ImmOpcode = PPC::SRADI;
2725  break;
2726  case PPC::SRADo:
2727  III.ImmWidth = 6;
2728  III.TruncateImmTo = 0;
2729  III.ImmOpcode = PPC::SRADIo;
2730  break;
2731  }
2732  break;
2733  // Loads and stores:
2734  case PPC::LBZX:
2735  case PPC::LBZX8:
2736  case PPC::LHZX:
2737  case PPC::LHZX8:
2738  case PPC::LHAX:
2739  case PPC::LHAX8:
2740  case PPC::LWZX:
2741  case PPC::LWZX8:
2742  case PPC::LWAX:
2743  case PPC::LDX:
2744  case PPC::LFSX:
2745  case PPC::LFDX:
2746  case PPC::STBX:
2747  case PPC::STBX8:
2748  case PPC::STHX:
2749  case PPC::STHX8:
2750  case PPC::STWX:
2751  case PPC::STWX8:
2752  case PPC::STDX:
2753  case PPC::STFSX:
2754  case PPC::STFDX:
2755  III.SignedImm = true;
2756  III.ZeroIsSpecialOrig = 1;
2757  III.ZeroIsSpecialNew = 2;
2758  III.IsCommutative = true;
2759  III.ImmOpNo = 1;
2760  III.ConstantOpNo = 2;
2761  switch(Opc) {
2762  default: llvm_unreachable("Unknown opcode");
2763  case PPC::LBZX: III.ImmOpcode = PPC::LBZ; break;
2764  case PPC::LBZX8: III.ImmOpcode = PPC::LBZ8; break;
2765  case PPC::LHZX: III.ImmOpcode = PPC::LHZ; break;
2766  case PPC::LHZX8: III.ImmOpcode = PPC::LHZ8; break;
2767  case PPC::LHAX: III.ImmOpcode = PPC::LHA; break;
2768  case PPC::LHAX8: III.ImmOpcode = PPC::LHA8; break;
2769  case PPC::LWZX: III.ImmOpcode = PPC::LWZ; break;
2770  case PPC::LWZX8: III.ImmOpcode = PPC::LWZ8; break;
2771  case PPC::LWAX:
2772  III.ImmOpcode = PPC::LWA;
2773  III.ImmMustBeMultipleOf = 4;
2774  break;
2775  case PPC::LDX: III.ImmOpcode = PPC::LD; III.ImmMustBeMultipleOf = 4; break;
2776  case PPC::LFSX: III.ImmOpcode = PPC::LFS; break;
2777  case PPC::LFDX: III.ImmOpcode = PPC::LFD; break;
2778  case PPC::STBX: III.ImmOpcode = PPC::STB; break;
2779  case PPC::STBX8: III.ImmOpcode = PPC::STB8; break;
2780  case PPC::STHX: III.ImmOpcode = PPC::STH; break;
2781  case PPC::STHX8: III.ImmOpcode = PPC::STH8; break;
2782  case PPC::STWX: III.ImmOpcode = PPC::STW; break;
2783  case PPC::STWX8: III.ImmOpcode = PPC::STW8; break;
2784  case PPC::STDX:
2785  III.ImmOpcode = PPC::STD;
2786  III.ImmMustBeMultipleOf = 4;
2787  break;
2788  case PPC::STFSX: III.ImmOpcode = PPC::STFS; break;
2789  case PPC::STFDX: III.ImmOpcode = PPC::STFD; break;
2790  }
2791  break;
2792  case PPC::LBZUX:
2793  case PPC::LBZUX8:
2794  case PPC::LHZUX:
2795  case PPC::LHZUX8:
2796  case PPC::LHAUX:
2797  case PPC::LHAUX8:
2798  case PPC::LWZUX:
2799  case PPC::LWZUX8:
2800  case PPC::LDUX:
2801  case PPC::LFSUX:
2802  case PPC::LFDUX:
2803  case PPC::STBUX:
2804  case PPC::STBUX8:
2805  case PPC::STHUX:
2806  case PPC::STHUX8:
2807  case PPC::STWUX:
2808  case PPC::STWUX8:
2809  case PPC::STDUX:
2810  case PPC::STFSUX:
2811  case PPC::STFDUX:
2812  III.SignedImm = true;
2813  III.ZeroIsSpecialOrig = 2;
2814  III.ZeroIsSpecialNew = 3;
2815  III.IsCommutative = false;
2816  III.ImmOpNo = 2;
2817  III.ConstantOpNo = 3;
2818  switch(Opc) {
2819  default: llvm_unreachable("Unknown opcode");
2820  case PPC::LBZUX: III.ImmOpcode = PPC::LBZU; break;
2821  case PPC::LBZUX8: III.ImmOpcode = PPC::LBZU8; break;
2822  case PPC::LHZUX: III.ImmOpcode = PPC::LHZU; break;
2823  case PPC::LHZUX8: III.ImmOpcode = PPC::LHZU8; break;
2824  case PPC::LHAUX: III.ImmOpcode = PPC::LHAU; break;
2825  case PPC::LHAUX8: III.ImmOpcode = PPC::LHAU8; break;
2826  case PPC::LWZUX: III.ImmOpcode = PPC::LWZU; break;
2827  case PPC::LWZUX8: III.ImmOpcode = PPC::LWZU8; break;
2828  case PPC::LDUX:
2829  III.ImmOpcode = PPC::LDU;
2830  III.ImmMustBeMultipleOf = 4;
2831  break;
2832  case PPC::LFSUX: III.ImmOpcode = PPC::LFSU; break;
2833  case PPC::LFDUX: III.ImmOpcode = PPC::LFDU; break;
2834  case PPC::STBUX: III.ImmOpcode = PPC::STBU; break;
2835  case PPC::STBUX8: III.ImmOpcode = PPC::STBU8; break;
2836  case PPC::STHUX: III.ImmOpcode = PPC::STHU; break;
2837  case PPC::STHUX8: III.ImmOpcode = PPC::STHU8; break;
2838  case PPC::STWUX: III.ImmOpcode = PPC::STWU; break;
2839  case PPC::STWUX8: III.ImmOpcode = PPC::STWU8; break;
2840  case PPC::STDUX:
2841  III.ImmOpcode = PPC::STDU;
2842  III.ImmMustBeMultipleOf = 4;
2843  break;
2844  case PPC::STFSUX: III.ImmOpcode = PPC::STFSU; break;
2845  case PPC::STFDUX: III.ImmOpcode = PPC::STFDU; break;
2846  }
2847  break;
2848  // Power9 only.
2849  case PPC::LXVX:
2850  case PPC::LXSSPX:
2851  case PPC::LXSDX:
2852  case PPC::STXVX:
2853  case PPC::STXSSPX:
2854  case PPC::STXSDX:
2855  if (!Subtarget.hasP9Vector())
2856  return false;
2857  III.SignedImm = true;
2858  III.ZeroIsSpecialOrig = 1;
2859  III.ZeroIsSpecialNew = 2;
2860  III.IsCommutative = true;
2861  III.ImmOpNo = 1;
2862  III.ConstantOpNo = 2;
2863  switch(Opc) {
2864  default: llvm_unreachable("Unknown opcode");
2865  case PPC::LXVX:
2866  III.ImmOpcode = PPC::LXV;
2867  III.ImmMustBeMultipleOf = 16;
2868  break;
2869  case PPC::LXSSPX:
2870  III.ImmOpcode = PPC::LXSSP;
2871  III.ImmMustBeMultipleOf = 4;
2872  break;
2873  case PPC::LXSDX:
2874  III.ImmOpcode = PPC::LXSD;
2875  III.ImmMustBeMultipleOf = 4;
2876  break;
2877  case PPC::STXVX:
2878  III.ImmOpcode = PPC::STXV;
2879  III.ImmMustBeMultipleOf = 16;
2880  break;
2881  case PPC::STXSSPX:
2882  III.ImmOpcode = PPC::STXSSP;
2883  III.ImmMustBeMultipleOf = 4;
2884  break;
2885  case PPC::STXSDX:
2886  III.ImmOpcode = PPC::STXSD;
2887  III.ImmMustBeMultipleOf = 4;
2888  break;
2889  }
2890  break;
2891  }
2892  return true;
2893 }
2894 
2895 // Utility function for swaping two arbitrary operands of an instruction.
2896 static void swapMIOperands(MachineInstr &MI, unsigned Op1, unsigned Op2) {
2897  assert(Op1 != Op2 && "Cannot swap operand with itself.");
2898 
2899  unsigned MaxOp = std::max(Op1, Op2);
2900  unsigned MinOp = std::min(Op1, Op2);
2901  MachineOperand MOp1 = MI.getOperand(MinOp);
2902  MachineOperand MOp2 = MI.getOperand(MaxOp);
2903  MI.RemoveOperand(std::max(Op1, Op2));
2904  MI.RemoveOperand(std::min(Op1, Op2));
2905 
2906  // If the operands we are swapping are the two at the end (the common case)
2907  // we can just remove both and add them in the opposite order.
2908  if (MaxOp - MinOp == 1 && MI.getNumOperands() == MinOp) {
2909  MI.addOperand(MOp2);
2910  MI.addOperand(MOp1);
2911  } else {
2912  // Store all operands in a temporary vector, remove them and re-add in the
2913  // right order.
2915  unsigned TotalOps = MI.getNumOperands() + 2; // We've already removed 2 ops.
2916  for (unsigned i = MI.getNumOperands() - 1; i >= MinOp; i--) {
2917  MOps.push_back(MI.getOperand(i));
2918  MI.RemoveOperand(i);
2919  }
2920  // MOp2 needs to be added next.
2921  MI.addOperand(MOp2);
2922  // Now add the rest.
2923  for (unsigned i = MI.getNumOperands(); i < TotalOps; i++) {
2924  if (i == MaxOp)
2925  MI.addOperand(MOp1);
2926  else {
2927  MI.addOperand(MOps.back());
2928  MOps.pop_back();
2929  }
2930  }
2931  }
2932 }
2933 
2934 bool PPCInstrInfo::transformToImmForm(MachineInstr &MI, const ImmInstrInfo &III,
2935  unsigned ConstantOpNo,
2936  int64_t Imm) const {
2938  bool PostRA = !MRI.isSSA();
2939  // Exit early if we can't convert this.
2940  if ((ConstantOpNo != III.ConstantOpNo) && !III.IsCommutative)
2941  return false;
2942  if (Imm % III.ImmMustBeMultipleOf)
2943  return false;
2944  if (III.TruncateImmTo)
2945  Imm &= ((1 << III.TruncateImmTo) - 1);
2946  if (III.SignedImm) {
2947  APInt ActualValue(64, Imm, true);
2948  if (!ActualValue.isSignedIntN(III.ImmWidth))
2949  return false;
2950  } else {
2951  uint64_t UnsignedMax = (1 << III.ImmWidth) - 1;
2952  if ((uint64_t)Imm > UnsignedMax)
2953  return false;
2954  }
2955 
2956  // If we're post-RA, the instructions don't agree on whether register zero is
2957  // special, we can transform this as long as the register operand that will
2958  // end up in the location where zero is special isn't R0.
2959  if (PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) {
2960  unsigned PosForOrigZero = III.ZeroIsSpecialOrig ? III.ZeroIsSpecialOrig :
2961  III.ZeroIsSpecialNew + 1;
2962  unsigned OrigZeroReg = MI.getOperand(PosForOrigZero).getReg();
2963  unsigned NewZeroReg = MI.getOperand(III.ZeroIsSpecialNew).getReg();
2964  // If R0 is in the operand where zero is special for the new instruction,
2965  // it is unsafe to transform if the constant operand isn't that operand.
2966  if ((NewZeroReg == PPC::R0 || NewZeroReg == PPC::X0) &&
2967  ConstantOpNo != III.ZeroIsSpecialNew)
2968  return false;
2969  if ((OrigZeroReg == PPC::R0 || OrigZeroReg == PPC::X0) &&
2970  ConstantOpNo != PosForOrigZero)
2971  return false;
2972  }
2973 
2974  unsigned Opc = MI.getOpcode();
2975  bool SpecialShift32 =
2976  Opc == PPC::SLW || Opc == PPC::SLWo || Opc == PPC::SRW || Opc == PPC::SRWo;
2977  bool SpecialShift64 =
2978  Opc == PPC::SLD || Opc == PPC::SLDo || Opc == PPC::SRD || Opc == PPC::SRDo;
2979  bool SetCR = Opc == PPC::SLWo || Opc == PPC::SRWo ||
2980  Opc == PPC::SLDo || Opc == PPC::SRDo;
2981  bool RightShift =
2982  Opc == PPC::SRW || Opc == PPC::SRWo || Opc == PPC::SRD || Opc == PPC::SRDo;
2983 
2984  MI.setDesc(get(III.ImmOpcode));
2985  if (ConstantOpNo == III.ConstantOpNo) {
2986  // Converting shifts to immediate form is a bit tricky since they may do
2987  // one of three things:
2988  // 1. If the shift amount is between OpSize and 2*OpSize, the result is zero
2989  // 2. If the shift amount is zero, the result is unchanged (save for maybe
2990  // setting CR0)
2991  // 3. If the shift amount is in [1, OpSize), it's just a shift
2992  if (SpecialShift32 || SpecialShift64) {
2993  LoadImmediateInfo LII;
2994  LII.Imm = 0;
2995  LII.SetCR = SetCR;
2996  LII.Is64Bit = SpecialShift64;
2997  uint64_t ShAmt = Imm & (SpecialShift32 ? 0x1F : 0x3F);
2998  if (Imm & (SpecialShift32 ? 0x20 : 0x40))
2999  replaceInstrWithLI(MI, LII);
3000  // Shifts by zero don't change the value. If we don't need to set CR0,
3001  // just convert this to a COPY. Can't do this post-RA since we've already
3002  // cleaned up the copies.
3003  else if (!SetCR && ShAmt == 0 && !PostRA) {
3004  MI.RemoveOperand(2);
3005  MI.setDesc(get(PPC::COPY));
3006  } else {
3007  // The 32 bit and 64 bit instructions are quite different.
3008  if (SpecialShift32) {
3009  // Left shifts use (N, 0, 31-N), right shifts use (32-N, N, 31).
3010  uint64_t SH = RightShift ? 32 - ShAmt : ShAmt;
3011  uint64_t MB = RightShift ? ShAmt : 0;
3012  uint64_t ME = RightShift ? 31 : 31 - ShAmt;
3014  MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(MB)
3015  .addImm(ME);
3016  } else {
3017  // Left shifts use (N, 63-N), right shifts use (64-N, N).
3018  uint64_t SH = RightShift ? 64 - ShAmt : ShAmt;
3019  uint64_t ME = RightShift ? ShAmt : 63 - ShAmt;
3021  MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(ME);
3022  }
3023  }
3024  } else
3025  MI.getOperand(ConstantOpNo).ChangeToImmediate(Imm);
3026  }
3027  // Convert commutative instructions (switch the operands and convert the
3028  // desired one to an immediate.
3029  else if (III.IsCommutative) {
3030  MI.getOperand(ConstantOpNo).ChangeToImmediate(Imm);
3031  swapMIOperands(MI, ConstantOpNo, III.ConstantOpNo);
3032  } else
3033  llvm_unreachable("Should have exited early!");
3034 
3035  // For instructions for which the constant register replaces a different
3036  // operand than where the immediate goes, we need to swap them.
3037  if (III.ConstantOpNo != III.ImmOpNo)
3038  swapMIOperands(MI, III.ConstantOpNo, III.ImmOpNo);
3039 
3040  // If the R0/X0 register is special for the original instruction and not for
3041  // the new instruction (or vice versa), we need to fix up the register class.
3042  if (!PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) {
3043  if (!III.ZeroIsSpecialOrig) {
3044  unsigned RegToModify = MI.getOperand(III.ZeroIsSpecialNew).getReg();
3045  const TargetRegisterClass *NewRC =
3046  MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ?
3047  &PPC::GPRC_and_GPRC_NOR0RegClass : &PPC::G8RC_and_G8RC_NOX0RegClass;
3048  MRI.setRegClass(RegToModify, NewRC);
3049  }
3050  }
3051  return true;
3052 }
3053 
3054 const TargetRegisterClass *
3056  if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
3057  return &PPC::VSRCRegClass;
3058  return RC;
3059 }
3060 
3062  return PPC::getRecordFormOpcode(Opcode);
3063 }
3064 
3065 // This function returns true if the machine instruction
3066 // always outputs a value by sign-extending a 32 bit value,
3067 // i.e. 0 to 31-th bits are same as 32-th bit.
3068 static bool isSignExtendingOp(const MachineInstr &MI) {
3069  int Opcode = MI.getOpcode();
3070  if (Opcode == PPC::LI || Opcode == PPC::LI8 ||
3071  Opcode == PPC::LIS || Opcode == PPC::LIS8 ||
3072  Opcode == PPC::SRAW || Opcode == PPC::SRAWo ||
3073  Opcode == PPC::SRAWI || Opcode == PPC::SRAWIo ||
3074  Opcode == PPC::LWA || Opcode == PPC::LWAX ||
3075  Opcode == PPC::LWA_32 || Opcode == PPC::LWAX_32 ||
3076  Opcode == PPC::LHA || Opcode == PPC::LHAX ||
3077  Opcode == PPC::LHA8 || Opcode == PPC::LHAX8 ||
3078  Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
3079  Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
3080  Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
3081  Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
3082  Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
3083  Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 ||
3084  Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
3085  Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 ||
3086  Opcode == PPC::EXTSB || Opcode == PPC::EXTSBo ||
3087  Opcode == PPC::EXTSH || Opcode == PPC::EXTSHo ||
3088  Opcode == PPC::EXTSB8 || Opcode == PPC::EXTSH8 ||
3089  Opcode == PPC::EXTSW || Opcode == PPC::EXTSWo ||
3090  Opcode == PPC::EXTSH8_32_64 || Opcode == PPC::EXTSW_32_64 ||
3091  Opcode == PPC::EXTSB8_32_64)
3092  return true;
3093 
3094  if (Opcode == PPC::RLDICL && MI.getOperand(3).getImm() >= 33)
3095  return true;
3096 
3097  if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
3098  Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo) &&
3099  MI.getOperand(3).getImm() > 0 &&
3100  MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
3101  return true;
3102 
3103  return false;
3104 }
3105 
3106 // This function returns true if the machine instruction
3107 // always outputs zeros in higher 32 bits.
3108 static bool isZeroExtendingOp(const MachineInstr &MI) {
3109  int Opcode = MI.getOpcode();
3110  // The 16-bit immediate is sign-extended in li/lis.
3111  // If the most significant bit is zero, all higher bits are zero.
3112  if (Opcode == PPC::LI || Opcode == PPC::LI8 ||
3113  Opcode == PPC::LIS || Opcode == PPC::LIS8) {
3114  int64_t Imm = MI.getOperand(1).getImm();
3115  if (((uint64_t)Imm & ~0x7FFFuLL) == 0)
3116  return true;
3117  }
3118 
3119  // We have some variations of rotate-and-mask instructions
3120  // that clear higher 32-bits.
3121  if ((Opcode == PPC::RLDICL || Opcode == PPC::RLDICLo ||
3122  Opcode == PPC::RLDCL || Opcode == PPC::RLDCLo ||
3123  Opcode == PPC::RLDICL_32_64) &&
3124  MI.getOperand(3).getImm() >= 32)
3125  return true;
3126 
3127  if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDICo) &&
3128  MI.getOperand(3).getImm() >= 32 &&
3129  MI.getOperand(3).getImm() <= 63 - MI.getOperand(2).getImm())
3130  return true;
3131 
3132  if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
3133  Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo ||
3134  Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) &&
3135  MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
3136  return true;
3137 
3138  // There are other instructions that clear higher 32-bits.
3139  if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZWo ||
3140  Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZWo ||
3141  Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8 ||
3142  Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZDo ||
3143  Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZDo ||
3144  Opcode == PPC::POPCNTD || Opcode == PPC::POPCNTW ||
3145  Opcode == PPC::SLW || Opcode == PPC::SLWo ||
3146  Opcode == PPC::SRW || Opcode == PPC::SRWo ||
3147  Opcode == PPC::SLW8 || Opcode == PPC::SRW8 ||
3148  Opcode == PPC::SLWI || Opcode == PPC::SLWIo ||
3149  Opcode == PPC::SRWI || Opcode == PPC::SRWIo ||
3150  Opcode == PPC::LWZ || Opcode == PPC::LWZX ||
3151  Opcode == PPC::LWZU || Opcode == PPC::LWZUX ||
3152  Opcode == PPC::LWBRX || Opcode == PPC::LHBRX ||
3153  Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
3154  Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
3155  Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
3156  Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
3157  Opcode == PPC::LWZ8 || Opcode == PPC::LWZX8 ||
3158  Opcode == PPC::LWZU8 || Opcode == PPC::LWZUX8 ||
3159  Opcode == PPC::LWBRX8 || Opcode == PPC::LHBRX8 ||
3160  Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 ||
3161  Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 ||
3162  Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
3163  Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
3164  Opcode == PPC::ANDIo || Opcode == PPC::ANDISo ||
3165  Opcode == PPC::ROTRWI || Opcode == PPC::ROTRWIo ||
3166  Opcode == PPC::EXTLWI || Opcode == PPC::EXTLWIo ||
3167  Opcode == PPC::MFVSRWZ)
3168  return true;
3169 
3170  return false;
3171 }
3172 
3173 // This function returns true if the input MachineInstr is a TOC save
3174 // instruction.
3176  if (!MI.getOperand(1).isImm() || !MI.getOperand(2).isReg())
3177  return false;
3178  unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
3179  unsigned StackOffset = MI.getOperand(1).getImm();
3180  unsigned StackReg = MI.getOperand(2).getReg();
3181  if (StackReg == PPC::X1 && StackOffset == TOCSaveOffset)
3182  return true;
3183 
3184  return false;
3185 }
3186 
3187 // We limit the max depth to track incoming values of PHIs or binary ops
3188 // (e.g. AND) to avoid exsessive cost.
3189 const unsigned MAX_DEPTH = 1;
3190 
3191 bool
3193  const unsigned Depth) const {
3194  const MachineFunction *MF = MI.getParent()->getParent();
3195  const MachineRegisterInfo *MRI = &MF->getRegInfo();
3196 
3197  // If we know this instruction returns sign- or zero-extended result,
3198  // return true.
3199  if (SignExt ? isSignExtendingOp(MI):
3200  isZeroExtendingOp(MI))
3201  return true;
3202 
3203  switch (MI.getOpcode()) {
3204  case PPC::COPY: {
3205  unsigned SrcReg = MI.getOperand(1).getReg();
3206 
3207  // In both ELFv1 and v2 ABI, method parameters and the return value
3208  // are sign- or zero-extended.
3209  if (MF->getSubtarget<PPCSubtarget>().isSVR4ABI()) {
3210  const PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
3211  // We check the ZExt/SExt flags for a method parameter.
3212  if (MI.getParent()->getBasicBlock() ==
3213  &MF->getFunction().getEntryBlock()) {
3214  unsigned VReg = MI.getOperand(0).getReg();
3215  if (MF->getRegInfo().isLiveIn(VReg))
3216  return SignExt ? FuncInfo->isLiveInSExt(VReg) :
3217  FuncInfo->isLiveInZExt(VReg);
3218  }
3219 
3220  // For a method return value, we check the ZExt/SExt flags in attribute.
3221  // We assume the following code sequence for method call.
3222  // ADJCALLSTACKDOWN 32, implicit dead %r1, implicit %r1
3223  // BL8_NOP @func,...
3224  // ADJCALLSTACKUP 32, 0, implicit dead %r1, implicit %r1
3225  // %5 = COPY %x3; G8RC:%5
3226  if (SrcReg == PPC::X3) {
3227  const MachineBasicBlock *MBB = MI.getParent();
3230  if (II != MBB->instr_begin() &&
3231  (--II)->getOpcode() == PPC::ADJCALLSTACKUP) {
3232  const MachineInstr &CallMI = *(--II);
3233  if (CallMI.isCall() && CallMI.getOperand(0).isGlobal()) {
3234  const Function *CalleeFn =
3235  dyn_cast<Function>(CallMI.getOperand(0).getGlobal());
3236  if (!CalleeFn)
3237  return false;
3238  const IntegerType *IntTy =
3239  dyn_cast<IntegerType>(CalleeFn->getReturnType());
3240  const AttributeSet &Attrs =
3241  CalleeFn->getAttributes().getRetAttributes();
3242  if (IntTy && IntTy->getBitWidth() <= 32)
3243  return Attrs.hasAttribute(SignExt ? Attribute::SExt :
3244  Attribute::ZExt);
3245  }
3246  }
3247  }
3248  }
3249 
3250  // If this is a copy from another register, we recursively check source.
3252  return false;
3253  const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3254  if (SrcMI != NULL)
3255  return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
3256 
3257  return false;
3258  }
3259 
3260  case PPC::ANDIo:
3261  case PPC::ANDISo:
3262  case PPC::ORI:
3263  case PPC::ORIS:
3264  case PPC::XORI:
3265  case PPC::XORIS:
3266  case PPC::ANDIo8:
3267  case PPC::ANDISo8:
3268  case PPC::ORI8:
3269  case PPC::ORIS8:
3270  case PPC::XORI8:
3271  case PPC::XORIS8: {
3272  // logical operation with 16-bit immediate does not change the upper bits.
3273  // So, we track the operand register as we do for register copy.
3274  unsigned SrcReg = MI.getOperand(1).getReg();
3276  return false;
3277  const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3278  if (SrcMI != NULL)
3279  return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
3280 
3281  return false;
3282  }
3283 
3284  // If all incoming values are sign-/zero-extended,
3285  // the output of OR, ISEL or PHI is also sign-/zero-extended.
3286  case PPC::OR:
3287  case PPC::OR8:
3288  case PPC::ISEL:
3289  case PPC::PHI: {
3290  if (Depth >= MAX_DEPTH)
3291  return false;
3292 
3293  // The input registers for PHI are operand 1, 3, ...
3294  // The input registers for others are operand 1 and 2.
3295  unsigned E = 3, D = 1;
3296  if (MI.getOpcode() == PPC::PHI) {
3297  E = MI.getNumOperands();
3298  D = 2;
3299  }
3300 
3301  for (unsigned I = 1; I != E; I += D) {
3302  if (MI.getOperand(I).isReg()) {
3303  unsigned SrcReg = MI.getOperand(I).getReg();
3305  return false;
3306  const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3307  if (SrcMI == NULL || !isSignOrZeroExtended(*SrcMI, SignExt, Depth+1))
3308  return false;
3309  }
3310  else
3311  return false;
3312  }
3313  return true;
3314  }
3315 
3316  // If at least one of the incoming values of an AND is zero extended
3317  // then the output is also zero-extended. If both of the incoming values
3318  // are sign-extended then the output is also sign extended.
3319  case PPC::AND:
3320  case PPC::AND8: {
3321  if (Depth >= MAX_DEPTH)
3322  return false;
3323 
3324  assert(MI.getOperand(1).isReg() && MI.getOperand(2).isReg());
3325 
3326  unsigned SrcReg1 = MI.getOperand(1).getReg();
3327  unsigned SrcReg2 = MI.getOperand(2).getReg();
3328 
3329  if (!TargetRegisterInfo::isVirtualRegister(SrcReg1) ||
3331  return false;
3332 
3333  const MachineInstr *MISrc1 = MRI->getVRegDef(SrcReg1);
3334  const MachineInstr *MISrc2 = MRI->getVRegDef(SrcReg2);
3335  if (!MISrc1 || !MISrc2)
3336  return false;
3337 
3338  if(SignExt)
3339  return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) &&
3340  isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
3341  else
3342  return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) ||
3343  isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
3344  }
3345 
3346  default:
3347  break;
3348  }
3349  return false;
3350 }
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
Definition: MachineInstr.h:997
instr_iterator instr_begin()
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:479
int getNonRecordFormOpcode(uint16_t)
MachineBasicBlock * getMBB() const
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
uint64_t ZeroIsSpecialNew
Definition: PPCInstrInfo.h:91
iterator begin() const
begin/end - Return all of the registers in this class.
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:223
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:285
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:513
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:161
unsigned getReg() const
getReg - Returns the register number.
static int getRecordFormOpcode(unsigned Opcode)
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned Reg
unsigned getSubReg() const
bool hasVSX() const
Definition: PPCSubtarget.h:243
static cl::opt< bool > DisableCmpOpt("disable-ppc-cmp-opt", cl::desc("Disable compare instruction optimization"), cl::Hidden)
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
uint64_t IsCommutative
Definition: PPCInstrInfo.h:93
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
uint64_t TruncateImmTo
Definition: PPCInstrInfo.h:103
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:298
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
bool isPseudo() const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MCInstrDesc.h:240
CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
#define R2(n)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool instrHasImmForm(const MachineInstr &MI, ImmInstrInfo &III) const
bool isSignExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always a sign-extended, i.e.
Definition: PPCInstrInfo.h:359
return AArch64::GPR64RegClass contains(Reg)
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling th...
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineFunction & MF
Machine function.
Definition: ScheduleDAG.h:570
bool isXFormMemOp(unsigned Opcode) const
Definition: PPCInstrInfo.h:158
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
PPCDispatchGroupSBHazardRecognizer - This class implements a scoreboard-based hazard recognizer for P...
A description of a memory reference used in the backend.
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:208
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:451
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:314
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:495
AttributeSet getRetAttributes() const
The attributes for the ret value are returned.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:311
const TargetRegisterClass * updatedRC(const TargetRegisterClass *RC) const
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const override
uint64_t ZeroIsSpecialOrig
Definition: PPCInstrInfo.h:88
const char * getSymbolName() const
static bool isZeroExtendingOp(const MachineInstr &MI)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:636
static void swapMIOperands(MachineInstr &MI, unsigned Op1, unsigned Op2)
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
bool isTOCSaveMI(const MachineInstr &MI) const
defusechain_iterator - This class provides iterator support for machine operands in the function that...
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
PPCInstrInfo(PPCSubtarget &STI)
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1559
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:308
CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based loops.
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const override
MO_NLP_HIDDEN_FLAG - If this bit is set, the symbol reference is to a symbol with hidden visibility...
Definition: PPC.h:92
virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns) const
Return true when there is potentially a faster code sequence for an instruction chain ending in Root...
CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
Itinerary data supplied by a subtarget to be used by a target.
const PPCTargetMachine & getTargetMachine() const
Definition: PPCSubtarget.h:190
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:210
constexpr char Attrs[]
Key for Kernel::Metadata::mAttrs.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
unsigned getBitWidth() const
Get the number of bits in this IntegerType.
Definition: DerivedTypes.h:66
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
reverse_iterator rend()
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:503
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
unsigned getKillRegState(bool B)
bool hasAttribute(Attribute::AttrKind Kind) const
Return true if the attribute exists in this set.
Definition: Attributes.cpp:576
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
unsigned getDeadRegState(bool B)
VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
const BasicBlock & getEntryBlock() const
Definition: Function.h:626
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:566
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, const unsigned PhiDepth) const
Type * getReturnType() const
Returns the type of the ret val.
Definition: Function.h:155
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:535
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static unsigned selectReg(int64_t Imm1, int64_t Imm2, unsigned CompareOpc, unsigned TrueReg, unsigned FalseReg, unsigned CRSubReg)
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
unsigned const MachineRegisterInfo * MRI
bool isLiveInSExt(unsigned VReg) const
This function returns true if the spesified vreg is a live-in register and sign-extended.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
int getAltVSXFMAOpcode(uint16_t Opcode)
Simple binary floating point operators.
Definition: ISDOpcodes.h:260
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void clearRegisterDeads(unsigned Reg)
Clear all dead flags on operands defining register Reg.
MachineInstrBuilder & UseMI
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
MO_NLP_FLAG - If this bit is set, the symbol reference is actually to the non_lazy_ptr for the global...
Definition: PPC.h:87
const GlobalValue * getGlobal() const
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:31
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:171
STFIWX - The STFIWX instruction.
use_instr_iterator use_instr_begin(unsigned RegNo) const
static const unsigned End
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
void setImm(int64_t immVal)
bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
Definition: MachineInstr.h:989
GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point load which sign-extends from a 32-bit inte...
MI-level patchpoint operands.
Definition: StackMaps.h:77
Class to represent integer types.
Definition: DerivedTypes.h:40
PPCHazardRecognizer970 - This class defines a finite state automata that models the dispatch logic on...
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
unsigned getStoreOpcodeForSpill(unsigned Reg, const TargetRegisterClass *RC=nullptr) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
auto find(R &&Range, const T &Val) -> decltype(adl_begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:929
unsigned getPredicateHint(Predicate Opcode)
Return the hint bits of the predicate.
Definition: PPCPredicates.h:80
unsigned getDarwinDirective() const
getDarwinDirective - Returns the -m directive specified for the cpu.
Definition: PPCSubtarget.h:169
static unsigned getCRFromCRBit(unsigned SrcReg)
MO_TLS - Indicates that the operand being accessed is some kind of thread-local symbol.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
unsigned first
void setIsKill(bool Val=true)
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
The next are not flags but distinct values.
Definition: PPC.h:95
The memory access writes data.
static bool MBBDefinesCTR(MachineBasicBlock &MBB)
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:185
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given stackmap should emit.
Definition: StackMaps.h:51
Predicate getPredicate(unsigned Condition, unsigned Hint)
Return predicate consisting of specified condition and hint bits.
Definition: PPCPredicates.h:85
Iterator for intrusive lists based on ilist_node.
void setOpcode(unsigned Op)
Definition: MCInst.h:173
bool isUnpredicatedTerminator(const MachineInstr &MI) const override
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
void getNoop(MCInst &NopInst) const override
Return the noop instruction to use for a noop.
static unsigned getCRBitValue(unsigned CRBit)
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:787
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:27
static cl::opt< bool > VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy", cl::desc("Causes the backend to crash instead of generating a nop VSX copy"), cl::Hidden)
static cl::opt< bool > UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden, cl::desc("Use the old (incorrect) instruction latency calculation"))
APInt rotl(unsigned rotateAmt) const
Rotate left by rotateAmt.
Definition: APInt.cpp:1001
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
uint64_t ConstantOpNo
Definition: PPCInstrInfo.h:95
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
int64_t getImm() const
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const Function & getFunction() const
Return the LLVM function that this machine code represents.
virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Class for arbitrary precision integers.
Definition: APInt.h:69
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
QVGPCI = This corresponds to the QPX qvgpci instruction.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:959
On a symbol operand, this represents the lo part.
Definition: AVRInstrInfo.h:53
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:156
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
TargetSubtargetInfo - Generic base class for all target subtargets.
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in <Root...
bool isPredicated(const MachineInstr &MI) const override
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
bool isLiveIn(unsigned Reg) const
Representation of each machine instruction.
Definition: MachineInstr.h:60
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Predicate InvertPredicate(Predicate Opcode)
Invert the specified predicate. != -> ==, < -> >=.
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:363
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
bool hasOneUse(unsigned RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MI-level stackmap operands.
Definition: StackMaps.h:36
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
TargetOptions Options
Definition: TargetMachine.h:98
static bool isSignExtendingOp(const MachineInstr &MI)
void setReg(unsigned Reg)
Change the register this operand corresponds to.
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned getLoadOpcodeForSpill(unsigned Reg, const TargetRegisterClass *RC=nullptr) const
void setSubReg(unsigned subReg)
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given patchpoint should emit.
Definition: StackMaps.h:105
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:568
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:338
bool isSignedIntN(unsigned N) const
Check if this APInt has an N-bits signed integer value.
Definition: APInt.h:449
const unsigned MAX_DEPTH
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator_range< use_instr_iterator > use_instructions(unsigned Reg) const
uint64_t ImmMustBeMultipleOf
Definition: PPCInstrInfo.h:85
unsigned getPredicateCondition(Predicate Opcode)
Return the condition without hint bits.
Definition: PPCPredicates.h:75
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
bool isLiveInZExt(unsigned VReg) const
This function returns true if the spesified vreg is a live-in register and zero-extended.
LLVM Value Representation.
Definition: Value.h:73
static use_instr_iterator use_instr_end()
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:172
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when ...
IRTranslator LLVM IR MI
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:486
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
bool isPredicable(const MachineInstr &MI) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool isSVR4ABI() const
Definition: PPCSubtarget.h:307
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:67
#define LLVM_DEBUG(X)
Definition: Debug.h:119
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:316
On a symbol operand "FOO", this indicates that the reference is actually to "FOO@plt".
Definition: PPC.h:79
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: PPCInstrInfo.h:156
virtual unsigned lookThruCopyLike(unsigned SrcReg, const MachineRegisterInfo *MRI) const
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:274
static cl::opt< bool > DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden, cl::desc("Disable analysis for CTR loops"))
Instructions::const_iterator const_instr_iterator
GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point load which zero-extends from a 32-bit inte...
SpillOpcodeKey
MO_PIC_FLAG - If this bit is set, the symbol reference is relative to the function&#39;s picbase...
Definition: PPC.h:83
bool convertToImmediateForm(MachineInstr &MI, MachineInstr **KilledDef=nullptr) const
bool expandPostRAPseudo(MachineInstr &MI) const override
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:144
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:170
bool expandVSXMemPseudo(MachineInstr &MI) const
bool isImplicit() const
bool isZeroExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always zero-extended, i.e.
Definition: PPCInstrInfo.h:365
Predicate getSwappedPredicate(Predicate Opcode)
Assume the condition register is set by MI(a,b), return the predicate if we modify the instructions s...