LLVM  8.0.0svn
PPCInstrInfo.cpp
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1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCInstrInfo.h"
16 #include "PPC.h"
17 #include "PPCHazardRecognizers.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCTargetMachine.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Statistic.h"
32 #include "llvm/CodeGen/StackMaps.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCInst.h"
36 #include "llvm/Support/Debug.h"
40 
41 using namespace llvm;
42 
43 #define DEBUG_TYPE "ppc-instr-info"
44 
45 #define GET_INSTRMAP_INFO
46 #define GET_INSTRINFO_CTOR_DTOR
47 #include "PPCGenInstrInfo.inc"
48 
49 STATISTIC(NumStoreSPILLVSRRCAsVec,
50  "Number of spillvsrrc spilled to stack as vec");
51 STATISTIC(NumStoreSPILLVSRRCAsGpr,
52  "Number of spillvsrrc spilled to stack as gpr");
53 STATISTIC(NumGPRtoVSRSpill, "Number of gpr spills to spillvsrrc");
54 STATISTIC(CmpIselsConverted,
55  "Number of ISELs that depend on comparison of constants converted");
56 STATISTIC(MissedConvertibleImmediateInstrs,
57  "Number of compare-immediate instructions fed by constants");
58 STATISTIC(NumRcRotatesConvertedToRcAnd,
59  "Number of record-form rotates converted to record-form andi");
60 
61 static cl::
62 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
63  cl::desc("Disable analysis for CTR loops"));
64 
65 static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
66 cl::desc("Disable compare instruction optimization"), cl::Hidden);
67 
68 static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
69 cl::desc("Causes the backend to crash instead of generating a nop VSX copy"),
70 cl::Hidden);
71 
72 static cl::opt<bool>
73 UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
74  cl::desc("Use the old (incorrect) instruction latency calculation"));
75 
76 // Index into the OpcodesForSpill array.
95  SOK_LastOpcodeSpill // This must be last on the enum.
96 };
97 
98 // Pin the vtable to this file.
99 void PPCInstrInfo::anchor() {}
100 
102  : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP,
103  /* CatchRetOpcode */ -1,
104  STI.isPPC64() ? PPC::BLR8 : PPC::BLR),
105  Subtarget(STI), RI(STI.getTargetMachine()) {}
106 
107 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
108 /// this target when scheduling the DAG.
111  const ScheduleDAG *DAG) const {
112  unsigned Directive =
113  static_cast<const PPCSubtarget *>(STI)->getDarwinDirective();
114  if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
115  Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
116  const InstrItineraryData *II =
117  static_cast<const PPCSubtarget *>(STI)->getInstrItineraryData();
118  return new ScoreboardHazardRecognizer(II, DAG);
119  }
120 
122 }
123 
124 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
125 /// to use for this target when scheduling the DAG.
128  const ScheduleDAG *DAG) const {
129  unsigned Directive =
130  DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
131 
132  // FIXME: Leaving this as-is until we have POWER9 scheduling info
133  if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8)
134  return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
135 
136  // Most subtargets use a PPC970 recognizer.
137  if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
138  Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
139  assert(DAG->TII && "No InstrInfo?");
140 
141  return new PPCHazardRecognizer970(*DAG);
142  }
143 
144  return new ScoreboardHazardRecognizer(II, DAG);
145 }
146 
148  const MachineInstr &MI,
149  unsigned *PredCost) const {
150  if (!ItinData || UseOldLatencyCalc)
151  return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
152 
153  // The default implementation of getInstrLatency calls getStageLatency, but
154  // getStageLatency does not do the right thing for us. While we have
155  // itinerary, most cores are fully pipelined, and so the itineraries only
156  // express the first part of the pipeline, not every stage. Instead, we need
157  // to use the listed output operand cycle number (using operand 0 here, which
158  // is an output).
159 
160  unsigned Latency = 1;
161  unsigned DefClass = MI.getDesc().getSchedClass();
162  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
163  const MachineOperand &MO = MI.getOperand(i);
164  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
165  continue;
166 
167  int Cycle = ItinData->getOperandCycle(DefClass, i);
168  if (Cycle < 0)
169  continue;
170 
171  Latency = std::max(Latency, (unsigned) Cycle);
172  }
173 
174  return Latency;
175 }
176 
178  const MachineInstr &DefMI, unsigned DefIdx,
179  const MachineInstr &UseMI,
180  unsigned UseIdx) const {
181  int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
182  UseMI, UseIdx);
183 
184  if (!DefMI.getParent())
185  return Latency;
186 
187  const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
188  unsigned Reg = DefMO.getReg();
189 
190  bool IsRegCR;
192  const MachineRegisterInfo *MRI =
193  &DefMI.getParent()->getParent()->getRegInfo();
194  IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
195  MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
196  } else {
197  IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
198  PPC::CRBITRCRegClass.contains(Reg);
199  }
200 
201  if (UseMI.isBranch() && IsRegCR) {
202  if (Latency < 0)
203  Latency = getInstrLatency(ItinData, DefMI);
204 
205  // On some cores, there is an additional delay between writing to a condition
206  // register, and using it from a branch.
207  unsigned Directive = Subtarget.getDarwinDirective();
208  switch (Directive) {
209  default: break;
210  case PPC::DIR_7400:
211  case PPC::DIR_750:
212  case PPC::DIR_970:
213  case PPC::DIR_E5500:
214  case PPC::DIR_PWR4:
215  case PPC::DIR_PWR5:
216  case PPC::DIR_PWR5X:
217  case PPC::DIR_PWR6:
218  case PPC::DIR_PWR6X:
219  case PPC::DIR_PWR7:
220  case PPC::DIR_PWR8:
221  // FIXME: Is this needed for POWER9?
222  Latency += 2;
223  break;
224  }
225  }
226 
227  return Latency;
228 }
229 
230 // This function does not list all associative and commutative operations, but
231 // only those worth feeding through the machine combiner in an attempt to
232 // reduce the critical path. Mostly, this means floating-point operations,
233 // because they have high latencies (compared to other operations, such and
234 // and/or, which are also associative and commutative, but have low latencies).
236  switch (Inst.getOpcode()) {
237  // FP Add:
238  case PPC::FADD:
239  case PPC::FADDS:
240  // FP Multiply:
241  case PPC::FMUL:
242  case PPC::FMULS:
243  // Altivec Add:
244  case PPC::VADDFP:
245  // VSX Add:
246  case PPC::XSADDDP:
247  case PPC::XVADDDP:
248  case PPC::XVADDSP:
249  case PPC::XSADDSP:
250  // VSX Multiply:
251  case PPC::XSMULDP:
252  case PPC::XVMULDP:
253  case PPC::XVMULSP:
254  case PPC::XSMULSP:
255  // QPX Add:
256  case PPC::QVFADD:
257  case PPC::QVFADDS:
258  case PPC::QVFADDSs:
259  // QPX Multiply:
260  case PPC::QVFMUL:
261  case PPC::QVFMULS:
262  case PPC::QVFMULSs:
263  return true;
264  default:
265  return false;
266  }
267 }
268 
270  MachineInstr &Root,
271  SmallVectorImpl<MachineCombinerPattern> &Patterns) const {
272  // Using the machine combiner in this way is potentially expensive, so
273  // restrict to when aggressive optimizations are desired.
275  return false;
276 
277  // FP reassociation is only legal when we don't need strict IEEE semantics.
279  return false;
280 
281  return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns);
282 }
283 
284 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
286  unsigned &SrcReg, unsigned &DstReg,
287  unsigned &SubIdx) const {
288  switch (MI.getOpcode()) {
289  default: return false;
290  case PPC::EXTSW:
291  case PPC::EXTSW_32:
292  case PPC::EXTSW_32_64:
293  SrcReg = MI.getOperand(1).getReg();
294  DstReg = MI.getOperand(0).getReg();
295  SubIdx = PPC::sub_32;
296  return true;
297  }
298 }
299 
301  int &FrameIndex) const {
302  unsigned Opcode = MI.getOpcode();
303  const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
304  const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill;
305 
306  if (End != std::find(OpcodesForSpill, End, Opcode)) {
307  // Check for the operands added by addFrameReference (the immediate is the
308  // offset which defaults to 0).
309  if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
310  MI.getOperand(2).isFI()) {
311  FrameIndex = MI.getOperand(2).getIndex();
312  return MI.getOperand(0).getReg();
313  }
314  }
315  return 0;
316 }
317 
318 // For opcodes with the ReMaterializable flag set, this function is called to
319 // verify the instruction is really rematable.
321  AliasAnalysis *AA) const {
322  switch (MI.getOpcode()) {
323  default:
324  // This function should only be called for opcodes with the ReMaterializable
325  // flag set.
326  llvm_unreachable("Unknown rematerializable operation!");
327  break;
328  case PPC::LI:
329  case PPC::LI8:
330  case PPC::LIS:
331  case PPC::LIS8:
332  case PPC::QVGPCI:
333  case PPC::ADDIStocHA:
334  case PPC::ADDItocL:
335  case PPC::LOAD_STACK_GUARD:
336  return true;
337  }
338  return false;
339 }
340 
342  int &FrameIndex) const {
343  unsigned Opcode = MI.getOpcode();
344  const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
345  const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill;
346 
347  if (End != std::find(OpcodesForSpill, End, Opcode)) {
348  if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
349  MI.getOperand(2).isFI()) {
350  FrameIndex = MI.getOperand(2).getIndex();
351  return MI.getOperand(0).getReg();
352  }
353  }
354  return 0;
355 }
356 
358  unsigned OpIdx1,
359  unsigned OpIdx2) const {
360  MachineFunction &MF = *MI.getParent()->getParent();
361 
362  // Normal instructions can be commuted the obvious way.
363  if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMIo)
364  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
365  // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
366  // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
367  // changing the relative order of the mask operands might change what happens
368  // to the high-bits of the mask (and, thus, the result).
369 
370  // Cannot commute if it has a non-zero rotate count.
371  if (MI.getOperand(3).getImm() != 0)
372  return nullptr;
373 
374  // If we have a zero rotate count, we have:
375  // M = mask(MB,ME)
376  // Op0 = (Op1 & ~M) | (Op2 & M)
377  // Change this to:
378  // M = mask((ME+1)&31, (MB-1)&31)
379  // Op0 = (Op2 & ~M) | (Op1 & M)
380 
381  // Swap op1/op2
382  assert(((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) &&
383  "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo.");
384  unsigned Reg0 = MI.getOperand(0).getReg();
385  unsigned Reg1 = MI.getOperand(1).getReg();
386  unsigned Reg2 = MI.getOperand(2).getReg();
387  unsigned SubReg1 = MI.getOperand(1).getSubReg();
388  unsigned SubReg2 = MI.getOperand(2).getSubReg();
389  bool Reg1IsKill = MI.getOperand(1).isKill();
390  bool Reg2IsKill = MI.getOperand(2).isKill();
391  bool ChangeReg0 = false;
392  // If machine instrs are no longer in two-address forms, update
393  // destination register as well.
394  if (Reg0 == Reg1) {
395  // Must be two address instruction!
397  "Expecting a two-address instruction!");
398  assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
399  Reg2IsKill = false;
400  ChangeReg0 = true;
401  }
402 
403  // Masks.
404  unsigned MB = MI.getOperand(4).getImm();
405  unsigned ME = MI.getOperand(5).getImm();
406 
407  // We can't commute a trivial mask (there is no way to represent an all-zero
408  // mask).
409  if (MB == 0 && ME == 31)
410  return nullptr;
411 
412  if (NewMI) {
413  // Create a new instruction.
414  unsigned Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg();
415  bool Reg0IsDead = MI.getOperand(0).isDead();
416  return BuildMI(MF, MI.getDebugLoc(), MI.getDesc())
417  .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
418  .addReg(Reg2, getKillRegState(Reg2IsKill))
419  .addReg(Reg1, getKillRegState(Reg1IsKill))
420  .addImm((ME + 1) & 31)
421  .addImm((MB - 1) & 31);
422  }
423 
424  if (ChangeReg0) {
425  MI.getOperand(0).setReg(Reg2);
426  MI.getOperand(0).setSubReg(SubReg2);
427  }
428  MI.getOperand(2).setReg(Reg1);
429  MI.getOperand(1).setReg(Reg2);
430  MI.getOperand(2).setSubReg(SubReg1);
431  MI.getOperand(1).setSubReg(SubReg2);
432  MI.getOperand(2).setIsKill(Reg1IsKill);
433  MI.getOperand(1).setIsKill(Reg2IsKill);
434 
435  // Swap the mask around.
436  MI.getOperand(4).setImm((ME + 1) & 31);
437  MI.getOperand(5).setImm((MB - 1) & 31);
438  return &MI;
439 }
440 
442  unsigned &SrcOpIdx2) const {
443  // For VSX A-Type FMA instructions, it is the first two operands that can be
444  // commuted, however, because the non-encoded tied input operand is listed
445  // first, the operands to swap are actually the second and third.
446 
447  int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode());
448  if (AltOpc == -1)
449  return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
450 
451  // The commutable operand indices are 2 and 3. Return them in SrcOpIdx1
452  // and SrcOpIdx2.
453  return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
454 }
455 
458  // This function is used for scheduling, and the nop wanted here is the type
459  // that terminates dispatch groups on the POWER cores.
460  unsigned Directive = Subtarget.getDarwinDirective();
461  unsigned Opcode;
462  switch (Directive) {
463  default: Opcode = PPC::NOP; break;
464  case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
465  case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
466  case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */
467  // FIXME: Update when POWER9 scheduling model is ready.
468  case PPC::DIR_PWR9: Opcode = PPC::NOP_GT_PWR7; break;
469  }
470 
471  DebugLoc DL;
472  BuildMI(MBB, MI, DL, get(Opcode));
473 }
474 
475 /// Return the noop instruction to use for a noop.
476 void PPCInstrInfo::getNoop(MCInst &NopInst) const {
477  NopInst.setOpcode(PPC::NOP);
478 }
479 
480 // Branch analysis.
481 // Note: If the condition register is set to CTR or CTR8 then this is a
482 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
484  MachineBasicBlock *&TBB,
485  MachineBasicBlock *&FBB,
487  bool AllowModify) const {
488  bool isPPC64 = Subtarget.isPPC64();
489 
490  // If the block has no terminators, it just falls into the block after it.
492  if (I == MBB.end())
493  return false;
494 
495  if (!isUnpredicatedTerminator(*I))
496  return false;
497 
498  if (AllowModify) {
499  // If the BB ends with an unconditional branch to the fallthrough BB,
500  // we eliminate the branch instruction.
501  if (I->getOpcode() == PPC::B &&
502  MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
503  I->eraseFromParent();
504 
505  // We update iterator after deleting the last branch.
506  I = MBB.getLastNonDebugInstr();
507  if (I == MBB.end() || !isUnpredicatedTerminator(*I))
508  return false;
509  }
510  }
511 
512  // Get the last instruction in the block.
513  MachineInstr &LastInst = *I;
514 
515  // If there is only one terminator instruction, process it.
516  if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
517  if (LastInst.getOpcode() == PPC::B) {
518  if (!LastInst.getOperand(0).isMBB())
519  return true;
520  TBB = LastInst.getOperand(0).getMBB();
521  return false;
522  } else if (LastInst.getOpcode() == PPC::BCC) {
523  if (!LastInst.getOperand(2).isMBB())
524  return true;
525  // Block ends with fall-through condbranch.
526  TBB = LastInst.getOperand(2).getMBB();
527  Cond.push_back(LastInst.getOperand(0));
528  Cond.push_back(LastInst.getOperand(1));
529  return false;
530  } else if (LastInst.getOpcode() == PPC::BC) {
531  if (!LastInst.getOperand(1).isMBB())
532  return true;
533  // Block ends with fall-through condbranch.
534  TBB = LastInst.getOperand(1).getMBB();
536  Cond.push_back(LastInst.getOperand(0));
537  return false;
538  } else if (LastInst.getOpcode() == PPC::BCn) {
539  if (!LastInst.getOperand(1).isMBB())
540  return true;
541  // Block ends with fall-through condbranch.
542  TBB = LastInst.getOperand(1).getMBB();
544  Cond.push_back(LastInst.getOperand(0));
545  return false;
546  } else if (LastInst.getOpcode() == PPC::BDNZ8 ||
547  LastInst.getOpcode() == PPC::BDNZ) {
548  if (!LastInst.getOperand(0).isMBB())
549  return true;
550  if (DisableCTRLoopAnal)
551  return true;
552  TBB = LastInst.getOperand(0).getMBB();
554  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
555  true));
556  return false;
557  } else if (LastInst.getOpcode() == PPC::BDZ8 ||
558  LastInst.getOpcode() == PPC::BDZ) {
559  if (!LastInst.getOperand(0).isMBB())
560  return true;
561  if (DisableCTRLoopAnal)
562  return true;
563  TBB = LastInst.getOperand(0).getMBB();
565  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
566  true));
567  return false;
568  }
569 
570  // Otherwise, don't know what this is.
571  return true;
572  }
573 
574  // Get the instruction before it if it's a terminator.
575  MachineInstr &SecondLastInst = *I;
576 
577  // If there are three terminators, we don't know what sort of block this is.
578  if (I != MBB.begin() && isUnpredicatedTerminator(*--I))
579  return true;
580 
581  // If the block ends with PPC::B and PPC:BCC, handle it.
582  if (SecondLastInst.getOpcode() == PPC::BCC &&
583  LastInst.getOpcode() == PPC::B) {
584  if (!SecondLastInst.getOperand(2).isMBB() ||
585  !LastInst.getOperand(0).isMBB())
586  return true;
587  TBB = SecondLastInst.getOperand(2).getMBB();
588  Cond.push_back(SecondLastInst.getOperand(0));
589  Cond.push_back(SecondLastInst.getOperand(1));
590  FBB = LastInst.getOperand(0).getMBB();
591  return false;
592  } else if (SecondLastInst.getOpcode() == PPC::BC &&
593  LastInst.getOpcode() == PPC::B) {
594  if (!SecondLastInst.getOperand(1).isMBB() ||
595  !LastInst.getOperand(0).isMBB())
596  return true;
597  TBB = SecondLastInst.getOperand(1).getMBB();
599  Cond.push_back(SecondLastInst.getOperand(0));
600  FBB = LastInst.getOperand(0).getMBB();
601  return false;
602  } else if (SecondLastInst.getOpcode() == PPC::BCn &&
603  LastInst.getOpcode() == PPC::B) {
604  if (!SecondLastInst.getOperand(1).isMBB() ||
605  !LastInst.getOperand(0).isMBB())
606  return true;
607  TBB = SecondLastInst.getOperand(1).getMBB();
609  Cond.push_back(SecondLastInst.getOperand(0));
610  FBB = LastInst.getOperand(0).getMBB();
611  return false;
612  } else if ((SecondLastInst.getOpcode() == PPC::BDNZ8 ||
613  SecondLastInst.getOpcode() == PPC::BDNZ) &&
614  LastInst.getOpcode() == PPC::B) {
615  if (!SecondLastInst.getOperand(0).isMBB() ||
616  !LastInst.getOperand(0).isMBB())
617  return true;
618  if (DisableCTRLoopAnal)
619  return true;
620  TBB = SecondLastInst.getOperand(0).getMBB();
622  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
623  true));
624  FBB = LastInst.getOperand(0).getMBB();
625  return false;
626  } else if ((SecondLastInst.getOpcode() == PPC::BDZ8 ||
627  SecondLastInst.getOpcode() == PPC::BDZ) &&
628  LastInst.getOpcode() == PPC::B) {
629  if (!SecondLastInst.getOperand(0).isMBB() ||
630  !LastInst.getOperand(0).isMBB())
631  return true;
632  if (DisableCTRLoopAnal)
633  return true;
634  TBB = SecondLastInst.getOperand(0).getMBB();
636  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
637  true));
638  FBB = LastInst.getOperand(0).getMBB();
639  return false;
640  }
641 
642  // If the block ends with two PPC:Bs, handle it. The second one is not
643  // executed, so remove it.
644  if (SecondLastInst.getOpcode() == PPC::B && LastInst.getOpcode() == PPC::B) {
645  if (!SecondLastInst.getOperand(0).isMBB())
646  return true;
647  TBB = SecondLastInst.getOperand(0).getMBB();
648  I = LastInst;
649  if (AllowModify)
650  I->eraseFromParent();
651  return false;
652  }
653 
654  // Otherwise, can't handle this.
655  return true;
656 }
657 
659  int *BytesRemoved) const {
660  assert(!BytesRemoved && "code size not handled");
661 
663  if (I == MBB.end())
664  return 0;
665 
666  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
667  I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
668  I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
669  I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
670  return 0;
671 
672  // Remove the branch.
673  I->eraseFromParent();
674 
675  I = MBB.end();
676 
677  if (I == MBB.begin()) return 1;
678  --I;
679  if (I->getOpcode() != PPC::BCC &&
680  I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
681  I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
682  I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
683  return 1;
684 
685  // Remove the branch.
686  I->eraseFromParent();
687  return 2;
688 }
689 
691  MachineBasicBlock *TBB,
692  MachineBasicBlock *FBB,
694  const DebugLoc &DL,
695  int *BytesAdded) const {
696  // Shouldn't be a fall through.
697  assert(TBB && "insertBranch must not be told to insert a fallthrough");
698  assert((Cond.size() == 2 || Cond.size() == 0) &&
699  "PPC branch conditions have two components!");
700  assert(!BytesAdded && "code size not handled");
701 
702  bool isPPC64 = Subtarget.isPPC64();
703 
704  // One-way branch.
705  if (!FBB) {
706  if (Cond.empty()) // Unconditional branch
707  BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
708  else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
709  BuildMI(&MBB, DL, get(Cond[0].getImm() ?
710  (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
711  (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
712  else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
713  BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
714  else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
715  BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
716  else // Conditional branch
717  BuildMI(&MBB, DL, get(PPC::BCC))
718  .addImm(Cond[0].getImm())
719  .add(Cond[1])
720  .addMBB(TBB);
721  return 1;
722  }
723 
724  // Two-way Conditional Branch.
725  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
726  BuildMI(&MBB, DL, get(Cond[0].getImm() ?
727  (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
728  (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
729  else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
730  BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
731  else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
732  BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
733  else
734  BuildMI(&MBB, DL, get(PPC::BCC))
735  .addImm(Cond[0].getImm())
736  .add(Cond[1])
737  .addMBB(TBB);
738  BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
739  return 2;
740 }
741 
742 // Select analysis.
745  unsigned TrueReg, unsigned FalseReg,
746  int &CondCycles, int &TrueCycles, int &FalseCycles) const {
747  if (Cond.size() != 2)
748  return false;
749 
750  // If this is really a bdnz-like condition, then it cannot be turned into a
751  // select.
752  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
753  return false;
754 
755  // Check register classes.
756  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
757  const TargetRegisterClass *RC =
758  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
759  if (!RC)
760  return false;
761 
762  // isel is for regular integer GPRs only.
763  if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
764  !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
765  !PPC::G8RCRegClass.hasSubClassEq(RC) &&
766  !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
767  return false;
768 
769  // FIXME: These numbers are for the A2, how well they work for other cores is
770  // an open question. On the A2, the isel instruction has a 2-cycle latency
771  // but single-cycle throughput. These numbers are used in combination with
772  // the MispredictPenalty setting from the active SchedMachineModel.
773  CondCycles = 1;
774  TrueCycles = 1;
775  FalseCycles = 1;
776 
777  return true;
778 }
779 
782  const DebugLoc &dl, unsigned DestReg,
783  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
784  unsigned FalseReg) const {
785  assert(Cond.size() == 2 &&
786  "PPC branch conditions have two components!");
787 
788  // Get the register classes.
790  const TargetRegisterClass *RC =
791  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
792  assert(RC && "TrueReg and FalseReg must have overlapping register classes");
793 
794  bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
795  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
796  assert((Is64Bit ||
797  PPC::GPRCRegClass.hasSubClassEq(RC) ||
798  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
799  "isel is for regular integer GPRs only");
800 
801  unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
802  auto SelectPred = static_cast<PPC::Predicate>(Cond[0].getImm());
803 
804  unsigned SubIdx = 0;
805  bool SwapOps = false;
806  switch (SelectPred) {
807  case PPC::PRED_EQ:
808  case PPC::PRED_EQ_MINUS:
809  case PPC::PRED_EQ_PLUS:
810  SubIdx = PPC::sub_eq; SwapOps = false; break;
811  case PPC::PRED_NE:
812  case PPC::PRED_NE_MINUS:
813  case PPC::PRED_NE_PLUS:
814  SubIdx = PPC::sub_eq; SwapOps = true; break;
815  case PPC::PRED_LT:
816  case PPC::PRED_LT_MINUS:
817  case PPC::PRED_LT_PLUS:
818  SubIdx = PPC::sub_lt; SwapOps = false; break;
819  case PPC::PRED_GE:
820  case PPC::PRED_GE_MINUS:
821  case PPC::PRED_GE_PLUS:
822  SubIdx = PPC::sub_lt; SwapOps = true; break;
823  case PPC::PRED_GT:
824  case PPC::PRED_GT_MINUS:
825  case PPC::PRED_GT_PLUS:
826  SubIdx = PPC::sub_gt; SwapOps = false; break;
827  case PPC::PRED_LE:
828  case PPC::PRED_LE_MINUS:
829  case PPC::PRED_LE_PLUS:
830  SubIdx = PPC::sub_gt; SwapOps = true; break;
831  case PPC::PRED_UN:
832  case PPC::PRED_UN_MINUS:
833  case PPC::PRED_UN_PLUS:
834  SubIdx = PPC::sub_un; SwapOps = false; break;
835  case PPC::PRED_NU:
836  case PPC::PRED_NU_MINUS:
837  case PPC::PRED_NU_PLUS:
838  SubIdx = PPC::sub_un; SwapOps = true; break;
839  case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break;
840  case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break;
841  }
842 
843  unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
844  SecondReg = SwapOps ? TrueReg : FalseReg;
845 
846  // The first input register of isel cannot be r0. If it is a member
847  // of a register class that can be r0, then copy it first (the
848  // register allocator should eliminate the copy).
849  if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
850  MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
851  const TargetRegisterClass *FirstRC =
852  MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
853  &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
854  unsigned OldFirstReg = FirstReg;
855  FirstReg = MRI.createVirtualRegister(FirstRC);
856  BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
857  .addReg(OldFirstReg);
858  }
859 
860  BuildMI(MBB, MI, dl, get(OpCode), DestReg)
861  .addReg(FirstReg).addReg(SecondReg)
862  .addReg(Cond[1].getReg(), 0, SubIdx);
863 }
864 
865 static unsigned getCRBitValue(unsigned CRBit) {
866  unsigned Ret = 4;
867  if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT ||
868  CRBit == PPC::CR2LT || CRBit == PPC::CR3LT ||
869  CRBit == PPC::CR4LT || CRBit == PPC::CR5LT ||
870  CRBit == PPC::CR6LT || CRBit == PPC::CR7LT)
871  Ret = 3;
872  if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT ||
873  CRBit == PPC::CR2GT || CRBit == PPC::CR3GT ||
874  CRBit == PPC::CR4GT || CRBit == PPC::CR5GT ||
875  CRBit == PPC::CR6GT || CRBit == PPC::CR7GT)
876  Ret = 2;
877  if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ ||
878  CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ ||
879  CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ ||
880  CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ)
881  Ret = 1;
882  if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN ||
883  CRBit == PPC::CR2UN || CRBit == PPC::CR3UN ||
884  CRBit == PPC::CR4UN || CRBit == PPC::CR5UN ||
885  CRBit == PPC::CR6UN || CRBit == PPC::CR7UN)
886  Ret = 0;
887 
888  assert(Ret != 4 && "Invalid CR bit register");
889  return Ret;
890 }
891 
894  const DebugLoc &DL, unsigned DestReg,
895  unsigned SrcReg, bool KillSrc) const {
896  // We can end up with self copies and similar things as a result of VSX copy
897  // legalization. Promote them here.
899  if (PPC::F8RCRegClass.contains(DestReg) &&
900  PPC::VSRCRegClass.contains(SrcReg)) {
901  unsigned SuperReg =
902  TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
903 
904  if (VSXSelfCopyCrash && SrcReg == SuperReg)
905  llvm_unreachable("nop VSX copy");
906 
907  DestReg = SuperReg;
908  } else if (PPC::F8RCRegClass.contains(SrcReg) &&
909  PPC::VSRCRegClass.contains(DestReg)) {
910  unsigned SuperReg =
911  TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
912 
913  if (VSXSelfCopyCrash && DestReg == SuperReg)
914  llvm_unreachable("nop VSX copy");
915 
916  SrcReg = SuperReg;
917  }
918 
919  // Different class register copy
920  if (PPC::CRBITRCRegClass.contains(SrcReg) &&
921  PPC::GPRCRegClass.contains(DestReg)) {
922  unsigned CRReg = getCRFromCRBit(SrcReg);
923  BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg);
924  getKillRegState(KillSrc);
925  // Rotate the CR bit in the CR fields to be the least significant bit and
926  // then mask with 0x1 (MB = ME = 31).
927  BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
928  .addReg(DestReg, RegState::Kill)
929  .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
930  .addImm(31)
931  .addImm(31);
932  return;
933  } else if (PPC::CRRCRegClass.contains(SrcReg) &&
934  PPC::G8RCRegClass.contains(DestReg)) {
935  BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg).addReg(SrcReg);
936  getKillRegState(KillSrc);
937  return;
938  } else if (PPC::CRRCRegClass.contains(SrcReg) &&
939  PPC::GPRCRegClass.contains(DestReg)) {
940  BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(SrcReg);
941  getKillRegState(KillSrc);
942  return;
943  } else if (PPC::G8RCRegClass.contains(SrcReg) &&
944  PPC::VSFRCRegClass.contains(DestReg)) {
945  BuildMI(MBB, I, DL, get(PPC::MTVSRD), DestReg).addReg(SrcReg);
946  NumGPRtoVSRSpill++;
947  getKillRegState(KillSrc);
948  return;
949  } else if (PPC::VSFRCRegClass.contains(SrcReg) &&
950  PPC::G8RCRegClass.contains(DestReg)) {
951  BuildMI(MBB, I, DL, get(PPC::MFVSRD), DestReg).addReg(SrcReg);
952  getKillRegState(KillSrc);
953  return;
954  } else if (PPC::SPERCRegClass.contains(SrcReg) &&
955  PPC::SPE4RCRegClass.contains(DestReg)) {
956  BuildMI(MBB, I, DL, get(PPC::EFSCFD), DestReg).addReg(SrcReg);
957  getKillRegState(KillSrc);
958  return;
959  } else if (PPC::SPE4RCRegClass.contains(SrcReg) &&
960  PPC::SPERCRegClass.contains(DestReg)) {
961  BuildMI(MBB, I, DL, get(PPC::EFDCFS), DestReg).addReg(SrcReg);
962  getKillRegState(KillSrc);
963  return;
964  }
965 
966 
967  unsigned Opc;
968  if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
969  Opc = PPC::OR;
970  else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
971  Opc = PPC::OR8;
972  else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
973  Opc = PPC::FMR;
974  else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
975  Opc = PPC::MCRF;
976  else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
977  Opc = PPC::VOR;
978  else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
979  // There are two different ways this can be done:
980  // 1. xxlor : This has lower latency (on the P7), 2 cycles, but can only
981  // issue in VSU pipeline 0.
982  // 2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
983  // can go to either pipeline.
984  // We'll always use xxlor here, because in practically all cases where
985  // copies are generated, they are close enough to some use that the
986  // lower-latency form is preferable.
987  Opc = PPC::XXLOR;
988  else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) ||
989  PPC::VSSRCRegClass.contains(DestReg, SrcReg))
990  Opc = (Subtarget.hasP9Vector()) ? PPC::XSCPSGNDP : PPC::XXLORf;
991  else if (PPC::QFRCRegClass.contains(DestReg, SrcReg))
992  Opc = PPC::QVFMR;
993  else if (PPC::QSRCRegClass.contains(DestReg, SrcReg))
994  Opc = PPC::QVFMRs;
995  else if (PPC::QBRCRegClass.contains(DestReg, SrcReg))
996  Opc = PPC::QVFMRb;
997  else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
998  Opc = PPC::CROR;
999  else if (PPC::SPERCRegClass.contains(DestReg, SrcReg))
1000  Opc = PPC::EVOR;
1001  else
1002  llvm_unreachable("Impossible reg-to-reg copy");
1003 
1004  const MCInstrDesc &MCID = get(Opc);
1005  if (MCID.getNumOperands() == 3)
1006  BuildMI(MBB, I, DL, MCID, DestReg)
1007  .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
1008  else
1009  BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
1010 }
1011 
1013  const TargetRegisterClass *RC)
1014  const {
1015  const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
1016  int OpcodeIndex = 0;
1017 
1018  if (RC != nullptr) {
1019  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1020  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1021  OpcodeIndex = SOK_Int4Spill;
1022  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1023  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1024  OpcodeIndex = SOK_Int8Spill;
1025  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1026  OpcodeIndex = SOK_Float8Spill;
1027  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1028  OpcodeIndex = SOK_Float4Spill;
1029  } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1030  OpcodeIndex = SOK_SPESpill;
1031  } else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) {
1032  OpcodeIndex = SOK_SPE4Spill;
1033  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1034  OpcodeIndex = SOK_CRSpill;
1035  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1036  OpcodeIndex = SOK_CRBitSpill;
1037  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1038  OpcodeIndex = SOK_VRVectorSpill;
1039  } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1040  OpcodeIndex = SOK_VSXVectorSpill;
1041  } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1042  OpcodeIndex = SOK_VectorFloat8Spill;
1043  } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1044  OpcodeIndex = SOK_VectorFloat4Spill;
1045  } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1046  OpcodeIndex = SOK_VRSaveSpill;
1047  } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1048  OpcodeIndex = SOK_QuadFloat8Spill;
1049  } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1050  OpcodeIndex = SOK_QuadFloat4Spill;
1051  } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1052  OpcodeIndex = SOK_QuadBitSpill;
1053  } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1054  OpcodeIndex = SOK_SpillToVSR;
1055  } else {
1056  llvm_unreachable("Unknown regclass!");
1057  }
1058  } else {
1059  if (PPC::GPRCRegClass.contains(Reg) ||
1060  PPC::GPRC_NOR0RegClass.contains(Reg)) {
1061  OpcodeIndex = SOK_Int4Spill;
1062  } else if (PPC::G8RCRegClass.contains(Reg) ||
1063  PPC::G8RC_NOX0RegClass.contains(Reg)) {
1064  OpcodeIndex = SOK_Int8Spill;
1065  } else if (PPC::F8RCRegClass.contains(Reg)) {
1066  OpcodeIndex = SOK_Float8Spill;
1067  } else if (PPC::F4RCRegClass.contains(Reg)) {
1068  OpcodeIndex = SOK_Float4Spill;
1069  } else if (PPC::CRRCRegClass.contains(Reg)) {
1070  OpcodeIndex = SOK_CRSpill;
1071  } else if (PPC::CRBITRCRegClass.contains(Reg)) {
1072  OpcodeIndex = SOK_CRBitSpill;
1073  } else if (PPC::VRRCRegClass.contains(Reg)) {
1074  OpcodeIndex = SOK_VRVectorSpill;
1075  } else if (PPC::VSRCRegClass.contains(Reg)) {
1076  OpcodeIndex = SOK_VSXVectorSpill;
1077  } else if (PPC::VSFRCRegClass.contains(Reg)) {
1078  OpcodeIndex = SOK_VectorFloat8Spill;
1079  } else if (PPC::VSSRCRegClass.contains(Reg)) {
1080  OpcodeIndex = SOK_VectorFloat4Spill;
1081  } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1082  OpcodeIndex = SOK_VRSaveSpill;
1083  } else if (PPC::QFRCRegClass.contains(Reg)) {
1084  OpcodeIndex = SOK_QuadFloat8Spill;
1085  } else if (PPC::QSRCRegClass.contains(Reg)) {
1086  OpcodeIndex = SOK_QuadFloat4Spill;
1087  } else if (PPC::QBRCRegClass.contains(Reg)) {
1088  OpcodeIndex = SOK_QuadBitSpill;
1089  } else if (PPC::SPILLTOVSRRCRegClass.contains(Reg)) {
1090  OpcodeIndex = SOK_SpillToVSR;
1091  } else {
1092  llvm_unreachable("Unknown regclass!");
1093  }
1094  }
1095  return OpcodesForSpill[OpcodeIndex];
1096 }
1097 
1098 unsigned
1100  const TargetRegisterClass *RC) const {
1101  const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
1102  int OpcodeIndex = 0;
1103 
1104  if (RC != nullptr) {
1105  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1106  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1107  OpcodeIndex = SOK_Int4Spill;
1108  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1109  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1110  OpcodeIndex = SOK_Int8Spill;
1111  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1112  OpcodeIndex = SOK_Float8Spill;
1113  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1114  OpcodeIndex = SOK_Float4Spill;
1115  } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1116  OpcodeIndex = SOK_SPESpill;
1117  } else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) {
1118  OpcodeIndex = SOK_SPE4Spill;
1119  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1120  OpcodeIndex = SOK_CRSpill;
1121  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1122  OpcodeIndex = SOK_CRBitSpill;
1123  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1124  OpcodeIndex = SOK_VRVectorSpill;
1125  } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1126  OpcodeIndex = SOK_VSXVectorSpill;
1127  } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1128  OpcodeIndex = SOK_VectorFloat8Spill;
1129  } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1130  OpcodeIndex = SOK_VectorFloat4Spill;
1131  } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1132  OpcodeIndex = SOK_VRSaveSpill;
1133  } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1134  OpcodeIndex = SOK_QuadFloat8Spill;
1135  } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1136  OpcodeIndex = SOK_QuadFloat4Spill;
1137  } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1138  OpcodeIndex = SOK_QuadBitSpill;
1139  } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1140  OpcodeIndex = SOK_SpillToVSR;
1141  } else {
1142  llvm_unreachable("Unknown regclass!");
1143  }
1144  } else {
1145  if (PPC::GPRCRegClass.contains(Reg) ||
1146  PPC::GPRC_NOR0RegClass.contains(Reg)) {
1147  OpcodeIndex = SOK_Int4Spill;
1148  } else if (PPC::G8RCRegClass.contains(Reg) ||
1149  PPC::G8RC_NOX0RegClass.contains(Reg)) {
1150  OpcodeIndex = SOK_Int8Spill;
1151  } else if (PPC::F8RCRegClass.contains(Reg)) {
1152  OpcodeIndex = SOK_Float8Spill;
1153  } else if (PPC::F4RCRegClass.contains(Reg)) {
1154  OpcodeIndex = SOK_Float4Spill;
1155  } else if (PPC::CRRCRegClass.contains(Reg)) {
1156  OpcodeIndex = SOK_CRSpill;
1157  } else if (PPC::CRBITRCRegClass.contains(Reg)) {
1158  OpcodeIndex = SOK_CRBitSpill;
1159  } else if (PPC::VRRCRegClass.contains(Reg)) {
1160  OpcodeIndex = SOK_VRVectorSpill;
1161  } else if (PPC::VSRCRegClass.contains(Reg)) {
1162  OpcodeIndex = SOK_VSXVectorSpill;
1163  } else if (PPC::VSFRCRegClass.contains(Reg)) {
1164  OpcodeIndex = SOK_VectorFloat8Spill;
1165  } else if (PPC::VSSRCRegClass.contains(Reg)) {
1166  OpcodeIndex = SOK_VectorFloat4Spill;
1167  } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1168  OpcodeIndex = SOK_VRSaveSpill;
1169  } else if (PPC::QFRCRegClass.contains(Reg)) {
1170  OpcodeIndex = SOK_QuadFloat8Spill;
1171  } else if (PPC::QSRCRegClass.contains(Reg)) {
1172  OpcodeIndex = SOK_QuadFloat4Spill;
1173  } else if (PPC::QBRCRegClass.contains(Reg)) {
1174  OpcodeIndex = SOK_QuadBitSpill;
1175  } else if (PPC::SPILLTOVSRRCRegClass.contains(Reg)) {
1176  OpcodeIndex = SOK_SpillToVSR;
1177  } else {
1178  llvm_unreachable("Unknown regclass!");
1179  }
1180  }
1181  return OpcodesForSpill[OpcodeIndex];
1182 }
1183 
1184 void PPCInstrInfo::StoreRegToStackSlot(
1185  MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx,
1186  const TargetRegisterClass *RC,
1187  SmallVectorImpl<MachineInstr *> &NewMIs) const {
1188  unsigned Opcode = getStoreOpcodeForSpill(PPC::NoRegister, RC);
1189  DebugLoc DL;
1190 
1191  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1192  FuncInfo->setHasSpills();
1193 
1195  BuildMI(MF, DL, get(Opcode)).addReg(SrcReg, getKillRegState(isKill)),
1196  FrameIdx));
1197 
1198  if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1199  PPC::CRBITRCRegClass.hasSubClassEq(RC))
1200  FuncInfo->setSpillsCR();
1201 
1202  if (PPC::VRSAVERCRegClass.hasSubClassEq(RC))
1203  FuncInfo->setSpillsVRSAVE();
1204 
1205  if (isXFormMemOp(Opcode))
1206  FuncInfo->setHasNonRISpills();
1207 }
1208 
1211  unsigned SrcReg, bool isKill,
1212  int FrameIdx,
1213  const TargetRegisterClass *RC,
1214  const TargetRegisterInfo *TRI) const {
1215  MachineFunction &MF = *MBB.getParent();
1217 
1218  // We need to avoid a situation in which the value from a VRRC register is
1219  // spilled using an Altivec instruction and reloaded into a VSRC register
1220  // using a VSX instruction. The issue with this is that the VSX
1221  // load/store instructions swap the doublewords in the vector and the Altivec
1222  // ones don't. The register classes on the spill/reload may be different if
1223  // the register is defined using an Altivec instruction and is then used by a
1224  // VSX instruction.
1225  RC = updatedRC(RC);
1226 
1227  StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs);
1228 
1229  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1230  MBB.insert(MI, NewMIs[i]);
1231 
1232  const MachineFrameInfo &MFI = MF.getFrameInfo();
1234  MachinePointerInfo::getFixedStack(MF, FrameIdx),
1236  MFI.getObjectAlignment(FrameIdx));
1237  NewMIs.back()->addMemOperand(MF, MMO);
1238 }
1239 
1240 void PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
1241  unsigned DestReg, int FrameIdx,
1242  const TargetRegisterClass *RC,
1244  const {
1245  unsigned Opcode = getLoadOpcodeForSpill(PPC::NoRegister, RC);
1246  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opcode), DestReg),
1247  FrameIdx));
1248  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1249 
1250  if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1251  PPC::CRBITRCRegClass.hasSubClassEq(RC))
1252  FuncInfo->setSpillsCR();
1253 
1254  if (PPC::VRSAVERCRegClass.hasSubClassEq(RC))
1255  FuncInfo->setSpillsVRSAVE();
1256 
1257  if (isXFormMemOp(Opcode))
1258  FuncInfo->setHasNonRISpills();
1259 }
1260 
1261 void
1264  unsigned DestReg, int FrameIdx,
1265  const TargetRegisterClass *RC,
1266  const TargetRegisterInfo *TRI) const {
1267  MachineFunction &MF = *MBB.getParent();
1269  DebugLoc DL;
1270  if (MI != MBB.end()) DL = MI->getDebugLoc();
1271 
1272  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1273  FuncInfo->setHasSpills();
1274 
1275  // We need to avoid a situation in which the value from a VRRC register is
1276  // spilled using an Altivec instruction and reloaded into a VSRC register
1277  // using a VSX instruction. The issue with this is that the VSX
1278  // load/store instructions swap the doublewords in the vector and the Altivec
1279  // ones don't. The register classes on the spill/reload may be different if
1280  // the register is defined using an Altivec instruction and is then used by a
1281  // VSX instruction.
1282  if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
1283  RC = &PPC::VSRCRegClass;
1284 
1285  LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
1286 
1287  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1288  MBB.insert(MI, NewMIs[i]);
1289 
1290  const MachineFrameInfo &MFI = MF.getFrameInfo();
1292  MachinePointerInfo::getFixedStack(MF, FrameIdx),
1294  MFI.getObjectAlignment(FrameIdx));
1295  NewMIs.back()->addMemOperand(MF, MMO);
1296 }
1297 
1298 bool PPCInstrInfo::
1300  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
1301  if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
1302  Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
1303  else
1304  // Leave the CR# the same, but invert the condition.
1305  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
1306  return false;
1307 }
1308 
1310  unsigned Reg, MachineRegisterInfo *MRI) const {
1311  // For some instructions, it is legal to fold ZERO into the RA register field.
1312  // A zero immediate should always be loaded with a single li.
1313  unsigned DefOpc = DefMI.getOpcode();
1314  if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
1315  return false;
1316  if (!DefMI.getOperand(1).isImm())
1317  return false;
1318  if (DefMI.getOperand(1).getImm() != 0)
1319  return false;
1320 
1321  // Note that we cannot here invert the arguments of an isel in order to fold
1322  // a ZERO into what is presented as the second argument. All we have here
1323  // is the condition bit, and that might come from a CR-logical bit operation.
1324 
1325  const MCInstrDesc &UseMCID = UseMI.getDesc();
1326 
1327  // Only fold into real machine instructions.
1328  if (UseMCID.isPseudo())
1329  return false;
1330 
1331  unsigned UseIdx;
1332  for (UseIdx = 0; UseIdx < UseMI.getNumOperands(); ++UseIdx)
1333  if (UseMI.getOperand(UseIdx).isReg() &&
1334  UseMI.getOperand(UseIdx).getReg() == Reg)
1335  break;
1336 
1337  assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI");
1338  assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
1339 
1340  const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
1341 
1342  // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
1343  // register (which might also be specified as a pointer class kind).
1344  if (UseInfo->isLookupPtrRegClass()) {
1345  if (UseInfo->RegClass /* Kind */ != 1)
1346  return false;
1347  } else {
1348  if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
1349  UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
1350  return false;
1351  }
1352 
1353  // Make sure this is not tied to an output register (or otherwise
1354  // constrained). This is true for ST?UX registers, for example, which
1355  // are tied to their output registers.
1356  if (UseInfo->Constraints != 0)
1357  return false;
1358 
1359  unsigned ZeroReg;
1360  if (UseInfo->isLookupPtrRegClass()) {
1361  bool isPPC64 = Subtarget.isPPC64();
1362  ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
1363  } else {
1364  ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
1365  PPC::ZERO8 : PPC::ZERO;
1366  }
1367 
1368  bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1369  UseMI.getOperand(UseIdx).setReg(ZeroReg);
1370 
1371  if (DeleteDef)
1372  DefMI.eraseFromParent();
1373 
1374  return true;
1375 }
1376 
1378  for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
1379  I != IE; ++I)
1380  if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
1381  return true;
1382  return false;
1383 }
1384 
1385 // We should make sure that, if we're going to predicate both sides of a
1386 // condition (a diamond), that both sides don't define the counter register. We
1387 // can predicate counter-decrement-based branches, but while that predicates
1388 // the branching, it does not predicate the counter decrement. If we tried to
1389 // merge the triangle into one predicated block, we'd decrement the counter
1390 // twice.
1392  unsigned NumT, unsigned ExtraT,
1393  MachineBasicBlock &FMBB,
1394  unsigned NumF, unsigned ExtraF,
1395  BranchProbability Probability) const {
1396  return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
1397 }
1398 
1399 
1401  // The predicated branches are identified by their type, not really by the
1402  // explicit presence of a predicate. Furthermore, some of them can be
1403  // predicated more than once. Because if conversion won't try to predicate
1404  // any instruction which already claims to be predicated (by returning true
1405  // here), always return false. In doing so, we let isPredicable() be the
1406  // final word on whether not the instruction can be (further) predicated.
1407 
1408  return false;
1409 }
1410 
1412  if (!MI.isTerminator())
1413  return false;
1414 
1415  // Conditional branch is a special case.
1416  if (MI.isBranch() && !MI.isBarrier())
1417  return true;
1418 
1419  return !isPredicated(MI);
1420 }
1421 
1423  ArrayRef<MachineOperand> Pred) const {
1424  unsigned OpC = MI.getOpcode();
1425  if (OpC == PPC::BLR || OpC == PPC::BLR8) {
1426  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1427  bool isPPC64 = Subtarget.isPPC64();
1428  MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR)
1429  : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
1430  } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1431  MI.setDesc(get(PPC::BCLR));
1432  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1433  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1434  MI.setDesc(get(PPC::BCLRn));
1435  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1436  } else {
1437  MI.setDesc(get(PPC::BCCLR));
1439  .addImm(Pred[0].getImm())
1440  .add(Pred[1]);
1441  }
1442 
1443  return true;
1444  } else if (OpC == PPC::B) {
1445  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1446  bool isPPC64 = Subtarget.isPPC64();
1447  MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
1448  : (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
1449  } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1450  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1451  MI.RemoveOperand(0);
1452 
1453  MI.setDesc(get(PPC::BC));
1455  .add(Pred[1])
1456  .addMBB(MBB);
1457  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1458  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1459  MI.RemoveOperand(0);
1460 
1461  MI.setDesc(get(PPC::BCn));
1463  .add(Pred[1])
1464  .addMBB(MBB);
1465  } else {
1466  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1467  MI.RemoveOperand(0);
1468 
1469  MI.setDesc(get(PPC::BCC));
1471  .addImm(Pred[0].getImm())
1472  .add(Pred[1])
1473  .addMBB(MBB);
1474  }
1475 
1476  return true;
1477  } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 || OpC == PPC::BCTRL ||
1478  OpC == PPC::BCTRL8) {
1479  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
1480  llvm_unreachable("Cannot predicate bctr[l] on the ctr register");
1481 
1482  bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
1483  bool isPPC64 = Subtarget.isPPC64();
1484 
1485  if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1486  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8)
1487  : (setLR ? PPC::BCCTRL : PPC::BCCTR)));
1488  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1489  return true;
1490  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1491  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n)
1492  : (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
1493  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1494  return true;
1495  }
1496 
1497  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8)
1498  : (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
1500  .addImm(Pred[0].getImm())
1501  .add(Pred[1]);
1502  return true;
1503  }
1504 
1505  return false;
1506 }
1507 
1509  ArrayRef<MachineOperand> Pred2) const {
1510  assert(Pred1.size() == 2 && "Invalid PPC first predicate");
1511  assert(Pred2.size() == 2 && "Invalid PPC second predicate");
1512 
1513  if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1514  return false;
1515  if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
1516  return false;
1517 
1518  // P1 can only subsume P2 if they test the same condition register.
1519  if (Pred1[1].getReg() != Pred2[1].getReg())
1520  return false;
1521 
1522  PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
1523  PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
1524 
1525  if (P1 == P2)
1526  return true;
1527 
1528  // Does P1 subsume P2, e.g. GE subsumes GT.
1529  if (P1 == PPC::PRED_LE &&
1530  (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
1531  return true;
1532  if (P1 == PPC::PRED_GE &&
1533  (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
1534  return true;
1535 
1536  return false;
1537 }
1538 
1540  std::vector<MachineOperand> &Pred) const {
1541  // Note: At the present time, the contents of Pred from this function is
1542  // unused by IfConversion. This implementation follows ARM by pushing the
1543  // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
1544  // predicate, instructions defining CTR or CTR8 are also included as
1545  // predicate-defining instructions.
1546 
1547  const TargetRegisterClass *RCs[] =
1548  { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1549  &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1550 
1551  bool Found = false;
1552  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1553  const MachineOperand &MO = MI.getOperand(i);
1554  for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
1555  const TargetRegisterClass *RC = RCs[c];
1556  if (MO.isReg()) {
1557  if (MO.isDef() && RC->contains(MO.getReg())) {
1558  Pred.push_back(MO);
1559  Found = true;
1560  }
1561  } else if (MO.isRegMask()) {
1562  for (TargetRegisterClass::iterator I = RC->begin(),
1563  IE = RC->end(); I != IE; ++I)
1564  if (MO.clobbersPhysReg(*I)) {
1565  Pred.push_back(MO);
1566  Found = true;
1567  }
1568  }
1569  }
1570  }
1571 
1572  return Found;
1573 }
1574 
1576  unsigned OpC = MI.getOpcode();
1577  switch (OpC) {
1578  default:
1579  return false;
1580  case PPC::B:
1581  case PPC::BLR:
1582  case PPC::BLR8:
1583  case PPC::BCTR:
1584  case PPC::BCTR8:
1585  case PPC::BCTRL:
1586  case PPC::BCTRL8:
1587  return true;
1588  }
1589 }
1590 
1591 bool PPCInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1592  unsigned &SrcReg2, int &Mask,
1593  int &Value) const {
1594  unsigned Opc = MI.getOpcode();
1595 
1596  switch (Opc) {
1597  default: return false;
1598  case PPC::CMPWI:
1599  case PPC::CMPLWI:
1600  case PPC::CMPDI:
1601  case PPC::CMPLDI:
1602  SrcReg = MI.getOperand(1).getReg();
1603  SrcReg2 = 0;
1604  Value = MI.getOperand(2).getImm();
1605  Mask = 0xFFFF;
1606  return true;
1607  case PPC::CMPW:
1608  case PPC::CMPLW:
1609  case PPC::CMPD:
1610  case PPC::CMPLD:
1611  case PPC::FCMPUS:
1612  case PPC::FCMPUD:
1613  SrcReg = MI.getOperand(1).getReg();
1614  SrcReg2 = MI.getOperand(2).getReg();
1615  Value = 0;
1616  Mask = 0;
1617  return true;
1618  }
1619 }
1620 
1621 bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1622  unsigned SrcReg2, int Mask, int Value,
1623  const MachineRegisterInfo *MRI) const {
1624  if (DisableCmpOpt)
1625  return false;
1626 
1627  int OpC = CmpInstr.getOpcode();
1628  unsigned CRReg = CmpInstr.getOperand(0).getReg();
1629 
1630  // FP record forms set CR1 based on the exception status bits, not a
1631  // comparison with zero.
1632  if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
1633  return false;
1634 
1635  // The record forms set the condition register based on a signed comparison
1636  // with zero (so says the ISA manual). This is not as straightforward as it
1637  // seems, however, because this is always a 64-bit comparison on PPC64, even
1638  // for instructions that are 32-bit in nature (like slw for example).
1639  // So, on PPC32, for unsigned comparisons, we can use the record forms only
1640  // for equality checks (as those don't depend on the sign). On PPC64,
1641  // we are restricted to equality for unsigned 64-bit comparisons and for
1642  // signed 32-bit comparisons the applicability is more restricted.
1643  bool isPPC64 = Subtarget.isPPC64();
1644  bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
1645  bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
1646  bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
1647 
1648  // Get the unique definition of SrcReg.
1649  MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1650  if (!MI) return false;
1651 
1652  bool equalityOnly = false;
1653  bool noSub = false;
1654  if (isPPC64) {
1655  if (is32BitSignedCompare) {
1656  // We can perform this optimization only if MI is sign-extending.
1657  if (isSignExtended(*MI))
1658  noSub = true;
1659  else
1660  return false;
1661  } else if (is32BitUnsignedCompare) {
1662  // We can perform this optimization, equality only, if MI is
1663  // zero-extending.
1664  if (isZeroExtended(*MI)) {
1665  noSub = true;
1666  equalityOnly = true;
1667  } else
1668  return false;
1669  } else
1670  equalityOnly = is64BitUnsignedCompare;
1671  } else
1672  equalityOnly = is32BitUnsignedCompare;
1673 
1674  if (equalityOnly) {
1675  // We need to check the uses of the condition register in order to reject
1676  // non-equality comparisons.
1678  I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1679  I != IE; ++I) {
1680  MachineInstr *UseMI = &*I;
1681  if (UseMI->getOpcode() == PPC::BCC) {
1682  PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
1683  unsigned PredCond = PPC::getPredicateCondition(Pred);
1684  // We ignore hint bits when checking for non-equality comparisons.
1685  if (PredCond != PPC::PRED_EQ && PredCond != PPC::PRED_NE)
1686  return false;
1687  } else if (UseMI->getOpcode() == PPC::ISEL ||
1688  UseMI->getOpcode() == PPC::ISEL8) {
1689  unsigned SubIdx = UseMI->getOperand(3).getSubReg();
1690  if (SubIdx != PPC::sub_eq)
1691  return false;
1692  } else
1693  return false;
1694  }
1695  }
1696 
1697  MachineBasicBlock::iterator I = CmpInstr;
1698 
1699  // Scan forward to find the first use of the compare.
1700  for (MachineBasicBlock::iterator EL = CmpInstr.getParent()->end(); I != EL;
1701  ++I) {
1702  bool FoundUse = false;
1704  J = MRI->use_instr_begin(CRReg), JE = MRI->use_instr_end();
1705  J != JE; ++J)
1706  if (&*J == &*I) {
1707  FoundUse = true;
1708  break;
1709  }
1710 
1711  if (FoundUse)
1712  break;
1713  }
1714 
1717 
1718  // There are two possible candidates which can be changed to set CR[01].
1719  // One is MI, the other is a SUB instruction.
1720  // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
1721  MachineInstr *Sub = nullptr;
1722  if (SrcReg2 != 0)
1723  // MI is not a candidate for CMPrr.
1724  MI = nullptr;
1725  // FIXME: Conservatively refuse to convert an instruction which isn't in the
1726  // same BB as the comparison. This is to allow the check below to avoid calls
1727  // (and other explicit clobbers); instead we should really check for these
1728  // more explicitly (in at least a few predecessors).
1729  else if (MI->getParent() != CmpInstr.getParent())
1730  return false;
1731  else if (Value != 0) {
1732  // The record-form instructions set CR bit based on signed comparison
1733  // against 0. We try to convert a compare against 1 or -1 into a compare
1734  // against 0 to exploit record-form instructions. For example, we change
1735  // the condition "greater than -1" into "greater than or equal to 0"
1736  // and "less than 1" into "less than or equal to 0".
1737 
1738  // Since we optimize comparison based on a specific branch condition,
1739  // we don't optimize if condition code is used by more than once.
1740  if (equalityOnly || !MRI->hasOneUse(CRReg))
1741  return false;
1742 
1743  MachineInstr *UseMI = &*MRI->use_instr_begin(CRReg);
1744  if (UseMI->getOpcode() != PPC::BCC)
1745  return false;
1746 
1747  PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
1748  PPC::Predicate NewPred = Pred;
1749  unsigned PredCond = PPC::getPredicateCondition(Pred);
1750  unsigned PredHint = PPC::getPredicateHint(Pred);
1751  int16_t Immed = (int16_t)Value;
1752 
1753  // When modifying the condition in the predicate, we propagate hint bits
1754  // from the original predicate to the new one.
1755  if (Immed == -1 && PredCond == PPC::PRED_GT)
1756  // We convert "greater than -1" into "greater than or equal to 0",
1757  // since we are assuming signed comparison by !equalityOnly
1758  NewPred = PPC::getPredicate(PPC::PRED_GE, PredHint);
1759  else if (Immed == -1 && PredCond == PPC::PRED_LE)
1760  // We convert "less than or equal to -1" into "less than 0".
1761  NewPred = PPC::getPredicate(PPC::PRED_LT, PredHint);
1762  else if (Immed == 1 && PredCond == PPC::PRED_LT)
1763  // We convert "less than 1" into "less than or equal to 0".
1764  NewPred = PPC::getPredicate(PPC::PRED_LE, PredHint);
1765  else if (Immed == 1 && PredCond == PPC::PRED_GE)
1766  // We convert "greater than or equal to 1" into "greater than 0".
1767  NewPred = PPC::getPredicate(PPC::PRED_GT, PredHint);
1768  else
1769  return false;
1770 
1771  PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1772  NewPred));
1773  }
1774 
1775  // Search for Sub.
1777  --I;
1778 
1779  // Get ready to iterate backward from CmpInstr.
1780  MachineBasicBlock::iterator E = MI, B = CmpInstr.getParent()->begin();
1781 
1782  for (; I != E && !noSub; --I) {
1783  const MachineInstr &Instr = *I;
1784  unsigned IOpC = Instr.getOpcode();
1785 
1786  if (&*I != &CmpInstr && (Instr.modifiesRegister(PPC::CR0, TRI) ||
1787  Instr.readsRegister(PPC::CR0, TRI)))
1788  // This instruction modifies or uses the record condition register after
1789  // the one we want to change. While we could do this transformation, it
1790  // would likely not be profitable. This transformation removes one
1791  // instruction, and so even forcing RA to generate one move probably
1792  // makes it unprofitable.
1793  return false;
1794 
1795  // Check whether CmpInstr can be made redundant by the current instruction.
1796  if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
1797  OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
1798  (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
1799  ((Instr.getOperand(1).getReg() == SrcReg &&
1800  Instr.getOperand(2).getReg() == SrcReg2) ||
1801  (Instr.getOperand(1).getReg() == SrcReg2 &&
1802  Instr.getOperand(2).getReg() == SrcReg))) {
1803  Sub = &*I;
1804  break;
1805  }
1806 
1807  if (I == B)
1808  // The 'and' is below the comparison instruction.
1809  return false;
1810  }
1811 
1812  // Return false if no candidates exist.
1813  if (!MI && !Sub)
1814  return false;
1815 
1816  // The single candidate is called MI.
1817  if (!MI) MI = Sub;
1818 
1819  int NewOpC = -1;
1820  int MIOpC = MI->getOpcode();
1821  if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8 ||
1822  MIOpC == PPC::ANDISo || MIOpC == PPC::ANDISo8)
1823  NewOpC = MIOpC;
1824  else {
1825  NewOpC = PPC::getRecordFormOpcode(MIOpC);
1826  if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
1827  NewOpC = MIOpC;
1828  }
1829 
1830  // FIXME: On the non-embedded POWER architectures, only some of the record
1831  // forms are fast, and we should use only the fast ones.
1832 
1833  // The defining instruction has a record form (or is already a record
1834  // form). It is possible, however, that we'll need to reverse the condition
1835  // code of the users.
1836  if (NewOpC == -1)
1837  return false;
1838 
1839  // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
1840  // needs to be updated to be based on SUB. Push the condition code
1841  // operands to OperandsToUpdate. If it is safe to remove CmpInstr, the
1842  // condition code of these operands will be modified.
1843  // Here, Value == 0 means we haven't converted comparison against 1 or -1 to
1844  // comparison against 0, which may modify predicate.
1845  bool ShouldSwap = false;
1846  if (Sub && Value == 0) {
1847  ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1848  Sub->getOperand(2).getReg() == SrcReg;
1849 
1850  // The operands to subf are the opposite of sub, so only in the fixed-point
1851  // case, invert the order.
1852  ShouldSwap = !ShouldSwap;
1853  }
1854 
1855  if (ShouldSwap)
1857  I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1858  I != IE; ++I) {
1859  MachineInstr *UseMI = &*I;
1860  if (UseMI->getOpcode() == PPC::BCC) {
1861  PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
1862  unsigned PredCond = PPC::getPredicateCondition(Pred);
1863  assert((!equalityOnly ||
1864  PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE) &&
1865  "Invalid predicate for equality-only optimization");
1866  (void)PredCond; // To suppress warning in release build.
1867  PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1868  PPC::getSwappedPredicate(Pred)));
1869  } else if (UseMI->getOpcode() == PPC::ISEL ||
1870  UseMI->getOpcode() == PPC::ISEL8) {
1871  unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
1872  assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
1873  "Invalid CR bit for equality-only optimization");
1874 
1875  if (NewSubReg == PPC::sub_lt)
1876  NewSubReg = PPC::sub_gt;
1877  else if (NewSubReg == PPC::sub_gt)
1878  NewSubReg = PPC::sub_lt;
1879 
1880  SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)),
1881  NewSubReg));
1882  } else // We need to abort on a user we don't understand.
1883  return false;
1884  }
1885  assert(!(Value != 0 && ShouldSwap) &&
1886  "Non-zero immediate support and ShouldSwap"
1887  "may conflict in updating predicate");
1888 
1889  // Create a new virtual register to hold the value of the CR set by the
1890  // record-form instruction. If the instruction was not previously in
1891  // record form, then set the kill flag on the CR.
1892  CmpInstr.eraseFromParent();
1893 
1895  BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
1896  get(TargetOpcode::COPY), CRReg)
1897  .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
1898 
1899  // Even if CR0 register were dead before, it is alive now since the
1900  // instruction we just built uses it.
1901  MI->clearRegisterDeads(PPC::CR0);
1902 
1903  if (MIOpC != NewOpC) {
1904  // We need to be careful here: we're replacing one instruction with
1905  // another, and we need to make sure that we get all of the right
1906  // implicit uses and defs. On the other hand, the caller may be holding
1907  // an iterator to this instruction, and so we can't delete it (this is
1908  // specifically the case if this is the instruction directly after the
1909  // compare).
1910 
1911  // Rotates are expensive instructions. If we're emitting a record-form
1912  // rotate that can just be an andi/andis, we should just emit that.
1913  if (MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINM8) {
1914  unsigned GPRRes = MI->getOperand(0).getReg();
1915  int64_t SH = MI->getOperand(2).getImm();
1916  int64_t MB = MI->getOperand(3).getImm();
1917  int64_t ME = MI->getOperand(4).getImm();
1918  // We can only do this if both the start and end of the mask are in the
1919  // same halfword.
1920  bool MBInLoHWord = MB >= 16;
1921  bool MEInLoHWord = ME >= 16;
1922  uint64_t Mask = ~0LLU;
1923 
1924  if (MB <= ME && MBInLoHWord == MEInLoHWord && SH == 0) {
1925  Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
1926  // The mask value needs to shift right 16 if we're emitting andis.
1927  Mask >>= MBInLoHWord ? 0 : 16;
1928  NewOpC = MIOpC == PPC::RLWINM ?
1929  (MBInLoHWord ? PPC::ANDIo : PPC::ANDISo) :
1930  (MBInLoHWord ? PPC::ANDIo8 :PPC::ANDISo8);
1931  } else if (MRI->use_empty(GPRRes) && (ME == 31) &&
1932  (ME - MB + 1 == SH) && (MB >= 16)) {
1933  // If we are rotating by the exact number of bits as are in the mask
1934  // and the mask is in the least significant bits of the register,
1935  // that's just an andis. (as long as the GPR result has no uses).
1936  Mask = ((1LLU << 32) - 1) & ~((1LLU << (32 - SH)) - 1);
1937  Mask >>= 16;
1938  NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDISo :PPC::ANDISo8;
1939  }
1940  // If we've set the mask, we can transform.
1941  if (Mask != ~0LLU) {
1942  MI->RemoveOperand(4);
1943  MI->RemoveOperand(3);
1944  MI->getOperand(2).setImm(Mask);
1945  NumRcRotatesConvertedToRcAnd++;
1946  }
1947  } else if (MIOpC == PPC::RLDICL && MI->getOperand(2).getImm() == 0) {
1948  int64_t MB = MI->getOperand(3).getImm();
1949  if (MB >= 48) {
1950  uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
1951  NewOpC = PPC::ANDIo8;
1952  MI->RemoveOperand(3);
1953  MI->getOperand(2).setImm(Mask);
1954  NumRcRotatesConvertedToRcAnd++;
1955  }
1956  }
1957 
1958  const MCInstrDesc &NewDesc = get(NewOpC);
1959  MI->setDesc(NewDesc);
1960 
1961  if (NewDesc.ImplicitDefs)
1962  for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs();
1963  *ImpDefs; ++ImpDefs)
1964  if (!MI->definesRegister(*ImpDefs))
1965  MI->addOperand(*MI->getParent()->getParent(),
1966  MachineOperand::CreateReg(*ImpDefs, true, true));
1967  if (NewDesc.ImplicitUses)
1968  for (const MCPhysReg *ImpUses = NewDesc.getImplicitUses();
1969  *ImpUses; ++ImpUses)
1970  if (!MI->readsRegister(*ImpUses))
1971  MI->addOperand(*MI->getParent()->getParent(),
1972  MachineOperand::CreateReg(*ImpUses, false, true));
1973  }
1974  assert(MI->definesRegister(PPC::CR0) &&
1975  "Record-form instruction does not define cr0?");
1976 
1977  // Modify the condition code of operands in OperandsToUpdate.
1978  // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
1979  // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
1980  for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
1981  PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
1982 
1983  for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
1984  SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
1985 
1986  return true;
1987 }
1988 
1989 /// GetInstSize - Return the number of bytes of code the specified
1990 /// instruction may be. This returns the maximum number of bytes.
1991 ///
1993  unsigned Opcode = MI.getOpcode();
1994 
1995  if (Opcode == PPC::INLINEASM) {
1996  const MachineFunction *MF = MI.getParent()->getParent();
1997  const char *AsmStr = MI.getOperand(0).getSymbolName();
1998  return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1999  } else if (Opcode == TargetOpcode::STACKMAP) {
2000  StackMapOpers Opers(&MI);
2001  return Opers.getNumPatchBytes();
2002  } else if (Opcode == TargetOpcode::PATCHPOINT) {
2003  PatchPointOpers Opers(&MI);
2004  return Opers.getNumPatchBytes();
2005  } else {
2006  return get(Opcode).getSize();
2007  }
2008 }
2009 
2010 std::pair<unsigned, unsigned>
2012  const unsigned Mask = PPCII::MO_ACCESS_MASK;
2013  return std::make_pair(TF & Mask, TF & ~Mask);
2014 }
2015 
2018  using namespace PPCII;
2019  static const std::pair<unsigned, const char *> TargetFlags[] = {
2020  {MO_LO, "ppc-lo"},
2021  {MO_HA, "ppc-ha"},
2022  {MO_TPREL_LO, "ppc-tprel-lo"},
2023  {MO_TPREL_HA, "ppc-tprel-ha"},
2024  {MO_DTPREL_LO, "ppc-dtprel-lo"},
2025  {MO_TLSLD_LO, "ppc-tlsld-lo"},
2026  {MO_TOC_LO, "ppc-toc-lo"},
2027  {MO_TLS, "ppc-tls"}};
2028  return makeArrayRef(TargetFlags);
2029 }
2030 
2033  using namespace PPCII;
2034  static const std::pair<unsigned, const char *> TargetFlags[] = {
2035  {MO_PLT, "ppc-plt"},
2036  {MO_PIC_FLAG, "ppc-pic"},
2037  {MO_NLP_FLAG, "ppc-nlp"},
2038  {MO_NLP_HIDDEN_FLAG, "ppc-nlp-hidden"}};
2039  return makeArrayRef(TargetFlags);
2040 }
2041 
2042 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
2043 // The VSX versions have the advantage of a full 64-register target whereas
2044 // the FP ones have the advantage of lower latency and higher throughput. So
2045 // what we are after is using the faster instructions in low register pressure
2046 // situations and using the larger register file in high register pressure
2047 // situations.
2049  unsigned UpperOpcode, LowerOpcode;
2050  switch (MI.getOpcode()) {
2051  case PPC::DFLOADf32:
2052  UpperOpcode = PPC::LXSSP;
2053  LowerOpcode = PPC::LFS;
2054  break;
2055  case PPC::DFLOADf64:
2056  UpperOpcode = PPC::LXSD;
2057  LowerOpcode = PPC::LFD;
2058  break;
2059  case PPC::DFSTOREf32:
2060  UpperOpcode = PPC::STXSSP;
2061  LowerOpcode = PPC::STFS;
2062  break;
2063  case PPC::DFSTOREf64:
2064  UpperOpcode = PPC::STXSD;
2065  LowerOpcode = PPC::STFD;
2066  break;
2067  case PPC::XFLOADf32:
2068  UpperOpcode = PPC::LXSSPX;
2069  LowerOpcode = PPC::LFSX;
2070  break;
2071  case PPC::XFLOADf64:
2072  UpperOpcode = PPC::LXSDX;
2073  LowerOpcode = PPC::LFDX;
2074  break;
2075  case PPC::XFSTOREf32:
2076  UpperOpcode = PPC::STXSSPX;
2077  LowerOpcode = PPC::STFSX;
2078  break;
2079  case PPC::XFSTOREf64:
2080  UpperOpcode = PPC::STXSDX;
2081  LowerOpcode = PPC::STFDX;
2082  break;
2083  case PPC::LIWAX:
2084  UpperOpcode = PPC::LXSIWAX;
2085  LowerOpcode = PPC::LFIWAX;
2086  break;
2087  case PPC::LIWZX:
2088  UpperOpcode = PPC::LXSIWZX;
2089  LowerOpcode = PPC::LFIWZX;
2090  break;
2091  case PPC::STIWX:
2092  UpperOpcode = PPC::STXSIWX;
2093  LowerOpcode = PPC::STFIWX;
2094  break;
2095  default:
2096  llvm_unreachable("Unknown Operation!");
2097  }
2098 
2099  unsigned TargetReg = MI.getOperand(0).getReg();
2100  unsigned Opcode;
2101  if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) ||
2102  (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31))
2103  Opcode = LowerOpcode;
2104  else
2105  Opcode = UpperOpcode;
2106  MI.setDesc(get(Opcode));
2107  return true;
2108 }
2109 
2110 static bool isAnImmediateOperand(const MachineOperand &MO) {
2111  return MO.isCPI() || MO.isGlobal() || MO.isImm();
2112 }
2113 
2115  auto &MBB = *MI.getParent();
2116  auto DL = MI.getDebugLoc();
2117 
2118  switch (MI.getOpcode()) {
2119  case TargetOpcode::LOAD_STACK_GUARD: {
2120  assert(Subtarget.isTargetLinux() &&
2121  "Only Linux target is expected to contain LOAD_STACK_GUARD");
2122  const int64_t Offset = Subtarget.isPPC64() ? -0x7010 : -0x7008;
2123  const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2;
2124  MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ));
2126  .addImm(Offset)
2127  .addReg(Reg);
2128  return true;
2129  }
2130  case PPC::DFLOADf32:
2131  case PPC::DFLOADf64:
2132  case PPC::DFSTOREf32:
2133  case PPC::DFSTOREf64: {
2134  assert(Subtarget.hasP9Vector() &&
2135  "Invalid D-Form Pseudo-ops on Pre-P9 target.");
2136  assert(MI.getOperand(2).isReg() &&
2138  "D-form op must have register and immediate operands");
2139  return expandVSXMemPseudo(MI);
2140  }
2141  case PPC::XFLOADf32:
2142  case PPC::XFSTOREf32:
2143  case PPC::LIWAX:
2144  case PPC::LIWZX:
2145  case PPC::STIWX: {
2146  assert(Subtarget.hasP8Vector() &&
2147  "Invalid X-Form Pseudo-ops on Pre-P8 target.");
2148  assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
2149  "X-form op must have register and register operands");
2150  return expandVSXMemPseudo(MI);
2151  }
2152  case PPC::XFLOADf64:
2153  case PPC::XFSTOREf64: {
2154  assert(Subtarget.hasVSX() &&
2155  "Invalid X-Form Pseudo-ops on target that has no VSX.");
2156  assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
2157  "X-form op must have register and register operands");
2158  return expandVSXMemPseudo(MI);
2159  }
2160  case PPC::SPILLTOVSR_LD: {
2161  unsigned TargetReg = MI.getOperand(0).getReg();
2162  if (PPC::VSFRCRegClass.contains(TargetReg)) {
2163  MI.setDesc(get(PPC::DFLOADf64));
2164  return expandPostRAPseudo(MI);
2165  }
2166  else
2167  MI.setDesc(get(PPC::LD));
2168  return true;
2169  }
2170  case PPC::SPILLTOVSR_ST: {
2171  unsigned SrcReg = MI.getOperand(0).getReg();
2172  if (PPC::VSFRCRegClass.contains(SrcReg)) {
2173  NumStoreSPILLVSRRCAsVec++;
2174  MI.setDesc(get(PPC::DFSTOREf64));
2175  return expandPostRAPseudo(MI);
2176  } else {
2177  NumStoreSPILLVSRRCAsGpr++;
2178  MI.setDesc(get(PPC::STD));
2179  }
2180  return true;
2181  }
2182  case PPC::SPILLTOVSR_LDX: {
2183  unsigned TargetReg = MI.getOperand(0).getReg();
2184  if (PPC::VSFRCRegClass.contains(TargetReg))
2185  MI.setDesc(get(PPC::LXSDX));
2186  else
2187  MI.setDesc(get(PPC::LDX));
2188  return true;
2189  }
2190  case PPC::SPILLTOVSR_STX: {
2191  unsigned SrcReg = MI.getOperand(0).getReg();
2192  if (PPC::VSFRCRegClass.contains(SrcReg)) {
2193  NumStoreSPILLVSRRCAsVec++;
2194  MI.setDesc(get(PPC::STXSDX));
2195  } else {
2196  NumStoreSPILLVSRRCAsGpr++;
2197  MI.setDesc(get(PPC::STDX));
2198  }
2199  return true;
2200  }
2201 
2202  case PPC::CFENCE8: {
2203  auto Val = MI.getOperand(0).getReg();
2204  BuildMI(MBB, MI, DL, get(PPC::CMPD), PPC::CR7).addReg(Val).addReg(Val);
2205  BuildMI(MBB, MI, DL, get(PPC::CTRL_DEP))
2207  .addReg(PPC::CR7)
2208  .addImm(1);
2209  MI.setDesc(get(PPC::ISYNC));
2210  MI.RemoveOperand(0);
2211  return true;
2212  }
2213  }
2214  return false;
2215 }
2216 
2217 // Essentially a compile-time implementation of a compare->isel sequence.
2218 // It takes two constants to compare, along with the true/false registers
2219 // and the comparison type (as a subreg to a CR field) and returns one
2220 // of the true/false registers, depending on the comparison results.
2221 static unsigned selectReg(int64_t Imm1, int64_t Imm2, unsigned CompareOpc,
2222  unsigned TrueReg, unsigned FalseReg,
2223  unsigned CRSubReg) {
2224  // Signed comparisons. The immediates are assumed to be sign-extended.
2225  if (CompareOpc == PPC::CMPWI || CompareOpc == PPC::CMPDI) {
2226  switch (CRSubReg) {
2227  default: llvm_unreachable("Unknown integer comparison type.");
2228  case PPC::sub_lt:
2229  return Imm1 < Imm2 ? TrueReg : FalseReg;
2230  case PPC::sub_gt:
2231  return Imm1 > Imm2 ? TrueReg : FalseReg;
2232  case PPC::sub_eq:
2233  return Imm1 == Imm2 ? TrueReg : FalseReg;
2234  }
2235  }
2236  // Unsigned comparisons.
2237  else if (CompareOpc == PPC::CMPLWI || CompareOpc == PPC::CMPLDI) {
2238  switch (CRSubReg) {
2239  default: llvm_unreachable("Unknown integer comparison type.");
2240  case PPC::sub_lt:
2241  return (uint64_t)Imm1 < (uint64_t)Imm2 ? TrueReg : FalseReg;
2242  case PPC::sub_gt:
2243  return (uint64_t)Imm1 > (uint64_t)Imm2 ? TrueReg : FalseReg;
2244  case PPC::sub_eq:
2245  return Imm1 == Imm2 ? TrueReg : FalseReg;
2246  }
2247  }
2248  return PPC::NoRegister;
2249 }
2250 
2251 // Replace an instruction with one that materializes a constant (and sets
2252 // CR0 if the original instruction was a record-form instruction).
2254  const LoadImmediateInfo &LII) const {
2255  // Remove existing operands.
2256  int OperandToKeep = LII.SetCR ? 1 : 0;
2257  for (int i = MI.getNumOperands() - 1; i > OperandToKeep; i--)
2258  MI.RemoveOperand(i);
2259 
2260  // Replace the instruction.
2261  if (LII.SetCR) {
2262  MI.setDesc(get(LII.Is64Bit ? PPC::ANDIo8 : PPC::ANDIo));
2263  // Set the immediate.
2265  .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine);
2266  return;
2267  }
2268  else
2269  MI.setDesc(get(LII.Is64Bit ? PPC::LI8 : PPC::LI));
2270 
2271  // Set the immediate.
2273  .addImm(LII.Imm);
2274 }
2275 
2276 MachineInstr *PPCInstrInfo::getForwardingDefMI(
2277  MachineInstr &MI,
2278  unsigned &OpNoForForwarding,
2279  bool &SeenIntermediateUse) const {
2280  OpNoForForwarding = ~0U;
2281  MachineInstr *DefMI = nullptr;
2284  // If we're in SSA, get the defs through the MRI. Otherwise, only look
2285  // within the basic block to see if the register is defined using an LI/LI8.
2286  if (MRI->isSSA()) {
2287  for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
2288  if (!MI.getOperand(i).isReg())
2289  continue;
2290  unsigned Reg = MI.getOperand(i).getReg();
2292  continue;
2293  unsigned TrueReg = TRI->lookThruCopyLike(Reg, MRI);
2295  DefMI = MRI->getVRegDef(TrueReg);
2296  if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8) {
2297  OpNoForForwarding = i;
2298  break;
2299  }
2300  }
2301  }
2302  } else {
2303  // Looking back through the definition for each operand could be expensive,
2304  // so exit early if this isn't an instruction that either has an immediate
2305  // form or is already an immediate form that we can handle.
2306  ImmInstrInfo III;
2307  unsigned Opc = MI.getOpcode();
2308  bool ConvertibleImmForm =
2309  Opc == PPC::CMPWI || Opc == PPC::CMPLWI ||
2310  Opc == PPC::CMPDI || Opc == PPC::CMPLDI ||
2311  Opc == PPC::ADDI || Opc == PPC::ADDI8 ||
2312  Opc == PPC::ORI || Opc == PPC::ORI8 ||
2313  Opc == PPC::XORI || Opc == PPC::XORI8 ||
2314  Opc == PPC::RLDICL || Opc == PPC::RLDICLo ||
2315  Opc == PPC::RLDICL_32 || Opc == PPC::RLDICL_32_64 ||
2316  Opc == PPC::RLWINM || Opc == PPC::RLWINMo ||
2317  Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
2318  if (!instrHasImmForm(MI, III, true) && !ConvertibleImmForm)
2319  return nullptr;
2320 
2321  // Don't convert or %X, %Y, %Y since that's just a register move.
2322  if ((Opc == PPC::OR || Opc == PPC::OR8) &&
2323  MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
2324  return nullptr;
2325  for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
2326  MachineOperand &MO = MI.getOperand(i);
2327  SeenIntermediateUse = false;
2328  if (MO.isReg() && MO.isUse() && !MO.isImplicit()) {
2330  It++;
2331  unsigned Reg = MI.getOperand(i).getReg();
2332  // MachineInstr::readsRegister only returns true if the machine
2333  // instruction reads the exact register or its super-register. It
2334  // does not consider uses of sub-registers which seems like strange
2335  // behaviour. Nonetheless, if we end up with a 64-bit register here,
2336  // get the corresponding 32-bit register to check.
2337  if (PPC::G8RCRegClass.contains(Reg))
2338  Reg = Reg - PPC::X0 + PPC::R0;
2339 
2340  // Is this register defined by some form of add-immediate (including
2341  // load-immediate) within this basic block?
2342  for ( ; It != E; ++It) {
2343  if (It->modifiesRegister(Reg, &getRegisterInfo())) {
2344  switch (It->getOpcode()) {
2345  default: break;
2346  case PPC::LI:
2347  case PPC::LI8:
2348  case PPC::ADDItocL:
2349  case PPC::ADDI:
2350  case PPC::ADDI8:
2351  OpNoForForwarding = i;
2352  return &*It;
2353  }
2354  break;
2355  } else if (It->readsRegister(Reg, &getRegisterInfo()))
2356  // If we see another use of this reg between the def and the MI,
2357  // we want to flat it so the def isn't deleted.
2358  SeenIntermediateUse = true;
2359  }
2360  }
2361  }
2362  }
2363  return OpNoForForwarding == ~0U ? nullptr : DefMI;
2364 }
2365 
2366 const unsigned *PPCInstrInfo::getStoreOpcodesForSpillArray() const {
2367  static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = {
2368  // Power 8
2369  {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
2370  PPC::SPILL_CRBIT, PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX,
2371  PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb,
2372  PPC::SPILLTOVSR_ST, PPC::EVSTDD, PPC::SPESTW},
2373  // Power 9
2374  {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
2375  PPC::SPILL_CRBIT, PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32,
2376  PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb,
2377  PPC::SPILLTOVSR_ST}};
2378 
2379  return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0];
2380 }
2381 
2382 const unsigned *PPCInstrInfo::getLoadOpcodesForSpillArray() const {
2383  static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = {
2384  // Power 8
2385  {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
2386  PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX,
2387  PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
2388  PPC::SPILLTOVSR_LD, PPC::EVLDD, PPC::SPELWZ},
2389  // Power 9
2390  {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
2391  PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, PPC::DFLOADf32,
2392  PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
2393  PPC::SPILLTOVSR_LD}};
2394 
2395  return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0];
2396 }
2397 
2398 // If this instruction has an immediate form and one of its operands is a
2399 // result of a load-immediate or an add-immediate, convert it to
2400 // the immediate form if the constant is in range.
2402  MachineInstr **KilledDef) const {
2403  MachineFunction *MF = MI.getParent()->getParent();
2405  bool PostRA = !MRI->isSSA();
2406  bool SeenIntermediateUse = true;
2407  unsigned ForwardingOperand = ~0U;
2408  MachineInstr *DefMI = getForwardingDefMI(MI, ForwardingOperand,
2409  SeenIntermediateUse);
2410  if (!DefMI)
2411  return false;
2412  assert(ForwardingOperand < MI.getNumOperands() &&
2413  "The forwarding operand needs to be valid at this point");
2414  bool KillFwdDefMI = !SeenIntermediateUse &&
2415  MI.getOperand(ForwardingOperand).isKill();
2416  if (KilledDef && KillFwdDefMI)
2417  *KilledDef = DefMI;
2418 
2419  ImmInstrInfo III;
2420  bool HasImmForm = instrHasImmForm(MI, III, PostRA);
2421  // If this is a reg+reg instruction that has a reg+imm form,
2422  // and one of the operands is produced by an add-immediate,
2423  // try to convert it.
2424  if (HasImmForm && transformToImmFormFedByAdd(MI, III, ForwardingOperand,
2425  *DefMI, KillFwdDefMI))
2426  return true;
2427 
2428  if ((DefMI->getOpcode() != PPC::LI && DefMI->getOpcode() != PPC::LI8) ||
2429  !DefMI->getOperand(1).isImm())
2430  return false;
2431 
2432  int64_t Immediate = DefMI->getOperand(1).getImm();
2433  // Sign-extend to 64-bits.
2434  int64_t SExtImm = ((uint64_t)Immediate & ~0x7FFFuLL) != 0 ?
2435  (Immediate | 0xFFFFFFFFFFFF0000) : Immediate;
2436 
2437  // If this is a reg+reg instruction that has a reg+imm form,
2438  // and one of the operands is produced by LI, convert it now.
2439  if (HasImmForm)
2440  return transformToImmFormFedByLI(MI, III, ForwardingOperand, SExtImm);
2441 
2442  bool ReplaceWithLI = false;
2443  bool Is64BitLI = false;
2444  int64_t NewImm = 0;
2445  bool SetCR = false;
2446  unsigned Opc = MI.getOpcode();
2447  switch (Opc) {
2448  default: return false;
2449 
2450  // FIXME: Any branches conditional on such a comparison can be made
2451  // unconditional. At this time, this happens too infrequently to be worth
2452  // the implementation effort, but if that ever changes, we could convert
2453  // such a pattern here.
2454  case PPC::CMPWI:
2455  case PPC::CMPLWI:
2456  case PPC::CMPDI:
2457  case PPC::CMPLDI: {
2458  // Doing this post-RA would require dataflow analysis to reliably find uses
2459  // of the CR register set by the compare.
2460  if (PostRA)
2461  return false;
2462  // If a compare-immediate is fed by an immediate and is itself an input of
2463  // an ISEL (the most common case) into a COPY of the correct register.
2464  bool Changed = false;
2465  unsigned DefReg = MI.getOperand(0).getReg();
2466  int64_t Comparand = MI.getOperand(2).getImm();
2467  int64_t SExtComparand = ((uint64_t)Comparand & ~0x7FFFuLL) != 0 ?
2468  (Comparand | 0xFFFFFFFFFFFF0000) : Comparand;
2469 
2470  for (auto &CompareUseMI : MRI->use_instructions(DefReg)) {
2471  unsigned UseOpc = CompareUseMI.getOpcode();
2472  if (UseOpc != PPC::ISEL && UseOpc != PPC::ISEL8)
2473  continue;
2474  unsigned CRSubReg = CompareUseMI.getOperand(3).getSubReg();
2475  unsigned TrueReg = CompareUseMI.getOperand(1).getReg();
2476  unsigned FalseReg = CompareUseMI.getOperand(2).getReg();
2477  unsigned RegToCopy = selectReg(SExtImm, SExtComparand, Opc, TrueReg,
2478  FalseReg, CRSubReg);
2479  if (RegToCopy == PPC::NoRegister)
2480  continue;
2481  // Can't use PPC::COPY to copy PPC::ZERO[8]. Convert it to LI[8] 0.
2482  if (RegToCopy == PPC::ZERO || RegToCopy == PPC::ZERO8) {
2483  CompareUseMI.setDesc(get(UseOpc == PPC::ISEL8 ? PPC::LI8 : PPC::LI));
2484  CompareUseMI.getOperand(1).ChangeToImmediate(0);
2485  CompareUseMI.RemoveOperand(3);
2486  CompareUseMI.RemoveOperand(2);
2487  continue;
2488  }
2489  LLVM_DEBUG(
2490  dbgs() << "Found LI -> CMPI -> ISEL, replacing with a copy.\n");
2491  LLVM_DEBUG(DefMI->dump(); MI.dump(); CompareUseMI.dump());
2492  LLVM_DEBUG(dbgs() << "Is converted to:\n");
2493  // Convert to copy and remove unneeded operands.
2494  CompareUseMI.setDesc(get(PPC::COPY));
2495  CompareUseMI.RemoveOperand(3);
2496  CompareUseMI.RemoveOperand(RegToCopy == TrueReg ? 2 : 1);
2497  CmpIselsConverted++;
2498  Changed = true;
2499  LLVM_DEBUG(CompareUseMI.dump());
2500  }
2501  if (Changed)
2502  return true;
2503  // This may end up incremented multiple times since this function is called
2504  // during a fixed-point transformation, but it is only meant to indicate the
2505  // presence of this opportunity.
2506  MissedConvertibleImmediateInstrs++;
2507  return false;
2508  }
2509 
2510  // Immediate forms - may simply be convertable to an LI.
2511  case PPC::ADDI:
2512  case PPC::ADDI8: {
2513  // Does the sum fit in a 16-bit signed field?
2514  int64_t Addend = MI.getOperand(2).getImm();
2515  if (isInt<16>(Addend + SExtImm)) {
2516  ReplaceWithLI = true;
2517  Is64BitLI = Opc == PPC::ADDI8;
2518  NewImm = Addend + SExtImm;
2519  break;
2520  }
2521  return false;
2522  }
2523  case PPC::RLDICL:
2524  case PPC::RLDICLo:
2525  case PPC::RLDICL_32:
2526  case PPC::RLDICL_32_64: {
2527  // Use APInt's rotate function.
2528  int64_t SH = MI.getOperand(2).getImm();
2529  int64_t MB = MI.getOperand(3).getImm();
2530  APInt InVal((Opc == PPC::RLDICL || Opc == PPC::RLDICLo) ?
2531  64 : 32, SExtImm, true);
2532  InVal = InVal.rotl(SH);
2533  uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
2534  InVal &= Mask;
2535  // Can't replace negative values with an LI as that will sign-extend
2536  // and not clear the left bits. If we're setting the CR bit, we will use
2537  // ANDIo which won't sign extend, so that's safe.
2538  if (isUInt<15>(InVal.getSExtValue()) ||
2539  (Opc == PPC::RLDICLo && isUInt<16>(InVal.getSExtValue()))) {
2540  ReplaceWithLI = true;
2541  Is64BitLI = Opc != PPC::RLDICL_32;
2542  NewImm = InVal.getSExtValue();
2543  SetCR = Opc == PPC::RLDICLo;
2544  break;
2545  }
2546  return false;
2547  }
2548  case PPC::RLWINM:
2549  case PPC::RLWINM8:
2550  case PPC::RLWINMo:
2551  case PPC::RLWINM8o: {
2552  int64_t SH = MI.getOperand(2).getImm();
2553  int64_t MB = MI.getOperand(3).getImm();
2554  int64_t ME = MI.getOperand(4).getImm();
2555  APInt InVal(32, SExtImm, true);
2556  InVal = InVal.rotl(SH);
2557  // Set the bits ( MB + 32 ) to ( ME + 32 ).
2558  uint64_t Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
2559  InVal &= Mask;
2560  // Can't replace negative values with an LI as that will sign-extend
2561  // and not clear the left bits. If we're setting the CR bit, we will use
2562  // ANDIo which won't sign extend, so that's safe.
2563  bool ValueFits = isUInt<15>(InVal.getSExtValue());
2564  ValueFits |= ((Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o) &&
2565  isUInt<16>(InVal.getSExtValue()));
2566  if (ValueFits) {
2567  ReplaceWithLI = true;
2568  Is64BitLI = Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
2569  NewImm = InVal.getSExtValue();
2570  SetCR = Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o;
2571  break;
2572  }
2573  return false;
2574  }
2575  case PPC::ORI:
2576  case PPC::ORI8:
2577  case PPC::XORI:
2578  case PPC::XORI8: {
2579  int64_t LogicalImm = MI.getOperand(2).getImm();
2580  int64_t Result = 0;
2581  if (Opc == PPC::ORI || Opc == PPC::ORI8)
2582  Result = LogicalImm | SExtImm;
2583  else
2584  Result = LogicalImm ^ SExtImm;
2585  if (isInt<16>(Result)) {
2586  ReplaceWithLI = true;
2587  Is64BitLI = Opc == PPC::ORI8 || Opc == PPC::XORI8;
2588  NewImm = Result;
2589  break;
2590  }
2591  return false;
2592  }
2593  }
2594 
2595  if (ReplaceWithLI) {
2596  // We need to be careful with CR-setting instructions we're replacing.
2597  if (SetCR) {
2598  // We don't know anything about uses when we're out of SSA, so only
2599  // replace if the new immediate will be reproduced.
2600  bool ImmChanged = (SExtImm & NewImm) != NewImm;
2601  if (PostRA && ImmChanged)
2602  return false;
2603 
2604  if (!PostRA) {
2605  // If the defining load-immediate has no other uses, we can just replace
2606  // the immediate with the new immediate.
2607  if (MRI->hasOneUse(DefMI->getOperand(0).getReg()))
2608  DefMI->getOperand(1).setImm(NewImm);
2609 
2610  // If we're not using the GPR result of the CR-setting instruction, we
2611  // just need to and with zero/non-zero depending on the new immediate.
2612  else if (MRI->use_empty(MI.getOperand(0).getReg())) {
2613  if (NewImm) {
2614  assert(Immediate && "Transformation converted zero to non-zero?");
2615  NewImm = Immediate;
2616  }
2617  }
2618  else if (ImmChanged)
2619  return false;
2620  }
2621  }
2622 
2623  LLVM_DEBUG(dbgs() << "Replacing instruction:\n");
2624  LLVM_DEBUG(MI.dump());
2625  LLVM_DEBUG(dbgs() << "Fed by:\n");
2626  LLVM_DEBUG(DefMI->dump());
2627  LoadImmediateInfo LII;
2628  LII.Imm = NewImm;
2629  LII.Is64Bit = Is64BitLI;
2630  LII.SetCR = SetCR;
2631  // If we're setting the CR, the original load-immediate must be kept (as an
2632  // operand to ANDIo/ANDI8o).
2633  if (KilledDef && SetCR)
2634  *KilledDef = nullptr;
2635  replaceInstrWithLI(MI, LII);
2636  LLVM_DEBUG(dbgs() << "With:\n");
2637  LLVM_DEBUG(MI.dump());
2638  return true;
2639  }
2640  return false;
2641 }
2642 
2643 static bool isVFReg(unsigned Reg) {
2644  return PPC::VFRCRegClass.contains(Reg);
2645 }
2646 
2648  ImmInstrInfo &III, bool PostRA) const {
2649  unsigned Opc = MI.getOpcode();
2650  // The vast majority of the instructions would need their operand 2 replaced
2651  // with an immediate when switching to the reg+imm form. A marked exception
2652  // are the update form loads/stores for which a constant operand 2 would need
2653  // to turn into a displacement and move operand 1 to the operand 2 position.
2654  III.ImmOpNo = 2;
2655  III.OpNoForForwarding = 2;
2656  III.ImmWidth = 16;
2657  III.ImmMustBeMultipleOf = 1;
2658  III.TruncateImmTo = 0;
2659  III.IsSummingOperands = false;
2660  switch (Opc) {
2661  default: return false;
2662  case PPC::ADD4:
2663  case PPC::ADD8:
2664  III.SignedImm = true;
2665  III.ZeroIsSpecialOrig = 0;
2666  III.ZeroIsSpecialNew = 1;
2667  III.IsCommutative = true;
2668  III.IsSummingOperands = true;
2669  III.ImmOpcode = Opc == PPC::ADD4 ? PPC::ADDI : PPC::ADDI8;
2670  break;
2671  case PPC::ADDC:
2672  case PPC::ADDC8:
2673  III.SignedImm = true;
2674  III.ZeroIsSpecialOrig = 0;
2675  III.ZeroIsSpecialNew = 0;
2676  III.IsCommutative = true;
2677  III.IsSummingOperands = true;
2678  III.ImmOpcode = Opc == PPC::ADDC ? PPC::ADDIC : PPC::ADDIC8;
2679  break;
2680  case PPC::ADDCo:
2681  III.SignedImm = true;
2682  III.ZeroIsSpecialOrig = 0;
2683  III.ZeroIsSpecialNew = 0;
2684  III.IsCommutative = true;
2685  III.IsSummingOperands = true;
2686  III.ImmOpcode = PPC::ADDICo;
2687  break;
2688  case PPC::SUBFC:
2689  case PPC::SUBFC8:
2690  III.SignedImm = true;
2691  III.ZeroIsSpecialOrig = 0;
2692  III.ZeroIsSpecialNew = 0;
2693  III.IsCommutative = false;
2694  III.ImmOpcode = Opc == PPC::SUBFC ? PPC::SUBFIC : PPC::SUBFIC8;
2695  break;
2696  case PPC::CMPW:
2697  case PPC::CMPD:
2698  III.SignedImm = true;
2699  III.ZeroIsSpecialOrig = 0;
2700  III.ZeroIsSpecialNew = 0;
2701  III.IsCommutative = false;
2702  III.ImmOpcode = Opc == PPC::CMPW ? PPC::CMPWI : PPC::CMPDI;
2703  break;
2704  case PPC::CMPLW:
2705  case PPC::CMPLD:
2706  III.SignedImm = false;
2707  III.ZeroIsSpecialOrig = 0;
2708  III.ZeroIsSpecialNew = 0;
2709  III.IsCommutative = false;
2710  III.ImmOpcode = Opc == PPC::CMPLW ? PPC::CMPLWI : PPC::CMPLDI;
2711  break;
2712  case PPC::ANDo:
2713  case PPC::AND8o:
2714  case PPC::OR:
2715  case PPC::OR8:
2716  case PPC::XOR:
2717  case PPC::XOR8:
2718  III.SignedImm = false;
2719  III.ZeroIsSpecialOrig = 0;
2720  III.ZeroIsSpecialNew = 0;
2721  III.IsCommutative = true;
2722  switch(Opc) {
2723  default: llvm_unreachable("Unknown opcode");
2724  case PPC::ANDo: III.ImmOpcode = PPC::ANDIo; break;
2725  case PPC::AND8o: III.ImmOpcode = PPC::ANDIo8; break;
2726  case PPC::OR: III.ImmOpcode = PPC::ORI; break;
2727  case PPC::OR8: III.ImmOpcode = PPC::ORI8; break;
2728  case PPC::XOR: III.ImmOpcode = PPC::XORI; break;
2729  case PPC::XOR8: III.ImmOpcode = PPC::XORI8; break;
2730  }
2731  break;
2732  case PPC::RLWNM:
2733  case PPC::RLWNM8:
2734  case PPC::RLWNMo:
2735  case PPC::RLWNM8o:
2736  case PPC::SLW:
2737  case PPC::SLW8:
2738  case PPC::SLWo:
2739  case PPC::SLW8o:
2740  case PPC::SRW:
2741  case PPC::SRW8:
2742  case PPC::SRWo:
2743  case PPC::SRW8o:
2744  case PPC::SRAW:
2745  case PPC::SRAWo:
2746  III.SignedImm = false;
2747  III.ZeroIsSpecialOrig = 0;
2748  III.ZeroIsSpecialNew = 0;
2749  III.IsCommutative = false;
2750  // This isn't actually true, but the instructions ignore any of the
2751  // upper bits, so any immediate loaded with an LI is acceptable.
2752  // This does not apply to shift right algebraic because a value
2753  // out of range will produce a -1/0.
2754  III.ImmWidth = 16;
2755  if (Opc == PPC::RLWNM || Opc == PPC::RLWNM8 ||
2756  Opc == PPC::RLWNMo || Opc == PPC::RLWNM8o)
2757  III.TruncateImmTo = 5;
2758  else
2759  III.TruncateImmTo = 6;
2760  switch(Opc) {
2761  default: llvm_unreachable("Unknown opcode");
2762  case PPC::RLWNM: III.ImmOpcode = PPC::RLWINM; break;
2763  case PPC::RLWNM8: III.ImmOpcode = PPC::RLWINM8; break;
2764  case PPC::RLWNMo: III.ImmOpcode = PPC::RLWINMo; break;
2765  case PPC::RLWNM8o: III.ImmOpcode = PPC::RLWINM8o; break;
2766  case PPC::SLW: III.ImmOpcode = PPC::RLWINM; break;
2767  case PPC::SLW8: III.ImmOpcode = PPC::RLWINM8; break;
2768  case PPC::SLWo: III.ImmOpcode = PPC::RLWINMo; break;
2769  case PPC::SLW8o: III.ImmOpcode = PPC::RLWINM8o; break;
2770  case PPC::SRW: III.ImmOpcode = PPC::RLWINM; break;
2771  case PPC::SRW8: III.ImmOpcode = PPC::RLWINM8; break;
2772  case PPC::SRWo: III.ImmOpcode = PPC::RLWINMo; break;
2773  case PPC::SRW8o: III.ImmOpcode = PPC::RLWINM8o; break;
2774  case PPC::SRAW:
2775  III.ImmWidth = 5;
2776  III.TruncateImmTo = 0;
2777  III.ImmOpcode = PPC::SRAWI;
2778  break;
2779  case PPC::SRAWo:
2780  III.ImmWidth = 5;
2781  III.TruncateImmTo = 0;
2782  III.ImmOpcode = PPC::SRAWIo;
2783  break;
2784  }
2785  break;
2786  case PPC::RLDCL:
2787  case PPC::RLDCLo:
2788  case PPC::RLDCR:
2789  case PPC::RLDCRo:
2790  case PPC::SLD:
2791  case PPC::SLDo:
2792  case PPC::SRD:
2793  case PPC::SRDo:
2794  case PPC::SRAD:
2795  case PPC::SRADo:
2796  III.SignedImm = false;
2797  III.ZeroIsSpecialOrig = 0;
2798  III.ZeroIsSpecialNew = 0;
2799  III.IsCommutative = false;
2800  // This isn't actually true, but the instructions ignore any of the
2801  // upper bits, so any immediate loaded with an LI is acceptable.
2802  // This does not apply to shift right algebraic because a value
2803  // out of range will produce a -1/0.
2804  III.ImmWidth = 16;
2805  if (Opc == PPC::RLDCL || Opc == PPC::RLDCLo ||
2806  Opc == PPC::RLDCR || Opc == PPC::RLDCRo)
2807  III.TruncateImmTo = 6;
2808  else
2809  III.TruncateImmTo = 7;
2810  switch(Opc) {
2811  default: llvm_unreachable("Unknown opcode");
2812  case PPC::RLDCL: III.ImmOpcode = PPC::RLDICL; break;
2813  case PPC::RLDCLo: III.ImmOpcode = PPC::RLDICLo; break;
2814  case PPC::RLDCR: III.ImmOpcode = PPC::RLDICR; break;
2815  case PPC::RLDCRo: III.ImmOpcode = PPC::RLDICRo; break;
2816  case PPC::SLD: III.ImmOpcode = PPC::RLDICR; break;
2817  case PPC::SLDo: III.ImmOpcode = PPC::RLDICRo; break;
2818  case PPC::SRD: III.ImmOpcode = PPC::RLDICL; break;
2819  case PPC::SRDo: III.ImmOpcode = PPC::RLDICLo; break;
2820  case PPC::SRAD:
2821  III.ImmWidth = 6;
2822  III.TruncateImmTo = 0;
2823  III.ImmOpcode = PPC::SRADI;
2824  break;
2825  case PPC::SRADo:
2826  III.ImmWidth = 6;
2827  III.TruncateImmTo = 0;
2828  III.ImmOpcode = PPC::SRADIo;
2829  break;
2830  }
2831  break;
2832  // Loads and stores:
2833  case PPC::LBZX:
2834  case PPC::LBZX8:
2835  case PPC::LHZX:
2836  case PPC::LHZX8:
2837  case PPC::LHAX:
2838  case PPC::LHAX8:
2839  case PPC::LWZX:
2840  case PPC::LWZX8:
2841  case PPC::LWAX:
2842  case PPC::LDX:
2843  case PPC::LFSX:
2844  case PPC::LFDX:
2845  case PPC::STBX:
2846  case PPC::STBX8:
2847  case PPC::STHX:
2848  case PPC::STHX8:
2849  case PPC::STWX:
2850  case PPC::STWX8:
2851  case PPC::STDX:
2852  case PPC::STFSX:
2853  case PPC::STFDX:
2854  III.SignedImm = true;
2855  III.ZeroIsSpecialOrig = 1;
2856  III.ZeroIsSpecialNew = 2;
2857  III.IsCommutative = true;
2858  III.IsSummingOperands = true;
2859  III.ImmOpNo = 1;
2860  III.OpNoForForwarding = 2;
2861  switch(Opc) {
2862  default: llvm_unreachable("Unknown opcode");
2863  case PPC::LBZX: III.ImmOpcode = PPC::LBZ; break;
2864  case PPC::LBZX8: III.ImmOpcode = PPC::LBZ8; break;
2865  case PPC::LHZX: III.ImmOpcode = PPC::LHZ; break;
2866  case PPC::LHZX8: III.ImmOpcode = PPC::LHZ8; break;
2867  case PPC::LHAX: III.ImmOpcode = PPC::LHA; break;
2868  case PPC::LHAX8: III.ImmOpcode = PPC::LHA8; break;
2869  case PPC::LWZX: III.ImmOpcode = PPC::LWZ; break;
2870  case PPC::LWZX8: III.ImmOpcode = PPC::LWZ8; break;
2871  case PPC::LWAX:
2872  III.ImmOpcode = PPC::LWA;
2873  III.ImmMustBeMultipleOf = 4;
2874  break;
2875  case PPC::LDX: III.ImmOpcode = PPC::LD; III.ImmMustBeMultipleOf = 4; break;
2876  case PPC::LFSX: III.ImmOpcode = PPC::LFS; break;
2877  case PPC::LFDX: III.ImmOpcode = PPC::LFD; break;
2878  case PPC::STBX: III.ImmOpcode = PPC::STB; break;
2879  case PPC::STBX8: III.ImmOpcode = PPC::STB8; break;
2880  case PPC::STHX: III.ImmOpcode = PPC::STH; break;
2881  case PPC::STHX8: III.ImmOpcode = PPC::STH8; break;
2882  case PPC::STWX: III.ImmOpcode = PPC::STW; break;
2883  case PPC::STWX8: III.ImmOpcode = PPC::STW8; break;
2884  case PPC::STDX:
2885  III.ImmOpcode = PPC::STD;
2886  III.ImmMustBeMultipleOf = 4;
2887  break;
2888  case PPC::STFSX: III.ImmOpcode = PPC::STFS; break;
2889  case PPC::STFDX: III.ImmOpcode = PPC::STFD; break;
2890  }
2891  break;
2892  case PPC::LBZUX:
2893  case PPC::LBZUX8:
2894  case PPC::LHZUX:
2895  case PPC::LHZUX8:
2896  case PPC::LHAUX:
2897  case PPC::LHAUX8:
2898  case PPC::LWZUX:
2899  case PPC::LWZUX8:
2900  case PPC::LDUX:
2901  case PPC::LFSUX:
2902  case PPC::LFDUX:
2903  case PPC::STBUX:
2904  case PPC::STBUX8:
2905  case PPC::STHUX:
2906  case PPC::STHUX8:
2907  case PPC::STWUX:
2908  case PPC::STWUX8:
2909  case PPC::STDUX:
2910  case PPC::STFSUX:
2911  case PPC::STFDUX:
2912  III.SignedImm = true;
2913  III.ZeroIsSpecialOrig = 2;
2914  III.ZeroIsSpecialNew = 3;
2915  III.IsCommutative = false;
2916  III.IsSummingOperands = true;
2917  III.ImmOpNo = 2;
2918  III.OpNoForForwarding = 3;
2919  switch(Opc) {
2920  default: llvm_unreachable("Unknown opcode");
2921  case PPC::LBZUX: III.ImmOpcode = PPC::LBZU; break;
2922  case PPC::LBZUX8: III.ImmOpcode = PPC::LBZU8; break;
2923  case PPC::LHZUX: III.ImmOpcode = PPC::LHZU; break;
2924  case PPC::LHZUX8: III.ImmOpcode = PPC::LHZU8; break;
2925  case PPC::LHAUX: III.ImmOpcode = PPC::LHAU; break;
2926  case PPC::LHAUX8: III.ImmOpcode = PPC::LHAU8; break;
2927  case PPC::LWZUX: III.ImmOpcode = PPC::LWZU; break;
2928  case PPC::LWZUX8: III.ImmOpcode = PPC::LWZU8; break;
2929  case PPC::LDUX:
2930  III.ImmOpcode = PPC::LDU;
2931  III.ImmMustBeMultipleOf = 4;
2932  break;
2933  case PPC::LFSUX: III.ImmOpcode = PPC::LFSU; break;
2934  case PPC::LFDUX: III.ImmOpcode = PPC::LFDU; break;
2935  case PPC::STBUX: III.ImmOpcode = PPC::STBU; break;
2936  case PPC::STBUX8: III.ImmOpcode = PPC::STBU8; break;
2937  case PPC::STHUX: III.ImmOpcode = PPC::STHU; break;
2938  case PPC::STHUX8: III.ImmOpcode = PPC::STHU8; break;
2939  case PPC::STWUX: III.ImmOpcode = PPC::STWU; break;
2940  case PPC::STWUX8: III.ImmOpcode = PPC::STWU8; break;
2941  case PPC::STDUX:
2942  III.ImmOpcode = PPC::STDU;
2943  III.ImmMustBeMultipleOf = 4;
2944  break;
2945  case PPC::STFSUX: III.ImmOpcode = PPC::STFSU; break;
2946  case PPC::STFDUX: III.ImmOpcode = PPC::STFDU; break;
2947  }
2948  break;
2949  // Power9 and up only. For some of these, the X-Form version has access to all
2950  // 64 VSR's whereas the D-Form only has access to the VR's. We replace those
2951  // with pseudo-ops pre-ra and for post-ra, we check that the register loaded
2952  // into or stored from is one of the VR registers.
2953  case PPC::LXVX:
2954  case PPC::LXSSPX:
2955  case PPC::LXSDX:
2956  case PPC::STXVX:
2957  case PPC::STXSSPX:
2958  case PPC::STXSDX:
2959  case PPC::XFLOADf32:
2960  case PPC::XFLOADf64:
2961  case PPC::XFSTOREf32:
2962  case PPC::XFSTOREf64:
2963  if (!Subtarget.hasP9Vector())
2964  return false;
2965  III.SignedImm = true;
2966  III.ZeroIsSpecialOrig = 1;
2967  III.ZeroIsSpecialNew = 2;
2968  III.IsCommutative = true;
2969  III.IsSummingOperands = true;
2970  III.ImmOpNo = 1;
2971  III.OpNoForForwarding = 2;
2972  III.ImmMustBeMultipleOf = 4;
2973  switch(Opc) {
2974  default: llvm_unreachable("Unknown opcode");
2975  case PPC::LXVX:
2976  III.ImmOpcode = PPC::LXV;
2977  III.ImmMustBeMultipleOf = 16;
2978  break;
2979  case PPC::LXSSPX:
2980  if (PostRA) {
2981  if (isVFReg(MI.getOperand(0).getReg()))
2982  III.ImmOpcode = PPC::LXSSP;
2983  else {
2984  III.ImmOpcode = PPC::LFS;
2985  III.ImmMustBeMultipleOf = 1;
2986  }
2987  break;
2988  }
2990  case PPC::XFLOADf32:
2991  III.ImmOpcode = PPC::DFLOADf32;
2992  break;
2993  case PPC::LXSDX:
2994  if (PostRA) {
2995  if (isVFReg(MI.getOperand(0).getReg()))
2996  III.ImmOpcode = PPC::LXSD;
2997  else {
2998  III.ImmOpcode = PPC::LFD;
2999  III.ImmMustBeMultipleOf = 1;
3000  }
3001  break;
3002  }
3004  case PPC::XFLOADf64:
3005  III.ImmOpcode = PPC::DFLOADf64;
3006  break;
3007  case PPC::STXVX:
3008  III.ImmOpcode = PPC::STXV;
3009  III.ImmMustBeMultipleOf = 16;
3010  break;
3011  case PPC::STXSSPX:
3012  if (PostRA) {
3013  if (isVFReg(MI.getOperand(0).getReg()))
3014  III.ImmOpcode = PPC::STXSSP;
3015  else {
3016  III.ImmOpcode = PPC::STFS;
3017  III.ImmMustBeMultipleOf = 1;
3018  }
3019  break;
3020  }
3022  case PPC::XFSTOREf32:
3023  III.ImmOpcode = PPC::DFSTOREf32;
3024  break;
3025  case PPC::STXSDX:
3026  if (PostRA) {
3027  if (isVFReg(MI.getOperand(0).getReg()))
3028  III.ImmOpcode = PPC::STXSD;
3029  else {
3030  III.ImmOpcode = PPC::STFD;
3031  III.ImmMustBeMultipleOf = 1;
3032  }
3033  break;
3034  }
3036  case PPC::XFSTOREf64:
3037  III.ImmOpcode = PPC::DFSTOREf64;
3038  break;
3039  }
3040  break;
3041  }
3042  return true;
3043 }
3044 
3045 // Utility function for swaping two arbitrary operands of an instruction.
3046 static void swapMIOperands(MachineInstr &MI, unsigned Op1, unsigned Op2) {
3047  assert(Op1 != Op2 && "Cannot swap operand with itself.");
3048 
3049  unsigned MaxOp = std::max(Op1, Op2);
3050  unsigned MinOp = std::min(Op1, Op2);
3051  MachineOperand MOp1 = MI.getOperand(MinOp);
3052  MachineOperand MOp2 = MI.getOperand(MaxOp);
3053  MI.RemoveOperand(std::max(Op1, Op2));
3054  MI.RemoveOperand(std::min(Op1, Op2));
3055 
3056  // If the operands we are swapping are the two at the end (the common case)
3057  // we can just remove both and add them in the opposite order.
3058  if (MaxOp - MinOp == 1 && MI.getNumOperands() == MinOp) {
3059  MI.addOperand(MOp2);
3060  MI.addOperand(MOp1);
3061  } else {
3062  // Store all operands in a temporary vector, remove them and re-add in the
3063  // right order.
3065  unsigned TotalOps = MI.getNumOperands() + 2; // We've already removed 2 ops.
3066  for (unsigned i = MI.getNumOperands() - 1; i >= MinOp; i--) {
3067  MOps.push_back(MI.getOperand(i));
3068  MI.RemoveOperand(i);
3069  }
3070  // MOp2 needs to be added next.
3071  MI.addOperand(MOp2);
3072  // Now add the rest.
3073  for (unsigned i = MI.getNumOperands(); i < TotalOps; i++) {
3074  if (i == MaxOp)
3075  MI.addOperand(MOp1);
3076  else {
3077  MI.addOperand(MOps.back());
3078  MOps.pop_back();
3079  }
3080  }
3081  }
3082 }
3083 
3084 // Check if the 'MI' that has the index OpNoForForwarding
3085 // meets the requirement described in the ImmInstrInfo.
3086 bool PPCInstrInfo::isUseMIElgibleForForwarding(MachineInstr &MI,
3087  const ImmInstrInfo &III,
3088  unsigned OpNoForForwarding
3089  ) const {
3090  // As the algorithm of checking for PPC::ZERO/PPC::ZERO8
3091  // would not work pre-RA, we can only do the check post RA.
3093  if (MRI.isSSA())
3094  return false;
3095 
3096  // Cannot do the transform if MI isn't summing the operands.
3097  if (!III.IsSummingOperands)
3098  return false;
3099 
3100  // The instruction we are trying to replace must have the ZeroIsSpecialOrig set.
3101  if (!III.ZeroIsSpecialOrig)
3102  return false;
3103 
3104  // We cannot do the transform if the operand we are trying to replace
3105  // isn't the same as the operand the instruction allows.
3106  if (OpNoForForwarding != III.OpNoForForwarding)
3107  return false;
3108 
3109  // Check if the instruction we are trying to transform really has
3110  // the special zero register as its operand.
3111  if (MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO &&
3112  MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO8)
3113  return false;
3114 
3115  // This machine instruction is convertible if it is,
3116  // 1. summing the operands.
3117  // 2. one of the operands is special zero register.
3118  // 3. the operand we are trying to replace is allowed by the MI.
3119  return true;
3120 }
3121 
3122 // Check if the DefMI is the add inst and set the ImmMO and RegMO
3123 // accordingly.
3124 bool PPCInstrInfo::isDefMIElgibleForForwarding(MachineInstr &DefMI,
3125  const ImmInstrInfo &III,
3126  MachineOperand *&ImmMO,
3127  MachineOperand *&RegMO) const {
3128  unsigned Opc = DefMI.getOpcode();
3129  if (Opc != PPC::ADDItocL && Opc != PPC::ADDI && Opc != PPC::ADDI8)
3130  return false;
3131 
3132  assert(DefMI.getNumOperands() >= 3 &&
3133  "Add inst must have at least three operands");
3134  RegMO = &DefMI.getOperand(1);
3135  ImmMO = &DefMI.getOperand(2);
3136 
3137  // This DefMI is elgible for forwarding if it is:
3138  // 1. add inst
3139  // 2. one of the operands is Imm/CPI/Global.
3140  return isAnImmediateOperand(*ImmMO);
3141 }
3142 
3143 bool PPCInstrInfo::isRegElgibleForForwarding(const MachineOperand &RegMO,
3144  const MachineInstr &DefMI,
3145  const MachineInstr &MI,
3146  bool KillDefMI
3147  ) const {
3148  // x = addi y, imm
3149  // ...
3150  // z = lfdx 0, x -> z = lfd imm(y)
3151  // The Reg "y" can be forwarded to the MI(z) only when there is no DEF
3152  // of "y" between the DEF of "x" and "z".
3153  // The query is only valid post RA.
3155  if (MRI.isSSA())
3156  return false;
3157 
3158  // MachineInstr::readsRegister only returns true if the machine
3159  // instruction reads the exact register or its super-register. It
3160  // does not consider uses of sub-registers which seems like strange
3161  // behaviour. Nonetheless, if we end up with a 64-bit register here,
3162  // get the corresponding 32-bit register to check.
3163  unsigned Reg = RegMO.getReg();
3164  if (PPC::G8RCRegClass.contains(Reg))
3165  Reg = Reg - PPC::X0 + PPC::R0;
3166 
3167  // Walking the inst in reverse(MI-->DefMI) to get the last DEF of the Reg.
3170  It++;
3171  for (; It != E; ++It) {
3172  if (It->modifiesRegister(Reg, &getRegisterInfo()) && (&*It) != &DefMI)
3173  return false;
3174  // Made it to DefMI without encountering a clobber.
3175  if ((&*It) == &DefMI)
3176  break;
3177  }
3178  assert((&*It) == &DefMI && "DefMI is missing");
3179 
3180  // If DefMI also uses the register to be forwarded, we can only forward it
3181  // if DefMI is being erased.
3182  if (DefMI.readsRegister(Reg, &getRegisterInfo()))
3183  return KillDefMI;
3184 
3185  return true;
3186 }
3187 
3188 bool PPCInstrInfo::isImmElgibleForForwarding(const MachineOperand &ImmMO,
3189  const MachineInstr &DefMI,
3190  const ImmInstrInfo &III,
3191  int64_t &Imm) const {
3192  assert(isAnImmediateOperand(ImmMO) && "ImmMO is NOT an immediate");
3193  if (DefMI.getOpcode() == PPC::ADDItocL) {
3194  // The operand for ADDItocL is CPI, which isn't imm at compiling time,
3195  // However, we know that, it is 16-bit width, and has the alignment of 4.
3196  // Check if the instruction met the requirement.
3197  if (III.ImmMustBeMultipleOf > 4 ||
3198  III.TruncateImmTo || III.ImmWidth != 16)
3199  return false;
3200 
3201  // Going from XForm to DForm loads means that the displacement needs to be
3202  // not just an immediate but also a multiple of 4, or 16 depending on the
3203  // load. A DForm load cannot be represented if it is a multiple of say 2.
3204  // XForm loads do not have this restriction.
3205  if (ImmMO.isGlobal() &&
3206  ImmMO.getGlobal()->getAlignment() < III.ImmMustBeMultipleOf)
3207  return false;
3208 
3209  return true;
3210  }
3211 
3212  if (ImmMO.isImm()) {
3213  // It is Imm, we need to check if the Imm fit the range.
3214  int64_t Immediate = ImmMO.getImm();
3215  // Sign-extend to 64-bits.
3216  Imm = ((uint64_t)Immediate & ~0x7FFFuLL) != 0 ?
3217  (Immediate | 0xFFFFFFFFFFFF0000) : Immediate;
3218 
3219  if (Imm % III.ImmMustBeMultipleOf)
3220  return false;
3221  if (III.TruncateImmTo)
3222  Imm &= ((1 << III.TruncateImmTo) - 1);
3223  if (III.SignedImm) {
3224  APInt ActualValue(64, Imm, true);
3225  if (!ActualValue.isSignedIntN(III.ImmWidth))
3226  return false;
3227  } else {
3228  uint64_t UnsignedMax = (1 << III.ImmWidth) - 1;
3229  if ((uint64_t)Imm > UnsignedMax)
3230  return false;
3231  }
3232  }
3233  else
3234  return false;
3235 
3236  // This ImmMO is forwarded if it meets the requriement describle
3237  // in ImmInstrInfo
3238  return true;
3239 }
3240 
3241 // If an X-Form instruction is fed by an add-immediate and one of its operands
3242 // is the literal zero, attempt to forward the source of the add-immediate to
3243 // the corresponding D-Form instruction with the displacement coming from
3244 // the immediate being added.
3245 bool PPCInstrInfo::transformToImmFormFedByAdd(MachineInstr &MI,
3246  const ImmInstrInfo &III,
3247  unsigned OpNoForForwarding,
3248  MachineInstr &DefMI,
3249  bool KillDefMI) const {
3250  // RegMO ImmMO
3251  // | |
3252  // x = addi reg, imm <----- DefMI
3253  // y = op 0 , x <----- MI
3254  // |
3255  // OpNoForForwarding
3256  // Check if the MI meet the requirement described in the III.
3257  if (!isUseMIElgibleForForwarding(MI, III, OpNoForForwarding))
3258  return false;
3259 
3260  // Check if the DefMI meet the requirement
3261  // described in the III. If yes, set the ImmMO and RegMO accordingly.
3262  MachineOperand *ImmMO = nullptr;
3263  MachineOperand *RegMO = nullptr;
3264  if (!isDefMIElgibleForForwarding(DefMI, III, ImmMO, RegMO))
3265  return false;
3266  assert(ImmMO && RegMO && "Imm and Reg operand must have been set");
3267 
3268  // As we get the Imm operand now, we need to check if the ImmMO meet
3269  // the requirement described in the III. If yes set the Imm.
3270  int64_t Imm = 0;
3271  if (!isImmElgibleForForwarding(*ImmMO, DefMI, III, Imm))
3272  return false;
3273 
3274  // Check if the RegMO can be forwarded to MI.
3275  if (!isRegElgibleForForwarding(*RegMO, DefMI, MI, KillDefMI))
3276  return false;
3277 
3278  // We know that, the MI and DefMI both meet the pattern, and
3279  // the Imm also meet the requirement with the new Imm-form.
3280  // It is safe to do the transformation now.
3281  LLVM_DEBUG(dbgs() << "Replacing instruction:\n");
3282  LLVM_DEBUG(MI.dump());
3283  LLVM_DEBUG(dbgs() << "Fed by:\n");
3284  LLVM_DEBUG(DefMI.dump());
3285 
3286  // Update the base reg first.
3288  false, false,
3289  RegMO->isKill());
3290 
3291  // Then, update the imm.
3292  if (ImmMO->isImm()) {
3293  // If the ImmMO is Imm, change the operand that has ZERO to that Imm
3294  // directly.
3296  }
3297  else {
3298  // Otherwise, it is Constant Pool Index(CPI) or Global,
3299  // which is relocation in fact. We need to replace the special zero
3300  // register with ImmMO.
3301  // Before that, we need to fixup the target flags for imm.
3302  // For some reason, we miss to set the flag for the ImmMO if it is CPI.
3303  if (DefMI.getOpcode() == PPC::ADDItocL)
3305 
3306  // MI didn't have the interface such as MI.setOperand(i) though
3307  // it has MI.getOperand(i). To repalce the ZERO MachineOperand with
3308  // ImmMO, we need to remove ZERO operand and all the operands behind it,
3309  // and, add the ImmMO, then, move back all the operands behind ZERO.
3311  for (unsigned i = MI.getNumOperands() - 1; i >= III.ZeroIsSpecialOrig; i--) {
3312  MOps.push_back(MI.getOperand(i));
3313  MI.RemoveOperand(i);
3314  }
3315 
3316  // Remove the last MO in the list, which is ZERO operand in fact.
3317  MOps.pop_back();
3318  // Add the imm operand.
3319  MI.addOperand(*ImmMO);
3320  // Now add the rest back.
3321  for (auto &MO : MOps)
3322  MI.addOperand(MO);
3323  }
3324 
3325  // Update the opcode.
3326  MI.setDesc(get(III.ImmOpcode));
3327 
3328  LLVM_DEBUG(dbgs() << "With:\n");
3329  LLVM_DEBUG(MI.dump());
3330 
3331  return true;
3332 }
3333 
3334 bool PPCInstrInfo::transformToImmFormFedByLI(MachineInstr &MI,
3335  const ImmInstrInfo &III,
3336  unsigned ConstantOpNo,
3337  int64_t Imm) const {
3339  bool PostRA = !MRI.isSSA();
3340  // Exit early if we can't convert this.
3341  if ((ConstantOpNo != III.OpNoForForwarding) && !III.IsCommutative)
3342  return false;
3343  if (Imm % III.ImmMustBeMultipleOf)
3344  return false;
3345  if (III.TruncateImmTo)
3346  Imm &= ((1 << III.TruncateImmTo) - 1);
3347  if (III.SignedImm) {
3348  APInt ActualValue(64, Imm, true);
3349  if (!ActualValue.isSignedIntN(III.ImmWidth))
3350  return false;
3351  } else {
3352  uint64_t UnsignedMax = (1 << III.ImmWidth) - 1;
3353  if ((uint64_t)Imm > UnsignedMax)
3354  return false;
3355  }
3356 
3357  // If we're post-RA, the instructions don't agree on whether register zero is
3358  // special, we can transform this as long as the register operand that will
3359  // end up in the location where zero is special isn't R0.
3360  if (PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) {
3361  unsigned PosForOrigZero = III.ZeroIsSpecialOrig ? III.ZeroIsSpecialOrig :
3362  III.ZeroIsSpecialNew + 1;
3363  unsigned OrigZeroReg = MI.getOperand(PosForOrigZero).getReg();
3364  unsigned NewZeroReg = MI.getOperand(III.ZeroIsSpecialNew).getReg();
3365  // If R0 is in the operand where zero is special for the new instruction,
3366  // it is unsafe to transform if the constant operand isn't that operand.
3367  if ((NewZeroReg == PPC::R0 || NewZeroReg == PPC::X0) &&
3368  ConstantOpNo != III.ZeroIsSpecialNew)
3369  return false;
3370  if ((OrigZeroReg == PPC::R0 || OrigZeroReg == PPC::X0) &&
3371  ConstantOpNo != PosForOrigZero)
3372  return false;
3373  }
3374 
3375  unsigned Opc = MI.getOpcode();
3376  bool SpecialShift32 =
3377  Opc == PPC::SLW || Opc == PPC::SLWo || Opc == PPC::SRW || Opc == PPC::SRWo;
3378  bool SpecialShift64 =
3379  Opc == PPC::SLD || Opc == PPC::SLDo || Opc == PPC::SRD || Opc == PPC::SRDo;
3380  bool SetCR = Opc == PPC::SLWo || Opc == PPC::SRWo ||
3381  Opc == PPC::SLDo || Opc == PPC::SRDo;
3382  bool RightShift =
3383  Opc == PPC::SRW || Opc == PPC::SRWo || Opc == PPC::SRD || Opc == PPC::SRDo;
3384 
3385  MI.setDesc(get(III.ImmOpcode));
3386  if (ConstantOpNo == III.OpNoForForwarding) {
3387  // Converting shifts to immediate form is a bit tricky since they may do
3388  // one of three things:
3389  // 1. If the shift amount is between OpSize and 2*OpSize, the result is zero
3390  // 2. If the shift amount is zero, the result is unchanged (save for maybe
3391  // setting CR0)
3392  // 3. If the shift amount is in [1, OpSize), it's just a shift
3393  if (SpecialShift32 || SpecialShift64) {
3394  LoadImmediateInfo LII;
3395  LII.Imm = 0;
3396  LII.SetCR = SetCR;
3397  LII.Is64Bit = SpecialShift64;
3398  uint64_t ShAmt = Imm & (SpecialShift32 ? 0x1F : 0x3F);
3399  if (Imm & (SpecialShift32 ? 0x20 : 0x40))
3400  replaceInstrWithLI(MI, LII);
3401  // Shifts by zero don't change the value. If we don't need to set CR0,
3402  // just convert this to a COPY. Can't do this post-RA since we've already
3403  // cleaned up the copies.
3404  else if (!SetCR && ShAmt == 0 && !PostRA) {
3405  MI.RemoveOperand(2);
3406  MI.setDesc(get(PPC::COPY));
3407  } else {
3408  // The 32 bit and 64 bit instructions are quite different.
3409  if (SpecialShift32) {
3410  // Left shifts use (N, 0, 31-N), right shifts use (32-N, N, 31).
3411  uint64_t SH = RightShift ? 32 - ShAmt : ShAmt;
3412  uint64_t MB = RightShift ? ShAmt : 0;
3413  uint64_t ME = RightShift ? 31 : 31 - ShAmt;
3415  MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(MB)
3416  .addImm(ME);
3417  } else {
3418  // Left shifts use (N, 63-N), right shifts use (64-N, N).
3419  uint64_t SH = RightShift ? 64 - ShAmt : ShAmt;
3420  uint64_t ME = RightShift ? ShAmt : 63 - ShAmt;
3422  MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(ME);
3423  }
3424  }
3425  } else
3426  MI.getOperand(ConstantOpNo).ChangeToImmediate(Imm);
3427  }
3428  // Convert commutative instructions (switch the operands and convert the
3429  // desired one to an immediate.
3430  else if (III.IsCommutative) {
3431  MI.getOperand(ConstantOpNo).ChangeToImmediate(Imm);
3432  swapMIOperands(MI, ConstantOpNo, III.OpNoForForwarding);
3433  } else
3434  llvm_unreachable("Should have exited early!");
3435 
3436  // For instructions for which the constant register replaces a different
3437  // operand than where the immediate goes, we need to swap them.
3438  if (III.OpNoForForwarding != III.ImmOpNo)
3440 
3441  // If the R0/X0 register is special for the original instruction and not for
3442  // the new instruction (or vice versa), we need to fix up the register class.
3443  if (!PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) {
3444  if (!III.ZeroIsSpecialOrig) {
3445  unsigned RegToModify = MI.getOperand(III.ZeroIsSpecialNew).getReg();
3446  const TargetRegisterClass *NewRC =
3447  MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ?
3448  &PPC::GPRC_and_GPRC_NOR0RegClass : &PPC::G8RC_and_G8RC_NOX0RegClass;
3449  MRI.setRegClass(RegToModify, NewRC);
3450  }
3451  }
3452  return true;
3453 }
3454 
3455 const TargetRegisterClass *
3457  if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
3458  return &PPC::VSRCRegClass;
3459  return RC;
3460 }
3461 
3463  return PPC::getRecordFormOpcode(Opcode);
3464 }
3465 
3466 // This function returns true if the machine instruction
3467 // always outputs a value by sign-extending a 32 bit value,
3468 // i.e. 0 to 31-th bits are same as 32-th bit.
3469 static bool isSignExtendingOp(const MachineInstr &MI) {
3470  int Opcode = MI.getOpcode();
3471  if (Opcode == PPC::LI || Opcode == PPC::LI8 ||
3472  Opcode == PPC::LIS || Opcode == PPC::LIS8 ||
3473  Opcode == PPC::SRAW || Opcode == PPC::SRAWo ||
3474  Opcode == PPC::SRAWI || Opcode == PPC::SRAWIo ||
3475  Opcode == PPC::LWA || Opcode == PPC::LWAX ||
3476  Opcode == PPC::LWA_32 || Opcode == PPC::LWAX_32 ||
3477  Opcode == PPC::LHA || Opcode == PPC::LHAX ||
3478  Opcode == PPC::LHA8 || Opcode == PPC::LHAX8 ||
3479  Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
3480  Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
3481  Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
3482  Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
3483  Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
3484  Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 ||
3485  Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
3486  Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 ||
3487  Opcode == PPC::EXTSB || Opcode == PPC::EXTSBo ||
3488  Opcode == PPC::EXTSH || Opcode == PPC::EXTSHo ||
3489  Opcode == PPC::EXTSB8 || Opcode == PPC::EXTSH8 ||
3490  Opcode == PPC::EXTSW || Opcode == PPC::EXTSWo ||
3491  Opcode == PPC::EXTSH8_32_64 || Opcode == PPC::EXTSW_32_64 ||
3492  Opcode == PPC::EXTSB8_32_64)
3493  return true;
3494 
3495  if (Opcode == PPC::RLDICL && MI.getOperand(3).getImm() >= 33)
3496  return true;
3497 
3498  if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
3499  Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo) &&
3500  MI.getOperand(3).getImm() > 0 &&
3501  MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
3502  return true;
3503 
3504  return false;
3505 }
3506 
3507 // This function returns true if the machine instruction
3508 // always outputs zeros in higher 32 bits.
3509 static bool isZeroExtendingOp(const MachineInstr &MI) {
3510  int Opcode = MI.getOpcode();
3511  // The 16-bit immediate is sign-extended in li/lis.
3512  // If the most significant bit is zero, all higher bits are zero.
3513  if (Opcode == PPC::LI || Opcode == PPC::LI8 ||
3514  Opcode == PPC::LIS || Opcode == PPC::LIS8) {
3515  int64_t Imm = MI.getOperand(1).getImm();
3516  if (((uint64_t)Imm & ~0x7FFFuLL) == 0)
3517  return true;
3518  }
3519 
3520  // We have some variations of rotate-and-mask instructions
3521  // that clear higher 32-bits.
3522  if ((Opcode == PPC::RLDICL || Opcode == PPC::RLDICLo ||
3523  Opcode == PPC::RLDCL || Opcode == PPC::RLDCLo ||
3524  Opcode == PPC::RLDICL_32_64) &&
3525  MI.getOperand(3).getImm() >= 32)
3526  return true;
3527 
3528  if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDICo) &&
3529  MI.getOperand(3).getImm() >= 32 &&
3530  MI.getOperand(3).getImm() <= 63 - MI.getOperand(2).getImm())
3531  return true;
3532 
3533  if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
3534  Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo ||
3535  Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) &&
3536  MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
3537  return true;
3538 
3539  // There are other instructions that clear higher 32-bits.
3540  if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZWo ||
3541  Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZWo ||
3542  Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8 ||
3543  Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZDo ||
3544  Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZDo ||
3545  Opcode == PPC::POPCNTD || Opcode == PPC::POPCNTW ||
3546  Opcode == PPC::SLW || Opcode == PPC::SLWo ||
3547  Opcode == PPC::SRW || Opcode == PPC::SRWo ||
3548  Opcode == PPC::SLW8 || Opcode == PPC::SRW8 ||
3549  Opcode == PPC::SLWI || Opcode == PPC::SLWIo ||
3550  Opcode == PPC::SRWI || Opcode == PPC::SRWIo ||
3551  Opcode == PPC::LWZ || Opcode == PPC::LWZX ||
3552  Opcode == PPC::LWZU || Opcode == PPC::LWZUX ||
3553  Opcode == PPC::LWBRX || Opcode == PPC::LHBRX ||
3554  Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
3555  Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
3556  Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
3557  Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
3558  Opcode == PPC::LWZ8 || Opcode == PPC::LWZX8 ||
3559  Opcode == PPC::LWZU8 || Opcode == PPC::LWZUX8 ||
3560  Opcode == PPC::LWBRX8 || Opcode == PPC::LHBRX8 ||
3561  Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 ||
3562  Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 ||
3563  Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
3564  Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
3565  Opcode == PPC::ANDIo || Opcode == PPC::ANDISo ||
3566  Opcode == PPC::ROTRWI || Opcode == PPC::ROTRWIo ||
3567  Opcode == PPC::EXTLWI || Opcode == PPC::EXTLWIo ||
3568  Opcode == PPC::MFVSRWZ)
3569  return true;
3570 
3571  return false;
3572 }
3573 
3574 // This function returns true if the input MachineInstr is a TOC save
3575 // instruction.
3577  if (!MI.getOperand(1).isImm() || !MI.getOperand(2).isReg())
3578  return false;
3579  unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
3580  unsigned StackOffset = MI.getOperand(1).getImm();
3581  unsigned StackReg = MI.getOperand(2).getReg();
3582  if (StackReg == PPC::X1 && StackOffset == TOCSaveOffset)
3583  return true;
3584 
3585  return false;
3586 }
3587 
3588 // We limit the max depth to track incoming values of PHIs or binary ops
3589 // (e.g. AND) to avoid excessive cost.
3590 const unsigned MAX_DEPTH = 1;
3591 
3592 bool
3594  const unsigned Depth) const {
3595  const MachineFunction *MF = MI.getParent()->getParent();
3596  const MachineRegisterInfo *MRI = &MF->getRegInfo();
3597 
3598  // If we know this instruction returns sign- or zero-extended result,
3599  // return true.
3600  if (SignExt ? isSignExtendingOp(MI):
3601  isZeroExtendingOp(MI))
3602  return true;
3603 
3604  switch (MI.getOpcode()) {
3605  case PPC::COPY: {
3606  unsigned SrcReg = MI.getOperand(1).getReg();
3607 
3608  // In both ELFv1 and v2 ABI, method parameters and the return value
3609  // are sign- or zero-extended.
3610  if (MF->getSubtarget<PPCSubtarget>().isSVR4ABI()) {
3611  const PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
3612  // We check the ZExt/SExt flags for a method parameter.
3613  if (MI.getParent()->getBasicBlock() ==
3614  &MF->getFunction().getEntryBlock()) {
3615  unsigned VReg = MI.getOperand(0).getReg();
3616  if (MF->getRegInfo().isLiveIn(VReg))
3617  return SignExt ? FuncInfo->isLiveInSExt(VReg) :
3618  FuncInfo->isLiveInZExt(VReg);
3619  }
3620 
3621  // For a method return value, we check the ZExt/SExt flags in attribute.
3622  // We assume the following code sequence for method call.
3623  // ADJCALLSTACKDOWN 32, implicit dead %r1, implicit %r1
3624  // BL8_NOP @func,...
3625  // ADJCALLSTACKUP 32, 0, implicit dead %r1, implicit %r1
3626  // %5 = COPY %x3; G8RC:%5
3627  if (SrcReg == PPC::X3) {
3628  const MachineBasicBlock *MBB = MI.getParent();
3631  if (II != MBB->instr_begin() &&
3632  (--II)->getOpcode() == PPC::ADJCALLSTACKUP) {
3633  const MachineInstr &CallMI = *(--II);
3634  if (CallMI.isCall() && CallMI.getOperand(0).isGlobal()) {
3635  const Function *CalleeFn =
3636  dyn_cast<Function>(CallMI.getOperand(0).getGlobal());
3637  if (!CalleeFn)
3638  return false;
3639  const IntegerType *IntTy =
3640  dyn_cast<IntegerType>(CalleeFn->getReturnType());
3641  const AttributeSet &Attrs =
3642  CalleeFn->getAttributes().getRetAttributes();
3643  if (IntTy && IntTy->getBitWidth() <= 32)
3644  return Attrs.hasAttribute(SignExt ? Attribute::SExt :
3645  Attribute::ZExt);
3646  }
3647  }
3648  }
3649  }
3650 
3651  // If this is a copy from another register, we recursively check source.
3653  return false;
3654  const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3655  if (SrcMI != NULL)
3656  return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
3657 
3658  return false;
3659  }
3660 
3661  case PPC::ANDIo:
3662  case PPC::ANDISo:
3663  case PPC::ORI:
3664  case PPC::ORIS:
3665  case PPC::XORI:
3666  case PPC::XORIS:
3667  case PPC::ANDIo8:
3668  case PPC::ANDISo8:
3669  case PPC::ORI8:
3670  case PPC::ORIS8:
3671  case PPC::XORI8:
3672  case PPC::XORIS8: {
3673  // logical operation with 16-bit immediate does not change the upper bits.
3674  // So, we track the operand register as we do for register copy.
3675  unsigned SrcReg = MI.getOperand(1).getReg();
3677  return false;
3678  const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3679  if (SrcMI != NULL)
3680  return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
3681 
3682  return false;
3683  }
3684 
3685  // If all incoming values are sign-/zero-extended,
3686  // the output of OR, ISEL or PHI is also sign-/zero-extended.
3687  case PPC::OR:
3688  case PPC::OR8:
3689  case PPC::ISEL:
3690  case PPC::PHI: {
3691  if (Depth >= MAX_DEPTH)
3692  return false;
3693 
3694  // The input registers for PHI are operand 1, 3, ...
3695  // The input registers for others are operand 1 and 2.
3696  unsigned E = 3, D = 1;
3697  if (MI.getOpcode() == PPC::PHI) {
3698  E = MI.getNumOperands();
3699  D = 2;
3700  }
3701 
3702  for (unsigned I = 1; I != E; I += D) {
3703  if (MI.getOperand(I).isReg()) {
3704  unsigned SrcReg = MI.getOperand(I).getReg();
3706  return false;
3707  const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3708  if (SrcMI == NULL || !isSignOrZeroExtended(*SrcMI, SignExt, Depth+1))
3709  return false;
3710  }
3711  else
3712  return false;
3713  }
3714  return true;
3715  }
3716 
3717  // If at least one of the incoming values of an AND is zero extended
3718  // then the output is also zero-extended. If both of the incoming values
3719  // are sign-extended then the output is also sign extended.
3720  case PPC::AND:
3721  case PPC::AND8: {
3722  if (Depth >= MAX_DEPTH)
3723  return false;
3724 
3725  assert(MI.getOperand(1).isReg() && MI.getOperand(2).isReg());
3726 
3727  unsigned SrcReg1 = MI.getOperand(1).getReg();
3728  unsigned SrcReg2 = MI.getOperand(2).getReg();
3729 
3730  if (!TargetRegisterInfo::isVirtualRegister(SrcReg1) ||
3732  return false;
3733 
3734  const MachineInstr *MISrc1 = MRI->getVRegDef(SrcReg1);
3735  const MachineInstr *MISrc2 = MRI->getVRegDef(SrcReg2);
3736  if (!MISrc1 || !MISrc2)
3737  return false;
3738 
3739  if(SignExt)
3740  return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) &&
3741  isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
3742  else
3743  return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) ||
3744  isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
3745  }
3746 
3747  default:
3748  break;
3749  }
3750  return false;
3751 }
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
instr_iterator instr_begin()
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:633
int getNonRecordFormOpcode(uint16_t)
MachineBasicBlock * getMBB() const
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
This class represents lattice values for constants.
Definition: AllocatorList.h:24
uint64_t ZeroIsSpecialNew
Definition: PPCInstrInfo.h:91
void setTargetFlags(unsigned F)
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
iterator begin() const
begin/end - Return all of the registers in this class.
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
#define LLVM_FALLTHROUGH
Definition: Compiler.h:86
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:223
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:383
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:524
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:164
unsigned getReg() const
getReg - Returns the register number.
static int getRecordFormOpcode(unsigned Opcode)
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned Reg
unsigned getSubReg() const
bool hasVSX() const
Definition: PPCSubtarget.h:246
static cl::opt< bool > DisableCmpOpt("disable-ppc-cmp-opt", cl::desc("Disable compare instruction optimization"), cl::Hidden)
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
uint64_t IsCommutative
Definition: PPCInstrInfo.h:93
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
uint64_t TruncateImmTo
Definition: PPCInstrInfo.h:103
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:306
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool isPseudo() const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MCInstrDesc.h:243
CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
#define R2(n)
uint64_t OpNoForForwarding
Definition: PPCInstrInfo.h:95
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
uint64_t IsSummingOperands
Definition: PPCInstrInfo.h:105
bool isSignExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always a sign-extended, i.e.
Definition: PPCInstrInfo.h:403
return AArch64::GPR64RegClass contains(Reg)
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling th...
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
bool instrHasImmForm(const MachineInstr &MI, ImmInstrInfo &III, bool PostRA) const
MachineFunction & MF
Machine function.
Definition: ScheduleDAG.h:564
bool isXFormMemOp(unsigned Opcode) const
Definition: PPCInstrInfo.h:192
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
PPCDispatchGroupSBHazardRecognizer - This class implements a scoreboard-based hazard recognizer for P...
A description of a memory reference used in the backend.
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:211
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:451
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:412
static Optional< unsigned > getOpcode(ArrayRef< VPValue *> Values)
Returns the opcode of Values or ~0 if they do not all agree.
Definition: VPlanSLP.cpp:197
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:649
AttributeSet getRetAttributes() const
The attributes for the ret value are returned.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:409
const TargetRegisterClass * updatedRC(const TargetRegisterClass *RC) const
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const override
uint64_t ZeroIsSpecialOrig
Definition: PPCInstrInfo.h:88
const char * getSymbolName() const
static bool isZeroExtendingOp(const MachineInstr &MI)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:667
static void swapMIOperands(MachineInstr &MI, unsigned Op1, unsigned Op2)
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
bool isTOCSaveMI(const MachineInstr &MI) const
defusechain_iterator - This class provides iterator support for machine operands in the function that...
PPCInstrInfo(PPCSubtarget &STI)
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1575
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:406
CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based loops.
bool hasP9Vector() const
Definition: PPCSubtarget.h:250
static bool isVFReg(unsigned Reg)
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const override
MO_NLP_HIDDEN_FLAG - If this bit is set, the symbol reference is to a symbol with hidden visibility...
Definition: PPC.h:92
virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns) const
Return true when there is potentially a faster code sequence for an instruction chain ending in Root...
CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
Itinerary data supplied by a subtarget to be used by a target.
const PPCTargetMachine & getTargetMachine() const
Definition: PPCSubtarget.h:192
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:224
unsigned getAlignment() const
Definition: Globals.cpp:97
constexpr char Attrs[]
Key for Kernel::Metadata::mAttrs.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
unsigned getBitWidth() const
Get the number of bits in this IntegerType.
Definition: DerivedTypes.h:66
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
reverse_iterator rend()
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:657
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
unsigned getKillRegState(bool B)
bool hasAttribute(Attribute::AttrKind Kind) const
Return true if the attribute exists in this set.
Definition: Attributes.cpp:578
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
unsigned getDeadRegState(bool B)
VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
const BasicBlock & getEntryBlock() const
Definition: Function.h:640
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:577
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, const unsigned PhiDepth) const
Type * getReturnType() const
Returns the type of the ret val.
Definition: Function.h:169
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:546
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static unsigned selectReg(int64_t Imm1, int64_t Imm2, unsigned CompareOpc, unsigned TrueReg, unsigned FalseReg, unsigned CRSubReg)
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
unsigned const MachineRegisterInfo * MRI
bool isLiveInSExt(unsigned VReg) const
This function returns true if the specified vreg is a live-in register and sign-extended.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
int getAltVSXFMAOpcode(uint16_t Opcode)
Simple binary floating point operators.
Definition: ISDOpcodes.h:283
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void clearRegisterDeads(unsigned Reg)
Clear all dead flags on operands defining register Reg.
MachineInstrBuilder & UseMI
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
MO_NLP_FLAG - If this bit is set, the symbol reference is actually to the non_lazy_ptr for the global...
Definition: PPC.h:87
const GlobalValue * getGlobal() const
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:31
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:174
STFIWX - The STFIWX instruction.
use_instr_iterator use_instr_begin(unsigned RegNo) const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
void setImm(int64_t immVal)
bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point load which sign-extends from a 32-bit inte...
MI-level patchpoint operands.
Definition: StackMaps.h:77
Class to represent integer types.
Definition: DerivedTypes.h:40
PPCHazardRecognizer970 - This class defines a finite state automata that models the dispatch logic on...
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
unsigned getStoreOpcodeForSpill(unsigned Reg, const TargetRegisterClass *RC=nullptr) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
size_t size() const
Definition: SmallVector.h:53
auto find(R &&Range, const T &Val) -> decltype(adl_begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1201
unsigned getPredicateHint(Predicate Opcode)
Return the hint bits of the predicate.
Definition: PPCPredicates.h:83
unsigned getDarwinDirective() const
getDarwinDirective - Returns the -m directive specified for the cpu.
Definition: PPCSubtarget.h:171
static unsigned getCRFromCRBit(unsigned SrcReg)
MO_TLS - Indicates that the operand being accessed is some kind of thread-local symbol.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
unsigned first
void setIsKill(bool Val=true)
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
The next are not flags but distinct values.
Definition: PPC.h:95
The memory access writes data.
static bool MBBDefinesCTR(MachineBasicBlock &MBB)
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:188
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given stackmap should emit.
Definition: StackMaps.h:51
Predicate getPredicate(unsigned Condition, unsigned Hint)
Return predicate consisting of specified condition and hint bits.
Definition: PPCPredicates.h:88
Iterator for intrusive lists based on ilist_node.
void setOpcode(unsigned Op)
Definition: MCInst.h:173
bool isUnpredicatedTerminator(const MachineInstr &MI) const override
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
void getNoop(MCInst &NopInst) const override
Return the noop instruction to use for a noop.
static unsigned getCRBitValue(unsigned CRBit)
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1038
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:27
static cl::opt< bool > VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy", cl::desc("Causes the backend to crash instead of generating a nop VSX copy"), cl::Hidden)
static cl::opt< bool > UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden, cl::desc("Use the old (incorrect) instruction latency calculation"))
APInt rotl(unsigned rotateAmt) const
Rotate left by rotateAmt.
Definition: APInt.cpp:995
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
int64_t getImm() const
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const Function & getFunction() const
Return the LLVM function that this machine code represents.
virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Class for arbitrary precision integers.
Definition: APInt.h:70
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
QVGPCI = This corresponds to the QPX qvgpci instruction.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
bool use_empty(unsigned RegNo) const
use_empty - Return true if there are no instructions using the specified register.
On a symbol operand, this represents the lo part.
Definition: AVRInstrInfo.h:53
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:254
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
TargetSubtargetInfo - Generic base class for all target subtargets.
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in <Root...
bool isPredicated(const MachineInstr &MI) const override
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
bool isLiveIn(unsigned Reg) const
Representation of each machine instruction.
Definition: MachineInstr.h:64
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Predicate InvertPredicate(Predicate Opcode)
Invert the specified predicate. != -> ==, < -> >=.
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:387
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
bool hasOneUse(unsigned RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MI-level stackmap operands.
Definition: StackMaps.h:36
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
TargetOptions Options
Definition: TargetMachine.h:97
static bool isSignExtendingOp(const MachineInstr &MI)
void setReg(unsigned Reg)
Change the register this operand corresponds to.
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned getLoadOpcodeForSpill(unsigned Reg, const TargetRegisterClass *RC=nullptr) const
void setSubReg(unsigned subReg)
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given patchpoint should emit.
Definition: StackMaps.h:105
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:562
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:346
bool isSignedIntN(unsigned N) const
Check if this APInt has an N-bits signed integer value.
Definition: APInt.h:456
const unsigned MAX_DEPTH
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator_range< use_instr_iterator > use_instructions(unsigned Reg) const
uint64_t ImmMustBeMultipleOf
Definition: PPCInstrInfo.h:85
unsigned getPredicateCondition(Predicate Opcode)
Return the condition without hint bits.
Definition: PPCPredicates.h:78
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
bool isLiveInZExt(unsigned VReg) const
This function returns true if the specified vreg is a live-in register and zero-extended.
LLVM Value Representation.
Definition: Value.h:73
static use_instr_iterator use_instr_end()
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:175
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when ...
IRTranslator LLVM IR MI
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:640
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
bool isPredicable(const MachineInstr &MI) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool isSVR4ABI() const
Definition: PPCSubtarget.h:310
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:67
#define LLVM_DEBUG(X)
Definition: Debug.h:123
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
On a symbol operand "FOO", this indicates that the reference is actually to "FOO@plt".
Definition: PPC.h:79
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: PPCInstrInfo.h:190
virtual unsigned lookThruCopyLike(unsigned SrcReg, const MachineRegisterInfo *MRI) const
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:318
static cl::opt< bool > DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden, cl::desc("Disable analysis for CTR loops"))
Instructions::const_iterator const_instr_iterator
GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point load which zero-extends from a 32-bit inte...
SpillOpcodeKey
MO_PIC_FLAG - If this bit is set, the symbol reference is relative to the function&#39;s picbase...
Definition: PPC.h:83
bool convertToImmediateForm(MachineInstr &MI, MachineInstr **KilledDef=nullptr) const
static bool isAnImmediateOperand(const MachineOperand &MO)
bool expandPostRAPseudo(MachineInstr &MI) const override
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:144
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:173
bool expandVSXMemPseudo(MachineInstr &MI) const
bool isImplicit() const
bool isZeroExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always zero-extended, i.e.
Definition: PPCInstrInfo.h:409
Predicate getSwappedPredicate(Predicate Opcode)
Assume the condition register is set by MI(a,b), return the predicate if we modify the instructions s...