LLVM  8.0.0svn
PPCInstrInfo.cpp
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1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCInstrInfo.h"
16 #include "PPC.h"
17 #include "PPCHazardRecognizers.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCTargetMachine.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Statistic.h"
32 #include "llvm/CodeGen/StackMaps.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCInst.h"
36 #include "llvm/Support/Debug.h"
40 
41 using namespace llvm;
42 
43 #define DEBUG_TYPE "ppc-instr-info"
44 
45 #define GET_INSTRMAP_INFO
46 #define GET_INSTRINFO_CTOR_DTOR
47 #include "PPCGenInstrInfo.inc"
48 
49 STATISTIC(NumStoreSPILLVSRRCAsVec,
50  "Number of spillvsrrc spilled to stack as vec");
51 STATISTIC(NumStoreSPILLVSRRCAsGpr,
52  "Number of spillvsrrc spilled to stack as gpr");
53 STATISTIC(NumGPRtoVSRSpill, "Number of gpr spills to spillvsrrc");
54 STATISTIC(CmpIselsConverted,
55  "Number of ISELs that depend on comparison of constants converted");
56 STATISTIC(MissedConvertibleImmediateInstrs,
57  "Number of compare-immediate instructions fed by constants");
58 STATISTIC(NumRcRotatesConvertedToRcAnd,
59  "Number of record-form rotates converted to record-form andi");
60 
61 static cl::
62 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
63  cl::desc("Disable analysis for CTR loops"));
64 
65 static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
66 cl::desc("Disable compare instruction optimization"), cl::Hidden);
67 
68 static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
69 cl::desc("Causes the backend to crash instead of generating a nop VSX copy"),
70 cl::Hidden);
71 
72 static cl::opt<bool>
73 UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
74  cl::desc("Use the old (incorrect) instruction latency calculation"));
75 
76 // Index into the OpcodesForSpill array.
95  SOK_LastOpcodeSpill // This must be last on the enum.
96 };
97 
98 // Pin the vtable to this file.
99 void PPCInstrInfo::anchor() {}
100 
102  : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP,
103  /* CatchRetOpcode */ -1,
104  STI.isPPC64() ? PPC::BLR8 : PPC::BLR),
105  Subtarget(STI), RI(STI.getTargetMachine()) {}
106 
107 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
108 /// this target when scheduling the DAG.
111  const ScheduleDAG *DAG) const {
112  unsigned Directive =
113  static_cast<const PPCSubtarget *>(STI)->getDarwinDirective();
114  if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
115  Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
116  const InstrItineraryData *II =
117  static_cast<const PPCSubtarget *>(STI)->getInstrItineraryData();
118  return new ScoreboardHazardRecognizer(II, DAG);
119  }
120 
122 }
123 
124 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
125 /// to use for this target when scheduling the DAG.
128  const ScheduleDAG *DAG) const {
129  unsigned Directive =
130  DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
131 
132  // FIXME: Leaving this as-is until we have POWER9 scheduling info
133  if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8)
134  return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
135 
136  // Most subtargets use a PPC970 recognizer.
137  if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
138  Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
139  assert(DAG->TII && "No InstrInfo?");
140 
141  return new PPCHazardRecognizer970(*DAG);
142  }
143 
144  return new ScoreboardHazardRecognizer(II, DAG);
145 }
146 
148  const MachineInstr &MI,
149  unsigned *PredCost) const {
150  if (!ItinData || UseOldLatencyCalc)
151  return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
152 
153  // The default implementation of getInstrLatency calls getStageLatency, but
154  // getStageLatency does not do the right thing for us. While we have
155  // itinerary, most cores are fully pipelined, and so the itineraries only
156  // express the first part of the pipeline, not every stage. Instead, we need
157  // to use the listed output operand cycle number (using operand 0 here, which
158  // is an output).
159 
160  unsigned Latency = 1;
161  unsigned DefClass = MI.getDesc().getSchedClass();
162  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
163  const MachineOperand &MO = MI.getOperand(i);
164  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
165  continue;
166 
167  int Cycle = ItinData->getOperandCycle(DefClass, i);
168  if (Cycle < 0)
169  continue;
170 
171  Latency = std::max(Latency, (unsigned) Cycle);
172  }
173 
174  return Latency;
175 }
176 
178  const MachineInstr &DefMI, unsigned DefIdx,
179  const MachineInstr &UseMI,
180  unsigned UseIdx) const {
181  int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
182  UseMI, UseIdx);
183 
184  if (!DefMI.getParent())
185  return Latency;
186 
187  const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
188  unsigned Reg = DefMO.getReg();
189 
190  bool IsRegCR;
192  const MachineRegisterInfo *MRI =
193  &DefMI.getParent()->getParent()->getRegInfo();
194  IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
195  MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
196  } else {
197  IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
198  PPC::CRBITRCRegClass.contains(Reg);
199  }
200 
201  if (UseMI.isBranch() && IsRegCR) {
202  if (Latency < 0)
203  Latency = getInstrLatency(ItinData, DefMI);
204 
205  // On some cores, there is an additional delay between writing to a condition
206  // register, and using it from a branch.
207  unsigned Directive = Subtarget.getDarwinDirective();
208  switch (Directive) {
209  default: break;
210  case PPC::DIR_7400:
211  case PPC::DIR_750:
212  case PPC::DIR_970:
213  case PPC::DIR_E5500:
214  case PPC::DIR_PWR4:
215  case PPC::DIR_PWR5:
216  case PPC::DIR_PWR5X:
217  case PPC::DIR_PWR6:
218  case PPC::DIR_PWR6X:
219  case PPC::DIR_PWR7:
220  case PPC::DIR_PWR8:
221  // FIXME: Is this needed for POWER9?
222  Latency += 2;
223  break;
224  }
225  }
226 
227  return Latency;
228 }
229 
230 // This function does not list all associative and commutative operations, but
231 // only those worth feeding through the machine combiner in an attempt to
232 // reduce the critical path. Mostly, this means floating-point operations,
233 // because they have high latencies (compared to other operations, such and
234 // and/or, which are also associative and commutative, but have low latencies).
236  switch (Inst.getOpcode()) {
237  // FP Add:
238  case PPC::FADD:
239  case PPC::FADDS:
240  // FP Multiply:
241  case PPC::FMUL:
242  case PPC::FMULS:
243  // Altivec Add:
244  case PPC::VADDFP:
245  // VSX Add:
246  case PPC::XSADDDP:
247  case PPC::XVADDDP:
248  case PPC::XVADDSP:
249  case PPC::XSADDSP:
250  // VSX Multiply:
251  case PPC::XSMULDP:
252  case PPC::XVMULDP:
253  case PPC::XVMULSP:
254  case PPC::XSMULSP:
255  // QPX Add:
256  case PPC::QVFADD:
257  case PPC::QVFADDS:
258  case PPC::QVFADDSs:
259  // QPX Multiply:
260  case PPC::QVFMUL:
261  case PPC::QVFMULS:
262  case PPC::QVFMULSs:
263  return true;
264  default:
265  return false;
266  }
267 }
268 
270  MachineInstr &Root,
271  SmallVectorImpl<MachineCombinerPattern> &Patterns) const {
272  // Using the machine combiner in this way is potentially expensive, so
273  // restrict to when aggressive optimizations are desired.
275  return false;
276 
277  // FP reassociation is only legal when we don't need strict IEEE semantics.
279  return false;
280 
281  return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns);
282 }
283 
284 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
286  unsigned &SrcReg, unsigned &DstReg,
287  unsigned &SubIdx) const {
288  switch (MI.getOpcode()) {
289  default: return false;
290  case PPC::EXTSW:
291  case PPC::EXTSW_32:
292  case PPC::EXTSW_32_64:
293  SrcReg = MI.getOperand(1).getReg();
294  DstReg = MI.getOperand(0).getReg();
295  SubIdx = PPC::sub_32;
296  return true;
297  }
298 }
299 
301  int &FrameIndex) const {
302  unsigned Opcode = MI.getOpcode();
303  const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
304  const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill;
305 
306  if (End != std::find(OpcodesForSpill, End, Opcode)) {
307  // Check for the operands added by addFrameReference (the immediate is the
308  // offset which defaults to 0).
309  if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
310  MI.getOperand(2).isFI()) {
311  FrameIndex = MI.getOperand(2).getIndex();
312  return MI.getOperand(0).getReg();
313  }
314  }
315  return 0;
316 }
317 
318 // For opcodes with the ReMaterializable flag set, this function is called to
319 // verify the instruction is really rematable.
321  AliasAnalysis *AA) const {
322  switch (MI.getOpcode()) {
323  default:
324  // This function should only be called for opcodes with the ReMaterializable
325  // flag set.
326  llvm_unreachable("Unknown rematerializable operation!");
327  break;
328  case PPC::LI:
329  case PPC::LI8:
330  case PPC::LIS:
331  case PPC::LIS8:
332  case PPC::QVGPCI:
333  case PPC::ADDIStocHA:
334  case PPC::ADDItocL:
335  case PPC::LOAD_STACK_GUARD:
336  return true;
337  }
338  return false;
339 }
340 
342  int &FrameIndex) const {
343  unsigned Opcode = MI.getOpcode();
344  const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
345  const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill;
346 
347  if (End != std::find(OpcodesForSpill, End, Opcode)) {
348  if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
349  MI.getOperand(2).isFI()) {
350  FrameIndex = MI.getOperand(2).getIndex();
351  return MI.getOperand(0).getReg();
352  }
353  }
354  return 0;
355 }
356 
358  unsigned OpIdx1,
359  unsigned OpIdx2) const {
360  MachineFunction &MF = *MI.getParent()->getParent();
361 
362  // Normal instructions can be commuted the obvious way.
363  if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMIo)
364  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
365  // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
366  // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
367  // changing the relative order of the mask operands might change what happens
368  // to the high-bits of the mask (and, thus, the result).
369 
370  // Cannot commute if it has a non-zero rotate count.
371  if (MI.getOperand(3).getImm() != 0)
372  return nullptr;
373 
374  // If we have a zero rotate count, we have:
375  // M = mask(MB,ME)
376  // Op0 = (Op1 & ~M) | (Op2 & M)
377  // Change this to:
378  // M = mask((ME+1)&31, (MB-1)&31)
379  // Op0 = (Op2 & ~M) | (Op1 & M)
380 
381  // Swap op1/op2
382  assert(((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) &&
383  "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo.");
384  unsigned Reg0 = MI.getOperand(0).getReg();
385  unsigned Reg1 = MI.getOperand(1).getReg();
386  unsigned Reg2 = MI.getOperand(2).getReg();
387  unsigned SubReg1 = MI.getOperand(1).getSubReg();
388  unsigned SubReg2 = MI.getOperand(2).getSubReg();
389  bool Reg1IsKill = MI.getOperand(1).isKill();
390  bool Reg2IsKill = MI.getOperand(2).isKill();
391  bool ChangeReg0 = false;
392  // If machine instrs are no longer in two-address forms, update
393  // destination register as well.
394  if (Reg0 == Reg1) {
395  // Must be two address instruction!
397  "Expecting a two-address instruction!");
398  assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
399  Reg2IsKill = false;
400  ChangeReg0 = true;
401  }
402 
403  // Masks.
404  unsigned MB = MI.getOperand(4).getImm();
405  unsigned ME = MI.getOperand(5).getImm();
406 
407  // We can't commute a trivial mask (there is no way to represent an all-zero
408  // mask).
409  if (MB == 0 && ME == 31)
410  return nullptr;
411 
412  if (NewMI) {
413  // Create a new instruction.
414  unsigned Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg();
415  bool Reg0IsDead = MI.getOperand(0).isDead();
416  return BuildMI(MF, MI.getDebugLoc(), MI.getDesc())
417  .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
418  .addReg(Reg2, getKillRegState(Reg2IsKill))
419  .addReg(Reg1, getKillRegState(Reg1IsKill))
420  .addImm((ME + 1) & 31)
421  .addImm((MB - 1) & 31);
422  }
423 
424  if (ChangeReg0) {
425  MI.getOperand(0).setReg(Reg2);
426  MI.getOperand(0).setSubReg(SubReg2);
427  }
428  MI.getOperand(2).setReg(Reg1);
429  MI.getOperand(1).setReg(Reg2);
430  MI.getOperand(2).setSubReg(SubReg1);
431  MI.getOperand(1).setSubReg(SubReg2);
432  MI.getOperand(2).setIsKill(Reg1IsKill);
433  MI.getOperand(1).setIsKill(Reg2IsKill);
434 
435  // Swap the mask around.
436  MI.getOperand(4).setImm((ME + 1) & 31);
437  MI.getOperand(5).setImm((MB - 1) & 31);
438  return &MI;
439 }
440 
442  unsigned &SrcOpIdx2) const {
443  // For VSX A-Type FMA instructions, it is the first two operands that can be
444  // commuted, however, because the non-encoded tied input operand is listed
445  // first, the operands to swap are actually the second and third.
446 
447  int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode());
448  if (AltOpc == -1)
449  return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
450 
451  // The commutable operand indices are 2 and 3. Return them in SrcOpIdx1
452  // and SrcOpIdx2.
453  return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
454 }
455 
458  // This function is used for scheduling, and the nop wanted here is the type
459  // that terminates dispatch groups on the POWER cores.
460  unsigned Directive = Subtarget.getDarwinDirective();
461  unsigned Opcode;
462  switch (Directive) {
463  default: Opcode = PPC::NOP; break;
464  case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
465  case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
466  case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */
467  // FIXME: Update when POWER9 scheduling model is ready.
468  case PPC::DIR_PWR9: Opcode = PPC::NOP_GT_PWR7; break;
469  }
470 
471  DebugLoc DL;
472  BuildMI(MBB, MI, DL, get(Opcode));
473 }
474 
475 /// Return the noop instruction to use for a noop.
476 void PPCInstrInfo::getNoop(MCInst &NopInst) const {
477  NopInst.setOpcode(PPC::NOP);
478 }
479 
480 // Branch analysis.
481 // Note: If the condition register is set to CTR or CTR8 then this is a
482 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
484  MachineBasicBlock *&TBB,
485  MachineBasicBlock *&FBB,
487  bool AllowModify) const {
488  bool isPPC64 = Subtarget.isPPC64();
489 
490  // If the block has no terminators, it just falls into the block after it.
492  if (I == MBB.end())
493  return false;
494 
495  if (!isUnpredicatedTerminator(*I))
496  return false;
497 
498  if (AllowModify) {
499  // If the BB ends with an unconditional branch to the fallthrough BB,
500  // we eliminate the branch instruction.
501  if (I->getOpcode() == PPC::B &&
502  MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
503  I->eraseFromParent();
504 
505  // We update iterator after deleting the last branch.
506  I = MBB.getLastNonDebugInstr();
507  if (I == MBB.end() || !isUnpredicatedTerminator(*I))
508  return false;
509  }
510  }
511 
512  // Get the last instruction in the block.
513  MachineInstr &LastInst = *I;
514 
515  // If there is only one terminator instruction, process it.
516  if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
517  if (LastInst.getOpcode() == PPC::B) {
518  if (!LastInst.getOperand(0).isMBB())
519  return true;
520  TBB = LastInst.getOperand(0).getMBB();
521  return false;
522  } else if (LastInst.getOpcode() == PPC::BCC) {
523  if (!LastInst.getOperand(2).isMBB())
524  return true;
525  // Block ends with fall-through condbranch.
526  TBB = LastInst.getOperand(2).getMBB();
527  Cond.push_back(LastInst.getOperand(0));
528  Cond.push_back(LastInst.getOperand(1));
529  return false;
530  } else if (LastInst.getOpcode() == PPC::BC) {
531  if (!LastInst.getOperand(1).isMBB())
532  return true;
533  // Block ends with fall-through condbranch.
534  TBB = LastInst.getOperand(1).getMBB();
536  Cond.push_back(LastInst.getOperand(0));
537  return false;
538  } else if (LastInst.getOpcode() == PPC::BCn) {
539  if (!LastInst.getOperand(1).isMBB())
540  return true;
541  // Block ends with fall-through condbranch.
542  TBB = LastInst.getOperand(1).getMBB();
544  Cond.push_back(LastInst.getOperand(0));
545  return false;
546  } else if (LastInst.getOpcode() == PPC::BDNZ8 ||
547  LastInst.getOpcode() == PPC::BDNZ) {
548  if (!LastInst.getOperand(0).isMBB())
549  return true;
550  if (DisableCTRLoopAnal)
551  return true;
552  TBB = LastInst.getOperand(0).getMBB();
554  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
555  true));
556  return false;
557  } else if (LastInst.getOpcode() == PPC::BDZ8 ||
558  LastInst.getOpcode() == PPC::BDZ) {
559  if (!LastInst.getOperand(0).isMBB())
560  return true;
561  if (DisableCTRLoopAnal)
562  return true;
563  TBB = LastInst.getOperand(0).getMBB();
565  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
566  true));
567  return false;
568  }
569 
570  // Otherwise, don't know what this is.
571  return true;
572  }
573 
574  // Get the instruction before it if it's a terminator.
575  MachineInstr &SecondLastInst = *I;
576 
577  // If there are three terminators, we don't know what sort of block this is.
578  if (I != MBB.begin() && isUnpredicatedTerminator(*--I))
579  return true;
580 
581  // If the block ends with PPC::B and PPC:BCC, handle it.
582  if (SecondLastInst.getOpcode() == PPC::BCC &&
583  LastInst.getOpcode() == PPC::B) {
584  if (!SecondLastInst.getOperand(2).isMBB() ||
585  !LastInst.getOperand(0).isMBB())
586  return true;
587  TBB = SecondLastInst.getOperand(2).getMBB();
588  Cond.push_back(SecondLastInst.getOperand(0));
589  Cond.push_back(SecondLastInst.getOperand(1));
590  FBB = LastInst.getOperand(0).getMBB();
591  return false;
592  } else if (SecondLastInst.getOpcode() == PPC::BC &&
593  LastInst.getOpcode() == PPC::B) {
594  if (!SecondLastInst.getOperand(1).isMBB() ||
595  !LastInst.getOperand(0).isMBB())
596  return true;
597  TBB = SecondLastInst.getOperand(1).getMBB();
599  Cond.push_back(SecondLastInst.getOperand(0));
600  FBB = LastInst.getOperand(0).getMBB();
601  return false;
602  } else if (SecondLastInst.getOpcode() == PPC::BCn &&
603  LastInst.getOpcode() == PPC::B) {
604  if (!SecondLastInst.getOperand(1).isMBB() ||
605  !LastInst.getOperand(0).isMBB())
606  return true;
607  TBB = SecondLastInst.getOperand(1).getMBB();
609  Cond.push_back(SecondLastInst.getOperand(0));
610  FBB = LastInst.getOperand(0).getMBB();
611  return false;
612  } else if ((SecondLastInst.getOpcode() == PPC::BDNZ8 ||
613  SecondLastInst.getOpcode() == PPC::BDNZ) &&
614  LastInst.getOpcode() == PPC::B) {
615  if (!SecondLastInst.getOperand(0).isMBB() ||
616  !LastInst.getOperand(0).isMBB())
617  return true;
618  if (DisableCTRLoopAnal)
619  return true;
620  TBB = SecondLastInst.getOperand(0).getMBB();
622  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
623  true));
624  FBB = LastInst.getOperand(0).getMBB();
625  return false;
626  } else if ((SecondLastInst.getOpcode() == PPC::BDZ8 ||
627  SecondLastInst.getOpcode() == PPC::BDZ) &&
628  LastInst.getOpcode() == PPC::B) {
629  if (!SecondLastInst.getOperand(0).isMBB() ||
630  !LastInst.getOperand(0).isMBB())
631  return true;
632  if (DisableCTRLoopAnal)
633  return true;
634  TBB = SecondLastInst.getOperand(0).getMBB();
636  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
637  true));
638  FBB = LastInst.getOperand(0).getMBB();
639  return false;
640  }
641 
642  // If the block ends with two PPC:Bs, handle it. The second one is not
643  // executed, so remove it.
644  if (SecondLastInst.getOpcode() == PPC::B && LastInst.getOpcode() == PPC::B) {
645  if (!SecondLastInst.getOperand(0).isMBB())
646  return true;
647  TBB = SecondLastInst.getOperand(0).getMBB();
648  I = LastInst;
649  if (AllowModify)
650  I->eraseFromParent();
651  return false;
652  }
653 
654  // Otherwise, can't handle this.
655  return true;
656 }
657 
659  int *BytesRemoved) const {
660  assert(!BytesRemoved && "code size not handled");
661 
663  if (I == MBB.end())
664  return 0;
665 
666  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
667  I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
668  I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
669  I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
670  return 0;
671 
672  // Remove the branch.
673  I->eraseFromParent();
674 
675  I = MBB.end();
676 
677  if (I == MBB.begin()) return 1;
678  --I;
679  if (I->getOpcode() != PPC::BCC &&
680  I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
681  I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
682  I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
683  return 1;
684 
685  // Remove the branch.
686  I->eraseFromParent();
687  return 2;
688 }
689 
691  MachineBasicBlock *TBB,
692  MachineBasicBlock *FBB,
694  const DebugLoc &DL,
695  int *BytesAdded) const {
696  // Shouldn't be a fall through.
697  assert(TBB && "insertBranch must not be told to insert a fallthrough");
698  assert((Cond.size() == 2 || Cond.size() == 0) &&
699  "PPC branch conditions have two components!");
700  assert(!BytesAdded && "code size not handled");
701 
702  bool isPPC64 = Subtarget.isPPC64();
703 
704  // One-way branch.
705  if (!FBB) {
706  if (Cond.empty()) // Unconditional branch
707  BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
708  else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
709  BuildMI(&MBB, DL, get(Cond[0].getImm() ?
710  (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
711  (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
712  else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
713  BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
714  else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
715  BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
716  else // Conditional branch
717  BuildMI(&MBB, DL, get(PPC::BCC))
718  .addImm(Cond[0].getImm())
719  .add(Cond[1])
720  .addMBB(TBB);
721  return 1;
722  }
723 
724  // Two-way Conditional Branch.
725  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
726  BuildMI(&MBB, DL, get(Cond[0].getImm() ?
727  (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
728  (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
729  else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
730  BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
731  else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
732  BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
733  else
734  BuildMI(&MBB, DL, get(PPC::BCC))
735  .addImm(Cond[0].getImm())
736  .add(Cond[1])
737  .addMBB(TBB);
738  BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
739  return 2;
740 }
741 
742 // Select analysis.
745  unsigned TrueReg, unsigned FalseReg,
746  int &CondCycles, int &TrueCycles, int &FalseCycles) const {
747  if (Cond.size() != 2)
748  return false;
749 
750  // If this is really a bdnz-like condition, then it cannot be turned into a
751  // select.
752  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
753  return false;
754 
755  // Check register classes.
756  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
757  const TargetRegisterClass *RC =
758  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
759  if (!RC)
760  return false;
761 
762  // isel is for regular integer GPRs only.
763  if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
764  !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
765  !PPC::G8RCRegClass.hasSubClassEq(RC) &&
766  !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
767  return false;
768 
769  // FIXME: These numbers are for the A2, how well they work for other cores is
770  // an open question. On the A2, the isel instruction has a 2-cycle latency
771  // but single-cycle throughput. These numbers are used in combination with
772  // the MispredictPenalty setting from the active SchedMachineModel.
773  CondCycles = 1;
774  TrueCycles = 1;
775  FalseCycles = 1;
776 
777  return true;
778 }
779 
782  const DebugLoc &dl, unsigned DestReg,
783  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
784  unsigned FalseReg) const {
785  assert(Cond.size() == 2 &&
786  "PPC branch conditions have two components!");
787 
788  // Get the register classes.
790  const TargetRegisterClass *RC =
791  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
792  assert(RC && "TrueReg and FalseReg must have overlapping register classes");
793 
794  bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
795  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
796  assert((Is64Bit ||
797  PPC::GPRCRegClass.hasSubClassEq(RC) ||
798  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
799  "isel is for regular integer GPRs only");
800 
801  unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
802  auto SelectPred = static_cast<PPC::Predicate>(Cond[0].getImm());
803 
804  unsigned SubIdx = 0;
805  bool SwapOps = false;
806  switch (SelectPred) {
807  case PPC::PRED_EQ:
808  case PPC::PRED_EQ_MINUS:
809  case PPC::PRED_EQ_PLUS:
810  SubIdx = PPC::sub_eq; SwapOps = false; break;
811  case PPC::PRED_NE:
812  case PPC::PRED_NE_MINUS:
813  case PPC::PRED_NE_PLUS:
814  SubIdx = PPC::sub_eq; SwapOps = true; break;
815  case PPC::PRED_LT:
816  case PPC::PRED_LT_MINUS:
817  case PPC::PRED_LT_PLUS:
818  SubIdx = PPC::sub_lt; SwapOps = false; break;
819  case PPC::PRED_GE:
820  case PPC::PRED_GE_MINUS:
821  case PPC::PRED_GE_PLUS:
822  SubIdx = PPC::sub_lt; SwapOps = true; break;
823  case PPC::PRED_GT:
824  case PPC::PRED_GT_MINUS:
825  case PPC::PRED_GT_PLUS:
826  SubIdx = PPC::sub_gt; SwapOps = false; break;
827  case PPC::PRED_LE:
828  case PPC::PRED_LE_MINUS:
829  case PPC::PRED_LE_PLUS:
830  SubIdx = PPC::sub_gt; SwapOps = true; break;
831  case PPC::PRED_UN:
832  case PPC::PRED_UN_MINUS:
833  case PPC::PRED_UN_PLUS:
834  SubIdx = PPC::sub_un; SwapOps = false; break;
835  case PPC::PRED_NU:
836  case PPC::PRED_NU_MINUS:
837  case PPC::PRED_NU_PLUS:
838  SubIdx = PPC::sub_un; SwapOps = true; break;
839  case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break;
840  case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break;
841  }
842 
843  unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
844  SecondReg = SwapOps ? TrueReg : FalseReg;
845 
846  // The first input register of isel cannot be r0. If it is a member
847  // of a register class that can be r0, then copy it first (the
848  // register allocator should eliminate the copy).
849  if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
850  MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
851  const TargetRegisterClass *FirstRC =
852  MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
853  &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
854  unsigned OldFirstReg = FirstReg;
855  FirstReg = MRI.createVirtualRegister(FirstRC);
856  BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
857  .addReg(OldFirstReg);
858  }
859 
860  BuildMI(MBB, MI, dl, get(OpCode), DestReg)
861  .addReg(FirstReg).addReg(SecondReg)
862  .addReg(Cond[1].getReg(), 0, SubIdx);
863 }
864 
865 static unsigned getCRBitValue(unsigned CRBit) {
866  unsigned Ret = 4;
867  if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT ||
868  CRBit == PPC::CR2LT || CRBit == PPC::CR3LT ||
869  CRBit == PPC::CR4LT || CRBit == PPC::CR5LT ||
870  CRBit == PPC::CR6LT || CRBit == PPC::CR7LT)
871  Ret = 3;
872  if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT ||
873  CRBit == PPC::CR2GT || CRBit == PPC::CR3GT ||
874  CRBit == PPC::CR4GT || CRBit == PPC::CR5GT ||
875  CRBit == PPC::CR6GT || CRBit == PPC::CR7GT)
876  Ret = 2;
877  if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ ||
878  CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ ||
879  CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ ||
880  CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ)
881  Ret = 1;
882  if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN ||
883  CRBit == PPC::CR2UN || CRBit == PPC::CR3UN ||
884  CRBit == PPC::CR4UN || CRBit == PPC::CR5UN ||
885  CRBit == PPC::CR6UN || CRBit == PPC::CR7UN)
886  Ret = 0;
887 
888  assert(Ret != 4 && "Invalid CR bit register");
889  return Ret;
890 }
891 
894  const DebugLoc &DL, unsigned DestReg,
895  unsigned SrcReg, bool KillSrc) const {
896  // We can end up with self copies and similar things as a result of VSX copy
897  // legalization. Promote them here.
899  if (PPC::F8RCRegClass.contains(DestReg) &&
900  PPC::VSRCRegClass.contains(SrcReg)) {
901  unsigned SuperReg =
902  TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
903 
904  if (VSXSelfCopyCrash && SrcReg == SuperReg)
905  llvm_unreachable("nop VSX copy");
906 
907  DestReg = SuperReg;
908  } else if (PPC::F8RCRegClass.contains(SrcReg) &&
909  PPC::VSRCRegClass.contains(DestReg)) {
910  unsigned SuperReg =
911  TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
912 
913  if (VSXSelfCopyCrash && DestReg == SuperReg)
914  llvm_unreachable("nop VSX copy");
915 
916  SrcReg = SuperReg;
917  }
918 
919  // Different class register copy
920  if (PPC::CRBITRCRegClass.contains(SrcReg) &&
921  PPC::GPRCRegClass.contains(DestReg)) {
922  unsigned CRReg = getCRFromCRBit(SrcReg);
923  BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg);
924  getKillRegState(KillSrc);
925  // Rotate the CR bit in the CR fields to be the least significant bit and
926  // then mask with 0x1 (MB = ME = 31).
927  BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
928  .addReg(DestReg, RegState::Kill)
929  .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
930  .addImm(31)
931  .addImm(31);
932  return;
933  } else if (PPC::CRRCRegClass.contains(SrcReg) &&
934  PPC::G8RCRegClass.contains(DestReg)) {
935  BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg).addReg(SrcReg);
936  getKillRegState(KillSrc);
937  return;
938  } else if (PPC::CRRCRegClass.contains(SrcReg) &&
939  PPC::GPRCRegClass.contains(DestReg)) {
940  BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(SrcReg);
941  getKillRegState(KillSrc);
942  return;
943  } else if (PPC::G8RCRegClass.contains(SrcReg) &&
944  PPC::VSFRCRegClass.contains(DestReg)) {
945  BuildMI(MBB, I, DL, get(PPC::MTVSRD), DestReg).addReg(SrcReg);
946  NumGPRtoVSRSpill++;
947  getKillRegState(KillSrc);
948  return;
949  } else if (PPC::VSFRCRegClass.contains(SrcReg) &&
950  PPC::G8RCRegClass.contains(DestReg)) {
951  BuildMI(MBB, I, DL, get(PPC::MFVSRD), DestReg).addReg(SrcReg);
952  getKillRegState(KillSrc);
953  return;
954  } else if (PPC::SPERCRegClass.contains(SrcReg) &&
955  PPC::SPE4RCRegClass.contains(DestReg)) {
956  BuildMI(MBB, I, DL, get(PPC::EFSCFD), DestReg).addReg(SrcReg);
957  getKillRegState(KillSrc);
958  return;
959  } else if (PPC::SPE4RCRegClass.contains(SrcReg) &&
960  PPC::SPERCRegClass.contains(DestReg)) {
961  BuildMI(MBB, I, DL, get(PPC::EFDCFS), DestReg).addReg(SrcReg);
962  getKillRegState(KillSrc);
963  return;
964  }
965 
966 
967  unsigned Opc;
968  if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
969  Opc = PPC::OR;
970  else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
971  Opc = PPC::OR8;
972  else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
973  Opc = PPC::FMR;
974  else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
975  Opc = PPC::MCRF;
976  else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
977  Opc = PPC::VOR;
978  else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
979  // There are two different ways this can be done:
980  // 1. xxlor : This has lower latency (on the P7), 2 cycles, but can only
981  // issue in VSU pipeline 0.
982  // 2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
983  // can go to either pipeline.
984  // We'll always use xxlor here, because in practically all cases where
985  // copies are generated, they are close enough to some use that the
986  // lower-latency form is preferable.
987  Opc = PPC::XXLOR;
988  else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) ||
989  PPC::VSSRCRegClass.contains(DestReg, SrcReg))
990  Opc = PPC::XXLORf;
991  else if (PPC::QFRCRegClass.contains(DestReg, SrcReg))
992  Opc = PPC::QVFMR;
993  else if (PPC::QSRCRegClass.contains(DestReg, SrcReg))
994  Opc = PPC::QVFMRs;
995  else if (PPC::QBRCRegClass.contains(DestReg, SrcReg))
996  Opc = PPC::QVFMRb;
997  else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
998  Opc = PPC::CROR;
999  else if (PPC::SPERCRegClass.contains(DestReg, SrcReg))
1000  Opc = PPC::EVOR;
1001  else
1002  llvm_unreachable("Impossible reg-to-reg copy");
1003 
1004  const MCInstrDesc &MCID = get(Opc);
1005  if (MCID.getNumOperands() == 3)
1006  BuildMI(MBB, I, DL, MCID, DestReg)
1007  .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
1008  else
1009  BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
1010 }
1011 
1013  const TargetRegisterClass *RC)
1014  const {
1015  const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
1016  int OpcodeIndex = 0;
1017 
1018  if (RC != nullptr) {
1019  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1020  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1021  OpcodeIndex = SOK_Int4Spill;
1022  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1023  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1024  OpcodeIndex = SOK_Int8Spill;
1025  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1026  OpcodeIndex = SOK_Float8Spill;
1027  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1028  OpcodeIndex = SOK_Float4Spill;
1029  } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1030  OpcodeIndex = SOK_SPESpill;
1031  } else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) {
1032  OpcodeIndex = SOK_SPE4Spill;
1033  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1034  OpcodeIndex = SOK_CRSpill;
1035  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1036  OpcodeIndex = SOK_CRBitSpill;
1037  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1038  OpcodeIndex = SOK_VRVectorSpill;
1039  } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1040  OpcodeIndex = SOK_VSXVectorSpill;
1041  } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1042  OpcodeIndex = SOK_VectorFloat8Spill;
1043  } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1044  OpcodeIndex = SOK_VectorFloat4Spill;
1045  } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1046  OpcodeIndex = SOK_VRSaveSpill;
1047  } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1048  OpcodeIndex = SOK_QuadFloat8Spill;
1049  } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1050  OpcodeIndex = SOK_QuadFloat4Spill;
1051  } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1052  OpcodeIndex = SOK_QuadBitSpill;
1053  } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1054  OpcodeIndex = SOK_SpillToVSR;
1055  } else {
1056  llvm_unreachable("Unknown regclass!");
1057  }
1058  } else {
1059  if (PPC::GPRCRegClass.contains(Reg) ||
1060  PPC::GPRC_NOR0RegClass.contains(Reg)) {
1061  OpcodeIndex = SOK_Int4Spill;
1062  } else if (PPC::G8RCRegClass.contains(Reg) ||
1063  PPC::G8RC_NOX0RegClass.contains(Reg)) {
1064  OpcodeIndex = SOK_Int8Spill;
1065  } else if (PPC::F8RCRegClass.contains(Reg)) {
1066  OpcodeIndex = SOK_Float8Spill;
1067  } else if (PPC::F4RCRegClass.contains(Reg)) {
1068  OpcodeIndex = SOK_Float4Spill;
1069  } else if (PPC::CRRCRegClass.contains(Reg)) {
1070  OpcodeIndex = SOK_CRSpill;
1071  } else if (PPC::CRBITRCRegClass.contains(Reg)) {
1072  OpcodeIndex = SOK_CRBitSpill;
1073  } else if (PPC::VRRCRegClass.contains(Reg)) {
1074  OpcodeIndex = SOK_VRVectorSpill;
1075  } else if (PPC::VSRCRegClass.contains(Reg)) {
1076  OpcodeIndex = SOK_VSXVectorSpill;
1077  } else if (PPC::VSFRCRegClass.contains(Reg)) {
1078  OpcodeIndex = SOK_VectorFloat8Spill;
1079  } else if (PPC::VSSRCRegClass.contains(Reg)) {
1080  OpcodeIndex = SOK_VectorFloat4Spill;
1081  } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1082  OpcodeIndex = SOK_VRSaveSpill;
1083  } else if (PPC::QFRCRegClass.contains(Reg)) {
1084  OpcodeIndex = SOK_QuadFloat8Spill;
1085  } else if (PPC::QSRCRegClass.contains(Reg)) {
1086  OpcodeIndex = SOK_QuadFloat4Spill;
1087  } else if (PPC::QBRCRegClass.contains(Reg)) {
1088  OpcodeIndex = SOK_QuadBitSpill;
1089  } else if (PPC::SPILLTOVSRRCRegClass.contains(Reg)) {
1090  OpcodeIndex = SOK_SpillToVSR;
1091  } else {
1092  llvm_unreachable("Unknown regclass!");
1093  }
1094  }
1095  return OpcodesForSpill[OpcodeIndex];
1096 }
1097 
1098 unsigned
1100  const TargetRegisterClass *RC) const {
1101  const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
1102  int OpcodeIndex = 0;
1103 
1104  if (RC != nullptr) {
1105  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1106  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1107  OpcodeIndex = SOK_Int4Spill;
1108  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1109  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1110  OpcodeIndex = SOK_Int8Spill;
1111  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1112  OpcodeIndex = SOK_Float8Spill;
1113  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1114  OpcodeIndex = SOK_Float4Spill;
1115  } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1116  OpcodeIndex = SOK_SPESpill;
1117  } else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) {
1118  OpcodeIndex = SOK_SPE4Spill;
1119  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1120  OpcodeIndex = SOK_CRSpill;
1121  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1122  OpcodeIndex = SOK_CRBitSpill;
1123  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1124  OpcodeIndex = SOK_VRVectorSpill;
1125  } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1126  OpcodeIndex = SOK_VSXVectorSpill;
1127  } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1128  OpcodeIndex = SOK_VectorFloat8Spill;
1129  } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1130  OpcodeIndex = SOK_VectorFloat4Spill;
1131  } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1132  OpcodeIndex = SOK_VRSaveSpill;
1133  } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1134  OpcodeIndex = SOK_QuadFloat8Spill;
1135  } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1136  OpcodeIndex = SOK_QuadFloat4Spill;
1137  } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1138  OpcodeIndex = SOK_QuadBitSpill;
1139  } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1140  OpcodeIndex = SOK_SpillToVSR;
1141  } else {
1142  llvm_unreachable("Unknown regclass!");
1143  }
1144  } else {
1145  if (PPC::GPRCRegClass.contains(Reg) ||
1146  PPC::GPRC_NOR0RegClass.contains(Reg)) {
1147  OpcodeIndex = SOK_Int4Spill;
1148  } else if (PPC::G8RCRegClass.contains(Reg) ||
1149  PPC::G8RC_NOX0RegClass.contains(Reg)) {
1150  OpcodeIndex = SOK_Int8Spill;
1151  } else if (PPC::F8RCRegClass.contains(Reg)) {
1152  OpcodeIndex = SOK_Float8Spill;
1153  } else if (PPC::F4RCRegClass.contains(Reg)) {
1154  OpcodeIndex = SOK_Float4Spill;
1155  } else if (PPC::CRRCRegClass.contains(Reg)) {
1156  OpcodeIndex = SOK_CRSpill;
1157  } else if (PPC::CRBITRCRegClass.contains(Reg)) {
1158  OpcodeIndex = SOK_CRBitSpill;
1159  } else if (PPC::VRRCRegClass.contains(Reg)) {
1160  OpcodeIndex = SOK_VRVectorSpill;
1161  } else if (PPC::VSRCRegClass.contains(Reg)) {
1162  OpcodeIndex = SOK_VSXVectorSpill;
1163  } else if (PPC::VSFRCRegClass.contains(Reg)) {
1164  OpcodeIndex = SOK_VectorFloat8Spill;
1165  } else if (PPC::VSSRCRegClass.contains(Reg)) {
1166  OpcodeIndex = SOK_VectorFloat4Spill;
1167  } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1168  OpcodeIndex = SOK_VRSaveSpill;
1169  } else if (PPC::QFRCRegClass.contains(Reg)) {
1170  OpcodeIndex = SOK_QuadFloat8Spill;
1171  } else if (PPC::QSRCRegClass.contains(Reg)) {
1172  OpcodeIndex = SOK_QuadFloat4Spill;
1173  } else if (PPC::QBRCRegClass.contains(Reg)) {
1174  OpcodeIndex = SOK_QuadBitSpill;
1175  } else if (PPC::SPILLTOVSRRCRegClass.contains(Reg)) {
1176  OpcodeIndex = SOK_SpillToVSR;
1177  } else {
1178  llvm_unreachable("Unknown regclass!");
1179  }
1180  }
1181  return OpcodesForSpill[OpcodeIndex];
1182 }
1183 
1184 void PPCInstrInfo::StoreRegToStackSlot(
1185  MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx,
1186  const TargetRegisterClass *RC,
1187  SmallVectorImpl<MachineInstr *> &NewMIs) const {
1188  unsigned Opcode = getStoreOpcodeForSpill(PPC::NoRegister, RC);
1189  DebugLoc DL;
1190 
1191  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1192  FuncInfo->setHasSpills();
1193 
1195  BuildMI(MF, DL, get(Opcode)).addReg(SrcReg, getKillRegState(isKill)),
1196  FrameIdx));
1197 
1198  if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1199  PPC::CRBITRCRegClass.hasSubClassEq(RC))
1200  FuncInfo->setSpillsCR();
1201 
1202  if (PPC::VRSAVERCRegClass.hasSubClassEq(RC))
1203  FuncInfo->setSpillsVRSAVE();
1204 
1205  if (isXFormMemOp(Opcode))
1206  FuncInfo->setHasNonRISpills();
1207 }
1208 
1211  unsigned SrcReg, bool isKill,
1212  int FrameIdx,
1213  const TargetRegisterClass *RC,
1214  const TargetRegisterInfo *TRI) const {
1215  MachineFunction &MF = *MBB.getParent();
1217 
1218  // We need to avoid a situation in which the value from a VRRC register is
1219  // spilled using an Altivec instruction and reloaded into a VSRC register
1220  // using a VSX instruction. The issue with this is that the VSX
1221  // load/store instructions swap the doublewords in the vector and the Altivec
1222  // ones don't. The register classes on the spill/reload may be different if
1223  // the register is defined using an Altivec instruction and is then used by a
1224  // VSX instruction.
1225  RC = updatedRC(RC);
1226 
1227  StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs);
1228 
1229  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1230  MBB.insert(MI, NewMIs[i]);
1231 
1232  const MachineFrameInfo &MFI = MF.getFrameInfo();
1234  MachinePointerInfo::getFixedStack(MF, FrameIdx),
1236  MFI.getObjectAlignment(FrameIdx));
1237  NewMIs.back()->addMemOperand(MF, MMO);
1238 }
1239 
1240 void PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
1241  unsigned DestReg, int FrameIdx,
1242  const TargetRegisterClass *RC,
1244  const {
1245  unsigned Opcode = getLoadOpcodeForSpill(PPC::NoRegister, RC);
1246  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opcode), DestReg),
1247  FrameIdx));
1248  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1249 
1250  if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1251  PPC::CRBITRCRegClass.hasSubClassEq(RC))
1252  FuncInfo->setSpillsCR();
1253 
1254  if (PPC::VRSAVERCRegClass.hasSubClassEq(RC))
1255  FuncInfo->setSpillsVRSAVE();
1256 
1257  if (isXFormMemOp(Opcode))
1258  FuncInfo->setHasNonRISpills();
1259 }
1260 
1261 void
1264  unsigned DestReg, int FrameIdx,
1265  const TargetRegisterClass *RC,
1266  const TargetRegisterInfo *TRI) const {
1267  MachineFunction &MF = *MBB.getParent();
1269  DebugLoc DL;
1270  if (MI != MBB.end()) DL = MI->getDebugLoc();
1271 
1272  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1273  FuncInfo->setHasSpills();
1274 
1275  // We need to avoid a situation in which the value from a VRRC register is
1276  // spilled using an Altivec instruction and reloaded into a VSRC register
1277  // using a VSX instruction. The issue with this is that the VSX
1278  // load/store instructions swap the doublewords in the vector and the Altivec
1279  // ones don't. The register classes on the spill/reload may be different if
1280  // the register is defined using an Altivec instruction and is then used by a
1281  // VSX instruction.
1282  if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
1283  RC = &PPC::VSRCRegClass;
1284 
1285  LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
1286 
1287  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1288  MBB.insert(MI, NewMIs[i]);
1289 
1290  const MachineFrameInfo &MFI = MF.getFrameInfo();
1292  MachinePointerInfo::getFixedStack(MF, FrameIdx),
1294  MFI.getObjectAlignment(FrameIdx));
1295  NewMIs.back()->addMemOperand(MF, MMO);
1296 }
1297 
1298 bool PPCInstrInfo::
1300  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
1301  if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
1302  Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
1303  else
1304  // Leave the CR# the same, but invert the condition.
1305  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
1306  return false;
1307 }
1308 
1310  unsigned Reg, MachineRegisterInfo *MRI) const {
1311  // For some instructions, it is legal to fold ZERO into the RA register field.
1312  // A zero immediate should always be loaded with a single li.
1313  unsigned DefOpc = DefMI.getOpcode();
1314  if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
1315  return false;
1316  if (!DefMI.getOperand(1).isImm())
1317  return false;
1318  if (DefMI.getOperand(1).getImm() != 0)
1319  return false;
1320 
1321  // Note that we cannot here invert the arguments of an isel in order to fold
1322  // a ZERO into what is presented as the second argument. All we have here
1323  // is the condition bit, and that might come from a CR-logical bit operation.
1324 
1325  const MCInstrDesc &UseMCID = UseMI.getDesc();
1326 
1327  // Only fold into real machine instructions.
1328  if (UseMCID.isPseudo())
1329  return false;
1330 
1331  unsigned UseIdx;
1332  for (UseIdx = 0; UseIdx < UseMI.getNumOperands(); ++UseIdx)
1333  if (UseMI.getOperand(UseIdx).isReg() &&
1334  UseMI.getOperand(UseIdx).getReg() == Reg)
1335  break;
1336 
1337  assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI");
1338  assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
1339 
1340  const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
1341 
1342  // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
1343  // register (which might also be specified as a pointer class kind).
1344  if (UseInfo->isLookupPtrRegClass()) {
1345  if (UseInfo->RegClass /* Kind */ != 1)
1346  return false;
1347  } else {
1348  if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
1349  UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
1350  return false;
1351  }
1352 
1353  // Make sure this is not tied to an output register (or otherwise
1354  // constrained). This is true for ST?UX registers, for example, which
1355  // are tied to their output registers.
1356  if (UseInfo->Constraints != 0)
1357  return false;
1358 
1359  unsigned ZeroReg;
1360  if (UseInfo->isLookupPtrRegClass()) {
1361  bool isPPC64 = Subtarget.isPPC64();
1362  ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
1363  } else {
1364  ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
1365  PPC::ZERO8 : PPC::ZERO;
1366  }
1367 
1368  bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1369  UseMI.getOperand(UseIdx).setReg(ZeroReg);
1370 
1371  if (DeleteDef)
1372  DefMI.eraseFromParent();
1373 
1374  return true;
1375 }
1376 
1378  for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
1379  I != IE; ++I)
1380  if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
1381  return true;
1382  return false;
1383 }
1384 
1385 // We should make sure that, if we're going to predicate both sides of a
1386 // condition (a diamond), that both sides don't define the counter register. We
1387 // can predicate counter-decrement-based branches, but while that predicates
1388 // the branching, it does not predicate the counter decrement. If we tried to
1389 // merge the triangle into one predicated block, we'd decrement the counter
1390 // twice.
1392  unsigned NumT, unsigned ExtraT,
1393  MachineBasicBlock &FMBB,
1394  unsigned NumF, unsigned ExtraF,
1395  BranchProbability Probability) const {
1396  return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
1397 }
1398 
1399 
1401  // The predicated branches are identified by their type, not really by the
1402  // explicit presence of a predicate. Furthermore, some of them can be
1403  // predicated more than once. Because if conversion won't try to predicate
1404  // any instruction which already claims to be predicated (by returning true
1405  // here), always return false. In doing so, we let isPredicable() be the
1406  // final word on whether not the instruction can be (further) predicated.
1407 
1408  return false;
1409 }
1410 
1412  if (!MI.isTerminator())
1413  return false;
1414 
1415  // Conditional branch is a special case.
1416  if (MI.isBranch() && !MI.isBarrier())
1417  return true;
1418 
1419  return !isPredicated(MI);
1420 }
1421 
1423  ArrayRef<MachineOperand> Pred) const {
1424  unsigned OpC = MI.getOpcode();
1425  if (OpC == PPC::BLR || OpC == PPC::BLR8) {
1426  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1427  bool isPPC64 = Subtarget.isPPC64();
1428  MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR)
1429  : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
1430  } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1431  MI.setDesc(get(PPC::BCLR));
1433  .addReg(Pred[1].getReg());
1434  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1435  MI.setDesc(get(PPC::BCLRn));
1437  .addReg(Pred[1].getReg());
1438  } else {
1439  MI.setDesc(get(PPC::BCCLR));
1441  .addImm(Pred[0].getImm())
1442  .addReg(Pred[1].getReg());
1443  }
1444 
1445  return true;
1446  } else if (OpC == PPC::B) {
1447  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1448  bool isPPC64 = Subtarget.isPPC64();
1449  MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
1450  : (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
1451  } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1452  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1453  MI.RemoveOperand(0);
1454 
1455  MI.setDesc(get(PPC::BC));
1457  .addReg(Pred[1].getReg())
1458  .addMBB(MBB);
1459  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1460  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1461  MI.RemoveOperand(0);
1462 
1463  MI.setDesc(get(PPC::BCn));
1465  .addReg(Pred[1].getReg())
1466  .addMBB(MBB);
1467  } else {
1468  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1469  MI.RemoveOperand(0);
1470 
1471  MI.setDesc(get(PPC::BCC));
1473  .addImm(Pred[0].getImm())
1474  .addReg(Pred[1].getReg())
1475  .addMBB(MBB);
1476  }
1477 
1478  return true;
1479  } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 ||
1480  OpC == PPC::BCTRL || OpC == PPC::BCTRL8) {
1481  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
1482  llvm_unreachable("Cannot predicate bctr[l] on the ctr register");
1483 
1484  bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
1485  bool isPPC64 = Subtarget.isPPC64();
1486 
1487  if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1488  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8)
1489  : (setLR ? PPC::BCCTRL : PPC::BCCTR)));
1491  .addReg(Pred[1].getReg());
1492  return true;
1493  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1494  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n)
1495  : (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
1497  .addReg(Pred[1].getReg());
1498  return true;
1499  }
1500 
1501  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8)
1502  : (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
1504  .addImm(Pred[0].getImm())
1505  .addReg(Pred[1].getReg());
1506  return true;
1507  }
1508 
1509  return false;
1510 }
1511 
1513  ArrayRef<MachineOperand> Pred2) const {
1514  assert(Pred1.size() == 2 && "Invalid PPC first predicate");
1515  assert(Pred2.size() == 2 && "Invalid PPC second predicate");
1516 
1517  if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1518  return false;
1519  if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
1520  return false;
1521 
1522  // P1 can only subsume P2 if they test the same condition register.
1523  if (Pred1[1].getReg() != Pred2[1].getReg())
1524  return false;
1525 
1526  PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
1527  PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
1528 
1529  if (P1 == P2)
1530  return true;
1531 
1532  // Does P1 subsume P2, e.g. GE subsumes GT.
1533  if (P1 == PPC::PRED_LE &&
1534  (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
1535  return true;
1536  if (P1 == PPC::PRED_GE &&
1537  (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
1538  return true;
1539 
1540  return false;
1541 }
1542 
1544  std::vector<MachineOperand> &Pred) const {
1545  // Note: At the present time, the contents of Pred from this function is
1546  // unused by IfConversion. This implementation follows ARM by pushing the
1547  // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
1548  // predicate, instructions defining CTR or CTR8 are also included as
1549  // predicate-defining instructions.
1550 
1551  const TargetRegisterClass *RCs[] =
1552  { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1553  &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1554 
1555  bool Found = false;
1556  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1557  const MachineOperand &MO = MI.getOperand(i);
1558  for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
1559  const TargetRegisterClass *RC = RCs[c];
1560  if (MO.isReg()) {
1561  if (MO.isDef() && RC->contains(MO.getReg())) {
1562  Pred.push_back(MO);
1563  Found = true;
1564  }
1565  } else if (MO.isRegMask()) {
1566  for (TargetRegisterClass::iterator I = RC->begin(),
1567  IE = RC->end(); I != IE; ++I)
1568  if (MO.clobbersPhysReg(*I)) {
1569  Pred.push_back(MO);
1570  Found = true;
1571  }
1572  }
1573  }
1574  }
1575 
1576  return Found;
1577 }
1578 
1580  unsigned OpC = MI.getOpcode();
1581  switch (OpC) {
1582  default:
1583  return false;
1584  case PPC::B:
1585  case PPC::BLR:
1586  case PPC::BLR8:
1587  case PPC::BCTR:
1588  case PPC::BCTR8:
1589  case PPC::BCTRL:
1590  case PPC::BCTRL8:
1591  return true;
1592  }
1593 }
1594 
1595 bool PPCInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1596  unsigned &SrcReg2, int &Mask,
1597  int &Value) const {
1598  unsigned Opc = MI.getOpcode();
1599 
1600  switch (Opc) {
1601  default: return false;
1602  case PPC::CMPWI:
1603  case PPC::CMPLWI:
1604  case PPC::CMPDI:
1605  case PPC::CMPLDI:
1606  SrcReg = MI.getOperand(1).getReg();
1607  SrcReg2 = 0;
1608  Value = MI.getOperand(2).getImm();
1609  Mask = 0xFFFF;
1610  return true;
1611  case PPC::CMPW:
1612  case PPC::CMPLW:
1613  case PPC::CMPD:
1614  case PPC::CMPLD:
1615  case PPC::FCMPUS:
1616  case PPC::FCMPUD:
1617  SrcReg = MI.getOperand(1).getReg();
1618  SrcReg2 = MI.getOperand(2).getReg();
1619  Value = 0;
1620  Mask = 0;
1621  return true;
1622  }
1623 }
1624 
1625 bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1626  unsigned SrcReg2, int Mask, int Value,
1627  const MachineRegisterInfo *MRI) const {
1628  if (DisableCmpOpt)
1629  return false;
1630 
1631  int OpC = CmpInstr.getOpcode();
1632  unsigned CRReg = CmpInstr.getOperand(0).getReg();
1633 
1634  // FP record forms set CR1 based on the exception status bits, not a
1635  // comparison with zero.
1636  if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
1637  return false;
1638 
1639  // The record forms set the condition register based on a signed comparison
1640  // with zero (so says the ISA manual). This is not as straightforward as it
1641  // seems, however, because this is always a 64-bit comparison on PPC64, even
1642  // for instructions that are 32-bit in nature (like slw for example).
1643  // So, on PPC32, for unsigned comparisons, we can use the record forms only
1644  // for equality checks (as those don't depend on the sign). On PPC64,
1645  // we are restricted to equality for unsigned 64-bit comparisons and for
1646  // signed 32-bit comparisons the applicability is more restricted.
1647  bool isPPC64 = Subtarget.isPPC64();
1648  bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
1649  bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
1650  bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
1651 
1652  // Get the unique definition of SrcReg.
1653  MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1654  if (!MI) return false;
1655 
1656  bool equalityOnly = false;
1657  bool noSub = false;
1658  if (isPPC64) {
1659  if (is32BitSignedCompare) {
1660  // We can perform this optimization only if MI is sign-extending.
1661  if (isSignExtended(*MI))
1662  noSub = true;
1663  else
1664  return false;
1665  } else if (is32BitUnsignedCompare) {
1666  // We can perform this optimization, equality only, if MI is
1667  // zero-extending.
1668  if (isZeroExtended(*MI)) {
1669  noSub = true;
1670  equalityOnly = true;
1671  } else
1672  return false;
1673  } else
1674  equalityOnly = is64BitUnsignedCompare;
1675  } else
1676  equalityOnly = is32BitUnsignedCompare;
1677 
1678  if (equalityOnly) {
1679  // We need to check the uses of the condition register in order to reject
1680  // non-equality comparisons.
1682  I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1683  I != IE; ++I) {
1684  MachineInstr *UseMI = &*I;
1685  if (UseMI->getOpcode() == PPC::BCC) {
1686  PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
1687  unsigned PredCond = PPC::getPredicateCondition(Pred);
1688  // We ignore hint bits when checking for non-equality comparisons.
1689  if (PredCond != PPC::PRED_EQ && PredCond != PPC::PRED_NE)
1690  return false;
1691  } else if (UseMI->getOpcode() == PPC::ISEL ||
1692  UseMI->getOpcode() == PPC::ISEL8) {
1693  unsigned SubIdx = UseMI->getOperand(3).getSubReg();
1694  if (SubIdx != PPC::sub_eq)
1695  return false;
1696  } else
1697  return false;
1698  }
1699  }
1700 
1701  MachineBasicBlock::iterator I = CmpInstr;
1702 
1703  // Scan forward to find the first use of the compare.
1704  for (MachineBasicBlock::iterator EL = CmpInstr.getParent()->end(); I != EL;
1705  ++I) {
1706  bool FoundUse = false;
1708  J = MRI->use_instr_begin(CRReg), JE = MRI->use_instr_end();
1709  J != JE; ++J)
1710  if (&*J == &*I) {
1711  FoundUse = true;
1712  break;
1713  }
1714 
1715  if (FoundUse)
1716  break;
1717  }
1718 
1721 
1722  // There are two possible candidates which can be changed to set CR[01].
1723  // One is MI, the other is a SUB instruction.
1724  // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
1725  MachineInstr *Sub = nullptr;
1726  if (SrcReg2 != 0)
1727  // MI is not a candidate for CMPrr.
1728  MI = nullptr;
1729  // FIXME: Conservatively refuse to convert an instruction which isn't in the
1730  // same BB as the comparison. This is to allow the check below to avoid calls
1731  // (and other explicit clobbers); instead we should really check for these
1732  // more explicitly (in at least a few predecessors).
1733  else if (MI->getParent() != CmpInstr.getParent())
1734  return false;
1735  else if (Value != 0) {
1736  // The record-form instructions set CR bit based on signed comparison
1737  // against 0. We try to convert a compare against 1 or -1 into a compare
1738  // against 0 to exploit record-form instructions. For example, we change
1739  // the condition "greater than -1" into "greater than or equal to 0"
1740  // and "less than 1" into "less than or equal to 0".
1741 
1742  // Since we optimize comparison based on a specific branch condition,
1743  // we don't optimize if condition code is used by more than once.
1744  if (equalityOnly || !MRI->hasOneUse(CRReg))
1745  return false;
1746 
1747  MachineInstr *UseMI = &*MRI->use_instr_begin(CRReg);
1748  if (UseMI->getOpcode() != PPC::BCC)
1749  return false;
1750 
1751  PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
1752  PPC::Predicate NewPred = Pred;
1753  unsigned PredCond = PPC::getPredicateCondition(Pred);
1754  unsigned PredHint = PPC::getPredicateHint(Pred);
1755  int16_t Immed = (int16_t)Value;
1756 
1757  // When modifying the condition in the predicate, we propagate hint bits
1758  // from the original predicate to the new one.
1759  if (Immed == -1 && PredCond == PPC::PRED_GT)
1760  // We convert "greater than -1" into "greater than or equal to 0",
1761  // since we are assuming signed comparison by !equalityOnly
1762  NewPred = PPC::getPredicate(PPC::PRED_GE, PredHint);
1763  else if (Immed == -1 && PredCond == PPC::PRED_LE)
1764  // We convert "less than or equal to -1" into "less than 0".
1765  NewPred = PPC::getPredicate(PPC::PRED_LT, PredHint);
1766  else if (Immed == 1 && PredCond == PPC::PRED_LT)
1767  // We convert "less than 1" into "less than or equal to 0".
1768  NewPred = PPC::getPredicate(PPC::PRED_LE, PredHint);
1769  else if (Immed == 1 && PredCond == PPC::PRED_GE)
1770  // We convert "greater than or equal to 1" into "greater than 0".
1771  NewPred = PPC::getPredicate(PPC::PRED_GT, PredHint);
1772  else
1773  return false;
1774 
1775  PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1776  NewPred));
1777  }
1778 
1779  // Search for Sub.
1781  --I;
1782 
1783  // Get ready to iterate backward from CmpInstr.
1784  MachineBasicBlock::iterator E = MI, B = CmpInstr.getParent()->begin();
1785 
1786  for (; I != E && !noSub; --I) {
1787  const MachineInstr &Instr = *I;
1788  unsigned IOpC = Instr.getOpcode();
1789 
1790  if (&*I != &CmpInstr && (Instr.modifiesRegister(PPC::CR0, TRI) ||
1791  Instr.readsRegister(PPC::CR0, TRI)))
1792  // This instruction modifies or uses the record condition register after
1793  // the one we want to change. While we could do this transformation, it
1794  // would likely not be profitable. This transformation removes one
1795  // instruction, and so even forcing RA to generate one move probably
1796  // makes it unprofitable.
1797  return false;
1798 
1799  // Check whether CmpInstr can be made redundant by the current instruction.
1800  if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
1801  OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
1802  (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
1803  ((Instr.getOperand(1).getReg() == SrcReg &&
1804  Instr.getOperand(2).getReg() == SrcReg2) ||
1805  (Instr.getOperand(1).getReg() == SrcReg2 &&
1806  Instr.getOperand(2).getReg() == SrcReg))) {
1807  Sub = &*I;
1808  break;
1809  }
1810 
1811  if (I == B)
1812  // The 'and' is below the comparison instruction.
1813  return false;
1814  }
1815 
1816  // Return false if no candidates exist.
1817  if (!MI && !Sub)
1818  return false;
1819 
1820  // The single candidate is called MI.
1821  if (!MI) MI = Sub;
1822 
1823  int NewOpC = -1;
1824  int MIOpC = MI->getOpcode();
1825  if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8)
1826  NewOpC = MIOpC;
1827  else {
1828  NewOpC = PPC::getRecordFormOpcode(MIOpC);
1829  if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
1830  NewOpC = MIOpC;
1831  }
1832 
1833  // FIXME: On the non-embedded POWER architectures, only some of the record
1834  // forms are fast, and we should use only the fast ones.
1835 
1836  // The defining instruction has a record form (or is already a record
1837  // form). It is possible, however, that we'll need to reverse the condition
1838  // code of the users.
1839  if (NewOpC == -1)
1840  return false;
1841 
1842  // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
1843  // needs to be updated to be based on SUB. Push the condition code
1844  // operands to OperandsToUpdate. If it is safe to remove CmpInstr, the
1845  // condition code of these operands will be modified.
1846  // Here, Value == 0 means we haven't converted comparison against 1 or -1 to
1847  // comparison against 0, which may modify predicate.
1848  bool ShouldSwap = false;
1849  if (Sub && Value == 0) {
1850  ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1851  Sub->getOperand(2).getReg() == SrcReg;
1852 
1853  // The operands to subf are the opposite of sub, so only in the fixed-point
1854  // case, invert the order.
1855  ShouldSwap = !ShouldSwap;
1856  }
1857 
1858  if (ShouldSwap)
1860  I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1861  I != IE; ++I) {
1862  MachineInstr *UseMI = &*I;
1863  if (UseMI->getOpcode() == PPC::BCC) {
1864  PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
1865  unsigned PredCond = PPC::getPredicateCondition(Pred);
1866  assert((!equalityOnly ||
1867  PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE) &&
1868  "Invalid predicate for equality-only optimization");
1869  (void)PredCond; // To suppress warning in release build.
1870  PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1871  PPC::getSwappedPredicate(Pred)));
1872  } else if (UseMI->getOpcode() == PPC::ISEL ||
1873  UseMI->getOpcode() == PPC::ISEL8) {
1874  unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
1875  assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
1876  "Invalid CR bit for equality-only optimization");
1877 
1878  if (NewSubReg == PPC::sub_lt)
1879  NewSubReg = PPC::sub_gt;
1880  else if (NewSubReg == PPC::sub_gt)
1881  NewSubReg = PPC::sub_lt;
1882 
1883  SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)),
1884  NewSubReg));
1885  } else // We need to abort on a user we don't understand.
1886  return false;
1887  }
1888  assert(!(Value != 0 && ShouldSwap) &&
1889  "Non-zero immediate support and ShouldSwap"
1890  "may conflict in updating predicate");
1891 
1892  // Create a new virtual register to hold the value of the CR set by the
1893  // record-form instruction. If the instruction was not previously in
1894  // record form, then set the kill flag on the CR.
1895  CmpInstr.eraseFromParent();
1896 
1898  BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
1899  get(TargetOpcode::COPY), CRReg)
1900  .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
1901 
1902  // Even if CR0 register were dead before, it is alive now since the
1903  // instruction we just built uses it.
1904  MI->clearRegisterDeads(PPC::CR0);
1905 
1906  if (MIOpC != NewOpC) {
1907  // We need to be careful here: we're replacing one instruction with
1908  // another, and we need to make sure that we get all of the right
1909  // implicit uses and defs. On the other hand, the caller may be holding
1910  // an iterator to this instruction, and so we can't delete it (this is
1911  // specifically the case if this is the instruction directly after the
1912  // compare).
1913 
1914  // Rotates are expensive instructions. If we're emitting a record-form
1915  // rotate that can just be an andi, we should just emit the andi.
1916  if ((MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINM8) &&
1917  MI->getOperand(2).getImm() == 0) {
1918  int64_t MB = MI->getOperand(3).getImm();
1919  int64_t ME = MI->getOperand(4).getImm();
1920  if (MB < ME && MB >= 16) {
1921  uint64_t Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
1922  NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDIo : PPC::ANDIo8;
1923  MI->RemoveOperand(4);
1924  MI->RemoveOperand(3);
1925  MI->getOperand(2).setImm(Mask);
1926  NumRcRotatesConvertedToRcAnd++;
1927  }
1928  } else if (MIOpC == PPC::RLDICL && MI->getOperand(2).getImm() == 0) {
1929  int64_t MB = MI->getOperand(3).getImm();
1930  if (MB >= 48) {
1931  uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
1932  NewOpC = PPC::ANDIo8;
1933  MI->RemoveOperand(3);
1934  MI->getOperand(2).setImm(Mask);
1935  NumRcRotatesConvertedToRcAnd++;
1936  }
1937  }
1938 
1939  const MCInstrDesc &NewDesc = get(NewOpC);
1940  MI->setDesc(NewDesc);
1941 
1942  if (NewDesc.ImplicitDefs)
1943  for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs();
1944  *ImpDefs; ++ImpDefs)
1945  if (!MI->definesRegister(*ImpDefs))
1946  MI->addOperand(*MI->getParent()->getParent(),
1947  MachineOperand::CreateReg(*ImpDefs, true, true));
1948  if (NewDesc.ImplicitUses)
1949  for (const MCPhysReg *ImpUses = NewDesc.getImplicitUses();
1950  *ImpUses; ++ImpUses)
1951  if (!MI->readsRegister(*ImpUses))
1952  MI->addOperand(*MI->getParent()->getParent(),
1953  MachineOperand::CreateReg(*ImpUses, false, true));
1954  }
1955  assert(MI->definesRegister(PPC::CR0) &&
1956  "Record-form instruction does not define cr0?");
1957 
1958  // Modify the condition code of operands in OperandsToUpdate.
1959  // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
1960  // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
1961  for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
1962  PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
1963 
1964  for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
1965  SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
1966 
1967  return true;
1968 }
1969 
1970 /// GetInstSize - Return the number of bytes of code the specified
1971 /// instruction may be. This returns the maximum number of bytes.
1972 ///
1974  unsigned Opcode = MI.getOpcode();
1975 
1976  if (Opcode == PPC::INLINEASM) {
1977  const MachineFunction *MF = MI.getParent()->getParent();
1978  const char *AsmStr = MI.getOperand(0).getSymbolName();
1979  return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1980  } else if (Opcode == TargetOpcode::STACKMAP) {
1981  StackMapOpers Opers(&MI);
1982  return Opers.getNumPatchBytes();
1983  } else if (Opcode == TargetOpcode::PATCHPOINT) {
1984  PatchPointOpers Opers(&MI);
1985  return Opers.getNumPatchBytes();
1986  } else {
1987  return get(Opcode).getSize();
1988  }
1989 }
1990 
1991 std::pair<unsigned, unsigned>
1993  const unsigned Mask = PPCII::MO_ACCESS_MASK;
1994  return std::make_pair(TF & Mask, TF & ~Mask);
1995 }
1996 
1999  using namespace PPCII;
2000  static const std::pair<unsigned, const char *> TargetFlags[] = {
2001  {MO_LO, "ppc-lo"},
2002  {MO_HA, "ppc-ha"},
2003  {MO_TPREL_LO, "ppc-tprel-lo"},
2004  {MO_TPREL_HA, "ppc-tprel-ha"},
2005  {MO_DTPREL_LO, "ppc-dtprel-lo"},
2006  {MO_TLSLD_LO, "ppc-tlsld-lo"},
2007  {MO_TOC_LO, "ppc-toc-lo"},
2008  {MO_TLS, "ppc-tls"}};
2009  return makeArrayRef(TargetFlags);
2010 }
2011 
2014  using namespace PPCII;
2015  static const std::pair<unsigned, const char *> TargetFlags[] = {
2016  {MO_PLT, "ppc-plt"},
2017  {MO_PIC_FLAG, "ppc-pic"},
2018  {MO_NLP_FLAG, "ppc-nlp"},
2019  {MO_NLP_HIDDEN_FLAG, "ppc-nlp-hidden"}};
2020  return makeArrayRef(TargetFlags);
2021 }
2022 
2023 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
2024 // The VSX versions have the advantage of a full 64-register target whereas
2025 // the FP ones have the advantage of lower latency and higher throughput. So
2026 // what we are after is using the faster instructions in low register pressure
2027 // situations and using the larger register file in high register pressure
2028 // situations.
2030  unsigned UpperOpcode, LowerOpcode;
2031  switch (MI.getOpcode()) {
2032  case PPC::DFLOADf32:
2033  UpperOpcode = PPC::LXSSP;
2034  LowerOpcode = PPC::LFS;
2035  break;
2036  case PPC::DFLOADf64:
2037  UpperOpcode = PPC::LXSD;
2038  LowerOpcode = PPC::LFD;
2039  break;
2040  case PPC::DFSTOREf32:
2041  UpperOpcode = PPC::STXSSP;
2042  LowerOpcode = PPC::STFS;
2043  break;
2044  case PPC::DFSTOREf64:
2045  UpperOpcode = PPC::STXSD;
2046  LowerOpcode = PPC::STFD;
2047  break;
2048  case PPC::XFLOADf32:
2049  UpperOpcode = PPC::LXSSPX;
2050  LowerOpcode = PPC::LFSX;
2051  break;
2052  case PPC::XFLOADf64:
2053  UpperOpcode = PPC::LXSDX;
2054  LowerOpcode = PPC::LFDX;
2055  break;
2056  case PPC::XFSTOREf32:
2057  UpperOpcode = PPC::STXSSPX;
2058  LowerOpcode = PPC::STFSX;
2059  break;
2060  case PPC::XFSTOREf64:
2061  UpperOpcode = PPC::STXSDX;
2062  LowerOpcode = PPC::STFDX;
2063  break;
2064  case PPC::LIWAX:
2065  UpperOpcode = PPC::LXSIWAX;
2066  LowerOpcode = PPC::LFIWAX;
2067  break;
2068  case PPC::LIWZX:
2069  UpperOpcode = PPC::LXSIWZX;
2070  LowerOpcode = PPC::LFIWZX;
2071  break;
2072  case PPC::STIWX:
2073  UpperOpcode = PPC::STXSIWX;
2074  LowerOpcode = PPC::STFIWX;
2075  break;
2076  default:
2077  llvm_unreachable("Unknown Operation!");
2078  }
2079 
2080  unsigned TargetReg = MI.getOperand(0).getReg();
2081  unsigned Opcode;
2082  if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) ||
2083  (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31))
2084  Opcode = LowerOpcode;
2085  else
2086  Opcode = UpperOpcode;
2087  MI.setDesc(get(Opcode));
2088  return true;
2089 }
2090 
2091 static bool isAnImmediateOperand(const MachineOperand &MO) {
2092  return MO.isCPI() || MO.isGlobal() || MO.isImm();
2093 }
2094 
2096  auto &MBB = *MI.getParent();
2097  auto DL = MI.getDebugLoc();
2098 
2099  switch (MI.getOpcode()) {
2100  case TargetOpcode::LOAD_STACK_GUARD: {
2101  assert(Subtarget.isTargetLinux() &&
2102  "Only Linux target is expected to contain LOAD_STACK_GUARD");
2103  const int64_t Offset = Subtarget.isPPC64() ? -0x7010 : -0x7008;
2104  const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2;
2105  MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ));
2107  .addImm(Offset)
2108  .addReg(Reg);
2109  return true;
2110  }
2111  case PPC::DFLOADf32:
2112  case PPC::DFLOADf64:
2113  case PPC::DFSTOREf32:
2114  case PPC::DFSTOREf64: {
2115  assert(Subtarget.hasP9Vector() &&
2116  "Invalid D-Form Pseudo-ops on Pre-P9 target.");
2117  assert(MI.getOperand(2).isReg() &&
2119  "D-form op must have register and immediate operands");
2120  return expandVSXMemPseudo(MI);
2121  }
2122  case PPC::XFLOADf32:
2123  case PPC::XFSTOREf32:
2124  case PPC::LIWAX:
2125  case PPC::LIWZX:
2126  case PPC::STIWX: {
2127  assert(Subtarget.hasP8Vector() &&
2128  "Invalid X-Form Pseudo-ops on Pre-P8 target.");
2129  assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
2130  "X-form op must have register and register operands");
2131  return expandVSXMemPseudo(MI);
2132  }
2133  case PPC::XFLOADf64:
2134  case PPC::XFSTOREf64: {
2135  assert(Subtarget.hasVSX() &&
2136  "Invalid X-Form Pseudo-ops on target that has no VSX.");
2137  assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
2138  "X-form op must have register and register operands");
2139  return expandVSXMemPseudo(MI);
2140  }
2141  case PPC::SPILLTOVSR_LD: {
2142  unsigned TargetReg = MI.getOperand(0).getReg();
2143  if (PPC::VSFRCRegClass.contains(TargetReg)) {
2144  MI.setDesc(get(PPC::DFLOADf64));
2145  return expandPostRAPseudo(MI);
2146  }
2147  else
2148  MI.setDesc(get(PPC::LD));
2149  return true;
2150  }
2151  case PPC::SPILLTOVSR_ST: {
2152  unsigned SrcReg = MI.getOperand(0).getReg();
2153  if (PPC::VSFRCRegClass.contains(SrcReg)) {
2154  NumStoreSPILLVSRRCAsVec++;
2155  MI.setDesc(get(PPC::DFSTOREf64));
2156  return expandPostRAPseudo(MI);
2157  } else {
2158  NumStoreSPILLVSRRCAsGpr++;
2159  MI.setDesc(get(PPC::STD));
2160  }
2161  return true;
2162  }
2163  case PPC::SPILLTOVSR_LDX: {
2164  unsigned TargetReg = MI.getOperand(0).getReg();
2165  if (PPC::VSFRCRegClass.contains(TargetReg))
2166  MI.setDesc(get(PPC::LXSDX));
2167  else
2168  MI.setDesc(get(PPC::LDX));
2169  return true;
2170  }
2171  case PPC::SPILLTOVSR_STX: {
2172  unsigned SrcReg = MI.getOperand(0).getReg();
2173  if (PPC::VSFRCRegClass.contains(SrcReg)) {
2174  NumStoreSPILLVSRRCAsVec++;
2175  MI.setDesc(get(PPC::STXSDX));
2176  } else {
2177  NumStoreSPILLVSRRCAsGpr++;
2178  MI.setDesc(get(PPC::STDX));
2179  }
2180  return true;
2181  }
2182 
2183  case PPC::CFENCE8: {
2184  auto Val = MI.getOperand(0).getReg();
2185  BuildMI(MBB, MI, DL, get(PPC::CMPD), PPC::CR7).addReg(Val).addReg(Val);
2186  BuildMI(MBB, MI, DL, get(PPC::CTRL_DEP))
2188  .addReg(PPC::CR7)
2189  .addImm(1);
2190  MI.setDesc(get(PPC::ISYNC));
2191  MI.RemoveOperand(0);
2192  return true;
2193  }
2194  }
2195  return false;
2196 }
2197 
2198 // Essentially a compile-time implementation of a compare->isel sequence.
2199 // It takes two constants to compare, along with the true/false registers
2200 // and the comparison type (as a subreg to a CR field) and returns one
2201 // of the true/false registers, depending on the comparison results.
2202 static unsigned selectReg(int64_t Imm1, int64_t Imm2, unsigned CompareOpc,
2203  unsigned TrueReg, unsigned FalseReg,
2204  unsigned CRSubReg) {
2205  // Signed comparisons. The immediates are assumed to be sign-extended.
2206  if (CompareOpc == PPC::CMPWI || CompareOpc == PPC::CMPDI) {
2207  switch (CRSubReg) {
2208  default: llvm_unreachable("Unknown integer comparison type.");
2209  case PPC::sub_lt:
2210  return Imm1 < Imm2 ? TrueReg : FalseReg;
2211  case PPC::sub_gt:
2212  return Imm1 > Imm2 ? TrueReg : FalseReg;
2213  case PPC::sub_eq:
2214  return Imm1 == Imm2 ? TrueReg : FalseReg;
2215  }
2216  }
2217  // Unsigned comparisons.
2218  else if (CompareOpc == PPC::CMPLWI || CompareOpc == PPC::CMPLDI) {
2219  switch (CRSubReg) {
2220  default: llvm_unreachable("Unknown integer comparison type.");
2221  case PPC::sub_lt:
2222  return (uint64_t)Imm1 < (uint64_t)Imm2 ? TrueReg : FalseReg;
2223  case PPC::sub_gt:
2224  return (uint64_t)Imm1 > (uint64_t)Imm2 ? TrueReg : FalseReg;
2225  case PPC::sub_eq:
2226  return Imm1 == Imm2 ? TrueReg : FalseReg;
2227  }
2228  }
2229  return PPC::NoRegister;
2230 }
2231 
2232 // Replace an instruction with one that materializes a constant (and sets
2233 // CR0 if the original instruction was a record-form instruction).
2235  const LoadImmediateInfo &LII) const {
2236  // Remove existing operands.
2237  int OperandToKeep = LII.SetCR ? 1 : 0;
2238  for (int i = MI.getNumOperands() - 1; i > OperandToKeep; i--)
2239  MI.RemoveOperand(i);
2240 
2241  // Replace the instruction.
2242  if (LII.SetCR) {
2243  MI.setDesc(get(LII.Is64Bit ? PPC::ANDIo8 : PPC::ANDIo));
2244  // Set the immediate.
2246  .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine);
2247  return;
2248  }
2249  else
2250  MI.setDesc(get(LII.Is64Bit ? PPC::LI8 : PPC::LI));
2251 
2252  // Set the immediate.
2254  .addImm(LII.Imm);
2255 }
2256 
2257 MachineInstr *PPCInstrInfo::getForwardingDefMI(
2258  MachineInstr &MI,
2259  unsigned &OpNoForForwarding,
2260  bool &SeenIntermediateUse) const {
2261  OpNoForForwarding = ~0U;
2262  MachineInstr *DefMI = nullptr;
2265  // If we're in SSA, get the defs through the MRI. Otherwise, only look
2266  // within the basic block to see if the register is defined using an LI/LI8.
2267  if (MRI->isSSA()) {
2268  for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
2269  if (!MI.getOperand(i).isReg())
2270  continue;
2271  unsigned Reg = MI.getOperand(i).getReg();
2273  continue;
2274  unsigned TrueReg = TRI->lookThruCopyLike(Reg, MRI);
2276  DefMI = MRI->getVRegDef(TrueReg);
2277  if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8) {
2278  OpNoForForwarding = i;
2279  break;
2280  }
2281  }
2282  }
2283  } else {
2284  // Looking back through the definition for each operand could be expensive,
2285  // so exit early if this isn't an instruction that either has an immediate
2286  // form or is already an immediate form that we can handle.
2287  ImmInstrInfo III;
2288  unsigned Opc = MI.getOpcode();
2289  bool ConvertibleImmForm =
2290  Opc == PPC::CMPWI || Opc == PPC::CMPLWI ||
2291  Opc == PPC::CMPDI || Opc == PPC::CMPLDI ||
2292  Opc == PPC::ADDI || Opc == PPC::ADDI8 ||
2293  Opc == PPC::ORI || Opc == PPC::ORI8 ||
2294  Opc == PPC::XORI || Opc == PPC::XORI8 ||
2295  Opc == PPC::RLDICL || Opc == PPC::RLDICLo ||
2296  Opc == PPC::RLDICL_32 || Opc == PPC::RLDICL_32_64 ||
2297  Opc == PPC::RLWINM || Opc == PPC::RLWINMo ||
2298  Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
2299  if (!instrHasImmForm(MI, III) && !ConvertibleImmForm)
2300  return nullptr;
2301 
2302  // Don't convert or %X, %Y, %Y since that's just a register move.
2303  if ((Opc == PPC::OR || Opc == PPC::OR8) &&
2304  MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
2305  return nullptr;
2306  for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
2307  MachineOperand &MO = MI.getOperand(i);
2308  SeenIntermediateUse = false;
2309  if (MO.isReg() && MO.isUse() && !MO.isImplicit()) {
2311  It++;
2312  unsigned Reg = MI.getOperand(i).getReg();
2313  // MachineInstr::readsRegister only returns true if the machine
2314  // instruction reads the exact register or its super-register. It
2315  // does not consider uses of sub-registers which seems like strange
2316  // behaviour. Nonetheless, if we end up with a 64-bit register here,
2317  // get the corresponding 32-bit register to check.
2318  if (PPC::G8RCRegClass.contains(Reg))
2319  Reg = Reg - PPC::X0 + PPC::R0;
2320 
2321  // Is this register defined by some form of add-immediate (including
2322  // load-immediate) within this basic block?
2323  for ( ; It != E; ++It) {
2324  if (It->modifiesRegister(Reg, &getRegisterInfo())) {
2325  switch (It->getOpcode()) {
2326  default: break;
2327  case PPC::LI:
2328  case PPC::LI8:
2329  case PPC::ADDItocL:
2330  case PPC::ADDI:
2331  case PPC::ADDI8:
2332  OpNoForForwarding = i;
2333  return &*It;
2334  }
2335  break;
2336  } else if (It->readsRegister(Reg, &getRegisterInfo()))
2337  // If we see another use of this reg between the def and the MI,
2338  // we want to flat it so the def isn't deleted.
2339  SeenIntermediateUse = true;
2340  }
2341  }
2342  }
2343  }
2344  return OpNoForForwarding == ~0U ? nullptr : DefMI;
2345 }
2346 
2347 const unsigned *PPCInstrInfo::getStoreOpcodesForSpillArray() const {
2348  static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = {
2349  // Power 8
2350  {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
2351  PPC::SPILL_CRBIT, PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX,
2352  PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb,
2353  PPC::SPILLTOVSR_ST, PPC::EVSTDD, PPC::SPESTW},
2354  // Power 9
2355  {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
2356  PPC::SPILL_CRBIT, PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32,
2357  PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb,
2358  PPC::SPILLTOVSR_ST}};
2359 
2360  return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0];
2361 }
2362 
2363 const unsigned *PPCInstrInfo::getLoadOpcodesForSpillArray() const {
2364  static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = {
2365  // Power 8
2366  {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
2367  PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX,
2368  PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
2369  PPC::SPILLTOVSR_LD, PPC::EVLDD, PPC::SPELWZ},
2370  // Power 9
2371  {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
2372  PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, PPC::DFLOADf32,
2373  PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
2374  PPC::SPILLTOVSR_LD}};
2375 
2376  return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0];
2377 }
2378 
2379 // If this instruction has an immediate form and one of its operands is a
2380 // result of a load-immediate or an add-immediate, convert it to
2381 // the immediate form if the constant is in range.
2383  MachineInstr **KilledDef) const {
2384  MachineFunction *MF = MI.getParent()->getParent();
2386  bool PostRA = !MRI->isSSA();
2387  bool SeenIntermediateUse = true;
2388  unsigned ForwardingOperand = ~0U;
2389  MachineInstr *DefMI = getForwardingDefMI(MI, ForwardingOperand,
2390  SeenIntermediateUse);
2391  if (!DefMI)
2392  return false;
2393  assert(ForwardingOperand < MI.getNumOperands() &&
2394  "The forwarding operand needs to be valid at this point");
2395  bool KillFwdDefMI = !SeenIntermediateUse &&
2396  MI.getOperand(ForwardingOperand).isKill();
2397  if (KilledDef && KillFwdDefMI)
2398  *KilledDef = DefMI;
2399 
2400  ImmInstrInfo III;
2401  bool HasImmForm = instrHasImmForm(MI, III);
2402  // If this is a reg+reg instruction that has a reg+imm form,
2403  // and one of the operands is produced by an add-immediate,
2404  // try to convert it.
2405  if (HasImmForm && transformToImmFormFedByAdd(MI, III, ForwardingOperand,
2406  *DefMI, KillFwdDefMI))
2407  return true;
2408 
2409  if ((DefMI->getOpcode() != PPC::LI && DefMI->getOpcode() != PPC::LI8) ||
2410  !DefMI->getOperand(1).isImm())
2411  return false;
2412 
2413  int64_t Immediate = DefMI->getOperand(1).getImm();
2414  // Sign-extend to 64-bits.
2415  int64_t SExtImm = ((uint64_t)Immediate & ~0x7FFFuLL) != 0 ?
2416  (Immediate | 0xFFFFFFFFFFFF0000) : Immediate;
2417 
2418  // If this is a reg+reg instruction that has a reg+imm form,
2419  // and one of the operands is produced by LI, convert it now.
2420  if (HasImmForm)
2421  return transformToImmFormFedByLI(MI, III, ForwardingOperand, SExtImm);
2422 
2423  bool ReplaceWithLI = false;
2424  bool Is64BitLI = false;
2425  int64_t NewImm = 0;
2426  bool SetCR = false;
2427  unsigned Opc = MI.getOpcode();
2428  switch (Opc) {
2429  default: return false;
2430 
2431  // FIXME: Any branches conditional on such a comparison can be made
2432  // unconditional. At this time, this happens too infrequently to be worth
2433  // the implementation effort, but if that ever changes, we could convert
2434  // such a pattern here.
2435  case PPC::CMPWI:
2436  case PPC::CMPLWI:
2437  case PPC::CMPDI:
2438  case PPC::CMPLDI: {
2439  // Doing this post-RA would require dataflow analysis to reliably find uses
2440  // of the CR register set by the compare.
2441  if (PostRA)
2442  return false;
2443  // If a compare-immediate is fed by an immediate and is itself an input of
2444  // an ISEL (the most common case) into a COPY of the correct register.
2445  bool Changed = false;
2446  unsigned DefReg = MI.getOperand(0).getReg();
2447  int64_t Comparand = MI.getOperand(2).getImm();
2448  int64_t SExtComparand = ((uint64_t)Comparand & ~0x7FFFuLL) != 0 ?
2449  (Comparand | 0xFFFFFFFFFFFF0000) : Comparand;
2450 
2451  for (auto &CompareUseMI : MRI->use_instructions(DefReg)) {
2452  unsigned UseOpc = CompareUseMI.getOpcode();
2453  if (UseOpc != PPC::ISEL && UseOpc != PPC::ISEL8)
2454  continue;
2455  unsigned CRSubReg = CompareUseMI.getOperand(3).getSubReg();
2456  unsigned TrueReg = CompareUseMI.getOperand(1).getReg();
2457  unsigned FalseReg = CompareUseMI.getOperand(2).getReg();
2458  unsigned RegToCopy = selectReg(SExtImm, SExtComparand, Opc, TrueReg,
2459  FalseReg, CRSubReg);
2460  if (RegToCopy == PPC::NoRegister)
2461  continue;
2462  // Can't use PPC::COPY to copy PPC::ZERO[8]. Convert it to LI[8] 0.
2463  if (RegToCopy == PPC::ZERO || RegToCopy == PPC::ZERO8) {
2464  CompareUseMI.setDesc(get(UseOpc == PPC::ISEL8 ? PPC::LI8 : PPC::LI));
2465  CompareUseMI.getOperand(1).ChangeToImmediate(0);
2466  CompareUseMI.RemoveOperand(3);
2467  CompareUseMI.RemoveOperand(2);
2468  continue;
2469  }
2470  LLVM_DEBUG(
2471  dbgs() << "Found LI -> CMPI -> ISEL, replacing with a copy.\n");
2472  LLVM_DEBUG(DefMI->dump(); MI.dump(); CompareUseMI.dump());
2473  LLVM_DEBUG(dbgs() << "Is converted to:\n");
2474  // Convert to copy and remove unneeded operands.
2475  CompareUseMI.setDesc(get(PPC::COPY));
2476  CompareUseMI.RemoveOperand(3);
2477  CompareUseMI.RemoveOperand(RegToCopy == TrueReg ? 2 : 1);
2478  CmpIselsConverted++;
2479  Changed = true;
2480  LLVM_DEBUG(CompareUseMI.dump());
2481  }
2482  if (Changed)
2483  return true;
2484  // This may end up incremented multiple times since this function is called
2485  // during a fixed-point transformation, but it is only meant to indicate the
2486  // presence of this opportunity.
2487  MissedConvertibleImmediateInstrs++;
2488  return false;
2489  }
2490 
2491  // Immediate forms - may simply be convertable to an LI.
2492  case PPC::ADDI:
2493  case PPC::ADDI8: {
2494  // Does the sum fit in a 16-bit signed field?
2495  int64_t Addend = MI.getOperand(2).getImm();
2496  if (isInt<16>(Addend + SExtImm)) {
2497  ReplaceWithLI = true;
2498  Is64BitLI = Opc == PPC::ADDI8;
2499  NewImm = Addend + SExtImm;
2500  break;
2501  }
2502  return false;
2503  }
2504  case PPC::RLDICL:
2505  case PPC::RLDICLo:
2506  case PPC::RLDICL_32:
2507  case PPC::RLDICL_32_64: {
2508  // Use APInt's rotate function.
2509  int64_t SH = MI.getOperand(2).getImm();
2510  int64_t MB = MI.getOperand(3).getImm();
2511  APInt InVal((Opc == PPC::RLDICL || Opc == PPC::RLDICLo) ?
2512  64 : 32, SExtImm, true);
2513  InVal = InVal.rotl(SH);
2514  uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
2515  InVal &= Mask;
2516  // Can't replace negative values with an LI as that will sign-extend
2517  // and not clear the left bits. If we're setting the CR bit, we will use
2518  // ANDIo which won't sign extend, so that's safe.
2519  if (isUInt<15>(InVal.getSExtValue()) ||
2520  (Opc == PPC::RLDICLo && isUInt<16>(InVal.getSExtValue()))) {
2521  ReplaceWithLI = true;
2522  Is64BitLI = Opc != PPC::RLDICL_32;
2523  NewImm = InVal.getSExtValue();
2524  SetCR = Opc == PPC::RLDICLo;
2525  break;
2526  }
2527  return false;
2528  }
2529  case PPC::RLWINM:
2530  case PPC::RLWINM8:
2531  case PPC::RLWINMo:
2532  case PPC::RLWINM8o: {
2533  int64_t SH = MI.getOperand(2).getImm();
2534  int64_t MB = MI.getOperand(3).getImm();
2535  int64_t ME = MI.getOperand(4).getImm();
2536  APInt InVal(32, SExtImm, true);
2537  InVal = InVal.rotl(SH);
2538  // Set the bits ( MB + 32 ) to ( ME + 32 ).
2539  uint64_t Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
2540  InVal &= Mask;
2541  // Can't replace negative values with an LI as that will sign-extend
2542  // and not clear the left bits. If we're setting the CR bit, we will use
2543  // ANDIo which won't sign extend, so that's safe.
2544  bool ValueFits = isUInt<15>(InVal.getSExtValue());
2545  ValueFits |= ((Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o) &&
2546  isUInt<16>(InVal.getSExtValue()));
2547  if (ValueFits) {
2548  ReplaceWithLI = true;
2549  Is64BitLI = Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
2550  NewImm = InVal.getSExtValue();
2551  SetCR = Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o;
2552  break;
2553  }
2554  return false;
2555  }
2556  case PPC::ORI:
2557  case PPC::ORI8:
2558  case PPC::XORI:
2559  case PPC::XORI8: {
2560  int64_t LogicalImm = MI.getOperand(2).getImm();
2561  int64_t Result = 0;
2562  if (Opc == PPC::ORI || Opc == PPC::ORI8)
2563  Result = LogicalImm | SExtImm;
2564  else
2565  Result = LogicalImm ^ SExtImm;
2566  if (isInt<16>(Result)) {
2567  ReplaceWithLI = true;
2568  Is64BitLI = Opc == PPC::ORI8 || Opc == PPC::XORI8;
2569  NewImm = Result;
2570  break;
2571  }
2572  return false;
2573  }
2574  }
2575 
2576  if (ReplaceWithLI) {
2577  // We need to be careful with CR-setting instructions we're replacing.
2578  if (SetCR) {
2579  // We don't know anything about uses when we're out of SSA, so only
2580  // replace if the new immediate will be reproduced.
2581  bool ImmChanged = (SExtImm & NewImm) != NewImm;
2582  if (PostRA && ImmChanged)
2583  return false;
2584 
2585  if (!PostRA) {
2586  // If the defining load-immediate has no other uses, we can just replace
2587  // the immediate with the new immediate.
2588  if (MRI->hasOneUse(DefMI->getOperand(0).getReg()))
2589  DefMI->getOperand(1).setImm(NewImm);
2590 
2591  // If we're not using the GPR result of the CR-setting instruction, we
2592  // just need to and with zero/non-zero depending on the new immediate.
2593  else if (MRI->use_empty(MI.getOperand(0).getReg())) {
2594  if (NewImm) {
2595  assert(Immediate && "Transformation converted zero to non-zero?");
2596  NewImm = Immediate;
2597  }
2598  }
2599  else if (ImmChanged)
2600  return false;
2601  }
2602  }
2603 
2604  LLVM_DEBUG(dbgs() << "Replacing instruction:\n");
2605  LLVM_DEBUG(MI.dump());
2606  LLVM_DEBUG(dbgs() << "Fed by:\n");
2607  LLVM_DEBUG(DefMI->dump());
2608  LoadImmediateInfo LII;
2609  LII.Imm = NewImm;
2610  LII.Is64Bit = Is64BitLI;
2611  LII.SetCR = SetCR;
2612  // If we're setting the CR, the original load-immediate must be kept (as an
2613  // operand to ANDIo/ANDI8o).
2614  if (KilledDef && SetCR)
2615  *KilledDef = nullptr;
2616  replaceInstrWithLI(MI, LII);
2617  LLVM_DEBUG(dbgs() << "With:\n");
2618  LLVM_DEBUG(MI.dump());
2619  return true;
2620  }
2621  return false;
2622 }
2623 
2625  ImmInstrInfo &III) const {
2626  unsigned Opc = MI.getOpcode();
2627  // The vast majority of the instructions would need their operand 2 replaced
2628  // with an immediate when switching to the reg+imm form. A marked exception
2629  // are the update form loads/stores for which a constant operand 2 would need
2630  // to turn into a displacement and move operand 1 to the operand 2 position.
2631  III.ImmOpNo = 2;
2632  III.OpNoForForwarding = 2;
2633  III.ImmWidth = 16;
2634  III.ImmMustBeMultipleOf = 1;
2635  III.TruncateImmTo = 0;
2636  III.IsSummingOperands = false;
2637  switch (Opc) {
2638  default: return false;
2639  case PPC::ADD4:
2640  case PPC::ADD8:
2641  III.SignedImm = true;
2642  III.ZeroIsSpecialOrig = 0;
2643  III.ZeroIsSpecialNew = 1;
2644  III.IsCommutative = true;
2645  III.IsSummingOperands = true;
2646  III.ImmOpcode = Opc == PPC::ADD4 ? PPC::ADDI : PPC::ADDI8;
2647  break;
2648  case PPC::ADDC:
2649  case PPC::ADDC8:
2650  III.SignedImm = true;
2651  III.ZeroIsSpecialOrig = 0;
2652  III.ZeroIsSpecialNew = 0;
2653  III.IsCommutative = true;
2654  III.IsSummingOperands = true;
2655  III.ImmOpcode = Opc == PPC::ADDC ? PPC::ADDIC : PPC::ADDIC8;
2656  break;
2657  case PPC::ADDCo:
2658  III.SignedImm = true;
2659  III.ZeroIsSpecialOrig = 0;
2660  III.ZeroIsSpecialNew = 0;
2661  III.IsCommutative = true;
2662  III.IsSummingOperands = true;
2663  III.ImmOpcode = PPC::ADDICo;
2664  break;
2665  case PPC::SUBFC:
2666  case PPC::SUBFC8:
2667  III.SignedImm = true;
2668  III.ZeroIsSpecialOrig = 0;
2669  III.ZeroIsSpecialNew = 0;
2670  III.IsCommutative = false;
2671  III.ImmOpcode = Opc == PPC::SUBFC ? PPC::SUBFIC : PPC::SUBFIC8;
2672  break;
2673  case PPC::CMPW:
2674  case PPC::CMPD:
2675  III.SignedImm = true;
2676  III.ZeroIsSpecialOrig = 0;
2677  III.ZeroIsSpecialNew = 0;
2678  III.IsCommutative = false;
2679  III.ImmOpcode = Opc == PPC::CMPW ? PPC::CMPWI : PPC::CMPDI;
2680  break;
2681  case PPC::CMPLW:
2682  case PPC::CMPLD:
2683  III.SignedImm = false;
2684  III.ZeroIsSpecialOrig = 0;
2685  III.ZeroIsSpecialNew = 0;
2686  III.IsCommutative = false;
2687  III.ImmOpcode = Opc == PPC::CMPLW ? PPC::CMPLWI : PPC::CMPLDI;
2688  break;
2689  case PPC::ANDo:
2690  case PPC::AND8o:
2691  case PPC::OR:
2692  case PPC::OR8:
2693  case PPC::XOR:
2694  case PPC::XOR8:
2695  III.SignedImm = false;
2696  III.ZeroIsSpecialOrig = 0;
2697  III.ZeroIsSpecialNew = 0;
2698  III.IsCommutative = true;
2699  switch(Opc) {
2700  default: llvm_unreachable("Unknown opcode");
2701  case PPC::ANDo: III.ImmOpcode = PPC::ANDIo; break;
2702  case PPC::AND8o: III.ImmOpcode = PPC::ANDIo8; break;
2703  case PPC::OR: III.ImmOpcode = PPC::ORI; break;
2704  case PPC::OR8: III.ImmOpcode = PPC::ORI8; break;
2705  case PPC::XOR: III.ImmOpcode = PPC::XORI; break;
2706  case PPC::XOR8: III.ImmOpcode = PPC::XORI8; break;
2707  }
2708  break;
2709  case PPC::RLWNM:
2710  case PPC::RLWNM8:
2711  case PPC::RLWNMo:
2712  case PPC::RLWNM8o:
2713  case PPC::SLW:
2714  case PPC::SLW8:
2715  case PPC::SLWo:
2716  case PPC::SLW8o:
2717  case PPC::SRW:
2718  case PPC::SRW8:
2719  case PPC::SRWo:
2720  case PPC::SRW8o:
2721  case PPC::SRAW:
2722  case PPC::SRAWo:
2723  III.SignedImm = false;
2724  III.ZeroIsSpecialOrig = 0;
2725  III.ZeroIsSpecialNew = 0;
2726  III.IsCommutative = false;
2727  // This isn't actually true, but the instructions ignore any of the
2728  // upper bits, so any immediate loaded with an LI is acceptable.
2729  // This does not apply to shift right algebraic because a value
2730  // out of range will produce a -1/0.
2731  III.ImmWidth = 16;
2732  if (Opc == PPC::RLWNM || Opc == PPC::RLWNM8 ||
2733  Opc == PPC::RLWNMo || Opc == PPC::RLWNM8o)
2734  III.TruncateImmTo = 5;
2735  else
2736  III.TruncateImmTo = 6;
2737  switch(Opc) {
2738  default: llvm_unreachable("Unknown opcode");
2739  case PPC::RLWNM: III.ImmOpcode = PPC::RLWINM; break;
2740  case PPC::RLWNM8: III.ImmOpcode = PPC::RLWINM8; break;
2741  case PPC::RLWNMo: III.ImmOpcode = PPC::RLWINMo; break;
2742  case PPC::RLWNM8o: III.ImmOpcode = PPC::RLWINM8o; break;
2743  case PPC::SLW: III.ImmOpcode = PPC::RLWINM; break;
2744  case PPC::SLW8: III.ImmOpcode = PPC::RLWINM8; break;
2745  case PPC::SLWo: III.ImmOpcode = PPC::RLWINMo; break;
2746  case PPC::SLW8o: III.ImmOpcode = PPC::RLWINM8o; break;
2747  case PPC::SRW: III.ImmOpcode = PPC::RLWINM; break;
2748  case PPC::SRW8: III.ImmOpcode = PPC::RLWINM8; break;
2749  case PPC::SRWo: III.ImmOpcode = PPC::RLWINMo; break;
2750  case PPC::SRW8o: III.ImmOpcode = PPC::RLWINM8o; break;
2751  case PPC::SRAW:
2752  III.ImmWidth = 5;
2753  III.TruncateImmTo = 0;
2754  III.ImmOpcode = PPC::SRAWI;
2755  break;
2756  case PPC::SRAWo:
2757  III.ImmWidth = 5;
2758  III.TruncateImmTo = 0;
2759  III.ImmOpcode = PPC::SRAWIo;
2760  break;
2761  }
2762  break;
2763  case PPC::RLDCL:
2764  case PPC::RLDCLo:
2765  case PPC::RLDCR:
2766  case PPC::RLDCRo:
2767  case PPC::SLD:
2768  case PPC::SLDo:
2769  case PPC::SRD:
2770  case PPC::SRDo:
2771  case PPC::SRAD:
2772  case PPC::SRADo:
2773  III.SignedImm = false;
2774  III.ZeroIsSpecialOrig = 0;
2775  III.ZeroIsSpecialNew = 0;
2776  III.IsCommutative = false;
2777  // This isn't actually true, but the instructions ignore any of the
2778  // upper bits, so any immediate loaded with an LI is acceptable.
2779  // This does not apply to shift right algebraic because a value
2780  // out of range will produce a -1/0.
2781  III.ImmWidth = 16;
2782  if (Opc == PPC::RLDCL || Opc == PPC::RLDCLo ||
2783  Opc == PPC::RLDCR || Opc == PPC::RLDCRo)
2784  III.TruncateImmTo = 6;
2785  else
2786  III.TruncateImmTo = 7;
2787  switch(Opc) {
2788  default: llvm_unreachable("Unknown opcode");
2789  case PPC::RLDCL: III.ImmOpcode = PPC::RLDICL; break;
2790  case PPC::RLDCLo: III.ImmOpcode = PPC::RLDICLo; break;
2791  case PPC::RLDCR: III.ImmOpcode = PPC::RLDICR; break;
2792  case PPC::RLDCRo: III.ImmOpcode = PPC::RLDICRo; break;
2793  case PPC::SLD: III.ImmOpcode = PPC::RLDICR; break;
2794  case PPC::SLDo: III.ImmOpcode = PPC::RLDICRo; break;
2795  case PPC::SRD: III.ImmOpcode = PPC::RLDICL; break;
2796  case PPC::SRDo: III.ImmOpcode = PPC::RLDICLo; break;
2797  case PPC::SRAD:
2798  III.ImmWidth = 6;
2799  III.TruncateImmTo = 0;
2800  III.ImmOpcode = PPC::SRADI;
2801  break;
2802  case PPC::SRADo:
2803  III.ImmWidth = 6;
2804  III.TruncateImmTo = 0;
2805  III.ImmOpcode = PPC::SRADIo;
2806  break;
2807  }
2808  break;
2809  // Loads and stores:
2810  case PPC::LBZX:
2811  case PPC::LBZX8:
2812  case PPC::LHZX:
2813  case PPC::LHZX8:
2814  case PPC::LHAX:
2815  case PPC::LHAX8:
2816  case PPC::LWZX:
2817  case PPC::LWZX8:
2818  case PPC::LWAX:
2819  case PPC::LDX:
2820  case PPC::LFSX:
2821  case PPC::LFDX:
2822  case PPC::STBX:
2823  case PPC::STBX8:
2824  case PPC::STHX:
2825  case PPC::STHX8:
2826  case PPC::STWX:
2827  case PPC::STWX8:
2828  case PPC::STDX:
2829  case PPC::STFSX:
2830  case PPC::STFDX:
2831  III.SignedImm = true;
2832  III.ZeroIsSpecialOrig = 1;
2833  III.ZeroIsSpecialNew = 2;
2834  III.IsCommutative = true;
2835  III.IsSummingOperands = true;
2836  III.ImmOpNo = 1;
2837  III.OpNoForForwarding = 2;
2838  switch(Opc) {
2839  default: llvm_unreachable("Unknown opcode");
2840  case PPC::LBZX: III.ImmOpcode = PPC::LBZ; break;
2841  case PPC::LBZX8: III.ImmOpcode = PPC::LBZ8; break;
2842  case PPC::LHZX: III.ImmOpcode = PPC::LHZ; break;
2843  case PPC::LHZX8: III.ImmOpcode = PPC::LHZ8; break;
2844  case PPC::LHAX: III.ImmOpcode = PPC::LHA; break;
2845  case PPC::LHAX8: III.ImmOpcode = PPC::LHA8; break;
2846  case PPC::LWZX: III.ImmOpcode = PPC::LWZ; break;
2847  case PPC::LWZX8: III.ImmOpcode = PPC::LWZ8; break;
2848  case PPC::LWAX:
2849  III.ImmOpcode = PPC::LWA;
2850  III.ImmMustBeMultipleOf = 4;
2851  break;
2852  case PPC::LDX: III.ImmOpcode = PPC::LD; III.ImmMustBeMultipleOf = 4; break;
2853  case PPC::LFSX: III.ImmOpcode = PPC::LFS; break;
2854  case PPC::LFDX: III.ImmOpcode = PPC::LFD; break;
2855  case PPC::STBX: III.ImmOpcode = PPC::STB; break;
2856  case PPC::STBX8: III.ImmOpcode = PPC::STB8; break;
2857  case PPC::STHX: III.ImmOpcode = PPC::STH; break;
2858  case PPC::STHX8: III.ImmOpcode = PPC::STH8; break;
2859  case PPC::STWX: III.ImmOpcode = PPC::STW; break;
2860  case PPC::STWX8: III.ImmOpcode = PPC::STW8; break;
2861  case PPC::STDX:
2862  III.ImmOpcode = PPC::STD;
2863  III.ImmMustBeMultipleOf = 4;
2864  break;
2865  case PPC::STFSX: III.ImmOpcode = PPC::STFS; break;
2866  case PPC::STFDX: III.ImmOpcode = PPC::STFD; break;
2867  }
2868  break;
2869  case PPC::LBZUX:
2870  case PPC::LBZUX8:
2871  case PPC::LHZUX:
2872  case PPC::LHZUX8:
2873  case PPC::LHAUX:
2874  case PPC::LHAUX8:
2875  case PPC::LWZUX:
2876  case PPC::LWZUX8:
2877  case PPC::LDUX:
2878  case PPC::LFSUX:
2879  case PPC::LFDUX:
2880  case PPC::STBUX:
2881  case PPC::STBUX8:
2882  case PPC::STHUX:
2883  case PPC::STHUX8:
2884  case PPC::STWUX:
2885  case PPC::STWUX8:
2886  case PPC::STDUX:
2887  case PPC::STFSUX:
2888  case PPC::STFDUX:
2889  III.SignedImm = true;
2890  III.ZeroIsSpecialOrig = 2;
2891  III.ZeroIsSpecialNew = 3;
2892  III.IsCommutative = false;
2893  III.IsSummingOperands = true;
2894  III.ImmOpNo = 2;
2895  III.OpNoForForwarding = 3;
2896  switch(Opc) {
2897  default: llvm_unreachable("Unknown opcode");
2898  case PPC::LBZUX: III.ImmOpcode = PPC::LBZU; break;
2899  case PPC::LBZUX8: III.ImmOpcode = PPC::LBZU8; break;
2900  case PPC::LHZUX: III.ImmOpcode = PPC::LHZU; break;
2901  case PPC::LHZUX8: III.ImmOpcode = PPC::LHZU8; break;
2902  case PPC::LHAUX: III.ImmOpcode = PPC::LHAU; break;
2903  case PPC::LHAUX8: III.ImmOpcode = PPC::LHAU8; break;
2904  case PPC::LWZUX: III.ImmOpcode = PPC::LWZU; break;
2905  case PPC::LWZUX8: III.ImmOpcode = PPC::LWZU8; break;
2906  case PPC::LDUX:
2907  III.ImmOpcode = PPC::LDU;
2908  III.ImmMustBeMultipleOf = 4;
2909  break;
2910  case PPC::LFSUX: III.ImmOpcode = PPC::LFSU; break;
2911  case PPC::LFDUX: III.ImmOpcode = PPC::LFDU; break;
2912  case PPC::STBUX: III.ImmOpcode = PPC::STBU; break;
2913  case PPC::STBUX8: III.ImmOpcode = PPC::STBU8; break;
2914  case PPC::STHUX: III.ImmOpcode = PPC::STHU; break;
2915  case PPC::STHUX8: III.ImmOpcode = PPC::STHU8; break;
2916  case PPC::STWUX: III.ImmOpcode = PPC::STWU; break;
2917  case PPC::STWUX8: III.ImmOpcode = PPC::STWU8; break;
2918  case PPC::STDUX:
2919  III.ImmOpcode = PPC::STDU;
2920  III.ImmMustBeMultipleOf = 4;
2921  break;
2922  case PPC::STFSUX: III.ImmOpcode = PPC::STFSU; break;
2923  case PPC::STFDUX: III.ImmOpcode = PPC::STFDU; break;
2924  }
2925  break;
2926  // Power9 only.
2927  case PPC::LXVX:
2928  case PPC::LXSSPX:
2929  case PPC::LXSDX:
2930  case PPC::STXVX:
2931  case PPC::STXSSPX:
2932  case PPC::STXSDX:
2933  if (!Subtarget.hasP9Vector())
2934  return false;
2935  III.SignedImm = true;
2936  III.ZeroIsSpecialOrig = 1;
2937  III.ZeroIsSpecialNew = 2;
2938  III.IsCommutative = true;
2939  III.IsSummingOperands = true;
2940  III.ImmOpNo = 1;
2941  III.OpNoForForwarding = 2;
2942  switch(Opc) {
2943  default: llvm_unreachable("Unknown opcode");
2944  case PPC::LXVX:
2945  III.ImmOpcode = PPC::LXV;
2946  III.ImmMustBeMultipleOf = 16;
2947  break;
2948  case PPC::LXSSPX:
2949  III.ImmOpcode = PPC::LXSSP;
2950  III.ImmMustBeMultipleOf = 4;
2951  break;
2952  case PPC::LXSDX:
2953  III.ImmOpcode = PPC::LXSD;
2954  III.ImmMustBeMultipleOf = 4;
2955  break;
2956  case PPC::STXVX:
2957  III.ImmOpcode = PPC::STXV;
2958  III.ImmMustBeMultipleOf = 16;
2959  break;
2960  case PPC::STXSSPX:
2961  III.ImmOpcode = PPC::STXSSP;
2962  III.ImmMustBeMultipleOf = 4;
2963  break;
2964  case PPC::STXSDX:
2965  III.ImmOpcode = PPC::STXSD;
2966  III.ImmMustBeMultipleOf = 4;
2967  break;
2968  }
2969  break;
2970  }
2971  return true;
2972 }
2973 
2974 // Utility function for swaping two arbitrary operands of an instruction.
2975 static void swapMIOperands(MachineInstr &MI, unsigned Op1, unsigned Op2) {
2976  assert(Op1 != Op2 && "Cannot swap operand with itself.");
2977 
2978  unsigned MaxOp = std::max(Op1, Op2);
2979  unsigned MinOp = std::min(Op1, Op2);
2980  MachineOperand MOp1 = MI.getOperand(MinOp);
2981  MachineOperand MOp2 = MI.getOperand(MaxOp);
2982  MI.RemoveOperand(std::max(Op1, Op2));
2983  MI.RemoveOperand(std::min(Op1, Op2));
2984 
2985  // If the operands we are swapping are the two at the end (the common case)
2986  // we can just remove both and add them in the opposite order.
2987  if (MaxOp - MinOp == 1 && MI.getNumOperands() == MinOp) {
2988  MI.addOperand(MOp2);
2989  MI.addOperand(MOp1);
2990  } else {
2991  // Store all operands in a temporary vector, remove them and re-add in the
2992  // right order.
2994  unsigned TotalOps = MI.getNumOperands() + 2; // We've already removed 2 ops.
2995  for (unsigned i = MI.getNumOperands() - 1; i >= MinOp; i--) {
2996  MOps.push_back(MI.getOperand(i));
2997  MI.RemoveOperand(i);
2998  }
2999  // MOp2 needs to be added next.
3000  MI.addOperand(MOp2);
3001  // Now add the rest.
3002  for (unsigned i = MI.getNumOperands(); i < TotalOps; i++) {
3003  if (i == MaxOp)
3004  MI.addOperand(MOp1);
3005  else {
3006  MI.addOperand(MOps.back());
3007  MOps.pop_back();
3008  }
3009  }
3010  }
3011 }
3012 
3013 // Check if the 'MI' that has the index OpNoForForwarding
3014 // meets the requirement described in the ImmInstrInfo.
3015 bool PPCInstrInfo::isUseMIElgibleForForwarding(MachineInstr &MI,
3016  const ImmInstrInfo &III,
3017  unsigned OpNoForForwarding
3018  ) const {
3019  // As the algorithm of checking for PPC::ZERO/PPC::ZERO8
3020  // would not work pre-RA, we can only do the check post RA.
3022  if (MRI.isSSA())
3023  return false;
3024 
3025  // Cannot do the transform if MI isn't summing the operands.
3026  if (!III.IsSummingOperands)
3027  return false;
3028 
3029  // The instruction we are trying to replace must have the ZeroIsSpecialOrig set.
3030  if (!III.ZeroIsSpecialOrig)
3031  return false;
3032 
3033  // We cannot do the transform if the operand we are trying to replace
3034  // isn't the same as the operand the instruction allows.
3035  if (OpNoForForwarding != III.OpNoForForwarding)
3036  return false;
3037 
3038  // Check if the instruction we are trying to transform really has
3039  // the special zero register as its operand.
3040  if (MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO &&
3041  MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO8)
3042  return false;
3043 
3044  // This machine instruction is convertible if it is,
3045  // 1. summing the operands.
3046  // 2. one of the operands is special zero register.
3047  // 3. the operand we are trying to replace is allowed by the MI.
3048  return true;
3049 }
3050 
3051 // Check if the DefMI is the add inst and set the ImmMO and RegMO
3052 // accordingly.
3053 bool PPCInstrInfo::isDefMIElgibleForForwarding(MachineInstr &DefMI,
3054  const ImmInstrInfo &III,
3055  MachineOperand *&ImmMO,
3056  MachineOperand *&RegMO) const {
3057  unsigned Opc = DefMI.getOpcode();
3058  if (Opc != PPC::ADDItocL && Opc != PPC::ADDI && Opc != PPC::ADDI8)
3059  return false;
3060 
3061  assert(DefMI.getNumOperands() >= 3 &&
3062  "Add inst must have at least three operands");
3063  RegMO = &DefMI.getOperand(1);
3064  ImmMO = &DefMI.getOperand(2);
3065 
3066  // This DefMI is elgible for forwarding if it is:
3067  // 1. add inst
3068  // 2. one of the operands is Imm/CPI/Global.
3069  return isAnImmediateOperand(*ImmMO);
3070 }
3071 
3072 bool PPCInstrInfo::isRegElgibleForForwarding(const MachineOperand &RegMO,
3073  const MachineInstr &DefMI,
3074  const MachineInstr &MI,
3075  bool KillDefMI
3076  ) const {
3077  // x = addi y, imm
3078  // ...
3079  // z = lfdx 0, x -> z = lfd imm(y)
3080  // The Reg "y" can be forwarded to the MI(z) only when there is no DEF
3081  // of "y" between the DEF of "x" and "z".
3082  // The query is only valid post RA.
3084  if (MRI.isSSA())
3085  return false;
3086 
3087  // MachineInstr::readsRegister only returns true if the machine
3088  // instruction reads the exact register or its super-register. It
3089  // does not consider uses of sub-registers which seems like strange
3090  // behaviour. Nonetheless, if we end up with a 64-bit register here,
3091  // get the corresponding 32-bit register to check.
3092  unsigned Reg = RegMO.getReg();
3093  if (PPC::G8RCRegClass.contains(Reg))
3094  Reg = Reg - PPC::X0 + PPC::R0;
3095 
3096  // Walking the inst in reverse(MI-->DefMI) to get the last DEF of the Reg.
3099  It++;
3100  for (; It != E; ++It) {
3101  if (It->modifiesRegister(Reg, &getRegisterInfo()) && (&*It) != &DefMI)
3102  return false;
3103  // Made it to DefMI without encountering a clobber.
3104  if ((&*It) == &DefMI)
3105  break;
3106  }
3107  assert((&*It) == &DefMI && "DefMI is missing");
3108 
3109  // If DefMI also uses the register to be forwarded, we can only forward it
3110  // if DefMI is being erased.
3111  if (DefMI.readsRegister(Reg, &getRegisterInfo()))
3112  return KillDefMI;
3113 
3114  return true;
3115 }
3116 
3117 bool PPCInstrInfo::isImmElgibleForForwarding(const MachineOperand &ImmMO,
3118  const MachineInstr &DefMI,
3119  const ImmInstrInfo &III,
3120  int64_t &Imm) const {
3121  assert(isAnImmediateOperand(ImmMO) && "ImmMO is NOT an immediate");
3122  if (DefMI.getOpcode() == PPC::ADDItocL) {
3123  // The operand for ADDItocL is CPI, which isn't imm at compiling time,
3124  // However, we know that, it is 16-bit width, and has the alignment of 4.
3125  // Check if the instruction met the requirement.
3126  if (III.ImmMustBeMultipleOf > 4 ||
3127  III.TruncateImmTo || III.ImmWidth != 16)
3128  return false;
3129 
3130  return true;
3131  }
3132 
3133  if (ImmMO.isImm()) {
3134  // It is Imm, we need to check if the Imm fit the range.
3135  int64_t Immediate = ImmMO.getImm();
3136  // Sign-extend to 64-bits.
3137  Imm = ((uint64_t)Immediate & ~0x7FFFuLL) != 0 ?
3138  (Immediate | 0xFFFFFFFFFFFF0000) : Immediate;
3139 
3140  if (Imm % III.ImmMustBeMultipleOf)
3141  return false;
3142  if (III.TruncateImmTo)
3143  Imm &= ((1 << III.TruncateImmTo) - 1);
3144  if (III.SignedImm) {
3145  APInt ActualValue(64, Imm, true);
3146  if (!ActualValue.isSignedIntN(III.ImmWidth))
3147  return false;
3148  } else {
3149  uint64_t UnsignedMax = (1 << III.ImmWidth) - 1;
3150  if ((uint64_t)Imm > UnsignedMax)
3151  return false;
3152  }
3153  }
3154  else
3155  return false;
3156 
3157  // This ImmMO is forwarded if it meets the requriement describle
3158  // in ImmInstrInfo
3159  return true;
3160 }
3161 
3162 // If an X-Form instruction is fed by an add-immediate and one of its operands
3163 // is the literal zero, attempt to forward the source of the add-immediate to
3164 // the corresponding D-Form instruction with the displacement coming from
3165 // the immediate being added.
3166 bool PPCInstrInfo::transformToImmFormFedByAdd(MachineInstr &MI,
3167  const ImmInstrInfo &III,
3168  unsigned OpNoForForwarding,
3169  MachineInstr &DefMI,
3170  bool KillDefMI) const {
3171  // RegMO ImmMO
3172  // | |
3173  // x = addi reg, imm <----- DefMI
3174  // y = op 0 , x <----- MI
3175  // |
3176  // OpNoForForwarding
3177  // Check if the MI meet the requirement described in the III.
3178  if (!isUseMIElgibleForForwarding(MI, III, OpNoForForwarding))
3179  return false;
3180 
3181  // Check if the DefMI meet the requirement
3182  // described in the III. If yes, set the ImmMO and RegMO accordingly.
3183  MachineOperand *ImmMO = nullptr;
3184  MachineOperand *RegMO = nullptr;
3185  if (!isDefMIElgibleForForwarding(DefMI, III, ImmMO, RegMO))
3186  return false;
3187  assert(ImmMO && RegMO && "Imm and Reg operand must have been set");
3188 
3189  // As we get the Imm operand now, we need to check if the ImmMO meet
3190  // the requirement described in the III. If yes set the Imm.
3191  int64_t Imm = 0;
3192  if (!isImmElgibleForForwarding(*ImmMO, DefMI, III, Imm))
3193  return false;
3194 
3195  // Check if the RegMO can be forwarded to MI.
3196  if (!isRegElgibleForForwarding(*RegMO, DefMI, MI, KillDefMI))
3197  return false;
3198 
3199  // We know that, the MI and DefMI both meet the pattern, and
3200  // the Imm also meet the requirement with the new Imm-form.
3201  // It is safe to do the transformation now.
3202  LLVM_DEBUG(dbgs() << "Replacing instruction:\n");
3203  LLVM_DEBUG(MI.dump());
3204  LLVM_DEBUG(dbgs() << "Fed by:\n");
3205  LLVM_DEBUG(DefMI.dump());
3206 
3207  // Update the base reg first.
3209  false, false,
3210  RegMO->isKill());
3211 
3212  // Then, update the imm.
3213  if (ImmMO->isImm()) {
3214  // If the ImmMO is Imm, change the operand that has ZERO to that Imm
3215  // directly.
3217  }
3218  else {
3219  // Otherwise, it is Constant Pool Index(CPI) or Global,
3220  // which is relocation in fact. We need to replace the special zero
3221  // register with ImmMO.
3222  // Before that, we need to fixup the target flags for imm.
3223  // For some reason, we miss to set the flag for the ImmMO if it is CPI.
3224  if (DefMI.getOpcode() == PPC::ADDItocL)
3226 
3227  // MI didn't have the interface such as MI.setOperand(i) though
3228  // it has MI.getOperand(i). To repalce the ZERO MachineOperand with
3229  // ImmMO, we need to remove ZERO operand and all the operands behind it,
3230  // and, add the ImmMO, then, move back all the operands behind ZERO.
3232  for (unsigned i = MI.getNumOperands() - 1; i >= III.ZeroIsSpecialOrig; i--) {
3233  MOps.push_back(MI.getOperand(i));
3234  MI.RemoveOperand(i);
3235  }
3236 
3237  // Remove the last MO in the list, which is ZERO operand in fact.
3238  MOps.pop_back();
3239  // Add the imm operand.
3240  MI.addOperand(*ImmMO);
3241  // Now add the rest back.
3242  for (auto &MO : MOps)
3243  MI.addOperand(MO);
3244  }
3245 
3246  // Update the opcode.
3247  MI.setDesc(get(III.ImmOpcode));
3248 
3249  LLVM_DEBUG(dbgs() << "With:\n");
3250  LLVM_DEBUG(MI.dump());
3251 
3252  return true;
3253 }
3254 
3255 bool PPCInstrInfo::transformToImmFormFedByLI(MachineInstr &MI,
3256  const ImmInstrInfo &III,
3257  unsigned ConstantOpNo,
3258  int64_t Imm) const {
3260  bool PostRA = !MRI.isSSA();
3261  // Exit early if we can't convert this.
3262  if ((ConstantOpNo != III.OpNoForForwarding) && !III.IsCommutative)
3263  return false;
3264  if (Imm % III.ImmMustBeMultipleOf)
3265  return false;
3266  if (III.TruncateImmTo)
3267  Imm &= ((1 << III.TruncateImmTo) - 1);
3268  if (III.SignedImm) {
3269  APInt ActualValue(64, Imm, true);
3270  if (!ActualValue.isSignedIntN(III.ImmWidth))
3271  return false;
3272  } else {
3273  uint64_t UnsignedMax = (1 << III.ImmWidth) - 1;
3274  if ((uint64_t)Imm > UnsignedMax)
3275  return false;
3276  }
3277 
3278  // If we're post-RA, the instructions don't agree on whether register zero is
3279  // special, we can transform this as long as the register operand that will
3280  // end up in the location where zero is special isn't R0.
3281  if (PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) {
3282  unsigned PosForOrigZero = III.ZeroIsSpecialOrig ? III.ZeroIsSpecialOrig :
3283  III.ZeroIsSpecialNew + 1;
3284  unsigned OrigZeroReg = MI.getOperand(PosForOrigZero).getReg();
3285  unsigned NewZeroReg = MI.getOperand(III.ZeroIsSpecialNew).getReg();
3286  // If R0 is in the operand where zero is special for the new instruction,
3287  // it is unsafe to transform if the constant operand isn't that operand.
3288  if ((NewZeroReg == PPC::R0 || NewZeroReg == PPC::X0) &&
3289  ConstantOpNo != III.ZeroIsSpecialNew)
3290  return false;
3291  if ((OrigZeroReg == PPC::R0 || OrigZeroReg == PPC::X0) &&
3292  ConstantOpNo != PosForOrigZero)
3293  return false;
3294  }
3295 
3296  unsigned Opc = MI.getOpcode();
3297  bool SpecialShift32 =
3298  Opc == PPC::SLW || Opc == PPC::SLWo || Opc == PPC::SRW || Opc == PPC::SRWo;
3299  bool SpecialShift64 =
3300  Opc == PPC::SLD || Opc == PPC::SLDo || Opc == PPC::SRD || Opc == PPC::SRDo;
3301  bool SetCR = Opc == PPC::SLWo || Opc == PPC::SRWo ||
3302  Opc == PPC::SLDo || Opc == PPC::SRDo;
3303  bool RightShift =
3304  Opc == PPC::SRW || Opc == PPC::SRWo || Opc == PPC::SRD || Opc == PPC::SRDo;
3305 
3306  MI.setDesc(get(III.ImmOpcode));
3307  if (ConstantOpNo == III.OpNoForForwarding) {
3308  // Converting shifts to immediate form is a bit tricky since they may do
3309  // one of three things:
3310  // 1. If the shift amount is between OpSize and 2*OpSize, the result is zero
3311  // 2. If the shift amount is zero, the result is unchanged (save for maybe
3312  // setting CR0)
3313  // 3. If the shift amount is in [1, OpSize), it's just a shift
3314  if (SpecialShift32 || SpecialShift64) {
3315  LoadImmediateInfo LII;
3316  LII.Imm = 0;
3317  LII.SetCR = SetCR;
3318  LII.Is64Bit = SpecialShift64;
3319  uint64_t ShAmt = Imm & (SpecialShift32 ? 0x1F : 0x3F);
3320  if (Imm & (SpecialShift32 ? 0x20 : 0x40))
3321  replaceInstrWithLI(MI, LII);
3322  // Shifts by zero don't change the value. If we don't need to set CR0,
3323  // just convert this to a COPY. Can't do this post-RA since we've already
3324  // cleaned up the copies.
3325  else if (!SetCR && ShAmt == 0 && !PostRA) {
3326  MI.RemoveOperand(2);
3327  MI.setDesc(get(PPC::COPY));
3328  } else {
3329  // The 32 bit and 64 bit instructions are quite different.
3330  if (SpecialShift32) {
3331  // Left shifts use (N, 0, 31-N), right shifts use (32-N, N, 31).
3332  uint64_t SH = RightShift ? 32 - ShAmt : ShAmt;
3333  uint64_t MB = RightShift ? ShAmt : 0;
3334  uint64_t ME = RightShift ? 31 : 31 - ShAmt;
3336  MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(MB)
3337  .addImm(ME);
3338  } else {
3339  // Left shifts use (N, 63-N), right shifts use (64-N, N).
3340  uint64_t SH = RightShift ? 64 - ShAmt : ShAmt;
3341  uint64_t ME = RightShift ? ShAmt : 63 - ShAmt;
3343  MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(ME);
3344  }
3345  }
3346  } else
3347  MI.getOperand(ConstantOpNo).ChangeToImmediate(Imm);
3348  }
3349  // Convert commutative instructions (switch the operands and convert the
3350  // desired one to an immediate.
3351  else if (III.IsCommutative) {
3352  MI.getOperand(ConstantOpNo).ChangeToImmediate(Imm);
3353  swapMIOperands(MI, ConstantOpNo, III.OpNoForForwarding);
3354  } else
3355  llvm_unreachable("Should have exited early!");
3356 
3357  // For instructions for which the constant register replaces a different
3358  // operand than where the immediate goes, we need to swap them.
3359  if (III.OpNoForForwarding != III.ImmOpNo)
3361 
3362  // If the R0/X0 register is special for the original instruction and not for
3363  // the new instruction (or vice versa), we need to fix up the register class.
3364  if (!PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) {
3365  if (!III.ZeroIsSpecialOrig) {
3366  unsigned RegToModify = MI.getOperand(III.ZeroIsSpecialNew).getReg();
3367  const TargetRegisterClass *NewRC =
3368  MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ?
3369  &PPC::GPRC_and_GPRC_NOR0RegClass : &PPC::G8RC_and_G8RC_NOX0RegClass;
3370  MRI.setRegClass(RegToModify, NewRC);
3371  }
3372  }
3373  return true;
3374 }
3375 
3376 const TargetRegisterClass *
3378  if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
3379  return &PPC::VSRCRegClass;
3380  return RC;
3381 }
3382 
3384  return PPC::getRecordFormOpcode(Opcode);
3385 }
3386 
3387 // This function returns true if the machine instruction
3388 // always outputs a value by sign-extending a 32 bit value,
3389 // i.e. 0 to 31-th bits are same as 32-th bit.
3390 static bool isSignExtendingOp(const MachineInstr &MI) {
3391  int Opcode = MI.getOpcode();
3392  if (Opcode == PPC::LI || Opcode == PPC::LI8 ||
3393  Opcode == PPC::LIS || Opcode == PPC::LIS8 ||
3394  Opcode == PPC::SRAW || Opcode == PPC::SRAWo ||
3395  Opcode == PPC::SRAWI || Opcode == PPC::SRAWIo ||
3396  Opcode == PPC::LWA || Opcode == PPC::LWAX ||
3397  Opcode == PPC::LWA_32 || Opcode == PPC::LWAX_32 ||
3398  Opcode == PPC::LHA || Opcode == PPC::LHAX ||
3399  Opcode == PPC::LHA8 || Opcode == PPC::LHAX8 ||
3400  Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
3401  Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
3402  Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
3403  Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
3404  Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
3405  Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 ||
3406  Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
3407  Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 ||
3408  Opcode == PPC::EXTSB || Opcode == PPC::EXTSBo ||
3409  Opcode == PPC::EXTSH || Opcode == PPC::EXTSHo ||
3410  Opcode == PPC::EXTSB8 || Opcode == PPC::EXTSH8 ||
3411  Opcode == PPC::EXTSW || Opcode == PPC::EXTSWo ||
3412  Opcode == PPC::EXTSH8_32_64 || Opcode == PPC::EXTSW_32_64 ||
3413  Opcode == PPC::EXTSB8_32_64)
3414  return true;
3415 
3416  if (Opcode == PPC::RLDICL && MI.getOperand(3).getImm() >= 33)
3417  return true;
3418 
3419  if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
3420  Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo) &&
3421  MI.getOperand(3).getImm() > 0 &&
3422  MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
3423  return true;
3424 
3425  return false;
3426 }
3427 
3428 // This function returns true if the machine instruction
3429 // always outputs zeros in higher 32 bits.
3430 static bool isZeroExtendingOp(const MachineInstr &MI) {
3431  int Opcode = MI.getOpcode();
3432  // The 16-bit immediate is sign-extended in li/lis.
3433  // If the most significant bit is zero, all higher bits are zero.
3434  if (Opcode == PPC::LI || Opcode == PPC::LI8 ||
3435  Opcode == PPC::LIS || Opcode == PPC::LIS8) {
3436  int64_t Imm = MI.getOperand(1).getImm();
3437  if (((uint64_t)Imm & ~0x7FFFuLL) == 0)
3438  return true;
3439  }
3440 
3441  // We have some variations of rotate-and-mask instructions
3442  // that clear higher 32-bits.
3443  if ((Opcode == PPC::RLDICL || Opcode == PPC::RLDICLo ||
3444  Opcode == PPC::RLDCL || Opcode == PPC::RLDCLo ||
3445  Opcode == PPC::RLDICL_32_64) &&
3446  MI.getOperand(3).getImm() >= 32)
3447  return true;
3448 
3449  if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDICo) &&
3450  MI.getOperand(3).getImm() >= 32 &&
3451  MI.getOperand(3).getImm() <= 63 - MI.getOperand(2).getImm())
3452  return true;
3453 
3454  if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
3455  Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo ||
3456  Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) &&
3457  MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
3458  return true;
3459 
3460  // There are other instructions that clear higher 32-bits.
3461  if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZWo ||
3462  Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZWo ||
3463  Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8 ||
3464  Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZDo ||
3465  Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZDo ||
3466  Opcode == PPC::POPCNTD || Opcode == PPC::POPCNTW ||
3467  Opcode == PPC::SLW || Opcode == PPC::SLWo ||
3468  Opcode == PPC::SRW || Opcode == PPC::SRWo ||
3469  Opcode == PPC::SLW8 || Opcode == PPC::SRW8 ||
3470  Opcode == PPC::SLWI || Opcode == PPC::SLWIo ||
3471  Opcode == PPC::SRWI || Opcode == PPC::SRWIo ||
3472  Opcode == PPC::LWZ || Opcode == PPC::LWZX ||
3473  Opcode == PPC::LWZU || Opcode == PPC::LWZUX ||
3474  Opcode == PPC::LWBRX || Opcode == PPC::LHBRX ||
3475  Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
3476  Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
3477  Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
3478  Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
3479  Opcode == PPC::LWZ8 || Opcode == PPC::LWZX8 ||
3480  Opcode == PPC::LWZU8 || Opcode == PPC::LWZUX8 ||
3481  Opcode == PPC::LWBRX8 || Opcode == PPC::LHBRX8 ||
3482  Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 ||
3483  Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 ||
3484  Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
3485  Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
3486  Opcode == PPC::ANDIo || Opcode == PPC::ANDISo ||
3487  Opcode == PPC::ROTRWI || Opcode == PPC::ROTRWIo ||
3488  Opcode == PPC::EXTLWI || Opcode == PPC::EXTLWIo ||
3489  Opcode == PPC::MFVSRWZ)
3490  return true;
3491 
3492  return false;
3493 }
3494 
3495 // This function returns true if the input MachineInstr is a TOC save
3496 // instruction.
3498  if (!MI.getOperand(1).isImm() || !MI.getOperand(2).isReg())
3499  return false;
3500  unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
3501  unsigned StackOffset = MI.getOperand(1).getImm();
3502  unsigned StackReg = MI.getOperand(2).getReg();
3503  if (StackReg == PPC::X1 && StackOffset == TOCSaveOffset)
3504  return true;
3505 
3506  return false;
3507 }
3508 
3509 // We limit the max depth to track incoming values of PHIs or binary ops
3510 // (e.g. AND) to avoid excessive cost.
3511 const unsigned MAX_DEPTH = 1;
3512 
3513 bool
3515  const unsigned Depth) const {
3516  const MachineFunction *MF = MI.getParent()->getParent();
3517  const MachineRegisterInfo *MRI = &MF->getRegInfo();
3518 
3519  // If we know this instruction returns sign- or zero-extended result,
3520  // return true.
3521  if (SignExt ? isSignExtendingOp(MI):
3522  isZeroExtendingOp(MI))
3523  return true;
3524 
3525  switch (MI.getOpcode()) {
3526  case PPC::COPY: {
3527  unsigned SrcReg = MI.getOperand(1).getReg();
3528 
3529  // In both ELFv1 and v2 ABI, method parameters and the return value
3530  // are sign- or zero-extended.
3531  if (MF->getSubtarget<PPCSubtarget>().isSVR4ABI()) {
3532  const PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
3533  // We check the ZExt/SExt flags for a method parameter.
3534  if (MI.getParent()->getBasicBlock() ==
3535  &MF->getFunction().getEntryBlock()) {
3536  unsigned VReg = MI.getOperand(0).getReg();
3537  if (MF->getRegInfo().isLiveIn(VReg))
3538  return SignExt ? FuncInfo->isLiveInSExt(VReg) :
3539  FuncInfo->isLiveInZExt(VReg);
3540  }
3541 
3542  // For a method return value, we check the ZExt/SExt flags in attribute.
3543  // We assume the following code sequence for method call.
3544  // ADJCALLSTACKDOWN 32, implicit dead %r1, implicit %r1
3545  // BL8_NOP @func,...
3546  // ADJCALLSTACKUP 32, 0, implicit dead %r1, implicit %r1
3547  // %5 = COPY %x3; G8RC:%5
3548  if (SrcReg == PPC::X3) {
3549  const MachineBasicBlock *MBB = MI.getParent();
3552  if (II != MBB->instr_begin() &&
3553  (--II)->getOpcode() == PPC::ADJCALLSTACKUP) {
3554  const MachineInstr &CallMI = *(--II);
3555  if (CallMI.isCall() && CallMI.getOperand(0).isGlobal()) {
3556  const Function *CalleeFn =
3557  dyn_cast<Function>(CallMI.getOperand(0).getGlobal());
3558  if (!CalleeFn)
3559  return false;
3560  const IntegerType *IntTy =
3561  dyn_cast<IntegerType>(CalleeFn->getReturnType());
3562  const AttributeSet &Attrs =
3563  CalleeFn->getAttributes().getRetAttributes();
3564  if (IntTy && IntTy->getBitWidth() <= 32)
3565  return Attrs.hasAttribute(SignExt ? Attribute::SExt :
3566  Attribute::ZExt);
3567  }
3568  }
3569  }
3570  }
3571 
3572  // If this is a copy from another register, we recursively check source.
3574  return false;
3575  const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3576  if (SrcMI != NULL)
3577  return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
3578 
3579  return false;
3580  }
3581 
3582  case PPC::ANDIo:
3583  case PPC::ANDISo:
3584  case PPC::ORI:
3585  case PPC::ORIS:
3586  case PPC::XORI:
3587  case PPC::XORIS:
3588  case PPC::ANDIo8:
3589  case PPC::ANDISo8:
3590  case PPC::ORI8:
3591  case PPC::ORIS8:
3592  case PPC::XORI8:
3593  case PPC::XORIS8: {
3594  // logical operation with 16-bit immediate does not change the upper bits.
3595  // So, we track the operand register as we do for register copy.
3596  unsigned SrcReg = MI.getOperand(1).getReg();
3598  return false;
3599  const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3600  if (SrcMI != NULL)
3601  return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
3602 
3603  return false;
3604  }
3605 
3606  // If all incoming values are sign-/zero-extended,
3607  // the output of OR, ISEL or PHI is also sign-/zero-extended.
3608  case PPC::OR:
3609  case PPC::OR8:
3610  case PPC::ISEL:
3611  case PPC::PHI: {
3612  if (Depth >= MAX_DEPTH)
3613  return false;
3614 
3615  // The input registers for PHI are operand 1, 3, ...
3616  // The input registers for others are operand 1 and 2.
3617  unsigned E = 3, D = 1;
3618  if (MI.getOpcode() == PPC::PHI) {
3619  E = MI.getNumOperands();
3620  D = 2;
3621  }
3622 
3623  for (unsigned I = 1; I != E; I += D) {
3624  if (MI.getOperand(I).isReg()) {
3625  unsigned SrcReg = MI.getOperand(I).getReg();
3627  return false;
3628  const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3629  if (SrcMI == NULL || !isSignOrZeroExtended(*SrcMI, SignExt, Depth+1))
3630  return false;
3631  }
3632  else
3633  return false;
3634  }
3635  return true;
3636  }
3637 
3638  // If at least one of the incoming values of an AND is zero extended
3639  // then the output is also zero-extended. If both of the incoming values
3640  // are sign-extended then the output is also sign extended.
3641  case PPC::AND:
3642  case PPC::AND8: {
3643  if (Depth >= MAX_DEPTH)
3644  return false;
3645 
3646  assert(MI.getOperand(1).isReg() && MI.getOperand(2).isReg());
3647 
3648  unsigned SrcReg1 = MI.getOperand(1).getReg();
3649  unsigned SrcReg2 = MI.getOperand(2).getReg();
3650 
3651  if (!TargetRegisterInfo::isVirtualRegister(SrcReg1) ||
3653  return false;
3654 
3655  const MachineInstr *MISrc1 = MRI->getVRegDef(SrcReg1);
3656  const MachineInstr *MISrc2 = MRI->getVRegDef(SrcReg2);
3657  if (!MISrc1 || !MISrc2)
3658  return false;
3659 
3660  if(SignExt)
3661  return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) &&
3662  isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
3663  else
3664  return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) ||
3665  isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
3666  }
3667 
3668  default:
3669  break;
3670  }
3671  return false;
3672 }
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
instr_iterator instr_begin()
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:619
int getNonRecordFormOpcode(uint16_t)
MachineBasicBlock * getMBB() const
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
uint64_t ZeroIsSpecialNew
Definition: PPCInstrInfo.h:91
void setTargetFlags(unsigned F)
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
iterator begin() const
begin/end - Return all of the registers in this class.
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:223
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:377
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:517
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:162
unsigned getReg() const
getReg - Returns the register number.
static int getRecordFormOpcode(unsigned Opcode)
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned Reg
unsigned getSubReg() const
bool hasVSX() const
Definition: PPCSubtarget.h:246
static cl::opt< bool > DisableCmpOpt("disable-ppc-cmp-opt", cl::desc("Disable compare instruction optimization"), cl::Hidden)
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
uint64_t IsCommutative
Definition: PPCInstrInfo.h:93
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
uint64_t TruncateImmTo
Definition: PPCInstrInfo.h:103
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:306
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool isPseudo() const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MCInstrDesc.h:241
CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
#define R2(n)
uint64_t OpNoForForwarding
Definition: PPCInstrInfo.h:95
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
uint64_t IsSummingOperands
Definition: PPCInstrInfo.h:105
bool instrHasImmForm(const MachineInstr &MI, ImmInstrInfo &III) const
bool isSignExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always a sign-extended, i.e.
Definition: PPCInstrInfo.h:393
return AArch64::GPR64RegClass contains(Reg)
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling th...
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineFunction & MF
Machine function.
Definition: ScheduleDAG.h:570
bool isXFormMemOp(unsigned Opcode) const
Definition: PPCInstrInfo.h:192
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
PPCDispatchGroupSBHazardRecognizer - This class implements a scoreboard-based hazard recognizer for P...
A description of a memory reference used in the backend.
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:209
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:451
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:406
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:635
AttributeSet getRetAttributes() const
The attributes for the ret value are returned.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:403
const TargetRegisterClass * updatedRC(const TargetRegisterClass *RC) const
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const override
uint64_t ZeroIsSpecialOrig
Definition: PPCInstrInfo.h:88
const char * getSymbolName() const
static bool isZeroExtendingOp(const MachineInstr &MI)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:630
static void swapMIOperands(MachineInstr &MI, unsigned Op1, unsigned Op2)
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
bool isTOCSaveMI(const MachineInstr &MI) const
defusechain_iterator - This class provides iterator support for machine operands in the function that...
PPCInstrInfo(PPCSubtarget &STI)
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1569
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:400
CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based loops.
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const override
MO_NLP_HIDDEN_FLAG - If this bit is set, the symbol reference is to a symbol with hidden visibility...
Definition: PPC.h:92
virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns) const
Return true when there is potentially a faster code sequence for an instruction chain ending in Root...
CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
Itinerary data supplied by a subtarget to be used by a target.
const PPCTargetMachine & getTargetMachine() const
Definition: PPCSubtarget.h:192
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:210
constexpr char Attrs[]
Key for Kernel::Metadata::mAttrs.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
unsigned getBitWidth() const
Get the number of bits in this IntegerType.
Definition: DerivedTypes.h:66
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
reverse_iterator rend()
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:643
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
unsigned getKillRegState(bool B)
bool hasAttribute(Attribute::AttrKind Kind) const
Return true if the attribute exists in this set.
Definition: Attributes.cpp:576
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
unsigned getDeadRegState(bool B)
VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
const BasicBlock & getEntryBlock() const
Definition: Function.h:626
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:570
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, const unsigned PhiDepth) const
Type * getReturnType() const
Returns the type of the ret val.
Definition: Function.h:155
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:539
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static unsigned selectReg(int64_t Imm1, int64_t Imm2, unsigned CompareOpc, unsigned TrueReg, unsigned FalseReg, unsigned CRSubReg)
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
unsigned const MachineRegisterInfo * MRI
bool isLiveInSExt(unsigned VReg) const
This function returns true if the specified vreg is a live-in register and sign-extended.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
int getAltVSXFMAOpcode(uint16_t Opcode)
Simple binary floating point operators.
Definition: ISDOpcodes.h:260
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void clearRegisterDeads(unsigned Reg)
Clear all dead flags on operands defining register Reg.
MachineInstrBuilder & UseMI
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
MO_NLP_FLAG - If this bit is set, the symbol reference is actually to the non_lazy_ptr for the global...
Definition: PPC.h:87
const GlobalValue * getGlobal() const
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:31
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:172
STFIWX - The STFIWX instruction.
use_instr_iterator use_instr_begin(unsigned RegNo) const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
void setImm(int64_t immVal)
bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point load which sign-extends from a 32-bit inte...
MI-level patchpoint operands.
Definition: StackMaps.h:77
Class to represent integer types.
Definition: DerivedTypes.h:40
PPCHazardRecognizer970 - This class defines a finite state automata that models the dispatch logic on...
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
unsigned getStoreOpcodeForSpill(unsigned Reg, const TargetRegisterClass *RC=nullptr) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
size_t size() const
Definition: SmallVector.h:53
auto find(R &&Range, const T &Val) -> decltype(adl_begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1051
unsigned getPredicateHint(Predicate Opcode)
Return the hint bits of the predicate.
Definition: PPCPredicates.h:83
unsigned getDarwinDirective() const
getDarwinDirective - Returns the -m directive specified for the cpu.
Definition: PPCSubtarget.h:171
static unsigned getCRFromCRBit(unsigned SrcReg)
MO_TLS - Indicates that the operand being accessed is some kind of thread-local symbol.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
unsigned first
void setIsKill(bool Val=true)
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
The next are not flags but distinct values.
Definition: PPC.h:95
The memory access writes data.
static bool MBBDefinesCTR(MachineBasicBlock &MBB)
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:186
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given stackmap should emit.
Definition: StackMaps.h:51
Predicate getPredicate(unsigned Condition, unsigned Hint)
Return predicate consisting of specified condition and hint bits.
Definition: PPCPredicates.h:88
Iterator for intrusive lists based on ilist_node.
void setOpcode(unsigned Op)
Definition: MCInst.h:173
bool isUnpredicatedTerminator(const MachineInstr &MI) const override
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
void getNoop(MCInst &NopInst) const override
Return the noop instruction to use for a noop.
static unsigned getCRBitValue(unsigned CRBit)
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:897
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:27
static cl::opt< bool > VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy", cl::desc("Causes the backend to crash instead of generating a nop VSX copy"), cl::Hidden)
static cl::opt< bool > UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden, cl::desc("Use the old (incorrect) instruction latency calculation"))
APInt rotl(unsigned rotateAmt) const
Rotate left by rotateAmt.
Definition: APInt.cpp:1002
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
int64_t getImm() const
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const Function & getFunction() const
Return the LLVM function that this machine code represents.
virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Class for arbitrary precision integers.
Definition: APInt.h:70
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
QVGPCI = This corresponds to the QPX qvgpci instruction.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
bool use_empty(unsigned RegNo) const
use_empty - Return true if there are no instructions using the specified register.
On a symbol operand, this represents the lo part.
Definition: AVRInstrInfo.h:53
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:248
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
TargetSubtargetInfo - Generic base class for all target subtargets.
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in <Root...
bool isPredicated(const MachineInstr &MI) const override
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
bool isLiveIn(unsigned Reg) const
Representation of each machine instruction.
Definition: MachineInstr.h:64
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Predicate InvertPredicate(Predicate Opcode)
Invert the specified predicate. != -> ==, < -> >=.
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:363
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
bool hasOneUse(unsigned RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MI-level stackmap operands.
Definition: StackMaps.h:36
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
TargetOptions Options
Definition: TargetMachine.h:98
static bool isSignExtendingOp(const MachineInstr &MI)
void setReg(unsigned Reg)
Change the register this operand corresponds to.
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned getLoadOpcodeForSpill(unsigned Reg, const TargetRegisterClass *RC=nullptr) const
void setSubReg(unsigned subReg)
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given patchpoint should emit.
Definition: StackMaps.h:105
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:568
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:346
bool isSignedIntN(unsigned N) const
Check if this APInt has an N-bits signed integer value.
Definition: APInt.h:456
const unsigned MAX_DEPTH
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator_range< use_instr_iterator > use_instructions(unsigned Reg) const
uint64_t ImmMustBeMultipleOf
Definition: PPCInstrInfo.h:85
unsigned getPredicateCondition(Predicate Opcode)
Return the condition without hint bits.
Definition: PPCPredicates.h:78
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
bool isLiveInZExt(unsigned VReg) const
This function returns true if the specified vreg is a live-in register and zero-extended.
LLVM Value Representation.
Definition: Value.h:73
static use_instr_iterator use_instr_end()
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:173
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when ...
IRTranslator LLVM IR MI
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:626
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
bool isPredicable(const MachineInstr &MI) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool isSVR4ABI() const
Definition: PPCSubtarget.h:310
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:67
#define LLVM_DEBUG(X)
Definition: Debug.h:123
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:408
On a symbol operand "FOO", this indicates that the reference is actually to "FOO@plt".
Definition: PPC.h:79
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: PPCInstrInfo.h:190
virtual unsigned lookThruCopyLike(unsigned SrcReg, const MachineRegisterInfo *MRI) const
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:308
static cl::opt< bool > DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden, cl::desc("Disable analysis for CTR loops"))
Instructions::const_iterator const_instr_iterator
GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point load which zero-extends from a 32-bit inte...
SpillOpcodeKey
MO_PIC_FLAG - If this bit is set, the symbol reference is relative to the function&#39;s picbase...
Definition: PPC.h:83
bool convertToImmediateForm(MachineInstr &MI, MachineInstr **KilledDef=nullptr) const
static bool isAnImmediateOperand(const MachineOperand &MO)
bool expandPostRAPseudo(MachineInstr &MI) const override
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:144
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:171
bool expandVSXMemPseudo(MachineInstr &MI) const
bool isImplicit() const
bool isZeroExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always zero-extended, i.e.
Definition: PPCInstrInfo.h:399
Predicate getSwappedPredicate(Predicate Opcode)
Assume the condition register is set by MI(a,b), return the predicate if we modify the instructions s...