LLVM  9.0.0svn
PPCInstrInfo.cpp
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1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the PowerPC implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "PPCInstrInfo.h"
15 #include "PPC.h"
16 #include "PPCHazardRecognizers.h"
17 #include "PPCInstrBuilder.h"
18 #include "PPCMachineFunctionInfo.h"
19 #include "PPCTargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Statistic.h"
31 #include "llvm/CodeGen/StackMaps.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/MC/MCInst.h"
35 #include "llvm/Support/Debug.h"
39 
40 using namespace llvm;
41 
42 #define DEBUG_TYPE "ppc-instr-info"
43 
44 #define GET_INSTRMAP_INFO
45 #define GET_INSTRINFO_CTOR_DTOR
46 #include "PPCGenInstrInfo.inc"
47 
48 STATISTIC(NumStoreSPILLVSRRCAsVec,
49  "Number of spillvsrrc spilled to stack as vec");
50 STATISTIC(NumStoreSPILLVSRRCAsGpr,
51  "Number of spillvsrrc spilled to stack as gpr");
52 STATISTIC(NumGPRtoVSRSpill, "Number of gpr spills to spillvsrrc");
53 STATISTIC(CmpIselsConverted,
54  "Number of ISELs that depend on comparison of constants converted");
55 STATISTIC(MissedConvertibleImmediateInstrs,
56  "Number of compare-immediate instructions fed by constants");
57 STATISTIC(NumRcRotatesConvertedToRcAnd,
58  "Number of record-form rotates converted to record-form andi");
59 
60 static cl::
61 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
62  cl::desc("Disable analysis for CTR loops"));
63 
64 static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
65 cl::desc("Disable compare instruction optimization"), cl::Hidden);
66 
67 static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
68 cl::desc("Causes the backend to crash instead of generating a nop VSX copy"),
69 cl::Hidden);
70 
71 static cl::opt<bool>
72 UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
73  cl::desc("Use the old (incorrect) instruction latency calculation"));
74 
75 // Index into the OpcodesForSpill array.
94  SOK_LastOpcodeSpill // This must be last on the enum.
95 };
96 
97 // Pin the vtable to this file.
98 void PPCInstrInfo::anchor() {}
99 
101  : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP,
102  /* CatchRetOpcode */ -1,
103  STI.isPPC64() ? PPC::BLR8 : PPC::BLR),
104  Subtarget(STI), RI(STI.getTargetMachine()) {}
105 
106 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
107 /// this target when scheduling the DAG.
110  const ScheduleDAG *DAG) const {
111  unsigned Directive =
112  static_cast<const PPCSubtarget *>(STI)->getDarwinDirective();
113  if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
114  Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
115  const InstrItineraryData *II =
116  static_cast<const PPCSubtarget *>(STI)->getInstrItineraryData();
117  return new ScoreboardHazardRecognizer(II, DAG);
118  }
119 
121 }
122 
123 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
124 /// to use for this target when scheduling the DAG.
127  const ScheduleDAG *DAG) const {
128  unsigned Directive =
129  DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
130 
131  // FIXME: Leaving this as-is until we have POWER9 scheduling info
132  if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8)
133  return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
134 
135  // Most subtargets use a PPC970 recognizer.
136  if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
137  Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
138  assert(DAG->TII && "No InstrInfo?");
139 
140  return new PPCHazardRecognizer970(*DAG);
141  }
142 
143  return new ScoreboardHazardRecognizer(II, DAG);
144 }
145 
147  const MachineInstr &MI,
148  unsigned *PredCost) const {
149  if (!ItinData || UseOldLatencyCalc)
150  return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
151 
152  // The default implementation of getInstrLatency calls getStageLatency, but
153  // getStageLatency does not do the right thing for us. While we have
154  // itinerary, most cores are fully pipelined, and so the itineraries only
155  // express the first part of the pipeline, not every stage. Instead, we need
156  // to use the listed output operand cycle number (using operand 0 here, which
157  // is an output).
158 
159  unsigned Latency = 1;
160  unsigned DefClass = MI.getDesc().getSchedClass();
161  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
162  const MachineOperand &MO = MI.getOperand(i);
163  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
164  continue;
165 
166  int Cycle = ItinData->getOperandCycle(DefClass, i);
167  if (Cycle < 0)
168  continue;
169 
170  Latency = std::max(Latency, (unsigned) Cycle);
171  }
172 
173  return Latency;
174 }
175 
177  const MachineInstr &DefMI, unsigned DefIdx,
178  const MachineInstr &UseMI,
179  unsigned UseIdx) const {
180  int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
181  UseMI, UseIdx);
182 
183  if (!DefMI.getParent())
184  return Latency;
185 
186  const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
187  unsigned Reg = DefMO.getReg();
188 
189  bool IsRegCR;
191  const MachineRegisterInfo *MRI =
192  &DefMI.getParent()->getParent()->getRegInfo();
193  IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
194  MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
195  } else {
196  IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
197  PPC::CRBITRCRegClass.contains(Reg);
198  }
199 
200  if (UseMI.isBranch() && IsRegCR) {
201  if (Latency < 0)
202  Latency = getInstrLatency(ItinData, DefMI);
203 
204  // On some cores, there is an additional delay between writing to a condition
205  // register, and using it from a branch.
206  unsigned Directive = Subtarget.getDarwinDirective();
207  switch (Directive) {
208  default: break;
209  case PPC::DIR_7400:
210  case PPC::DIR_750:
211  case PPC::DIR_970:
212  case PPC::DIR_E5500:
213  case PPC::DIR_PWR4:
214  case PPC::DIR_PWR5:
215  case PPC::DIR_PWR5X:
216  case PPC::DIR_PWR6:
217  case PPC::DIR_PWR6X:
218  case PPC::DIR_PWR7:
219  case PPC::DIR_PWR8:
220  // FIXME: Is this needed for POWER9?
221  Latency += 2;
222  break;
223  }
224  }
225 
226  return Latency;
227 }
228 
229 // This function does not list all associative and commutative operations, but
230 // only those worth feeding through the machine combiner in an attempt to
231 // reduce the critical path. Mostly, this means floating-point operations,
232 // because they have high latencies (compared to other operations, such and
233 // and/or, which are also associative and commutative, but have low latencies).
235  switch (Inst.getOpcode()) {
236  // FP Add:
237  case PPC::FADD:
238  case PPC::FADDS:
239  // FP Multiply:
240  case PPC::FMUL:
241  case PPC::FMULS:
242  // Altivec Add:
243  case PPC::VADDFP:
244  // VSX Add:
245  case PPC::XSADDDP:
246  case PPC::XVADDDP:
247  case PPC::XVADDSP:
248  case PPC::XSADDSP:
249  // VSX Multiply:
250  case PPC::XSMULDP:
251  case PPC::XVMULDP:
252  case PPC::XVMULSP:
253  case PPC::XSMULSP:
254  // QPX Add:
255  case PPC::QVFADD:
256  case PPC::QVFADDS:
257  case PPC::QVFADDSs:
258  // QPX Multiply:
259  case PPC::QVFMUL:
260  case PPC::QVFMULS:
261  case PPC::QVFMULSs:
262  return true;
263  default:
264  return false;
265  }
266 }
267 
269  MachineInstr &Root,
270  SmallVectorImpl<MachineCombinerPattern> &Patterns) const {
271  // Using the machine combiner in this way is potentially expensive, so
272  // restrict to when aggressive optimizations are desired.
274  return false;
275 
276  // FP reassociation is only legal when we don't need strict IEEE semantics.
278  return false;
279 
280  return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns);
281 }
282 
283 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
285  unsigned &SrcReg, unsigned &DstReg,
286  unsigned &SubIdx) const {
287  switch (MI.getOpcode()) {
288  default: return false;
289  case PPC::EXTSW:
290  case PPC::EXTSW_32:
291  case PPC::EXTSW_32_64:
292  SrcReg = MI.getOperand(1).getReg();
293  DstReg = MI.getOperand(0).getReg();
294  SubIdx = PPC::sub_32;
295  return true;
296  }
297 }
298 
300  int &FrameIndex) const {
301  unsigned Opcode = MI.getOpcode();
302  const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
303  const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill;
304 
305  if (End != std::find(OpcodesForSpill, End, Opcode)) {
306  // Check for the operands added by addFrameReference (the immediate is the
307  // offset which defaults to 0).
308  if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
309  MI.getOperand(2).isFI()) {
310  FrameIndex = MI.getOperand(2).getIndex();
311  return MI.getOperand(0).getReg();
312  }
313  }
314  return 0;
315 }
316 
317 // For opcodes with the ReMaterializable flag set, this function is called to
318 // verify the instruction is really rematable.
320  AliasAnalysis *AA) const {
321  switch (MI.getOpcode()) {
322  default:
323  // This function should only be called for opcodes with the ReMaterializable
324  // flag set.
325  llvm_unreachable("Unknown rematerializable operation!");
326  break;
327  case PPC::LI:
328  case PPC::LI8:
329  case PPC::LIS:
330  case PPC::LIS8:
331  case PPC::QVGPCI:
332  case PPC::ADDIStocHA:
333  case PPC::ADDItocL:
334  case PPC::LOAD_STACK_GUARD:
335  return true;
336  }
337  return false;
338 }
339 
341  int &FrameIndex) const {
342  unsigned Opcode = MI.getOpcode();
343  const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
344  const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill;
345 
346  if (End != std::find(OpcodesForSpill, End, Opcode)) {
347  if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
348  MI.getOperand(2).isFI()) {
349  FrameIndex = MI.getOperand(2).getIndex();
350  return MI.getOperand(0).getReg();
351  }
352  }
353  return 0;
354 }
355 
357  unsigned OpIdx1,
358  unsigned OpIdx2) const {
359  MachineFunction &MF = *MI.getParent()->getParent();
360 
361  // Normal instructions can be commuted the obvious way.
362  if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMIo)
363  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
364  // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
365  // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
366  // changing the relative order of the mask operands might change what happens
367  // to the high-bits of the mask (and, thus, the result).
368 
369  // Cannot commute if it has a non-zero rotate count.
370  if (MI.getOperand(3).getImm() != 0)
371  return nullptr;
372 
373  // If we have a zero rotate count, we have:
374  // M = mask(MB,ME)
375  // Op0 = (Op1 & ~M) | (Op2 & M)
376  // Change this to:
377  // M = mask((ME+1)&31, (MB-1)&31)
378  // Op0 = (Op2 & ~M) | (Op1 & M)
379 
380  // Swap op1/op2
381  assert(((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) &&
382  "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo.");
383  unsigned Reg0 = MI.getOperand(0).getReg();
384  unsigned Reg1 = MI.getOperand(1).getReg();
385  unsigned Reg2 = MI.getOperand(2).getReg();
386  unsigned SubReg1 = MI.getOperand(1).getSubReg();
387  unsigned SubReg2 = MI.getOperand(2).getSubReg();
388  bool Reg1IsKill = MI.getOperand(1).isKill();
389  bool Reg2IsKill = MI.getOperand(2).isKill();
390  bool ChangeReg0 = false;
391  // If machine instrs are no longer in two-address forms, update
392  // destination register as well.
393  if (Reg0 == Reg1) {
394  // Must be two address instruction!
396  "Expecting a two-address instruction!");
397  assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
398  Reg2IsKill = false;
399  ChangeReg0 = true;
400  }
401 
402  // Masks.
403  unsigned MB = MI.getOperand(4).getImm();
404  unsigned ME = MI.getOperand(5).getImm();
405 
406  // We can't commute a trivial mask (there is no way to represent an all-zero
407  // mask).
408  if (MB == 0 && ME == 31)
409  return nullptr;
410 
411  if (NewMI) {
412  // Create a new instruction.
413  unsigned Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg();
414  bool Reg0IsDead = MI.getOperand(0).isDead();
415  return BuildMI(MF, MI.getDebugLoc(), MI.getDesc())
416  .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
417  .addReg(Reg2, getKillRegState(Reg2IsKill))
418  .addReg(Reg1, getKillRegState(Reg1IsKill))
419  .addImm((ME + 1) & 31)
420  .addImm((MB - 1) & 31);
421  }
422 
423  if (ChangeReg0) {
424  MI.getOperand(0).setReg(Reg2);
425  MI.getOperand(0).setSubReg(SubReg2);
426  }
427  MI.getOperand(2).setReg(Reg1);
428  MI.getOperand(1).setReg(Reg2);
429  MI.getOperand(2).setSubReg(SubReg1);
430  MI.getOperand(1).setSubReg(SubReg2);
431  MI.getOperand(2).setIsKill(Reg1IsKill);
432  MI.getOperand(1).setIsKill(Reg2IsKill);
433 
434  // Swap the mask around.
435  MI.getOperand(4).setImm((ME + 1) & 31);
436  MI.getOperand(5).setImm((MB - 1) & 31);
437  return &MI;
438 }
439 
441  unsigned &SrcOpIdx2) const {
442  // For VSX A-Type FMA instructions, it is the first two operands that can be
443  // commuted, however, because the non-encoded tied input operand is listed
444  // first, the operands to swap are actually the second and third.
445 
446  int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode());
447  if (AltOpc == -1)
448  return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
449 
450  // The commutable operand indices are 2 and 3. Return them in SrcOpIdx1
451  // and SrcOpIdx2.
452  return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
453 }
454 
457  // This function is used for scheduling, and the nop wanted here is the type
458  // that terminates dispatch groups on the POWER cores.
459  unsigned Directive = Subtarget.getDarwinDirective();
460  unsigned Opcode;
461  switch (Directive) {
462  default: Opcode = PPC::NOP; break;
463  case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
464  case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
465  case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */
466  // FIXME: Update when POWER9 scheduling model is ready.
467  case PPC::DIR_PWR9: Opcode = PPC::NOP_GT_PWR7; break;
468  }
469 
470  DebugLoc DL;
471  BuildMI(MBB, MI, DL, get(Opcode));
472 }
473 
474 /// Return the noop instruction to use for a noop.
475 void PPCInstrInfo::getNoop(MCInst &NopInst) const {
476  NopInst.setOpcode(PPC::NOP);
477 }
478 
479 // Branch analysis.
480 // Note: If the condition register is set to CTR or CTR8 then this is a
481 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
483  MachineBasicBlock *&TBB,
484  MachineBasicBlock *&FBB,
486  bool AllowModify) const {
487  bool isPPC64 = Subtarget.isPPC64();
488 
489  // If the block has no terminators, it just falls into the block after it.
491  if (I == MBB.end())
492  return false;
493 
494  if (!isUnpredicatedTerminator(*I))
495  return false;
496 
497  if (AllowModify) {
498  // If the BB ends with an unconditional branch to the fallthrough BB,
499  // we eliminate the branch instruction.
500  if (I->getOpcode() == PPC::B &&
501  MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
502  I->eraseFromParent();
503 
504  // We update iterator after deleting the last branch.
505  I = MBB.getLastNonDebugInstr();
506  if (I == MBB.end() || !isUnpredicatedTerminator(*I))
507  return false;
508  }
509  }
510 
511  // Get the last instruction in the block.
512  MachineInstr &LastInst = *I;
513 
514  // If there is only one terminator instruction, process it.
515  if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
516  if (LastInst.getOpcode() == PPC::B) {
517  if (!LastInst.getOperand(0).isMBB())
518  return true;
519  TBB = LastInst.getOperand(0).getMBB();
520  return false;
521  } else if (LastInst.getOpcode() == PPC::BCC) {
522  if (!LastInst.getOperand(2).isMBB())
523  return true;
524  // Block ends with fall-through condbranch.
525  TBB = LastInst.getOperand(2).getMBB();
526  Cond.push_back(LastInst.getOperand(0));
527  Cond.push_back(LastInst.getOperand(1));
528  return false;
529  } else if (LastInst.getOpcode() == PPC::BC) {
530  if (!LastInst.getOperand(1).isMBB())
531  return true;
532  // Block ends with fall-through condbranch.
533  TBB = LastInst.getOperand(1).getMBB();
535  Cond.push_back(LastInst.getOperand(0));
536  return false;
537  } else if (LastInst.getOpcode() == PPC::BCn) {
538  if (!LastInst.getOperand(1).isMBB())
539  return true;
540  // Block ends with fall-through condbranch.
541  TBB = LastInst.getOperand(1).getMBB();
543  Cond.push_back(LastInst.getOperand(0));
544  return false;
545  } else if (LastInst.getOpcode() == PPC::BDNZ8 ||
546  LastInst.getOpcode() == PPC::BDNZ) {
547  if (!LastInst.getOperand(0).isMBB())
548  return true;
549  if (DisableCTRLoopAnal)
550  return true;
551  TBB = LastInst.getOperand(0).getMBB();
553  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
554  true));
555  return false;
556  } else if (LastInst.getOpcode() == PPC::BDZ8 ||
557  LastInst.getOpcode() == PPC::BDZ) {
558  if (!LastInst.getOperand(0).isMBB())
559  return true;
560  if (DisableCTRLoopAnal)
561  return true;
562  TBB = LastInst.getOperand(0).getMBB();
564  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
565  true));
566  return false;
567  }
568 
569  // Otherwise, don't know what this is.
570  return true;
571  }
572 
573  // Get the instruction before it if it's a terminator.
574  MachineInstr &SecondLastInst = *I;
575 
576  // If there are three terminators, we don't know what sort of block this is.
577  if (I != MBB.begin() && isUnpredicatedTerminator(*--I))
578  return true;
579 
580  // If the block ends with PPC::B and PPC:BCC, handle it.
581  if (SecondLastInst.getOpcode() == PPC::BCC &&
582  LastInst.getOpcode() == PPC::B) {
583  if (!SecondLastInst.getOperand(2).isMBB() ||
584  !LastInst.getOperand(0).isMBB())
585  return true;
586  TBB = SecondLastInst.getOperand(2).getMBB();
587  Cond.push_back(SecondLastInst.getOperand(0));
588  Cond.push_back(SecondLastInst.getOperand(1));
589  FBB = LastInst.getOperand(0).getMBB();
590  return false;
591  } else if (SecondLastInst.getOpcode() == PPC::BC &&
592  LastInst.getOpcode() == PPC::B) {
593  if (!SecondLastInst.getOperand(1).isMBB() ||
594  !LastInst.getOperand(0).isMBB())
595  return true;
596  TBB = SecondLastInst.getOperand(1).getMBB();
598  Cond.push_back(SecondLastInst.getOperand(0));
599  FBB = LastInst.getOperand(0).getMBB();
600  return false;
601  } else if (SecondLastInst.getOpcode() == PPC::BCn &&
602  LastInst.getOpcode() == PPC::B) {
603  if (!SecondLastInst.getOperand(1).isMBB() ||
604  !LastInst.getOperand(0).isMBB())
605  return true;
606  TBB = SecondLastInst.getOperand(1).getMBB();
608  Cond.push_back(SecondLastInst.getOperand(0));
609  FBB = LastInst.getOperand(0).getMBB();
610  return false;
611  } else if ((SecondLastInst.getOpcode() == PPC::BDNZ8 ||
612  SecondLastInst.getOpcode() == PPC::BDNZ) &&
613  LastInst.getOpcode() == PPC::B) {
614  if (!SecondLastInst.getOperand(0).isMBB() ||
615  !LastInst.getOperand(0).isMBB())
616  return true;
617  if (DisableCTRLoopAnal)
618  return true;
619  TBB = SecondLastInst.getOperand(0).getMBB();
621  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
622  true));
623  FBB = LastInst.getOperand(0).getMBB();
624  return false;
625  } else if ((SecondLastInst.getOpcode() == PPC::BDZ8 ||
626  SecondLastInst.getOpcode() == PPC::BDZ) &&
627  LastInst.getOpcode() == PPC::B) {
628  if (!SecondLastInst.getOperand(0).isMBB() ||
629  !LastInst.getOperand(0).isMBB())
630  return true;
631  if (DisableCTRLoopAnal)
632  return true;
633  TBB = SecondLastInst.getOperand(0).getMBB();
635  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
636  true));
637  FBB = LastInst.getOperand(0).getMBB();
638  return false;
639  }
640 
641  // If the block ends with two PPC:Bs, handle it. The second one is not
642  // executed, so remove it.
643  if (SecondLastInst.getOpcode() == PPC::B && LastInst.getOpcode() == PPC::B) {
644  if (!SecondLastInst.getOperand(0).isMBB())
645  return true;
646  TBB = SecondLastInst.getOperand(0).getMBB();
647  I = LastInst;
648  if (AllowModify)
649  I->eraseFromParent();
650  return false;
651  }
652 
653  // Otherwise, can't handle this.
654  return true;
655 }
656 
658  int *BytesRemoved) const {
659  assert(!BytesRemoved && "code size not handled");
660 
662  if (I == MBB.end())
663  return 0;
664 
665  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
666  I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
667  I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
668  I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
669  return 0;
670 
671  // Remove the branch.
672  I->eraseFromParent();
673 
674  I = MBB.end();
675 
676  if (I == MBB.begin()) return 1;
677  --I;
678  if (I->getOpcode() != PPC::BCC &&
679  I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
680  I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
681  I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
682  return 1;
683 
684  // Remove the branch.
685  I->eraseFromParent();
686  return 2;
687 }
688 
690  MachineBasicBlock *TBB,
691  MachineBasicBlock *FBB,
693  const DebugLoc &DL,
694  int *BytesAdded) const {
695  // Shouldn't be a fall through.
696  assert(TBB && "insertBranch must not be told to insert a fallthrough");
697  assert((Cond.size() == 2 || Cond.size() == 0) &&
698  "PPC branch conditions have two components!");
699  assert(!BytesAdded && "code size not handled");
700 
701  bool isPPC64 = Subtarget.isPPC64();
702 
703  // One-way branch.
704  if (!FBB) {
705  if (Cond.empty()) // Unconditional branch
706  BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
707  else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
708  BuildMI(&MBB, DL, get(Cond[0].getImm() ?
709  (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
710  (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
711  else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
712  BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
713  else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
714  BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
715  else // Conditional branch
716  BuildMI(&MBB, DL, get(PPC::BCC))
717  .addImm(Cond[0].getImm())
718  .add(Cond[1])
719  .addMBB(TBB);
720  return 1;
721  }
722 
723  // Two-way Conditional Branch.
724  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
725  BuildMI(&MBB, DL, get(Cond[0].getImm() ?
726  (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
727  (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
728  else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
729  BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
730  else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
731  BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
732  else
733  BuildMI(&MBB, DL, get(PPC::BCC))
734  .addImm(Cond[0].getImm())
735  .add(Cond[1])
736  .addMBB(TBB);
737  BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
738  return 2;
739 }
740 
741 // Select analysis.
744  unsigned TrueReg, unsigned FalseReg,
745  int &CondCycles, int &TrueCycles, int &FalseCycles) const {
746  if (Cond.size() != 2)
747  return false;
748 
749  // If this is really a bdnz-like condition, then it cannot be turned into a
750  // select.
751  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
752  return false;
753 
754  // Check register classes.
755  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
756  const TargetRegisterClass *RC =
757  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
758  if (!RC)
759  return false;
760 
761  // isel is for regular integer GPRs only.
762  if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
763  !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
764  !PPC::G8RCRegClass.hasSubClassEq(RC) &&
765  !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
766  return false;
767 
768  // FIXME: These numbers are for the A2, how well they work for other cores is
769  // an open question. On the A2, the isel instruction has a 2-cycle latency
770  // but single-cycle throughput. These numbers are used in combination with
771  // the MispredictPenalty setting from the active SchedMachineModel.
772  CondCycles = 1;
773  TrueCycles = 1;
774  FalseCycles = 1;
775 
776  return true;
777 }
778 
781  const DebugLoc &dl, unsigned DestReg,
782  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
783  unsigned FalseReg) const {
784  assert(Cond.size() == 2 &&
785  "PPC branch conditions have two components!");
786 
787  // Get the register classes.
789  const TargetRegisterClass *RC =
790  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
791  assert(RC && "TrueReg and FalseReg must have overlapping register classes");
792 
793  bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
794  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
795  assert((Is64Bit ||
796  PPC::GPRCRegClass.hasSubClassEq(RC) ||
797  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
798  "isel is for regular integer GPRs only");
799 
800  unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
801  auto SelectPred = static_cast<PPC::Predicate>(Cond[0].getImm());
802 
803  unsigned SubIdx = 0;
804  bool SwapOps = false;
805  switch (SelectPred) {
806  case PPC::PRED_EQ:
807  case PPC::PRED_EQ_MINUS:
808  case PPC::PRED_EQ_PLUS:
809  SubIdx = PPC::sub_eq; SwapOps = false; break;
810  case PPC::PRED_NE:
811  case PPC::PRED_NE_MINUS:
812  case PPC::PRED_NE_PLUS:
813  SubIdx = PPC::sub_eq; SwapOps = true; break;
814  case PPC::PRED_LT:
815  case PPC::PRED_LT_MINUS:
816  case PPC::PRED_LT_PLUS:
817  SubIdx = PPC::sub_lt; SwapOps = false; break;
818  case PPC::PRED_GE:
819  case PPC::PRED_GE_MINUS:
820  case PPC::PRED_GE_PLUS:
821  SubIdx = PPC::sub_lt; SwapOps = true; break;
822  case PPC::PRED_GT:
823  case PPC::PRED_GT_MINUS:
824  case PPC::PRED_GT_PLUS:
825  SubIdx = PPC::sub_gt; SwapOps = false; break;
826  case PPC::PRED_LE:
827  case PPC::PRED_LE_MINUS:
828  case PPC::PRED_LE_PLUS:
829  SubIdx = PPC::sub_gt; SwapOps = true; break;
830  case PPC::PRED_UN:
831  case PPC::PRED_UN_MINUS:
832  case PPC::PRED_UN_PLUS:
833  SubIdx = PPC::sub_un; SwapOps = false; break;
834  case PPC::PRED_NU:
835  case PPC::PRED_NU_MINUS:
836  case PPC::PRED_NU_PLUS:
837  SubIdx = PPC::sub_un; SwapOps = true; break;
838  case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break;
839  case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break;
840  }
841 
842  unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
843  SecondReg = SwapOps ? TrueReg : FalseReg;
844 
845  // The first input register of isel cannot be r0. If it is a member
846  // of a register class that can be r0, then copy it first (the
847  // register allocator should eliminate the copy).
848  if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
849  MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
850  const TargetRegisterClass *FirstRC =
851  MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
852  &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
853  unsigned OldFirstReg = FirstReg;
854  FirstReg = MRI.createVirtualRegister(FirstRC);
855  BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
856  .addReg(OldFirstReg);
857  }
858 
859  BuildMI(MBB, MI, dl, get(OpCode), DestReg)
860  .addReg(FirstReg).addReg(SecondReg)
861  .addReg(Cond[1].getReg(), 0, SubIdx);
862 }
863 
864 static unsigned getCRBitValue(unsigned CRBit) {
865  unsigned Ret = 4;
866  if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT ||
867  CRBit == PPC::CR2LT || CRBit == PPC::CR3LT ||
868  CRBit == PPC::CR4LT || CRBit == PPC::CR5LT ||
869  CRBit == PPC::CR6LT || CRBit == PPC::CR7LT)
870  Ret = 3;
871  if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT ||
872  CRBit == PPC::CR2GT || CRBit == PPC::CR3GT ||
873  CRBit == PPC::CR4GT || CRBit == PPC::CR5GT ||
874  CRBit == PPC::CR6GT || CRBit == PPC::CR7GT)
875  Ret = 2;
876  if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ ||
877  CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ ||
878  CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ ||
879  CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ)
880  Ret = 1;
881  if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN ||
882  CRBit == PPC::CR2UN || CRBit == PPC::CR3UN ||
883  CRBit == PPC::CR4UN || CRBit == PPC::CR5UN ||
884  CRBit == PPC::CR6UN || CRBit == PPC::CR7UN)
885  Ret = 0;
886 
887  assert(Ret != 4 && "Invalid CR bit register");
888  return Ret;
889 }
890 
893  const DebugLoc &DL, unsigned DestReg,
894  unsigned SrcReg, bool KillSrc) const {
895  // We can end up with self copies and similar things as a result of VSX copy
896  // legalization. Promote them here.
898  if (PPC::F8RCRegClass.contains(DestReg) &&
899  PPC::VSRCRegClass.contains(SrcReg)) {
900  unsigned SuperReg =
901  TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
902 
903  if (VSXSelfCopyCrash && SrcReg == SuperReg)
904  llvm_unreachable("nop VSX copy");
905 
906  DestReg = SuperReg;
907  } else if (PPC::F8RCRegClass.contains(SrcReg) &&
908  PPC::VSRCRegClass.contains(DestReg)) {
909  unsigned SuperReg =
910  TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
911 
912  if (VSXSelfCopyCrash && DestReg == SuperReg)
913  llvm_unreachable("nop VSX copy");
914 
915  SrcReg = SuperReg;
916  }
917 
918  // Different class register copy
919  if (PPC::CRBITRCRegClass.contains(SrcReg) &&
920  PPC::GPRCRegClass.contains(DestReg)) {
921  unsigned CRReg = getCRFromCRBit(SrcReg);
922  BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg);
923  getKillRegState(KillSrc);
924  // Rotate the CR bit in the CR fields to be the least significant bit and
925  // then mask with 0x1 (MB = ME = 31).
926  BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
927  .addReg(DestReg, RegState::Kill)
928  .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
929  .addImm(31)
930  .addImm(31);
931  return;
932  } else if (PPC::CRRCRegClass.contains(SrcReg) &&
933  PPC::G8RCRegClass.contains(DestReg)) {
934  BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg).addReg(SrcReg);
935  getKillRegState(KillSrc);
936  return;
937  } else if (PPC::CRRCRegClass.contains(SrcReg) &&
938  PPC::GPRCRegClass.contains(DestReg)) {
939  BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(SrcReg);
940  getKillRegState(KillSrc);
941  return;
942  } else if (PPC::G8RCRegClass.contains(SrcReg) &&
943  PPC::VSFRCRegClass.contains(DestReg)) {
944  BuildMI(MBB, I, DL, get(PPC::MTVSRD), DestReg).addReg(SrcReg);
945  NumGPRtoVSRSpill++;
946  getKillRegState(KillSrc);
947  return;
948  } else if (PPC::VSFRCRegClass.contains(SrcReg) &&
949  PPC::G8RCRegClass.contains(DestReg)) {
950  BuildMI(MBB, I, DL, get(PPC::MFVSRD), DestReg).addReg(SrcReg);
951  getKillRegState(KillSrc);
952  return;
953  } else if (PPC::SPERCRegClass.contains(SrcReg) &&
954  PPC::SPE4RCRegClass.contains(DestReg)) {
955  BuildMI(MBB, I, DL, get(PPC::EFSCFD), DestReg).addReg(SrcReg);
956  getKillRegState(KillSrc);
957  return;
958  } else if (PPC::SPE4RCRegClass.contains(SrcReg) &&
959  PPC::SPERCRegClass.contains(DestReg)) {
960  BuildMI(MBB, I, DL, get(PPC::EFDCFS), DestReg).addReg(SrcReg);
961  getKillRegState(KillSrc);
962  return;
963  }
964 
965 
966  unsigned Opc;
967  if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
968  Opc = PPC::OR;
969  else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
970  Opc = PPC::OR8;
971  else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
972  Opc = PPC::FMR;
973  else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
974  Opc = PPC::MCRF;
975  else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
976  Opc = PPC::VOR;
977  else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
978  // There are two different ways this can be done:
979  // 1. xxlor : This has lower latency (on the P7), 2 cycles, but can only
980  // issue in VSU pipeline 0.
981  // 2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
982  // can go to either pipeline.
983  // We'll always use xxlor here, because in practically all cases where
984  // copies are generated, they are close enough to some use that the
985  // lower-latency form is preferable.
986  Opc = PPC::XXLOR;
987  else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) ||
988  PPC::VSSRCRegClass.contains(DestReg, SrcReg))
989  Opc = (Subtarget.hasP9Vector()) ? PPC::XSCPSGNDP : PPC::XXLORf;
990  else if (PPC::QFRCRegClass.contains(DestReg, SrcReg))
991  Opc = PPC::QVFMR;
992  else if (PPC::QSRCRegClass.contains(DestReg, SrcReg))
993  Opc = PPC::QVFMRs;
994  else if (PPC::QBRCRegClass.contains(DestReg, SrcReg))
995  Opc = PPC::QVFMRb;
996  else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
997  Opc = PPC::CROR;
998  else if (PPC::SPERCRegClass.contains(DestReg, SrcReg))
999  Opc = PPC::EVOR;
1000  else
1001  llvm_unreachable("Impossible reg-to-reg copy");
1002 
1003  const MCInstrDesc &MCID = get(Opc);
1004  if (MCID.getNumOperands() == 3)
1005  BuildMI(MBB, I, DL, MCID, DestReg)
1006  .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
1007  else
1008  BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
1009 }
1010 
1012  const TargetRegisterClass *RC)
1013  const {
1014  const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
1015  int OpcodeIndex = 0;
1016 
1017  if (RC != nullptr) {
1018  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1019  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1020  OpcodeIndex = SOK_Int4Spill;
1021  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1022  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1023  OpcodeIndex = SOK_Int8Spill;
1024  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1025  OpcodeIndex = SOK_Float8Spill;
1026  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1027  OpcodeIndex = SOK_Float4Spill;
1028  } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1029  OpcodeIndex = SOK_SPESpill;
1030  } else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) {
1031  OpcodeIndex = SOK_SPE4Spill;
1032  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1033  OpcodeIndex = SOK_CRSpill;
1034  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1035  OpcodeIndex = SOK_CRBitSpill;
1036  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1037  OpcodeIndex = SOK_VRVectorSpill;
1038  } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1039  OpcodeIndex = SOK_VSXVectorSpill;
1040  } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1041  OpcodeIndex = SOK_VectorFloat8Spill;
1042  } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1043  OpcodeIndex = SOK_VectorFloat4Spill;
1044  } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1045  OpcodeIndex = SOK_VRSaveSpill;
1046  } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1047  OpcodeIndex = SOK_QuadFloat8Spill;
1048  } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1049  OpcodeIndex = SOK_QuadFloat4Spill;
1050  } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1051  OpcodeIndex = SOK_QuadBitSpill;
1052  } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1053  OpcodeIndex = SOK_SpillToVSR;
1054  } else {
1055  llvm_unreachable("Unknown regclass!");
1056  }
1057  } else {
1058  if (PPC::GPRCRegClass.contains(Reg) ||
1059  PPC::GPRC_NOR0RegClass.contains(Reg)) {
1060  OpcodeIndex = SOK_Int4Spill;
1061  } else if (PPC::G8RCRegClass.contains(Reg) ||
1062  PPC::G8RC_NOX0RegClass.contains(Reg)) {
1063  OpcodeIndex = SOK_Int8Spill;
1064  } else if (PPC::F8RCRegClass.contains(Reg)) {
1065  OpcodeIndex = SOK_Float8Spill;
1066  } else if (PPC::F4RCRegClass.contains(Reg)) {
1067  OpcodeIndex = SOK_Float4Spill;
1068  } else if (PPC::CRRCRegClass.contains(Reg)) {
1069  OpcodeIndex = SOK_CRSpill;
1070  } else if (PPC::CRBITRCRegClass.contains(Reg)) {
1071  OpcodeIndex = SOK_CRBitSpill;
1072  } else if (PPC::VRRCRegClass.contains(Reg)) {
1073  OpcodeIndex = SOK_VRVectorSpill;
1074  } else if (PPC::VSRCRegClass.contains(Reg)) {
1075  OpcodeIndex = SOK_VSXVectorSpill;
1076  } else if (PPC::VSFRCRegClass.contains(Reg)) {
1077  OpcodeIndex = SOK_VectorFloat8Spill;
1078  } else if (PPC::VSSRCRegClass.contains(Reg)) {
1079  OpcodeIndex = SOK_VectorFloat4Spill;
1080  } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1081  OpcodeIndex = SOK_VRSaveSpill;
1082  } else if (PPC::QFRCRegClass.contains(Reg)) {
1083  OpcodeIndex = SOK_QuadFloat8Spill;
1084  } else if (PPC::QSRCRegClass.contains(Reg)) {
1085  OpcodeIndex = SOK_QuadFloat4Spill;
1086  } else if (PPC::QBRCRegClass.contains(Reg)) {
1087  OpcodeIndex = SOK_QuadBitSpill;
1088  } else if (PPC::SPILLTOVSRRCRegClass.contains(Reg)) {
1089  OpcodeIndex = SOK_SpillToVSR;
1090  } else {
1091  llvm_unreachable("Unknown regclass!");
1092  }
1093  }
1094  return OpcodesForSpill[OpcodeIndex];
1095 }
1096 
1097 unsigned
1099  const TargetRegisterClass *RC) const {
1100  const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
1101  int OpcodeIndex = 0;
1102 
1103  if (RC != nullptr) {
1104  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1105  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1106  OpcodeIndex = SOK_Int4Spill;
1107  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1108  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1109  OpcodeIndex = SOK_Int8Spill;
1110  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1111  OpcodeIndex = SOK_Float8Spill;
1112  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1113  OpcodeIndex = SOK_Float4Spill;
1114  } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1115  OpcodeIndex = SOK_SPESpill;
1116  } else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) {
1117  OpcodeIndex = SOK_SPE4Spill;
1118  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1119  OpcodeIndex = SOK_CRSpill;
1120  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1121  OpcodeIndex = SOK_CRBitSpill;
1122  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1123  OpcodeIndex = SOK_VRVectorSpill;
1124  } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1125  OpcodeIndex = SOK_VSXVectorSpill;
1126  } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1127  OpcodeIndex = SOK_VectorFloat8Spill;
1128  } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1129  OpcodeIndex = SOK_VectorFloat4Spill;
1130  } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1131  OpcodeIndex = SOK_VRSaveSpill;
1132  } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1133  OpcodeIndex = SOK_QuadFloat8Spill;
1134  } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1135  OpcodeIndex = SOK_QuadFloat4Spill;
1136  } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1137  OpcodeIndex = SOK_QuadBitSpill;
1138  } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1139  OpcodeIndex = SOK_SpillToVSR;
1140  } else {
1141  llvm_unreachable("Unknown regclass!");
1142  }
1143  } else {
1144  if (PPC::GPRCRegClass.contains(Reg) ||
1145  PPC::GPRC_NOR0RegClass.contains(Reg)) {
1146  OpcodeIndex = SOK_Int4Spill;
1147  } else if (PPC::G8RCRegClass.contains(Reg) ||
1148  PPC::G8RC_NOX0RegClass.contains(Reg)) {
1149  OpcodeIndex = SOK_Int8Spill;
1150  } else if (PPC::F8RCRegClass.contains(Reg)) {
1151  OpcodeIndex = SOK_Float8Spill;
1152  } else if (PPC::F4RCRegClass.contains(Reg)) {
1153  OpcodeIndex = SOK_Float4Spill;
1154  } else if (PPC::CRRCRegClass.contains(Reg)) {
1155  OpcodeIndex = SOK_CRSpill;
1156  } else if (PPC::CRBITRCRegClass.contains(Reg)) {
1157  OpcodeIndex = SOK_CRBitSpill;
1158  } else if (PPC::VRRCRegClass.contains(Reg)) {
1159  OpcodeIndex = SOK_VRVectorSpill;
1160  } else if (PPC::VSRCRegClass.contains(Reg)) {
1161  OpcodeIndex = SOK_VSXVectorSpill;
1162  } else if (PPC::VSFRCRegClass.contains(Reg)) {
1163  OpcodeIndex = SOK_VectorFloat8Spill;
1164  } else if (PPC::VSSRCRegClass.contains(Reg)) {
1165  OpcodeIndex = SOK_VectorFloat4Spill;
1166  } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1167  OpcodeIndex = SOK_VRSaveSpill;
1168  } else if (PPC::QFRCRegClass.contains(Reg)) {
1169  OpcodeIndex = SOK_QuadFloat8Spill;
1170  } else if (PPC::QSRCRegClass.contains(Reg)) {
1171  OpcodeIndex = SOK_QuadFloat4Spill;
1172  } else if (PPC::QBRCRegClass.contains(Reg)) {
1173  OpcodeIndex = SOK_QuadBitSpill;
1174  } else if (PPC::SPILLTOVSRRCRegClass.contains(Reg)) {
1175  OpcodeIndex = SOK_SpillToVSR;
1176  } else {
1177  llvm_unreachable("Unknown regclass!");
1178  }
1179  }
1180  return OpcodesForSpill[OpcodeIndex];
1181 }
1182 
1183 void PPCInstrInfo::StoreRegToStackSlot(
1184  MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx,
1185  const TargetRegisterClass *RC,
1186  SmallVectorImpl<MachineInstr *> &NewMIs) const {
1187  unsigned Opcode = getStoreOpcodeForSpill(PPC::NoRegister, RC);
1188  DebugLoc DL;
1189 
1190  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1191  FuncInfo->setHasSpills();
1192 
1194  BuildMI(MF, DL, get(Opcode)).addReg(SrcReg, getKillRegState(isKill)),
1195  FrameIdx));
1196 
1197  if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1198  PPC::CRBITRCRegClass.hasSubClassEq(RC))
1199  FuncInfo->setSpillsCR();
1200 
1201  if (PPC::VRSAVERCRegClass.hasSubClassEq(RC))
1202  FuncInfo->setSpillsVRSAVE();
1203 
1204  if (isXFormMemOp(Opcode))
1205  FuncInfo->setHasNonRISpills();
1206 }
1207 
1210  unsigned SrcReg, bool isKill,
1211  int FrameIdx,
1212  const TargetRegisterClass *RC,
1213  const TargetRegisterInfo *TRI) const {
1214  MachineFunction &MF = *MBB.getParent();
1216 
1217  // We need to avoid a situation in which the value from a VRRC register is
1218  // spilled using an Altivec instruction and reloaded into a VSRC register
1219  // using a VSX instruction. The issue with this is that the VSX
1220  // load/store instructions swap the doublewords in the vector and the Altivec
1221  // ones don't. The register classes on the spill/reload may be different if
1222  // the register is defined using an Altivec instruction and is then used by a
1223  // VSX instruction.
1224  RC = updatedRC(RC);
1225 
1226  StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs);
1227 
1228  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1229  MBB.insert(MI, NewMIs[i]);
1230 
1231  const MachineFrameInfo &MFI = MF.getFrameInfo();
1233  MachinePointerInfo::getFixedStack(MF, FrameIdx),
1235  MFI.getObjectAlignment(FrameIdx));
1236  NewMIs.back()->addMemOperand(MF, MMO);
1237 }
1238 
1239 void PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
1240  unsigned DestReg, int FrameIdx,
1241  const TargetRegisterClass *RC,
1243  const {
1244  unsigned Opcode = getLoadOpcodeForSpill(PPC::NoRegister, RC);
1245  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opcode), DestReg),
1246  FrameIdx));
1247  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1248 
1249  if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1250  PPC::CRBITRCRegClass.hasSubClassEq(RC))
1251  FuncInfo->setSpillsCR();
1252 
1253  if (PPC::VRSAVERCRegClass.hasSubClassEq(RC))
1254  FuncInfo->setSpillsVRSAVE();
1255 
1256  if (isXFormMemOp(Opcode))
1257  FuncInfo->setHasNonRISpills();
1258 }
1259 
1260 void
1263  unsigned DestReg, int FrameIdx,
1264  const TargetRegisterClass *RC,
1265  const TargetRegisterInfo *TRI) const {
1266  MachineFunction &MF = *MBB.getParent();
1268  DebugLoc DL;
1269  if (MI != MBB.end()) DL = MI->getDebugLoc();
1270 
1271  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1272  FuncInfo->setHasSpills();
1273 
1274  // We need to avoid a situation in which the value from a VRRC register is
1275  // spilled using an Altivec instruction and reloaded into a VSRC register
1276  // using a VSX instruction. The issue with this is that the VSX
1277  // load/store instructions swap the doublewords in the vector and the Altivec
1278  // ones don't. The register classes on the spill/reload may be different if
1279  // the register is defined using an Altivec instruction and is then used by a
1280  // VSX instruction.
1281  if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
1282  RC = &PPC::VSRCRegClass;
1283 
1284  LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
1285 
1286  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1287  MBB.insert(MI, NewMIs[i]);
1288 
1289  const MachineFrameInfo &MFI = MF.getFrameInfo();
1291  MachinePointerInfo::getFixedStack(MF, FrameIdx),
1293  MFI.getObjectAlignment(FrameIdx));
1294  NewMIs.back()->addMemOperand(MF, MMO);
1295 }
1296 
1297 bool PPCInstrInfo::
1299  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
1300  if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
1301  Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
1302  else
1303  // Leave the CR# the same, but invert the condition.
1304  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
1305  return false;
1306 }
1307 
1309  unsigned Reg, MachineRegisterInfo *MRI) const {
1310  // For some instructions, it is legal to fold ZERO into the RA register field.
1311  // A zero immediate should always be loaded with a single li.
1312  unsigned DefOpc = DefMI.getOpcode();
1313  if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
1314  return false;
1315  if (!DefMI.getOperand(1).isImm())
1316  return false;
1317  if (DefMI.getOperand(1).getImm() != 0)
1318  return false;
1319 
1320  // Note that we cannot here invert the arguments of an isel in order to fold
1321  // a ZERO into what is presented as the second argument. All we have here
1322  // is the condition bit, and that might come from a CR-logical bit operation.
1323 
1324  const MCInstrDesc &UseMCID = UseMI.getDesc();
1325 
1326  // Only fold into real machine instructions.
1327  if (UseMCID.isPseudo())
1328  return false;
1329 
1330  unsigned UseIdx;
1331  for (UseIdx = 0; UseIdx < UseMI.getNumOperands(); ++UseIdx)
1332  if (UseMI.getOperand(UseIdx).isReg() &&
1333  UseMI.getOperand(UseIdx).getReg() == Reg)
1334  break;
1335 
1336  assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI");
1337  assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
1338 
1339  const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
1340 
1341  // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
1342  // register (which might also be specified as a pointer class kind).
1343  if (UseInfo->isLookupPtrRegClass()) {
1344  if (UseInfo->RegClass /* Kind */ != 1)
1345  return false;
1346  } else {
1347  if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
1348  UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
1349  return false;
1350  }
1351 
1352  // Make sure this is not tied to an output register (or otherwise
1353  // constrained). This is true for ST?UX registers, for example, which
1354  // are tied to their output registers.
1355  if (UseInfo->Constraints != 0)
1356  return false;
1357 
1358  unsigned ZeroReg;
1359  if (UseInfo->isLookupPtrRegClass()) {
1360  bool isPPC64 = Subtarget.isPPC64();
1361  ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
1362  } else {
1363  ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
1364  PPC::ZERO8 : PPC::ZERO;
1365  }
1366 
1367  bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1368  UseMI.getOperand(UseIdx).setReg(ZeroReg);
1369 
1370  if (DeleteDef)
1371  DefMI.eraseFromParent();
1372 
1373  return true;
1374 }
1375 
1377  for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
1378  I != IE; ++I)
1379  if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
1380  return true;
1381  return false;
1382 }
1383 
1384 // We should make sure that, if we're going to predicate both sides of a
1385 // condition (a diamond), that both sides don't define the counter register. We
1386 // can predicate counter-decrement-based branches, but while that predicates
1387 // the branching, it does not predicate the counter decrement. If we tried to
1388 // merge the triangle into one predicated block, we'd decrement the counter
1389 // twice.
1391  unsigned NumT, unsigned ExtraT,
1392  MachineBasicBlock &FMBB,
1393  unsigned NumF, unsigned ExtraF,
1394  BranchProbability Probability) const {
1395  return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
1396 }
1397 
1398 
1400  // The predicated branches are identified by their type, not really by the
1401  // explicit presence of a predicate. Furthermore, some of them can be
1402  // predicated more than once. Because if conversion won't try to predicate
1403  // any instruction which already claims to be predicated (by returning true
1404  // here), always return false. In doing so, we let isPredicable() be the
1405  // final word on whether not the instruction can be (further) predicated.
1406 
1407  return false;
1408 }
1409 
1411  if (!MI.isTerminator())
1412  return false;
1413 
1414  // Conditional branch is a special case.
1415  if (MI.isBranch() && !MI.isBarrier())
1416  return true;
1417 
1418  return !isPredicated(MI);
1419 }
1420 
1422  ArrayRef<MachineOperand> Pred) const {
1423  unsigned OpC = MI.getOpcode();
1424  if (OpC == PPC::BLR || OpC == PPC::BLR8) {
1425  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1426  bool isPPC64 = Subtarget.isPPC64();
1427  MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR)
1428  : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
1429  } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1430  MI.setDesc(get(PPC::BCLR));
1431  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1432  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1433  MI.setDesc(get(PPC::BCLRn));
1434  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1435  } else {
1436  MI.setDesc(get(PPC::BCCLR));
1438  .addImm(Pred[0].getImm())
1439  .add(Pred[1]);
1440  }
1441 
1442  return true;
1443  } else if (OpC == PPC::B) {
1444  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1445  bool isPPC64 = Subtarget.isPPC64();
1446  MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
1447  : (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
1448  } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1449  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1450  MI.RemoveOperand(0);
1451 
1452  MI.setDesc(get(PPC::BC));
1454  .add(Pred[1])
1455  .addMBB(MBB);
1456  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1457  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1458  MI.RemoveOperand(0);
1459 
1460  MI.setDesc(get(PPC::BCn));
1462  .add(Pred[1])
1463  .addMBB(MBB);
1464  } else {
1465  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1466  MI.RemoveOperand(0);
1467 
1468  MI.setDesc(get(PPC::BCC));
1470  .addImm(Pred[0].getImm())
1471  .add(Pred[1])
1472  .addMBB(MBB);
1473  }
1474 
1475  return true;
1476  } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 || OpC == PPC::BCTRL ||
1477  OpC == PPC::BCTRL8) {
1478  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
1479  llvm_unreachable("Cannot predicate bctr[l] on the ctr register");
1480 
1481  bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
1482  bool isPPC64 = Subtarget.isPPC64();
1483 
1484  if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1485  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8)
1486  : (setLR ? PPC::BCCTRL : PPC::BCCTR)));
1487  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1488  return true;
1489  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1490  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n)
1491  : (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
1492  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1493  return true;
1494  }
1495 
1496  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8)
1497  : (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
1499  .addImm(Pred[0].getImm())
1500  .add(Pred[1]);
1501  return true;
1502  }
1503 
1504  return false;
1505 }
1506 
1508  ArrayRef<MachineOperand> Pred2) const {
1509  assert(Pred1.size() == 2 && "Invalid PPC first predicate");
1510  assert(Pred2.size() == 2 && "Invalid PPC second predicate");
1511 
1512  if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1513  return false;
1514  if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
1515  return false;
1516 
1517  // P1 can only subsume P2 if they test the same condition register.
1518  if (Pred1[1].getReg() != Pred2[1].getReg())
1519  return false;
1520 
1521  PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
1522  PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
1523 
1524  if (P1 == P2)
1525  return true;
1526 
1527  // Does P1 subsume P2, e.g. GE subsumes GT.
1528  if (P1 == PPC::PRED_LE &&
1529  (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
1530  return true;
1531  if (P1 == PPC::PRED_GE &&
1532  (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
1533  return true;
1534 
1535  return false;
1536 }
1537 
1539  std::vector<MachineOperand> &Pred) const {
1540  // Note: At the present time, the contents of Pred from this function is
1541  // unused by IfConversion. This implementation follows ARM by pushing the
1542  // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
1543  // predicate, instructions defining CTR or CTR8 are also included as
1544  // predicate-defining instructions.
1545 
1546  const TargetRegisterClass *RCs[] =
1547  { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1548  &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1549 
1550  bool Found = false;
1551  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1552  const MachineOperand &MO = MI.getOperand(i);
1553  for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
1554  const TargetRegisterClass *RC = RCs[c];
1555  if (MO.isReg()) {
1556  if (MO.isDef() && RC->contains(MO.getReg())) {
1557  Pred.push_back(MO);
1558  Found = true;
1559  }
1560  } else if (MO.isRegMask()) {
1561  for (TargetRegisterClass::iterator I = RC->begin(),
1562  IE = RC->end(); I != IE; ++I)
1563  if (MO.clobbersPhysReg(*I)) {
1564  Pred.push_back(MO);
1565  Found = true;
1566  }
1567  }
1568  }
1569  }
1570 
1571  return Found;
1572 }
1573 
1575  unsigned OpC = MI.getOpcode();
1576  switch (OpC) {
1577  default:
1578  return false;
1579  case PPC::B:
1580  case PPC::BLR:
1581  case PPC::BLR8:
1582  case PPC::BCTR:
1583  case PPC::BCTR8:
1584  case PPC::BCTRL:
1585  case PPC::BCTRL8:
1586  return true;
1587  }
1588 }
1589 
1590 bool PPCInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1591  unsigned &SrcReg2, int &Mask,
1592  int &Value) const {
1593  unsigned Opc = MI.getOpcode();
1594 
1595  switch (Opc) {
1596  default: return false;
1597  case PPC::CMPWI:
1598  case PPC::CMPLWI:
1599  case PPC::CMPDI:
1600  case PPC::CMPLDI:
1601  SrcReg = MI.getOperand(1).getReg();
1602  SrcReg2 = 0;
1603  Value = MI.getOperand(2).getImm();
1604  Mask = 0xFFFF;
1605  return true;
1606  case PPC::CMPW:
1607  case PPC::CMPLW:
1608  case PPC::CMPD:
1609  case PPC::CMPLD:
1610  case PPC::FCMPUS:
1611  case PPC::FCMPUD:
1612  SrcReg = MI.getOperand(1).getReg();
1613  SrcReg2 = MI.getOperand(2).getReg();
1614  Value = 0;
1615  Mask = 0;
1616  return true;
1617  }
1618 }
1619 
1620 bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1621  unsigned SrcReg2, int Mask, int Value,
1622  const MachineRegisterInfo *MRI) const {
1623  if (DisableCmpOpt)
1624  return false;
1625 
1626  int OpC = CmpInstr.getOpcode();
1627  unsigned CRReg = CmpInstr.getOperand(0).getReg();
1628 
1629  // FP record forms set CR1 based on the exception status bits, not a
1630  // comparison with zero.
1631  if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
1632  return false;
1633 
1634  // The record forms set the condition register based on a signed comparison
1635  // with zero (so says the ISA manual). This is not as straightforward as it
1636  // seems, however, because this is always a 64-bit comparison on PPC64, even
1637  // for instructions that are 32-bit in nature (like slw for example).
1638  // So, on PPC32, for unsigned comparisons, we can use the record forms only
1639  // for equality checks (as those don't depend on the sign). On PPC64,
1640  // we are restricted to equality for unsigned 64-bit comparisons and for
1641  // signed 32-bit comparisons the applicability is more restricted.
1642  bool isPPC64 = Subtarget.isPPC64();
1643  bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
1644  bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
1645  bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
1646 
1647  // Get the unique definition of SrcReg.
1648  MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1649  if (!MI) return false;
1650 
1651  bool equalityOnly = false;
1652  bool noSub = false;
1653  if (isPPC64) {
1654  if (is32BitSignedCompare) {
1655  // We can perform this optimization only if MI is sign-extending.
1656  if (isSignExtended(*MI))
1657  noSub = true;
1658  else
1659  return false;
1660  } else if (is32BitUnsignedCompare) {
1661  // We can perform this optimization, equality only, if MI is
1662  // zero-extending.
1663  if (isZeroExtended(*MI)) {
1664  noSub = true;
1665  equalityOnly = true;
1666  } else
1667  return false;
1668  } else
1669  equalityOnly = is64BitUnsignedCompare;
1670  } else
1671  equalityOnly = is32BitUnsignedCompare;
1672 
1673  if (equalityOnly) {
1674  // We need to check the uses of the condition register in order to reject
1675  // non-equality comparisons.
1677  I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1678  I != IE; ++I) {
1679  MachineInstr *UseMI = &*I;
1680  if (UseMI->getOpcode() == PPC::BCC) {
1681  PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
1682  unsigned PredCond = PPC::getPredicateCondition(Pred);
1683  // We ignore hint bits when checking for non-equality comparisons.
1684  if (PredCond != PPC::PRED_EQ && PredCond != PPC::PRED_NE)
1685  return false;
1686  } else if (UseMI->getOpcode() == PPC::ISEL ||
1687  UseMI->getOpcode() == PPC::ISEL8) {
1688  unsigned SubIdx = UseMI->getOperand(3).getSubReg();
1689  if (SubIdx != PPC::sub_eq)
1690  return false;
1691  } else
1692  return false;
1693  }
1694  }
1695 
1696  MachineBasicBlock::iterator I = CmpInstr;
1697 
1698  // Scan forward to find the first use of the compare.
1699  for (MachineBasicBlock::iterator EL = CmpInstr.getParent()->end(); I != EL;
1700  ++I) {
1701  bool FoundUse = false;
1703  J = MRI->use_instr_begin(CRReg), JE = MRI->use_instr_end();
1704  J != JE; ++J)
1705  if (&*J == &*I) {
1706  FoundUse = true;
1707  break;
1708  }
1709 
1710  if (FoundUse)
1711  break;
1712  }
1713 
1716 
1717  // There are two possible candidates which can be changed to set CR[01].
1718  // One is MI, the other is a SUB instruction.
1719  // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
1720  MachineInstr *Sub = nullptr;
1721  if (SrcReg2 != 0)
1722  // MI is not a candidate for CMPrr.
1723  MI = nullptr;
1724  // FIXME: Conservatively refuse to convert an instruction which isn't in the
1725  // same BB as the comparison. This is to allow the check below to avoid calls
1726  // (and other explicit clobbers); instead we should really check for these
1727  // more explicitly (in at least a few predecessors).
1728  else if (MI->getParent() != CmpInstr.getParent())
1729  return false;
1730  else if (Value != 0) {
1731  // The record-form instructions set CR bit based on signed comparison
1732  // against 0. We try to convert a compare against 1 or -1 into a compare
1733  // against 0 to exploit record-form instructions. For example, we change
1734  // the condition "greater than -1" into "greater than or equal to 0"
1735  // and "less than 1" into "less than or equal to 0".
1736 
1737  // Since we optimize comparison based on a specific branch condition,
1738  // we don't optimize if condition code is used by more than once.
1739  if (equalityOnly || !MRI->hasOneUse(CRReg))
1740  return false;
1741 
1742  MachineInstr *UseMI = &*MRI->use_instr_begin(CRReg);
1743  if (UseMI->getOpcode() != PPC::BCC)
1744  return false;
1745 
1746  PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
1747  PPC::Predicate NewPred = Pred;
1748  unsigned PredCond = PPC::getPredicateCondition(Pred);
1749  unsigned PredHint = PPC::getPredicateHint(Pred);
1750  int16_t Immed = (int16_t)Value;
1751 
1752  // When modifying the condition in the predicate, we propagate hint bits
1753  // from the original predicate to the new one.
1754  if (Immed == -1 && PredCond == PPC::PRED_GT)
1755  // We convert "greater than -1" into "greater than or equal to 0",
1756  // since we are assuming signed comparison by !equalityOnly
1757  NewPred = PPC::getPredicate(PPC::PRED_GE, PredHint);
1758  else if (Immed == -1 && PredCond == PPC::PRED_LE)
1759  // We convert "less than or equal to -1" into "less than 0".
1760  NewPred = PPC::getPredicate(PPC::PRED_LT, PredHint);
1761  else if (Immed == 1 && PredCond == PPC::PRED_LT)
1762  // We convert "less than 1" into "less than or equal to 0".
1763  NewPred = PPC::getPredicate(PPC::PRED_LE, PredHint);
1764  else if (Immed == 1 && PredCond == PPC::PRED_GE)
1765  // We convert "greater than or equal to 1" into "greater than 0".
1766  NewPred = PPC::getPredicate(PPC::PRED_GT, PredHint);
1767  else
1768  return false;
1769 
1770  PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1771  NewPred));
1772  }
1773 
1774  // Search for Sub.
1776  --I;
1777 
1778  // Get ready to iterate backward from CmpInstr.
1779  MachineBasicBlock::iterator E = MI, B = CmpInstr.getParent()->begin();
1780 
1781  for (; I != E && !noSub; --I) {
1782  const MachineInstr &Instr = *I;
1783  unsigned IOpC = Instr.getOpcode();
1784 
1785  if (&*I != &CmpInstr && (Instr.modifiesRegister(PPC::CR0, TRI) ||
1786  Instr.readsRegister(PPC::CR0, TRI)))
1787  // This instruction modifies or uses the record condition register after
1788  // the one we want to change. While we could do this transformation, it
1789  // would likely not be profitable. This transformation removes one
1790  // instruction, and so even forcing RA to generate one move probably
1791  // makes it unprofitable.
1792  return false;
1793 
1794  // Check whether CmpInstr can be made redundant by the current instruction.
1795  if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
1796  OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
1797  (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
1798  ((Instr.getOperand(1).getReg() == SrcReg &&
1799  Instr.getOperand(2).getReg() == SrcReg2) ||
1800  (Instr.getOperand(1).getReg() == SrcReg2 &&
1801  Instr.getOperand(2).getReg() == SrcReg))) {
1802  Sub = &*I;
1803  break;
1804  }
1805 
1806  if (I == B)
1807  // The 'and' is below the comparison instruction.
1808  return false;
1809  }
1810 
1811  // Return false if no candidates exist.
1812  if (!MI && !Sub)
1813  return false;
1814 
1815  // The single candidate is called MI.
1816  if (!MI) MI = Sub;
1817 
1818  int NewOpC = -1;
1819  int MIOpC = MI->getOpcode();
1820  if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8 ||
1821  MIOpC == PPC::ANDISo || MIOpC == PPC::ANDISo8)
1822  NewOpC = MIOpC;
1823  else {
1824  NewOpC = PPC::getRecordFormOpcode(MIOpC);
1825  if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
1826  NewOpC = MIOpC;
1827  }
1828 
1829  // FIXME: On the non-embedded POWER architectures, only some of the record
1830  // forms are fast, and we should use only the fast ones.
1831 
1832  // The defining instruction has a record form (or is already a record
1833  // form). It is possible, however, that we'll need to reverse the condition
1834  // code of the users.
1835  if (NewOpC == -1)
1836  return false;
1837 
1838  // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
1839  // needs to be updated to be based on SUB. Push the condition code
1840  // operands to OperandsToUpdate. If it is safe to remove CmpInstr, the
1841  // condition code of these operands will be modified.
1842  // Here, Value == 0 means we haven't converted comparison against 1 or -1 to
1843  // comparison against 0, which may modify predicate.
1844  bool ShouldSwap = false;
1845  if (Sub && Value == 0) {
1846  ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1847  Sub->getOperand(2).getReg() == SrcReg;
1848 
1849  // The operands to subf are the opposite of sub, so only in the fixed-point
1850  // case, invert the order.
1851  ShouldSwap = !ShouldSwap;
1852  }
1853 
1854  if (ShouldSwap)
1856  I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1857  I != IE; ++I) {
1858  MachineInstr *UseMI = &*I;
1859  if (UseMI->getOpcode() == PPC::BCC) {
1860  PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
1861  unsigned PredCond = PPC::getPredicateCondition(Pred);
1862  assert((!equalityOnly ||
1863  PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE) &&
1864  "Invalid predicate for equality-only optimization");
1865  (void)PredCond; // To suppress warning in release build.
1866  PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1867  PPC::getSwappedPredicate(Pred)));
1868  } else if (UseMI->getOpcode() == PPC::ISEL ||
1869  UseMI->getOpcode() == PPC::ISEL8) {
1870  unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
1871  assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
1872  "Invalid CR bit for equality-only optimization");
1873 
1874  if (NewSubReg == PPC::sub_lt)
1875  NewSubReg = PPC::sub_gt;
1876  else if (NewSubReg == PPC::sub_gt)
1877  NewSubReg = PPC::sub_lt;
1878 
1879  SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)),
1880  NewSubReg));
1881  } else // We need to abort on a user we don't understand.
1882  return false;
1883  }
1884  assert(!(Value != 0 && ShouldSwap) &&
1885  "Non-zero immediate support and ShouldSwap"
1886  "may conflict in updating predicate");
1887 
1888  // Create a new virtual register to hold the value of the CR set by the
1889  // record-form instruction. If the instruction was not previously in
1890  // record form, then set the kill flag on the CR.
1891  CmpInstr.eraseFromParent();
1892 
1894  BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
1895  get(TargetOpcode::COPY), CRReg)
1896  .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
1897 
1898  // Even if CR0 register were dead before, it is alive now since the
1899  // instruction we just built uses it.
1900  MI->clearRegisterDeads(PPC::CR0);
1901 
1902  if (MIOpC != NewOpC) {
1903  // We need to be careful here: we're replacing one instruction with
1904  // another, and we need to make sure that we get all of the right
1905  // implicit uses and defs. On the other hand, the caller may be holding
1906  // an iterator to this instruction, and so we can't delete it (this is
1907  // specifically the case if this is the instruction directly after the
1908  // compare).
1909 
1910  // Rotates are expensive instructions. If we're emitting a record-form
1911  // rotate that can just be an andi/andis, we should just emit that.
1912  if (MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINM8) {
1913  unsigned GPRRes = MI->getOperand(0).getReg();
1914  int64_t SH = MI->getOperand(2).getImm();
1915  int64_t MB = MI->getOperand(3).getImm();
1916  int64_t ME = MI->getOperand(4).getImm();
1917  // We can only do this if both the start and end of the mask are in the
1918  // same halfword.
1919  bool MBInLoHWord = MB >= 16;
1920  bool MEInLoHWord = ME >= 16;
1921  uint64_t Mask = ~0LLU;
1922 
1923  if (MB <= ME && MBInLoHWord == MEInLoHWord && SH == 0) {
1924  Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
1925  // The mask value needs to shift right 16 if we're emitting andis.
1926  Mask >>= MBInLoHWord ? 0 : 16;
1927  NewOpC = MIOpC == PPC::RLWINM ?
1928  (MBInLoHWord ? PPC::ANDIo : PPC::ANDISo) :
1929  (MBInLoHWord ? PPC::ANDIo8 :PPC::ANDISo8);
1930  } else if (MRI->use_empty(GPRRes) && (ME == 31) &&
1931  (ME - MB + 1 == SH) && (MB >= 16)) {
1932  // If we are rotating by the exact number of bits as are in the mask
1933  // and the mask is in the least significant bits of the register,
1934  // that's just an andis. (as long as the GPR result has no uses).
1935  Mask = ((1LLU << 32) - 1) & ~((1LLU << (32 - SH)) - 1);
1936  Mask >>= 16;
1937  NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDISo :PPC::ANDISo8;
1938  }
1939  // If we've set the mask, we can transform.
1940  if (Mask != ~0LLU) {
1941  MI->RemoveOperand(4);
1942  MI->RemoveOperand(3);
1943  MI->getOperand(2).setImm(Mask);
1944  NumRcRotatesConvertedToRcAnd++;
1945  }
1946  } else if (MIOpC == PPC::RLDICL && MI->getOperand(2).getImm() == 0) {
1947  int64_t MB = MI->getOperand(3).getImm();
1948  if (MB >= 48) {
1949  uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
1950  NewOpC = PPC::ANDIo8;
1951  MI->RemoveOperand(3);
1952  MI->getOperand(2).setImm(Mask);
1953  NumRcRotatesConvertedToRcAnd++;
1954  }
1955  }
1956 
1957  const MCInstrDesc &NewDesc = get(NewOpC);
1958  MI->setDesc(NewDesc);
1959 
1960  if (NewDesc.ImplicitDefs)
1961  for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs();
1962  *ImpDefs; ++ImpDefs)
1963  if (!MI->definesRegister(*ImpDefs))
1964  MI->addOperand(*MI->getParent()->getParent(),
1965  MachineOperand::CreateReg(*ImpDefs, true, true));
1966  if (NewDesc.ImplicitUses)
1967  for (const MCPhysReg *ImpUses = NewDesc.getImplicitUses();
1968  *ImpUses; ++ImpUses)
1969  if (!MI->readsRegister(*ImpUses))
1970  MI->addOperand(*MI->getParent()->getParent(),
1971  MachineOperand::CreateReg(*ImpUses, false, true));
1972  }
1973  assert(MI->definesRegister(PPC::CR0) &&
1974  "Record-form instruction does not define cr0?");
1975 
1976  // Modify the condition code of operands in OperandsToUpdate.
1977  // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
1978  // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
1979  for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
1980  PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
1981 
1982  for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
1983  SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
1984 
1985  return true;
1986 }
1987 
1988 /// GetInstSize - Return the number of bytes of code the specified
1989 /// instruction may be. This returns the maximum number of bytes.
1990 ///
1992  unsigned Opcode = MI.getOpcode();
1993 
1994  if (Opcode == PPC::INLINEASM) {
1995  const MachineFunction *MF = MI.getParent()->getParent();
1996  const char *AsmStr = MI.getOperand(0).getSymbolName();
1997  return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1998  } else if (Opcode == TargetOpcode::STACKMAP) {
1999  StackMapOpers Opers(&MI);
2000  return Opers.getNumPatchBytes();
2001  } else if (Opcode == TargetOpcode::PATCHPOINT) {
2002  PatchPointOpers Opers(&MI);
2003  return Opers.getNumPatchBytes();
2004  } else {
2005  return get(Opcode).getSize();
2006  }
2007 }
2008 
2009 std::pair<unsigned, unsigned>
2011  const unsigned Mask = PPCII::MO_ACCESS_MASK;
2012  return std::make_pair(TF & Mask, TF & ~Mask);
2013 }
2014 
2017  using namespace PPCII;
2018  static const std::pair<unsigned, const char *> TargetFlags[] = {
2019  {MO_LO, "ppc-lo"},
2020  {MO_HA, "ppc-ha"},
2021  {MO_TPREL_LO, "ppc-tprel-lo"},
2022  {MO_TPREL_HA, "ppc-tprel-ha"},
2023  {MO_DTPREL_LO, "ppc-dtprel-lo"},
2024  {MO_TLSLD_LO, "ppc-tlsld-lo"},
2025  {MO_TOC_LO, "ppc-toc-lo"},
2026  {MO_TLS, "ppc-tls"}};
2027  return makeArrayRef(TargetFlags);
2028 }
2029 
2032  using namespace PPCII;
2033  static const std::pair<unsigned, const char *> TargetFlags[] = {
2034  {MO_PLT, "ppc-plt"},
2035  {MO_PIC_FLAG, "ppc-pic"},
2036  {MO_NLP_FLAG, "ppc-nlp"},
2037  {MO_NLP_HIDDEN_FLAG, "ppc-nlp-hidden"}};
2038  return makeArrayRef(TargetFlags);
2039 }
2040 
2041 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
2042 // The VSX versions have the advantage of a full 64-register target whereas
2043 // the FP ones have the advantage of lower latency and higher throughput. So
2044 // what we are after is using the faster instructions in low register pressure
2045 // situations and using the larger register file in high register pressure
2046 // situations.
2048  unsigned UpperOpcode, LowerOpcode;
2049  switch (MI.getOpcode()) {
2050  case PPC::DFLOADf32:
2051  UpperOpcode = PPC::LXSSP;
2052  LowerOpcode = PPC::LFS;
2053  break;
2054  case PPC::DFLOADf64:
2055  UpperOpcode = PPC::LXSD;
2056  LowerOpcode = PPC::LFD;
2057  break;
2058  case PPC::DFSTOREf32:
2059  UpperOpcode = PPC::STXSSP;
2060  LowerOpcode = PPC::STFS;
2061  break;
2062  case PPC::DFSTOREf64:
2063  UpperOpcode = PPC::STXSD;
2064  LowerOpcode = PPC::STFD;
2065  break;
2066  case PPC::XFLOADf32:
2067  UpperOpcode = PPC::LXSSPX;
2068  LowerOpcode = PPC::LFSX;
2069  break;
2070  case PPC::XFLOADf64:
2071  UpperOpcode = PPC::LXSDX;
2072  LowerOpcode = PPC::LFDX;
2073  break;
2074  case PPC::XFSTOREf32:
2075  UpperOpcode = PPC::STXSSPX;
2076  LowerOpcode = PPC::STFSX;
2077  break;
2078  case PPC::XFSTOREf64:
2079  UpperOpcode = PPC::STXSDX;
2080  LowerOpcode = PPC::STFDX;
2081  break;
2082  case PPC::LIWAX:
2083  UpperOpcode = PPC::LXSIWAX;
2084  LowerOpcode = PPC::LFIWAX;
2085  break;
2086  case PPC::LIWZX:
2087  UpperOpcode = PPC::LXSIWZX;
2088  LowerOpcode = PPC::LFIWZX;
2089  break;
2090  case PPC::STIWX:
2091  UpperOpcode = PPC::STXSIWX;
2092  LowerOpcode = PPC::STFIWX;
2093  break;
2094  default:
2095  llvm_unreachable("Unknown Operation!");
2096  }
2097 
2098  unsigned TargetReg = MI.getOperand(0).getReg();
2099  unsigned Opcode;
2100  if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) ||
2101  (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31))
2102  Opcode = LowerOpcode;
2103  else
2104  Opcode = UpperOpcode;
2105  MI.setDesc(get(Opcode));
2106  return true;
2107 }
2108 
2109 static bool isAnImmediateOperand(const MachineOperand &MO) {
2110  return MO.isCPI() || MO.isGlobal() || MO.isImm();
2111 }
2112 
2114  auto &MBB = *MI.getParent();
2115  auto DL = MI.getDebugLoc();
2116 
2117  switch (MI.getOpcode()) {
2118  case TargetOpcode::LOAD_STACK_GUARD: {
2119  assert(Subtarget.isTargetLinux() &&
2120  "Only Linux target is expected to contain LOAD_STACK_GUARD");
2121  const int64_t Offset = Subtarget.isPPC64() ? -0x7010 : -0x7008;
2122  const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2;
2123  MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ));
2125  .addImm(Offset)
2126  .addReg(Reg);
2127  return true;
2128  }
2129  case PPC::DFLOADf32:
2130  case PPC::DFLOADf64:
2131  case PPC::DFSTOREf32:
2132  case PPC::DFSTOREf64: {
2133  assert(Subtarget.hasP9Vector() &&
2134  "Invalid D-Form Pseudo-ops on Pre-P9 target.");
2135  assert(MI.getOperand(2).isReg() &&
2137  "D-form op must have register and immediate operands");
2138  return expandVSXMemPseudo(MI);
2139  }
2140  case PPC::XFLOADf32:
2141  case PPC::XFSTOREf32:
2142  case PPC::LIWAX:
2143  case PPC::LIWZX:
2144  case PPC::STIWX: {
2145  assert(Subtarget.hasP8Vector() &&
2146  "Invalid X-Form Pseudo-ops on Pre-P8 target.");
2147  assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
2148  "X-form op must have register and register operands");
2149  return expandVSXMemPseudo(MI);
2150  }
2151  case PPC::XFLOADf64:
2152  case PPC::XFSTOREf64: {
2153  assert(Subtarget.hasVSX() &&
2154  "Invalid X-Form Pseudo-ops on target that has no VSX.");
2155  assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
2156  "X-form op must have register and register operands");
2157  return expandVSXMemPseudo(MI);
2158  }
2159  case PPC::SPILLTOVSR_LD: {
2160  unsigned TargetReg = MI.getOperand(0).getReg();
2161  if (PPC::VSFRCRegClass.contains(TargetReg)) {
2162  MI.setDesc(get(PPC::DFLOADf64));
2163  return expandPostRAPseudo(MI);
2164  }
2165  else
2166  MI.setDesc(get(PPC::LD));
2167  return true;
2168  }
2169  case PPC::SPILLTOVSR_ST: {
2170  unsigned SrcReg = MI.getOperand(0).getReg();
2171  if (PPC::VSFRCRegClass.contains(SrcReg)) {
2172  NumStoreSPILLVSRRCAsVec++;
2173  MI.setDesc(get(PPC::DFSTOREf64));
2174  return expandPostRAPseudo(MI);
2175  } else {
2176  NumStoreSPILLVSRRCAsGpr++;
2177  MI.setDesc(get(PPC::STD));
2178  }
2179  return true;
2180  }
2181  case PPC::SPILLTOVSR_LDX: {
2182  unsigned TargetReg = MI.getOperand(0).getReg();
2183  if (PPC::VSFRCRegClass.contains(TargetReg))
2184  MI.setDesc(get(PPC::LXSDX));
2185  else
2186  MI.setDesc(get(PPC::LDX));
2187  return true;
2188  }
2189  case PPC::SPILLTOVSR_STX: {
2190  unsigned SrcReg = MI.getOperand(0).getReg();
2191  if (PPC::VSFRCRegClass.contains(SrcReg)) {
2192  NumStoreSPILLVSRRCAsVec++;
2193  MI.setDesc(get(PPC::STXSDX));
2194  } else {
2195  NumStoreSPILLVSRRCAsGpr++;
2196  MI.setDesc(get(PPC::STDX));
2197  }
2198  return true;
2199  }
2200 
2201  case PPC::CFENCE8: {
2202  auto Val = MI.getOperand(0).getReg();
2203  BuildMI(MBB, MI, DL, get(PPC::CMPD), PPC::CR7).addReg(Val).addReg(Val);
2204  BuildMI(MBB, MI, DL, get(PPC::CTRL_DEP))
2206  .addReg(PPC::CR7)
2207  .addImm(1);
2208  MI.setDesc(get(PPC::ISYNC));
2209  MI.RemoveOperand(0);
2210  return true;
2211  }
2212  }
2213  return false;
2214 }
2215 
2216 // Essentially a compile-time implementation of a compare->isel sequence.
2217 // It takes two constants to compare, along with the true/false registers
2218 // and the comparison type (as a subreg to a CR field) and returns one
2219 // of the true/false registers, depending on the comparison results.
2220 static unsigned selectReg(int64_t Imm1, int64_t Imm2, unsigned CompareOpc,
2221  unsigned TrueReg, unsigned FalseReg,
2222  unsigned CRSubReg) {
2223  // Signed comparisons. The immediates are assumed to be sign-extended.
2224  if (CompareOpc == PPC::CMPWI || CompareOpc == PPC::CMPDI) {
2225  switch (CRSubReg) {
2226  default: llvm_unreachable("Unknown integer comparison type.");
2227  case PPC::sub_lt:
2228  return Imm1 < Imm2 ? TrueReg : FalseReg;
2229  case PPC::sub_gt:
2230  return Imm1 > Imm2 ? TrueReg : FalseReg;
2231  case PPC::sub_eq:
2232  return Imm1 == Imm2 ? TrueReg : FalseReg;
2233  }
2234  }
2235  // Unsigned comparisons.
2236  else if (CompareOpc == PPC::CMPLWI || CompareOpc == PPC::CMPLDI) {
2237  switch (CRSubReg) {
2238  default: llvm_unreachable("Unknown integer comparison type.");
2239  case PPC::sub_lt:
2240  return (uint64_t)Imm1 < (uint64_t)Imm2 ? TrueReg : FalseReg;
2241  case PPC::sub_gt:
2242  return (uint64_t)Imm1 > (uint64_t)Imm2 ? TrueReg : FalseReg;
2243  case PPC::sub_eq:
2244  return Imm1 == Imm2 ? TrueReg : FalseReg;
2245  }
2246  }
2247  return PPC::NoRegister;
2248 }
2249 
2251  unsigned OpNo,
2252  int64_t Imm) const {
2253  assert(MI.getOperand(OpNo).isReg() && "Operand must be a REG");
2254  // Replace the REG with the Immediate.
2255  unsigned InUseReg = MI.getOperand(OpNo).getReg();
2256  MI.getOperand(OpNo).ChangeToImmediate(Imm);
2257 
2258  if (empty(MI.implicit_operands()))
2259  return;
2260 
2261  // We need to make sure that the MI didn't have any implicit use
2262  // of this REG any more.
2264  int UseOpIdx = MI.findRegisterUseOperandIdx(InUseReg, false, TRI);
2265  if (UseOpIdx >= 0) {
2266  MachineOperand &MO = MI.getOperand(UseOpIdx);
2267  if (MO.isImplicit())
2268  // The operands must always be in the following order:
2269  // - explicit reg defs,
2270  // - other explicit operands (reg uses, immediates, etc.),
2271  // - implicit reg defs
2272  // - implicit reg uses
2273  // Therefore, removing the implicit operand won't change the explicit
2274  // operands layout.
2275  MI.RemoveOperand(UseOpIdx);
2276  }
2277 }
2278 
2279 // Replace an instruction with one that materializes a constant (and sets
2280 // CR0 if the original instruction was a record-form instruction).
2282  const LoadImmediateInfo &LII) const {
2283  // Remove existing operands.
2284  int OperandToKeep = LII.SetCR ? 1 : 0;
2285  for (int i = MI.getNumOperands() - 1; i > OperandToKeep; i--)
2286  MI.RemoveOperand(i);
2287 
2288  // Replace the instruction.
2289  if (LII.SetCR) {
2290  MI.setDesc(get(LII.Is64Bit ? PPC::ANDIo8 : PPC::ANDIo));
2291  // Set the immediate.
2293  .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine);
2294  return;
2295  }
2296  else
2297  MI.setDesc(get(LII.Is64Bit ? PPC::LI8 : PPC::LI));
2298 
2299  // Set the immediate.
2301  .addImm(LII.Imm);
2302 }
2303 
2304 MachineInstr *PPCInstrInfo::getForwardingDefMI(
2305  MachineInstr &MI,
2306  unsigned &OpNoForForwarding,
2307  bool &SeenIntermediateUse) const {
2308  OpNoForForwarding = ~0U;
2309  MachineInstr *DefMI = nullptr;
2312  // If we're in SSA, get the defs through the MRI. Otherwise, only look
2313  // within the basic block to see if the register is defined using an LI/LI8.
2314  if (MRI->isSSA()) {
2315  for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
2316  if (!MI.getOperand(i).isReg())
2317  continue;
2318  unsigned Reg = MI.getOperand(i).getReg();
2320  continue;
2321  unsigned TrueReg = TRI->lookThruCopyLike(Reg, MRI);
2323  DefMI = MRI->getVRegDef(TrueReg);
2324  if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8) {
2325  OpNoForForwarding = i;
2326  break;
2327  }
2328  }
2329  }
2330  } else {
2331  // Looking back through the definition for each operand could be expensive,
2332  // so exit early if this isn't an instruction that either has an immediate
2333  // form or is already an immediate form that we can handle.
2334  ImmInstrInfo III;
2335  unsigned Opc = MI.getOpcode();
2336  bool ConvertibleImmForm =
2337  Opc == PPC::CMPWI || Opc == PPC::CMPLWI ||
2338  Opc == PPC::CMPDI || Opc == PPC::CMPLDI ||
2339  Opc == PPC::ADDI || Opc == PPC::ADDI8 ||
2340  Opc == PPC::ORI || Opc == PPC::ORI8 ||
2341  Opc == PPC::XORI || Opc == PPC::XORI8 ||
2342  Opc == PPC::RLDICL || Opc == PPC::RLDICLo ||
2343  Opc == PPC::RLDICL_32 || Opc == PPC::RLDICL_32_64 ||
2344  Opc == PPC::RLWINM || Opc == PPC::RLWINMo ||
2345  Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
2346  if (!instrHasImmForm(MI, III, true) && !ConvertibleImmForm)
2347  return nullptr;
2348 
2349  // Don't convert or %X, %Y, %Y since that's just a register move.
2350  if ((Opc == PPC::OR || Opc == PPC::OR8) &&
2351  MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
2352  return nullptr;
2353  for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
2354  MachineOperand &MO = MI.getOperand(i);
2355  SeenIntermediateUse = false;
2356  if (MO.isReg() && MO.isUse() && !MO.isImplicit()) {
2358  It++;
2359  unsigned Reg = MI.getOperand(i).getReg();
2360 
2361  // Is this register defined by some form of add-immediate (including
2362  // load-immediate) within this basic block?
2363  for ( ; It != E; ++It) {
2364  if (It->modifiesRegister(Reg, &getRegisterInfo())) {
2365  switch (It->getOpcode()) {
2366  default: break;
2367  case PPC::LI:
2368  case PPC::LI8:
2369  case PPC::ADDItocL:
2370  case PPC::ADDI:
2371  case PPC::ADDI8:
2372  OpNoForForwarding = i;
2373  return &*It;
2374  }
2375  break;
2376  } else if (It->readsRegister(Reg, &getRegisterInfo()))
2377  // If we see another use of this reg between the def and the MI,
2378  // we want to flat it so the def isn't deleted.
2379  SeenIntermediateUse = true;
2380  }
2381  }
2382  }
2383  }
2384  return OpNoForForwarding == ~0U ? nullptr : DefMI;
2385 }
2386 
2387 const unsigned *PPCInstrInfo::getStoreOpcodesForSpillArray() const {
2388  static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = {
2389  // Power 8
2390  {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
2391  PPC::SPILL_CRBIT, PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX,
2392  PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb,
2393  PPC::SPILLTOVSR_ST, PPC::EVSTDD, PPC::SPESTW},
2394  // Power 9
2395  {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
2396  PPC::SPILL_CRBIT, PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32,
2397  PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb,
2398  PPC::SPILLTOVSR_ST}};
2399 
2400  return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0];
2401 }
2402 
2403 const unsigned *PPCInstrInfo::getLoadOpcodesForSpillArray() const {
2404  static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = {
2405  // Power 8
2406  {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
2407  PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX,
2408  PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
2409  PPC::SPILLTOVSR_LD, PPC::EVLDD, PPC::SPELWZ},
2410  // Power 9
2411  {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
2412  PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, PPC::DFLOADf32,
2413  PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
2414  PPC::SPILLTOVSR_LD}};
2415 
2416  return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0];
2417 }
2418 
2419 // If this instruction has an immediate form and one of its operands is a
2420 // result of a load-immediate or an add-immediate, convert it to
2421 // the immediate form if the constant is in range.
2423  MachineInstr **KilledDef) const {
2424  MachineFunction *MF = MI.getParent()->getParent();
2426  bool PostRA = !MRI->isSSA();
2427  bool SeenIntermediateUse = true;
2428  unsigned ForwardingOperand = ~0U;
2429  MachineInstr *DefMI = getForwardingDefMI(MI, ForwardingOperand,
2430  SeenIntermediateUse);
2431  if (!DefMI)
2432  return false;
2433  assert(ForwardingOperand < MI.getNumOperands() &&
2434  "The forwarding operand needs to be valid at this point");
2435  bool KillFwdDefMI = !SeenIntermediateUse &&
2436  MI.getOperand(ForwardingOperand).isKill();
2437  if (KilledDef && KillFwdDefMI)
2438  *KilledDef = DefMI;
2439 
2440  ImmInstrInfo III;
2441  bool HasImmForm = instrHasImmForm(MI, III, PostRA);
2442  // If this is a reg+reg instruction that has a reg+imm form,
2443  // and one of the operands is produced by an add-immediate,
2444  // try to convert it.
2445  if (HasImmForm && transformToImmFormFedByAdd(MI, III, ForwardingOperand,
2446  *DefMI, KillFwdDefMI))
2447  return true;
2448 
2449  if ((DefMI->getOpcode() != PPC::LI && DefMI->getOpcode() != PPC::LI8) ||
2450  !DefMI->getOperand(1).isImm())
2451  return false;
2452 
2453  int64_t Immediate = DefMI->getOperand(1).getImm();
2454  // Sign-extend to 64-bits.
2455  int64_t SExtImm = ((uint64_t)Immediate & ~0x7FFFuLL) != 0 ?
2456  (Immediate | 0xFFFFFFFFFFFF0000) : Immediate;
2457 
2458  // If this is a reg+reg instruction that has a reg+imm form,
2459  // and one of the operands is produced by LI, convert it now.
2460  if (HasImmForm)
2461  return transformToImmFormFedByLI(MI, III, ForwardingOperand, SExtImm);
2462 
2463  bool ReplaceWithLI = false;
2464  bool Is64BitLI = false;
2465  int64_t NewImm = 0;
2466  bool SetCR = false;
2467  unsigned Opc = MI.getOpcode();
2468  switch (Opc) {
2469  default: return false;
2470 
2471  // FIXME: Any branches conditional on such a comparison can be made
2472  // unconditional. At this time, this happens too infrequently to be worth
2473  // the implementation effort, but if that ever changes, we could convert
2474  // such a pattern here.
2475  case PPC::CMPWI:
2476  case PPC::CMPLWI:
2477  case PPC::CMPDI:
2478  case PPC::CMPLDI: {
2479  // Doing this post-RA would require dataflow analysis to reliably find uses
2480  // of the CR register set by the compare.
2481  if (PostRA)
2482  return false;
2483  // If a compare-immediate is fed by an immediate and is itself an input of
2484  // an ISEL (the most common case) into a COPY of the correct register.
2485  bool Changed = false;
2486  unsigned DefReg = MI.getOperand(0).getReg();
2487  int64_t Comparand = MI.getOperand(2).getImm();
2488  int64_t SExtComparand = ((uint64_t)Comparand & ~0x7FFFuLL) != 0 ?
2489  (Comparand | 0xFFFFFFFFFFFF0000) : Comparand;
2490 
2491  for (auto &CompareUseMI : MRI->use_instructions(DefReg)) {
2492  unsigned UseOpc = CompareUseMI.getOpcode();
2493  if (UseOpc != PPC::ISEL && UseOpc != PPC::ISEL8)
2494  continue;
2495  unsigned CRSubReg = CompareUseMI.getOperand(3).getSubReg();
2496  unsigned TrueReg = CompareUseMI.getOperand(1).getReg();
2497  unsigned FalseReg = CompareUseMI.getOperand(2).getReg();
2498  unsigned RegToCopy = selectReg(SExtImm, SExtComparand, Opc, TrueReg,
2499  FalseReg, CRSubReg);
2500  if (RegToCopy == PPC::NoRegister)
2501  continue;
2502  // Can't use PPC::COPY to copy PPC::ZERO[8]. Convert it to LI[8] 0.
2503  if (RegToCopy == PPC::ZERO || RegToCopy == PPC::ZERO8) {
2504  CompareUseMI.setDesc(get(UseOpc == PPC::ISEL8 ? PPC::LI8 : PPC::LI));
2505  replaceInstrOperandWithImm(CompareUseMI, 1, 0);
2506  CompareUseMI.RemoveOperand(3);
2507  CompareUseMI.RemoveOperand(2);
2508  continue;
2509  }
2510  LLVM_DEBUG(
2511  dbgs() << "Found LI -> CMPI -> ISEL, replacing with a copy.\n");
2512  LLVM_DEBUG(DefMI->dump(); MI.dump(); CompareUseMI.dump());
2513  LLVM_DEBUG(dbgs() << "Is converted to:\n");
2514  // Convert to copy and remove unneeded operands.
2515  CompareUseMI.setDesc(get(PPC::COPY));
2516  CompareUseMI.RemoveOperand(3);
2517  CompareUseMI.RemoveOperand(RegToCopy == TrueReg ? 2 : 1);
2518  CmpIselsConverted++;
2519  Changed = true;
2520  LLVM_DEBUG(CompareUseMI.dump());
2521  }
2522  if (Changed)
2523  return true;
2524  // This may end up incremented multiple times since this function is called
2525  // during a fixed-point transformation, but it is only meant to indicate the
2526  // presence of this opportunity.
2527  MissedConvertibleImmediateInstrs++;
2528  return false;
2529  }
2530 
2531  // Immediate forms - may simply be convertable to an LI.
2532  case PPC::ADDI:
2533  case PPC::ADDI8: {
2534  // Does the sum fit in a 16-bit signed field?
2535  int64_t Addend = MI.getOperand(2).getImm();
2536  if (isInt<16>(Addend + SExtImm)) {
2537  ReplaceWithLI = true;
2538  Is64BitLI = Opc == PPC::ADDI8;
2539  NewImm = Addend + SExtImm;
2540  break;
2541  }
2542  return false;
2543  }
2544  case PPC::RLDICL:
2545  case PPC::RLDICLo:
2546  case PPC::RLDICL_32:
2547  case PPC::RLDICL_32_64: {
2548  // Use APInt's rotate function.
2549  int64_t SH = MI.getOperand(2).getImm();
2550  int64_t MB = MI.getOperand(3).getImm();
2551  APInt InVal((Opc == PPC::RLDICL || Opc == PPC::RLDICLo) ?
2552  64 : 32, SExtImm, true);
2553  InVal = InVal.rotl(SH);
2554  uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
2555  InVal &= Mask;
2556  // Can't replace negative values with an LI as that will sign-extend
2557  // and not clear the left bits. If we're setting the CR bit, we will use
2558  // ANDIo which won't sign extend, so that's safe.
2559  if (isUInt<15>(InVal.getSExtValue()) ||
2560  (Opc == PPC::RLDICLo && isUInt<16>(InVal.getSExtValue()))) {
2561  ReplaceWithLI = true;
2562  Is64BitLI = Opc != PPC::RLDICL_32;
2563  NewImm = InVal.getSExtValue();
2564  SetCR = Opc == PPC::RLDICLo;
2565  break;
2566  }
2567  return false;
2568  }
2569  case PPC::RLWINM:
2570  case PPC::RLWINM8:
2571  case PPC::RLWINMo:
2572  case PPC::RLWINM8o: {
2573  int64_t SH = MI.getOperand(2).getImm();
2574  int64_t MB = MI.getOperand(3).getImm();
2575  int64_t ME = MI.getOperand(4).getImm();
2576  APInt InVal(32, SExtImm, true);
2577  InVal = InVal.rotl(SH);
2578  // Set the bits ( MB + 32 ) to ( ME + 32 ).
2579  uint64_t Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
2580  InVal &= Mask;
2581  // Can't replace negative values with an LI as that will sign-extend
2582  // and not clear the left bits. If we're setting the CR bit, we will use
2583  // ANDIo which won't sign extend, so that's safe.
2584  bool ValueFits = isUInt<15>(InVal.getSExtValue());
2585  ValueFits |= ((Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o) &&
2586  isUInt<16>(InVal.getSExtValue()));
2587  if (ValueFits) {
2588  ReplaceWithLI = true;
2589  Is64BitLI = Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
2590  NewImm = InVal.getSExtValue();
2591  SetCR = Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o;
2592  break;
2593  }
2594  return false;
2595  }
2596  case PPC::ORI:
2597  case PPC::ORI8:
2598  case PPC::XORI:
2599  case PPC::XORI8: {
2600  int64_t LogicalImm = MI.getOperand(2).getImm();
2601  int64_t Result = 0;
2602  if (Opc == PPC::ORI || Opc == PPC::ORI8)
2603  Result = LogicalImm | SExtImm;
2604  else
2605  Result = LogicalImm ^ SExtImm;
2606  if (isInt<16>(Result)) {
2607  ReplaceWithLI = true;
2608  Is64BitLI = Opc == PPC::ORI8 || Opc == PPC::XORI8;
2609  NewImm = Result;
2610  break;
2611  }
2612  return false;
2613  }
2614  }
2615 
2616  if (ReplaceWithLI) {
2617  // We need to be careful with CR-setting instructions we're replacing.
2618  if (SetCR) {
2619  // We don't know anything about uses when we're out of SSA, so only
2620  // replace if the new immediate will be reproduced.
2621  bool ImmChanged = (SExtImm & NewImm) != NewImm;
2622  if (PostRA && ImmChanged)
2623  return false;
2624 
2625  if (!PostRA) {
2626  // If the defining load-immediate has no other uses, we can just replace
2627  // the immediate with the new immediate.
2628  if (MRI->hasOneUse(DefMI->getOperand(0).getReg()))
2629  DefMI->getOperand(1).setImm(NewImm);
2630 
2631  // If we're not using the GPR result of the CR-setting instruction, we
2632  // just need to and with zero/non-zero depending on the new immediate.
2633  else if (MRI->use_empty(MI.getOperand(0).getReg())) {
2634  if (NewImm) {
2635  assert(Immediate && "Transformation converted zero to non-zero?");
2636  NewImm = Immediate;
2637  }
2638  }
2639  else if (ImmChanged)
2640  return false;
2641  }
2642  }
2643 
2644  LLVM_DEBUG(dbgs() << "Replacing instruction:\n");
2645  LLVM_DEBUG(MI.dump());
2646  LLVM_DEBUG(dbgs() << "Fed by:\n");
2647  LLVM_DEBUG(DefMI->dump());
2648  LoadImmediateInfo LII;
2649  LII.Imm = NewImm;
2650  LII.Is64Bit = Is64BitLI;
2651  LII.SetCR = SetCR;
2652  // If we're setting the CR, the original load-immediate must be kept (as an
2653  // operand to ANDIo/ANDI8o).
2654  if (KilledDef && SetCR)
2655  *KilledDef = nullptr;
2656  replaceInstrWithLI(MI, LII);
2657  LLVM_DEBUG(dbgs() << "With:\n");
2658  LLVM_DEBUG(MI.dump());
2659  return true;
2660  }
2661  return false;
2662 }
2663 
2664 static bool isVFReg(unsigned Reg) {
2665  return PPC::VFRCRegClass.contains(Reg);
2666 }
2667 
2669  ImmInstrInfo &III, bool PostRA) const {
2670  unsigned Opc = MI.getOpcode();
2671  // The vast majority of the instructions would need their operand 2 replaced
2672  // with an immediate when switching to the reg+imm form. A marked exception
2673  // are the update form loads/stores for which a constant operand 2 would need
2674  // to turn into a displacement and move operand 1 to the operand 2 position.
2675  III.ImmOpNo = 2;
2676  III.OpNoForForwarding = 2;
2677  III.ImmWidth = 16;
2678  III.ImmMustBeMultipleOf = 1;
2679  III.TruncateImmTo = 0;
2680  III.IsSummingOperands = false;
2681  switch (Opc) {
2682  default: return false;
2683  case PPC::ADD4:
2684  case PPC::ADD8:
2685  III.SignedImm = true;
2686  III.ZeroIsSpecialOrig = 0;
2687  III.ZeroIsSpecialNew = 1;
2688  III.IsCommutative = true;
2689  III.IsSummingOperands = true;
2690  III.ImmOpcode = Opc == PPC::ADD4 ? PPC::ADDI : PPC::ADDI8;
2691  break;
2692  case PPC::ADDC:
2693  case PPC::ADDC8:
2694  III.SignedImm = true;
2695  III.ZeroIsSpecialOrig = 0;
2696  III.ZeroIsSpecialNew = 0;
2697  III.IsCommutative = true;
2698  III.IsSummingOperands = true;
2699  III.ImmOpcode = Opc == PPC::ADDC ? PPC::ADDIC : PPC::ADDIC8;
2700  break;
2701  case PPC::ADDCo:
2702  III.SignedImm = true;
2703  III.ZeroIsSpecialOrig = 0;
2704  III.ZeroIsSpecialNew = 0;
2705  III.IsCommutative = true;
2706  III.IsSummingOperands = true;
2707  III.ImmOpcode = PPC::ADDICo;
2708  break;
2709  case PPC::SUBFC:
2710  case PPC::SUBFC8:
2711  III.SignedImm = true;
2712  III.ZeroIsSpecialOrig = 0;
2713  III.ZeroIsSpecialNew = 0;
2714  III.IsCommutative = false;
2715  III.ImmOpcode = Opc == PPC::SUBFC ? PPC::SUBFIC : PPC::SUBFIC8;
2716  break;
2717  case PPC::CMPW:
2718  case PPC::CMPD:
2719  III.SignedImm = true;
2720  III.ZeroIsSpecialOrig = 0;
2721  III.ZeroIsSpecialNew = 0;
2722  III.IsCommutative = false;
2723  III.ImmOpcode = Opc == PPC::CMPW ? PPC::CMPWI : PPC::CMPDI;
2724  break;
2725  case PPC::CMPLW:
2726  case PPC::CMPLD:
2727  III.SignedImm = false;
2728  III.ZeroIsSpecialOrig = 0;
2729  III.ZeroIsSpecialNew = 0;
2730  III.IsCommutative = false;
2731  III.ImmOpcode = Opc == PPC::CMPLW ? PPC::CMPLWI : PPC::CMPLDI;
2732  break;
2733  case PPC::ANDo:
2734  case PPC::AND8o:
2735  case PPC::OR:
2736  case PPC::OR8:
2737  case PPC::XOR:
2738  case PPC::XOR8:
2739  III.SignedImm = false;
2740  III.ZeroIsSpecialOrig = 0;
2741  III.ZeroIsSpecialNew = 0;
2742  III.IsCommutative = true;
2743  switch(Opc) {
2744  default: llvm_unreachable("Unknown opcode");
2745  case PPC::ANDo: III.ImmOpcode = PPC::ANDIo; break;
2746  case PPC::AND8o: III.ImmOpcode = PPC::ANDIo8; break;
2747  case PPC::OR: III.ImmOpcode = PPC::ORI; break;
2748  case PPC::OR8: III.ImmOpcode = PPC::ORI8; break;
2749  case PPC::XOR: III.ImmOpcode = PPC::XORI; break;
2750  case PPC::XOR8: III.ImmOpcode = PPC::XORI8; break;
2751  }
2752  break;
2753  case PPC::RLWNM:
2754  case PPC::RLWNM8:
2755  case PPC::RLWNMo:
2756  case PPC::RLWNM8o:
2757  case PPC::SLW:
2758  case PPC::SLW8:
2759  case PPC::SLWo:
2760  case PPC::SLW8o:
2761  case PPC::SRW:
2762  case PPC::SRW8:
2763  case PPC::SRWo:
2764  case PPC::SRW8o:
2765  case PPC::SRAW:
2766  case PPC::SRAWo:
2767  III.SignedImm = false;
2768  III.ZeroIsSpecialOrig = 0;
2769  III.ZeroIsSpecialNew = 0;
2770  III.IsCommutative = false;
2771  // This isn't actually true, but the instructions ignore any of the
2772  // upper bits, so any immediate loaded with an LI is acceptable.
2773  // This does not apply to shift right algebraic because a value
2774  // out of range will produce a -1/0.
2775  III.ImmWidth = 16;
2776  if (Opc == PPC::RLWNM || Opc == PPC::RLWNM8 ||
2777  Opc == PPC::RLWNMo || Opc == PPC::RLWNM8o)
2778  III.TruncateImmTo = 5;
2779  else
2780  III.TruncateImmTo = 6;
2781  switch(Opc) {
2782  default: llvm_unreachable("Unknown opcode");
2783  case PPC::RLWNM: III.ImmOpcode = PPC::RLWINM; break;
2784  case PPC::RLWNM8: III.ImmOpcode = PPC::RLWINM8; break;
2785  case PPC::RLWNMo: III.ImmOpcode = PPC::RLWINMo; break;
2786  case PPC::RLWNM8o: III.ImmOpcode = PPC::RLWINM8o; break;
2787  case PPC::SLW: III.ImmOpcode = PPC::RLWINM; break;
2788  case PPC::SLW8: III.ImmOpcode = PPC::RLWINM8; break;
2789  case PPC::SLWo: III.ImmOpcode = PPC::RLWINMo; break;
2790  case PPC::SLW8o: III.ImmOpcode = PPC::RLWINM8o; break;
2791  case PPC::SRW: III.ImmOpcode = PPC::RLWINM; break;
2792  case PPC::SRW8: III.ImmOpcode = PPC::RLWINM8; break;
2793  case PPC::SRWo: III.ImmOpcode = PPC::RLWINMo; break;
2794  case PPC::SRW8o: III.ImmOpcode = PPC::RLWINM8o; break;
2795  case PPC::SRAW:
2796  III.ImmWidth = 5;
2797  III.TruncateImmTo = 0;
2798  III.ImmOpcode = PPC::SRAWI;
2799  break;
2800  case PPC::SRAWo:
2801  III.ImmWidth = 5;
2802  III.TruncateImmTo = 0;
2803  III.ImmOpcode = PPC::SRAWIo;
2804  break;
2805  }
2806  break;
2807  case PPC::RLDCL:
2808  case PPC::RLDCLo:
2809  case PPC::RLDCR:
2810  case PPC::RLDCRo:
2811  case PPC::SLD:
2812  case PPC::SLDo:
2813  case PPC::SRD:
2814  case PPC::SRDo:
2815  case PPC::SRAD:
2816  case PPC::SRADo:
2817  III.SignedImm = false;
2818  III.ZeroIsSpecialOrig = 0;
2819  III.ZeroIsSpecialNew = 0;
2820  III.IsCommutative = false;
2821  // This isn't actually true, but the instructions ignore any of the
2822  // upper bits, so any immediate loaded with an LI is acceptable.
2823  // This does not apply to shift right algebraic because a value
2824  // out of range will produce a -1/0.
2825  III.ImmWidth = 16;
2826  if (Opc == PPC::RLDCL || Opc == PPC::RLDCLo ||
2827  Opc == PPC::RLDCR || Opc == PPC::RLDCRo)
2828  III.TruncateImmTo = 6;
2829  else
2830  III.TruncateImmTo = 7;
2831  switch(Opc) {
2832  default: llvm_unreachable("Unknown opcode");
2833  case PPC::RLDCL: III.ImmOpcode = PPC::RLDICL; break;
2834  case PPC::RLDCLo: III.ImmOpcode = PPC::RLDICLo; break;
2835  case PPC::RLDCR: III.ImmOpcode = PPC::RLDICR; break;
2836  case PPC::RLDCRo: III.ImmOpcode = PPC::RLDICRo; break;
2837  case PPC::SLD: III.ImmOpcode = PPC::RLDICR; break;
2838  case PPC::SLDo: III.ImmOpcode = PPC::RLDICRo; break;
2839  case PPC::SRD: III.ImmOpcode = PPC::RLDICL; break;
2840  case PPC::SRDo: III.ImmOpcode = PPC::RLDICLo; break;
2841  case PPC::SRAD:
2842  III.ImmWidth = 6;
2843  III.TruncateImmTo = 0;
2844  III.ImmOpcode = PPC::SRADI;
2845  break;
2846  case PPC::SRADo:
2847  III.ImmWidth = 6;
2848  III.TruncateImmTo = 0;
2849  III.ImmOpcode = PPC::SRADIo;
2850  break;
2851  }
2852  break;
2853  // Loads and stores:
2854  case PPC::LBZX:
2855  case PPC::LBZX8:
2856  case PPC::LHZX:
2857  case PPC::LHZX8:
2858  case PPC::LHAX:
2859  case PPC::LHAX8:
2860  case PPC::LWZX:
2861  case PPC::LWZX8:
2862  case PPC::LWAX:
2863  case PPC::LDX:
2864  case PPC::LFSX:
2865  case PPC::LFDX:
2866  case PPC::STBX:
2867  case PPC::STBX8:
2868  case PPC::STHX:
2869  case PPC::STHX8:
2870  case PPC::STWX:
2871  case PPC::STWX8:
2872  case PPC::STDX:
2873  case PPC::STFSX:
2874  case PPC::STFDX:
2875  III.SignedImm = true;
2876  III.ZeroIsSpecialOrig = 1;
2877  III.ZeroIsSpecialNew = 2;
2878  III.IsCommutative = true;
2879  III.IsSummingOperands = true;
2880  III.ImmOpNo = 1;
2881  III.OpNoForForwarding = 2;
2882  switch(Opc) {
2883  default: llvm_unreachable("Unknown opcode");
2884  case PPC::LBZX: III.ImmOpcode = PPC::LBZ; break;
2885  case PPC::LBZX8: III.ImmOpcode = PPC::LBZ8; break;
2886  case PPC::LHZX: III.ImmOpcode = PPC::LHZ; break;
2887  case PPC::LHZX8: III.ImmOpcode = PPC::LHZ8; break;
2888  case PPC::LHAX: III.ImmOpcode = PPC::LHA; break;
2889  case PPC::LHAX8: III.ImmOpcode = PPC::LHA8; break;
2890  case PPC::LWZX: III.ImmOpcode = PPC::LWZ; break;
2891  case PPC::LWZX8: III.ImmOpcode = PPC::LWZ8; break;
2892  case PPC::LWAX:
2893  III.ImmOpcode = PPC::LWA;
2894  III.ImmMustBeMultipleOf = 4;
2895  break;
2896  case PPC::LDX: III.ImmOpcode = PPC::LD; III.ImmMustBeMultipleOf = 4; break;
2897  case PPC::LFSX: III.ImmOpcode = PPC::LFS; break;
2898  case PPC::LFDX: III.ImmOpcode = PPC::LFD; break;
2899  case PPC::STBX: III.ImmOpcode = PPC::STB; break;
2900  case PPC::STBX8: III.ImmOpcode = PPC::STB8; break;
2901  case PPC::STHX: III.ImmOpcode = PPC::STH; break;
2902  case PPC::STHX8: III.ImmOpcode = PPC::STH8; break;
2903  case PPC::STWX: III.ImmOpcode = PPC::STW; break;
2904  case PPC::STWX8: III.ImmOpcode = PPC::STW8; break;
2905  case PPC::STDX:
2906  III.ImmOpcode = PPC::STD;
2907  III.ImmMustBeMultipleOf = 4;
2908  break;
2909  case PPC::STFSX: III.ImmOpcode = PPC::STFS; break;
2910  case PPC::STFDX: III.ImmOpcode = PPC::STFD; break;
2911  }
2912  break;
2913  case PPC::LBZUX:
2914  case PPC::LBZUX8:
2915  case PPC::LHZUX:
2916  case PPC::LHZUX8:
2917  case PPC::LHAUX:
2918  case PPC::LHAUX8:
2919  case PPC::LWZUX:
2920  case PPC::LWZUX8:
2921  case PPC::LDUX:
2922  case PPC::LFSUX:
2923  case PPC::LFDUX:
2924  case PPC::STBUX:
2925  case PPC::STBUX8:
2926  case PPC::STHUX:
2927  case PPC::STHUX8:
2928  case PPC::STWUX:
2929  case PPC::STWUX8:
2930  case PPC::STDUX:
2931  case PPC::STFSUX:
2932  case PPC::STFDUX:
2933  III.SignedImm = true;
2934  III.ZeroIsSpecialOrig = 2;
2935  III.ZeroIsSpecialNew = 3;
2936  III.IsCommutative = false;
2937  III.IsSummingOperands = true;
2938  III.ImmOpNo = 2;
2939  III.OpNoForForwarding = 3;
2940  switch(Opc) {
2941  default: llvm_unreachable("Unknown opcode");
2942  case PPC::LBZUX: III.ImmOpcode = PPC::LBZU; break;
2943  case PPC::LBZUX8: III.ImmOpcode = PPC::LBZU8; break;
2944  case PPC::LHZUX: III.ImmOpcode = PPC::LHZU; break;
2945  case PPC::LHZUX8: III.ImmOpcode = PPC::LHZU8; break;
2946  case PPC::LHAUX: III.ImmOpcode = PPC::LHAU; break;
2947  case PPC::LHAUX8: III.ImmOpcode = PPC::LHAU8; break;
2948  case PPC::LWZUX: III.ImmOpcode = PPC::LWZU; break;
2949  case PPC::LWZUX8: III.ImmOpcode = PPC::LWZU8; break;
2950  case PPC::LDUX:
2951  III.ImmOpcode = PPC::LDU;
2952  III.ImmMustBeMultipleOf = 4;
2953  break;
2954  case PPC::LFSUX: III.ImmOpcode = PPC::LFSU; break;
2955  case PPC::LFDUX: III.ImmOpcode = PPC::LFDU; break;
2956  case PPC::STBUX: III.ImmOpcode = PPC::STBU; break;
2957  case PPC::STBUX8: III.ImmOpcode = PPC::STBU8; break;
2958  case PPC::STHUX: III.ImmOpcode = PPC::STHU; break;
2959  case PPC::STHUX8: III.ImmOpcode = PPC::STHU8; break;
2960  case PPC::STWUX: III.ImmOpcode = PPC::STWU; break;
2961  case PPC::STWUX8: III.ImmOpcode = PPC::STWU8; break;
2962  case PPC::STDUX:
2963  III.ImmOpcode = PPC::STDU;
2964  III.ImmMustBeMultipleOf = 4;
2965  break;
2966  case PPC::STFSUX: III.ImmOpcode = PPC::STFSU; break;
2967  case PPC::STFDUX: III.ImmOpcode = PPC::STFDU; break;
2968  }
2969  break;
2970  // Power9 and up only. For some of these, the X-Form version has access to all
2971  // 64 VSR's whereas the D-Form only has access to the VR's. We replace those
2972  // with pseudo-ops pre-ra and for post-ra, we check that the register loaded
2973  // into or stored from is one of the VR registers.
2974  case PPC::LXVX:
2975  case PPC::LXSSPX:
2976  case PPC::LXSDX:
2977  case PPC::STXVX:
2978  case PPC::STXSSPX:
2979  case PPC::STXSDX:
2980  case PPC::XFLOADf32:
2981  case PPC::XFLOADf64:
2982  case PPC::XFSTOREf32:
2983  case PPC::XFSTOREf64:
2984  if (!Subtarget.hasP9Vector())
2985  return false;
2986  III.SignedImm = true;
2987  III.ZeroIsSpecialOrig = 1;
2988  III.ZeroIsSpecialNew = 2;
2989  III.IsCommutative = true;
2990  III.IsSummingOperands = true;
2991  III.ImmOpNo = 1;
2992  III.OpNoForForwarding = 2;
2993  III.ImmMustBeMultipleOf = 4;
2994  switch(Opc) {
2995  default: llvm_unreachable("Unknown opcode");
2996  case PPC::LXVX:
2997  III.ImmOpcode = PPC::LXV;
2998  III.ImmMustBeMultipleOf = 16;
2999  break;
3000  case PPC::LXSSPX:
3001  if (PostRA) {
3002  if (isVFReg(MI.getOperand(0).getReg()))
3003  III.ImmOpcode = PPC::LXSSP;
3004  else {
3005  III.ImmOpcode = PPC::LFS;
3006  III.ImmMustBeMultipleOf = 1;
3007  }
3008  break;
3009  }
3011  case PPC::XFLOADf32:
3012  III.ImmOpcode = PPC::DFLOADf32;
3013  break;
3014  case PPC::LXSDX:
3015  if (PostRA) {
3016  if (isVFReg(MI.getOperand(0).getReg()))
3017  III.ImmOpcode = PPC::LXSD;
3018  else {
3019  III.ImmOpcode = PPC::LFD;
3020  III.ImmMustBeMultipleOf = 1;
3021  }
3022  break;
3023  }
3025  case PPC::XFLOADf64:
3026  III.ImmOpcode = PPC::DFLOADf64;
3027  break;
3028  case PPC::STXVX:
3029  III.ImmOpcode = PPC::STXV;
3030  III.ImmMustBeMultipleOf = 16;
3031  break;
3032  case PPC::STXSSPX:
3033  if (PostRA) {
3034  if (isVFReg(MI.getOperand(0).getReg()))
3035  III.ImmOpcode = PPC::STXSSP;
3036  else {
3037  III.ImmOpcode = PPC::STFS;
3038  III.ImmMustBeMultipleOf = 1;
3039  }
3040  break;
3041  }
3043  case PPC::XFSTOREf32:
3044  III.ImmOpcode = PPC::DFSTOREf32;
3045  break;
3046  case PPC::STXSDX:
3047  if (PostRA) {
3048  if (isVFReg(MI.getOperand(0).getReg()))
3049  III.ImmOpcode = PPC::STXSD;
3050  else {
3051  III.ImmOpcode = PPC::STFD;
3052  III.ImmMustBeMultipleOf = 1;
3053  }
3054  break;
3055  }
3057  case PPC::XFSTOREf64:
3058  III.ImmOpcode = PPC::DFSTOREf64;
3059  break;
3060  }
3061  break;
3062  }
3063  return true;
3064 }
3065 
3066 // Utility function for swaping two arbitrary operands of an instruction.
3067 static void swapMIOperands(MachineInstr &MI, unsigned Op1, unsigned Op2) {
3068  assert(Op1 != Op2 && "Cannot swap operand with itself.");
3069 
3070  unsigned MaxOp = std::max(Op1, Op2);
3071  unsigned MinOp = std::min(Op1, Op2);
3072  MachineOperand MOp1 = MI.getOperand(MinOp);
3073  MachineOperand MOp2 = MI.getOperand(MaxOp);
3074  MI.RemoveOperand(std::max(Op1, Op2));
3075  MI.RemoveOperand(std::min(Op1, Op2));
3076 
3077  // If the operands we are swapping are the two at the end (the common case)
3078  // we can just remove both and add them in the opposite order.
3079  if (MaxOp - MinOp == 1 && MI.getNumOperands() == MinOp) {
3080  MI.addOperand(MOp2);
3081  MI.addOperand(MOp1);
3082  } else {
3083  // Store all operands in a temporary vector, remove them and re-add in the
3084  // right order.
3086  unsigned TotalOps = MI.getNumOperands() + 2; // We've already removed 2 ops.
3087  for (unsigned i = MI.getNumOperands() - 1; i >= MinOp; i--) {
3088  MOps.push_back(MI.getOperand(i));
3089  MI.RemoveOperand(i);
3090  }
3091  // MOp2 needs to be added next.
3092  MI.addOperand(MOp2);
3093  // Now add the rest.
3094  for (unsigned i = MI.getNumOperands(); i < TotalOps; i++) {
3095  if (i == MaxOp)
3096  MI.addOperand(MOp1);
3097  else {
3098  MI.addOperand(MOps.back());
3099  MOps.pop_back();
3100  }
3101  }
3102  }
3103 }
3104 
3105 // Check if the 'MI' that has the index OpNoForForwarding
3106 // meets the requirement described in the ImmInstrInfo.
3107 bool PPCInstrInfo::isUseMIElgibleForForwarding(MachineInstr &MI,
3108  const ImmInstrInfo &III,
3109  unsigned OpNoForForwarding
3110  ) const {
3111  // As the algorithm of checking for PPC::ZERO/PPC::ZERO8
3112  // would not work pre-RA, we can only do the check post RA.
3114  if (MRI.isSSA())
3115  return false;
3116 
3117  // Cannot do the transform if MI isn't summing the operands.
3118  if (!III.IsSummingOperands)
3119  return false;
3120 
3121  // The instruction we are trying to replace must have the ZeroIsSpecialOrig set.
3122  if (!III.ZeroIsSpecialOrig)
3123  return false;
3124 
3125  // We cannot do the transform if the operand we are trying to replace
3126  // isn't the same as the operand the instruction allows.
3127  if (OpNoForForwarding != III.OpNoForForwarding)
3128  return false;
3129 
3130  // Check if the instruction we are trying to transform really has
3131  // the special zero register as its operand.
3132  if (MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO &&
3133  MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO8)
3134  return false;
3135 
3136  // This machine instruction is convertible if it is,
3137  // 1. summing the operands.
3138  // 2. one of the operands is special zero register.
3139  // 3. the operand we are trying to replace is allowed by the MI.
3140  return true;
3141 }
3142 
3143 // Check if the DefMI is the add inst and set the ImmMO and RegMO
3144 // accordingly.
3145 bool PPCInstrInfo::isDefMIElgibleForForwarding(MachineInstr &DefMI,
3146  const ImmInstrInfo &III,
3147  MachineOperand *&ImmMO,
3148  MachineOperand *&RegMO) const {
3149  unsigned Opc = DefMI.getOpcode();
3150  if (Opc != PPC::ADDItocL && Opc != PPC::ADDI && Opc != PPC::ADDI8)
3151  return false;
3152 
3153  assert(DefMI.getNumOperands() >= 3 &&
3154  "Add inst must have at least three operands");
3155  RegMO = &DefMI.getOperand(1);
3156  ImmMO = &DefMI.getOperand(2);
3157 
3158  // This DefMI is elgible for forwarding if it is:
3159  // 1. add inst
3160  // 2. one of the operands is Imm/CPI/Global.
3161  return isAnImmediateOperand(*ImmMO);
3162 }
3163 
3164 bool PPCInstrInfo::isRegElgibleForForwarding(const MachineOperand &RegMO,
3165  const MachineInstr &DefMI,
3166  const MachineInstr &MI,
3167  bool KillDefMI
3168  ) const {
3169  // x = addi y, imm
3170  // ...
3171  // z = lfdx 0, x -> z = lfd imm(y)
3172  // The Reg "y" can be forwarded to the MI(z) only when there is no DEF
3173  // of "y" between the DEF of "x" and "z".
3174  // The query is only valid post RA.
3176  if (MRI.isSSA())
3177  return false;
3178 
3179  unsigned Reg = RegMO.getReg();
3180 
3181  // Walking the inst in reverse(MI-->DefMI) to get the last DEF of the Reg.
3184  It++;
3185  for (; It != E; ++It) {
3186  if (It->modifiesRegister(Reg, &getRegisterInfo()) && (&*It) != &DefMI)
3187  return false;
3188  // Made it to DefMI without encountering a clobber.
3189  if ((&*It) == &DefMI)
3190  break;
3191  }
3192  assert((&*It) == &DefMI && "DefMI is missing");
3193 
3194  // If DefMI also defines the register to be forwarded, we can only forward it
3195  // if DefMI is being erased.
3196  if (DefMI.modifiesRegister(Reg, &getRegisterInfo()))
3197  return KillDefMI;
3198 
3199  return true;
3200 }
3201 
3202 bool PPCInstrInfo::isImmElgibleForForwarding(const MachineOperand &ImmMO,
3203  const MachineInstr &DefMI,
3204  const ImmInstrInfo &III,
3205  int64_t &Imm) const {
3206  assert(isAnImmediateOperand(ImmMO) && "ImmMO is NOT an immediate");
3207  if (DefMI.getOpcode() == PPC::ADDItocL) {
3208  // The operand for ADDItocL is CPI, which isn't imm at compiling time,
3209  // However, we know that, it is 16-bit width, and has the alignment of 4.
3210  // Check if the instruction met the requirement.
3211  if (III.ImmMustBeMultipleOf > 4 ||
3212  III.TruncateImmTo || III.ImmWidth != 16)
3213  return false;
3214 
3215  // Going from XForm to DForm loads means that the displacement needs to be
3216  // not just an immediate but also a multiple of 4, or 16 depending on the
3217  // load. A DForm load cannot be represented if it is a multiple of say 2.
3218  // XForm loads do not have this restriction.
3219  if (ImmMO.isGlobal() &&
3220  ImmMO.getGlobal()->getAlignment() < III.ImmMustBeMultipleOf)
3221  return false;
3222 
3223  return true;
3224  }
3225 
3226  if (ImmMO.isImm()) {
3227  // It is Imm, we need to check if the Imm fit the range.
3228  int64_t Immediate = ImmMO.getImm();
3229  // Sign-extend to 64-bits.
3230  Imm = ((uint64_t)Immediate & ~0x7FFFuLL) != 0 ?
3231  (Immediate | 0xFFFFFFFFFFFF0000) : Immediate;
3232 
3233  if (Imm % III.ImmMustBeMultipleOf)
3234  return false;
3235  if (III.TruncateImmTo)
3236  Imm &= ((1 << III.TruncateImmTo) - 1);
3237  if (III.SignedImm) {
3238  APInt ActualValue(64, Imm, true);
3239  if (!ActualValue.isSignedIntN(III.ImmWidth))
3240  return false;
3241  } else {
3242  uint64_t UnsignedMax = (1 << III.ImmWidth) - 1;
3243  if ((uint64_t)Imm > UnsignedMax)
3244  return false;
3245  }
3246  }
3247  else
3248  return false;
3249 
3250  // This ImmMO is forwarded if it meets the requriement describle
3251  // in ImmInstrInfo
3252  return true;
3253 }
3254 
3255 // If an X-Form instruction is fed by an add-immediate and one of its operands
3256 // is the literal zero, attempt to forward the source of the add-immediate to
3257 // the corresponding D-Form instruction with the displacement coming from
3258 // the immediate being added.
3259 bool PPCInstrInfo::transformToImmFormFedByAdd(MachineInstr &MI,
3260  const ImmInstrInfo &III,
3261  unsigned OpNoForForwarding,
3262  MachineInstr &DefMI,
3263  bool KillDefMI) const {
3264  // RegMO ImmMO
3265  // | |
3266  // x = addi reg, imm <----- DefMI
3267  // y = op 0 , x <----- MI
3268  // |
3269  // OpNoForForwarding
3270  // Check if the MI meet the requirement described in the III.
3271  if (!isUseMIElgibleForForwarding(MI, III, OpNoForForwarding))
3272  return false;
3273 
3274  // Check if the DefMI meet the requirement
3275  // described in the III. If yes, set the ImmMO and RegMO accordingly.
3276  MachineOperand *ImmMO = nullptr;
3277  MachineOperand *RegMO = nullptr;
3278  if (!isDefMIElgibleForForwarding(DefMI, III, ImmMO, RegMO))
3279  return false;
3280  assert(ImmMO && RegMO && "Imm and Reg operand must have been set");
3281 
3282  // As we get the Imm operand now, we need to check if the ImmMO meet
3283  // the requirement described in the III. If yes set the Imm.
3284  int64_t Imm = 0;
3285  if (!isImmElgibleForForwarding(*ImmMO, DefMI, III, Imm))
3286  return false;
3287 
3288  // Check if the RegMO can be forwarded to MI.
3289  if (!isRegElgibleForForwarding(*RegMO, DefMI, MI, KillDefMI))
3290  return false;
3291 
3292  // We know that, the MI and DefMI both meet the pattern, and
3293  // the Imm also meet the requirement with the new Imm-form.
3294  // It is safe to do the transformation now.
3295  LLVM_DEBUG(dbgs() << "Replacing instruction:\n");
3296  LLVM_DEBUG(MI.dump());
3297  LLVM_DEBUG(dbgs() << "Fed by:\n");
3298  LLVM_DEBUG(DefMI.dump());
3299 
3300  // Update the base reg first.
3302  false, false,
3303  RegMO->isKill());
3304 
3305  // Then, update the imm.
3306  if (ImmMO->isImm()) {
3307  // If the ImmMO is Imm, change the operand that has ZERO to that Imm
3308  // directly.
3310  }
3311  else {
3312  // Otherwise, it is Constant Pool Index(CPI) or Global,
3313  // which is relocation in fact. We need to replace the special zero
3314  // register with ImmMO.
3315  // Before that, we need to fixup the target flags for imm.
3316  // For some reason, we miss to set the flag for the ImmMO if it is CPI.
3317  if (DefMI.getOpcode() == PPC::ADDItocL)
3319 
3320  // MI didn't have the interface such as MI.setOperand(i) though
3321  // it has MI.getOperand(i). To repalce the ZERO MachineOperand with
3322  // ImmMO, we need to remove ZERO operand and all the operands behind it,
3323  // and, add the ImmMO, then, move back all the operands behind ZERO.
3325  for (unsigned i = MI.getNumOperands() - 1; i >= III.ZeroIsSpecialOrig; i--) {
3326  MOps.push_back(MI.getOperand(i));
3327  MI.RemoveOperand(i);
3328  }
3329 
3330  // Remove the last MO in the list, which is ZERO operand in fact.
3331  MOps.pop_back();
3332  // Add the imm operand.
3333  MI.addOperand(*ImmMO);
3334  // Now add the rest back.
3335  for (auto &MO : MOps)
3336  MI.addOperand(MO);
3337  }
3338 
3339  // Update the opcode.
3340  MI.setDesc(get(III.ImmOpcode));
3341 
3342  LLVM_DEBUG(dbgs() << "With:\n");
3343  LLVM_DEBUG(MI.dump());
3344 
3345  return true;
3346 }
3347 
3348 bool PPCInstrInfo::transformToImmFormFedByLI(MachineInstr &MI,
3349  const ImmInstrInfo &III,
3350  unsigned ConstantOpNo,
3351  int64_t Imm) const {
3353  bool PostRA = !MRI.isSSA();
3354  // Exit early if we can't convert this.
3355  if ((ConstantOpNo != III.OpNoForForwarding) && !III.IsCommutative)
3356  return false;
3357  if (Imm % III.ImmMustBeMultipleOf)
3358  return false;
3359  if (III.TruncateImmTo)
3360  Imm &= ((1 << III.TruncateImmTo) - 1);
3361  if (III.SignedImm) {
3362  APInt ActualValue(64, Imm, true);
3363  if (!ActualValue.isSignedIntN(III.ImmWidth))
3364  return false;
3365  } else {
3366  uint64_t UnsignedMax = (1 << III.ImmWidth) - 1;
3367  if ((uint64_t)Imm > UnsignedMax)
3368  return false;
3369  }
3370 
3371  // If we're post-RA, the instructions don't agree on whether register zero is
3372  // special, we can transform this as long as the register operand that will
3373  // end up in the location where zero is special isn't R0.
3374  if (PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) {
3375  unsigned PosForOrigZero = III.ZeroIsSpecialOrig ? III.ZeroIsSpecialOrig :
3376  III.ZeroIsSpecialNew + 1;
3377  unsigned OrigZeroReg = MI.getOperand(PosForOrigZero).getReg();
3378  unsigned NewZeroReg = MI.getOperand(III.ZeroIsSpecialNew).getReg();
3379  // If R0 is in the operand where zero is special for the new instruction,
3380  // it is unsafe to transform if the constant operand isn't that operand.
3381  if ((NewZeroReg == PPC::R0 || NewZeroReg == PPC::X0) &&
3382  ConstantOpNo != III.ZeroIsSpecialNew)
3383  return false;
3384  if ((OrigZeroReg == PPC::R0 || OrigZeroReg == PPC::X0) &&
3385  ConstantOpNo != PosForOrigZero)
3386  return false;
3387  }
3388 
3389  unsigned Opc = MI.getOpcode();
3390  bool SpecialShift32 =
3391  Opc == PPC::SLW || Opc == PPC::SLWo || Opc == PPC::SRW || Opc == PPC::SRWo;
3392  bool SpecialShift64 =
3393  Opc == PPC::SLD || Opc == PPC::SLDo || Opc == PPC::SRD || Opc == PPC::SRDo;
3394  bool SetCR = Opc == PPC::SLWo || Opc == PPC::SRWo ||
3395  Opc == PPC::SLDo || Opc == PPC::SRDo;
3396  bool RightShift =
3397  Opc == PPC::SRW || Opc == PPC::SRWo || Opc == PPC::SRD || Opc == PPC::SRDo;
3398 
3399  MI.setDesc(get(III.ImmOpcode));
3400  if (ConstantOpNo == III.OpNoForForwarding) {
3401  // Converting shifts to immediate form is a bit tricky since they may do
3402  // one of three things:
3403  // 1. If the shift amount is between OpSize and 2*OpSize, the result is zero
3404  // 2. If the shift amount is zero, the result is unchanged (save for maybe
3405  // setting CR0)
3406  // 3. If the shift amount is in [1, OpSize), it's just a shift
3407  if (SpecialShift32 || SpecialShift64) {
3408  LoadImmediateInfo LII;
3409  LII.Imm = 0;
3410  LII.SetCR = SetCR;
3411  LII.Is64Bit = SpecialShift64;
3412  uint64_t ShAmt = Imm & (SpecialShift32 ? 0x1F : 0x3F);
3413  if (Imm & (SpecialShift32 ? 0x20 : 0x40))
3414  replaceInstrWithLI(MI, LII);
3415  // Shifts by zero don't change the value. If we don't need to set CR0,
3416  // just convert this to a COPY. Can't do this post-RA since we've already
3417  // cleaned up the copies.
3418  else if (!SetCR && ShAmt == 0 && !PostRA) {
3419  MI.RemoveOperand(2);
3420  MI.setDesc(get(PPC::COPY));
3421  } else {
3422  // The 32 bit and 64 bit instructions are quite different.
3423  if (SpecialShift32) {
3424  // Left shifts use (N, 0, 31-N), right shifts use (32-N, N, 31).
3425  uint64_t SH = RightShift ? 32 - ShAmt : ShAmt;
3426  uint64_t MB = RightShift ? ShAmt : 0;
3427  uint64_t ME = RightShift ? 31 : 31 - ShAmt;
3429  MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(MB)
3430  .addImm(ME);
3431  } else {
3432  // Left shifts use (N, 63-N), right shifts use (64-N, N).
3433  uint64_t SH = RightShift ? 64 - ShAmt : ShAmt;
3434  uint64_t ME = RightShift ? ShAmt : 63 - ShAmt;
3436  MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(ME);
3437  }
3438  }
3439  } else
3440  replaceInstrOperandWithImm(MI, ConstantOpNo, Imm);
3441  }
3442  // Convert commutative instructions (switch the operands and convert the
3443  // desired one to an immediate.
3444  else if (III.IsCommutative) {
3445  replaceInstrOperandWithImm(MI, ConstantOpNo, Imm);
3446  swapMIOperands(MI, ConstantOpNo, III.OpNoForForwarding);
3447  } else
3448  llvm_unreachable("Should have exited early!");
3449 
3450  // For instructions for which the constant register replaces a different
3451  // operand than where the immediate goes, we need to swap them.
3452  if (III.OpNoForForwarding != III.ImmOpNo)
3454 
3455  // If the special R0/X0 register index are different for original instruction
3456  // and new instruction, we need to fix up the register class in new
3457  // instruction.
3458  if (!PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) {
3459  if (III.ZeroIsSpecialNew) {
3460  // If operand at III.ZeroIsSpecialNew is physical reg(eg: ZERO/ZERO8), no
3461  // need to fix up register class.
3462  unsigned RegToModify = MI.getOperand(III.ZeroIsSpecialNew).getReg();
3463  if (TargetRegisterInfo::isVirtualRegister(RegToModify)) {
3464  const TargetRegisterClass *NewRC =
3465  MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ?
3466  &PPC::GPRC_and_GPRC_NOR0RegClass : &PPC::G8RC_and_G8RC_NOX0RegClass;
3467  MRI.setRegClass(RegToModify, NewRC);
3468  }
3469  }
3470  }
3471  return true;
3472 }
3473 
3474 const TargetRegisterClass *
3476  if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
3477  return &PPC::VSRCRegClass;
3478  return RC;
3479 }
3480 
3482  return PPC::getRecordFormOpcode(Opcode);
3483 }
3484 
3485 // This function returns true if the machine instruction
3486 // always outputs a value by sign-extending a 32 bit value,
3487 // i.e. 0 to 31-th bits are same as 32-th bit.
3488 static bool isSignExtendingOp(const MachineInstr &MI) {
3489  int Opcode = MI.getOpcode();
3490  if (Opcode == PPC::LI || Opcode == PPC::LI8 ||
3491  Opcode == PPC::LIS || Opcode == PPC::LIS8 ||
3492  Opcode == PPC::SRAW || Opcode == PPC::SRAWo ||
3493  Opcode == PPC::SRAWI || Opcode == PPC::SRAWIo ||
3494  Opcode == PPC::LWA || Opcode == PPC::LWAX ||
3495  Opcode == PPC::LWA_32 || Opcode == PPC::LWAX_32 ||
3496  Opcode == PPC::LHA || Opcode == PPC::LHAX ||
3497  Opcode == PPC::LHA8 || Opcode == PPC::LHAX8 ||
3498  Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
3499  Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
3500  Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
3501  Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
3502  Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
3503  Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 ||
3504  Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
3505  Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 ||
3506  Opcode == PPC::EXTSB || Opcode == PPC::EXTSBo ||
3507  Opcode == PPC::EXTSH || Opcode == PPC::EXTSHo ||
3508  Opcode == PPC::EXTSB8 || Opcode == PPC::EXTSH8 ||
3509  Opcode == PPC::EXTSW || Opcode == PPC::EXTSWo ||
3510  Opcode == PPC::SETB || Opcode == PPC::SETB8 ||
3511  Opcode == PPC::EXTSH8_32_64 || Opcode == PPC::EXTSW_32_64 ||
3512  Opcode == PPC::EXTSB8_32_64)
3513  return true;
3514 
3515  if (Opcode == PPC::RLDICL && MI.getOperand(3).getImm() >= 33)
3516  return true;
3517 
3518  if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
3519  Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo) &&
3520  MI.getOperand(3).getImm() > 0 &&
3521  MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
3522  return true;
3523 
3524  return false;
3525 }
3526 
3527 // This function returns true if the machine instruction
3528 // always outputs zeros in higher 32 bits.
3529 static bool isZeroExtendingOp(const MachineInstr &MI) {
3530  int Opcode = MI.getOpcode();
3531  // The 16-bit immediate is sign-extended in li/lis.
3532  // If the most significant bit is zero, all higher bits are zero.
3533  if (Opcode == PPC::LI || Opcode == PPC::LI8 ||
3534  Opcode == PPC::LIS || Opcode == PPC::LIS8) {
3535  int64_t Imm = MI.getOperand(1).getImm();
3536  if (((uint64_t)Imm & ~0x7FFFuLL) == 0)
3537  return true;
3538  }
3539 
3540  // We have some variations of rotate-and-mask instructions
3541  // that clear higher 32-bits.
3542  if ((Opcode == PPC::RLDICL || Opcode == PPC::RLDICLo ||
3543  Opcode == PPC::RLDCL || Opcode == PPC::RLDCLo ||
3544  Opcode == PPC::RLDICL_32_64) &&
3545  MI.getOperand(3).getImm() >= 32)
3546  return true;
3547 
3548  if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDICo) &&
3549  MI.getOperand(3).getImm() >= 32 &&
3550  MI.getOperand(3).getImm() <= 63 - MI.getOperand(2).getImm())
3551  return true;
3552 
3553  if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
3554  Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo ||
3555  Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) &&
3556  MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
3557  return true;
3558 
3559  // There are other instructions that clear higher 32-bits.
3560  if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZWo ||
3561  Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZWo ||
3562  Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8 ||
3563  Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZDo ||
3564  Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZDo ||
3565  Opcode == PPC::POPCNTD || Opcode == PPC::POPCNTW ||
3566  Opcode == PPC::SLW || Opcode == PPC::SLWo ||
3567  Opcode == PPC::SRW || Opcode == PPC::SRWo ||
3568  Opcode == PPC::SLW8 || Opcode == PPC::SRW8 ||
3569  Opcode == PPC::SLWI || Opcode == PPC::SLWIo ||
3570  Opcode == PPC::SRWI || Opcode == PPC::SRWIo ||
3571  Opcode == PPC::LWZ || Opcode == PPC::LWZX ||
3572  Opcode == PPC::LWZU || Opcode == PPC::LWZUX ||
3573  Opcode == PPC::LWBRX || Opcode == PPC::LHBRX ||
3574  Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
3575  Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
3576  Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
3577  Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
3578  Opcode == PPC::LWZ8 || Opcode == PPC::LWZX8 ||
3579  Opcode == PPC::LWZU8 || Opcode == PPC::LWZUX8 ||
3580  Opcode == PPC::LWBRX8 || Opcode == PPC::LHBRX8 ||
3581  Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 ||
3582  Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 ||
3583  Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
3584  Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
3585  Opcode == PPC::ANDIo || Opcode == PPC::ANDISo ||
3586  Opcode == PPC::ROTRWI || Opcode == PPC::ROTRWIo ||
3587  Opcode == PPC::EXTLWI || Opcode == PPC::EXTLWIo ||
3588  Opcode == PPC::MFVSRWZ)
3589  return true;
3590 
3591  return false;
3592 }
3593 
3594 // This function returns true if the input MachineInstr is a TOC save
3595 // instruction.
3597  if (!MI.getOperand(1).isImm() || !MI.getOperand(2).isReg())
3598  return false;
3599  unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
3600  unsigned StackOffset = MI.getOperand(1).getImm();
3601  unsigned StackReg = MI.getOperand(2).getReg();
3602  if (StackReg == PPC::X1 && StackOffset == TOCSaveOffset)
3603  return true;
3604 
3605  return false;
3606 }
3607 
3608 // We limit the max depth to track incoming values of PHIs or binary ops
3609 // (e.g. AND) to avoid excessive cost.
3610 const unsigned MAX_DEPTH = 1;
3611 
3612 bool
3614  const unsigned Depth) const {
3615  const MachineFunction *MF = MI.getParent()->getParent();
3616  const MachineRegisterInfo *MRI = &MF->getRegInfo();
3617 
3618  // If we know this instruction returns sign- or zero-extended result,
3619  // return true.
3620  if (SignExt ? isSignExtendingOp(MI):
3621  isZeroExtendingOp(MI))
3622  return true;
3623 
3624  switch (MI.getOpcode()) {
3625  case PPC::COPY: {
3626  unsigned SrcReg = MI.getOperand(1).getReg();
3627 
3628  // In both ELFv1 and v2 ABI, method parameters and the return value
3629  // are sign- or zero-extended.
3630  if (MF->getSubtarget<PPCSubtarget>().isSVR4ABI()) {
3631  const PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
3632  // We check the ZExt/SExt flags for a method parameter.
3633  if (MI.getParent()->getBasicBlock() ==
3634  &MF->getFunction().getEntryBlock()) {
3635  unsigned VReg = MI.getOperand(0).getReg();
3636  if (MF->getRegInfo().isLiveIn(VReg))
3637  return SignExt ? FuncInfo->isLiveInSExt(VReg) :
3638  FuncInfo->isLiveInZExt(VReg);
3639  }
3640 
3641  // For a method return value, we check the ZExt/SExt flags in attribute.
3642  // We assume the following code sequence for method call.
3643  // ADJCALLSTACKDOWN 32, implicit dead %r1, implicit %r1
3644  // BL8_NOP @func,...
3645  // ADJCALLSTACKUP 32, 0, implicit dead %r1, implicit %r1
3646  // %5 = COPY %x3; G8RC:%5
3647  if (SrcReg == PPC::X3) {
3648  const MachineBasicBlock *MBB = MI.getParent();
3651  if (II != MBB->instr_begin() &&
3652  (--II)->getOpcode() == PPC::ADJCALLSTACKUP) {
3653  const MachineInstr &CallMI = *(--II);
3654  if (CallMI.isCall() && CallMI.getOperand(0).isGlobal()) {
3655  const Function *CalleeFn =
3656  dyn_cast<Function>(CallMI.getOperand(0).getGlobal());
3657  if (!CalleeFn)
3658  return false;
3659  const IntegerType *IntTy =
3660  dyn_cast<IntegerType>(CalleeFn->getReturnType());
3661  const AttributeSet &Attrs =
3662  CalleeFn->getAttributes().getRetAttributes();
3663  if (IntTy && IntTy->getBitWidth() <= 32)
3664  return Attrs.hasAttribute(SignExt ? Attribute::SExt :
3665  Attribute::ZExt);
3666  }
3667  }
3668  }
3669  }
3670 
3671  // If this is a copy from another register, we recursively check source.
3673  return false;
3674  const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3675  if (SrcMI != NULL)
3676  return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
3677 
3678  return false;
3679  }
3680 
3681  case PPC::ANDIo:
3682  case PPC::ANDISo:
3683  case PPC::ORI:
3684  case PPC::ORIS:
3685  case PPC::XORI:
3686  case PPC::XORIS:
3687  case PPC::ANDIo8:
3688  case PPC::ANDISo8:
3689  case PPC::ORI8:
3690  case PPC::ORIS8:
3691  case PPC::XORI8:
3692  case PPC::XORIS8: {
3693  // logical operation with 16-bit immediate does not change the upper bits.
3694  // So, we track the operand register as we do for register copy.
3695  unsigned SrcReg = MI.getOperand(1).getReg();
3697  return false;
3698  const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3699  if (SrcMI != NULL)
3700  return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
3701 
3702  return false;
3703  }
3704 
3705  // If all incoming values are sign-/zero-extended,
3706  // the output of OR, ISEL or PHI is also sign-/zero-extended.
3707  case PPC::OR:
3708  case PPC::OR8:
3709  case PPC::ISEL:
3710  case PPC::PHI: {
3711  if (Depth >= MAX_DEPTH)
3712  return false;
3713 
3714  // The input registers for PHI are operand 1, 3, ...
3715  // The input registers for others are operand 1 and 2.
3716  unsigned E = 3, D = 1;
3717  if (MI.getOpcode() == PPC::PHI) {
3718  E = MI.getNumOperands();
3719  D = 2;
3720  }
3721 
3722  for (unsigned I = 1; I != E; I += D) {
3723  if (MI.getOperand(I).isReg()) {
3724  unsigned SrcReg = MI.getOperand(I).getReg();
3726  return false;
3727  const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3728  if (SrcMI == NULL || !isSignOrZeroExtended(*SrcMI, SignExt, Depth+1))
3729  return false;
3730  }
3731  else
3732  return false;
3733  }
3734  return true;
3735  }
3736 
3737  // If at least one of the incoming values of an AND is zero extended
3738  // then the output is also zero-extended. If both of the incoming values
3739  // are sign-extended then the output is also sign extended.
3740  case PPC::AND:
3741  case PPC::AND8: {
3742  if (Depth >= MAX_DEPTH)
3743  return false;
3744 
3745  assert(MI.getOperand(1).isReg() && MI.getOperand(2).isReg());
3746 
3747  unsigned SrcReg1 = MI.getOperand(1).getReg();
3748  unsigned SrcReg2 = MI.getOperand(2).getReg();
3749 
3750  if (!TargetRegisterInfo::isVirtualRegister(SrcReg1) ||
3752  return false;
3753 
3754  const MachineInstr *MISrc1 = MRI->getVRegDef(SrcReg1);
3755  const MachineInstr *MISrc2 = MRI->getVRegDef(SrcReg2);
3756  if (!MISrc1 || !MISrc2)
3757  return false;
3758 
3759  if(SignExt)
3760  return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) &&
3761  isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
3762  else
3763  return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) ||
3764  isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
3765  }
3766 
3767  default:
3768  break;
3769  }
3770  return false;
3771 }
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
instr_iterator instr_begin()
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:632
int getNonRecordFormOpcode(uint16_t)
MachineBasicBlock * getMBB() const
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
uint64_t ZeroIsSpecialNew
Definition: PPCInstrInfo.h:90
void setTargetFlags(unsigned F)
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
iterator begin() const
begin/end - Return all of the registers in this class.
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:222
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:382
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:523
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
static int getRecordFormOpcode(unsigned Opcode)
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned Reg
unsigned getSubReg() const
bool hasVSX() const
Definition: PPCSubtarget.h:246
static cl::opt< bool > DisableCmpOpt("disable-ppc-cmp-opt", cl::desc("Disable compare instruction optimization"), cl::Hidden)
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
uint64_t IsCommutative
Definition: PPCInstrInfo.h:92
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
uint64_t TruncateImmTo
Definition: PPCInstrInfo.h:102
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:305
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool isPseudo() const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MCInstrDesc.h:242
CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
#define R2(n)
uint64_t OpNoForForwarding
Definition: PPCInstrInfo.h:94
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
uint64_t IsSummingOperands
Definition: PPCInstrInfo.h:104
bool isSignExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always a sign-extended, i.e.
Definition: PPCInstrInfo.h:402
return AArch64::GPR64RegClass contains(Reg)
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling th...
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
bool instrHasImmForm(const MachineInstr &MI, ImmInstrInfo &III, bool PostRA) const
MachineFunction & MF
Machine function.
Definition: ScheduleDAG.h:560
bool isXFormMemOp(unsigned Opcode) const
Definition: PPCInstrInfo.h:191
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
PPCDispatchGroupSBHazardRecognizer - This class implements a scoreboard-based hazard recognizer for P...
A description of a memory reference used in the backend.
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:450
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:411
static Optional< unsigned > getOpcode(ArrayRef< VPValue *> Values)
Returns the opcode of Values or ~0 if they do not all agree.
Definition: VPlanSLP.cpp:196
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:648
AttributeSet getRetAttributes() const
The attributes for the ret value are returned.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
const TargetRegisterClass * updatedRC(const TargetRegisterClass *RC) const
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const override
uint64_t ZeroIsSpecialOrig
Definition: PPCInstrInfo.h:87
const char * getSymbolName() const
static bool isZeroExtendingOp(const MachineInstr &MI)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:668
static void swapMIOperands(MachineInstr &MI, unsigned Op1, unsigned Op2)
void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo, int64_t Imm) const
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
bool isTOCSaveMI(const MachineInstr &MI) const
defusechain_iterator - This class provides iterator support for machine operands in the function that...
PPCInstrInfo(PPCSubtarget &STI)
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1574
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:405
CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based loops.
bool hasP9Vector() const
Definition: PPCSubtarget.h:250
static bool isVFReg(unsigned Reg)
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const override
MO_NLP_HIDDEN_FLAG - If this bit is set, the symbol reference is to a symbol with hidden visibility...
Definition: PPC.h:91
virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns) const
Return true when there is potentially a faster code sequence for an instruction chain ending in Root...
CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
Itinerary data supplied by a subtarget to be used by a target.
const PPCTargetMachine & getTargetMachine() const
Definition: PPCSubtarget.h:192
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:223
unsigned getAlignment() const
Definition: Globals.cpp:96
constexpr char Attrs[]
Key for Kernel::Metadata::mAttrs.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
unsigned getBitWidth() const
Get the number of bits in this IntegerType.
Definition: DerivedTypes.h:65
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
reverse_iterator rend()
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:656
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
unsigned getKillRegState(bool B)
bool hasAttribute(Attribute::AttrKind Kind) const
Return true if the attribute exists in this set.
Definition: Attributes.cpp:577
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
unsigned getDeadRegState(bool B)
VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
const BasicBlock & getEntryBlock() const
Definition: Function.h:639
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:576
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, const unsigned PhiDepth) const
Type * getReturnType() const
Returns the type of the ret val.
Definition: Function.h:168
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:545
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static unsigned selectReg(int64_t Imm1, int64_t Imm2, unsigned CompareOpc, unsigned TrueReg, unsigned FalseReg, unsigned CRSubReg)
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
unsigned const MachineRegisterInfo * MRI
bool isLiveInSExt(unsigned VReg) const
This function returns true if the specified vreg is a live-in register and sign-extended.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
int getAltVSXFMAOpcode(uint16_t Opcode)
Simple binary floating point operators.
Definition: ISDOpcodes.h:282
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void clearRegisterDeads(unsigned Reg)
Clear all dead flags on operands defining register Reg.
MachineInstrBuilder & UseMI
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
MO_NLP_FLAG - If this bit is set, the symbol reference is actually to the non_lazy_ptr for the global...
Definition: PPC.h:86
const GlobalValue * getGlobal() const
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:30
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:173
STFIWX - The STFIWX instruction.
use_instr_iterator use_instr_begin(unsigned RegNo) const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
void setImm(int64_t immVal)
bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point load which sign-extends from a 32-bit inte...
MI-level patchpoint operands.
Definition: StackMaps.h:76
Class to represent integer types.
Definition: DerivedTypes.h:39
PPCHazardRecognizer970 - This class defines a finite state automata that models the dispatch logic on...
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
unsigned getStoreOpcodeForSpill(unsigned Reg, const TargetRegisterClass *RC=nullptr) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
size_t size() const
Definition: SmallVector.h:52
auto find(R &&Range, const T &Val) -> decltype(adl_begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1206
unsigned getPredicateHint(Predicate Opcode)
Return the hint bits of the predicate.
Definition: PPCPredicates.h:82
unsigned getDarwinDirective() const
getDarwinDirective - Returns the -m directive specified for the cpu.
Definition: PPCSubtarget.h:171
static unsigned getCRFromCRBit(unsigned SrcReg)
MO_TLS - Indicates that the operand being accessed is some kind of thread-local symbol.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
unsigned first
void setIsKill(bool Val=true)
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
The next are not flags but distinct values.
Definition: PPC.h:94
constexpr bool empty(const T &RangeOrContainer)
Test whether RangeOrContainer is empty. Similar to C++17 std::empty.
Definition: STLExtras.h:209
The memory access writes data.
static bool MBBDefinesCTR(MachineBasicBlock &MBB)
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:187
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given stackmap should emit.
Definition: StackMaps.h:50
Predicate getPredicate(unsigned Condition, unsigned Hint)
Return predicate consisting of specified condition and hint bits.
Definition: PPCPredicates.h:87
Iterator for intrusive lists based on ilist_node.
void setOpcode(unsigned Op)
Definition: MCInst.h:170
bool isUnpredicatedTerminator(const MachineInstr &MI) const override
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
void getNoop(MCInst &NopInst) const override
Return the noop instruction to use for a noop.
static unsigned getCRBitValue(unsigned CRBit)
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1043
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
static cl::opt< bool > VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy", cl::desc("Causes the backend to crash instead of generating a nop VSX copy"), cl::Hidden)
static cl::opt< bool > UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden, cl::desc("Use the old (incorrect) instruction latency calculation"))
APInt rotl(unsigned rotateAmt) const
Rotate left by rotateAmt.
Definition: APInt.cpp:994
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
int64_t getImm() const
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const Function & getFunction() const
Return the LLVM function that this machine code represents.
virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Class for arbitrary precision integers.
Definition: APInt.h:69
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
QVGPCI = This corresponds to the QPX qvgpci instruction.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
iterator_range< mop_iterator > implicit_operands()
Definition: MachineInstr.h:472
bool use_empty(unsigned RegNo) const
use_empty - Return true if there are no instructions using the specified register.
On a symbol operand, this represents the lo part.
Definition: AVRInstrInfo.h:52
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:253
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
TargetSubtargetInfo - Generic base class for all target subtargets.
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in <Root...
bool isPredicated(const MachineInstr &MI) const override
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
bool isLiveIn(unsigned Reg) const
Representation of each machine instruction.
Definition: MachineInstr.h:63
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Predicate InvertPredicate(Predicate Opcode)
Invert the specified predicate. != -> ==, < -> >=.
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:386
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
bool hasOneUse(unsigned RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MI-level stackmap operands.
Definition: StackMaps.h:35
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
TargetOptions Options
Definition: TargetMachine.h:96
static bool isSignExtendingOp(const MachineInstr &MI)
void setReg(unsigned Reg)
Change the register this operand corresponds to.
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned getLoadOpcodeForSpill(unsigned Reg, const TargetRegisterClass *RC=nullptr) const
void setSubReg(unsigned subReg)
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:322
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given patchpoint should emit.
Definition: StackMaps.h:104
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:558
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:345
bool isSignedIntN(unsigned N) const
Check if this APInt has an N-bits signed integer value.
Definition: APInt.h:455
const unsigned MAX_DEPTH
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator_range< use_instr_iterator > use_instructions(unsigned Reg) const
uint64_t ImmMustBeMultipleOf
Definition: PPCInstrInfo.h:84
unsigned getPredicateCondition(Predicate Opcode)
Return the condition without hint bits.
Definition: PPCPredicates.h:77
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
bool isLiveInZExt(unsigned VReg) const
This function returns true if the specified vreg is a live-in register and zero-extended.
LLVM Value Representation.
Definition: Value.h:72
static use_instr_iterator use_instr_end()
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:250
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when ...
IRTranslator LLVM IR MI
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:639
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
bool isPredicable(const MachineInstr &MI) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool isSVR4ABI() const
Definition: PPCSubtarget.h:311
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:66
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
On a symbol operand "FOO", this indicates that the reference is actually to "FOO@plt".
Definition: PPC.h:78
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: PPCInstrInfo.h:189
virtual unsigned lookThruCopyLike(unsigned SrcReg, const MachineRegisterInfo *MRI) const
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:317
static cl::opt< bool > DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden, cl::desc("Disable analysis for CTR loops"))
int findRegisterUseOperandIdx(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found...
Instructions::const_iterator const_instr_iterator
GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point load which zero-extends from a 32-bit inte...
SpillOpcodeKey
MO_PIC_FLAG - If this bit is set, the symbol reference is relative to the function&#39;s picbase...
Definition: PPC.h:82
bool convertToImmediateForm(MachineInstr &MI, MachineInstr **KilledDef=nullptr) const
static bool isAnImmediateOperand(const MachineOperand &MO)
bool expandPostRAPseudo(MachineInstr &MI) const override
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:143
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:172
bool expandVSXMemPseudo(MachineInstr &MI) const
bool isImplicit() const
bool isZeroExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always zero-extended, i.e.
Definition: PPCInstrInfo.h:408
Predicate getSwappedPredicate(Predicate Opcode)
Assume the condition register is set by MI(a,b), return the predicate if we modify the instructions s...