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PPCInstrInfo.cpp
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1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCInstrInfo.h"
16 #include "PPC.h"
17 #include "PPCHazardRecognizers.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCTargetMachine.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Statistic.h"
32 #include "llvm/CodeGen/StackMaps.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCInst.h"
36 #include "llvm/Support/Debug.h"
40 
41 using namespace llvm;
42 
43 #define DEBUG_TYPE "ppc-instr-info"
44 
45 #define GET_INSTRMAP_INFO
46 #define GET_INSTRINFO_CTOR_DTOR
47 #include "PPCGenInstrInfo.inc"
48 
49 STATISTIC(NumStoreSPILLVSRRCAsVec,
50  "Number of spillvsrrc spilled to stack as vec");
51 STATISTIC(NumStoreSPILLVSRRCAsGpr,
52  "Number of spillvsrrc spilled to stack as gpr");
53 STATISTIC(NumGPRtoVSRSpill, "Number of gpr spills to spillvsrrc");
54 
55 static cl::
56 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
57  cl::desc("Disable analysis for CTR loops"));
58 
59 static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
60 cl::desc("Disable compare instruction optimization"), cl::Hidden);
61 
62 static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
63 cl::desc("Causes the backend to crash instead of generating a nop VSX copy"),
64 cl::Hidden);
65 
66 static cl::opt<bool>
67 UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
68  cl::desc("Use the old (incorrect) instruction latency calculation"));
69 
70 // Pin the vtable to this file.
71 void PPCInstrInfo::anchor() {}
72 
74  : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP,
75  /* CatchRetOpcode */ -1,
76  STI.isPPC64() ? PPC::BLR8 : PPC::BLR),
77  Subtarget(STI), RI(STI.getTargetMachine()) {}
78 
79 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
80 /// this target when scheduling the DAG.
83  const ScheduleDAG *DAG) const {
84  unsigned Directive =
85  static_cast<const PPCSubtarget *>(STI)->getDarwinDirective();
86  if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
87  Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
88  const InstrItineraryData *II =
89  static_cast<const PPCSubtarget *>(STI)->getInstrItineraryData();
90  return new ScoreboardHazardRecognizer(II, DAG);
91  }
92 
94 }
95 
96 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
97 /// to use for this target when scheduling the DAG.
100  const ScheduleDAG *DAG) const {
101  unsigned Directive =
102  DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
103 
104  // FIXME: Leaving this as-is until we have POWER9 scheduling info
105  if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8)
106  return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
107 
108  // Most subtargets use a PPC970 recognizer.
109  if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
110  Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
111  assert(DAG->TII && "No InstrInfo?");
112 
113  return new PPCHazardRecognizer970(*DAG);
114  }
115 
116  return new ScoreboardHazardRecognizer(II, DAG);
117 }
118 
120  const MachineInstr &MI,
121  unsigned *PredCost) const {
122  if (!ItinData || UseOldLatencyCalc)
123  return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
124 
125  // The default implementation of getInstrLatency calls getStageLatency, but
126  // getStageLatency does not do the right thing for us. While we have
127  // itinerary, most cores are fully pipelined, and so the itineraries only
128  // express the first part of the pipeline, not every stage. Instead, we need
129  // to use the listed output operand cycle number (using operand 0 here, which
130  // is an output).
131 
132  unsigned Latency = 1;
133  unsigned DefClass = MI.getDesc().getSchedClass();
134  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
135  const MachineOperand &MO = MI.getOperand(i);
136  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
137  continue;
138 
139  int Cycle = ItinData->getOperandCycle(DefClass, i);
140  if (Cycle < 0)
141  continue;
142 
143  Latency = std::max(Latency, (unsigned) Cycle);
144  }
145 
146  return Latency;
147 }
148 
150  const MachineInstr &DefMI, unsigned DefIdx,
151  const MachineInstr &UseMI,
152  unsigned UseIdx) const {
153  int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
154  UseMI, UseIdx);
155 
156  if (!DefMI.getParent())
157  return Latency;
158 
159  const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
160  unsigned Reg = DefMO.getReg();
161 
162  bool IsRegCR;
164  const MachineRegisterInfo *MRI =
165  &DefMI.getParent()->getParent()->getRegInfo();
166  IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
167  MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
168  } else {
169  IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
170  PPC::CRBITRCRegClass.contains(Reg);
171  }
172 
173  if (UseMI.isBranch() && IsRegCR) {
174  if (Latency < 0)
175  Latency = getInstrLatency(ItinData, DefMI);
176 
177  // On some cores, there is an additional delay between writing to a condition
178  // register, and using it from a branch.
179  unsigned Directive = Subtarget.getDarwinDirective();
180  switch (Directive) {
181  default: break;
182  case PPC::DIR_7400:
183  case PPC::DIR_750:
184  case PPC::DIR_970:
185  case PPC::DIR_E5500:
186  case PPC::DIR_PWR4:
187  case PPC::DIR_PWR5:
188  case PPC::DIR_PWR5X:
189  case PPC::DIR_PWR6:
190  case PPC::DIR_PWR6X:
191  case PPC::DIR_PWR7:
192  case PPC::DIR_PWR8:
193  // FIXME: Is this needed for POWER9?
194  Latency += 2;
195  break;
196  }
197  }
198 
199  return Latency;
200 }
201 
202 // This function does not list all associative and commutative operations, but
203 // only those worth feeding through the machine combiner in an attempt to
204 // reduce the critical path. Mostly, this means floating-point operations,
205 // because they have high latencies (compared to other operations, such and
206 // and/or, which are also associative and commutative, but have low latencies).
208  switch (Inst.getOpcode()) {
209  // FP Add:
210  case PPC::FADD:
211  case PPC::FADDS:
212  // FP Multiply:
213  case PPC::FMUL:
214  case PPC::FMULS:
215  // Altivec Add:
216  case PPC::VADDFP:
217  // VSX Add:
218  case PPC::XSADDDP:
219  case PPC::XVADDDP:
220  case PPC::XVADDSP:
221  case PPC::XSADDSP:
222  // VSX Multiply:
223  case PPC::XSMULDP:
224  case PPC::XVMULDP:
225  case PPC::XVMULSP:
226  case PPC::XSMULSP:
227  // QPX Add:
228  case PPC::QVFADD:
229  case PPC::QVFADDS:
230  case PPC::QVFADDSs:
231  // QPX Multiply:
232  case PPC::QVFMUL:
233  case PPC::QVFMULS:
234  case PPC::QVFMULSs:
235  return true;
236  default:
237  return false;
238  }
239 }
240 
242  MachineInstr &Root,
243  SmallVectorImpl<MachineCombinerPattern> &Patterns) const {
244  // Using the machine combiner in this way is potentially expensive, so
245  // restrict to when aggressive optimizations are desired.
247  return false;
248 
249  // FP reassociation is only legal when we don't need strict IEEE semantics.
251  return false;
252 
253  return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns);
254 }
255 
256 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
258  unsigned &SrcReg, unsigned &DstReg,
259  unsigned &SubIdx) const {
260  switch (MI.getOpcode()) {
261  default: return false;
262  case PPC::EXTSW:
263  case PPC::EXTSW_32:
264  case PPC::EXTSW_32_64:
265  SrcReg = MI.getOperand(1).getReg();
266  DstReg = MI.getOperand(0).getReg();
267  SubIdx = PPC::sub_32;
268  return true;
269  }
270 }
271 
273  int &FrameIndex) const {
274  // Note: This list must be kept consistent with LoadRegFromStackSlot.
275  switch (MI.getOpcode()) {
276  default: break;
277  case PPC::LD:
278  case PPC::LWZ:
279  case PPC::LFS:
280  case PPC::LFD:
281  case PPC::RESTORE_CR:
282  case PPC::RESTORE_CRBIT:
283  case PPC::LVX:
284  case PPC::LXVD2X:
285  case PPC::LXV:
286  case PPC::QVLFDX:
287  case PPC::QVLFSXs:
288  case PPC::QVLFDXb:
289  case PPC::RESTORE_VRSAVE:
290  case PPC::SPILLTOVSR_LD:
291  // Check for the operands added by addFrameReference (the immediate is the
292  // offset which defaults to 0).
293  if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
294  MI.getOperand(2).isFI()) {
295  FrameIndex = MI.getOperand(2).getIndex();
296  return MI.getOperand(0).getReg();
297  }
298  break;
299  }
300  return 0;
301 }
302 
303 // For opcodes with the ReMaterializable flag set, this function is called to
304 // verify the instruction is really rematable.
306  AliasAnalysis *AA) const {
307  switch (MI.getOpcode()) {
308  default:
309  // This function should only be called for opcodes with the ReMaterializable
310  // flag set.
311  llvm_unreachable("Unknown rematerializable operation!");
312  break;
313  case PPC::LI:
314  case PPC::LI8:
315  case PPC::LIS:
316  case PPC::LIS8:
317  case PPC::QVGPCI:
318  case PPC::ADDIStocHA:
319  case PPC::ADDItocL:
320  case PPC::LOAD_STACK_GUARD:
321  return true;
322  }
323  return false;
324 }
325 
327  int &FrameIndex) const {
328  // Note: This list must be kept consistent with StoreRegToStackSlot.
329  switch (MI.getOpcode()) {
330  default: break;
331  case PPC::STD:
332  case PPC::STW:
333  case PPC::STFS:
334  case PPC::STFD:
335  case PPC::SPILL_CR:
336  case PPC::SPILL_CRBIT:
337  case PPC::STVX:
338  case PPC::STXVD2X:
339  case PPC::STXV:
340  case PPC::QVSTFDX:
341  case PPC::QVSTFSXs:
342  case PPC::QVSTFDXb:
343  case PPC::SPILL_VRSAVE:
344  case PPC::SPILLTOVSR_ST:
345  // Check for the operands added by addFrameReference (the immediate is the
346  // offset which defaults to 0).
347  if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
348  MI.getOperand(2).isFI()) {
349  FrameIndex = MI.getOperand(2).getIndex();
350  return MI.getOperand(0).getReg();
351  }
352  break;
353  }
354  return 0;
355 }
356 
358  unsigned OpIdx1,
359  unsigned OpIdx2) const {
360  MachineFunction &MF = *MI.getParent()->getParent();
361 
362  // Normal instructions can be commuted the obvious way.
363  if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMIo)
364  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
365  // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
366  // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
367  // changing the relative order of the mask operands might change what happens
368  // to the high-bits of the mask (and, thus, the result).
369 
370  // Cannot commute if it has a non-zero rotate count.
371  if (MI.getOperand(3).getImm() != 0)
372  return nullptr;
373 
374  // If we have a zero rotate count, we have:
375  // M = mask(MB,ME)
376  // Op0 = (Op1 & ~M) | (Op2 & M)
377  // Change this to:
378  // M = mask((ME+1)&31, (MB-1)&31)
379  // Op0 = (Op2 & ~M) | (Op1 & M)
380 
381  // Swap op1/op2
382  assert(((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) &&
383  "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo.");
384  unsigned Reg0 = MI.getOperand(0).getReg();
385  unsigned Reg1 = MI.getOperand(1).getReg();
386  unsigned Reg2 = MI.getOperand(2).getReg();
387  unsigned SubReg1 = MI.getOperand(1).getSubReg();
388  unsigned SubReg2 = MI.getOperand(2).getSubReg();
389  bool Reg1IsKill = MI.getOperand(1).isKill();
390  bool Reg2IsKill = MI.getOperand(2).isKill();
391  bool ChangeReg0 = false;
392  // If machine instrs are no longer in two-address forms, update
393  // destination register as well.
394  if (Reg0 == Reg1) {
395  // Must be two address instruction!
397  "Expecting a two-address instruction!");
398  assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
399  Reg2IsKill = false;
400  ChangeReg0 = true;
401  }
402 
403  // Masks.
404  unsigned MB = MI.getOperand(4).getImm();
405  unsigned ME = MI.getOperand(5).getImm();
406 
407  // We can't commute a trivial mask (there is no way to represent an all-zero
408  // mask).
409  if (MB == 0 && ME == 31)
410  return nullptr;
411 
412  if (NewMI) {
413  // Create a new instruction.
414  unsigned Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg();
415  bool Reg0IsDead = MI.getOperand(0).isDead();
416  return BuildMI(MF, MI.getDebugLoc(), MI.getDesc())
417  .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
418  .addReg(Reg2, getKillRegState(Reg2IsKill))
419  .addReg(Reg1, getKillRegState(Reg1IsKill))
420  .addImm((ME + 1) & 31)
421  .addImm((MB - 1) & 31);
422  }
423 
424  if (ChangeReg0) {
425  MI.getOperand(0).setReg(Reg2);
426  MI.getOperand(0).setSubReg(SubReg2);
427  }
428  MI.getOperand(2).setReg(Reg1);
429  MI.getOperand(1).setReg(Reg2);
430  MI.getOperand(2).setSubReg(SubReg1);
431  MI.getOperand(1).setSubReg(SubReg2);
432  MI.getOperand(2).setIsKill(Reg1IsKill);
433  MI.getOperand(1).setIsKill(Reg2IsKill);
434 
435  // Swap the mask around.
436  MI.getOperand(4).setImm((ME + 1) & 31);
437  MI.getOperand(5).setImm((MB - 1) & 31);
438  return &MI;
439 }
440 
442  unsigned &SrcOpIdx2) const {
443  // For VSX A-Type FMA instructions, it is the first two operands that can be
444  // commuted, however, because the non-encoded tied input operand is listed
445  // first, the operands to swap are actually the second and third.
446 
447  int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode());
448  if (AltOpc == -1)
449  return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
450 
451  // The commutable operand indices are 2 and 3. Return them in SrcOpIdx1
452  // and SrcOpIdx2.
453  return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
454 }
455 
458  // This function is used for scheduling, and the nop wanted here is the type
459  // that terminates dispatch groups on the POWER cores.
460  unsigned Directive = Subtarget.getDarwinDirective();
461  unsigned Opcode;
462  switch (Directive) {
463  default: Opcode = PPC::NOP; break;
464  case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
465  case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
466  case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */
467  // FIXME: Update when POWER9 scheduling model is ready.
468  case PPC::DIR_PWR9: Opcode = PPC::NOP_GT_PWR7; break;
469  }
470 
471  DebugLoc DL;
472  BuildMI(MBB, MI, DL, get(Opcode));
473 }
474 
475 /// Return the noop instruction to use for a noop.
476 void PPCInstrInfo::getNoop(MCInst &NopInst) const {
477  NopInst.setOpcode(PPC::NOP);
478 }
479 
480 // Branch analysis.
481 // Note: If the condition register is set to CTR or CTR8 then this is a
482 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
484  MachineBasicBlock *&TBB,
485  MachineBasicBlock *&FBB,
487  bool AllowModify) const {
488  bool isPPC64 = Subtarget.isPPC64();
489 
490  // If the block has no terminators, it just falls into the block after it.
492  if (I == MBB.end())
493  return false;
494 
495  if (!isUnpredicatedTerminator(*I))
496  return false;
497 
498  if (AllowModify) {
499  // If the BB ends with an unconditional branch to the fallthrough BB,
500  // we eliminate the branch instruction.
501  if (I->getOpcode() == PPC::B &&
502  MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
503  I->eraseFromParent();
504 
505  // We update iterator after deleting the last branch.
506  I = MBB.getLastNonDebugInstr();
507  if (I == MBB.end() || !isUnpredicatedTerminator(*I))
508  return false;
509  }
510  }
511 
512  // Get the last instruction in the block.
513  MachineInstr &LastInst = *I;
514 
515  // If there is only one terminator instruction, process it.
516  if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
517  if (LastInst.getOpcode() == PPC::B) {
518  if (!LastInst.getOperand(0).isMBB())
519  return true;
520  TBB = LastInst.getOperand(0).getMBB();
521  return false;
522  } else if (LastInst.getOpcode() == PPC::BCC) {
523  if (!LastInst.getOperand(2).isMBB())
524  return true;
525  // Block ends with fall-through condbranch.
526  TBB = LastInst.getOperand(2).getMBB();
527  Cond.push_back(LastInst.getOperand(0));
528  Cond.push_back(LastInst.getOperand(1));
529  return false;
530  } else if (LastInst.getOpcode() == PPC::BC) {
531  if (!LastInst.getOperand(1).isMBB())
532  return true;
533  // Block ends with fall-through condbranch.
534  TBB = LastInst.getOperand(1).getMBB();
536  Cond.push_back(LastInst.getOperand(0));
537  return false;
538  } else if (LastInst.getOpcode() == PPC::BCn) {
539  if (!LastInst.getOperand(1).isMBB())
540  return true;
541  // Block ends with fall-through condbranch.
542  TBB = LastInst.getOperand(1).getMBB();
544  Cond.push_back(LastInst.getOperand(0));
545  return false;
546  } else if (LastInst.getOpcode() == PPC::BDNZ8 ||
547  LastInst.getOpcode() == PPC::BDNZ) {
548  if (!LastInst.getOperand(0).isMBB())
549  return true;
550  if (DisableCTRLoopAnal)
551  return true;
552  TBB = LastInst.getOperand(0).getMBB();
554  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
555  true));
556  return false;
557  } else if (LastInst.getOpcode() == PPC::BDZ8 ||
558  LastInst.getOpcode() == PPC::BDZ) {
559  if (!LastInst.getOperand(0).isMBB())
560  return true;
561  if (DisableCTRLoopAnal)
562  return true;
563  TBB = LastInst.getOperand(0).getMBB();
565  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
566  true));
567  return false;
568  }
569 
570  // Otherwise, don't know what this is.
571  return true;
572  }
573 
574  // Get the instruction before it if it's a terminator.
575  MachineInstr &SecondLastInst = *I;
576 
577  // If there are three terminators, we don't know what sort of block this is.
578  if (I != MBB.begin() && isUnpredicatedTerminator(*--I))
579  return true;
580 
581  // If the block ends with PPC::B and PPC:BCC, handle it.
582  if (SecondLastInst.getOpcode() == PPC::BCC &&
583  LastInst.getOpcode() == PPC::B) {
584  if (!SecondLastInst.getOperand(2).isMBB() ||
585  !LastInst.getOperand(0).isMBB())
586  return true;
587  TBB = SecondLastInst.getOperand(2).getMBB();
588  Cond.push_back(SecondLastInst.getOperand(0));
589  Cond.push_back(SecondLastInst.getOperand(1));
590  FBB = LastInst.getOperand(0).getMBB();
591  return false;
592  } else if (SecondLastInst.getOpcode() == PPC::BC &&
593  LastInst.getOpcode() == PPC::B) {
594  if (!SecondLastInst.getOperand(1).isMBB() ||
595  !LastInst.getOperand(0).isMBB())
596  return true;
597  TBB = SecondLastInst.getOperand(1).getMBB();
599  Cond.push_back(SecondLastInst.getOperand(0));
600  FBB = LastInst.getOperand(0).getMBB();
601  return false;
602  } else if (SecondLastInst.getOpcode() == PPC::BCn &&
603  LastInst.getOpcode() == PPC::B) {
604  if (!SecondLastInst.getOperand(1).isMBB() ||
605  !LastInst.getOperand(0).isMBB())
606  return true;
607  TBB = SecondLastInst.getOperand(1).getMBB();
609  Cond.push_back(SecondLastInst.getOperand(0));
610  FBB = LastInst.getOperand(0).getMBB();
611  return false;
612  } else if ((SecondLastInst.getOpcode() == PPC::BDNZ8 ||
613  SecondLastInst.getOpcode() == PPC::BDNZ) &&
614  LastInst.getOpcode() == PPC::B) {
615  if (!SecondLastInst.getOperand(0).isMBB() ||
616  !LastInst.getOperand(0).isMBB())
617  return true;
618  if (DisableCTRLoopAnal)
619  return true;
620  TBB = SecondLastInst.getOperand(0).getMBB();
622  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
623  true));
624  FBB = LastInst.getOperand(0).getMBB();
625  return false;
626  } else if ((SecondLastInst.getOpcode() == PPC::BDZ8 ||
627  SecondLastInst.getOpcode() == PPC::BDZ) &&
628  LastInst.getOpcode() == PPC::B) {
629  if (!SecondLastInst.getOperand(0).isMBB() ||
630  !LastInst.getOperand(0).isMBB())
631  return true;
632  if (DisableCTRLoopAnal)
633  return true;
634  TBB = SecondLastInst.getOperand(0).getMBB();
636  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
637  true));
638  FBB = LastInst.getOperand(0).getMBB();
639  return false;
640  }
641 
642  // If the block ends with two PPC:Bs, handle it. The second one is not
643  // executed, so remove it.
644  if (SecondLastInst.getOpcode() == PPC::B && LastInst.getOpcode() == PPC::B) {
645  if (!SecondLastInst.getOperand(0).isMBB())
646  return true;
647  TBB = SecondLastInst.getOperand(0).getMBB();
648  I = LastInst;
649  if (AllowModify)
650  I->eraseFromParent();
651  return false;
652  }
653 
654  // Otherwise, can't handle this.
655  return true;
656 }
657 
659  int *BytesRemoved) const {
660  assert(!BytesRemoved && "code size not handled");
661 
663  if (I == MBB.end())
664  return 0;
665 
666  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
667  I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
668  I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
669  I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
670  return 0;
671 
672  // Remove the branch.
673  I->eraseFromParent();
674 
675  I = MBB.end();
676 
677  if (I == MBB.begin()) return 1;
678  --I;
679  if (I->getOpcode() != PPC::BCC &&
680  I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
681  I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
682  I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
683  return 1;
684 
685  // Remove the branch.
686  I->eraseFromParent();
687  return 2;
688 }
689 
691  MachineBasicBlock *TBB,
692  MachineBasicBlock *FBB,
694  const DebugLoc &DL,
695  int *BytesAdded) const {
696  // Shouldn't be a fall through.
697  assert(TBB && "insertBranch must not be told to insert a fallthrough");
698  assert((Cond.size() == 2 || Cond.size() == 0) &&
699  "PPC branch conditions have two components!");
700  assert(!BytesAdded && "code size not handled");
701 
702  bool isPPC64 = Subtarget.isPPC64();
703 
704  // One-way branch.
705  if (!FBB) {
706  if (Cond.empty()) // Unconditional branch
707  BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
708  else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
709  BuildMI(&MBB, DL, get(Cond[0].getImm() ?
710  (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
711  (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
712  else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
713  BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
714  else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
715  BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
716  else // Conditional branch
717  BuildMI(&MBB, DL, get(PPC::BCC))
718  .addImm(Cond[0].getImm())
719  .add(Cond[1])
720  .addMBB(TBB);
721  return 1;
722  }
723 
724  // Two-way Conditional Branch.
725  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
726  BuildMI(&MBB, DL, get(Cond[0].getImm() ?
727  (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
728  (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
729  else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
730  BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
731  else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
732  BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
733  else
734  BuildMI(&MBB, DL, get(PPC::BCC))
735  .addImm(Cond[0].getImm())
736  .add(Cond[1])
737  .addMBB(TBB);
738  BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
739  return 2;
740 }
741 
742 // Select analysis.
745  unsigned TrueReg, unsigned FalseReg,
746  int &CondCycles, int &TrueCycles, int &FalseCycles) const {
747  if (Cond.size() != 2)
748  return false;
749 
750  // If this is really a bdnz-like condition, then it cannot be turned into a
751  // select.
752  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
753  return false;
754 
755  // Check register classes.
756  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
757  const TargetRegisterClass *RC =
758  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
759  if (!RC)
760  return false;
761 
762  // isel is for regular integer GPRs only.
763  if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
764  !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
765  !PPC::G8RCRegClass.hasSubClassEq(RC) &&
766  !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
767  return false;
768 
769  // FIXME: These numbers are for the A2, how well they work for other cores is
770  // an open question. On the A2, the isel instruction has a 2-cycle latency
771  // but single-cycle throughput. These numbers are used in combination with
772  // the MispredictPenalty setting from the active SchedMachineModel.
773  CondCycles = 1;
774  TrueCycles = 1;
775  FalseCycles = 1;
776 
777  return true;
778 }
779 
782  const DebugLoc &dl, unsigned DestReg,
783  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
784  unsigned FalseReg) const {
785  assert(Cond.size() == 2 &&
786  "PPC branch conditions have two components!");
787 
788  // Get the register classes.
790  const TargetRegisterClass *RC =
791  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
792  assert(RC && "TrueReg and FalseReg must have overlapping register classes");
793 
794  bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
795  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
796  assert((Is64Bit ||
797  PPC::GPRCRegClass.hasSubClassEq(RC) ||
798  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
799  "isel is for regular integer GPRs only");
800 
801  unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
802  auto SelectPred = static_cast<PPC::Predicate>(Cond[0].getImm());
803 
804  unsigned SubIdx = 0;
805  bool SwapOps = false;
806  switch (SelectPred) {
807  case PPC::PRED_EQ:
808  case PPC::PRED_EQ_MINUS:
809  case PPC::PRED_EQ_PLUS:
810  SubIdx = PPC::sub_eq; SwapOps = false; break;
811  case PPC::PRED_NE:
812  case PPC::PRED_NE_MINUS:
813  case PPC::PRED_NE_PLUS:
814  SubIdx = PPC::sub_eq; SwapOps = true; break;
815  case PPC::PRED_LT:
816  case PPC::PRED_LT_MINUS:
817  case PPC::PRED_LT_PLUS:
818  SubIdx = PPC::sub_lt; SwapOps = false; break;
819  case PPC::PRED_GE:
820  case PPC::PRED_GE_MINUS:
821  case PPC::PRED_GE_PLUS:
822  SubIdx = PPC::sub_lt; SwapOps = true; break;
823  case PPC::PRED_GT:
824  case PPC::PRED_GT_MINUS:
825  case PPC::PRED_GT_PLUS:
826  SubIdx = PPC::sub_gt; SwapOps = false; break;
827  case PPC::PRED_LE:
828  case PPC::PRED_LE_MINUS:
829  case PPC::PRED_LE_PLUS:
830  SubIdx = PPC::sub_gt; SwapOps = true; break;
831  case PPC::PRED_UN:
832  case PPC::PRED_UN_MINUS:
833  case PPC::PRED_UN_PLUS:
834  SubIdx = PPC::sub_un; SwapOps = false; break;
835  case PPC::PRED_NU:
836  case PPC::PRED_NU_MINUS:
837  case PPC::PRED_NU_PLUS:
838  SubIdx = PPC::sub_un; SwapOps = true; break;
839  case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break;
840  case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break;
841  }
842 
843  unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
844  SecondReg = SwapOps ? TrueReg : FalseReg;
845 
846  // The first input register of isel cannot be r0. If it is a member
847  // of a register class that can be r0, then copy it first (the
848  // register allocator should eliminate the copy).
849  if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
850  MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
851  const TargetRegisterClass *FirstRC =
852  MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
853  &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
854  unsigned OldFirstReg = FirstReg;
855  FirstReg = MRI.createVirtualRegister(FirstRC);
856  BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
857  .addReg(OldFirstReg);
858  }
859 
860  BuildMI(MBB, MI, dl, get(OpCode), DestReg)
861  .addReg(FirstReg).addReg(SecondReg)
862  .addReg(Cond[1].getReg(), 0, SubIdx);
863 }
864 
865 static unsigned getCRBitValue(unsigned CRBit) {
866  unsigned Ret = 4;
867  if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT ||
868  CRBit == PPC::CR2LT || CRBit == PPC::CR3LT ||
869  CRBit == PPC::CR4LT || CRBit == PPC::CR5LT ||
870  CRBit == PPC::CR6LT || CRBit == PPC::CR7LT)
871  Ret = 3;
872  if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT ||
873  CRBit == PPC::CR2GT || CRBit == PPC::CR3GT ||
874  CRBit == PPC::CR4GT || CRBit == PPC::CR5GT ||
875  CRBit == PPC::CR6GT || CRBit == PPC::CR7GT)
876  Ret = 2;
877  if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ ||
878  CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ ||
879  CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ ||
880  CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ)
881  Ret = 1;
882  if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN ||
883  CRBit == PPC::CR2UN || CRBit == PPC::CR3UN ||
884  CRBit == PPC::CR4UN || CRBit == PPC::CR5UN ||
885  CRBit == PPC::CR6UN || CRBit == PPC::CR7UN)
886  Ret = 0;
887 
888  assert(Ret != 4 && "Invalid CR bit register");
889  return Ret;
890 }
891 
894  const DebugLoc &DL, unsigned DestReg,
895  unsigned SrcReg, bool KillSrc) const {
896  // We can end up with self copies and similar things as a result of VSX copy
897  // legalization. Promote them here.
898  const TargetRegisterInfo *TRI = &getRegisterInfo();
899  if (PPC::F8RCRegClass.contains(DestReg) &&
900  PPC::VSRCRegClass.contains(SrcReg)) {
901  unsigned SuperReg =
902  TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
903 
904  if (VSXSelfCopyCrash && SrcReg == SuperReg)
905  llvm_unreachable("nop VSX copy");
906 
907  DestReg = SuperReg;
908  } else if (PPC::F8RCRegClass.contains(SrcReg) &&
909  PPC::VSRCRegClass.contains(DestReg)) {
910  unsigned SuperReg =
911  TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
912 
913  if (VSXSelfCopyCrash && DestReg == SuperReg)
914  llvm_unreachable("nop VSX copy");
915 
916  SrcReg = SuperReg;
917  }
918 
919  // Different class register copy
920  if (PPC::CRBITRCRegClass.contains(SrcReg) &&
921  PPC::GPRCRegClass.contains(DestReg)) {
922  unsigned CRReg = getCRFromCRBit(SrcReg);
923  BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg);
924  getKillRegState(KillSrc);
925  // Rotate the CR bit in the CR fields to be the least significant bit and
926  // then mask with 0x1 (MB = ME = 31).
927  BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
928  .addReg(DestReg, RegState::Kill)
929  .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
930  .addImm(31)
931  .addImm(31);
932  return;
933  } else if (PPC::CRRCRegClass.contains(SrcReg) &&
934  PPC::G8RCRegClass.contains(DestReg)) {
935  BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg).addReg(SrcReg);
936  getKillRegState(KillSrc);
937  return;
938  } else if (PPC::CRRCRegClass.contains(SrcReg) &&
939  PPC::GPRCRegClass.contains(DestReg)) {
940  BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(SrcReg);
941  getKillRegState(KillSrc);
942  return;
943  } else if (PPC::G8RCRegClass.contains(SrcReg) &&
944  PPC::VSFRCRegClass.contains(DestReg)) {
945  BuildMI(MBB, I, DL, get(PPC::MTVSRD), DestReg).addReg(SrcReg);
946  NumGPRtoVSRSpill++;
947  getKillRegState(KillSrc);
948  return;
949  } else if (PPC::VSFRCRegClass.contains(SrcReg) &&
950  PPC::G8RCRegClass.contains(DestReg)) {
951  BuildMI(MBB, I, DL, get(PPC::MFVSRD), DestReg).addReg(SrcReg);
952  getKillRegState(KillSrc);
953  return;
954  }
955 
956  unsigned Opc;
957  if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
958  Opc = PPC::OR;
959  else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
960  Opc = PPC::OR8;
961  else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
962  Opc = PPC::FMR;
963  else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
964  Opc = PPC::MCRF;
965  else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
966  Opc = PPC::VOR;
967  else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
968  // There are two different ways this can be done:
969  // 1. xxlor : This has lower latency (on the P7), 2 cycles, but can only
970  // issue in VSU pipeline 0.
971  // 2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
972  // can go to either pipeline.
973  // We'll always use xxlor here, because in practically all cases where
974  // copies are generated, they are close enough to some use that the
975  // lower-latency form is preferable.
976  Opc = PPC::XXLOR;
977  else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) ||
978  PPC::VSSRCRegClass.contains(DestReg, SrcReg))
979  Opc = PPC::XXLORf;
980  else if (PPC::QFRCRegClass.contains(DestReg, SrcReg))
981  Opc = PPC::QVFMR;
982  else if (PPC::QSRCRegClass.contains(DestReg, SrcReg))
983  Opc = PPC::QVFMRs;
984  else if (PPC::QBRCRegClass.contains(DestReg, SrcReg))
985  Opc = PPC::QVFMRb;
986  else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
987  Opc = PPC::CROR;
988  else
989  llvm_unreachable("Impossible reg-to-reg copy");
990 
991  const MCInstrDesc &MCID = get(Opc);
992  if (MCID.getNumOperands() == 3)
993  BuildMI(MBB, I, DL, MCID, DestReg)
994  .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
995  else
996  BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
997 }
998 
999 // This function returns true if a CR spill is necessary and false otherwise.
1000 bool
1001 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
1002  unsigned SrcReg, bool isKill,
1003  int FrameIdx,
1004  const TargetRegisterClass *RC,
1006  bool &NonRI, bool &SpillsVRS) const{
1007  // Note: If additional store instructions are added here,
1008  // update isStoreToStackSlot.
1009 
1010  DebugLoc DL;
1011  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1012  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1013  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
1014  .addReg(SrcReg,
1015  getKillRegState(isKill)),
1016  FrameIdx));
1017  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1018  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1019  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
1020  .addReg(SrcReg,
1021  getKillRegState(isKill)),
1022  FrameIdx));
1023  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1024  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
1025  .addReg(SrcReg,
1026  getKillRegState(isKill)),
1027  FrameIdx));
1028  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1029  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
1030  .addReg(SrcReg,
1031  getKillRegState(isKill)),
1032  FrameIdx));
1033  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1034  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
1035  .addReg(SrcReg,
1036  getKillRegState(isKill)),
1037  FrameIdx));
1038  return true;
1039  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1040  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CRBIT))
1041  .addReg(SrcReg,
1042  getKillRegState(isKill)),
1043  FrameIdx));
1044  return true;
1045  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1046  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX))
1047  .addReg(SrcReg,
1048  getKillRegState(isKill)),
1049  FrameIdx));
1050  NonRI = true;
1051  } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1052  unsigned Op = Subtarget.hasP9Vector() ? PPC::STXV : PPC::STXVD2X;
1053  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Op))
1054  .addReg(SrcReg,
1055  getKillRegState(isKill)),
1056  FrameIdx));
1057  NonRI = true;
1058  } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1059  unsigned Opc = Subtarget.hasP9Vector() ? PPC::DFSTOREf64 : PPC::STXSDX;
1060  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opc))
1061  .addReg(SrcReg,
1062  getKillRegState(isKill)),
1063  FrameIdx));
1064  NonRI = true;
1065  } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1066  unsigned Opc = Subtarget.hasP9Vector() ? PPC::DFSTOREf32 : PPC::STXSSPX;
1067  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opc))
1068  .addReg(SrcReg,
1069  getKillRegState(isKill)),
1070  FrameIdx));
1071  NonRI = true;
1072  } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1073  assert(Subtarget.isDarwin() &&
1074  "VRSAVE only needs spill/restore on Darwin");
1075  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE))
1076  .addReg(SrcReg,
1077  getKillRegState(isKill)),
1078  FrameIdx));
1079  SpillsVRS = true;
1080  } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1081  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDX))
1082  .addReg(SrcReg,
1083  getKillRegState(isKill)),
1084  FrameIdx));
1085  NonRI = true;
1086  } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1087  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFSXs))
1088  .addReg(SrcReg,
1089  getKillRegState(isKill)),
1090  FrameIdx));
1091  NonRI = true;
1092  } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1093  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDXb))
1094  .addReg(SrcReg,
1095  getKillRegState(isKill)),
1096  FrameIdx));
1097  NonRI = true;
1098  } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1099  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILLTOVSR_ST))
1100  .addReg(SrcReg,
1101  getKillRegState(isKill)),
1102  FrameIdx));
1103  } else {
1104  llvm_unreachable("Unknown regclass!");
1105  }
1106 
1107  return false;
1108 }
1109 
1110 void
1113  unsigned SrcReg, bool isKill, int FrameIdx,
1114  const TargetRegisterClass *RC,
1115  const TargetRegisterInfo *TRI) const {
1116  MachineFunction &MF = *MBB.getParent();
1118 
1119  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1120  FuncInfo->setHasSpills();
1121 
1122  // We need to avoid a situation in which the value from a VRRC register is
1123  // spilled using an Altivec instruction and reloaded into a VSRC register
1124  // using a VSX instruction. The issue with this is that the VSX
1125  // load/store instructions swap the doublewords in the vector and the Altivec
1126  // ones don't. The register classes on the spill/reload may be different if
1127  // the register is defined using an Altivec instruction and is then used by a
1128  // VSX instruction.
1129  RC = updatedRC(RC);
1130 
1131  bool NonRI = false, SpillsVRS = false;
1132  if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs,
1133  NonRI, SpillsVRS))
1134  FuncInfo->setSpillsCR();
1135 
1136  if (SpillsVRS)
1137  FuncInfo->setSpillsVRSAVE();
1138 
1139  if (NonRI)
1140  FuncInfo->setHasNonRISpills();
1141 
1142  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1143  MBB.insert(MI, NewMIs[i]);
1144 
1145  const MachineFrameInfo &MFI = MF.getFrameInfo();
1147  MachinePointerInfo::getFixedStack(MF, FrameIdx),
1149  MFI.getObjectAlignment(FrameIdx));
1150  NewMIs.back()->addMemOperand(MF, MMO);
1151 }
1152 
1153 bool PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
1154  unsigned DestReg, int FrameIdx,
1155  const TargetRegisterClass *RC,
1157  bool &NonRI, bool &SpillsVRS) const {
1158  // Note: If additional load instructions are added here,
1159  // update isLoadFromStackSlot.
1160 
1161  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1162  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1163  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
1164  DestReg), FrameIdx));
1165  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1166  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1167  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
1168  FrameIdx));
1169  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1170  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
1171  FrameIdx));
1172  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1173  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
1174  FrameIdx));
1175  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1176  NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1177  get(PPC::RESTORE_CR), DestReg),
1178  FrameIdx));
1179  return true;
1180  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1181  NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1182  get(PPC::RESTORE_CRBIT), DestReg),
1183  FrameIdx));
1184  return true;
1185  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1186  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LVX), DestReg),
1187  FrameIdx));
1188  NonRI = true;
1189  } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1190  unsigned Op = Subtarget.hasP9Vector() ? PPC::LXV : PPC::LXVD2X;
1191  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Op), DestReg),
1192  FrameIdx));
1193  NonRI = true;
1194  } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1195  unsigned Opc = Subtarget.hasP9Vector() ? PPC::DFLOADf64 : PPC::LXSDX;
1196  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opc),
1197  DestReg), FrameIdx));
1198  NonRI = true;
1199  } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1200  unsigned Opc = Subtarget.hasP9Vector() ? PPC::DFLOADf32 : PPC::LXSSPX;
1201  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opc),
1202  DestReg), FrameIdx));
1203  NonRI = true;
1204  } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1205  assert(Subtarget.isDarwin() &&
1206  "VRSAVE only needs spill/restore on Darwin");
1207  NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1208  get(PPC::RESTORE_VRSAVE),
1209  DestReg),
1210  FrameIdx));
1211  SpillsVRS = true;
1212  } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1213  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFDX), DestReg),
1214  FrameIdx));
1215  NonRI = true;
1216  } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1217  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFSXs), DestReg),
1218  FrameIdx));
1219  NonRI = true;
1220  } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1221  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFDXb), DestReg),
1222  FrameIdx));
1223  NonRI = true;
1224  } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1225  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILLTOVSR_LD),
1226  DestReg), FrameIdx));
1227  } else {
1228  llvm_unreachable("Unknown regclass!");
1229  }
1230 
1231  return false;
1232 }
1233 
1234 void
1237  unsigned DestReg, int FrameIdx,
1238  const TargetRegisterClass *RC,
1239  const TargetRegisterInfo *TRI) const {
1240  MachineFunction &MF = *MBB.getParent();
1242  DebugLoc DL;
1243  if (MI != MBB.end()) DL = MI->getDebugLoc();
1244 
1245  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1246  FuncInfo->setHasSpills();
1247 
1248  // We need to avoid a situation in which the value from a VRRC register is
1249  // spilled using an Altivec instruction and reloaded into a VSRC register
1250  // using a VSX instruction. The issue with this is that the VSX
1251  // load/store instructions swap the doublewords in the vector and the Altivec
1252  // ones don't. The register classes on the spill/reload may be different if
1253  // the register is defined using an Altivec instruction and is then used by a
1254  // VSX instruction.
1255  if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
1256  RC = &PPC::VSRCRegClass;
1257 
1258  bool NonRI = false, SpillsVRS = false;
1259  if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs,
1260  NonRI, SpillsVRS))
1261  FuncInfo->setSpillsCR();
1262 
1263  if (SpillsVRS)
1264  FuncInfo->setSpillsVRSAVE();
1265 
1266  if (NonRI)
1267  FuncInfo->setHasNonRISpills();
1268 
1269  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1270  MBB.insert(MI, NewMIs[i]);
1271 
1272  const MachineFrameInfo &MFI = MF.getFrameInfo();
1274  MachinePointerInfo::getFixedStack(MF, FrameIdx),
1276  MFI.getObjectAlignment(FrameIdx));
1277  NewMIs.back()->addMemOperand(MF, MMO);
1278 }
1279 
1280 bool PPCInstrInfo::
1282  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
1283  if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
1284  Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
1285  else
1286  // Leave the CR# the same, but invert the condition.
1287  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
1288  return false;
1289 }
1290 
1292  unsigned Reg, MachineRegisterInfo *MRI) const {
1293  // For some instructions, it is legal to fold ZERO into the RA register field.
1294  // A zero immediate should always be loaded with a single li.
1295  unsigned DefOpc = DefMI.getOpcode();
1296  if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
1297  return false;
1298  if (!DefMI.getOperand(1).isImm())
1299  return false;
1300  if (DefMI.getOperand(1).getImm() != 0)
1301  return false;
1302 
1303  // Note that we cannot here invert the arguments of an isel in order to fold
1304  // a ZERO into what is presented as the second argument. All we have here
1305  // is the condition bit, and that might come from a CR-logical bit operation.
1306 
1307  const MCInstrDesc &UseMCID = UseMI.getDesc();
1308 
1309  // Only fold into real machine instructions.
1310  if (UseMCID.isPseudo())
1311  return false;
1312 
1313  unsigned UseIdx;
1314  for (UseIdx = 0; UseIdx < UseMI.getNumOperands(); ++UseIdx)
1315  if (UseMI.getOperand(UseIdx).isReg() &&
1316  UseMI.getOperand(UseIdx).getReg() == Reg)
1317  break;
1318 
1319  assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI");
1320  assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
1321 
1322  const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
1323 
1324  // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
1325  // register (which might also be specified as a pointer class kind).
1326  if (UseInfo->isLookupPtrRegClass()) {
1327  if (UseInfo->RegClass /* Kind */ != 1)
1328  return false;
1329  } else {
1330  if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
1331  UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
1332  return false;
1333  }
1334 
1335  // Make sure this is not tied to an output register (or otherwise
1336  // constrained). This is true for ST?UX registers, for example, which
1337  // are tied to their output registers.
1338  if (UseInfo->Constraints != 0)
1339  return false;
1340 
1341  unsigned ZeroReg;
1342  if (UseInfo->isLookupPtrRegClass()) {
1343  bool isPPC64 = Subtarget.isPPC64();
1344  ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
1345  } else {
1346  ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
1347  PPC::ZERO8 : PPC::ZERO;
1348  }
1349 
1350  bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1351  UseMI.getOperand(UseIdx).setReg(ZeroReg);
1352 
1353  if (DeleteDef)
1354  DefMI.eraseFromParent();
1355 
1356  return true;
1357 }
1358 
1360  for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
1361  I != IE; ++I)
1362  if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
1363  return true;
1364  return false;
1365 }
1366 
1367 // We should make sure that, if we're going to predicate both sides of a
1368 // condition (a diamond), that both sides don't define the counter register. We
1369 // can predicate counter-decrement-based branches, but while that predicates
1370 // the branching, it does not predicate the counter decrement. If we tried to
1371 // merge the triangle into one predicated block, we'd decrement the counter
1372 // twice.
1374  unsigned NumT, unsigned ExtraT,
1375  MachineBasicBlock &FMBB,
1376  unsigned NumF, unsigned ExtraF,
1377  BranchProbability Probability) const {
1378  return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
1379 }
1380 
1381 
1383  // The predicated branches are identified by their type, not really by the
1384  // explicit presence of a predicate. Furthermore, some of them can be
1385  // predicated more than once. Because if conversion won't try to predicate
1386  // any instruction which already claims to be predicated (by returning true
1387  // here), always return false. In doing so, we let isPredicable() be the
1388  // final word on whether not the instruction can be (further) predicated.
1389 
1390  return false;
1391 }
1392 
1394  if (!MI.isTerminator())
1395  return false;
1396 
1397  // Conditional branch is a special case.
1398  if (MI.isBranch() && !MI.isBarrier())
1399  return true;
1400 
1401  return !isPredicated(MI);
1402 }
1403 
1405  ArrayRef<MachineOperand> Pred) const {
1406  unsigned OpC = MI.getOpcode();
1407  if (OpC == PPC::BLR || OpC == PPC::BLR8) {
1408  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1409  bool isPPC64 = Subtarget.isPPC64();
1410  MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR)
1411  : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
1412  } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1413  MI.setDesc(get(PPC::BCLR));
1415  .addReg(Pred[1].getReg());
1416  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1417  MI.setDesc(get(PPC::BCLRn));
1419  .addReg(Pred[1].getReg());
1420  } else {
1421  MI.setDesc(get(PPC::BCCLR));
1423  .addImm(Pred[0].getImm())
1424  .addReg(Pred[1].getReg());
1425  }
1426 
1427  return true;
1428  } else if (OpC == PPC::B) {
1429  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1430  bool isPPC64 = Subtarget.isPPC64();
1431  MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
1432  : (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
1433  } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1434  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1435  MI.RemoveOperand(0);
1436 
1437  MI.setDesc(get(PPC::BC));
1439  .addReg(Pred[1].getReg())
1440  .addMBB(MBB);
1441  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1442  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1443  MI.RemoveOperand(0);
1444 
1445  MI.setDesc(get(PPC::BCn));
1447  .addReg(Pred[1].getReg())
1448  .addMBB(MBB);
1449  } else {
1450  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1451  MI.RemoveOperand(0);
1452 
1453  MI.setDesc(get(PPC::BCC));
1455  .addImm(Pred[0].getImm())
1456  .addReg(Pred[1].getReg())
1457  .addMBB(MBB);
1458  }
1459 
1460  return true;
1461  } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 ||
1462  OpC == PPC::BCTRL || OpC == PPC::BCTRL8) {
1463  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
1464  llvm_unreachable("Cannot predicate bctr[l] on the ctr register");
1465 
1466  bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
1467  bool isPPC64 = Subtarget.isPPC64();
1468 
1469  if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1470  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8)
1471  : (setLR ? PPC::BCCTRL : PPC::BCCTR)));
1473  .addReg(Pred[1].getReg());
1474  return true;
1475  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1476  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n)
1477  : (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
1479  .addReg(Pred[1].getReg());
1480  return true;
1481  }
1482 
1483  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8)
1484  : (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
1486  .addImm(Pred[0].getImm())
1487  .addReg(Pred[1].getReg());
1488  return true;
1489  }
1490 
1491  return false;
1492 }
1493 
1495  ArrayRef<MachineOperand> Pred2) const {
1496  assert(Pred1.size() == 2 && "Invalid PPC first predicate");
1497  assert(Pred2.size() == 2 && "Invalid PPC second predicate");
1498 
1499  if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1500  return false;
1501  if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
1502  return false;
1503 
1504  // P1 can only subsume P2 if they test the same condition register.
1505  if (Pred1[1].getReg() != Pred2[1].getReg())
1506  return false;
1507 
1508  PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
1509  PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
1510 
1511  if (P1 == P2)
1512  return true;
1513 
1514  // Does P1 subsume P2, e.g. GE subsumes GT.
1515  if (P1 == PPC::PRED_LE &&
1516  (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
1517  return true;
1518  if (P1 == PPC::PRED_GE &&
1519  (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
1520  return true;
1521 
1522  return false;
1523 }
1524 
1526  std::vector<MachineOperand> &Pred) const {
1527  // Note: At the present time, the contents of Pred from this function is
1528  // unused by IfConversion. This implementation follows ARM by pushing the
1529  // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
1530  // predicate, instructions defining CTR or CTR8 are also included as
1531  // predicate-defining instructions.
1532 
1533  const TargetRegisterClass *RCs[] =
1534  { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1535  &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1536 
1537  bool Found = false;
1538  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1539  const MachineOperand &MO = MI.getOperand(i);
1540  for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
1541  const TargetRegisterClass *RC = RCs[c];
1542  if (MO.isReg()) {
1543  if (MO.isDef() && RC->contains(MO.getReg())) {
1544  Pred.push_back(MO);
1545  Found = true;
1546  }
1547  } else if (MO.isRegMask()) {
1548  for (TargetRegisterClass::iterator I = RC->begin(),
1549  IE = RC->end(); I != IE; ++I)
1550  if (MO.clobbersPhysReg(*I)) {
1551  Pred.push_back(MO);
1552  Found = true;
1553  }
1554  }
1555  }
1556  }
1557 
1558  return Found;
1559 }
1560 
1562  unsigned OpC = MI.getOpcode();
1563  switch (OpC) {
1564  default:
1565  return false;
1566  case PPC::B:
1567  case PPC::BLR:
1568  case PPC::BLR8:
1569  case PPC::BCTR:
1570  case PPC::BCTR8:
1571  case PPC::BCTRL:
1572  case PPC::BCTRL8:
1573  return true;
1574  }
1575 }
1576 
1577 bool PPCInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1578  unsigned &SrcReg2, int &Mask,
1579  int &Value) const {
1580  unsigned Opc = MI.getOpcode();
1581 
1582  switch (Opc) {
1583  default: return false;
1584  case PPC::CMPWI:
1585  case PPC::CMPLWI:
1586  case PPC::CMPDI:
1587  case PPC::CMPLDI:
1588  SrcReg = MI.getOperand(1).getReg();
1589  SrcReg2 = 0;
1590  Value = MI.getOperand(2).getImm();
1591  Mask = 0xFFFF;
1592  return true;
1593  case PPC::CMPW:
1594  case PPC::CMPLW:
1595  case PPC::CMPD:
1596  case PPC::CMPLD:
1597  case PPC::FCMPUS:
1598  case PPC::FCMPUD:
1599  SrcReg = MI.getOperand(1).getReg();
1600  SrcReg2 = MI.getOperand(2).getReg();
1601  Value = 0;
1602  Mask = 0;
1603  return true;
1604  }
1605 }
1606 
1607 bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1608  unsigned SrcReg2, int Mask, int Value,
1609  const MachineRegisterInfo *MRI) const {
1610  if (DisableCmpOpt)
1611  return false;
1612 
1613  int OpC = CmpInstr.getOpcode();
1614  unsigned CRReg = CmpInstr.getOperand(0).getReg();
1615 
1616  // FP record forms set CR1 based on the execption status bits, not a
1617  // comparison with zero.
1618  if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
1619  return false;
1620 
1621  // The record forms set the condition register based on a signed comparison
1622  // with zero (so says the ISA manual). This is not as straightforward as it
1623  // seems, however, because this is always a 64-bit comparison on PPC64, even
1624  // for instructions that are 32-bit in nature (like slw for example).
1625  // So, on PPC32, for unsigned comparisons, we can use the record forms only
1626  // for equality checks (as those don't depend on the sign). On PPC64,
1627  // we are restricted to equality for unsigned 64-bit comparisons and for
1628  // signed 32-bit comparisons the applicability is more restricted.
1629  bool isPPC64 = Subtarget.isPPC64();
1630  bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
1631  bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
1632  bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
1633 
1634  // Get the unique definition of SrcReg.
1635  MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1636  if (!MI) return false;
1637 
1638  bool equalityOnly = false;
1639  bool noSub = false;
1640  if (isPPC64) {
1641  if (is32BitSignedCompare) {
1642  // We can perform this optimization only if MI is sign-extending.
1643  if (isSignExtended(*MI))
1644  noSub = true;
1645  else
1646  return false;
1647  } else if (is32BitUnsignedCompare) {
1648  // We can perform this optimization, equality only, if MI is
1649  // zero-extending.
1650  if (isZeroExtended(*MI)) {
1651  noSub = true;
1652  equalityOnly = true;
1653  } else
1654  return false;
1655  } else
1656  equalityOnly = is64BitUnsignedCompare;
1657  } else
1658  equalityOnly = is32BitUnsignedCompare;
1659 
1660  if (equalityOnly) {
1661  // We need to check the uses of the condition register in order to reject
1662  // non-equality comparisons.
1664  I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1665  I != IE; ++I) {
1666  MachineInstr *UseMI = &*I;
1667  if (UseMI->getOpcode() == PPC::BCC) {
1668  PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
1669  unsigned PredCond = PPC::getPredicateCondition(Pred);
1670  // We ignore hint bits when checking for non-equality comparisons.
1671  if (PredCond != PPC::PRED_EQ && PredCond != PPC::PRED_NE)
1672  return false;
1673  } else if (UseMI->getOpcode() == PPC::ISEL ||
1674  UseMI->getOpcode() == PPC::ISEL8) {
1675  unsigned SubIdx = UseMI->getOperand(3).getSubReg();
1676  if (SubIdx != PPC::sub_eq)
1677  return false;
1678  } else
1679  return false;
1680  }
1681  }
1682 
1683  MachineBasicBlock::iterator I = CmpInstr;
1684 
1685  // Scan forward to find the first use of the compare.
1686  for (MachineBasicBlock::iterator EL = CmpInstr.getParent()->end(); I != EL;
1687  ++I) {
1688  bool FoundUse = false;
1690  J = MRI->use_instr_begin(CRReg), JE = MRI->use_instr_end();
1691  J != JE; ++J)
1692  if (&*J == &*I) {
1693  FoundUse = true;
1694  break;
1695  }
1696 
1697  if (FoundUse)
1698  break;
1699  }
1700 
1703 
1704  // There are two possible candidates which can be changed to set CR[01].
1705  // One is MI, the other is a SUB instruction.
1706  // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
1707  MachineInstr *Sub = nullptr;
1708  if (SrcReg2 != 0)
1709  // MI is not a candidate for CMPrr.
1710  MI = nullptr;
1711  // FIXME: Conservatively refuse to convert an instruction which isn't in the
1712  // same BB as the comparison. This is to allow the check below to avoid calls
1713  // (and other explicit clobbers); instead we should really check for these
1714  // more explicitly (in at least a few predecessors).
1715  else if (MI->getParent() != CmpInstr.getParent())
1716  return false;
1717  else if (Value != 0) {
1718  // The record-form instructions set CR bit based on signed comparison
1719  // against 0. We try to convert a compare against 1 or -1 into a compare
1720  // against 0 to exploit record-form instructions. For example, we change
1721  // the condition "greater than -1" into "greater than or equal to 0"
1722  // and "less than 1" into "less than or equal to 0".
1723 
1724  // Since we optimize comparison based on a specific branch condition,
1725  // we don't optimize if condition code is used by more than once.
1726  if (equalityOnly || !MRI->hasOneUse(CRReg))
1727  return false;
1728 
1729  MachineInstr *UseMI = &*MRI->use_instr_begin(CRReg);
1730  if (UseMI->getOpcode() != PPC::BCC)
1731  return false;
1732 
1733  PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
1734  PPC::Predicate NewPred = Pred;
1735  unsigned PredCond = PPC::getPredicateCondition(Pred);
1736  unsigned PredHint = PPC::getPredicateHint(Pred);
1737  int16_t Immed = (int16_t)Value;
1738 
1739  // When modyfing the condition in the predicate, we propagate hint bits
1740  // from the original predicate to the new one.
1741  if (Immed == -1 && PredCond == PPC::PRED_GT)
1742  // We convert "greater than -1" into "greater than or equal to 0",
1743  // since we are assuming signed comparison by !equalityOnly
1744  NewPred = PPC::getPredicate(PPC::PRED_GE, PredHint);
1745  else if (Immed == -1 && PredCond == PPC::PRED_LE)
1746  // We convert "less than or equal to -1" into "less than 0".
1747  NewPred = PPC::getPredicate(PPC::PRED_LT, PredHint);
1748  else if (Immed == 1 && PredCond == PPC::PRED_LT)
1749  // We convert "less than 1" into "less than or equal to 0".
1750  NewPred = PPC::getPredicate(PPC::PRED_LE, PredHint);
1751  else if (Immed == 1 && PredCond == PPC::PRED_GE)
1752  // We convert "greater than or equal to 1" into "greater than 0".
1753  NewPred = PPC::getPredicate(PPC::PRED_GT, PredHint);
1754  else
1755  return false;
1756 
1757  PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1758  NewPred));
1759  }
1760 
1761  // Search for Sub.
1762  const TargetRegisterInfo *TRI = &getRegisterInfo();
1763  --I;
1764 
1765  // Get ready to iterate backward from CmpInstr.
1766  MachineBasicBlock::iterator E = MI, B = CmpInstr.getParent()->begin();
1767 
1768  for (; I != E && !noSub; --I) {
1769  const MachineInstr &Instr = *I;
1770  unsigned IOpC = Instr.getOpcode();
1771 
1772  if (&*I != &CmpInstr && (Instr.modifiesRegister(PPC::CR0, TRI) ||
1773  Instr.readsRegister(PPC::CR0, TRI)))
1774  // This instruction modifies or uses the record condition register after
1775  // the one we want to change. While we could do this transformation, it
1776  // would likely not be profitable. This transformation removes one
1777  // instruction, and so even forcing RA to generate one move probably
1778  // makes it unprofitable.
1779  return false;
1780 
1781  // Check whether CmpInstr can be made redundant by the current instruction.
1782  if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
1783  OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
1784  (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
1785  ((Instr.getOperand(1).getReg() == SrcReg &&
1786  Instr.getOperand(2).getReg() == SrcReg2) ||
1787  (Instr.getOperand(1).getReg() == SrcReg2 &&
1788  Instr.getOperand(2).getReg() == SrcReg))) {
1789  Sub = &*I;
1790  break;
1791  }
1792 
1793  if (I == B)
1794  // The 'and' is below the comparison instruction.
1795  return false;
1796  }
1797 
1798  // Return false if no candidates exist.
1799  if (!MI && !Sub)
1800  return false;
1801 
1802  // The single candidate is called MI.
1803  if (!MI) MI = Sub;
1804 
1805  int NewOpC = -1;
1806  int MIOpC = MI->getOpcode();
1807  if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8)
1808  NewOpC = MIOpC;
1809  else {
1810  NewOpC = PPC::getRecordFormOpcode(MIOpC);
1811  if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
1812  NewOpC = MIOpC;
1813  }
1814 
1815  // FIXME: On the non-embedded POWER architectures, only some of the record
1816  // forms are fast, and we should use only the fast ones.
1817 
1818  // The defining instruction has a record form (or is already a record
1819  // form). It is possible, however, that we'll need to reverse the condition
1820  // code of the users.
1821  if (NewOpC == -1)
1822  return false;
1823 
1824  // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
1825  // needs to be updated to be based on SUB. Push the condition code
1826  // operands to OperandsToUpdate. If it is safe to remove CmpInstr, the
1827  // condition code of these operands will be modified.
1828  // Here, Value == 0 means we haven't converted comparison against 1 or -1 to
1829  // comparison against 0, which may modify predicate.
1830  bool ShouldSwap = false;
1831  if (Sub && Value == 0) {
1832  ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1833  Sub->getOperand(2).getReg() == SrcReg;
1834 
1835  // The operands to subf are the opposite of sub, so only in the fixed-point
1836  // case, invert the order.
1837  ShouldSwap = !ShouldSwap;
1838  }
1839 
1840  if (ShouldSwap)
1842  I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1843  I != IE; ++I) {
1844  MachineInstr *UseMI = &*I;
1845  if (UseMI->getOpcode() == PPC::BCC) {
1846  PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
1847  unsigned PredCond = PPC::getPredicateCondition(Pred);
1848  assert((!equalityOnly ||
1849  PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE) &&
1850  "Invalid predicate for equality-only optimization");
1851  (void)PredCond; // To suppress warning in release build.
1852  PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1853  PPC::getSwappedPredicate(Pred)));
1854  } else if (UseMI->getOpcode() == PPC::ISEL ||
1855  UseMI->getOpcode() == PPC::ISEL8) {
1856  unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
1857  assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
1858  "Invalid CR bit for equality-only optimization");
1859 
1860  if (NewSubReg == PPC::sub_lt)
1861  NewSubReg = PPC::sub_gt;
1862  else if (NewSubReg == PPC::sub_gt)
1863  NewSubReg = PPC::sub_lt;
1864 
1865  SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)),
1866  NewSubReg));
1867  } else // We need to abort on a user we don't understand.
1868  return false;
1869  }
1870  assert(!(Value != 0 && ShouldSwap) &&
1871  "Non-zero immediate support and ShouldSwap"
1872  "may conflict in updating predicate");
1873 
1874  // Create a new virtual register to hold the value of the CR set by the
1875  // record-form instruction. If the instruction was not previously in
1876  // record form, then set the kill flag on the CR.
1877  CmpInstr.eraseFromParent();
1878 
1880  BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
1881  get(TargetOpcode::COPY), CRReg)
1882  .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
1883 
1884  // Even if CR0 register were dead before, it is alive now since the
1885  // instruction we just built uses it.
1886  MI->clearRegisterDeads(PPC::CR0);
1887 
1888  if (MIOpC != NewOpC) {
1889  // We need to be careful here: we're replacing one instruction with
1890  // another, and we need to make sure that we get all of the right
1891  // implicit uses and defs. On the other hand, the caller may be holding
1892  // an iterator to this instruction, and so we can't delete it (this is
1893  // specifically the case if this is the instruction directly after the
1894  // compare).
1895 
1896  const MCInstrDesc &NewDesc = get(NewOpC);
1897  MI->setDesc(NewDesc);
1898 
1899  if (NewDesc.ImplicitDefs)
1900  for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs();
1901  *ImpDefs; ++ImpDefs)
1902  if (!MI->definesRegister(*ImpDefs))
1903  MI->addOperand(*MI->getParent()->getParent(),
1904  MachineOperand::CreateReg(*ImpDefs, true, true));
1905  if (NewDesc.ImplicitUses)
1906  for (const MCPhysReg *ImpUses = NewDesc.getImplicitUses();
1907  *ImpUses; ++ImpUses)
1908  if (!MI->readsRegister(*ImpUses))
1909  MI->addOperand(*MI->getParent()->getParent(),
1910  MachineOperand::CreateReg(*ImpUses, false, true));
1911  }
1912  assert(MI->definesRegister(PPC::CR0) &&
1913  "Record-form instruction does not define cr0?");
1914 
1915  // Modify the condition code of operands in OperandsToUpdate.
1916  // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
1917  // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
1918  for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
1919  PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
1920 
1921  for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
1922  SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
1923 
1924  return true;
1925 }
1926 
1927 /// GetInstSize - Return the number of bytes of code the specified
1928 /// instruction may be. This returns the maximum number of bytes.
1929 ///
1931  unsigned Opcode = MI.getOpcode();
1932 
1933  if (Opcode == PPC::INLINEASM) {
1934  const MachineFunction *MF = MI.getParent()->getParent();
1935  const char *AsmStr = MI.getOperand(0).getSymbolName();
1936  return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1937  } else if (Opcode == TargetOpcode::STACKMAP) {
1938  StackMapOpers Opers(&MI);
1939  return Opers.getNumPatchBytes();
1940  } else if (Opcode == TargetOpcode::PATCHPOINT) {
1941  PatchPointOpers Opers(&MI);
1942  return Opers.getNumPatchBytes();
1943  } else {
1944  return get(Opcode).getSize();
1945  }
1946 }
1947 
1948 std::pair<unsigned, unsigned>
1950  const unsigned Mask = PPCII::MO_ACCESS_MASK;
1951  return std::make_pair(TF & Mask, TF & ~Mask);
1952 }
1953 
1956  using namespace PPCII;
1957  static const std::pair<unsigned, const char *> TargetFlags[] = {
1958  {MO_LO, "ppc-lo"},
1959  {MO_HA, "ppc-ha"},
1960  {MO_TPREL_LO, "ppc-tprel-lo"},
1961  {MO_TPREL_HA, "ppc-tprel-ha"},
1962  {MO_DTPREL_LO, "ppc-dtprel-lo"},
1963  {MO_TLSLD_LO, "ppc-tlsld-lo"},
1964  {MO_TOC_LO, "ppc-toc-lo"},
1965  {MO_TLS, "ppc-tls"}};
1966  return makeArrayRef(TargetFlags);
1967 }
1968 
1971  using namespace PPCII;
1972  static const std::pair<unsigned, const char *> TargetFlags[] = {
1973  {MO_PLT, "ppc-plt"},
1974  {MO_PIC_FLAG, "ppc-pic"},
1975  {MO_NLP_FLAG, "ppc-nlp"},
1976  {MO_NLP_HIDDEN_FLAG, "ppc-nlp-hidden"}};
1977  return makeArrayRef(TargetFlags);
1978 }
1979 
1980 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
1981 // The VSX versions have the advantage of a full 64-register target whereas
1982 // the FP ones have the advantage of lower latency and higher throughput. So
1983 // what we are after is using the faster instructions in low register pressure
1984 // situations and using the larger register file in high register pressure
1985 // situations.
1987  unsigned UpperOpcode, LowerOpcode;
1988  switch (MI.getOpcode()) {
1989  case PPC::DFLOADf32:
1990  UpperOpcode = PPC::LXSSP;
1991  LowerOpcode = PPC::LFS;
1992  break;
1993  case PPC::DFLOADf64:
1994  UpperOpcode = PPC::LXSD;
1995  LowerOpcode = PPC::LFD;
1996  break;
1997  case PPC::DFSTOREf32:
1998  UpperOpcode = PPC::STXSSP;
1999  LowerOpcode = PPC::STFS;
2000  break;
2001  case PPC::DFSTOREf64:
2002  UpperOpcode = PPC::STXSD;
2003  LowerOpcode = PPC::STFD;
2004  break;
2005  case PPC::XFLOADf32:
2006  UpperOpcode = PPC::LXSSPX;
2007  LowerOpcode = PPC::LFSX;
2008  break;
2009  case PPC::XFLOADf64:
2010  UpperOpcode = PPC::LXSDX;
2011  LowerOpcode = PPC::LFDX;
2012  break;
2013  case PPC::XFSTOREf32:
2014  UpperOpcode = PPC::STXSSPX;
2015  LowerOpcode = PPC::STFSX;
2016  break;
2017  case PPC::XFSTOREf64:
2018  UpperOpcode = PPC::STXSDX;
2019  LowerOpcode = PPC::STFDX;
2020  break;
2021  case PPC::LIWAX:
2022  UpperOpcode = PPC::LXSIWAX;
2023  LowerOpcode = PPC::LFIWAX;
2024  break;
2025  case PPC::LIWZX:
2026  UpperOpcode = PPC::LXSIWZX;
2027  LowerOpcode = PPC::LFIWZX;
2028  break;
2029  case PPC::STIWX:
2030  UpperOpcode = PPC::STXSIWX;
2031  LowerOpcode = PPC::STFIWX;
2032  break;
2033  default:
2034  llvm_unreachable("Unknown Operation!");
2035  }
2036 
2037  unsigned TargetReg = MI.getOperand(0).getReg();
2038  unsigned Opcode;
2039  if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) ||
2040  (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31))
2041  Opcode = LowerOpcode;
2042  else
2043  Opcode = UpperOpcode;
2044  MI.setDesc(get(Opcode));
2045  return true;
2046 }
2047 
2049  auto &MBB = *MI.getParent();
2050  auto DL = MI.getDebugLoc();
2051 
2052  switch (MI.getOpcode()) {
2053  case TargetOpcode::LOAD_STACK_GUARD: {
2054  assert(Subtarget.isTargetLinux() &&
2055  "Only Linux target is expected to contain LOAD_STACK_GUARD");
2056  const int64_t Offset = Subtarget.isPPC64() ? -0x7010 : -0x7008;
2057  const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2;
2058  MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ));
2060  .addImm(Offset)
2061  .addReg(Reg);
2062  return true;
2063  }
2064  case PPC::DFLOADf32:
2065  case PPC::DFLOADf64:
2066  case PPC::DFSTOREf32:
2067  case PPC::DFSTOREf64: {
2068  assert(Subtarget.hasP9Vector() &&
2069  "Invalid D-Form Pseudo-ops on Pre-P9 target.");
2070  assert(MI.getOperand(2).isReg() && MI.getOperand(1).isImm() &&
2071  "D-form op must have register and immediate operands");
2072  return expandVSXMemPseudo(MI);
2073  }
2074  case PPC::XFLOADf32:
2075  case PPC::XFSTOREf32:
2076  case PPC::LIWAX:
2077  case PPC::LIWZX:
2078  case PPC::STIWX: {
2079  assert(Subtarget.hasP8Vector() &&
2080  "Invalid X-Form Pseudo-ops on Pre-P8 target.");
2081  assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
2082  "X-form op must have register and register operands");
2083  return expandVSXMemPseudo(MI);
2084  }
2085  case PPC::XFLOADf64:
2086  case PPC::XFSTOREf64: {
2087  assert(Subtarget.hasVSX() &&
2088  "Invalid X-Form Pseudo-ops on target that has no VSX.");
2089  assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
2090  "X-form op must have register and register operands");
2091  return expandVSXMemPseudo(MI);
2092  }
2093  case PPC::SPILLTOVSR_LD: {
2094  unsigned TargetReg = MI.getOperand(0).getReg();
2095  if (PPC::VSFRCRegClass.contains(TargetReg)) {
2096  MI.setDesc(get(PPC::DFLOADf64));
2097  return expandPostRAPseudo(MI);
2098  }
2099  else
2100  MI.setDesc(get(PPC::LD));
2101  return true;
2102  }
2103  case PPC::SPILLTOVSR_ST: {
2104  unsigned SrcReg = MI.getOperand(0).getReg();
2105  if (PPC::VSFRCRegClass.contains(SrcReg)) {
2106  NumStoreSPILLVSRRCAsVec++;
2107  MI.setDesc(get(PPC::DFSTOREf64));
2108  return expandPostRAPseudo(MI);
2109  } else {
2110  NumStoreSPILLVSRRCAsGpr++;
2111  MI.setDesc(get(PPC::STD));
2112  }
2113  return true;
2114  }
2115  case PPC::SPILLTOVSR_LDX: {
2116  unsigned TargetReg = MI.getOperand(0).getReg();
2117  if (PPC::VSFRCRegClass.contains(TargetReg))
2118  MI.setDesc(get(PPC::LXSDX));
2119  else
2120  MI.setDesc(get(PPC::LDX));
2121  return true;
2122  }
2123  case PPC::SPILLTOVSR_STX: {
2124  unsigned SrcReg = MI.getOperand(0).getReg();
2125  if (PPC::VSFRCRegClass.contains(SrcReg)) {
2126  NumStoreSPILLVSRRCAsVec++;
2127  MI.setDesc(get(PPC::STXSDX));
2128  } else {
2129  NumStoreSPILLVSRRCAsGpr++;
2130  MI.setDesc(get(PPC::STDX));
2131  }
2132  return true;
2133  }
2134 
2135  case PPC::CFENCE8: {
2136  auto Val = MI.getOperand(0).getReg();
2137  BuildMI(MBB, MI, DL, get(PPC::CMPD), PPC::CR7).addReg(Val).addReg(Val);
2138  BuildMI(MBB, MI, DL, get(PPC::CTRL_DEP))
2140  .addReg(PPC::CR7)
2141  .addImm(1);
2142  MI.setDesc(get(PPC::ISYNC));
2143  MI.RemoveOperand(0);
2144  return true;
2145  }
2146  }
2147  return false;
2148 }
2149 
2150 const TargetRegisterClass *
2152  if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
2153  return &PPC::VSRCRegClass;
2154  return RC;
2155 }
2156 
2158  return PPC::getRecordFormOpcode(Opcode);
2159 }
2160 
2161 // This function returns true if the machine instruction
2162 // always outputs a value by sign-extending a 32 bit value,
2163 // i.e. 0 to 31-th bits are same as 32-th bit.
2164 static bool isSignExtendingOp(const MachineInstr &MI) {
2165  int Opcode = MI.getOpcode();
2166  if (Opcode == PPC::LI || Opcode == PPC::LI8 ||
2167  Opcode == PPC::LIS || Opcode == PPC::LIS8 ||
2168  Opcode == PPC::SRAW || Opcode == PPC::SRAWo ||
2169  Opcode == PPC::SRAWI || Opcode == PPC::SRAWIo ||
2170  Opcode == PPC::LWA || Opcode == PPC::LWAX ||
2171  Opcode == PPC::LWA_32 || Opcode == PPC::LWAX_32 ||
2172  Opcode == PPC::LHA || Opcode == PPC::LHAX ||
2173  Opcode == PPC::LHA8 || Opcode == PPC::LHAX8 ||
2174  Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
2175  Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
2176  Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
2177  Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
2178  Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
2179  Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 ||
2180  Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
2181  Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 ||
2182  Opcode == PPC::EXTSB || Opcode == PPC::EXTSBo ||
2183  Opcode == PPC::EXTSH || Opcode == PPC::EXTSHo ||
2184  Opcode == PPC::EXTSB8 || Opcode == PPC::EXTSH8 ||
2185  Opcode == PPC::EXTSW || Opcode == PPC::EXTSWo ||
2186  Opcode == PPC::EXTSH8_32_64 || Opcode == PPC::EXTSW_32_64 ||
2187  Opcode == PPC::EXTSB8_32_64)
2188  return true;
2189 
2190  if (Opcode == PPC::RLDICL && MI.getOperand(3).getImm() >= 33)
2191  return true;
2192 
2193  if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
2194  Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo) &&
2195  MI.getOperand(3).getImm() > 0 &&
2196  MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
2197  return true;
2198 
2199  return false;
2200 }
2201 
2202 // This function returns true if the machine instruction
2203 // always outputs zeros in higher 32 bits.
2204 static bool isZeroExtendingOp(const MachineInstr &MI) {
2205  int Opcode = MI.getOpcode();
2206  // The 16-bit immediate is sign-extended in li/lis.
2207  // If the most significant bit is zero, all higher bits are zero.
2208  if (Opcode == PPC::LI || Opcode == PPC::LI8 ||
2209  Opcode == PPC::LIS || Opcode == PPC::LIS8) {
2210  int64_t Imm = MI.getOperand(1).getImm();
2211  if (((uint64_t)Imm & ~0x7FFFuLL) == 0)
2212  return true;
2213  }
2214 
2215  // We have some variations of rotate-and-mask instructions
2216  // that clear higher 32-bits.
2217  if ((Opcode == PPC::RLDICL || Opcode == PPC::RLDICLo ||
2218  Opcode == PPC::RLDCL || Opcode == PPC::RLDCLo ||
2219  Opcode == PPC::RLDICL_32_64) &&
2220  MI.getOperand(3).getImm() >= 32)
2221  return true;
2222 
2223  if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDICo) &&
2224  MI.getOperand(3).getImm() >= 32 &&
2225  MI.getOperand(3).getImm() <= 63 - MI.getOperand(2).getImm())
2226  return true;
2227 
2228  if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
2229  Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo ||
2230  Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) &&
2231  MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
2232  return true;
2233 
2234  // There are other instructions that clear higher 32-bits.
2235  if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZWo ||
2236  Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZWo ||
2237  Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8 ||
2238  Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZDo ||
2239  Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZDo ||
2240  Opcode == PPC::POPCNTD || Opcode == PPC::POPCNTW ||
2241  Opcode == PPC::SLW || Opcode == PPC::SLWo ||
2242  Opcode == PPC::SRW || Opcode == PPC::SRWo ||
2243  Opcode == PPC::SLW8 || Opcode == PPC::SRW8 ||
2244  Opcode == PPC::SLWI || Opcode == PPC::SLWIo ||
2245  Opcode == PPC::SRWI || Opcode == PPC::SRWIo ||
2246  Opcode == PPC::LWZ || Opcode == PPC::LWZX ||
2247  Opcode == PPC::LWZU || Opcode == PPC::LWZUX ||
2248  Opcode == PPC::LWBRX || Opcode == PPC::LHBRX ||
2249  Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
2250  Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
2251  Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
2252  Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
2253  Opcode == PPC::LWZ8 || Opcode == PPC::LWZX8 ||
2254  Opcode == PPC::LWZU8 || Opcode == PPC::LWZUX8 ||
2255  Opcode == PPC::LWBRX8 || Opcode == PPC::LHBRX8 ||
2256  Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 ||
2257  Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 ||
2258  Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
2259  Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
2260  Opcode == PPC::ANDIo || Opcode == PPC::ANDISo ||
2261  Opcode == PPC::ROTRWI || Opcode == PPC::ROTRWIo ||
2262  Opcode == PPC::EXTLWI || Opcode == PPC::EXTLWIo ||
2263  Opcode == PPC::MFVSRWZ)
2264  return true;
2265 
2266  return false;
2267 }
2268 
2269 // We limit the max depth to track incoming values of PHIs or binary ops
2270 // (e.g. AND) to avoid exsessive cost.
2271 const unsigned MAX_DEPTH = 1;
2272 
2273 bool
2275  const unsigned Depth) const {
2276  const MachineFunction *MF = MI.getParent()->getParent();
2277  const MachineRegisterInfo *MRI = &MF->getRegInfo();
2278 
2279  // If we know this instruction returns sign- or zero-extended result,
2280  // return true.
2281  if (SignExt ? isSignExtendingOp(MI):
2282  isZeroExtendingOp(MI))
2283  return true;
2284 
2285  switch (MI.getOpcode()) {
2286  case PPC::COPY: {
2287  unsigned SrcReg = MI.getOperand(1).getReg();
2288 
2289  // In both ELFv1 and v2 ABI, method parameters and the return value
2290  // are sign- or zero-extended.
2291  if (MF->getSubtarget<PPCSubtarget>().isSVR4ABI()) {
2292  const PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
2293  // We check the ZExt/SExt flags for a method parameter.
2294  if (MI.getParent()->getBasicBlock() ==
2295  &MF->getFunction()->getEntryBlock()) {
2296  unsigned VReg = MI.getOperand(0).getReg();
2297  if (MF->getRegInfo().isLiveIn(VReg))
2298  return SignExt ? FuncInfo->isLiveInSExt(VReg) :
2299  FuncInfo->isLiveInZExt(VReg);
2300  }
2301 
2302  // For a method return value, we check the ZExt/SExt flags in attribute.
2303  // We assume the following code sequence for method call.
2304  // ADJCALLSTACKDOWN 32, %R1<imp-def,dead>, %R1<imp-use>
2305  // BL8_NOP <ga:@func>,...
2306  // ADJCALLSTACKUP 32, 0, %R1<imp-def,dead>, %R1<imp-use>
2307  // %vreg5<def> = COPY %X3; G8RC:%vreg5
2308  if (SrcReg == PPC::X3) {
2309  const MachineBasicBlock *MBB = MI.getParent();
2312  if (II != MBB->instr_begin() &&
2313  (--II)->getOpcode() == PPC::ADJCALLSTACKUP) {
2314  const MachineInstr &CallMI = *(--II);
2315  if (CallMI.isCall() && CallMI.getOperand(0).isGlobal()) {
2316  const Function *CalleeFn =
2317  dyn_cast<Function>(CallMI.getOperand(0).getGlobal());
2318  if (!CalleeFn)
2319  return false;
2320  const IntegerType *IntTy =
2321  dyn_cast<IntegerType>(CalleeFn->getReturnType());
2322  const AttributeSet &Attrs =
2323  CalleeFn->getAttributes().getRetAttributes();
2324  if (IntTy && IntTy->getBitWidth() <= 32)
2325  return Attrs.hasAttribute(SignExt ? Attribute::SExt :
2326  Attribute::ZExt);
2327  }
2328  }
2329  }
2330  }
2331 
2332  // If this is a copy from another register, we recursively check source.
2334  return false;
2335  const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
2336  if (SrcMI != NULL)
2337  return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
2338 
2339  return false;
2340  }
2341 
2342  case PPC::ANDIo:
2343  case PPC::ANDISo:
2344  case PPC::ORI:
2345  case PPC::ORIS:
2346  case PPC::XORI:
2347  case PPC::XORIS:
2348  case PPC::ANDIo8:
2349  case PPC::ANDISo8:
2350  case PPC::ORI8:
2351  case PPC::ORIS8:
2352  case PPC::XORI8:
2353  case PPC::XORIS8: {
2354  // logical operation with 16-bit immediate does not change the upper bits.
2355  // So, we track the operand register as we do for register copy.
2356  unsigned SrcReg = MI.getOperand(1).getReg();
2358  return false;
2359  const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
2360  if (SrcMI != NULL)
2361  return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
2362 
2363  return false;
2364  }
2365 
2366  // If all incoming values are sign-/zero-extended,
2367  // the output of AND, OR, ISEL or PHI is also sign-/zero-extended.
2368  case PPC::AND:
2369  case PPC::AND8:
2370  case PPC::OR:
2371  case PPC::OR8:
2372  case PPC::ISEL:
2373  case PPC::PHI: {
2374  if (Depth >= MAX_DEPTH)
2375  return false;
2376 
2377  // The input registers for PHI are operand 1, 3, ...
2378  // The input registers for others are operand 1 and 2.
2379  unsigned E = 3, D = 1;
2380  if (MI.getOpcode() == PPC::PHI) {
2381  E = MI.getNumOperands();
2382  D = 2;
2383  }
2384 
2385  for (unsigned I = 1; I != E; I += D) {
2386  if (MI.getOperand(I).isReg()) {
2387  unsigned SrcReg = MI.getOperand(I).getReg();
2389  return false;
2390  const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
2391  if (SrcMI == NULL || !isSignOrZeroExtended(*SrcMI, SignExt, Depth+1))
2392  return false;
2393  }
2394  else
2395  return false;
2396  }
2397  return true;
2398  }
2399 
2400  default:
2401  break;
2402  }
2403  return false;
2404 }
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
Definition: MachineInstr.h:965
instr_iterator instr_begin()
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:458
int getNonRecordFormOpcode(uint16_t)
MachineBasicBlock * getMBB() const
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
iterator begin() const
begin/end - Return all of the registers in this class.
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:268
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:512
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
static int getRecordFormOpcode(unsigned Opcode)
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned getSubReg() const
bool hasVSX() const
Definition: PPCSubtarget.h:242
static cl::opt< bool > DisableCmpOpt("disable-ppc-cmp-opt", cl::desc("Disable compare instruction optimization"), cl::Hidden)
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
STATISTIC(NumFunctions, "Total number of functions")
A debug info location.
Definition: DebugLoc.h:34
bool isPseudo() const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MCInstrDesc.h:242
CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
#define R2(n)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isSignExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always a sign-extended, i.e.
Definition: PPCInstrInfo.h:305
return AArch64::GPR64RegClass contains(Reg)
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling th...
MachineFunction & MF
Machine function.
Definition: ScheduleDAG.h:570
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
PPCDispatchGroupSBHazardRecognizer - This class implements a scoreboard-based hazard recognizer for P...
A description of a memory reference used in the backend.
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:451
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:293
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
Reg
All possible values of the reg field in the ModR/M byte.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:474
AttributeSet getRetAttributes() const
The attributes for the ret value are returned.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
const TargetRegisterClass * updatedRC(const TargetRegisterClass *RC) const
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const override
const char * getSymbolName() const
static bool isZeroExtendingOp(const MachineInstr &MI)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:634
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
defusechain_iterator - This class provides iterator support for machine operands in the function that...
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
PPCInstrInfo(PPCSubtarget &STI)
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:287
CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based loops.
bool hasP9Vector() const
Definition: PPCSubtarget.h:246
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const override
MO_NLP_HIDDEN_FLAG - If this bit is set, the symbol reference is to a symbol with hidden visibility...
Definition: PPC.h:88
virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns) const
Return true when there is potentially a faster code sequence for an instruction chain ending in Root...
CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
Itinerary data supplied by a subtarget to be used by a target.
const PPCTargetMachine & getTargetMachine() const
Definition: PPCSubtarget.h:189
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:205
constexpr char Attrs[]
Key for Kernel::Metadata::mAttrs.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
unsigned getBitWidth() const
Get the number of bits in this IntegerType.
Definition: DerivedTypes.h:66
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:482
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:159
unsigned getKillRegState(bool B)
bool hasAttribute(Attribute::AttrKind Kind) const
Return true if the attribute exists in this set.
Definition: Attributes.cpp:573
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
unsigned getDeadRegState(bool B)
VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
const BasicBlock & getEntryBlock() const
Definition: Function.h:572
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:565
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, const unsigned PhiDepth) const
Type * getReturnType() const
Returns the type of the ret val.
Definition: Function.h:150
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:534
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
unsigned const MachineRegisterInfo * MRI
bool isLiveInSExt(unsigned VReg) const
This function returns true if the spesified vreg is a live-in register and sign-extended.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
int getAltVSXFMAOpcode(uint16_t Opcode)
Simple binary floating point operators.
Definition: ISDOpcodes.h:259
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void clearRegisterDeads(unsigned Reg)
Clear all dead flags on operands defining register Reg.
MachineInstrBuilder & UseMI
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
MO_NLP_FLAG - If this bit is set, the symbol reference is actually to the non_lazy_ptr for the global...
Definition: PPC.h:83
const GlobalValue * getGlobal() const
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:31
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:173
STFIWX - The STFIWX instruction.
use_instr_iterator use_instr_begin(unsigned RegNo) const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
void setImm(int64_t immVal)
bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
Definition: MachineInstr.h:957
GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point load which sign-extends from a 32-bit inte...
MI-level patchpoint operands.
Definition: StackMaps.h:77
Class to represent integer types.
Definition: DerivedTypes.h:40
PPCHazardRecognizer970 - This class defines a finite state automata that models the dispatch logic on...
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned getPredicateHint(Predicate Opcode)
Return the hint bits of the predicate.
Definition: PPCPredicates.h:80
unsigned getDarwinDirective() const
getDarwinDirective - Returns the -m directive specified for the cpu.
Definition: PPCSubtarget.h:168
static unsigned getCRFromCRBit(unsigned SrcReg)
MO_TLS - Indicates that the operand being accessed is some kind of thread-local symbol.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
unsigned first
void setIsKill(bool Val=true)
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
The next are not flags but distinct values.
Definition: PPC.h:91
The memory access writes data.
static bool MBBDefinesCTR(MachineBasicBlock &MBB)
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:187
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given stackmap should emit.
Definition: StackMaps.h:51
Predicate getPredicate(unsigned Condition, unsigned Hint)
Return predicate consisting of specified condition and hint bits.
Definition: PPCPredicates.h:85
Iterator for intrusive lists based on ilist_node.
void setOpcode(unsigned Op)
Definition: MCInst.h:171
bool isUnpredicatedTerminator(const MachineInstr &MI) const override
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
void getNoop(MCInst &NopInst) const override
Return the noop instruction to use for a noop.
static unsigned getCRBitValue(unsigned CRBit)
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:720
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:27
static cl::opt< bool > VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy", cl::desc("Causes the backend to crash instead of generating a nop VSX copy"), cl::Hidden)
static cl::opt< bool > UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden, cl::desc("Use the old (incorrect) instruction latency calculation"))
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
int64_t getImm() const
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction...
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
QVGPCI = This corresponds to the QPX qvgpci instruction.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:927
On a symbol operand, this represents the lo part.
Definition: AVRInstrInfo.h:53
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
TargetSubtargetInfo - Generic base class for all target subtargets.
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in <Root...
bool isPredicated(const MachineInstr &MI) const override
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
bool isLiveIn(unsigned Reg) const
Representation of each machine instruction.
Definition: MachineInstr.h:59
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Predicate InvertPredicate(Predicate Opcode)
Invert the specified predicate. != -> ==, < -> >=.
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:362
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
bool hasOneUse(unsigned RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MI-level stackmap operands.
Definition: StackMaps.h:36
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
TargetOptions Options
Definition: TargetMachine.h:96
static bool isSignExtendingOp(const MachineInstr &MI)
void setReg(unsigned Reg)
Change the register this operand corresponds to.
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:58
void setSubReg(unsigned subReg)
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given patchpoint should emit.
Definition: StackMaps.h:105
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:568
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
bool isDarwin() const
isDarwin - True if this is any darwin platform.
Definition: PPCSubtarget.h:296
const unsigned MAX_DEPTH
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
unsigned getPredicateCondition(Predicate Opcode)
Return the condition without hint bits.
Definition: PPCPredicates.h:75
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
bool isLiveInZExt(unsigned VReg) const
This function returns true if the spesified vreg is a live-in register and zero-extended.
LLVM Value Representation.
Definition: Value.h:73
static use_instr_iterator use_instr_end()
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when ...
IRTranslator LLVM IR MI
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:465
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
bool isPredicable(const MachineInstr &MI) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool isSVR4ABI() const
Definition: PPCSubtarget.h:305
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:70
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
On a symbol operand "FOO", this indicates that the reference is actually to "FOO@plt".
Definition: PPC.h:75
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: PPCInstrInfo.h:114
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:222
static cl::opt< bool > DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden, cl::desc("Disable analysis for CTR loops"))
Instructions::const_iterator const_instr_iterator
GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point load which zero-extends from a 32-bit inte...
MO_PIC_FLAG - If this bit is set, the symbol reference is relative to the function&#39;s picbase...
Definition: PPC.h:79
bool expandPostRAPseudo(MachineInstr &MI) const override
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:144
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:172
bool expandVSXMemPseudo(MachineInstr &MI) const
bool isImplicit() const
bool isZeroExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always zero-extended, i.e.
Definition: PPCInstrInfo.h:311
Predicate getSwappedPredicate(Predicate Opcode)
Assume the condition register is set by MI(a,b), return the predicate if we modify the instructions s...