LLVM  10.0.0svn
PPCInstrInfo.cpp
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1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the PowerPC implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "PPCInstrInfo.h"
15 #include "PPC.h"
16 #include "PPCHazardRecognizers.h"
17 #include "PPCInstrBuilder.h"
18 #include "PPCMachineFunctionInfo.h"
19 #include "PPCTargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Statistic.h"
31 #include "llvm/CodeGen/StackMaps.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/MC/MCInst.h"
35 #include "llvm/Support/Debug.h"
39 
40 using namespace llvm;
41 
42 #define DEBUG_TYPE "ppc-instr-info"
43 
44 #define GET_INSTRMAP_INFO
45 #define GET_INSTRINFO_CTOR_DTOR
46 #include "PPCGenInstrInfo.inc"
47 
48 STATISTIC(NumStoreSPILLVSRRCAsVec,
49  "Number of spillvsrrc spilled to stack as vec");
50 STATISTIC(NumStoreSPILLVSRRCAsGpr,
51  "Number of spillvsrrc spilled to stack as gpr");
52 STATISTIC(NumGPRtoVSRSpill, "Number of gpr spills to spillvsrrc");
53 STATISTIC(CmpIselsConverted,
54  "Number of ISELs that depend on comparison of constants converted");
55 STATISTIC(MissedConvertibleImmediateInstrs,
56  "Number of compare-immediate instructions fed by constants");
57 STATISTIC(NumRcRotatesConvertedToRcAnd,
58  "Number of record-form rotates converted to record-form andi");
59 
60 static cl::
61 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
62  cl::desc("Disable analysis for CTR loops"));
63 
64 static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
65 cl::desc("Disable compare instruction optimization"), cl::Hidden);
66 
67 static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
68 cl::desc("Causes the backend to crash instead of generating a nop VSX copy"),
69 cl::Hidden);
70 
71 static cl::opt<bool>
72 UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
73  cl::desc("Use the old (incorrect) instruction latency calculation"));
74 
75 // Index into the OpcodesForSpill array.
94  SOK_LastOpcodeSpill // This must be last on the enum.
95 };
96 
97 // Pin the vtable to this file.
98 void PPCInstrInfo::anchor() {}
99 
101  : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP,
102  /* CatchRetOpcode */ -1,
103  STI.isPPC64() ? PPC::BLR8 : PPC::BLR),
104  Subtarget(STI), RI(STI.getTargetMachine()) {}
105 
106 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
107 /// this target when scheduling the DAG.
110  const ScheduleDAG *DAG) const {
111  unsigned Directive =
112  static_cast<const PPCSubtarget *>(STI)->getDarwinDirective();
113  if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
114  Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
115  const InstrItineraryData *II =
116  static_cast<const PPCSubtarget *>(STI)->getInstrItineraryData();
117  return new ScoreboardHazardRecognizer(II, DAG);
118  }
119 
121 }
122 
123 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
124 /// to use for this target when scheduling the DAG.
127  const ScheduleDAG *DAG) const {
128  unsigned Directive =
129  DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
130 
131  // FIXME: Leaving this as-is until we have POWER9 scheduling info
132  if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8)
133  return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
134 
135  // Most subtargets use a PPC970 recognizer.
136  if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
137  Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
138  assert(DAG->TII && "No InstrInfo?");
139 
140  return new PPCHazardRecognizer970(*DAG);
141  }
142 
143  return new ScoreboardHazardRecognizer(II, DAG);
144 }
145 
147  const MachineInstr &MI,
148  unsigned *PredCost) const {
149  if (!ItinData || UseOldLatencyCalc)
150  return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
151 
152  // The default implementation of getInstrLatency calls getStageLatency, but
153  // getStageLatency does not do the right thing for us. While we have
154  // itinerary, most cores are fully pipelined, and so the itineraries only
155  // express the first part of the pipeline, not every stage. Instead, we need
156  // to use the listed output operand cycle number (using operand 0 here, which
157  // is an output).
158 
159  unsigned Latency = 1;
160  unsigned DefClass = MI.getDesc().getSchedClass();
161  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
162  const MachineOperand &MO = MI.getOperand(i);
163  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
164  continue;
165 
166  int Cycle = ItinData->getOperandCycle(DefClass, i);
167  if (Cycle < 0)
168  continue;
169 
170  Latency = std::max(Latency, (unsigned) Cycle);
171  }
172 
173  return Latency;
174 }
175 
177  const MachineInstr &DefMI, unsigned DefIdx,
178  const MachineInstr &UseMI,
179  unsigned UseIdx) const {
180  int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
181  UseMI, UseIdx);
182 
183  if (!DefMI.getParent())
184  return Latency;
185 
186  const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
187  Register Reg = DefMO.getReg();
188 
189  bool IsRegCR;
190  if (Register::isVirtualRegister(Reg)) {
191  const MachineRegisterInfo *MRI =
192  &DefMI.getParent()->getParent()->getRegInfo();
193  IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
194  MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
195  } else {
196  IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
197  PPC::CRBITRCRegClass.contains(Reg);
198  }
199 
200  if (UseMI.isBranch() && IsRegCR) {
201  if (Latency < 0)
202  Latency = getInstrLatency(ItinData, DefMI);
203 
204  // On some cores, there is an additional delay between writing to a condition
205  // register, and using it from a branch.
206  unsigned Directive = Subtarget.getDarwinDirective();
207  switch (Directive) {
208  default: break;
209  case PPC::DIR_7400:
210  case PPC::DIR_750:
211  case PPC::DIR_970:
212  case PPC::DIR_E5500:
213  case PPC::DIR_PWR4:
214  case PPC::DIR_PWR5:
215  case PPC::DIR_PWR5X:
216  case PPC::DIR_PWR6:
217  case PPC::DIR_PWR6X:
218  case PPC::DIR_PWR7:
219  case PPC::DIR_PWR8:
220  // FIXME: Is this needed for POWER9?
221  Latency += 2;
222  break;
223  }
224  }
225 
226  return Latency;
227 }
228 
229 // This function does not list all associative and commutative operations, but
230 // only those worth feeding through the machine combiner in an attempt to
231 // reduce the critical path. Mostly, this means floating-point operations,
232 // because they have high latencies (compared to other operations, such and
233 // and/or, which are also associative and commutative, but have low latencies).
235  switch (Inst.getOpcode()) {
236  // FP Add:
237  case PPC::FADD:
238  case PPC::FADDS:
239  // FP Multiply:
240  case PPC::FMUL:
241  case PPC::FMULS:
242  // Altivec Add:
243  case PPC::VADDFP:
244  // VSX Add:
245  case PPC::XSADDDP:
246  case PPC::XVADDDP:
247  case PPC::XVADDSP:
248  case PPC::XSADDSP:
249  // VSX Multiply:
250  case PPC::XSMULDP:
251  case PPC::XVMULDP:
252  case PPC::XVMULSP:
253  case PPC::XSMULSP:
254  // QPX Add:
255  case PPC::QVFADD:
256  case PPC::QVFADDS:
257  case PPC::QVFADDSs:
258  // QPX Multiply:
259  case PPC::QVFMUL:
260  case PPC::QVFMULS:
261  case PPC::QVFMULSs:
262  return true;
263  default:
264  return false;
265  }
266 }
267 
269  MachineInstr &Root,
270  SmallVectorImpl<MachineCombinerPattern> &Patterns) const {
271  // Using the machine combiner in this way is potentially expensive, so
272  // restrict to when aggressive optimizations are desired.
274  return false;
275 
276  // FP reassociation is only legal when we don't need strict IEEE semantics.
278  return false;
279 
280  return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns);
281 }
282 
283 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
285  unsigned &SrcReg, unsigned &DstReg,
286  unsigned &SubIdx) const {
287  switch (MI.getOpcode()) {
288  default: return false;
289  case PPC::EXTSW:
290  case PPC::EXTSW_32:
291  case PPC::EXTSW_32_64:
292  SrcReg = MI.getOperand(1).getReg();
293  DstReg = MI.getOperand(0).getReg();
294  SubIdx = PPC::sub_32;
295  return true;
296  }
297 }
298 
300  int &FrameIndex) const {
301  unsigned Opcode = MI.getOpcode();
302  const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
303  const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill;
304 
305  if (End != std::find(OpcodesForSpill, End, Opcode)) {
306  // Check for the operands added by addFrameReference (the immediate is the
307  // offset which defaults to 0).
308  if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
309  MI.getOperand(2).isFI()) {
310  FrameIndex = MI.getOperand(2).getIndex();
311  return MI.getOperand(0).getReg();
312  }
313  }
314  return 0;
315 }
316 
317 // For opcodes with the ReMaterializable flag set, this function is called to
318 // verify the instruction is really rematable.
320  AliasAnalysis *AA) const {
321  switch (MI.getOpcode()) {
322  default:
323  // This function should only be called for opcodes with the ReMaterializable
324  // flag set.
325  llvm_unreachable("Unknown rematerializable operation!");
326  break;
327  case PPC::LI:
328  case PPC::LI8:
329  case PPC::LIS:
330  case PPC::LIS8:
331  case PPC::QVGPCI:
332  case PPC::ADDIStocHA8:
333  case PPC::ADDItocL:
334  case PPC::LOAD_STACK_GUARD:
335  case PPC::XXLXORz:
336  case PPC::XXLXORspz:
337  case PPC::XXLXORdpz:
338  case PPC::XXLEQVOnes:
339  case PPC::V_SET0B:
340  case PPC::V_SET0H:
341  case PPC::V_SET0:
342  case PPC::V_SETALLONESB:
343  case PPC::V_SETALLONESH:
344  case PPC::V_SETALLONES:
345  case PPC::CRSET:
346  case PPC::CRUNSET:
347  return true;
348  }
349  return false;
350 }
351 
353  int &FrameIndex) const {
354  unsigned Opcode = MI.getOpcode();
355  const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
356  const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill;
357 
358  if (End != std::find(OpcodesForSpill, End, Opcode)) {
359  if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
360  MI.getOperand(2).isFI()) {
361  FrameIndex = MI.getOperand(2).getIndex();
362  return MI.getOperand(0).getReg();
363  }
364  }
365  return 0;
366 }
367 
369  unsigned OpIdx1,
370  unsigned OpIdx2) const {
371  MachineFunction &MF = *MI.getParent()->getParent();
372 
373  // Normal instructions can be commuted the obvious way.
374  if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMIo)
375  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
376  // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
377  // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
378  // changing the relative order of the mask operands might change what happens
379  // to the high-bits of the mask (and, thus, the result).
380 
381  // Cannot commute if it has a non-zero rotate count.
382  if (MI.getOperand(3).getImm() != 0)
383  return nullptr;
384 
385  // If we have a zero rotate count, we have:
386  // M = mask(MB,ME)
387  // Op0 = (Op1 & ~M) | (Op2 & M)
388  // Change this to:
389  // M = mask((ME+1)&31, (MB-1)&31)
390  // Op0 = (Op2 & ~M) | (Op1 & M)
391 
392  // Swap op1/op2
393  assert(((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) &&
394  "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo.");
395  Register Reg0 = MI.getOperand(0).getReg();
396  Register Reg1 = MI.getOperand(1).getReg();
397  Register Reg2 = MI.getOperand(2).getReg();
398  unsigned SubReg1 = MI.getOperand(1).getSubReg();
399  unsigned SubReg2 = MI.getOperand(2).getSubReg();
400  bool Reg1IsKill = MI.getOperand(1).isKill();
401  bool Reg2IsKill = MI.getOperand(2).isKill();
402  bool ChangeReg0 = false;
403  // If machine instrs are no longer in two-address forms, update
404  // destination register as well.
405  if (Reg0 == Reg1) {
406  // Must be two address instruction!
408  "Expecting a two-address instruction!");
409  assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
410  Reg2IsKill = false;
411  ChangeReg0 = true;
412  }
413 
414  // Masks.
415  unsigned MB = MI.getOperand(4).getImm();
416  unsigned ME = MI.getOperand(5).getImm();
417 
418  // We can't commute a trivial mask (there is no way to represent an all-zero
419  // mask).
420  if (MB == 0 && ME == 31)
421  return nullptr;
422 
423  if (NewMI) {
424  // Create a new instruction.
425  Register Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg();
426  bool Reg0IsDead = MI.getOperand(0).isDead();
427  return BuildMI(MF, MI.getDebugLoc(), MI.getDesc())
428  .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
429  .addReg(Reg2, getKillRegState(Reg2IsKill))
430  .addReg(Reg1, getKillRegState(Reg1IsKill))
431  .addImm((ME + 1) & 31)
432  .addImm((MB - 1) & 31);
433  }
434 
435  if (ChangeReg0) {
436  MI.getOperand(0).setReg(Reg2);
437  MI.getOperand(0).setSubReg(SubReg2);
438  }
439  MI.getOperand(2).setReg(Reg1);
440  MI.getOperand(1).setReg(Reg2);
441  MI.getOperand(2).setSubReg(SubReg1);
442  MI.getOperand(1).setSubReg(SubReg2);
443  MI.getOperand(2).setIsKill(Reg1IsKill);
444  MI.getOperand(1).setIsKill(Reg2IsKill);
445 
446  // Swap the mask around.
447  MI.getOperand(4).setImm((ME + 1) & 31);
448  MI.getOperand(5).setImm((MB - 1) & 31);
449  return &MI;
450 }
451 
453  unsigned &SrcOpIdx2) const {
454  // For VSX A-Type FMA instructions, it is the first two operands that can be
455  // commuted, however, because the non-encoded tied input operand is listed
456  // first, the operands to swap are actually the second and third.
457 
458  int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode());
459  if (AltOpc == -1)
460  return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
461 
462  // The commutable operand indices are 2 and 3. Return them in SrcOpIdx1
463  // and SrcOpIdx2.
464  return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
465 }
466 
469  // This function is used for scheduling, and the nop wanted here is the type
470  // that terminates dispatch groups on the POWER cores.
471  unsigned Directive = Subtarget.getDarwinDirective();
472  unsigned Opcode;
473  switch (Directive) {
474  default: Opcode = PPC::NOP; break;
475  case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
476  case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
477  case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */
478  // FIXME: Update when POWER9 scheduling model is ready.
479  case PPC::DIR_PWR9: Opcode = PPC::NOP_GT_PWR7; break;
480  }
481 
482  DebugLoc DL;
483  BuildMI(MBB, MI, DL, get(Opcode));
484 }
485 
486 /// Return the noop instruction to use for a noop.
487 void PPCInstrInfo::getNoop(MCInst &NopInst) const {
488  NopInst.setOpcode(PPC::NOP);
489 }
490 
491 // Branch analysis.
492 // Note: If the condition register is set to CTR or CTR8 then this is a
493 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
495  MachineBasicBlock *&TBB,
496  MachineBasicBlock *&FBB,
498  bool AllowModify) const {
499  bool isPPC64 = Subtarget.isPPC64();
500 
501  // If the block has no terminators, it just falls into the block after it.
503  if (I == MBB.end())
504  return false;
505 
506  if (!isUnpredicatedTerminator(*I))
507  return false;
508 
509  if (AllowModify) {
510  // If the BB ends with an unconditional branch to the fallthrough BB,
511  // we eliminate the branch instruction.
512  if (I->getOpcode() == PPC::B &&
513  MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
514  I->eraseFromParent();
515 
516  // We update iterator after deleting the last branch.
517  I = MBB.getLastNonDebugInstr();
518  if (I == MBB.end() || !isUnpredicatedTerminator(*I))
519  return false;
520  }
521  }
522 
523  // Get the last instruction in the block.
524  MachineInstr &LastInst = *I;
525 
526  // If there is only one terminator instruction, process it.
527  if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
528  if (LastInst.getOpcode() == PPC::B) {
529  if (!LastInst.getOperand(0).isMBB())
530  return true;
531  TBB = LastInst.getOperand(0).getMBB();
532  return false;
533  } else if (LastInst.getOpcode() == PPC::BCC) {
534  if (!LastInst.getOperand(2).isMBB())
535  return true;
536  // Block ends with fall-through condbranch.
537  TBB = LastInst.getOperand(2).getMBB();
538  Cond.push_back(LastInst.getOperand(0));
539  Cond.push_back(LastInst.getOperand(1));
540  return false;
541  } else if (LastInst.getOpcode() == PPC::BC) {
542  if (!LastInst.getOperand(1).isMBB())
543  return true;
544  // Block ends with fall-through condbranch.
545  TBB = LastInst.getOperand(1).getMBB();
547  Cond.push_back(LastInst.getOperand(0));
548  return false;
549  } else if (LastInst.getOpcode() == PPC::BCn) {
550  if (!LastInst.getOperand(1).isMBB())
551  return true;
552  // Block ends with fall-through condbranch.
553  TBB = LastInst.getOperand(1).getMBB();
555  Cond.push_back(LastInst.getOperand(0));
556  return false;
557  } else if (LastInst.getOpcode() == PPC::BDNZ8 ||
558  LastInst.getOpcode() == PPC::BDNZ) {
559  if (!LastInst.getOperand(0).isMBB())
560  return true;
561  if (DisableCTRLoopAnal)
562  return true;
563  TBB = LastInst.getOperand(0).getMBB();
565  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
566  true));
567  return false;
568  } else if (LastInst.getOpcode() == PPC::BDZ8 ||
569  LastInst.getOpcode() == PPC::BDZ) {
570  if (!LastInst.getOperand(0).isMBB())
571  return true;
572  if (DisableCTRLoopAnal)
573  return true;
574  TBB = LastInst.getOperand(0).getMBB();
576  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
577  true));
578  return false;
579  }
580 
581  // Otherwise, don't know what this is.
582  return true;
583  }
584 
585  // Get the instruction before it if it's a terminator.
586  MachineInstr &SecondLastInst = *I;
587 
588  // If there are three terminators, we don't know what sort of block this is.
589  if (I != MBB.begin() && isUnpredicatedTerminator(*--I))
590  return true;
591 
592  // If the block ends with PPC::B and PPC:BCC, handle it.
593  if (SecondLastInst.getOpcode() == PPC::BCC &&
594  LastInst.getOpcode() == PPC::B) {
595  if (!SecondLastInst.getOperand(2).isMBB() ||
596  !LastInst.getOperand(0).isMBB())
597  return true;
598  TBB = SecondLastInst.getOperand(2).getMBB();
599  Cond.push_back(SecondLastInst.getOperand(0));
600  Cond.push_back(SecondLastInst.getOperand(1));
601  FBB = LastInst.getOperand(0).getMBB();
602  return false;
603  } else if (SecondLastInst.getOpcode() == PPC::BC &&
604  LastInst.getOpcode() == PPC::B) {
605  if (!SecondLastInst.getOperand(1).isMBB() ||
606  !LastInst.getOperand(0).isMBB())
607  return true;
608  TBB = SecondLastInst.getOperand(1).getMBB();
610  Cond.push_back(SecondLastInst.getOperand(0));
611  FBB = LastInst.getOperand(0).getMBB();
612  return false;
613  } else if (SecondLastInst.getOpcode() == PPC::BCn &&
614  LastInst.getOpcode() == PPC::B) {
615  if (!SecondLastInst.getOperand(1).isMBB() ||
616  !LastInst.getOperand(0).isMBB())
617  return true;
618  TBB = SecondLastInst.getOperand(1).getMBB();
620  Cond.push_back(SecondLastInst.getOperand(0));
621  FBB = LastInst.getOperand(0).getMBB();
622  return false;
623  } else if ((SecondLastInst.getOpcode() == PPC::BDNZ8 ||
624  SecondLastInst.getOpcode() == PPC::BDNZ) &&
625  LastInst.getOpcode() == PPC::B) {
626  if (!SecondLastInst.getOperand(0).isMBB() ||
627  !LastInst.getOperand(0).isMBB())
628  return true;
629  if (DisableCTRLoopAnal)
630  return true;
631  TBB = SecondLastInst.getOperand(0).getMBB();
633  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
634  true));
635  FBB = LastInst.getOperand(0).getMBB();
636  return false;
637  } else if ((SecondLastInst.getOpcode() == PPC::BDZ8 ||
638  SecondLastInst.getOpcode() == PPC::BDZ) &&
639  LastInst.getOpcode() == PPC::B) {
640  if (!SecondLastInst.getOperand(0).isMBB() ||
641  !LastInst.getOperand(0).isMBB())
642  return true;
643  if (DisableCTRLoopAnal)
644  return true;
645  TBB = SecondLastInst.getOperand(0).getMBB();
647  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
648  true));
649  FBB = LastInst.getOperand(0).getMBB();
650  return false;
651  }
652 
653  // If the block ends with two PPC:Bs, handle it. The second one is not
654  // executed, so remove it.
655  if (SecondLastInst.getOpcode() == PPC::B && LastInst.getOpcode() == PPC::B) {
656  if (!SecondLastInst.getOperand(0).isMBB())
657  return true;
658  TBB = SecondLastInst.getOperand(0).getMBB();
659  I = LastInst;
660  if (AllowModify)
661  I->eraseFromParent();
662  return false;
663  }
664 
665  // Otherwise, can't handle this.
666  return true;
667 }
668 
670  int *BytesRemoved) const {
671  assert(!BytesRemoved && "code size not handled");
672 
674  if (I == MBB.end())
675  return 0;
676 
677  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
678  I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
679  I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
680  I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
681  return 0;
682 
683  // Remove the branch.
684  I->eraseFromParent();
685 
686  I = MBB.end();
687 
688  if (I == MBB.begin()) return 1;
689  --I;
690  if (I->getOpcode() != PPC::BCC &&
691  I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
692  I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
693  I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
694  return 1;
695 
696  // Remove the branch.
697  I->eraseFromParent();
698  return 2;
699 }
700 
702  MachineBasicBlock *TBB,
703  MachineBasicBlock *FBB,
705  const DebugLoc &DL,
706  int *BytesAdded) const {
707  // Shouldn't be a fall through.
708  assert(TBB && "insertBranch must not be told to insert a fallthrough");
709  assert((Cond.size() == 2 || Cond.size() == 0) &&
710  "PPC branch conditions have two components!");
711  assert(!BytesAdded && "code size not handled");
712 
713  bool isPPC64 = Subtarget.isPPC64();
714 
715  // One-way branch.
716  if (!FBB) {
717  if (Cond.empty()) // Unconditional branch
718  BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
719  else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
720  BuildMI(&MBB, DL, get(Cond[0].getImm() ?
721  (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
722  (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
723  else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
724  BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
725  else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
726  BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
727  else // Conditional branch
728  BuildMI(&MBB, DL, get(PPC::BCC))
729  .addImm(Cond[0].getImm())
730  .add(Cond[1])
731  .addMBB(TBB);
732  return 1;
733  }
734 
735  // Two-way Conditional Branch.
736  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
737  BuildMI(&MBB, DL, get(Cond[0].getImm() ?
738  (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
739  (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
740  else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
741  BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
742  else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
743  BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
744  else
745  BuildMI(&MBB, DL, get(PPC::BCC))
746  .addImm(Cond[0].getImm())
747  .add(Cond[1])
748  .addMBB(TBB);
749  BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
750  return 2;
751 }
752 
753 // Select analysis.
756  unsigned TrueReg, unsigned FalseReg,
757  int &CondCycles, int &TrueCycles, int &FalseCycles) const {
758  if (Cond.size() != 2)
759  return false;
760 
761  // If this is really a bdnz-like condition, then it cannot be turned into a
762  // select.
763  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
764  return false;
765 
766  // Check register classes.
767  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
768  const TargetRegisterClass *RC =
769  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
770  if (!RC)
771  return false;
772 
773  // isel is for regular integer GPRs only.
774  if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
775  !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
776  !PPC::G8RCRegClass.hasSubClassEq(RC) &&
777  !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
778  return false;
779 
780  // FIXME: These numbers are for the A2, how well they work for other cores is
781  // an open question. On the A2, the isel instruction has a 2-cycle latency
782  // but single-cycle throughput. These numbers are used in combination with
783  // the MispredictPenalty setting from the active SchedMachineModel.
784  CondCycles = 1;
785  TrueCycles = 1;
786  FalseCycles = 1;
787 
788  return true;
789 }
790 
793  const DebugLoc &dl, unsigned DestReg,
794  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
795  unsigned FalseReg) const {
796  assert(Cond.size() == 2 &&
797  "PPC branch conditions have two components!");
798 
799  // Get the register classes.
801  const TargetRegisterClass *RC =
802  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
803  assert(RC && "TrueReg and FalseReg must have overlapping register classes");
804 
805  bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
806  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
807  assert((Is64Bit ||
808  PPC::GPRCRegClass.hasSubClassEq(RC) ||
809  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
810  "isel is for regular integer GPRs only");
811 
812  unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
813  auto SelectPred = static_cast<PPC::Predicate>(Cond[0].getImm());
814 
815  unsigned SubIdx = 0;
816  bool SwapOps = false;
817  switch (SelectPred) {
818  case PPC::PRED_EQ:
819  case PPC::PRED_EQ_MINUS:
820  case PPC::PRED_EQ_PLUS:
821  SubIdx = PPC::sub_eq; SwapOps = false; break;
822  case PPC::PRED_NE:
823  case PPC::PRED_NE_MINUS:
824  case PPC::PRED_NE_PLUS:
825  SubIdx = PPC::sub_eq; SwapOps = true; break;
826  case PPC::PRED_LT:
827  case PPC::PRED_LT_MINUS:
828  case PPC::PRED_LT_PLUS:
829  SubIdx = PPC::sub_lt; SwapOps = false; break;
830  case PPC::PRED_GE:
831  case PPC::PRED_GE_MINUS:
832  case PPC::PRED_GE_PLUS:
833  SubIdx = PPC::sub_lt; SwapOps = true; break;
834  case PPC::PRED_GT:
835  case PPC::PRED_GT_MINUS:
836  case PPC::PRED_GT_PLUS:
837  SubIdx = PPC::sub_gt; SwapOps = false; break;
838  case PPC::PRED_LE:
839  case PPC::PRED_LE_MINUS:
840  case PPC::PRED_LE_PLUS:
841  SubIdx = PPC::sub_gt; SwapOps = true; break;
842  case PPC::PRED_UN:
843  case PPC::PRED_UN_MINUS:
844  case PPC::PRED_UN_PLUS:
845  SubIdx = PPC::sub_un; SwapOps = false; break;
846  case PPC::PRED_NU:
847  case PPC::PRED_NU_MINUS:
848  case PPC::PRED_NU_PLUS:
849  SubIdx = PPC::sub_un; SwapOps = true; break;
850  case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break;
851  case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break;
852  }
853 
854  unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
855  SecondReg = SwapOps ? TrueReg : FalseReg;
856 
857  // The first input register of isel cannot be r0. If it is a member
858  // of a register class that can be r0, then copy it first (the
859  // register allocator should eliminate the copy).
860  if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
861  MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
862  const TargetRegisterClass *FirstRC =
863  MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
864  &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
865  unsigned OldFirstReg = FirstReg;
866  FirstReg = MRI.createVirtualRegister(FirstRC);
867  BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
868  .addReg(OldFirstReg);
869  }
870 
871  BuildMI(MBB, MI, dl, get(OpCode), DestReg)
872  .addReg(FirstReg).addReg(SecondReg)
873  .addReg(Cond[1].getReg(), 0, SubIdx);
874 }
875 
876 static unsigned getCRBitValue(unsigned CRBit) {
877  unsigned Ret = 4;
878  if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT ||
879  CRBit == PPC::CR2LT || CRBit == PPC::CR3LT ||
880  CRBit == PPC::CR4LT || CRBit == PPC::CR5LT ||
881  CRBit == PPC::CR6LT || CRBit == PPC::CR7LT)
882  Ret = 3;
883  if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT ||
884  CRBit == PPC::CR2GT || CRBit == PPC::CR3GT ||
885  CRBit == PPC::CR4GT || CRBit == PPC::CR5GT ||
886  CRBit == PPC::CR6GT || CRBit == PPC::CR7GT)
887  Ret = 2;
888  if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ ||
889  CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ ||
890  CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ ||
891  CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ)
892  Ret = 1;
893  if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN ||
894  CRBit == PPC::CR2UN || CRBit == PPC::CR3UN ||
895  CRBit == PPC::CR4UN || CRBit == PPC::CR5UN ||
896  CRBit == PPC::CR6UN || CRBit == PPC::CR7UN)
897  Ret = 0;
898 
899  assert(Ret != 4 && "Invalid CR bit register");
900  return Ret;
901 }
902 
905  const DebugLoc &DL, unsigned DestReg,
906  unsigned SrcReg, bool KillSrc) const {
907  // We can end up with self copies and similar things as a result of VSX copy
908  // legalization. Promote them here.
910  if (PPC::F8RCRegClass.contains(DestReg) &&
911  PPC::VSRCRegClass.contains(SrcReg)) {
912  unsigned SuperReg =
913  TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
914 
915  if (VSXSelfCopyCrash && SrcReg == SuperReg)
916  llvm_unreachable("nop VSX copy");
917 
918  DestReg = SuperReg;
919  } else if (PPC::F8RCRegClass.contains(SrcReg) &&
920  PPC::VSRCRegClass.contains(DestReg)) {
921  unsigned SuperReg =
922  TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
923 
924  if (VSXSelfCopyCrash && DestReg == SuperReg)
925  llvm_unreachable("nop VSX copy");
926 
927  SrcReg = SuperReg;
928  }
929 
930  // Different class register copy
931  if (PPC::CRBITRCRegClass.contains(SrcReg) &&
932  PPC::GPRCRegClass.contains(DestReg)) {
933  unsigned CRReg = getCRFromCRBit(SrcReg);
934  BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg);
935  getKillRegState(KillSrc);
936  // Rotate the CR bit in the CR fields to be the least significant bit and
937  // then mask with 0x1 (MB = ME = 31).
938  BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
939  .addReg(DestReg, RegState::Kill)
940  .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
941  .addImm(31)
942  .addImm(31);
943  return;
944  } else if (PPC::CRRCRegClass.contains(SrcReg) &&
945  PPC::G8RCRegClass.contains(DestReg)) {
946  BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg).addReg(SrcReg);
947  getKillRegState(KillSrc);
948  return;
949  } else if (PPC::CRRCRegClass.contains(SrcReg) &&
950  PPC::GPRCRegClass.contains(DestReg)) {
951  BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(SrcReg);
952  getKillRegState(KillSrc);
953  return;
954  } else if (PPC::G8RCRegClass.contains(SrcReg) &&
955  PPC::VSFRCRegClass.contains(DestReg)) {
956  assert(Subtarget.hasDirectMove() &&
957  "Subtarget doesn't support directmove, don't know how to copy.");
958  BuildMI(MBB, I, DL, get(PPC::MTVSRD), DestReg).addReg(SrcReg);
959  NumGPRtoVSRSpill++;
960  getKillRegState(KillSrc);
961  return;
962  } else if (PPC::VSFRCRegClass.contains(SrcReg) &&
963  PPC::G8RCRegClass.contains(DestReg)) {
964  assert(Subtarget.hasDirectMove() &&
965  "Subtarget doesn't support directmove, don't know how to copy.");
966  BuildMI(MBB, I, DL, get(PPC::MFVSRD), DestReg).addReg(SrcReg);
967  getKillRegState(KillSrc);
968  return;
969  } else if (PPC::SPERCRegClass.contains(SrcReg) &&
970  PPC::SPE4RCRegClass.contains(DestReg)) {
971  BuildMI(MBB, I, DL, get(PPC::EFSCFD), DestReg).addReg(SrcReg);
972  getKillRegState(KillSrc);
973  return;
974  } else if (PPC::SPE4RCRegClass.contains(SrcReg) &&
975  PPC::SPERCRegClass.contains(DestReg)) {
976  BuildMI(MBB, I, DL, get(PPC::EFDCFS), DestReg).addReg(SrcReg);
977  getKillRegState(KillSrc);
978  return;
979  }
980 
981  unsigned Opc;
982  if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
983  Opc = PPC::OR;
984  else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
985  Opc = PPC::OR8;
986  else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
987  Opc = PPC::FMR;
988  else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
989  Opc = PPC::MCRF;
990  else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
991  Opc = PPC::VOR;
992  else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
993  // There are two different ways this can be done:
994  // 1. xxlor : This has lower latency (on the P7), 2 cycles, but can only
995  // issue in VSU pipeline 0.
996  // 2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
997  // can go to either pipeline.
998  // We'll always use xxlor here, because in practically all cases where
999  // copies are generated, they are close enough to some use that the
1000  // lower-latency form is preferable.
1001  Opc = PPC::XXLOR;
1002  else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) ||
1003  PPC::VSSRCRegClass.contains(DestReg, SrcReg))
1004  Opc = (Subtarget.hasP9Vector()) ? PPC::XSCPSGNDP : PPC::XXLORf;
1005  else if (PPC::QFRCRegClass.contains(DestReg, SrcReg))
1006  Opc = PPC::QVFMR;
1007  else if (PPC::QSRCRegClass.contains(DestReg, SrcReg))
1008  Opc = PPC::QVFMRs;
1009  else if (PPC::QBRCRegClass.contains(DestReg, SrcReg))
1010  Opc = PPC::QVFMRb;
1011  else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
1012  Opc = PPC::CROR;
1013  else if (PPC::SPE4RCRegClass.contains(DestReg, SrcReg))
1014  Opc = PPC::OR;
1015  else if (PPC::SPERCRegClass.contains(DestReg, SrcReg))
1016  Opc = PPC::EVOR;
1017  else
1018  llvm_unreachable("Impossible reg-to-reg copy");
1019 
1020  const MCInstrDesc &MCID = get(Opc);
1021  if (MCID.getNumOperands() == 3)
1022  BuildMI(MBB, I, DL, MCID, DestReg)
1023  .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
1024  else
1025  BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
1026 }
1027 
1029  const TargetRegisterClass *RC)
1030  const {
1031  const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
1032  int OpcodeIndex = 0;
1033 
1034  if (RC != nullptr) {
1035  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1036  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1037  OpcodeIndex = SOK_Int4Spill;
1038  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1039  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1040  OpcodeIndex = SOK_Int8Spill;
1041  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1042  OpcodeIndex = SOK_Float8Spill;
1043  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1044  OpcodeIndex = SOK_Float4Spill;
1045  } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1046  OpcodeIndex = SOK_SPESpill;
1047  } else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) {
1048  OpcodeIndex = SOK_SPE4Spill;
1049  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1050  OpcodeIndex = SOK_CRSpill;
1051  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1052  OpcodeIndex = SOK_CRBitSpill;
1053  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1054  OpcodeIndex = SOK_VRVectorSpill;
1055  } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1056  OpcodeIndex = SOK_VSXVectorSpill;
1057  } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1058  OpcodeIndex = SOK_VectorFloat8Spill;
1059  } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1060  OpcodeIndex = SOK_VectorFloat4Spill;
1061  } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1062  OpcodeIndex = SOK_VRSaveSpill;
1063  } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1064  OpcodeIndex = SOK_QuadFloat8Spill;
1065  } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1066  OpcodeIndex = SOK_QuadFloat4Spill;
1067  } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1068  OpcodeIndex = SOK_QuadBitSpill;
1069  } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1070  OpcodeIndex = SOK_SpillToVSR;
1071  } else {
1072  llvm_unreachable("Unknown regclass!");
1073  }
1074  } else {
1075  if (PPC::GPRCRegClass.contains(Reg) ||
1076  PPC::GPRC_NOR0RegClass.contains(Reg)) {
1077  OpcodeIndex = SOK_Int4Spill;
1078  } else if (PPC::G8RCRegClass.contains(Reg) ||
1079  PPC::G8RC_NOX0RegClass.contains(Reg)) {
1080  OpcodeIndex = SOK_Int8Spill;
1081  } else if (PPC::F8RCRegClass.contains(Reg)) {
1082  OpcodeIndex = SOK_Float8Spill;
1083  } else if (PPC::F4RCRegClass.contains(Reg)) {
1084  OpcodeIndex = SOK_Float4Spill;
1085  } else if (PPC::SPERCRegClass.contains(Reg)) {
1086  OpcodeIndex = SOK_SPESpill;
1087  } else if (PPC::SPE4RCRegClass.contains(Reg)) {
1088  OpcodeIndex = SOK_SPE4Spill;
1089  } else if (PPC::CRRCRegClass.contains(Reg)) {
1090  OpcodeIndex = SOK_CRSpill;
1091  } else if (PPC::CRBITRCRegClass.contains(Reg)) {
1092  OpcodeIndex = SOK_CRBitSpill;
1093  } else if (PPC::VRRCRegClass.contains(Reg)) {
1094  OpcodeIndex = SOK_VRVectorSpill;
1095  } else if (PPC::VSRCRegClass.contains(Reg)) {
1096  OpcodeIndex = SOK_VSXVectorSpill;
1097  } else if (PPC::VSFRCRegClass.contains(Reg)) {
1098  OpcodeIndex = SOK_VectorFloat8Spill;
1099  } else if (PPC::VSSRCRegClass.contains(Reg)) {
1100  OpcodeIndex = SOK_VectorFloat4Spill;
1101  } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1102  OpcodeIndex = SOK_VRSaveSpill;
1103  } else if (PPC::QFRCRegClass.contains(Reg)) {
1104  OpcodeIndex = SOK_QuadFloat8Spill;
1105  } else if (PPC::QSRCRegClass.contains(Reg)) {
1106  OpcodeIndex = SOK_QuadFloat4Spill;
1107  } else if (PPC::QBRCRegClass.contains(Reg)) {
1108  OpcodeIndex = SOK_QuadBitSpill;
1109  } else if (PPC::SPILLTOVSRRCRegClass.contains(Reg)) {
1110  OpcodeIndex = SOK_SpillToVSR;
1111  } else {
1112  llvm_unreachable("Unknown regclass!");
1113  }
1114  }
1115  return OpcodesForSpill[OpcodeIndex];
1116 }
1117 
1118 unsigned
1120  const TargetRegisterClass *RC) const {
1121  const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
1122  int OpcodeIndex = 0;
1123 
1124  if (RC != nullptr) {
1125  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1126  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1127  OpcodeIndex = SOK_Int4Spill;
1128  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1129  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1130  OpcodeIndex = SOK_Int8Spill;
1131  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1132  OpcodeIndex = SOK_Float8Spill;
1133  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1134  OpcodeIndex = SOK_Float4Spill;
1135  } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1136  OpcodeIndex = SOK_SPESpill;
1137  } else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) {
1138  OpcodeIndex = SOK_SPE4Spill;
1139  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1140  OpcodeIndex = SOK_CRSpill;
1141  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1142  OpcodeIndex = SOK_CRBitSpill;
1143  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1144  OpcodeIndex = SOK_VRVectorSpill;
1145  } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1146  OpcodeIndex = SOK_VSXVectorSpill;
1147  } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1148  OpcodeIndex = SOK_VectorFloat8Spill;
1149  } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1150  OpcodeIndex = SOK_VectorFloat4Spill;
1151  } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1152  OpcodeIndex = SOK_VRSaveSpill;
1153  } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1154  OpcodeIndex = SOK_QuadFloat8Spill;
1155  } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1156  OpcodeIndex = SOK_QuadFloat4Spill;
1157  } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1158  OpcodeIndex = SOK_QuadBitSpill;
1159  } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1160  OpcodeIndex = SOK_SpillToVSR;
1161  } else {
1162  llvm_unreachable("Unknown regclass!");
1163  }
1164  } else {
1165  if (PPC::GPRCRegClass.contains(Reg) ||
1166  PPC::GPRC_NOR0RegClass.contains(Reg)) {
1167  OpcodeIndex = SOK_Int4Spill;
1168  } else if (PPC::G8RCRegClass.contains(Reg) ||
1169  PPC::G8RC_NOX0RegClass.contains(Reg)) {
1170  OpcodeIndex = SOK_Int8Spill;
1171  } else if (PPC::F8RCRegClass.contains(Reg)) {
1172  OpcodeIndex = SOK_Float8Spill;
1173  } else if (PPC::F4RCRegClass.contains(Reg)) {
1174  OpcodeIndex = SOK_Float4Spill;
1175  } else if (PPC::SPERCRegClass.contains(Reg)) {
1176  OpcodeIndex = SOK_SPESpill;
1177  } else if (PPC::SPE4RCRegClass.contains(Reg)) {
1178  OpcodeIndex = SOK_SPE4Spill;
1179  } else if (PPC::CRRCRegClass.contains(Reg)) {
1180  OpcodeIndex = SOK_CRSpill;
1181  } else if (PPC::CRBITRCRegClass.contains(Reg)) {
1182  OpcodeIndex = SOK_CRBitSpill;
1183  } else if (PPC::VRRCRegClass.contains(Reg)) {
1184  OpcodeIndex = SOK_VRVectorSpill;
1185  } else if (PPC::VSRCRegClass.contains(Reg)) {
1186  OpcodeIndex = SOK_VSXVectorSpill;
1187  } else if (PPC::VSFRCRegClass.contains(Reg)) {
1188  OpcodeIndex = SOK_VectorFloat8Spill;
1189  } else if (PPC::VSSRCRegClass.contains(Reg)) {
1190  OpcodeIndex = SOK_VectorFloat4Spill;
1191  } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1192  OpcodeIndex = SOK_VRSaveSpill;
1193  } else if (PPC::QFRCRegClass.contains(Reg)) {
1194  OpcodeIndex = SOK_QuadFloat8Spill;
1195  } else if (PPC::QSRCRegClass.contains(Reg)) {
1196  OpcodeIndex = SOK_QuadFloat4Spill;
1197  } else if (PPC::QBRCRegClass.contains(Reg)) {
1198  OpcodeIndex = SOK_QuadBitSpill;
1199  } else if (PPC::SPILLTOVSRRCRegClass.contains(Reg)) {
1200  OpcodeIndex = SOK_SpillToVSR;
1201  } else {
1202  llvm_unreachable("Unknown regclass!");
1203  }
1204  }
1205  return OpcodesForSpill[OpcodeIndex];
1206 }
1207 
1208 void PPCInstrInfo::StoreRegToStackSlot(
1209  MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx,
1210  const TargetRegisterClass *RC,
1211  SmallVectorImpl<MachineInstr *> &NewMIs) const {
1212  unsigned Opcode = getStoreOpcodeForSpill(PPC::NoRegister, RC);
1213  DebugLoc DL;
1214 
1215  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1216  FuncInfo->setHasSpills();
1217 
1219  BuildMI(MF, DL, get(Opcode)).addReg(SrcReg, getKillRegState(isKill)),
1220  FrameIdx));
1221 
1222  if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1223  PPC::CRBITRCRegClass.hasSubClassEq(RC))
1224  FuncInfo->setSpillsCR();
1225 
1226  if (PPC::VRSAVERCRegClass.hasSubClassEq(RC))
1227  FuncInfo->setSpillsVRSAVE();
1228 
1229  if (isXFormMemOp(Opcode))
1230  FuncInfo->setHasNonRISpills();
1231 }
1232 
1235  unsigned SrcReg, bool isKill,
1236  int FrameIdx,
1237  const TargetRegisterClass *RC,
1238  const TargetRegisterInfo *TRI) const {
1239  MachineFunction &MF = *MBB.getParent();
1241 
1242  // We need to avoid a situation in which the value from a VRRC register is
1243  // spilled using an Altivec instruction and reloaded into a VSRC register
1244  // using a VSX instruction. The issue with this is that the VSX
1245  // load/store instructions swap the doublewords in the vector and the Altivec
1246  // ones don't. The register classes on the spill/reload may be different if
1247  // the register is defined using an Altivec instruction and is then used by a
1248  // VSX instruction.
1249  RC = updatedRC(RC);
1250 
1251  StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs);
1252 
1253  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1254  MBB.insert(MI, NewMIs[i]);
1255 
1256  const MachineFrameInfo &MFI = MF.getFrameInfo();
1258  MachinePointerInfo::getFixedStack(MF, FrameIdx),
1260  MFI.getObjectAlignment(FrameIdx));
1261  NewMIs.back()->addMemOperand(MF, MMO);
1262 }
1263 
1264 void PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
1265  unsigned DestReg, int FrameIdx,
1266  const TargetRegisterClass *RC,
1268  const {
1269  unsigned Opcode = getLoadOpcodeForSpill(PPC::NoRegister, RC);
1270  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opcode), DestReg),
1271  FrameIdx));
1272  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1273 
1274  if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1275  PPC::CRBITRCRegClass.hasSubClassEq(RC))
1276  FuncInfo->setSpillsCR();
1277 
1278  if (PPC::VRSAVERCRegClass.hasSubClassEq(RC))
1279  FuncInfo->setSpillsVRSAVE();
1280 
1281  if (isXFormMemOp(Opcode))
1282  FuncInfo->setHasNonRISpills();
1283 }
1284 
1285 void
1288  unsigned DestReg, int FrameIdx,
1289  const TargetRegisterClass *RC,
1290  const TargetRegisterInfo *TRI) const {
1291  MachineFunction &MF = *MBB.getParent();
1293  DebugLoc DL;
1294  if (MI != MBB.end()) DL = MI->getDebugLoc();
1295 
1296  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1297  FuncInfo->setHasSpills();
1298 
1299  // We need to avoid a situation in which the value from a VRRC register is
1300  // spilled using an Altivec instruction and reloaded into a VSRC register
1301  // using a VSX instruction. The issue with this is that the VSX
1302  // load/store instructions swap the doublewords in the vector and the Altivec
1303  // ones don't. The register classes on the spill/reload may be different if
1304  // the register is defined using an Altivec instruction and is then used by a
1305  // VSX instruction.
1306  if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
1307  RC = &PPC::VSRCRegClass;
1308 
1309  LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
1310 
1311  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1312  MBB.insert(MI, NewMIs[i]);
1313 
1314  const MachineFrameInfo &MFI = MF.getFrameInfo();
1316  MachinePointerInfo::getFixedStack(MF, FrameIdx),
1318  MFI.getObjectAlignment(FrameIdx));
1319  NewMIs.back()->addMemOperand(MF, MMO);
1320 }
1321 
1322 bool PPCInstrInfo::
1324  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
1325  if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
1326  Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
1327  else
1328  // Leave the CR# the same, but invert the condition.
1329  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
1330  return false;
1331 }
1332 
1334  unsigned Reg, MachineRegisterInfo *MRI) const {
1335  // For some instructions, it is legal to fold ZERO into the RA register field.
1336  // A zero immediate should always be loaded with a single li.
1337  unsigned DefOpc = DefMI.getOpcode();
1338  if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
1339  return false;
1340  if (!DefMI.getOperand(1).isImm())
1341  return false;
1342  if (DefMI.getOperand(1).getImm() != 0)
1343  return false;
1344 
1345  // Note that we cannot here invert the arguments of an isel in order to fold
1346  // a ZERO into what is presented as the second argument. All we have here
1347  // is the condition bit, and that might come from a CR-logical bit operation.
1348 
1349  const MCInstrDesc &UseMCID = UseMI.getDesc();
1350 
1351  // Only fold into real machine instructions.
1352  if (UseMCID.isPseudo())
1353  return false;
1354 
1355  unsigned UseIdx;
1356  for (UseIdx = 0; UseIdx < UseMI.getNumOperands(); ++UseIdx)
1357  if (UseMI.getOperand(UseIdx).isReg() &&
1358  UseMI.getOperand(UseIdx).getReg() == Reg)
1359  break;
1360 
1361  assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI");
1362  assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
1363 
1364  const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
1365 
1366  // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
1367  // register (which might also be specified as a pointer class kind).
1368  if (UseInfo->isLookupPtrRegClass()) {
1369  if (UseInfo->RegClass /* Kind */ != 1)
1370  return false;
1371  } else {
1372  if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
1373  UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
1374  return false;
1375  }
1376 
1377  // Make sure this is not tied to an output register (or otherwise
1378  // constrained). This is true for ST?UX registers, for example, which
1379  // are tied to their output registers.
1380  if (UseInfo->Constraints != 0)
1381  return false;
1382 
1383  unsigned ZeroReg;
1384  if (UseInfo->isLookupPtrRegClass()) {
1385  bool isPPC64 = Subtarget.isPPC64();
1386  ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
1387  } else {
1388  ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
1389  PPC::ZERO8 : PPC::ZERO;
1390  }
1391 
1392  bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1393  UseMI.getOperand(UseIdx).setReg(ZeroReg);
1394 
1395  if (DeleteDef)
1396  DefMI.eraseFromParent();
1397 
1398  return true;
1399 }
1400 
1402  for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
1403  I != IE; ++I)
1404  if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
1405  return true;
1406  return false;
1407 }
1408 
1409 // We should make sure that, if we're going to predicate both sides of a
1410 // condition (a diamond), that both sides don't define the counter register. We
1411 // can predicate counter-decrement-based branches, but while that predicates
1412 // the branching, it does not predicate the counter decrement. If we tried to
1413 // merge the triangle into one predicated block, we'd decrement the counter
1414 // twice.
1416  unsigned NumT, unsigned ExtraT,
1417  MachineBasicBlock &FMBB,
1418  unsigned NumF, unsigned ExtraF,
1419  BranchProbability Probability) const {
1420  return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
1421 }
1422 
1423 
1425  // The predicated branches are identified by their type, not really by the
1426  // explicit presence of a predicate. Furthermore, some of them can be
1427  // predicated more than once. Because if conversion won't try to predicate
1428  // any instruction which already claims to be predicated (by returning true
1429  // here), always return false. In doing so, we let isPredicable() be the
1430  // final word on whether not the instruction can be (further) predicated.
1431 
1432  return false;
1433 }
1434 
1436  if (!MI.isTerminator())
1437  return false;
1438 
1439  // Conditional branch is a special case.
1440  if (MI.isBranch() && !MI.isBarrier())
1441  return true;
1442 
1443  return !isPredicated(MI);
1444 }
1445 
1447  ArrayRef<MachineOperand> Pred) const {
1448  unsigned OpC = MI.getOpcode();
1449  if (OpC == PPC::BLR || OpC == PPC::BLR8) {
1450  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1451  bool isPPC64 = Subtarget.isPPC64();
1452  MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR)
1453  : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
1454  } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1455  MI.setDesc(get(PPC::BCLR));
1456  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1457  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1458  MI.setDesc(get(PPC::BCLRn));
1459  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1460  } else {
1461  MI.setDesc(get(PPC::BCCLR));
1463  .addImm(Pred[0].getImm())
1464  .add(Pred[1]);
1465  }
1466 
1467  return true;
1468  } else if (OpC == PPC::B) {
1469  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1470  bool isPPC64 = Subtarget.isPPC64();
1471  MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
1472  : (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
1473  } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1474  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1475  MI.RemoveOperand(0);
1476 
1477  MI.setDesc(get(PPC::BC));
1479  .add(Pred[1])
1480  .addMBB(MBB);
1481  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1482  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1483  MI.RemoveOperand(0);
1484 
1485  MI.setDesc(get(PPC::BCn));
1487  .add(Pred[1])
1488  .addMBB(MBB);
1489  } else {
1490  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1491  MI.RemoveOperand(0);
1492 
1493  MI.setDesc(get(PPC::BCC));
1495  .addImm(Pred[0].getImm())
1496  .add(Pred[1])
1497  .addMBB(MBB);
1498  }
1499 
1500  return true;
1501  } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 || OpC == PPC::BCTRL ||
1502  OpC == PPC::BCTRL8) {
1503  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
1504  llvm_unreachable("Cannot predicate bctr[l] on the ctr register");
1505 
1506  bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
1507  bool isPPC64 = Subtarget.isPPC64();
1508 
1509  if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1510  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8)
1511  : (setLR ? PPC::BCCTRL : PPC::BCCTR)));
1512  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1513  return true;
1514  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1515  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n)
1516  : (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
1517  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1518  return true;
1519  }
1520 
1521  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8)
1522  : (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
1524  .addImm(Pred[0].getImm())
1525  .add(Pred[1]);
1526  return true;
1527  }
1528 
1529  return false;
1530 }
1531 
1533  ArrayRef<MachineOperand> Pred2) const {
1534  assert(Pred1.size() == 2 && "Invalid PPC first predicate");
1535  assert(Pred2.size() == 2 && "Invalid PPC second predicate");
1536 
1537  if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1538  return false;
1539  if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
1540  return false;
1541 
1542  // P1 can only subsume P2 if they test the same condition register.
1543  if (Pred1[1].getReg() != Pred2[1].getReg())
1544  return false;
1545 
1546  PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
1547  PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
1548 
1549  if (P1 == P2)
1550  return true;
1551 
1552  // Does P1 subsume P2, e.g. GE subsumes GT.
1553  if (P1 == PPC::PRED_LE &&
1554  (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
1555  return true;
1556  if (P1 == PPC::PRED_GE &&
1557  (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
1558  return true;
1559 
1560  return false;
1561 }
1562 
1564  std::vector<MachineOperand> &Pred) const {
1565  // Note: At the present time, the contents of Pred from this function is
1566  // unused by IfConversion. This implementation follows ARM by pushing the
1567  // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
1568  // predicate, instructions defining CTR or CTR8 are also included as
1569  // predicate-defining instructions.
1570 
1571  const TargetRegisterClass *RCs[] =
1572  { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1573  &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1574 
1575  bool Found = false;
1576  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1577  const MachineOperand &MO = MI.getOperand(i);
1578  for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
1579  const TargetRegisterClass *RC = RCs[c];
1580  if (MO.isReg()) {
1581  if (MO.isDef() && RC->contains(MO.getReg())) {
1582  Pred.push_back(MO);
1583  Found = true;
1584  }
1585  } else if (MO.isRegMask()) {
1586  for (TargetRegisterClass::iterator I = RC->begin(),
1587  IE = RC->end(); I != IE; ++I)
1588  if (MO.clobbersPhysReg(*I)) {
1589  Pred.push_back(MO);
1590  Found = true;
1591  }
1592  }
1593  }
1594  }
1595 
1596  return Found;
1597 }
1598 
1600  unsigned OpC = MI.getOpcode();
1601  switch (OpC) {
1602  default:
1603  return false;
1604  case PPC::B:
1605  case PPC::BLR:
1606  case PPC::BLR8:
1607  case PPC::BCTR:
1608  case PPC::BCTR8:
1609  case PPC::BCTRL:
1610  case PPC::BCTRL8:
1611  return true;
1612  }
1613 }
1614 
1615 bool PPCInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1616  unsigned &SrcReg2, int &Mask,
1617  int &Value) const {
1618  unsigned Opc = MI.getOpcode();
1619 
1620  switch (Opc) {
1621  default: return false;
1622  case PPC::CMPWI:
1623  case PPC::CMPLWI:
1624  case PPC::CMPDI:
1625  case PPC::CMPLDI:
1626  SrcReg = MI.getOperand(1).getReg();
1627  SrcReg2 = 0;
1628  Value = MI.getOperand(2).getImm();
1629  Mask = 0xFFFF;
1630  return true;
1631  case PPC::CMPW:
1632  case PPC::CMPLW:
1633  case PPC::CMPD:
1634  case PPC::CMPLD:
1635  case PPC::FCMPUS:
1636  case PPC::FCMPUD:
1637  SrcReg = MI.getOperand(1).getReg();
1638  SrcReg2 = MI.getOperand(2).getReg();
1639  Value = 0;
1640  Mask = 0;
1641  return true;
1642  }
1643 }
1644 
1645 bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1646  unsigned SrcReg2, int Mask, int Value,
1647  const MachineRegisterInfo *MRI) const {
1648  if (DisableCmpOpt)
1649  return false;
1650 
1651  int OpC = CmpInstr.getOpcode();
1652  Register CRReg = CmpInstr.getOperand(0).getReg();
1653 
1654  // FP record forms set CR1 based on the exception status bits, not a
1655  // comparison with zero.
1656  if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
1657  return false;
1658 
1660  // The record forms set the condition register based on a signed comparison
1661  // with zero (so says the ISA manual). This is not as straightforward as it
1662  // seems, however, because this is always a 64-bit comparison on PPC64, even
1663  // for instructions that are 32-bit in nature (like slw for example).
1664  // So, on PPC32, for unsigned comparisons, we can use the record forms only
1665  // for equality checks (as those don't depend on the sign). On PPC64,
1666  // we are restricted to equality for unsigned 64-bit comparisons and for
1667  // signed 32-bit comparisons the applicability is more restricted.
1668  bool isPPC64 = Subtarget.isPPC64();
1669  bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
1670  bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
1671  bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
1672 
1673  // Look through copies unless that gets us to a physical register.
1674  unsigned ActualSrc = TRI->lookThruCopyLike(SrcReg, MRI);
1675  if (Register::isVirtualRegister(ActualSrc))
1676  SrcReg = ActualSrc;
1677 
1678  // Get the unique definition of SrcReg.
1679  MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1680  if (!MI) return false;
1681 
1682  bool equalityOnly = false;
1683  bool noSub = false;
1684  if (isPPC64) {
1685  if (is32BitSignedCompare) {
1686  // We can perform this optimization only if MI is sign-extending.
1687  if (isSignExtended(*MI))
1688  noSub = true;
1689  else
1690  return false;
1691  } else if (is32BitUnsignedCompare) {
1692  // We can perform this optimization, equality only, if MI is
1693  // zero-extending.
1694  if (isZeroExtended(*MI)) {
1695  noSub = true;
1696  equalityOnly = true;
1697  } else
1698  return false;
1699  } else
1700  equalityOnly = is64BitUnsignedCompare;
1701  } else
1702  equalityOnly = is32BitUnsignedCompare;
1703 
1704  if (equalityOnly) {
1705  // We need to check the uses of the condition register in order to reject
1706  // non-equality comparisons.
1708  I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1709  I != IE; ++I) {
1710  MachineInstr *UseMI = &*I;
1711  if (UseMI->getOpcode() == PPC::BCC) {
1712  PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
1713  unsigned PredCond = PPC::getPredicateCondition(Pred);
1714  // We ignore hint bits when checking for non-equality comparisons.
1715  if (PredCond != PPC::PRED_EQ && PredCond != PPC::PRED_NE)
1716  return false;
1717  } else if (UseMI->getOpcode() == PPC::ISEL ||
1718  UseMI->getOpcode() == PPC::ISEL8) {
1719  unsigned SubIdx = UseMI->getOperand(3).getSubReg();
1720  if (SubIdx != PPC::sub_eq)
1721  return false;
1722  } else
1723  return false;
1724  }
1725  }
1726 
1727  MachineBasicBlock::iterator I = CmpInstr;
1728 
1729  // Scan forward to find the first use of the compare.
1730  for (MachineBasicBlock::iterator EL = CmpInstr.getParent()->end(); I != EL;
1731  ++I) {
1732  bool FoundUse = false;
1734  J = MRI->use_instr_begin(CRReg), JE = MRI->use_instr_end();
1735  J != JE; ++J)
1736  if (&*J == &*I) {
1737  FoundUse = true;
1738  break;
1739  }
1740 
1741  if (FoundUse)
1742  break;
1743  }
1744 
1747 
1748  // There are two possible candidates which can be changed to set CR[01].
1749  // One is MI, the other is a SUB instruction.
1750  // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
1751  MachineInstr *Sub = nullptr;
1752  if (SrcReg2 != 0)
1753  // MI is not a candidate for CMPrr.
1754  MI = nullptr;
1755  // FIXME: Conservatively refuse to convert an instruction which isn't in the
1756  // same BB as the comparison. This is to allow the check below to avoid calls
1757  // (and other explicit clobbers); instead we should really check for these
1758  // more explicitly (in at least a few predecessors).
1759  else if (MI->getParent() != CmpInstr.getParent())
1760  return false;
1761  else if (Value != 0) {
1762  // The record-form instructions set CR bit based on signed comparison
1763  // against 0. We try to convert a compare against 1 or -1 into a compare
1764  // against 0 to exploit record-form instructions. For example, we change
1765  // the condition "greater than -1" into "greater than or equal to 0"
1766  // and "less than 1" into "less than or equal to 0".
1767 
1768  // Since we optimize comparison based on a specific branch condition,
1769  // we don't optimize if condition code is used by more than once.
1770  if (equalityOnly || !MRI->hasOneUse(CRReg))
1771  return false;
1772 
1773  MachineInstr *UseMI = &*MRI->use_instr_begin(CRReg);
1774  if (UseMI->getOpcode() != PPC::BCC)
1775  return false;
1776 
1777  PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
1778  unsigned PredCond = PPC::getPredicateCondition(Pred);
1779  unsigned PredHint = PPC::getPredicateHint(Pred);
1780  int16_t Immed = (int16_t)Value;
1781 
1782  // When modifying the condition in the predicate, we propagate hint bits
1783  // from the original predicate to the new one.
1784  if (Immed == -1 && PredCond == PPC::PRED_GT)
1785  // We convert "greater than -1" into "greater than or equal to 0",
1786  // since we are assuming signed comparison by !equalityOnly
1787  Pred = PPC::getPredicate(PPC::PRED_GE, PredHint);
1788  else if (Immed == -1 && PredCond == PPC::PRED_LE)
1789  // We convert "less than or equal to -1" into "less than 0".
1790  Pred = PPC::getPredicate(PPC::PRED_LT, PredHint);
1791  else if (Immed == 1 && PredCond == PPC::PRED_LT)
1792  // We convert "less than 1" into "less than or equal to 0".
1793  Pred = PPC::getPredicate(PPC::PRED_LE, PredHint);
1794  else if (Immed == 1 && PredCond == PPC::PRED_GE)
1795  // We convert "greater than or equal to 1" into "greater than 0".
1796  Pred = PPC::getPredicate(PPC::PRED_GT, PredHint);
1797  else
1798  return false;
1799 
1800  PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)), Pred));
1801  }
1802 
1803  // Search for Sub.
1804  --I;
1805 
1806  // Get ready to iterate backward from CmpInstr.
1807  MachineBasicBlock::iterator E = MI, B = CmpInstr.getParent()->begin();
1808 
1809  for (; I != E && !noSub; --I) {
1810  const MachineInstr &Instr = *I;
1811  unsigned IOpC = Instr.getOpcode();
1812 
1813  if (&*I != &CmpInstr && (Instr.modifiesRegister(PPC::CR0, TRI) ||
1814  Instr.readsRegister(PPC::CR0, TRI)))
1815  // This instruction modifies or uses the record condition register after
1816  // the one we want to change. While we could do this transformation, it
1817  // would likely not be profitable. This transformation removes one
1818  // instruction, and so even forcing RA to generate one move probably
1819  // makes it unprofitable.
1820  return false;
1821 
1822  // Check whether CmpInstr can be made redundant by the current instruction.
1823  if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
1824  OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
1825  (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
1826  ((Instr.getOperand(1).getReg() == SrcReg &&
1827  Instr.getOperand(2).getReg() == SrcReg2) ||
1828  (Instr.getOperand(1).getReg() == SrcReg2 &&
1829  Instr.getOperand(2).getReg() == SrcReg))) {
1830  Sub = &*I;
1831  break;
1832  }
1833 
1834  if (I == B)
1835  // The 'and' is below the comparison instruction.
1836  return false;
1837  }
1838 
1839  // Return false if no candidates exist.
1840  if (!MI && !Sub)
1841  return false;
1842 
1843  // The single candidate is called MI.
1844  if (!MI) MI = Sub;
1845 
1846  int NewOpC = -1;
1847  int MIOpC = MI->getOpcode();
1848  if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8 ||
1849  MIOpC == PPC::ANDISo || MIOpC == PPC::ANDISo8)
1850  NewOpC = MIOpC;
1851  else {
1852  NewOpC = PPC::getRecordFormOpcode(MIOpC);
1853  if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
1854  NewOpC = MIOpC;
1855  }
1856 
1857  // FIXME: On the non-embedded POWER architectures, only some of the record
1858  // forms are fast, and we should use only the fast ones.
1859 
1860  // The defining instruction has a record form (or is already a record
1861  // form). It is possible, however, that we'll need to reverse the condition
1862  // code of the users.
1863  if (NewOpC == -1)
1864  return false;
1865 
1866  // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
1867  // needs to be updated to be based on SUB. Push the condition code
1868  // operands to OperandsToUpdate. If it is safe to remove CmpInstr, the
1869  // condition code of these operands will be modified.
1870  // Here, Value == 0 means we haven't converted comparison against 1 or -1 to
1871  // comparison against 0, which may modify predicate.
1872  bool ShouldSwap = false;
1873  if (Sub && Value == 0) {
1874  ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1875  Sub->getOperand(2).getReg() == SrcReg;
1876 
1877  // The operands to subf are the opposite of sub, so only in the fixed-point
1878  // case, invert the order.
1879  ShouldSwap = !ShouldSwap;
1880  }
1881 
1882  if (ShouldSwap)
1884  I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1885  I != IE; ++I) {
1886  MachineInstr *UseMI = &*I;
1887  if (UseMI->getOpcode() == PPC::BCC) {
1888  PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
1889  unsigned PredCond = PPC::getPredicateCondition(Pred);
1890  assert((!equalityOnly ||
1891  PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE) &&
1892  "Invalid predicate for equality-only optimization");
1893  (void)PredCond; // To suppress warning in release build.
1894  PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1895  PPC::getSwappedPredicate(Pred)));
1896  } else if (UseMI->getOpcode() == PPC::ISEL ||
1897  UseMI->getOpcode() == PPC::ISEL8) {
1898  unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
1899  assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
1900  "Invalid CR bit for equality-only optimization");
1901 
1902  if (NewSubReg == PPC::sub_lt)
1903  NewSubReg = PPC::sub_gt;
1904  else if (NewSubReg == PPC::sub_gt)
1905  NewSubReg = PPC::sub_lt;
1906 
1907  SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)),
1908  NewSubReg));
1909  } else // We need to abort on a user we don't understand.
1910  return false;
1911  }
1912  assert(!(Value != 0 && ShouldSwap) &&
1913  "Non-zero immediate support and ShouldSwap"
1914  "may conflict in updating predicate");
1915 
1916  // Create a new virtual register to hold the value of the CR set by the
1917  // record-form instruction. If the instruction was not previously in
1918  // record form, then set the kill flag on the CR.
1919  CmpInstr.eraseFromParent();
1920 
1922  BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
1923  get(TargetOpcode::COPY), CRReg)
1924  .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
1925 
1926  // Even if CR0 register were dead before, it is alive now since the
1927  // instruction we just built uses it.
1928  MI->clearRegisterDeads(PPC::CR0);
1929 
1930  if (MIOpC != NewOpC) {
1931  // We need to be careful here: we're replacing one instruction with
1932  // another, and we need to make sure that we get all of the right
1933  // implicit uses and defs. On the other hand, the caller may be holding
1934  // an iterator to this instruction, and so we can't delete it (this is
1935  // specifically the case if this is the instruction directly after the
1936  // compare).
1937 
1938  // Rotates are expensive instructions. If we're emitting a record-form
1939  // rotate that can just be an andi/andis, we should just emit that.
1940  if (MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINM8) {
1941  Register GPRRes = MI->getOperand(0).getReg();
1942  int64_t SH = MI->getOperand(2).getImm();
1943  int64_t MB = MI->getOperand(3).getImm();
1944  int64_t ME = MI->getOperand(4).getImm();
1945  // We can only do this if both the start and end of the mask are in the
1946  // same halfword.
1947  bool MBInLoHWord = MB >= 16;
1948  bool MEInLoHWord = ME >= 16;
1949  uint64_t Mask = ~0LLU;
1950 
1951  if (MB <= ME && MBInLoHWord == MEInLoHWord && SH == 0) {
1952  Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
1953  // The mask value needs to shift right 16 if we're emitting andis.
1954  Mask >>= MBInLoHWord ? 0 : 16;
1955  NewOpC = MIOpC == PPC::RLWINM ?
1956  (MBInLoHWord ? PPC::ANDIo : PPC::ANDISo) :
1957  (MBInLoHWord ? PPC::ANDIo8 :PPC::ANDISo8);
1958  } else if (MRI->use_empty(GPRRes) && (ME == 31) &&
1959  (ME - MB + 1 == SH) && (MB >= 16)) {
1960  // If we are rotating by the exact number of bits as are in the mask
1961  // and the mask is in the least significant bits of the register,
1962  // that's just an andis. (as long as the GPR result has no uses).
1963  Mask = ((1LLU << 32) - 1) & ~((1LLU << (32 - SH)) - 1);
1964  Mask >>= 16;
1965  NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDISo :PPC::ANDISo8;
1966  }
1967  // If we've set the mask, we can transform.
1968  if (Mask != ~0LLU) {
1969  MI->RemoveOperand(4);
1970  MI->RemoveOperand(3);
1971  MI->getOperand(2).setImm(Mask);
1972  NumRcRotatesConvertedToRcAnd++;
1973  }
1974  } else if (MIOpC == PPC::RLDICL && MI->getOperand(2).getImm() == 0) {
1975  int64_t MB = MI->getOperand(3).getImm();
1976  if (MB >= 48) {
1977  uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
1978  NewOpC = PPC::ANDIo8;
1979  MI->RemoveOperand(3);
1980  MI->getOperand(2).setImm(Mask);
1981  NumRcRotatesConvertedToRcAnd++;
1982  }
1983  }
1984 
1985  const MCInstrDesc &NewDesc = get(NewOpC);
1986  MI->setDesc(NewDesc);
1987 
1988  if (NewDesc.ImplicitDefs)
1989  for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs();
1990  *ImpDefs; ++ImpDefs)
1991  if (!MI->definesRegister(*ImpDefs))
1992  MI->addOperand(*MI->getParent()->getParent(),
1993  MachineOperand::CreateReg(*ImpDefs, true, true));
1994  if (NewDesc.ImplicitUses)
1995  for (const MCPhysReg *ImpUses = NewDesc.getImplicitUses();
1996  *ImpUses; ++ImpUses)
1997  if (!MI->readsRegister(*ImpUses))
1998  MI->addOperand(*MI->getParent()->getParent(),
1999  MachineOperand::CreateReg(*ImpUses, false, true));
2000  }
2001  assert(MI->definesRegister(PPC::CR0) &&
2002  "Record-form instruction does not define cr0?");
2003 
2004  // Modify the condition code of operands in OperandsToUpdate.
2005  // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
2006  // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
2007  for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
2008  PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
2009 
2010  for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
2011  SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
2012 
2013  return true;
2014 }
2015 
2016 /// GetInstSize - Return the number of bytes of code the specified
2017 /// instruction may be. This returns the maximum number of bytes.
2018 ///
2020  unsigned Opcode = MI.getOpcode();
2021 
2022  if (Opcode == PPC::INLINEASM || Opcode == PPC::INLINEASM_BR) {
2023  const MachineFunction *MF = MI.getParent()->getParent();
2024  const char *AsmStr = MI.getOperand(0).getSymbolName();
2025  return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
2026  } else if (Opcode == TargetOpcode::STACKMAP) {
2027  StackMapOpers Opers(&MI);
2028  return Opers.getNumPatchBytes();
2029  } else if (Opcode == TargetOpcode::PATCHPOINT) {
2030  PatchPointOpers Opers(&MI);
2031  return Opers.getNumPatchBytes();
2032  } else {
2033  return get(Opcode).getSize();
2034  }
2035 }
2036 
2037 std::pair<unsigned, unsigned>
2039  const unsigned Mask = PPCII::MO_ACCESS_MASK;
2040  return std::make_pair(TF & Mask, TF & ~Mask);
2041 }
2042 
2045  using namespace PPCII;
2046  static const std::pair<unsigned, const char *> TargetFlags[] = {
2047  {MO_LO, "ppc-lo"},
2048  {MO_HA, "ppc-ha"},
2049  {MO_TPREL_LO, "ppc-tprel-lo"},
2050  {MO_TPREL_HA, "ppc-tprel-ha"},
2051  {MO_DTPREL_LO, "ppc-dtprel-lo"},
2052  {MO_TLSLD_LO, "ppc-tlsld-lo"},
2053  {MO_TOC_LO, "ppc-toc-lo"},
2054  {MO_TLS, "ppc-tls"}};
2055  return makeArrayRef(TargetFlags);
2056 }
2057 
2060  using namespace PPCII;
2061  static const std::pair<unsigned, const char *> TargetFlags[] = {
2062  {MO_PLT, "ppc-plt"},
2063  {MO_PIC_FLAG, "ppc-pic"},
2064  {MO_NLP_FLAG, "ppc-nlp"},
2065  {MO_NLP_HIDDEN_FLAG, "ppc-nlp-hidden"}};
2066  return makeArrayRef(TargetFlags);
2067 }
2068 
2069 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
2070 // The VSX versions have the advantage of a full 64-register target whereas
2071 // the FP ones have the advantage of lower latency and higher throughput. So
2072 // what we are after is using the faster instructions in low register pressure
2073 // situations and using the larger register file in high register pressure
2074 // situations.
2076  unsigned UpperOpcode, LowerOpcode;
2077  switch (MI.getOpcode()) {
2078  case PPC::DFLOADf32:
2079  UpperOpcode = PPC::LXSSP;
2080  LowerOpcode = PPC::LFS;
2081  break;
2082  case PPC::DFLOADf64:
2083  UpperOpcode = PPC::LXSD;
2084  LowerOpcode = PPC::LFD;
2085  break;
2086  case PPC::DFSTOREf32:
2087  UpperOpcode = PPC::STXSSP;
2088  LowerOpcode = PPC::STFS;
2089  break;
2090  case PPC::DFSTOREf64:
2091  UpperOpcode = PPC::STXSD;
2092  LowerOpcode = PPC::STFD;
2093  break;
2094  case PPC::XFLOADf32:
2095  UpperOpcode = PPC::LXSSPX;
2096  LowerOpcode = PPC::LFSX;
2097  break;
2098  case PPC::XFLOADf64:
2099  UpperOpcode = PPC::LXSDX;
2100  LowerOpcode = PPC::LFDX;
2101  break;
2102  case PPC::XFSTOREf32:
2103  UpperOpcode = PPC::STXSSPX;
2104  LowerOpcode = PPC::STFSX;
2105  break;
2106  case PPC::XFSTOREf64:
2107  UpperOpcode = PPC::STXSDX;
2108  LowerOpcode = PPC::STFDX;
2109  break;
2110  case PPC::LIWAX:
2111  UpperOpcode = PPC::LXSIWAX;
2112  LowerOpcode = PPC::LFIWAX;
2113  break;
2114  case PPC::LIWZX:
2115  UpperOpcode = PPC::LXSIWZX;
2116  LowerOpcode = PPC::LFIWZX;
2117  break;
2118  case PPC::STIWX:
2119  UpperOpcode = PPC::STXSIWX;
2120  LowerOpcode = PPC::STFIWX;
2121  break;
2122  default:
2123  llvm_unreachable("Unknown Operation!");
2124  }
2125 
2126  Register TargetReg = MI.getOperand(0).getReg();
2127  unsigned Opcode;
2128  if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) ||
2129  (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31))
2130  Opcode = LowerOpcode;
2131  else
2132  Opcode = UpperOpcode;
2133  MI.setDesc(get(Opcode));
2134  return true;
2135 }
2136 
2137 static bool isAnImmediateOperand(const MachineOperand &MO) {
2138  return MO.isCPI() || MO.isGlobal() || MO.isImm();
2139 }
2140 
2142  auto &MBB = *MI.getParent();
2143  auto DL = MI.getDebugLoc();
2144 
2145  switch (MI.getOpcode()) {
2146  case TargetOpcode::LOAD_STACK_GUARD: {
2147  assert(Subtarget.isTargetLinux() &&
2148  "Only Linux target is expected to contain LOAD_STACK_GUARD");
2149  const int64_t Offset = Subtarget.isPPC64() ? -0x7010 : -0x7008;
2150  const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2;
2151  MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ));
2153  .addImm(Offset)
2154  .addReg(Reg);
2155  return true;
2156  }
2157  case PPC::DFLOADf32:
2158  case PPC::DFLOADf64:
2159  case PPC::DFSTOREf32:
2160  case PPC::DFSTOREf64: {
2161  assert(Subtarget.hasP9Vector() &&
2162  "Invalid D-Form Pseudo-ops on Pre-P9 target.");
2163  assert(MI.getOperand(2).isReg() &&
2165  "D-form op must have register and immediate operands");
2166  return expandVSXMemPseudo(MI);
2167  }
2168  case PPC::XFLOADf32:
2169  case PPC::XFSTOREf32:
2170  case PPC::LIWAX:
2171  case PPC::LIWZX:
2172  case PPC::STIWX: {
2173  assert(Subtarget.hasP8Vector() &&
2174  "Invalid X-Form Pseudo-ops on Pre-P8 target.");
2175  assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
2176  "X-form op must have register and register operands");
2177  return expandVSXMemPseudo(MI);
2178  }
2179  case PPC::XFLOADf64:
2180  case PPC::XFSTOREf64: {
2181  assert(Subtarget.hasVSX() &&
2182  "Invalid X-Form Pseudo-ops on target that has no VSX.");
2183  assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
2184  "X-form op must have register and register operands");
2185  return expandVSXMemPseudo(MI);
2186  }
2187  case PPC::SPILLTOVSR_LD: {
2188  Register TargetReg = MI.getOperand(0).getReg();
2189  if (PPC::VSFRCRegClass.contains(TargetReg)) {
2190  MI.setDesc(get(PPC::DFLOADf64));
2191  return expandPostRAPseudo(MI);
2192  }
2193  else
2194  MI.setDesc(get(PPC::LD));
2195  return true;
2196  }
2197  case PPC::SPILLTOVSR_ST: {
2198  Register SrcReg = MI.getOperand(0).getReg();
2199  if (PPC::VSFRCRegClass.contains(SrcReg)) {
2200  NumStoreSPILLVSRRCAsVec++;
2201  MI.setDesc(get(PPC::DFSTOREf64));
2202  return expandPostRAPseudo(MI);
2203  } else {
2204  NumStoreSPILLVSRRCAsGpr++;
2205  MI.setDesc(get(PPC::STD));
2206  }
2207  return true;
2208  }
2209  case PPC::SPILLTOVSR_LDX: {
2210  Register TargetReg = MI.getOperand(0).getReg();
2211  if (PPC::VSFRCRegClass.contains(TargetReg))
2212  MI.setDesc(get(PPC::LXSDX));
2213  else
2214  MI.setDesc(get(PPC::LDX));
2215  return true;
2216  }
2217  case PPC::SPILLTOVSR_STX: {
2218  Register SrcReg = MI.getOperand(0).getReg();
2219  if (PPC::VSFRCRegClass.contains(SrcReg)) {
2220  NumStoreSPILLVSRRCAsVec++;
2221  MI.setDesc(get(PPC::STXSDX));
2222  } else {
2223  NumStoreSPILLVSRRCAsGpr++;
2224  MI.setDesc(get(PPC::STDX));
2225  }
2226  return true;
2227  }
2228 
2229  case PPC::CFENCE8: {
2230  auto Val = MI.getOperand(0).getReg();
2231  BuildMI(MBB, MI, DL, get(PPC::CMPD), PPC::CR7).addReg(Val).addReg(Val);
2232  BuildMI(MBB, MI, DL, get(PPC::CTRL_DEP))
2234  .addReg(PPC::CR7)
2235  .addImm(1);
2236  MI.setDesc(get(PPC::ISYNC));
2237  MI.RemoveOperand(0);
2238  return true;
2239  }
2240  }
2241  return false;
2242 }
2243 
2244 // Essentially a compile-time implementation of a compare->isel sequence.
2245 // It takes two constants to compare, along with the true/false registers
2246 // and the comparison type (as a subreg to a CR field) and returns one
2247 // of the true/false registers, depending on the comparison results.
2248 static unsigned selectReg(int64_t Imm1, int64_t Imm2, unsigned CompareOpc,
2249  unsigned TrueReg, unsigned FalseReg,
2250  unsigned CRSubReg) {
2251  // Signed comparisons. The immediates are assumed to be sign-extended.
2252  if (CompareOpc == PPC::CMPWI || CompareOpc == PPC::CMPDI) {
2253  switch (CRSubReg) {
2254  default: llvm_unreachable("Unknown integer comparison type.");
2255  case PPC::sub_lt:
2256  return Imm1 < Imm2 ? TrueReg : FalseReg;
2257  case PPC::sub_gt:
2258  return Imm1 > Imm2 ? TrueReg : FalseReg;
2259  case PPC::sub_eq:
2260  return Imm1 == Imm2 ? TrueReg : FalseReg;
2261  }
2262  }
2263  // Unsigned comparisons.
2264  else if (CompareOpc == PPC::CMPLWI || CompareOpc == PPC::CMPLDI) {
2265  switch (CRSubReg) {
2266  default: llvm_unreachable("Unknown integer comparison type.");
2267  case PPC::sub_lt:
2268  return (uint64_t)Imm1 < (uint64_t)Imm2 ? TrueReg : FalseReg;
2269  case PPC::sub_gt:
2270  return (uint64_t)Imm1 > (uint64_t)Imm2 ? TrueReg : FalseReg;
2271  case PPC::sub_eq:
2272  return Imm1 == Imm2 ? TrueReg : FalseReg;
2273  }
2274  }
2275  return PPC::NoRegister;
2276 }
2277 
2279  unsigned OpNo,
2280  int64_t Imm) const {
2281  assert(MI.getOperand(OpNo).isReg() && "Operand must be a REG");
2282  // Replace the REG with the Immediate.
2283  Register InUseReg = MI.getOperand(OpNo).getReg();
2284  MI.getOperand(OpNo).ChangeToImmediate(Imm);
2285 
2286  if (empty(MI.implicit_operands()))
2287  return;
2288 
2289  // We need to make sure that the MI didn't have any implicit use
2290  // of this REG any more.
2292  int UseOpIdx = MI.findRegisterUseOperandIdx(InUseReg, false, TRI);
2293  if (UseOpIdx >= 0) {
2294  MachineOperand &MO = MI.getOperand(UseOpIdx);
2295  if (MO.isImplicit())
2296  // The operands must always be in the following order:
2297  // - explicit reg defs,
2298  // - other explicit operands (reg uses, immediates, etc.),
2299  // - implicit reg defs
2300  // - implicit reg uses
2301  // Therefore, removing the implicit operand won't change the explicit
2302  // operands layout.
2303  MI.RemoveOperand(UseOpIdx);
2304  }
2305 }
2306 
2307 // Replace an instruction with one that materializes a constant (and sets
2308 // CR0 if the original instruction was a record-form instruction).
2310  const LoadImmediateInfo &LII) const {
2311  // Remove existing operands.
2312  int OperandToKeep = LII.SetCR ? 1 : 0;
2313  for (int i = MI.getNumOperands() - 1; i > OperandToKeep; i--)
2314  MI.RemoveOperand(i);
2315 
2316  // Replace the instruction.
2317  if (LII.SetCR) {
2318  MI.setDesc(get(LII.Is64Bit ? PPC::ANDIo8 : PPC::ANDIo));
2319  // Set the immediate.
2321  .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine);
2322  return;
2323  }
2324  else
2325  MI.setDesc(get(LII.Is64Bit ? PPC::LI8 : PPC::LI));
2326 
2327  // Set the immediate.
2329  .addImm(LII.Imm);
2330 }
2331 
2333  bool &SeenIntermediateUse) const {
2334  assert(!MI.getParent()->getParent()->getRegInfo().isSSA() &&
2335  "Should be called after register allocation.");
2338  It++;
2339  SeenIntermediateUse = false;
2340  for (; It != E; ++It) {
2341  if (It->modifiesRegister(Reg, TRI))
2342  return &*It;
2343  if (It->readsRegister(Reg, TRI))
2344  SeenIntermediateUse = true;
2345  }
2346  return nullptr;
2347 }
2348 
2349 MachineInstr *PPCInstrInfo::getForwardingDefMI(
2350  MachineInstr &MI,
2351  unsigned &OpNoForForwarding,
2352  bool &SeenIntermediateUse) const {
2353  OpNoForForwarding = ~0U;
2354  MachineInstr *DefMI = nullptr;
2357  // If we're in SSA, get the defs through the MRI. Otherwise, only look
2358  // within the basic block to see if the register is defined using an LI/LI8.
2359  if (MRI->isSSA()) {
2360  for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
2361  if (!MI.getOperand(i).isReg())
2362  continue;
2363  Register Reg = MI.getOperand(i).getReg();
2364  if (!Register::isVirtualRegister(Reg))
2365  continue;
2366  unsigned TrueReg = TRI->lookThruCopyLike(Reg, MRI);
2367  if (Register::isVirtualRegister(TrueReg)) {
2368  DefMI = MRI->getVRegDef(TrueReg);
2369  if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8) {
2370  OpNoForForwarding = i;
2371  break;
2372  }
2373  }
2374  }
2375  } else {
2376  // Looking back through the definition for each operand could be expensive,
2377  // so exit early if this isn't an instruction that either has an immediate
2378  // form or is already an immediate form that we can handle.
2379  ImmInstrInfo III;
2380  unsigned Opc = MI.getOpcode();
2381  bool ConvertibleImmForm =
2382  Opc == PPC::CMPWI || Opc == PPC::CMPLWI ||
2383  Opc == PPC::CMPDI || Opc == PPC::CMPLDI ||
2384  Opc == PPC::ADDI || Opc == PPC::ADDI8 ||
2385  Opc == PPC::ORI || Opc == PPC::ORI8 ||
2386  Opc == PPC::XORI || Opc == PPC::XORI8 ||
2387  Opc == PPC::RLDICL || Opc == PPC::RLDICLo ||
2388  Opc == PPC::RLDICL_32 || Opc == PPC::RLDICL_32_64 ||
2389  Opc == PPC::RLWINM || Opc == PPC::RLWINMo ||
2390  Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
2391  bool IsVFReg = (MI.getNumOperands() && MI.getOperand(0).isReg())
2392  ? isVFRegister(MI.getOperand(0).getReg())
2393  : false;
2394  if (!ConvertibleImmForm && !instrHasImmForm(Opc, IsVFReg, III, true))
2395  return nullptr;
2396 
2397  // Don't convert or %X, %Y, %Y since that's just a register move.
2398  if ((Opc == PPC::OR || Opc == PPC::OR8) &&
2399  MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
2400  return nullptr;
2401  for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
2402  MachineOperand &MO = MI.getOperand(i);
2403  SeenIntermediateUse = false;
2404  if (MO.isReg() && MO.isUse() && !MO.isImplicit()) {
2405  Register Reg = MI.getOperand(i).getReg();
2406  // If we see another use of this reg between the def and the MI,
2407  // we want to flat it so the def isn't deleted.
2408  MachineInstr *DefMI = getDefMIPostRA(Reg, MI, SeenIntermediateUse);
2409  if (DefMI) {
2410  // Is this register defined by some form of add-immediate (including
2411  // load-immediate) within this basic block?
2412  switch (DefMI->getOpcode()) {
2413  default:
2414  break;
2415  case PPC::LI:
2416  case PPC::LI8:
2417  case PPC::ADDItocL:
2418  case PPC::ADDI:
2419  case PPC::ADDI8:
2420  OpNoForForwarding = i;
2421  return DefMI;
2422  }
2423  }
2424  }
2425  }
2426  }
2427  return OpNoForForwarding == ~0U ? nullptr : DefMI;
2428 }
2429 
2430 const unsigned *PPCInstrInfo::getStoreOpcodesForSpillArray() const {
2431  static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = {
2432  // Power 8
2433  {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
2434  PPC::SPILL_CRBIT, PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX,
2435  PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb,
2436  PPC::SPILLTOVSR_ST, PPC::EVSTDD, PPC::SPESTW},
2437  // Power 9
2438  {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
2439  PPC::SPILL_CRBIT, PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32,
2440  PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb,
2441  PPC::SPILLTOVSR_ST}};
2442 
2443  return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0];
2444 }
2445 
2446 const unsigned *PPCInstrInfo::getLoadOpcodesForSpillArray() const {
2447  static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = {
2448  // Power 8
2449  {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
2450  PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX,
2451  PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
2452  PPC::SPILLTOVSR_LD, PPC::EVLDD, PPC::SPELWZ},
2453  // Power 9
2454  {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
2455  PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, PPC::DFLOADf32,
2456  PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
2457  PPC::SPILLTOVSR_LD}};
2458 
2459  return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0];
2460 }
2461 
2463  unsigned RegNo) const {
2464  const MachineRegisterInfo &MRI =
2465  StartMI.getParent()->getParent()->getRegInfo();
2466  if (MRI.isSSA())
2467  return;
2468 
2469  // Instructions between [StartMI, EndMI] should be in same basic block.
2470  assert((StartMI.getParent() == EndMI.getParent()) &&
2471  "Instructions are not in same basic block");
2472 
2473  bool IsKillSet = false;
2474 
2475  auto clearOperandKillInfo = [=] (MachineInstr &MI, unsigned Index) {
2476  MachineOperand &MO = MI.getOperand(Index);
2477  if (MO.isReg() && MO.isUse() && MO.isKill() &&
2478  getRegisterInfo().regsOverlap(MO.getReg(), RegNo))
2479  MO.setIsKill(false);
2480  };
2481 
2482  // Set killed flag for EndMI.
2483  // No need to do anything if EndMI defines RegNo.
2484  int UseIndex =
2485  EndMI.findRegisterUseOperandIdx(RegNo, false, &getRegisterInfo());
2486  if (UseIndex != -1) {
2487  EndMI.getOperand(UseIndex).setIsKill(true);
2488  IsKillSet = true;
2489  // Clear killed flag for other EndMI operands related to RegNo. In some
2490  // upexpected cases, killed may be set multiple times for same register
2491  // operand in same MI.
2492  for (int i = 0, e = EndMI.getNumOperands(); i != e; ++i)
2493  if (i != UseIndex)
2494  clearOperandKillInfo(EndMI, i);
2495  }
2496 
2497  // Walking the inst in reverse order (EndMI -> StartMI].
2500  // EndMI has been handled above, skip it here.
2501  It++;
2502  MachineOperand *MO = nullptr;
2503  for (; It != E; ++It) {
2504  // Skip insturctions which could not be a def/use of RegNo.
2505  if (It->isDebugInstr() || It->isPosition())
2506  continue;
2507 
2508  // Clear killed flag for all It operands related to RegNo. In some
2509  // upexpected cases, killed may be set multiple times for same register
2510  // operand in same MI.
2511  for (int i = 0, e = It->getNumOperands(); i != e; ++i)
2512  clearOperandKillInfo(*It, i);
2513 
2514  // If killed is not set, set killed for its last use or set dead for its def
2515  // if no use found.
2516  if (!IsKillSet) {
2517  if ((MO = It->findRegisterUseOperand(RegNo, false, &getRegisterInfo()))) {
2518  // Use found, set it killed.
2519  IsKillSet = true;
2520  MO->setIsKill(true);
2521  continue;
2522  } else if ((MO = It->findRegisterDefOperand(RegNo, false, true,
2523  &getRegisterInfo()))) {
2524  // No use found, set dead for its def.
2525  assert(&*It == &StartMI && "No new def between StartMI and EndMI.");
2526  MO->setIsDead(true);
2527  break;
2528  }
2529  }
2530 
2531  if ((&*It) == &StartMI)
2532  break;
2533  }
2534  // Ensure RegMo liveness is killed after EndMI.
2535  assert((IsKillSet || (MO && MO->isDead())) &&
2536  "RegNo should be killed or dead");
2537 }
2538 
2539 // If this instruction has an immediate form and one of its operands is a
2540 // result of a load-immediate or an add-immediate, convert it to
2541 // the immediate form if the constant is in range.
2543  MachineInstr **KilledDef) const {
2544  MachineFunction *MF = MI.getParent()->getParent();
2546  bool PostRA = !MRI->isSSA();
2547  bool SeenIntermediateUse = true;
2548  unsigned ForwardingOperand = ~0U;
2549  MachineInstr *DefMI = getForwardingDefMI(MI, ForwardingOperand,
2550  SeenIntermediateUse);
2551  if (!DefMI)
2552  return false;
2553  assert(ForwardingOperand < MI.getNumOperands() &&
2554  "The forwarding operand needs to be valid at this point");
2555  bool IsForwardingOperandKilled = MI.getOperand(ForwardingOperand).isKill();
2556  bool KillFwdDefMI = !SeenIntermediateUse && IsForwardingOperandKilled;
2557  Register ForwardingOperandReg = MI.getOperand(ForwardingOperand).getReg();
2558  if (KilledDef && KillFwdDefMI)
2559  *KilledDef = DefMI;
2560 
2561  ImmInstrInfo III;
2562  bool IsVFReg = MI.getOperand(0).isReg()
2563  ? isVFRegister(MI.getOperand(0).getReg())
2564  : false;
2565  bool HasImmForm = instrHasImmForm(MI.getOpcode(), IsVFReg, III, PostRA);
2566  // If this is a reg+reg instruction that has a reg+imm form,
2567  // and one of the operands is produced by an add-immediate,
2568  // try to convert it.
2569  if (HasImmForm &&
2570  transformToImmFormFedByAdd(MI, III, ForwardingOperand, *DefMI,
2571  KillFwdDefMI))
2572  return true;
2573 
2574  if ((DefMI->getOpcode() != PPC::LI && DefMI->getOpcode() != PPC::LI8) ||
2575  !DefMI->getOperand(1).isImm())
2576  return false;
2577 
2578  int64_t Immediate = DefMI->getOperand(1).getImm();
2579  // Sign-extend to 64-bits.
2580  int64_t SExtImm = ((uint64_t)Immediate & ~0x7FFFuLL) != 0 ?
2581  (Immediate | 0xFFFFFFFFFFFF0000) : Immediate;
2582 
2583  // If this is a reg+reg instruction that has a reg+imm form,
2584  // and one of the operands is produced by LI, convert it now.
2585  if (HasImmForm)
2586  return transformToImmFormFedByLI(MI, III, ForwardingOperand, *DefMI, SExtImm);
2587 
2588  bool ReplaceWithLI = false;
2589  bool Is64BitLI = false;
2590  int64_t NewImm = 0;
2591  bool SetCR = false;
2592  unsigned Opc = MI.getOpcode();
2593  switch (Opc) {
2594  default: return false;
2595 
2596  // FIXME: Any branches conditional on such a comparison can be made
2597  // unconditional. At this time, this happens too infrequently to be worth
2598  // the implementation effort, but if that ever changes, we could convert
2599  // such a pattern here.
2600  case PPC::CMPWI:
2601  case PPC::CMPLWI:
2602  case PPC::CMPDI:
2603  case PPC::CMPLDI: {
2604  // Doing this post-RA would require dataflow analysis to reliably find uses
2605  // of the CR register set by the compare.
2606  // No need to fixup killed/dead flag since this transformation is only valid
2607  // before RA.
2608  if (PostRA)
2609  return false;
2610  // If a compare-immediate is fed by an immediate and is itself an input of
2611  // an ISEL (the most common case) into a COPY of the correct register.
2612  bool Changed = false;
2613  Register DefReg = MI.getOperand(0).getReg();
2614  int64_t Comparand = MI.getOperand(2).getImm();
2615  int64_t SExtComparand = ((uint64_t)Comparand & ~0x7FFFuLL) != 0 ?
2616  (Comparand | 0xFFFFFFFFFFFF0000) : Comparand;
2617 
2618  for (auto &CompareUseMI : MRI->use_instructions(DefReg)) {
2619  unsigned UseOpc = CompareUseMI.getOpcode();
2620  if (UseOpc != PPC::ISEL && UseOpc != PPC::ISEL8)
2621  continue;
2622  unsigned CRSubReg = CompareUseMI.getOperand(3).getSubReg();
2623  Register TrueReg = CompareUseMI.getOperand(1).getReg();
2624  Register FalseReg = CompareUseMI.getOperand(2).getReg();
2625  unsigned RegToCopy = selectReg(SExtImm, SExtComparand, Opc, TrueReg,
2626  FalseReg, CRSubReg);
2627  if (RegToCopy == PPC::NoRegister)
2628  continue;
2629  // Can't use PPC::COPY to copy PPC::ZERO[8]. Convert it to LI[8] 0.
2630  if (RegToCopy == PPC::ZERO || RegToCopy == PPC::ZERO8) {
2631  CompareUseMI.setDesc(get(UseOpc == PPC::ISEL8 ? PPC::LI8 : PPC::LI));
2632  replaceInstrOperandWithImm(CompareUseMI, 1, 0);
2633  CompareUseMI.RemoveOperand(3);
2634  CompareUseMI.RemoveOperand(2);
2635  continue;
2636  }
2637  LLVM_DEBUG(
2638  dbgs() << "Found LI -> CMPI -> ISEL, replacing with a copy.\n");
2639  LLVM_DEBUG(DefMI->dump(); MI.dump(); CompareUseMI.dump());
2640  LLVM_DEBUG(dbgs() << "Is converted to:\n");
2641  // Convert to copy and remove unneeded operands.
2642  CompareUseMI.setDesc(get(PPC::COPY));
2643  CompareUseMI.RemoveOperand(3);
2644  CompareUseMI.RemoveOperand(RegToCopy == TrueReg ? 2 : 1);
2645  CmpIselsConverted++;
2646  Changed = true;
2647  LLVM_DEBUG(CompareUseMI.dump());
2648  }
2649  if (Changed)
2650  return true;
2651  // This may end up incremented multiple times since this function is called
2652  // during a fixed-point transformation, but it is only meant to indicate the
2653  // presence of this opportunity.
2654  MissedConvertibleImmediateInstrs++;
2655  return false;
2656  }
2657 
2658  // Immediate forms - may simply be convertable to an LI.
2659  case PPC::ADDI:
2660  case PPC::ADDI8: {
2661  // Does the sum fit in a 16-bit signed field?
2662  int64_t Addend = MI.getOperand(2).getImm();
2663  if (isInt<16>(Addend + SExtImm)) {
2664  ReplaceWithLI = true;
2665  Is64BitLI = Opc == PPC::ADDI8;
2666  NewImm = Addend + SExtImm;
2667  break;
2668  }
2669  return false;
2670  }
2671  case PPC::RLDICL:
2672  case PPC::RLDICLo:
2673  case PPC::RLDICL_32:
2674  case PPC::RLDICL_32_64: {
2675  // Use APInt's rotate function.
2676  int64_t SH = MI.getOperand(2).getImm();
2677  int64_t MB = MI.getOperand(3).getImm();
2678  APInt InVal((Opc == PPC::RLDICL || Opc == PPC::RLDICLo) ?
2679  64 : 32, SExtImm, true);
2680  InVal = InVal.rotl(SH);
2681  uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
2682  InVal &= Mask;
2683  // Can't replace negative values with an LI as that will sign-extend
2684  // and not clear the left bits. If we're setting the CR bit, we will use
2685  // ANDIo which won't sign extend, so that's safe.
2686  if (isUInt<15>(InVal.getSExtValue()) ||
2687  (Opc == PPC::RLDICLo && isUInt<16>(InVal.getSExtValue()))) {
2688  ReplaceWithLI = true;
2689  Is64BitLI = Opc != PPC::RLDICL_32;
2690  NewImm = InVal.getSExtValue();
2691  SetCR = Opc == PPC::RLDICLo;
2692  break;
2693  }
2694  return false;
2695  }
2696  case PPC::RLWINM:
2697  case PPC::RLWINM8:
2698  case PPC::RLWINMo:
2699  case PPC::RLWINM8o: {
2700  int64_t SH = MI.getOperand(2).getImm();
2701  int64_t MB = MI.getOperand(3).getImm();
2702  int64_t ME = MI.getOperand(4).getImm();
2703  APInt InVal(32, SExtImm, true);
2704  InVal = InVal.rotl(SH);
2705  // Set the bits ( MB + 32 ) to ( ME + 32 ).
2706  uint64_t Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
2707  InVal &= Mask;
2708  // Can't replace negative values with an LI as that will sign-extend
2709  // and not clear the left bits. If we're setting the CR bit, we will use
2710  // ANDIo which won't sign extend, so that's safe.
2711  bool ValueFits = isUInt<15>(InVal.getSExtValue());
2712  ValueFits |= ((Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o) &&
2713  isUInt<16>(InVal.getSExtValue()));
2714  if (ValueFits) {
2715  ReplaceWithLI = true;
2716  Is64BitLI = Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
2717  NewImm = InVal.getSExtValue();
2718  SetCR = Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o;
2719  break;
2720  }
2721  return false;
2722  }
2723  case PPC::ORI:
2724  case PPC::ORI8:
2725  case PPC::XORI:
2726  case PPC::XORI8: {
2727  int64_t LogicalImm = MI.getOperand(2).getImm();
2728  int64_t Result = 0;
2729  if (Opc == PPC::ORI || Opc == PPC::ORI8)
2730  Result = LogicalImm | SExtImm;
2731  else
2732  Result = LogicalImm ^ SExtImm;
2733  if (isInt<16>(Result)) {
2734  ReplaceWithLI = true;
2735  Is64BitLI = Opc == PPC::ORI8 || Opc == PPC::XORI8;
2736  NewImm = Result;
2737  break;
2738  }
2739  return false;
2740  }
2741  }
2742 
2743  if (ReplaceWithLI) {
2744  // We need to be careful with CR-setting instructions we're replacing.
2745  if (SetCR) {
2746  // We don't know anything about uses when we're out of SSA, so only
2747  // replace if the new immediate will be reproduced.
2748  bool ImmChanged = (SExtImm & NewImm) != NewImm;
2749  if (PostRA && ImmChanged)
2750  return false;
2751 
2752  if (!PostRA) {
2753  // If the defining load-immediate has no other uses, we can just replace
2754  // the immediate with the new immediate.
2755  if (MRI->hasOneUse(DefMI->getOperand(0).getReg()))
2756  DefMI->getOperand(1).setImm(NewImm);
2757 
2758  // If we're not using the GPR result of the CR-setting instruction, we
2759  // just need to and with zero/non-zero depending on the new immediate.
2760  else if (MRI->use_empty(MI.getOperand(0).getReg())) {
2761  if (NewImm) {
2762  assert(Immediate && "Transformation converted zero to non-zero?");
2763  NewImm = Immediate;
2764  }
2765  }
2766  else if (ImmChanged)
2767  return false;
2768  }
2769  }
2770 
2771  LLVM_DEBUG(dbgs() << "Replacing instruction:\n");
2772  LLVM_DEBUG(MI.dump());
2773  LLVM_DEBUG(dbgs() << "Fed by:\n");
2774  LLVM_DEBUG(DefMI->dump());
2775  LoadImmediateInfo LII;
2776  LII.Imm = NewImm;
2777  LII.Is64Bit = Is64BitLI;
2778  LII.SetCR = SetCR;
2779  // If we're setting the CR, the original load-immediate must be kept (as an
2780  // operand to ANDIo/ANDI8o).
2781  if (KilledDef && SetCR)
2782  *KilledDef = nullptr;
2783  replaceInstrWithLI(MI, LII);
2784 
2785  // Fixup killed/dead flag after transformation.
2786  // Pattern:
2787  // ForwardingOperandReg = LI imm1
2788  // y = op2 imm2, ForwardingOperandReg(killed)
2789  if (IsForwardingOperandKilled)
2790  fixupIsDeadOrKill(*DefMI, MI, ForwardingOperandReg);
2791 
2792  LLVM_DEBUG(dbgs() << "With:\n");
2793  LLVM_DEBUG(MI.dump());
2794  return true;
2795  }
2796  return false;
2797 }
2798 
2799 bool PPCInstrInfo::instrHasImmForm(unsigned Opc, bool IsVFReg,
2800  ImmInstrInfo &III, bool PostRA) const {
2801  // The vast majority of the instructions would need their operand 2 replaced
2802  // with an immediate when switching to the reg+imm form. A marked exception
2803  // are the update form loads/stores for which a constant operand 2 would need
2804  // to turn into a displacement and move operand 1 to the operand 2 position.
2805  III.ImmOpNo = 2;
2806  III.OpNoForForwarding = 2;
2807  III.ImmWidth = 16;
2808  III.ImmMustBeMultipleOf = 1;
2809  III.TruncateImmTo = 0;
2810  III.IsSummingOperands = false;
2811  switch (Opc) {
2812  default: return false;
2813  case PPC::ADD4:
2814  case PPC::ADD8:
2815  III.SignedImm = true;
2816  III.ZeroIsSpecialOrig = 0;
2817  III.ZeroIsSpecialNew = 1;
2818  III.IsCommutative = true;
2819  III.IsSummingOperands = true;
2820  III.ImmOpcode = Opc == PPC::ADD4 ? PPC::ADDI : PPC::ADDI8;
2821  break;
2822  case PPC::ADDC:
2823  case PPC::ADDC8:
2824  III.SignedImm = true;
2825  III.ZeroIsSpecialOrig = 0;
2826  III.ZeroIsSpecialNew = 0;
2827  III.IsCommutative = true;
2828  III.IsSummingOperands = true;
2829  III.ImmOpcode = Opc == PPC::ADDC ? PPC::ADDIC : PPC::ADDIC8;
2830  break;
2831  case PPC::ADDCo:
2832  III.SignedImm = true;
2833  III.ZeroIsSpecialOrig = 0;
2834  III.ZeroIsSpecialNew = 0;
2835  III.IsCommutative = true;
2836  III.IsSummingOperands = true;
2837  III.ImmOpcode = PPC::ADDICo;
2838  break;
2839  case PPC::SUBFC:
2840  case PPC::SUBFC8:
2841  III.SignedImm = true;
2842  III.ZeroIsSpecialOrig = 0;
2843  III.ZeroIsSpecialNew = 0;
2844  III.IsCommutative = false;
2845  III.ImmOpcode = Opc == PPC::SUBFC ? PPC::SUBFIC : PPC::SUBFIC8;
2846  break;
2847  case PPC::CMPW:
2848  case PPC::CMPD:
2849  III.SignedImm = true;
2850  III.ZeroIsSpecialOrig = 0;
2851  III.ZeroIsSpecialNew = 0;
2852  III.IsCommutative = false;
2853  III.ImmOpcode = Opc == PPC::CMPW ? PPC::CMPWI : PPC::CMPDI;
2854  break;
2855  case PPC::CMPLW:
2856  case PPC::CMPLD:
2857  III.SignedImm = false;
2858  III.ZeroIsSpecialOrig = 0;
2859  III.ZeroIsSpecialNew = 0;
2860  III.IsCommutative = false;
2861  III.ImmOpcode = Opc == PPC::CMPLW ? PPC::CMPLWI : PPC::CMPLDI;
2862  break;
2863  case PPC::ANDo:
2864  case PPC::AND8o:
2865  case PPC::OR:
2866  case PPC::OR8:
2867  case PPC::XOR:
2868  case PPC::XOR8:
2869  III.SignedImm = false;
2870  III.ZeroIsSpecialOrig = 0;
2871  III.ZeroIsSpecialNew = 0;
2872  III.IsCommutative = true;
2873  switch(Opc) {
2874  default: llvm_unreachable("Unknown opcode");
2875  case PPC::ANDo: III.ImmOpcode = PPC::ANDIo; break;
2876  case PPC::AND8o: III.ImmOpcode = PPC::ANDIo8; break;
2877  case PPC::OR: III.ImmOpcode = PPC::ORI; break;
2878  case PPC::OR8: III.ImmOpcode = PPC::ORI8; break;
2879  case PPC::XOR: III.ImmOpcode = PPC::XORI; break;
2880  case PPC::XOR8: III.ImmOpcode = PPC::XORI8; break;
2881  }
2882  break;
2883  case PPC::RLWNM:
2884  case PPC::RLWNM8:
2885  case PPC::RLWNMo:
2886  case PPC::RLWNM8o:
2887  case PPC::SLW:
2888  case PPC::SLW8:
2889  case PPC::SLWo:
2890  case PPC::SLW8o:
2891  case PPC::SRW:
2892  case PPC::SRW8:
2893  case PPC::SRWo:
2894  case PPC::SRW8o:
2895  case PPC::SRAW:
2896  case PPC::SRAWo:
2897  III.SignedImm = false;
2898  III.ZeroIsSpecialOrig = 0;
2899  III.ZeroIsSpecialNew = 0;
2900  III.IsCommutative = false;
2901  // This isn't actually true, but the instructions ignore any of the
2902  // upper bits, so any immediate loaded with an LI is acceptable.
2903  // This does not apply to shift right algebraic because a value
2904  // out of range will produce a -1/0.
2905  III.ImmWidth = 16;
2906  if (Opc == PPC::RLWNM || Opc == PPC::RLWNM8 ||
2907  Opc == PPC::RLWNMo || Opc == PPC::RLWNM8o)
2908  III.TruncateImmTo = 5;
2909  else
2910  III.TruncateImmTo = 6;
2911  switch(Opc) {
2912  default: llvm_unreachable("Unknown opcode");
2913  case PPC::RLWNM: III.ImmOpcode = PPC::RLWINM; break;
2914  case PPC::RLWNM8: III.ImmOpcode = PPC::RLWINM8; break;
2915  case PPC::RLWNMo: III.ImmOpcode = PPC::RLWINMo; break;
2916  case PPC::RLWNM8o: III.ImmOpcode = PPC::RLWINM8o; break;
2917  case PPC::SLW: III.ImmOpcode = PPC::RLWINM; break;
2918  case PPC::SLW8: III.ImmOpcode = PPC::RLWINM8; break;
2919  case PPC::SLWo: III.ImmOpcode = PPC::RLWINMo; break;
2920  case PPC::SLW8o: III.ImmOpcode = PPC::RLWINM8o; break;
2921  case PPC::SRW: III.ImmOpcode = PPC::RLWINM; break;
2922  case PPC::SRW8: III.ImmOpcode = PPC::RLWINM8; break;
2923  case PPC::SRWo: III.ImmOpcode = PPC::RLWINMo; break;
2924  case PPC::SRW8o: III.ImmOpcode = PPC::RLWINM8o; break;
2925  case PPC::SRAW:
2926  III.ImmWidth = 5;
2927  III.TruncateImmTo = 0;
2928  III.ImmOpcode = PPC::SRAWI;
2929  break;
2930  case PPC::SRAWo:
2931  III.ImmWidth = 5;
2932  III.TruncateImmTo = 0;
2933  III.ImmOpcode = PPC::SRAWIo;
2934  break;
2935  }
2936  break;
2937  case PPC::RLDCL:
2938  case PPC::RLDCLo:
2939  case PPC::RLDCR:
2940  case PPC::RLDCRo:
2941  case PPC::SLD:
2942  case PPC::SLDo:
2943  case PPC::SRD:
2944  case PPC::SRDo:
2945  case PPC::SRAD:
2946  case PPC::SRADo:
2947  III.SignedImm = false;
2948  III.ZeroIsSpecialOrig = 0;
2949  III.ZeroIsSpecialNew = 0;
2950  III.IsCommutative = false;
2951  // This isn't actually true, but the instructions ignore any of the
2952  // upper bits, so any immediate loaded with an LI is acceptable.
2953  // This does not apply to shift right algebraic because a value
2954  // out of range will produce a -1/0.
2955  III.ImmWidth = 16;
2956  if (Opc == PPC::RLDCL || Opc == PPC::RLDCLo ||
2957  Opc == PPC::RLDCR || Opc == PPC::RLDCRo)
2958  III.TruncateImmTo = 6;
2959  else
2960  III.TruncateImmTo = 7;
2961  switch(Opc) {
2962  default: llvm_unreachable("Unknown opcode");
2963  case PPC::RLDCL: III.ImmOpcode = PPC::RLDICL; break;
2964  case PPC::RLDCLo: III.ImmOpcode = PPC::RLDICLo; break;
2965  case PPC::RLDCR: III.ImmOpcode = PPC::RLDICR; break;
2966  case PPC::RLDCRo: III.ImmOpcode = PPC::RLDICRo; break;
2967  case PPC::SLD: III.ImmOpcode = PPC::RLDICR; break;
2968  case PPC::SLDo: III.ImmOpcode = PPC::RLDICRo; break;
2969  case PPC::SRD: III.ImmOpcode = PPC::RLDICL; break;
2970  case PPC::SRDo: III.ImmOpcode = PPC::RLDICLo; break;
2971  case PPC::SRAD:
2972  III.ImmWidth = 6;
2973  III.TruncateImmTo = 0;
2974  III.ImmOpcode = PPC::SRADI;
2975  break;
2976  case PPC::SRADo:
2977  III.ImmWidth = 6;
2978  III.TruncateImmTo = 0;
2979  III.ImmOpcode = PPC::SRADIo;
2980  break;
2981  }
2982  break;
2983  // Loads and stores:
2984  case PPC::LBZX:
2985  case PPC::LBZX8:
2986  case PPC::LHZX:
2987  case PPC::LHZX8:
2988  case PPC::LHAX:
2989  case PPC::LHAX8:
2990  case PPC::LWZX:
2991  case PPC::LWZX8:
2992  case PPC::LWAX:
2993  case PPC::LDX:
2994  case PPC::LFSX:
2995  case PPC::LFDX:
2996  case PPC::STBX:
2997  case PPC::STBX8:
2998  case PPC::STHX:
2999  case PPC::STHX8:
3000  case PPC::STWX:
3001  case PPC::STWX8:
3002  case PPC::STDX:
3003  case PPC::STFSX:
3004  case PPC::STFDX:
3005  III.SignedImm = true;
3006  III.ZeroIsSpecialOrig = 1;
3007  III.ZeroIsSpecialNew = 2;
3008  III.IsCommutative = true;
3009  III.IsSummingOperands = true;
3010  III.ImmOpNo = 1;
3011  III.OpNoForForwarding = 2;
3012  switch(Opc) {
3013  default: llvm_unreachable("Unknown opcode");
3014  case PPC::LBZX: III.ImmOpcode = PPC::LBZ; break;
3015  case PPC::LBZX8: III.ImmOpcode = PPC::LBZ8; break;
3016  case PPC::LHZX: III.ImmOpcode = PPC::LHZ; break;
3017  case PPC::LHZX8: III.ImmOpcode = PPC::LHZ8; break;
3018  case PPC::LHAX: III.ImmOpcode = PPC::LHA; break;
3019  case PPC::LHAX8: III.ImmOpcode = PPC::LHA8; break;
3020  case PPC::LWZX: III.ImmOpcode = PPC::LWZ; break;
3021  case PPC::LWZX8: III.ImmOpcode = PPC::LWZ8; break;
3022  case PPC::LWAX:
3023  III.ImmOpcode = PPC::LWA;
3024  III.ImmMustBeMultipleOf = 4;
3025  break;
3026  case PPC::LDX: III.ImmOpcode = PPC::LD; III.ImmMustBeMultipleOf = 4; break;
3027  case PPC::LFSX: III.ImmOpcode = PPC::LFS; break;
3028  case PPC::LFDX: III.ImmOpcode = PPC::LFD; break;
3029  case PPC::STBX: III.ImmOpcode = PPC::STB; break;
3030  case PPC::STBX8: III.ImmOpcode = PPC::STB8; break;
3031  case PPC::STHX: III.ImmOpcode = PPC::STH; break;
3032  case PPC::STHX8: III.ImmOpcode = PPC::STH8; break;
3033  case PPC::STWX: III.ImmOpcode = PPC::STW; break;
3034  case PPC::STWX8: III.ImmOpcode = PPC::STW8; break;
3035  case PPC::STDX:
3036  III.ImmOpcode = PPC::STD;
3037  III.ImmMustBeMultipleOf = 4;
3038  break;
3039  case PPC::STFSX: III.ImmOpcode = PPC::STFS; break;
3040  case PPC::STFDX: III.ImmOpcode = PPC::STFD; break;
3041  }
3042  break;
3043  case PPC::LBZUX:
3044  case PPC::LBZUX8:
3045  case PPC::LHZUX:
3046  case PPC::LHZUX8:
3047  case PPC::LHAUX:
3048  case PPC::LHAUX8:
3049  case PPC::LWZUX:
3050  case PPC::LWZUX8:
3051  case PPC::LDUX:
3052  case PPC::LFSUX:
3053  case PPC::LFDUX:
3054  case PPC::STBUX:
3055  case PPC::STBUX8:
3056  case PPC::STHUX:
3057  case PPC::STHUX8:
3058  case PPC::STWUX:
3059  case PPC::STWUX8:
3060  case PPC::STDUX:
3061  case PPC::STFSUX:
3062  case PPC::STFDUX:
3063  III.SignedImm = true;
3064  III.ZeroIsSpecialOrig = 2;
3065  III.ZeroIsSpecialNew = 3;
3066  III.IsCommutative = false;
3067  III.IsSummingOperands = true;
3068  III.ImmOpNo = 2;
3069  III.OpNoForForwarding = 3;
3070  switch(Opc) {
3071  default: llvm_unreachable("Unknown opcode");
3072  case PPC::LBZUX: III.ImmOpcode = PPC::LBZU; break;
3073  case PPC::LBZUX8: III.ImmOpcode = PPC::LBZU8; break;
3074  case PPC::LHZUX: III.ImmOpcode = PPC::LHZU; break;
3075  case PPC::LHZUX8: III.ImmOpcode = PPC::LHZU8; break;
3076  case PPC::LHAUX: III.ImmOpcode = PPC::LHAU; break;
3077  case PPC::LHAUX8: III.ImmOpcode = PPC::LHAU8; break;
3078  case PPC::LWZUX: III.ImmOpcode = PPC::LWZU; break;
3079  case PPC::LWZUX8: III.ImmOpcode = PPC::LWZU8; break;
3080  case PPC::LDUX:
3081  III.ImmOpcode = PPC::LDU;
3082  III.ImmMustBeMultipleOf = 4;
3083  break;
3084  case PPC::LFSUX: III.ImmOpcode = PPC::LFSU; break;
3085  case PPC::LFDUX: III.ImmOpcode = PPC::LFDU; break;
3086  case PPC::STBUX: III.ImmOpcode = PPC::STBU; break;
3087  case PPC::STBUX8: III.ImmOpcode = PPC::STBU8; break;
3088  case PPC::STHUX: III.ImmOpcode = PPC::STHU; break;
3089  case PPC::STHUX8: III.ImmOpcode = PPC::STHU8; break;
3090  case PPC::STWUX: III.ImmOpcode = PPC::STWU; break;
3091  case PPC::STWUX8: III.ImmOpcode = PPC::STWU8; break;
3092  case PPC::STDUX:
3093  III.ImmOpcode = PPC::STDU;
3094  III.ImmMustBeMultipleOf = 4;
3095  break;
3096  case PPC::STFSUX: III.ImmOpcode = PPC::STFSU; break;
3097  case PPC::STFDUX: III.ImmOpcode = PPC::STFDU; break;
3098  }
3099  break;
3100  // Power9 and up only. For some of these, the X-Form version has access to all
3101  // 64 VSR's whereas the D-Form only has access to the VR's. We replace those
3102  // with pseudo-ops pre-ra and for post-ra, we check that the register loaded
3103  // into or stored from is one of the VR registers.
3104  case PPC::LXVX:
3105  case PPC::LXSSPX:
3106  case PPC::LXSDX:
3107  case PPC::STXVX:
3108  case PPC::STXSSPX:
3109  case PPC::STXSDX:
3110  case PPC::XFLOADf32:
3111  case PPC::XFLOADf64:
3112  case PPC::XFSTOREf32:
3113  case PPC::XFSTOREf64:
3114  if (!Subtarget.hasP9Vector())
3115  return false;
3116  III.SignedImm = true;
3117  III.ZeroIsSpecialOrig = 1;
3118  III.ZeroIsSpecialNew = 2;
3119  III.IsCommutative = true;
3120  III.IsSummingOperands = true;
3121  III.ImmOpNo = 1;
3122  III.OpNoForForwarding = 2;
3123  III.ImmMustBeMultipleOf = 4;
3124  switch(Opc) {
3125  default: llvm_unreachable("Unknown opcode");
3126  case PPC::LXVX:
3127  III.ImmOpcode = PPC::LXV;
3128  III.ImmMustBeMultipleOf = 16;
3129  break;
3130  case PPC::LXSSPX:
3131  if (PostRA) {
3132  if (IsVFReg)
3133  III.ImmOpcode = PPC::LXSSP;
3134  else {
3135  III.ImmOpcode = PPC::LFS;
3136  III.ImmMustBeMultipleOf = 1;
3137  }
3138  break;
3139  }
3141  case PPC::XFLOADf32:
3142  III.ImmOpcode = PPC::DFLOADf32;
3143  break;
3144  case PPC::LXSDX:
3145  if (PostRA) {
3146  if (IsVFReg)
3147  III.ImmOpcode = PPC::LXSD;
3148  else {
3149  III.ImmOpcode = PPC::LFD;
3150  III.ImmMustBeMultipleOf = 1;
3151  }
3152  break;
3153  }
3155  case PPC::XFLOADf64:
3156  III.ImmOpcode = PPC::DFLOADf64;
3157  break;
3158  case PPC::STXVX:
3159  III.ImmOpcode = PPC::STXV;
3160  III.ImmMustBeMultipleOf = 16;
3161  break;
3162  case PPC::STXSSPX:
3163  if (PostRA) {
3164  if (IsVFReg)
3165  III.ImmOpcode = PPC::STXSSP;
3166  else {
3167  III.ImmOpcode = PPC::STFS;
3168  III.ImmMustBeMultipleOf = 1;
3169  }
3170  break;
3171  }
3173  case PPC::XFSTOREf32:
3174  III.ImmOpcode = PPC::DFSTOREf32;
3175  break;
3176  case PPC::STXSDX:
3177  if (PostRA) {
3178  if (IsVFReg)
3179  III.ImmOpcode = PPC::STXSD;
3180  else {
3181  III.ImmOpcode = PPC::STFD;
3182  III.ImmMustBeMultipleOf = 1;
3183  }
3184  break;
3185  }
3187  case PPC::XFSTOREf64:
3188  III.ImmOpcode = PPC::DFSTOREf64;
3189  break;
3190  }
3191  break;
3192  }
3193  return true;
3194 }
3195 
3196 // Utility function for swaping two arbitrary operands of an instruction.
3197 static void swapMIOperands(MachineInstr &MI, unsigned Op1, unsigned Op2) {
3198  assert(Op1 != Op2 && "Cannot swap operand with itself.");
3199 
3200  unsigned MaxOp = std::max(Op1, Op2);
3201  unsigned MinOp = std::min(Op1, Op2);
3202  MachineOperand MOp1 = MI.getOperand(MinOp);
3203  MachineOperand MOp2 = MI.getOperand(MaxOp);
3204  MI.RemoveOperand(std::max(Op1, Op2));
3205  MI.RemoveOperand(std::min(Op1, Op2));
3206 
3207  // If the operands we are swapping are the two at the end (the common case)
3208  // we can just remove both and add them in the opposite order.
3209  if (MaxOp - MinOp == 1 && MI.getNumOperands() == MinOp) {
3210  MI.addOperand(MOp2);
3211  MI.addOperand(MOp1);
3212  } else {
3213  // Store all operands in a temporary vector, remove them and re-add in the
3214  // right order.
3216  unsigned TotalOps = MI.getNumOperands() + 2; // We've already removed 2 ops.
3217  for (unsigned i = MI.getNumOperands() - 1; i >= MinOp; i--) {
3218  MOps.push_back(MI.getOperand(i));
3219  MI.RemoveOperand(i);
3220  }
3221  // MOp2 needs to be added next.
3222  MI.addOperand(MOp2);
3223  // Now add the rest.
3224  for (unsigned i = MI.getNumOperands(); i < TotalOps; i++) {
3225  if (i == MaxOp)
3226  MI.addOperand(MOp1);
3227  else {
3228  MI.addOperand(MOps.back());
3229  MOps.pop_back();
3230  }
3231  }
3232  }
3233 }
3234 
3235 // Check if the 'MI' that has the index OpNoForForwarding
3236 // meets the requirement described in the ImmInstrInfo.
3237 bool PPCInstrInfo::isUseMIElgibleForForwarding(MachineInstr &MI,
3238  const ImmInstrInfo &III,
3239  unsigned OpNoForForwarding
3240  ) const {
3241  // As the algorithm of checking for PPC::ZERO/PPC::ZERO8
3242  // would not work pre-RA, we can only do the check post RA.
3244  if (MRI.isSSA())
3245  return false;
3246 
3247  // Cannot do the transform if MI isn't summing the operands.
3248  if (!III.IsSummingOperands)
3249  return false;
3250 
3251  // The instruction we are trying to replace must have the ZeroIsSpecialOrig set.
3252  if (!III.ZeroIsSpecialOrig)
3253  return false;
3254 
3255  // We cannot do the transform if the operand we are trying to replace
3256  // isn't the same as the operand the instruction allows.
3257  if (OpNoForForwarding != III.OpNoForForwarding)
3258  return false;
3259 
3260  // Check if the instruction we are trying to transform really has
3261  // the special zero register as its operand.
3262  if (MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO &&
3263  MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO8)
3264  return false;
3265 
3266  // This machine instruction is convertible if it is,
3267  // 1. summing the operands.
3268  // 2. one of the operands is special zero register.
3269  // 3. the operand we are trying to replace is allowed by the MI.
3270  return true;
3271 }
3272 
3273 // Check if the DefMI is the add inst and set the ImmMO and RegMO
3274 // accordingly.
3275 bool PPCInstrInfo::isDefMIElgibleForForwarding(MachineInstr &DefMI,
3276  const ImmInstrInfo &III,
3277  MachineOperand *&ImmMO,
3278  MachineOperand *&RegMO) const {
3279  unsigned Opc = DefMI.getOpcode();
3280  if (Opc != PPC::ADDItocL && Opc != PPC::ADDI && Opc != PPC::ADDI8)
3281  return false;
3282 
3283  assert(DefMI.getNumOperands() >= 3 &&
3284  "Add inst must have at least three operands");
3285  RegMO = &DefMI.getOperand(1);
3286  ImmMO = &DefMI.getOperand(2);
3287 
3288  // This DefMI is elgible for forwarding if it is:
3289  // 1. add inst
3290  // 2. one of the operands is Imm/CPI/Global.
3291  return isAnImmediateOperand(*ImmMO);
3292 }
3293 
3294 bool PPCInstrInfo::isRegElgibleForForwarding(
3295  const MachineOperand &RegMO, const MachineInstr &DefMI,
3296  const MachineInstr &MI, bool KillDefMI,
3297  bool &IsFwdFeederRegKilled) const {
3298  // x = addi y, imm
3299  // ...
3300  // z = lfdx 0, x -> z = lfd imm(y)
3301  // The Reg "y" can be forwarded to the MI(z) only when there is no DEF
3302  // of "y" between the DEF of "x" and "z".
3303  // The query is only valid post RA.
3305  if (MRI.isSSA())
3306  return false;
3307 
3308  Register Reg = RegMO.getReg();
3309 
3310  // Walking the inst in reverse(MI-->DefMI) to get the last DEF of the Reg.
3313  It++;
3314  for (; It != E; ++It) {
3315  if (It->modifiesRegister(Reg, &getRegisterInfo()) && (&*It) != &DefMI)
3316  return false;
3317  else if (It->killsRegister(Reg, &getRegisterInfo()) && (&*It) != &DefMI)
3318  IsFwdFeederRegKilled = true;
3319  // Made it to DefMI without encountering a clobber.
3320  if ((&*It) == &DefMI)
3321  break;
3322  }
3323  assert((&*It) == &DefMI && "DefMI is missing");
3324 
3325  // If DefMI also defines the register to be forwarded, we can only forward it
3326  // if DefMI is being erased.
3327  if (DefMI.modifiesRegister(Reg, &getRegisterInfo()))
3328  return KillDefMI;
3329 
3330  return true;
3331 }
3332 
3333 bool PPCInstrInfo::isImmElgibleForForwarding(const MachineOperand &ImmMO,
3334  const MachineInstr &DefMI,
3335  const ImmInstrInfo &III,
3336  int64_t &Imm) const {
3337  assert(isAnImmediateOperand(ImmMO) && "ImmMO is NOT an immediate");
3338  if (DefMI.getOpcode() == PPC::ADDItocL) {
3339  // The operand for ADDItocL is CPI, which isn't imm at compiling time,
3340  // However, we know that, it is 16-bit width, and has the alignment of 4.
3341  // Check if the instruction met the requirement.
3342  if (III.ImmMustBeMultipleOf > 4 ||
3343  III.TruncateImmTo || III.ImmWidth != 16)
3344  return false;
3345 
3346  // Going from XForm to DForm loads means that the displacement needs to be
3347  // not just an immediate but also a multiple of 4, or 16 depending on the
3348  // load. A DForm load cannot be represented if it is a multiple of say 2.
3349  // XForm loads do not have this restriction.
3350  if (ImmMO.isGlobal() &&
3351  ImmMO.getGlobal()->getAlignment() < III.ImmMustBeMultipleOf)
3352  return false;
3353 
3354  return true;
3355  }
3356 
3357  if (ImmMO.isImm()) {
3358  // It is Imm, we need to check if the Imm fit the range.
3359  int64_t Immediate = ImmMO.getImm();
3360  // Sign-extend to 64-bits.
3361  Imm = ((uint64_t)Immediate & ~0x7FFFuLL) != 0 ?
3362  (Immediate | 0xFFFFFFFFFFFF0000) : Immediate;
3363 
3364  if (Imm % III.ImmMustBeMultipleOf)
3365  return false;
3366  if (III.TruncateImmTo)
3367  Imm &= ((1 << III.TruncateImmTo) - 1);
3368  if (III.SignedImm) {
3369  APInt ActualValue(64, Imm, true);
3370  if (!ActualValue.isSignedIntN(III.ImmWidth))
3371  return false;
3372  } else {
3373  uint64_t UnsignedMax = (1 << III.ImmWidth) - 1;
3374  if ((uint64_t)Imm > UnsignedMax)
3375  return false;
3376  }
3377  }
3378  else
3379  return false;
3380 
3381  // This ImmMO is forwarded if it meets the requriement describle
3382  // in ImmInstrInfo
3383  return true;
3384 }
3385 
3386 // If an X-Form instruction is fed by an add-immediate and one of its operands
3387 // is the literal zero, attempt to forward the source of the add-immediate to
3388 // the corresponding D-Form instruction with the displacement coming from
3389 // the immediate being added.
3390 bool PPCInstrInfo::transformToImmFormFedByAdd(
3391  MachineInstr &MI, const ImmInstrInfo &III, unsigned OpNoForForwarding,
3392  MachineInstr &DefMI, bool KillDefMI) const {
3393  // RegMO ImmMO
3394  // | |
3395  // x = addi reg, imm <----- DefMI
3396  // y = op 0 , x <----- MI
3397  // |
3398  // OpNoForForwarding
3399  // Check if the MI meet the requirement described in the III.
3400  if (!isUseMIElgibleForForwarding(MI, III, OpNoForForwarding))
3401  return false;
3402 
3403  // Check if the DefMI meet the requirement
3404  // described in the III. If yes, set the ImmMO and RegMO accordingly.
3405  MachineOperand *ImmMO = nullptr;
3406  MachineOperand *RegMO = nullptr;
3407  if (!isDefMIElgibleForForwarding(DefMI, III, ImmMO, RegMO))
3408  return false;
3409  assert(ImmMO && RegMO && "Imm and Reg operand must have been set");
3410 
3411  // As we get the Imm operand now, we need to check if the ImmMO meet
3412  // the requirement described in the III. If yes set the Imm.
3413  int64_t Imm = 0;
3414  if (!isImmElgibleForForwarding(*ImmMO, DefMI, III, Imm))
3415  return false;
3416 
3417  bool IsFwdFeederRegKilled = false;
3418  // Check if the RegMO can be forwarded to MI.
3419  if (!isRegElgibleForForwarding(*RegMO, DefMI, MI, KillDefMI,
3420  IsFwdFeederRegKilled))
3421  return false;
3422 
3423  // Get killed info in case fixup needed after transformation.
3424  unsigned ForwardKilledOperandReg = ~0U;
3426  bool PostRA = !MRI.isSSA();
3427  if (PostRA && MI.getOperand(OpNoForForwarding).isKill())
3428  ForwardKilledOperandReg = MI.getOperand(OpNoForForwarding).getReg();
3429 
3430  // We know that, the MI and DefMI both meet the pattern, and
3431  // the Imm also meet the requirement with the new Imm-form.
3432  // It is safe to do the transformation now.
3433  LLVM_DEBUG(dbgs() << "Replacing instruction:\n");
3434  LLVM_DEBUG(MI.dump());
3435  LLVM_DEBUG(dbgs() << "Fed by:\n");
3436  LLVM_DEBUG(DefMI.dump());
3437 
3438  // Update the base reg first.
3440  false, false,
3441  RegMO->isKill());
3442 
3443  // Then, update the imm.
3444  if (ImmMO->isImm()) {
3445  // If the ImmMO is Imm, change the operand that has ZERO to that Imm
3446  // directly.
3448  }
3449  else {
3450  // Otherwise, it is Constant Pool Index(CPI) or Global,
3451  // which is relocation in fact. We need to replace the special zero
3452  // register with ImmMO.
3453  // Before that, we need to fixup the target flags for imm.
3454  // For some reason, we miss to set the flag for the ImmMO if it is CPI.
3455  if (DefMI.getOpcode() == PPC::ADDItocL)
3457 
3458  // MI didn't have the interface such as MI.setOperand(i) though
3459  // it has MI.getOperand(i). To repalce the ZERO MachineOperand with
3460  // ImmMO, we need to remove ZERO operand and all the operands behind it,
3461  // and, add the ImmMO, then, move back all the operands behind ZERO.
3463  for (unsigned i = MI.getNumOperands() - 1; i >= III.ZeroIsSpecialOrig; i--) {
3464  MOps.push_back(MI.getOperand(i));
3465  MI.RemoveOperand(i);
3466  }
3467 
3468  // Remove the last MO in the list, which is ZERO operand in fact.
3469  MOps.pop_back();
3470  // Add the imm operand.
3471  MI.addOperand(*ImmMO);
3472  // Now add the rest back.
3473  for (auto &MO : MOps)
3474  MI.addOperand(MO);
3475  }
3476 
3477  // Update the opcode.
3478  MI.setDesc(get(III.ImmOpcode));
3479 
3480  // Fix up killed/dead flag after transformation.
3481  // Pattern 1:
3482  // x = ADD KilledFwdFeederReg, imm
3483  // n = opn KilledFwdFeederReg(killed), regn
3484  // y = XOP 0, x
3485  // Pattern 2:
3486  // x = ADD reg(killed), imm
3487  // y = XOP 0, x
3488  if (IsFwdFeederRegKilled || RegMO->isKill())
3489  fixupIsDeadOrKill(DefMI, MI, RegMO->getReg());
3490  // Pattern 3:
3491  // ForwardKilledOperandReg = ADD reg, imm
3492  // y = XOP 0, ForwardKilledOperandReg(killed)
3493  if (ForwardKilledOperandReg != ~0U)
3494  fixupIsDeadOrKill(DefMI, MI, ForwardKilledOperandReg);
3495 
3496  LLVM_DEBUG(dbgs() << "With:\n");
3497  LLVM_DEBUG(MI.dump());
3498 
3499  return true;
3500 }
3501 
3502 bool PPCInstrInfo::transformToImmFormFedByLI(MachineInstr &MI,
3503  const ImmInstrInfo &III,
3504  unsigned ConstantOpNo,
3505  MachineInstr &DefMI,
3506  int64_t Imm) const {
3508  bool PostRA = !MRI.isSSA();
3509  // Exit early if we can't convert this.
3510  if ((ConstantOpNo != III.OpNoForForwarding) && !III.IsCommutative)
3511  return false;
3512  if (Imm % III.ImmMustBeMultipleOf)
3513  return false;
3514  if (III.TruncateImmTo)
3515  Imm &= ((1 << III.TruncateImmTo) - 1);
3516  if (III.SignedImm) {
3517  APInt ActualValue(64, Imm, true);
3518  if (!ActualValue.isSignedIntN(III.ImmWidth))
3519  return false;
3520  } else {
3521  uint64_t UnsignedMax = (1 << III.ImmWidth) - 1;
3522  if ((uint64_t)Imm > UnsignedMax)
3523  return false;
3524  }
3525 
3526  // If we're post-RA, the instructions don't agree on whether register zero is
3527  // special, we can transform this as long as the register operand that will
3528  // end up in the location where zero is special isn't R0.
3529  if (PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) {
3530  unsigned PosForOrigZero = III.ZeroIsSpecialOrig ? III.ZeroIsSpecialOrig :
3531  III.ZeroIsSpecialNew + 1;
3532  Register OrigZeroReg = MI.getOperand(PosForOrigZero).getReg();
3533  Register NewZeroReg = MI.getOperand(III.ZeroIsSpecialNew).getReg();
3534  // If R0 is in the operand where zero is special for the new instruction,
3535  // it is unsafe to transform if the constant operand isn't that operand.
3536  if ((NewZeroReg == PPC::R0 || NewZeroReg == PPC::X0) &&
3537  ConstantOpNo != III.ZeroIsSpecialNew)
3538  return false;
3539  if ((OrigZeroReg == PPC::R0 || OrigZeroReg == PPC::X0) &&
3540  ConstantOpNo != PosForOrigZero)
3541  return false;
3542  }
3543 
3544  // Get killed info in case fixup needed after transformation.
3545  unsigned ForwardKilledOperandReg = ~0U;
3546  if (PostRA && MI.getOperand(ConstantOpNo).isKill())
3547  ForwardKilledOperandReg = MI.getOperand(ConstantOpNo).getReg();
3548 
3549  unsigned Opc = MI.getOpcode();
3550  bool SpecialShift32 =
3551  Opc == PPC::SLW || Opc == PPC::SLWo || Opc == PPC::SRW || Opc == PPC::SRWo;
3552  bool SpecialShift64 =
3553  Opc == PPC::SLD || Opc == PPC::SLDo || Opc == PPC::SRD || Opc == PPC::SRDo;
3554  bool SetCR = Opc == PPC::SLWo || Opc == PPC::SRWo ||
3555  Opc == PPC::SLDo || Opc == PPC::SRDo;
3556  bool RightShift =
3557  Opc == PPC::SRW || Opc == PPC::SRWo || Opc == PPC::SRD || Opc == PPC::SRDo;
3558 
3559  MI.setDesc(get(III.ImmOpcode));
3560  if (ConstantOpNo == III.OpNoForForwarding) {
3561  // Converting shifts to immediate form is a bit tricky since they may do
3562  // one of three things:
3563  // 1. If the shift amount is between OpSize and 2*OpSize, the result is zero
3564  // 2. If the shift amount is zero, the result is unchanged (save for maybe
3565  // setting CR0)
3566  // 3. If the shift amount is in [1, OpSize), it's just a shift
3567  if (SpecialShift32 || SpecialShift64) {
3568  LoadImmediateInfo LII;
3569  LII.Imm = 0;
3570  LII.SetCR = SetCR;
3571  LII.Is64Bit = SpecialShift64;
3572  uint64_t ShAmt = Imm & (SpecialShift32 ? 0x1F : 0x3F);
3573  if (Imm & (SpecialShift32 ? 0x20 : 0x40))
3574  replaceInstrWithLI(MI, LII);
3575  // Shifts by zero don't change the value. If we don't need to set CR0,
3576  // just convert this to a COPY. Can't do this post-RA since we've already
3577  // cleaned up the copies.
3578  else if (!SetCR && ShAmt == 0 && !PostRA) {
3579  MI.RemoveOperand(2);
3580  MI.setDesc(get(PPC::COPY));
3581  } else {
3582  // The 32 bit and 64 bit instructions are quite different.
3583  if (SpecialShift32) {
3584  // Left shifts use (N, 0, 31-N), right shifts use (32-N, N, 31).
3585  uint64_t SH = RightShift ? 32 - ShAmt : ShAmt;
3586  uint64_t MB = RightShift ? ShAmt : 0;
3587  uint64_t ME = RightShift ? 31 : 31 - ShAmt;
3589  MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(MB)
3590  .addImm(ME);
3591  } else {
3592  // Left shifts use (N, 63-N), right shifts use (64-N, N).
3593  uint64_t SH = RightShift ? 64 - ShAmt : ShAmt;
3594  uint64_t ME = RightShift ? ShAmt : 63 - ShAmt;
3596  MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(ME);
3597  }
3598  }
3599  } else
3600  replaceInstrOperandWithImm(MI, ConstantOpNo, Imm);
3601  }
3602  // Convert commutative instructions (switch the operands and convert the
3603  // desired one to an immediate.
3604  else if (III.IsCommutative) {
3605  replaceInstrOperandWithImm(MI, ConstantOpNo, Imm);
3606  swapMIOperands(MI, ConstantOpNo, III.OpNoForForwarding);
3607  } else
3608  llvm_unreachable("Should have exited early!");
3609 
3610  // For instructions for which the constant register replaces a different
3611  // operand than where the immediate goes, we need to swap them.
3612  if (III.OpNoForForwarding != III.ImmOpNo)
3614 
3615  // If the special R0/X0 register index are different for original instruction
3616  // and new instruction, we need to fix up the register class in new
3617  // instruction.
3618  if (!PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) {
3619  if (III.ZeroIsSpecialNew) {
3620  // If operand at III.ZeroIsSpecialNew is physical reg(eg: ZERO/ZERO8), no
3621  // need to fix up register class.
3622  Register RegToModify = MI.getOperand(III.ZeroIsSpecialNew).getReg();
3623  if (Register::isVirtualRegister(RegToModify)) {
3624  const TargetRegisterClass *NewRC =
3625  MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ?
3626  &PPC::GPRC_and_GPRC_NOR0RegClass : &PPC::G8RC_and_G8RC_NOX0RegClass;
3627  MRI.setRegClass(RegToModify, NewRC);
3628  }
3629  }
3630  }
3631 
3632  // Fix up killed/dead flag after transformation.
3633  // Pattern:
3634  // ForwardKilledOperandReg = LI imm
3635  // y = XOP reg, ForwardKilledOperandReg(killed)
3636  if (ForwardKilledOperandReg != ~0U)
3637  fixupIsDeadOrKill(DefMI, MI, ForwardKilledOperandReg);
3638  return true;
3639 }
3640 
3641 const TargetRegisterClass *
3643  if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
3644  return &PPC::VSRCRegClass;
3645  return RC;
3646 }
3647 
3649  return PPC::getRecordFormOpcode(Opcode);
3650 }
3651 
3652 // This function returns true if the machine instruction
3653 // always outputs a value by sign-extending a 32 bit value,
3654 // i.e. 0 to 31-th bits are same as 32-th bit.
3655 static bool isSignExtendingOp(const MachineInstr &MI) {
3656  int Opcode = MI.getOpcode();
3657  if (Opcode == PPC::LI || Opcode == PPC::LI8 ||
3658  Opcode == PPC::LIS || Opcode == PPC::LIS8 ||
3659  Opcode == PPC::SRAW || Opcode == PPC::SRAWo ||
3660  Opcode == PPC::SRAWI || Opcode == PPC::SRAWIo ||
3661  Opcode == PPC::LWA || Opcode == PPC::LWAX ||
3662  Opcode == PPC::LWA_32 || Opcode == PPC::LWAX_32 ||
3663  Opcode == PPC::LHA || Opcode == PPC::LHAX ||
3664  Opcode == PPC::LHA8 || Opcode == PPC::LHAX8 ||
3665  Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
3666  Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
3667  Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
3668  Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
3669  Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
3670  Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 ||
3671  Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
3672  Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 ||
3673  Opcode == PPC::EXTSB || Opcode == PPC::EXTSBo ||
3674  Opcode == PPC::EXTSH || Opcode == PPC::EXTSHo ||
3675  Opcode == PPC::EXTSB8 || Opcode == PPC::EXTSH8 ||
3676  Opcode == PPC::EXTSW || Opcode == PPC::EXTSWo ||
3677  Opcode == PPC::SETB || Opcode == PPC::SETB8 ||
3678  Opcode == PPC::EXTSH8_32_64 || Opcode == PPC::EXTSW_32_64 ||
3679  Opcode == PPC::EXTSB8_32_64)
3680  return true;
3681 
3682  if (Opcode == PPC::RLDICL && MI.getOperand(3).getImm() >= 33)
3683  return true;
3684 
3685  if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
3686  Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo) &&
3687  MI.getOperand(3).getImm() > 0 &&
3688  MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
3689  return true;
3690 
3691  return false;
3692 }
3693 
3694 // This function returns true if the machine instruction
3695 // always outputs zeros in higher 32 bits.
3696 static bool isZeroExtendingOp(const MachineInstr &MI) {
3697  int Opcode = MI.getOpcode();
3698  // The 16-bit immediate is sign-extended in li/lis.
3699  // If the most significant bit is zero, all higher bits are zero.
3700  if (Opcode == PPC::LI || Opcode == PPC::LI8 ||
3701  Opcode == PPC::LIS || Opcode == PPC::LIS8) {
3702  int64_t Imm = MI.getOperand(1).getImm();
3703  if (((uint64_t)Imm & ~0x7FFFuLL) == 0)
3704  return true;
3705  }
3706 
3707  // We have some variations of rotate-and-mask instructions
3708  // that clear higher 32-bits.
3709  if ((Opcode == PPC::RLDICL || Opcode == PPC::RLDICLo ||
3710  Opcode == PPC::RLDCL || Opcode == PPC::RLDCLo ||
3711  Opcode == PPC::RLDICL_32_64) &&
3712  MI.getOperand(3).getImm() >= 32)
3713  return true;
3714 
3715  if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDICo) &&
3716  MI.getOperand(3).getImm() >= 32 &&
3717  MI.getOperand(3).getImm() <= 63 - MI.getOperand(2).getImm())
3718  return true;
3719 
3720  if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
3721  Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo ||
3722  Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) &&
3723  MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
3724  return true;
3725 
3726  // There are other instructions that clear higher 32-bits.
3727  if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZWo ||
3728  Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZWo ||
3729  Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8 ||
3730  Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZDo ||
3731  Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZDo ||
3732  Opcode == PPC::POPCNTD || Opcode == PPC::POPCNTW ||
3733  Opcode == PPC::SLW || Opcode == PPC::SLWo ||
3734  Opcode == PPC::SRW || Opcode == PPC::SRWo ||
3735  Opcode == PPC::SLW8 || Opcode == PPC::SRW8 ||
3736  Opcode == PPC::SLWI || Opcode == PPC::SLWIo ||
3737  Opcode == PPC::SRWI || Opcode == PPC::SRWIo ||
3738  Opcode == PPC::LWZ || Opcode == PPC::LWZX ||
3739  Opcode == PPC::LWZU || Opcode == PPC::LWZUX ||
3740  Opcode == PPC::LWBRX || Opcode == PPC::LHBRX ||
3741  Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
3742  Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
3743  Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
3744  Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
3745  Opcode == PPC::LWZ8 || Opcode == PPC::LWZX8 ||
3746  Opcode == PPC::LWZU8 || Opcode == PPC::LWZUX8 ||
3747  Opcode == PPC::LWBRX8 || Opcode == PPC::LHBRX8 ||
3748  Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 ||
3749  Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 ||
3750  Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
3751  Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
3752  Opcode == PPC::ANDIo || Opcode == PPC::ANDISo ||
3753  Opcode == PPC::ROTRWI || Opcode == PPC::ROTRWIo ||
3754  Opcode == PPC::EXTLWI || Opcode == PPC::EXTLWIo ||
3755  Opcode == PPC::MFVSRWZ)
3756  return true;
3757 
3758  return false;
3759 }
3760 
3761 // This function returns true if the input MachineInstr is a TOC save
3762 // instruction.
3764  if (!MI.getOperand(1).isImm() || !MI.getOperand(2).isReg())
3765  return false;
3766  unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
3767  unsigned StackOffset = MI.getOperand(1).getImm();
3768  Register StackReg = MI.getOperand(2).getReg();
3769  if (StackReg == PPC::X1 && StackOffset == TOCSaveOffset)
3770  return true;
3771 
3772  return false;
3773 }
3774 
3775 // We limit the max depth to track incoming values of PHIs or binary ops
3776 // (e.g. AND) to avoid excessive cost.
3777 const unsigned MAX_DEPTH = 1;
3778 
3779 bool
3781  const unsigned Depth) const {
3782  const MachineFunction *MF = MI.getParent()->getParent();
3783  const MachineRegisterInfo *MRI = &MF->getRegInfo();
3784 
3785  // If we know this instruction returns sign- or zero-extended result,
3786  // return true.
3787  if (SignExt ? isSignExtendingOp(MI):
3788  isZeroExtendingOp(MI))
3789  return true;
3790 
3791  switch (MI.getOpcode()) {
3792  case PPC::COPY: {
3793  Register SrcReg = MI.getOperand(1).getReg();
3794 
3795  // In both ELFv1 and v2 ABI, method parameters and the return value
3796  // are sign- or zero-extended.
3797  if (MF->getSubtarget<PPCSubtarget>().isSVR4ABI()) {
3798  const PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
3799  // We check the ZExt/SExt flags for a method parameter.
3800  if (MI.getParent()->getBasicBlock() ==
3801  &MF->getFunction().getEntryBlock()) {
3802  Register VReg = MI.getOperand(0).getReg();
3803  if (MF->getRegInfo().isLiveIn(VReg))
3804  return SignExt ? FuncInfo->isLiveInSExt(VReg) :
3805  FuncInfo->isLiveInZExt(VReg);
3806  }
3807 
3808  // For a method return value, we check the ZExt/SExt flags in attribute.
3809  // We assume the following code sequence for method call.
3810  // ADJCALLSTACKDOWN 32, implicit dead %r1, implicit %r1
3811  // BL8_NOP @func,...
3812  // ADJCALLSTACKUP 32, 0, implicit dead %r1, implicit %r1
3813  // %5 = COPY %x3; G8RC:%5
3814  if (SrcReg == PPC::X3) {
3815  const MachineBasicBlock *MBB = MI.getParent();
3818  if (II != MBB->instr_begin() &&
3819  (--II)->getOpcode() == PPC::ADJCALLSTACKUP) {
3820  const MachineInstr &CallMI = *(--II);
3821  if (CallMI.isCall() && CallMI.getOperand(0).isGlobal()) {
3822  const Function *CalleeFn =
3823  dyn_cast<Function>(CallMI.getOperand(0).getGlobal());
3824  if (!CalleeFn)
3825  return false;
3826  const IntegerType *IntTy =
3827  dyn_cast<IntegerType>(CalleeFn->getReturnType());
3828  const AttributeSet &Attrs =
3829  CalleeFn->getAttributes().getRetAttributes();
3830  if (IntTy && IntTy->getBitWidth() <= 32)
3831  return Attrs.hasAttribute(SignExt ? Attribute::SExt :
3832  Attribute::ZExt);
3833  }
3834  }
3835  }
3836  }
3837 
3838  // If this is a copy from another register, we recursively check source.
3839  if (!Register::isVirtualRegister(SrcReg))
3840  return false;
3841  const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3842  if (SrcMI != NULL)
3843  return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
3844 
3845  return false;
3846  }
3847 
3848  case PPC::ANDIo:
3849  case PPC::ANDISo:
3850  case PPC::ORI:
3851  case PPC::ORIS:
3852  case PPC::XORI:
3853  case PPC::XORIS:
3854  case PPC::ANDIo8:
3855  case PPC::ANDISo8:
3856  case PPC::ORI8:
3857  case PPC::ORIS8:
3858  case PPC::XORI8:
3859  case PPC::XORIS8: {
3860  // logical operation with 16-bit immediate does not change the upper bits.
3861  // So, we track the operand register as we do for register copy.
3862  Register SrcReg = MI.getOperand(1).getReg();
3863  if (!Register::isVirtualRegister(SrcReg))
3864  return false;
3865  const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3866  if (SrcMI != NULL)
3867  return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
3868 
3869  return false;
3870  }
3871 
3872  // If all incoming values are sign-/zero-extended,
3873  // the output of OR, ISEL or PHI is also sign-/zero-extended.
3874  case PPC::OR:
3875  case PPC::OR8:
3876  case PPC::ISEL:
3877  case PPC::PHI: {
3878  if (Depth >= MAX_DEPTH)
3879  return false;
3880 
3881  // The input registers for PHI are operand 1, 3, ...
3882  // The input registers for others are operand 1 and 2.
3883  unsigned E = 3, D = 1;
3884  if (MI.getOpcode() == PPC::PHI) {
3885  E = MI.getNumOperands();
3886  D = 2;
3887  }
3888 
3889  for (unsigned I = 1; I != E; I += D) {
3890  if (MI.getOperand(I).isReg()) {
3891  Register SrcReg = MI.getOperand(I).getReg();
3892  if (!Register::isVirtualRegister(SrcReg))
3893  return false;
3894  const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3895  if (SrcMI == NULL || !isSignOrZeroExtended(*SrcMI, SignExt, Depth+1))
3896  return false;
3897  }
3898  else
3899  return false;
3900  }
3901  return true;
3902  }
3903 
3904  // If at least one of the incoming values of an AND is zero extended
3905  // then the output is also zero-extended. If both of the incoming values
3906  // are sign-extended then the output is also sign extended.
3907  case PPC::AND:
3908  case PPC::AND8: {
3909  if (Depth >= MAX_DEPTH)
3910  return false;
3911 
3912  assert(MI.getOperand(1).isReg() && MI.getOperand(2).isReg());
3913 
3914  Register SrcReg1 = MI.getOperand(1).getReg();
3915  Register SrcReg2 = MI.getOperand(2).getReg();
3916 
3917  if (!Register::isVirtualRegister(SrcReg1) ||
3918  !Register::isVirtualRegister(SrcReg2))
3919  return false;
3920 
3921  const MachineInstr *MISrc1 = MRI->getVRegDef(SrcReg1);
3922  const MachineInstr *MISrc2 = MRI->getVRegDef(SrcReg2);
3923  if (!MISrc1 || !MISrc2)
3924  return false;
3925 
3926  if(SignExt)
3927  return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) &&
3928  isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
3929  else
3930  return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) ||
3931  isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
3932  }
3933 
3934  default:
3935  break;
3936  }
3937  return false;
3938 }
3939 
3940 bool PPCInstrInfo::isBDNZ(unsigned Opcode) const {
3941  return (Opcode == (Subtarget.isPPC64() ? PPC::BDNZ8 : PPC::BDNZ));
3942 }
3943 
3945  MachineInstr *&CmpInst) const {
3946  MachineBasicBlock *LoopEnd = L.getBottomBlock();
3948  // We really "analyze" only CTR loops right now.
3949  if (I != LoopEnd->end() && isBDNZ(I->getOpcode())) {
3950  IndVarInst = nullptr;
3951  CmpInst = &*I;
3952  return false;
3953  }
3954  return true;
3955 }
3956 
3957 MachineInstr *
3959 
3960  unsigned LOOPi = (Subtarget.isPPC64() ? PPC::MTCTR8loop : PPC::MTCTRloop);
3961 
3962  // The loop set-up instruction should be in preheader
3963  for (auto &I : PreHeader.instrs())
3964  if (I.getOpcode() == LOOPi)
3965  return &I;
3966  return nullptr;
3967 }
3968 
3970  MachineBasicBlock &MBB, MachineBasicBlock &PreHeader, MachineInstr *IndVar,
3972  SmallVectorImpl<MachineInstr *> &PrevInsts, unsigned Iter,
3973  unsigned MaxIter) const {
3974  // We expect a hardware loop currently. This means that IndVar is set
3975  // to null, and the compare is the ENDLOOP instruction.
3976  assert((!IndVar) && isBDNZ(Cmp.getOpcode()) && "Expecting a CTR loop");
3977  MachineFunction *MF = MBB.getParent();
3978  DebugLoc DL = Cmp.getDebugLoc();
3979  MachineInstr *Loop = findLoopInstr(PreHeader);
3980  if (!Loop)
3981  return 0;
3982  Register LoopCountReg = Loop->getOperand(0).getReg();
3984  MachineInstr *LoopCount = MRI.getUniqueVRegDef(LoopCountReg);
3985 
3986  if (!LoopCount)
3987  return 0;
3988  // If the loop trip count is a compile-time value, then just change the
3989  // value.
3990  if (LoopCount->getOpcode() == PPC::LI8 || LoopCount->getOpcode() == PPC::LI) {
3991  int64_t Offset = LoopCount->getOperand(1).getImm();
3992  if (Offset <= 1) {
3993  LoopCount->eraseFromParent();
3994  Loop->eraseFromParent();
3995  return 0;
3996  }
3997  LoopCount->getOperand(1).setImm(Offset - 1);
3998  return Offset - 1;
3999  }
4000 
4001  // The loop trip count is a run-time value.
4002  // We need to subtract one from the trip count,
4003  // and insert branch later to check if we're done with the loop.
4004 
4005  // Since BDZ/BDZ8 that we will insert will also decrease the ctr by 1,
4006  // so we don't need to generate any thing here.
4009  Subtarget.isPPC64() ? PPC::CTR8 : PPC::CTR, true));
4010  return LoopCountReg;
4011 }
4012 
4013 // Return true if get the base operand, byte offset of an instruction and the
4014 // memory width. Width is the size of memory that is being loaded/stored.
4016  const MachineInstr &LdSt,
4017  const MachineOperand *&BaseReg,
4018  int64_t &Offset,
4019  unsigned &Width,
4020  const TargetRegisterInfo *TRI) const {
4021  assert(LdSt.mayLoadOrStore() && "Expected a memory operation.");
4022 
4023  // Handle only loads/stores with base register followed by immediate offset.
4024  if (LdSt.getNumExplicitOperands() != 3)
4025  return false;
4026  if (!LdSt.getOperand(1).isImm() || !LdSt.getOperand(2).isReg())
4027  return false;
4028 
4029  if (!LdSt.hasOneMemOperand())
4030  return false;
4031 
4032  Width = (*LdSt.memoperands_begin())->getSize();
4033  Offset = LdSt.getOperand(1).getImm();
4034  BaseReg = &LdSt.getOperand(2);
4035  return true;
4036 }
4037 
4039  const MachineInstr &MIa, const MachineInstr &MIb,
4040  AliasAnalysis * /*AA*/) const {
4041  assert(MIa.mayLoadOrStore() && "MIa must be a load or store.");
4042  assert(MIb.mayLoadOrStore() && "MIb must be a load or store.");
4043 
4044  if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
4046  return false;
4047 
4048  // Retrieve the base register, offset from the base register and width. Width
4049  // is the size of memory that is being loaded/stored (e.g. 1, 2, 4). If
4050  // base registers are identical, and the offset of a lower memory access +
4051  // the width doesn't overlap the offset of a higher memory access,
4052  // then the memory accesses are different.
4054  const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr;
4055  int64_t OffsetA = 0, OffsetB = 0;
4056  unsigned int WidthA = 0, WidthB = 0;
4057  if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) &&
4058  getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
4059  if (BaseOpA->isIdenticalTo(*BaseOpB)) {
4060  int LowOffset = std::min(OffsetA, OffsetB);
4061  int HighOffset = std::max(OffsetA, OffsetB);
4062  int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
4063  if (LowOffset + LowWidth <= HighOffset)
4064  return true;
4065  }
4066  }
4067  return false;
4068 }
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:722
void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const
instr_iterator instr_begin()
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
StackOffset is a wrapper around scalable and non-scalable offsets and is used in several functions su...
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:635
int getNonRecordFormOpcode(uint16_t)
MachineBasicBlock * getMBB() const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
uint64_t ZeroIsSpecialNew
Definition: PPCInstrInfo.h:86
void setTargetFlags(unsigned F)
iterator begin() const
begin/end - Return all of the registers in this class.
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:222
bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III, bool PostRA) const
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:385
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:543
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:178
static int getRecordFormOpcode(unsigned Opcode)
unsigned Reg
unsigned getSubReg() const
bool hasVSX() const
Definition: PPCSubtarget.h:252
static cl::opt< bool > DisableCmpOpt("disable-ppc-cmp-opt", cl::desc("Disable compare instruction optimization"), cl::Hidden)
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
Return true if get the base operand, byte offset of an instruction and the memory width...
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
uint64_t IsCommutative
Definition: PPCInstrInfo.h:88
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
Definition: MachineInstr.h:832
uint64_t TruncateImmTo
Definition: PPCInstrInfo.h:98
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:305
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
void setIsDead(bool Val=true)
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
MachineInstr * findLoopInstr(MachineBasicBlock &PreHeader) const
Find the hardware loop instruction used to set-up the specified loop.
bool isPseudo() const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MCInstrDesc.h:257
CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
#define R2(n)
uint64_t OpNoForForwarding
Definition: PPCInstrInfo.h:90
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
uint64_t IsSummingOperands
Definition: PPCInstrInfo.h:100
bool isSignExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always a sign-extended, i.e.
Definition: PPCInstrInfo.h:414
void clearRegisterDeads(Register Reg)
Clear all dead flags on operands defining register Reg.
return AArch64::GPR64RegClass contains(Reg)
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling th...
MachineFunction & MF
Machine function.
Definition: ScheduleDAG.h:560
bool isXFormMemOp(unsigned Opcode) const
Definition: PPCInstrInfo.h:187
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst, MachineInstr *&CmpInst) const override
Analyze the loop code to find the loop induction variable and compare used to compute the number of i...
PPCDispatchGroupSBHazardRecognizer - This class implements a scoreboard-based hazard recognizer for P...
A description of a memory reference used in the backend.
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:225
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:450
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:414
bool hasDirectMove() const
Definition: PPCSubtarget.h:281
static Optional< unsigned > getOpcode(ArrayRef< VPValue *> Values)
Returns the opcode of Values or ~0 if they do not all agree.
Definition: VPlanSLP.cpp:196
MachineBasicBlock * getBottomBlock()
Return the "bottom" block in the loop, which is the last block in the linear layout, ignoring any parts of the loop not contiguous with the part that contains the header.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:651
AttributeSet getRetAttributes() const
The attributes for the ret value are returned.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
const TargetRegisterClass * updatedRC(const TargetRegisterClass *RC) const
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const override
uint64_t ZeroIsSpecialOrig
Definition: PPCInstrInfo.h:83
const char * getSymbolName() const
static bool isZeroExtendingOp(const MachineInstr &MI)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:695
static void swapMIOperands(MachineInstr &MI, unsigned Op1, unsigned Op2)
void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo, int64_t Imm) const
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
bool isTOCSaveMI(const MachineInstr &MI) const
defusechain_iterator - This class provides iterator support for machine operands in the function that...
PPCInstrInfo(PPCSubtarget &STI)
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1581
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:408
CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based loops.
bool hasP9Vector() const
Definition: PPCSubtarget.h:257
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const override
MO_NLP_HIDDEN_FLAG - If this bit is set, the symbol reference is to a symbol with hidden visibility...
Definition: PPC.h:104
virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns) const
Return true when there is potentially a faster code sequence for an instruction chain ending in Root...
CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
Itinerary data supplied by a subtarget to be used by a target.
const PPCTargetMachine & getTargetMachine() const
Definition: PPCSubtarget.h:194
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:223
void setReg(Register Reg)
Change the register this operand corresponds to.
unsigned getAlignment() const
Definition: Globals.cpp:97
constexpr char Attrs[]
Key for Kernel::Metadata::mAttrs.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
unsigned getBitWidth() const
Get the number of bits in this IntegerType.
Definition: DerivedTypes.h:66
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
reverse_iterator rend()
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:659
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
unsigned getKillRegState(bool B)
bool hasAttribute(Attribute::AttrKind Kind) const
Return true if the attribute exists in this set.
Definition: Attributes.cpp:657
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:19
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
unsigned getDeadRegState(bool B)
VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
const BasicBlock & getEntryBlock() const
Definition: Function.h:664
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:596
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, const unsigned PhiDepth) const
Type * getReturnType() const
Returns the type of the ret val.
Definition: Function.h:168
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:565
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static unsigned selectReg(int64_t Imm1, int64_t Imm2, unsigned CompareOpc, unsigned TrueReg, unsigned FalseReg, unsigned CRSubReg)
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
unsigned const MachineRegisterInfo * MRI
bool isLiveInSExt(unsigned VReg) const
This function returns true if the specified vreg is a live-in register and sign-extended.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
int getAltVSXFMAOpcode(uint16_t Opcode)
Simple binary floating point operators.
Definition: ISDOpcodes.h:287
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineInstrBuilder & UseMI
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
MO_NLP_FLAG - If this bit is set, the symbol reference is actually to the non_lazy_ptr for the global...
Definition: PPC.h:99
const GlobalValue * getGlobal() const
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:30
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:188
STFIWX - The STFIWX instruction.
use_instr_iterator use_instr_begin(unsigned RegNo) const
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:551
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
void setImm(int64_t immVal)
GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point load which sign-extends from a 32-bit inte...
MI-level patchpoint operands.
Definition: StackMaps.h:76
Class to represent integer types.
Definition: DerivedTypes.h:40
PPCHazardRecognizer970 - This class defines a finite state automata that models the dispatch logic on...
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
unsigned getStoreOpcodeForSpill(unsigned Reg, const TargetRegisterClass *RC=nullptr) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
size_t size() const
Definition: SmallVector.h:52
auto find(R &&Range, const T &Val) -> decltype(adl_begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1198
unsigned getPredicateHint(Predicate Opcode)
Return the hint bits of the predicate.
Definition: PPCPredicates.h:82
unsigned getDarwinDirective() const
getDarwinDirective - Returns the -m directive specified for the cpu.
Definition: PPCSubtarget.h:173
static unsigned getCRFromCRBit(unsigned SrcReg)
MO_TLS - Indicates that the operand being accessed is some kind of thread-local symbol.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
unsigned first
void setIsKill(bool Val=true)
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
The next are not flags but distinct values.
Definition: PPC.h:107
constexpr bool empty(const T &RangeOrContainer)
Test whether RangeOrContainer is empty. Similar to C++17 std::empty.
Definition: STLExtras.h:209
The memory access writes data.
static bool MBBDefinesCTR(MachineBasicBlock &MBB)
bool isBDNZ(unsigned Opcode) const
Check Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:202
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given stackmap should emit.
Definition: StackMaps.h:50
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Predicate getPredicate(unsigned Condition, unsigned Hint)
Return predicate consisting of specified condition and hint bits.
Definition: PPCPredicates.h:87
Iterator for intrusive lists based on ilist_node.
void setOpcode(unsigned Op)
Definition: MCInst.h:170
bool isUnpredicatedTerminator(const MachineInstr &MI) const override
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:536
static uint64_t add(uint64_t LeftOp, uint64_t RightOp)
Definition: FileCheck.cpp:243
void getNoop(MCInst &NopInst) const override
Return the noop instruction to use for a noop.
static unsigned getCRBitValue(unsigned CRBit)
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1035
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
static cl::opt< bool > VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy", cl::desc("Causes the backend to crash instead of generating a nop VSX copy"), cl::Hidden)
static cl::opt< bool > UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden, cl::desc("Use the old (incorrect) instruction latency calculation"))
APInt rotl(unsigned rotateAmt) const
Rotate left by rotateAmt.
Definition: APInt.cpp:997
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
static bool isVFRegister(unsigned Reg)
Definition: PPCInstrInfo.h:398
int64_t getImm() const
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const Function & getFunction() const
Return the LLVM function that this machine code represents.
virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Class for arbitrary precision integers.
Definition: APInt.h:69
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
QVGPCI = This corresponds to the QPX qvgpci instruction.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
MachineInstr * getDefMIPostRA(unsigned Reg, MachineInstr &MI, bool &SeenIntermediateUse) const
iterator_range< mop_iterator > implicit_operands()
Definition: MachineInstr.h:475
bool use_empty(unsigned RegNo) const
use_empty - Return true if there are no instructions using the specified register.
int findRegisterUseOperandIdx(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found...
On a symbol operand, this represents the lo part.
Definition: AVRInstrInfo.h:52
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:256
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
TargetSubtargetInfo - Generic base class for all target subtargets.
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in <Root...
bool isPredicated(const MachineInstr &MI) const override
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
bool isLiveIn(unsigned Reg) const
unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineBasicBlock &PreHeader, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr *> &PrevInsts, unsigned Iter, unsigned MaxIter) const override
Generate code to reduce the loop iteration by one and check if the loop is finished.
Representation of each machine instruction.
Definition: MachineInstr.h:64
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Predicate InvertPredicate(Predicate Opcode)
Invert the specified predicate. != -> ==, < -> >=.
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
Return true if two MIs access different memory addresses and false otherwise.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:411
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
bool hasOneUse(unsigned RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MI-level stackmap operands.
Definition: StackMaps.h:35
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:509
TargetOptions Options
static bool isSignExtendingOp(const MachineInstr &MI)
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned getLoadOpcodeForSpill(unsigned Reg, const TargetRegisterClass *RC=nullptr) const
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
void setSubReg(unsigned subReg)
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
void fixupIsDeadOrKill(MachineInstr &StartMI, MachineInstr &EndMI, unsigned RegNo) const
Fixup killed/dead flag for register RegNo between instructions [StartMI, EndMI].
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given patchpoint should emit.
Definition: StackMaps.h:104
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:558
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register...
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:345
bool isSignedIntN(unsigned N) const
Check if this APInt has an N-bits signed integer value.
Definition: APInt.h:455
const unsigned MAX_DEPTH
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator_range< use_instr_iterator > use_instructions(unsigned Reg) const
uint64_t ImmMustBeMultipleOf
Definition: PPCInstrInfo.h:80
unsigned getPredicateCondition(Predicate Opcode)
Return the condition without hint bits.
Definition: PPCPredicates.h:77
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
bool isLiveInZExt(unsigned VReg) const
This function returns true if the specified vreg is a live-in register and zero-extended.
INLINEASM_BR - Terminator version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:698
LLVM Value Representation.
Definition: Value.h:73
static use_instr_iterator use_instr_end()
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:69
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:258
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:189
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when ...
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
IRTranslator LLVM IR MI
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:642
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
bool isPredicable(const MachineInstr &MI) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool isSVR4ABI() const
Definition: PPCSubtarget.h:320
Register getReg() const
getReg - Returns the register number.
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:70
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
On a symbol operand "FOO", this indicates that the reference is actually to "FOO@plt".
Definition: PPC.h:91
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: PPCInstrInfo.h:185
virtual unsigned lookThruCopyLike(unsigned SrcReg, const MachineRegisterInfo *MRI) const
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:313
static cl::opt< bool > DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden, cl::desc("Disable analysis for CTR loops"))
Instructions::const_iterator const_instr_iterator
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point load which zero-extends from a 32-bit inte...
SpillOpcodeKey
MO_PIC_FLAG - If this bit is set, the symbol reference is relative to the function&#39;s picbase...
Definition: PPC.h:95
bool convertToImmediateForm(MachineInstr &MI, MachineInstr **KilledDef=nullptr) const
static bool isAnImmediateOperand(const MachineOperand &MO)
bool expandPostRAPseudo(MachineInstr &MI) const override
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:143
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:187
bool expandVSXMemPseudo(MachineInstr &MI) const
bool isImplicit() const
bool isZeroExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always zero-extended, i.e.
Definition: PPCInstrInfo.h:420
Predicate getSwappedPredicate(Predicate Opcode)
Assume the condition register is set by MI(a,b), return the predicate if we modify the instructions s...