LLVM  10.0.0svn
PPCInstrInfo.cpp
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1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the PowerPC implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "PPCInstrInfo.h"
15 #include "PPC.h"
16 #include "PPCHazardRecognizers.h"
17 #include "PPCInstrBuilder.h"
18 #include "PPCMachineFunctionInfo.h"
19 #include "PPCTargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Statistic.h"
31 #include "llvm/CodeGen/StackMaps.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/MC/MCInst.h"
35 #include "llvm/Support/Debug.h"
39 
40 using namespace llvm;
41 
42 #define DEBUG_TYPE "ppc-instr-info"
43 
44 #define GET_INSTRMAP_INFO
45 #define GET_INSTRINFO_CTOR_DTOR
46 #include "PPCGenInstrInfo.inc"
47 
48 STATISTIC(NumStoreSPILLVSRRCAsVec,
49  "Number of spillvsrrc spilled to stack as vec");
50 STATISTIC(NumStoreSPILLVSRRCAsGpr,
51  "Number of spillvsrrc spilled to stack as gpr");
52 STATISTIC(NumGPRtoVSRSpill, "Number of gpr spills to spillvsrrc");
53 STATISTIC(CmpIselsConverted,
54  "Number of ISELs that depend on comparison of constants converted");
55 STATISTIC(MissedConvertibleImmediateInstrs,
56  "Number of compare-immediate instructions fed by constants");
57 STATISTIC(NumRcRotatesConvertedToRcAnd,
58  "Number of record-form rotates converted to record-form andi");
59 
60 static cl::
61 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
62  cl::desc("Disable analysis for CTR loops"));
63 
64 static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
65 cl::desc("Disable compare instruction optimization"), cl::Hidden);
66 
67 static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
68 cl::desc("Causes the backend to crash instead of generating a nop VSX copy"),
69 cl::Hidden);
70 
71 static cl::opt<bool>
72 UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
73  cl::desc("Use the old (incorrect) instruction latency calculation"));
74 
75 // Index into the OpcodesForSpill array.
93  SOK_LastOpcodeSpill // This must be last on the enum.
94 };
95 
96 // Pin the vtable to this file.
97 void PPCInstrInfo::anchor() {}
98 
100  : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP,
101  /* CatchRetOpcode */ -1,
102  STI.isPPC64() ? PPC::BLR8 : PPC::BLR),
103  Subtarget(STI), RI(STI.getTargetMachine()) {}
104 
105 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
106 /// this target when scheduling the DAG.
109  const ScheduleDAG *DAG) const {
110  unsigned Directive =
111  static_cast<const PPCSubtarget *>(STI)->getDarwinDirective();
112  if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
113  Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
114  const InstrItineraryData *II =
115  static_cast<const PPCSubtarget *>(STI)->getInstrItineraryData();
116  return new ScoreboardHazardRecognizer(II, DAG);
117  }
118 
120 }
121 
122 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
123 /// to use for this target when scheduling the DAG.
126  const ScheduleDAG *DAG) const {
127  unsigned Directive =
128  DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
129 
130  // FIXME: Leaving this as-is until we have POWER9 scheduling info
131  if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8)
132  return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
133 
134  // Most subtargets use a PPC970 recognizer.
135  if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
136  Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
137  assert(DAG->TII && "No InstrInfo?");
138 
139  return new PPCHazardRecognizer970(*DAG);
140  }
141 
142  return new ScoreboardHazardRecognizer(II, DAG);
143 }
144 
146  const MachineInstr &MI,
147  unsigned *PredCost) const {
148  if (!ItinData || UseOldLatencyCalc)
149  return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
150 
151  // The default implementation of getInstrLatency calls getStageLatency, but
152  // getStageLatency does not do the right thing for us. While we have
153  // itinerary, most cores are fully pipelined, and so the itineraries only
154  // express the first part of the pipeline, not every stage. Instead, we need
155  // to use the listed output operand cycle number (using operand 0 here, which
156  // is an output).
157 
158  unsigned Latency = 1;
159  unsigned DefClass = MI.getDesc().getSchedClass();
160  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
161  const MachineOperand &MO = MI.getOperand(i);
162  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
163  continue;
164 
165  int Cycle = ItinData->getOperandCycle(DefClass, i);
166  if (Cycle < 0)
167  continue;
168 
169  Latency = std::max(Latency, (unsigned) Cycle);
170  }
171 
172  return Latency;
173 }
174 
176  const MachineInstr &DefMI, unsigned DefIdx,
177  const MachineInstr &UseMI,
178  unsigned UseIdx) const {
179  int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
180  UseMI, UseIdx);
181 
182  if (!DefMI.getParent())
183  return Latency;
184 
185  const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
186  Register Reg = DefMO.getReg();
187 
188  bool IsRegCR;
189  if (Register::isVirtualRegister(Reg)) {
190  const MachineRegisterInfo *MRI =
191  &DefMI.getParent()->getParent()->getRegInfo();
192  IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
193  MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
194  } else {
195  IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
196  PPC::CRBITRCRegClass.contains(Reg);
197  }
198 
199  if (UseMI.isBranch() && IsRegCR) {
200  if (Latency < 0)
201  Latency = getInstrLatency(ItinData, DefMI);
202 
203  // On some cores, there is an additional delay between writing to a condition
204  // register, and using it from a branch.
205  unsigned Directive = Subtarget.getDarwinDirective();
206  switch (Directive) {
207  default: break;
208  case PPC::DIR_7400:
209  case PPC::DIR_750:
210  case PPC::DIR_970:
211  case PPC::DIR_E5500:
212  case PPC::DIR_PWR4:
213  case PPC::DIR_PWR5:
214  case PPC::DIR_PWR5X:
215  case PPC::DIR_PWR6:
216  case PPC::DIR_PWR6X:
217  case PPC::DIR_PWR7:
218  case PPC::DIR_PWR8:
219  // FIXME: Is this needed for POWER9?
220  Latency += 2;
221  break;
222  }
223  }
224 
225  return Latency;
226 }
227 
228 // This function does not list all associative and commutative operations, but
229 // only those worth feeding through the machine combiner in an attempt to
230 // reduce the critical path. Mostly, this means floating-point operations,
231 // because they have high latencies (compared to other operations, such and
232 // and/or, which are also associative and commutative, but have low latencies).
234  switch (Inst.getOpcode()) {
235  // FP Add:
236  case PPC::FADD:
237  case PPC::FADDS:
238  // FP Multiply:
239  case PPC::FMUL:
240  case PPC::FMULS:
241  // Altivec Add:
242  case PPC::VADDFP:
243  // VSX Add:
244  case PPC::XSADDDP:
245  case PPC::XVADDDP:
246  case PPC::XVADDSP:
247  case PPC::XSADDSP:
248  // VSX Multiply:
249  case PPC::XSMULDP:
250  case PPC::XVMULDP:
251  case PPC::XVMULSP:
252  case PPC::XSMULSP:
253  // QPX Add:
254  case PPC::QVFADD:
255  case PPC::QVFADDS:
256  case PPC::QVFADDSs:
257  // QPX Multiply:
258  case PPC::QVFMUL:
259  case PPC::QVFMULS:
260  case PPC::QVFMULSs:
261  return true;
262  default:
263  return false;
264  }
265 }
266 
268  MachineInstr &Root,
269  SmallVectorImpl<MachineCombinerPattern> &Patterns) const {
270  // Using the machine combiner in this way is potentially expensive, so
271  // restrict to when aggressive optimizations are desired.
273  return false;
274 
275  // FP reassociation is only legal when we don't need strict IEEE semantics.
277  return false;
278 
279  return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns);
280 }
281 
282 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
284  unsigned &SrcReg, unsigned &DstReg,
285  unsigned &SubIdx) const {
286  switch (MI.getOpcode()) {
287  default: return false;
288  case PPC::EXTSW:
289  case PPC::EXTSW_32:
290  case PPC::EXTSW_32_64:
291  SrcReg = MI.getOperand(1).getReg();
292  DstReg = MI.getOperand(0).getReg();
293  SubIdx = PPC::sub_32;
294  return true;
295  }
296 }
297 
299  int &FrameIndex) const {
300  unsigned Opcode = MI.getOpcode();
301  const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
302  const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill;
303 
304  if (End != std::find(OpcodesForSpill, End, Opcode)) {
305  // Check for the operands added by addFrameReference (the immediate is the
306  // offset which defaults to 0).
307  if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
308  MI.getOperand(2).isFI()) {
309  FrameIndex = MI.getOperand(2).getIndex();
310  return MI.getOperand(0).getReg();
311  }
312  }
313  return 0;
314 }
315 
316 // For opcodes with the ReMaterializable flag set, this function is called to
317 // verify the instruction is really rematable.
319  AliasAnalysis *AA) const {
320  switch (MI.getOpcode()) {
321  default:
322  // This function should only be called for opcodes with the ReMaterializable
323  // flag set.
324  llvm_unreachable("Unknown rematerializable operation!");
325  break;
326  case PPC::LI:
327  case PPC::LI8:
328  case PPC::LIS:
329  case PPC::LIS8:
330  case PPC::QVGPCI:
331  case PPC::ADDIStocHA:
332  case PPC::ADDIStocHA8:
333  case PPC::ADDItocL:
334  case PPC::LOAD_STACK_GUARD:
335  case PPC::XXLXORz:
336  case PPC::XXLXORspz:
337  case PPC::XXLXORdpz:
338  case PPC::XXLEQVOnes:
339  case PPC::V_SET0B:
340  case PPC::V_SET0H:
341  case PPC::V_SET0:
342  case PPC::V_SETALLONESB:
343  case PPC::V_SETALLONESH:
344  case PPC::V_SETALLONES:
345  case PPC::CRSET:
346  case PPC::CRUNSET:
347  return true;
348  }
349  return false;
350 }
351 
353  int &FrameIndex) const {
354  unsigned Opcode = MI.getOpcode();
355  const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
356  const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill;
357 
358  if (End != std::find(OpcodesForSpill, End, Opcode)) {
359  if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
360  MI.getOperand(2).isFI()) {
361  FrameIndex = MI.getOperand(2).getIndex();
362  return MI.getOperand(0).getReg();
363  }
364  }
365  return 0;
366 }
367 
369  unsigned OpIdx1,
370  unsigned OpIdx2) const {
371  MachineFunction &MF = *MI.getParent()->getParent();
372 
373  // Normal instructions can be commuted the obvious way.
374  if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMIo)
375  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
376  // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
377  // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
378  // changing the relative order of the mask operands might change what happens
379  // to the high-bits of the mask (and, thus, the result).
380 
381  // Cannot commute if it has a non-zero rotate count.
382  if (MI.getOperand(3).getImm() != 0)
383  return nullptr;
384 
385  // If we have a zero rotate count, we have:
386  // M = mask(MB,ME)
387  // Op0 = (Op1 & ~M) | (Op2 & M)
388  // Change this to:
389  // M = mask((ME+1)&31, (MB-1)&31)
390  // Op0 = (Op2 & ~M) | (Op1 & M)
391 
392  // Swap op1/op2
393  assert(((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) &&
394  "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo.");
395  Register Reg0 = MI.getOperand(0).getReg();
396  Register Reg1 = MI.getOperand(1).getReg();
397  Register Reg2 = MI.getOperand(2).getReg();
398  unsigned SubReg1 = MI.getOperand(1).getSubReg();
399  unsigned SubReg2 = MI.getOperand(2).getSubReg();
400  bool Reg1IsKill = MI.getOperand(1).isKill();
401  bool Reg2IsKill = MI.getOperand(2).isKill();
402  bool ChangeReg0 = false;
403  // If machine instrs are no longer in two-address forms, update
404  // destination register as well.
405  if (Reg0 == Reg1) {
406  // Must be two address instruction!
408  "Expecting a two-address instruction!");
409  assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
410  Reg2IsKill = false;
411  ChangeReg0 = true;
412  }
413 
414  // Masks.
415  unsigned MB = MI.getOperand(4).getImm();
416  unsigned ME = MI.getOperand(5).getImm();
417 
418  // We can't commute a trivial mask (there is no way to represent an all-zero
419  // mask).
420  if (MB == 0 && ME == 31)
421  return nullptr;
422 
423  if (NewMI) {
424  // Create a new instruction.
425  Register Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg();
426  bool Reg0IsDead = MI.getOperand(0).isDead();
427  return BuildMI(MF, MI.getDebugLoc(), MI.getDesc())
428  .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
429  .addReg(Reg2, getKillRegState(Reg2IsKill))
430  .addReg(Reg1, getKillRegState(Reg1IsKill))
431  .addImm((ME + 1) & 31)
432  .addImm((MB - 1) & 31);
433  }
434 
435  if (ChangeReg0) {
436  MI.getOperand(0).setReg(Reg2);
437  MI.getOperand(0).setSubReg(SubReg2);
438  }
439  MI.getOperand(2).setReg(Reg1);
440  MI.getOperand(1).setReg(Reg2);
441  MI.getOperand(2).setSubReg(SubReg1);
442  MI.getOperand(1).setSubReg(SubReg2);
443  MI.getOperand(2).setIsKill(Reg1IsKill);
444  MI.getOperand(1).setIsKill(Reg2IsKill);
445 
446  // Swap the mask around.
447  MI.getOperand(4).setImm((ME + 1) & 31);
448  MI.getOperand(5).setImm((MB - 1) & 31);
449  return &MI;
450 }
451 
453  unsigned &SrcOpIdx1,
454  unsigned &SrcOpIdx2) const {
455  // For VSX A-Type FMA instructions, it is the first two operands that can be
456  // commuted, however, because the non-encoded tied input operand is listed
457  // first, the operands to swap are actually the second and third.
458 
459  int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode());
460  if (AltOpc == -1)
461  return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
462 
463  // The commutable operand indices are 2 and 3. Return them in SrcOpIdx1
464  // and SrcOpIdx2.
465  return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
466 }
467 
470  // This function is used for scheduling, and the nop wanted here is the type
471  // that terminates dispatch groups on the POWER cores.
472  unsigned Directive = Subtarget.getDarwinDirective();
473  unsigned Opcode;
474  switch (Directive) {
475  default: Opcode = PPC::NOP; break;
476  case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
477  case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
478  case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */
479  // FIXME: Update when POWER9 scheduling model is ready.
480  case PPC::DIR_PWR9: Opcode = PPC::NOP_GT_PWR7; break;
481  }
482 
483  DebugLoc DL;
484  BuildMI(MBB, MI, DL, get(Opcode));
485 }
486 
487 /// Return the noop instruction to use for a noop.
488 void PPCInstrInfo::getNoop(MCInst &NopInst) const {
489  NopInst.setOpcode(PPC::NOP);
490 }
491 
492 // Branch analysis.
493 // Note: If the condition register is set to CTR or CTR8 then this is a
494 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
496  MachineBasicBlock *&TBB,
497  MachineBasicBlock *&FBB,
499  bool AllowModify) const {
500  bool isPPC64 = Subtarget.isPPC64();
501 
502  // If the block has no terminators, it just falls into the block after it.
504  if (I == MBB.end())
505  return false;
506 
507  if (!isUnpredicatedTerminator(*I))
508  return false;
509 
510  if (AllowModify) {
511  // If the BB ends with an unconditional branch to the fallthrough BB,
512  // we eliminate the branch instruction.
513  if (I->getOpcode() == PPC::B &&
514  MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
515  I->eraseFromParent();
516 
517  // We update iterator after deleting the last branch.
518  I = MBB.getLastNonDebugInstr();
519  if (I == MBB.end() || !isUnpredicatedTerminator(*I))
520  return false;
521  }
522  }
523 
524  // Get the last instruction in the block.
525  MachineInstr &LastInst = *I;
526 
527  // If there is only one terminator instruction, process it.
528  if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
529  if (LastInst.getOpcode() == PPC::B) {
530  if (!LastInst.getOperand(0).isMBB())
531  return true;
532  TBB = LastInst.getOperand(0).getMBB();
533  return false;
534  } else if (LastInst.getOpcode() == PPC::BCC) {
535  if (!LastInst.getOperand(2).isMBB())
536  return true;
537  // Block ends with fall-through condbranch.
538  TBB = LastInst.getOperand(2).getMBB();
539  Cond.push_back(LastInst.getOperand(0));
540  Cond.push_back(LastInst.getOperand(1));
541  return false;
542  } else if (LastInst.getOpcode() == PPC::BC) {
543  if (!LastInst.getOperand(1).isMBB())
544  return true;
545  // Block ends with fall-through condbranch.
546  TBB = LastInst.getOperand(1).getMBB();
548  Cond.push_back(LastInst.getOperand(0));
549  return false;
550  } else if (LastInst.getOpcode() == PPC::BCn) {
551  if (!LastInst.getOperand(1).isMBB())
552  return true;
553  // Block ends with fall-through condbranch.
554  TBB = LastInst.getOperand(1).getMBB();
556  Cond.push_back(LastInst.getOperand(0));
557  return false;
558  } else if (LastInst.getOpcode() == PPC::BDNZ8 ||
559  LastInst.getOpcode() == PPC::BDNZ) {
560  if (!LastInst.getOperand(0).isMBB())
561  return true;
562  if (DisableCTRLoopAnal)
563  return true;
564  TBB = LastInst.getOperand(0).getMBB();
566  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
567  true));
568  return false;
569  } else if (LastInst.getOpcode() == PPC::BDZ8 ||
570  LastInst.getOpcode() == PPC::BDZ) {
571  if (!LastInst.getOperand(0).isMBB())
572  return true;
573  if (DisableCTRLoopAnal)
574  return true;
575  TBB = LastInst.getOperand(0).getMBB();
577  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
578  true));
579  return false;
580  }
581 
582  // Otherwise, don't know what this is.
583  return true;
584  }
585 
586  // Get the instruction before it if it's a terminator.
587  MachineInstr &SecondLastInst = *I;
588 
589  // If there are three terminators, we don't know what sort of block this is.
590  if (I != MBB.begin() && isUnpredicatedTerminator(*--I))
591  return true;
592 
593  // If the block ends with PPC::B and PPC:BCC, handle it.
594  if (SecondLastInst.getOpcode() == PPC::BCC &&
595  LastInst.getOpcode() == PPC::B) {
596  if (!SecondLastInst.getOperand(2).isMBB() ||
597  !LastInst.getOperand(0).isMBB())
598  return true;
599  TBB = SecondLastInst.getOperand(2).getMBB();
600  Cond.push_back(SecondLastInst.getOperand(0));
601  Cond.push_back(SecondLastInst.getOperand(1));
602  FBB = LastInst.getOperand(0).getMBB();
603  return false;
604  } else if (SecondLastInst.getOpcode() == PPC::BC &&
605  LastInst.getOpcode() == PPC::B) {
606  if (!SecondLastInst.getOperand(1).isMBB() ||
607  !LastInst.getOperand(0).isMBB())
608  return true;
609  TBB = SecondLastInst.getOperand(1).getMBB();
611  Cond.push_back(SecondLastInst.getOperand(0));
612  FBB = LastInst.getOperand(0).getMBB();
613  return false;
614  } else if (SecondLastInst.getOpcode() == PPC::BCn &&
615  LastInst.getOpcode() == PPC::B) {
616  if (!SecondLastInst.getOperand(1).isMBB() ||
617  !LastInst.getOperand(0).isMBB())
618  return true;
619  TBB = SecondLastInst.getOperand(1).getMBB();
621  Cond.push_back(SecondLastInst.getOperand(0));
622  FBB = LastInst.getOperand(0).getMBB();
623  return false;
624  } else if ((SecondLastInst.getOpcode() == PPC::BDNZ8 ||
625  SecondLastInst.getOpcode() == PPC::BDNZ) &&
626  LastInst.getOpcode() == PPC::B) {
627  if (!SecondLastInst.getOperand(0).isMBB() ||
628  !LastInst.getOperand(0).isMBB())
629  return true;
630  if (DisableCTRLoopAnal)
631  return true;
632  TBB = SecondLastInst.getOperand(0).getMBB();
634  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
635  true));
636  FBB = LastInst.getOperand(0).getMBB();
637  return false;
638  } else if ((SecondLastInst.getOpcode() == PPC::BDZ8 ||
639  SecondLastInst.getOpcode() == PPC::BDZ) &&
640  LastInst.getOpcode() == PPC::B) {
641  if (!SecondLastInst.getOperand(0).isMBB() ||
642  !LastInst.getOperand(0).isMBB())
643  return true;
644  if (DisableCTRLoopAnal)
645  return true;
646  TBB = SecondLastInst.getOperand(0).getMBB();
648  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
649  true));
650  FBB = LastInst.getOperand(0).getMBB();
651  return false;
652  }
653 
654  // If the block ends with two PPC:Bs, handle it. The second one is not
655  // executed, so remove it.
656  if (SecondLastInst.getOpcode() == PPC::B && LastInst.getOpcode() == PPC::B) {
657  if (!SecondLastInst.getOperand(0).isMBB())
658  return true;
659  TBB = SecondLastInst.getOperand(0).getMBB();
660  I = LastInst;
661  if (AllowModify)
662  I->eraseFromParent();
663  return false;
664  }
665 
666  // Otherwise, can't handle this.
667  return true;
668 }
669 
671  int *BytesRemoved) const {
672  assert(!BytesRemoved && "code size not handled");
673 
675  if (I == MBB.end())
676  return 0;
677 
678  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
679  I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
680  I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
681  I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
682  return 0;
683 
684  // Remove the branch.
685  I->eraseFromParent();
686 
687  I = MBB.end();
688 
689  if (I == MBB.begin()) return 1;
690  --I;
691  if (I->getOpcode() != PPC::BCC &&
692  I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
693  I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
694  I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
695  return 1;
696 
697  // Remove the branch.
698  I->eraseFromParent();
699  return 2;
700 }
701 
703  MachineBasicBlock *TBB,
704  MachineBasicBlock *FBB,
706  const DebugLoc &DL,
707  int *BytesAdded) const {
708  // Shouldn't be a fall through.
709  assert(TBB && "insertBranch must not be told to insert a fallthrough");
710  assert((Cond.size() == 2 || Cond.size() == 0) &&
711  "PPC branch conditions have two components!");
712  assert(!BytesAdded && "code size not handled");
713 
714  bool isPPC64 = Subtarget.isPPC64();
715 
716  // One-way branch.
717  if (!FBB) {
718  if (Cond.empty()) // Unconditional branch
719  BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
720  else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
721  BuildMI(&MBB, DL, get(Cond[0].getImm() ?
722  (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
723  (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
724  else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
725  BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
726  else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
727  BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
728  else // Conditional branch
729  BuildMI(&MBB, DL, get(PPC::BCC))
730  .addImm(Cond[0].getImm())
731  .add(Cond[1])
732  .addMBB(TBB);
733  return 1;
734  }
735 
736  // Two-way Conditional Branch.
737  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
738  BuildMI(&MBB, DL, get(Cond[0].getImm() ?
739  (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
740  (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
741  else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
742  BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
743  else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
744  BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
745  else
746  BuildMI(&MBB, DL, get(PPC::BCC))
747  .addImm(Cond[0].getImm())
748  .add(Cond[1])
749  .addMBB(TBB);
750  BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
751  return 2;
752 }
753 
754 // Select analysis.
757  unsigned TrueReg, unsigned FalseReg,
758  int &CondCycles, int &TrueCycles, int &FalseCycles) const {
759  if (Cond.size() != 2)
760  return false;
761 
762  // If this is really a bdnz-like condition, then it cannot be turned into a
763  // select.
764  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
765  return false;
766 
767  // Check register classes.
768  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
769  const TargetRegisterClass *RC =
770  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
771  if (!RC)
772  return false;
773 
774  // isel is for regular integer GPRs only.
775  if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
776  !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
777  !PPC::G8RCRegClass.hasSubClassEq(RC) &&
778  !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
779  return false;
780 
781  // FIXME: These numbers are for the A2, how well they work for other cores is
782  // an open question. On the A2, the isel instruction has a 2-cycle latency
783  // but single-cycle throughput. These numbers are used in combination with
784  // the MispredictPenalty setting from the active SchedMachineModel.
785  CondCycles = 1;
786  TrueCycles = 1;
787  FalseCycles = 1;
788 
789  return true;
790 }
791 
794  const DebugLoc &dl, unsigned DestReg,
795  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
796  unsigned FalseReg) const {
797  assert(Cond.size() == 2 &&
798  "PPC branch conditions have two components!");
799 
800  // Get the register classes.
802  const TargetRegisterClass *RC =
803  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
804  assert(RC && "TrueReg and FalseReg must have overlapping register classes");
805 
806  bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
807  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
808  assert((Is64Bit ||
809  PPC::GPRCRegClass.hasSubClassEq(RC) ||
810  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
811  "isel is for regular integer GPRs only");
812 
813  unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
814  auto SelectPred = static_cast<PPC::Predicate>(Cond[0].getImm());
815 
816  unsigned SubIdx = 0;
817  bool SwapOps = false;
818  switch (SelectPred) {
819  case PPC::PRED_EQ:
820  case PPC::PRED_EQ_MINUS:
821  case PPC::PRED_EQ_PLUS:
822  SubIdx = PPC::sub_eq; SwapOps = false; break;
823  case PPC::PRED_NE:
824  case PPC::PRED_NE_MINUS:
825  case PPC::PRED_NE_PLUS:
826  SubIdx = PPC::sub_eq; SwapOps = true; break;
827  case PPC::PRED_LT:
828  case PPC::PRED_LT_MINUS:
829  case PPC::PRED_LT_PLUS:
830  SubIdx = PPC::sub_lt; SwapOps = false; break;
831  case PPC::PRED_GE:
832  case PPC::PRED_GE_MINUS:
833  case PPC::PRED_GE_PLUS:
834  SubIdx = PPC::sub_lt; SwapOps = true; break;
835  case PPC::PRED_GT:
836  case PPC::PRED_GT_MINUS:
837  case PPC::PRED_GT_PLUS:
838  SubIdx = PPC::sub_gt; SwapOps = false; break;
839  case PPC::PRED_LE:
840  case PPC::PRED_LE_MINUS:
841  case PPC::PRED_LE_PLUS:
842  SubIdx = PPC::sub_gt; SwapOps = true; break;
843  case PPC::PRED_UN:
844  case PPC::PRED_UN_MINUS:
845  case PPC::PRED_UN_PLUS:
846  SubIdx = PPC::sub_un; SwapOps = false; break;
847  case PPC::PRED_NU:
848  case PPC::PRED_NU_MINUS:
849  case PPC::PRED_NU_PLUS:
850  SubIdx = PPC::sub_un; SwapOps = true; break;
851  case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break;
852  case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break;
853  }
854 
855  unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
856  SecondReg = SwapOps ? TrueReg : FalseReg;
857 
858  // The first input register of isel cannot be r0. If it is a member
859  // of a register class that can be r0, then copy it first (the
860  // register allocator should eliminate the copy).
861  if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
862  MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
863  const TargetRegisterClass *FirstRC =
864  MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
865  &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
866  unsigned OldFirstReg = FirstReg;
867  FirstReg = MRI.createVirtualRegister(FirstRC);
868  BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
869  .addReg(OldFirstReg);
870  }
871 
872  BuildMI(MBB, MI, dl, get(OpCode), DestReg)
873  .addReg(FirstReg).addReg(SecondReg)
874  .addReg(Cond[1].getReg(), 0, SubIdx);
875 }
876 
877 static unsigned getCRBitValue(unsigned CRBit) {
878  unsigned Ret = 4;
879  if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT ||
880  CRBit == PPC::CR2LT || CRBit == PPC::CR3LT ||
881  CRBit == PPC::CR4LT || CRBit == PPC::CR5LT ||
882  CRBit == PPC::CR6LT || CRBit == PPC::CR7LT)
883  Ret = 3;
884  if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT ||
885  CRBit == PPC::CR2GT || CRBit == PPC::CR3GT ||
886  CRBit == PPC::CR4GT || CRBit == PPC::CR5GT ||
887  CRBit == PPC::CR6GT || CRBit == PPC::CR7GT)
888  Ret = 2;
889  if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ ||
890  CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ ||
891  CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ ||
892  CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ)
893  Ret = 1;
894  if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN ||
895  CRBit == PPC::CR2UN || CRBit == PPC::CR3UN ||
896  CRBit == PPC::CR4UN || CRBit == PPC::CR5UN ||
897  CRBit == PPC::CR6UN || CRBit == PPC::CR7UN)
898  Ret = 0;
899 
900  assert(Ret != 4 && "Invalid CR bit register");
901  return Ret;
902 }
903 
906  const DebugLoc &DL, unsigned DestReg,
907  unsigned SrcReg, bool KillSrc) const {
908  // We can end up with self copies and similar things as a result of VSX copy
909  // legalization. Promote them here.
911  if (PPC::F8RCRegClass.contains(DestReg) &&
912  PPC::VSRCRegClass.contains(SrcReg)) {
913  unsigned SuperReg =
914  TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
915 
916  if (VSXSelfCopyCrash && SrcReg == SuperReg)
917  llvm_unreachable("nop VSX copy");
918 
919  DestReg = SuperReg;
920  } else if (PPC::F8RCRegClass.contains(SrcReg) &&
921  PPC::VSRCRegClass.contains(DestReg)) {
922  unsigned SuperReg =
923  TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
924 
925  if (VSXSelfCopyCrash && DestReg == SuperReg)
926  llvm_unreachable("nop VSX copy");
927 
928  SrcReg = SuperReg;
929  }
930 
931  // Different class register copy
932  if (PPC::CRBITRCRegClass.contains(SrcReg) &&
933  PPC::GPRCRegClass.contains(DestReg)) {
934  unsigned CRReg = getCRFromCRBit(SrcReg);
935  BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg);
936  getKillRegState(KillSrc);
937  // Rotate the CR bit in the CR fields to be the least significant bit and
938  // then mask with 0x1 (MB = ME = 31).
939  BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
940  .addReg(DestReg, RegState::Kill)
941  .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
942  .addImm(31)
943  .addImm(31);
944  return;
945  } else if (PPC::CRRCRegClass.contains(SrcReg) &&
946  PPC::G8RCRegClass.contains(DestReg)) {
947  BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg).addReg(SrcReg);
948  getKillRegState(KillSrc);
949  return;
950  } else if (PPC::CRRCRegClass.contains(SrcReg) &&
951  PPC::GPRCRegClass.contains(DestReg)) {
952  BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(SrcReg);
953  getKillRegState(KillSrc);
954  return;
955  } else if (PPC::G8RCRegClass.contains(SrcReg) &&
956  PPC::VSFRCRegClass.contains(DestReg)) {
957  assert(Subtarget.hasDirectMove() &&
958  "Subtarget doesn't support directmove, don't know how to copy.");
959  BuildMI(MBB, I, DL, get(PPC::MTVSRD), DestReg).addReg(SrcReg);
960  NumGPRtoVSRSpill++;
961  getKillRegState(KillSrc);
962  return;
963  } else if (PPC::VSFRCRegClass.contains(SrcReg) &&
964  PPC::G8RCRegClass.contains(DestReg)) {
965  assert(Subtarget.hasDirectMove() &&
966  "Subtarget doesn't support directmove, don't know how to copy.");
967  BuildMI(MBB, I, DL, get(PPC::MFVSRD), DestReg).addReg(SrcReg);
968  getKillRegState(KillSrc);
969  return;
970  } else if (PPC::SPERCRegClass.contains(SrcReg) &&
971  PPC::GPRCRegClass.contains(DestReg)) {
972  BuildMI(MBB, I, DL, get(PPC::EFSCFD), DestReg).addReg(SrcReg);
973  getKillRegState(KillSrc);
974  return;
975  } else if (PPC::GPRCRegClass.contains(SrcReg) &&
976  PPC::SPERCRegClass.contains(DestReg)) {
977  BuildMI(MBB, I, DL, get(PPC::EFDCFS), DestReg).addReg(SrcReg);
978  getKillRegState(KillSrc);
979  return;
980  }
981 
982  unsigned Opc;
983  if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
984  Opc = PPC::OR;
985  else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
986  Opc = PPC::OR8;
987  else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
988  Opc = PPC::FMR;
989  else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
990  Opc = PPC::MCRF;
991  else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
992  Opc = PPC::VOR;
993  else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
994  // There are two different ways this can be done:
995  // 1. xxlor : This has lower latency (on the P7), 2 cycles, but can only
996  // issue in VSU pipeline 0.
997  // 2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
998  // can go to either pipeline.
999  // We'll always use xxlor here, because in practically all cases where
1000  // copies are generated, they are close enough to some use that the
1001  // lower-latency form is preferable.
1002  Opc = PPC::XXLOR;
1003  else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) ||
1004  PPC::VSSRCRegClass.contains(DestReg, SrcReg))
1005  Opc = (Subtarget.hasP9Vector()) ? PPC::XSCPSGNDP : PPC::XXLORf;
1006  else if (PPC::QFRCRegClass.contains(DestReg, SrcReg))
1007  Opc = PPC::QVFMR;
1008  else if (PPC::QSRCRegClass.contains(DestReg, SrcReg))
1009  Opc = PPC::QVFMRs;
1010  else if (PPC::QBRCRegClass.contains(DestReg, SrcReg))
1011  Opc = PPC::QVFMRb;
1012  else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
1013  Opc = PPC::CROR;
1014  else if (PPC::SPERCRegClass.contains(DestReg, SrcReg))
1015  Opc = PPC::EVOR;
1016  else
1017  llvm_unreachable("Impossible reg-to-reg copy");
1018 
1019  const MCInstrDesc &MCID = get(Opc);
1020  if (MCID.getNumOperands() == 3)
1021  BuildMI(MBB, I, DL, MCID, DestReg)
1022  .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
1023  else
1024  BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
1025 }
1026 
1028  const TargetRegisterClass *RC)
1029  const {
1030  const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
1031  int OpcodeIndex = 0;
1032 
1033  if (RC != nullptr) {
1034  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1035  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1036  OpcodeIndex = SOK_Int4Spill;
1037  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1038  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1039  OpcodeIndex = SOK_Int8Spill;
1040  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1041  OpcodeIndex = SOK_Float8Spill;
1042  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1043  OpcodeIndex = SOK_Float4Spill;
1044  } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1045  OpcodeIndex = SOK_SPESpill;
1046  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1047  OpcodeIndex = SOK_CRSpill;
1048  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1049  OpcodeIndex = SOK_CRBitSpill;
1050  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1051  OpcodeIndex = SOK_VRVectorSpill;
1052  } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1053  OpcodeIndex = SOK_VSXVectorSpill;
1054  } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1055  OpcodeIndex = SOK_VectorFloat8Spill;
1056  } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1057  OpcodeIndex = SOK_VectorFloat4Spill;
1058  } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1059  OpcodeIndex = SOK_VRSaveSpill;
1060  } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1061  OpcodeIndex = SOK_QuadFloat8Spill;
1062  } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1063  OpcodeIndex = SOK_QuadFloat4Spill;
1064  } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1065  OpcodeIndex = SOK_QuadBitSpill;
1066  } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1067  OpcodeIndex = SOK_SpillToVSR;
1068  } else {
1069  llvm_unreachable("Unknown regclass!");
1070  }
1071  } else {
1072  if (PPC::GPRCRegClass.contains(Reg) ||
1073  PPC::GPRC_NOR0RegClass.contains(Reg)) {
1074  OpcodeIndex = SOK_Int4Spill;
1075  } else if (PPC::G8RCRegClass.contains(Reg) ||
1076  PPC::G8RC_NOX0RegClass.contains(Reg)) {
1077  OpcodeIndex = SOK_Int8Spill;
1078  } else if (PPC::F8RCRegClass.contains(Reg)) {
1079  OpcodeIndex = SOK_Float8Spill;
1080  } else if (PPC::F4RCRegClass.contains(Reg)) {
1081  OpcodeIndex = SOK_Float4Spill;
1082  } else if (PPC::SPERCRegClass.contains(Reg)) {
1083  OpcodeIndex = SOK_SPESpill;
1084  } else if (PPC::CRRCRegClass.contains(Reg)) {
1085  OpcodeIndex = SOK_CRSpill;
1086  } else if (PPC::CRBITRCRegClass.contains(Reg)) {
1087  OpcodeIndex = SOK_CRBitSpill;
1088  } else if (PPC::VRRCRegClass.contains(Reg)) {
1089  OpcodeIndex = SOK_VRVectorSpill;
1090  } else if (PPC::VSRCRegClass.contains(Reg)) {
1091  OpcodeIndex = SOK_VSXVectorSpill;
1092  } else if (PPC::VSFRCRegClass.contains(Reg)) {
1093  OpcodeIndex = SOK_VectorFloat8Spill;
1094  } else if (PPC::VSSRCRegClass.contains(Reg)) {
1095  OpcodeIndex = SOK_VectorFloat4Spill;
1096  } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1097  OpcodeIndex = SOK_VRSaveSpill;
1098  } else if (PPC::QFRCRegClass.contains(Reg)) {
1099  OpcodeIndex = SOK_QuadFloat8Spill;
1100  } else if (PPC::QSRCRegClass.contains(Reg)) {
1101  OpcodeIndex = SOK_QuadFloat4Spill;
1102  } else if (PPC::QBRCRegClass.contains(Reg)) {
1103  OpcodeIndex = SOK_QuadBitSpill;
1104  } else if (PPC::SPILLTOVSRRCRegClass.contains(Reg)) {
1105  OpcodeIndex = SOK_SpillToVSR;
1106  } else {
1107  llvm_unreachable("Unknown regclass!");
1108  }
1109  }
1110  return OpcodesForSpill[OpcodeIndex];
1111 }
1112 
1113 unsigned
1115  const TargetRegisterClass *RC) const {
1116  const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
1117  int OpcodeIndex = 0;
1118 
1119  if (RC != nullptr) {
1120  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1121  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1122  OpcodeIndex = SOK_Int4Spill;
1123  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1124  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1125  OpcodeIndex = SOK_Int8Spill;
1126  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1127  OpcodeIndex = SOK_Float8Spill;
1128  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1129  OpcodeIndex = SOK_Float4Spill;
1130  } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1131  OpcodeIndex = SOK_SPESpill;
1132  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1133  OpcodeIndex = SOK_CRSpill;
1134  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1135  OpcodeIndex = SOK_CRBitSpill;
1136  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1137  OpcodeIndex = SOK_VRVectorSpill;
1138  } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1139  OpcodeIndex = SOK_VSXVectorSpill;
1140  } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1141  OpcodeIndex = SOK_VectorFloat8Spill;
1142  } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1143  OpcodeIndex = SOK_VectorFloat4Spill;
1144  } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1145  OpcodeIndex = SOK_VRSaveSpill;
1146  } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1147  OpcodeIndex = SOK_QuadFloat8Spill;
1148  } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1149  OpcodeIndex = SOK_QuadFloat4Spill;
1150  } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1151  OpcodeIndex = SOK_QuadBitSpill;
1152  } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1153  OpcodeIndex = SOK_SpillToVSR;
1154  } else {
1155  llvm_unreachable("Unknown regclass!");
1156  }
1157  } else {
1158  if (PPC::GPRCRegClass.contains(Reg) ||
1159  PPC::GPRC_NOR0RegClass.contains(Reg)) {
1160  OpcodeIndex = SOK_Int4Spill;
1161  } else if (PPC::G8RCRegClass.contains(Reg) ||
1162  PPC::G8RC_NOX0RegClass.contains(Reg)) {
1163  OpcodeIndex = SOK_Int8Spill;
1164  } else if (PPC::F8RCRegClass.contains(Reg)) {
1165  OpcodeIndex = SOK_Float8Spill;
1166  } else if (PPC::F4RCRegClass.contains(Reg)) {
1167  OpcodeIndex = SOK_Float4Spill;
1168  } else if (PPC::SPERCRegClass.contains(Reg)) {
1169  OpcodeIndex = SOK_SPESpill;
1170  } else if (PPC::CRRCRegClass.contains(Reg)) {
1171  OpcodeIndex = SOK_CRSpill;
1172  } else if (PPC::CRBITRCRegClass.contains(Reg)) {
1173  OpcodeIndex = SOK_CRBitSpill;
1174  } else if (PPC::VRRCRegClass.contains(Reg)) {
1175  OpcodeIndex = SOK_VRVectorSpill;
1176  } else if (PPC::VSRCRegClass.contains(Reg)) {
1177  OpcodeIndex = SOK_VSXVectorSpill;
1178  } else if (PPC::VSFRCRegClass.contains(Reg)) {
1179  OpcodeIndex = SOK_VectorFloat8Spill;
1180  } else if (PPC::VSSRCRegClass.contains(Reg)) {
1181  OpcodeIndex = SOK_VectorFloat4Spill;
1182  } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1183  OpcodeIndex = SOK_VRSaveSpill;
1184  } else if (PPC::QFRCRegClass.contains(Reg)) {
1185  OpcodeIndex = SOK_QuadFloat8Spill;
1186  } else if (PPC::QSRCRegClass.contains(Reg)) {
1187  OpcodeIndex = SOK_QuadFloat4Spill;
1188  } else if (PPC::QBRCRegClass.contains(Reg)) {
1189  OpcodeIndex = SOK_QuadBitSpill;
1190  } else if (PPC::SPILLTOVSRRCRegClass.contains(Reg)) {
1191  OpcodeIndex = SOK_SpillToVSR;
1192  } else {
1193  llvm_unreachable("Unknown regclass!");
1194  }
1195  }
1196  return OpcodesForSpill[OpcodeIndex];
1197 }
1198 
1199 void PPCInstrInfo::StoreRegToStackSlot(
1200  MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx,
1201  const TargetRegisterClass *RC,
1202  SmallVectorImpl<MachineInstr *> &NewMIs) const {
1203  unsigned Opcode = getStoreOpcodeForSpill(PPC::NoRegister, RC);
1204  DebugLoc DL;
1205 
1206  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1207  FuncInfo->setHasSpills();
1208 
1210  BuildMI(MF, DL, get(Opcode)).addReg(SrcReg, getKillRegState(isKill)),
1211  FrameIdx));
1212 
1213  if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1214  PPC::CRBITRCRegClass.hasSubClassEq(RC))
1215  FuncInfo->setSpillsCR();
1216 
1217  if (PPC::VRSAVERCRegClass.hasSubClassEq(RC))
1218  FuncInfo->setSpillsVRSAVE();
1219 
1220  if (isXFormMemOp(Opcode))
1221  FuncInfo->setHasNonRISpills();
1222 }
1223 
1226  unsigned SrcReg, bool isKill,
1227  int FrameIdx,
1228  const TargetRegisterClass *RC,
1229  const TargetRegisterInfo *TRI) const {
1230  MachineFunction &MF = *MBB.getParent();
1232 
1233  // We need to avoid a situation in which the value from a VRRC register is
1234  // spilled using an Altivec instruction and reloaded into a VSRC register
1235  // using a VSX instruction. The issue with this is that the VSX
1236  // load/store instructions swap the doublewords in the vector and the Altivec
1237  // ones don't. The register classes on the spill/reload may be different if
1238  // the register is defined using an Altivec instruction and is then used by a
1239  // VSX instruction.
1240  RC = updatedRC(RC);
1241 
1242  StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs);
1243 
1244  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1245  MBB.insert(MI, NewMIs[i]);
1246 
1247  const MachineFrameInfo &MFI = MF.getFrameInfo();
1249  MachinePointerInfo::getFixedStack(MF, FrameIdx),
1251  MFI.getObjectAlignment(FrameIdx));
1252  NewMIs.back()->addMemOperand(MF, MMO);
1253 }
1254 
1255 void PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
1256  unsigned DestReg, int FrameIdx,
1257  const TargetRegisterClass *RC,
1259  const {
1260  unsigned Opcode = getLoadOpcodeForSpill(PPC::NoRegister, RC);
1261  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opcode), DestReg),
1262  FrameIdx));
1263  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1264 
1265  if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1266  PPC::CRBITRCRegClass.hasSubClassEq(RC))
1267  FuncInfo->setSpillsCR();
1268 
1269  if (PPC::VRSAVERCRegClass.hasSubClassEq(RC))
1270  FuncInfo->setSpillsVRSAVE();
1271 
1272  if (isXFormMemOp(Opcode))
1273  FuncInfo->setHasNonRISpills();
1274 }
1275 
1276 void
1279  unsigned DestReg, int FrameIdx,
1280  const TargetRegisterClass *RC,
1281  const TargetRegisterInfo *TRI) const {
1282  MachineFunction &MF = *MBB.getParent();
1284  DebugLoc DL;
1285  if (MI != MBB.end()) DL = MI->getDebugLoc();
1286 
1287  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1288  FuncInfo->setHasSpills();
1289 
1290  // We need to avoid a situation in which the value from a VRRC register is
1291  // spilled using an Altivec instruction and reloaded into a VSRC register
1292  // using a VSX instruction. The issue with this is that the VSX
1293  // load/store instructions swap the doublewords in the vector and the Altivec
1294  // ones don't. The register classes on the spill/reload may be different if
1295  // the register is defined using an Altivec instruction and is then used by a
1296  // VSX instruction.
1297  if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
1298  RC = &PPC::VSRCRegClass;
1299 
1300  LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
1301 
1302  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1303  MBB.insert(MI, NewMIs[i]);
1304 
1305  const MachineFrameInfo &MFI = MF.getFrameInfo();
1307  MachinePointerInfo::getFixedStack(MF, FrameIdx),
1309  MFI.getObjectAlignment(FrameIdx));
1310  NewMIs.back()->addMemOperand(MF, MMO);
1311 }
1312 
1313 bool PPCInstrInfo::
1315  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
1316  if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
1317  Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
1318  else
1319  // Leave the CR# the same, but invert the condition.
1320  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
1321  return false;
1322 }
1323 
1325  unsigned Reg, MachineRegisterInfo *MRI) const {
1326  // For some instructions, it is legal to fold ZERO into the RA register field.
1327  // A zero immediate should always be loaded with a single li.
1328  unsigned DefOpc = DefMI.getOpcode();
1329  if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
1330  return false;
1331  if (!DefMI.getOperand(1).isImm())
1332  return false;
1333  if (DefMI.getOperand(1).getImm() != 0)
1334  return false;
1335 
1336  // Note that we cannot here invert the arguments of an isel in order to fold
1337  // a ZERO into what is presented as the second argument. All we have here
1338  // is the condition bit, and that might come from a CR-logical bit operation.
1339 
1340  const MCInstrDesc &UseMCID = UseMI.getDesc();
1341 
1342  // Only fold into real machine instructions.
1343  if (UseMCID.isPseudo())
1344  return false;
1345 
1346  unsigned UseIdx;
1347  for (UseIdx = 0; UseIdx < UseMI.getNumOperands(); ++UseIdx)
1348  if (UseMI.getOperand(UseIdx).isReg() &&
1349  UseMI.getOperand(UseIdx).getReg() == Reg)
1350  break;
1351 
1352  assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI");
1353  assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
1354 
1355  const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
1356 
1357  // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
1358  // register (which might also be specified as a pointer class kind).
1359  if (UseInfo->isLookupPtrRegClass()) {
1360  if (UseInfo->RegClass /* Kind */ != 1)
1361  return false;
1362  } else {
1363  if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
1364  UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
1365  return false;
1366  }
1367 
1368  // Make sure this is not tied to an output register (or otherwise
1369  // constrained). This is true for ST?UX registers, for example, which
1370  // are tied to their output registers.
1371  if (UseInfo->Constraints != 0)
1372  return false;
1373 
1374  unsigned ZeroReg;
1375  if (UseInfo->isLookupPtrRegClass()) {
1376  bool isPPC64 = Subtarget.isPPC64();
1377  ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
1378  } else {
1379  ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
1380  PPC::ZERO8 : PPC::ZERO;
1381  }
1382 
1383  bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1384  UseMI.getOperand(UseIdx).setReg(ZeroReg);
1385 
1386  if (DeleteDef)
1387  DefMI.eraseFromParent();
1388 
1389  return true;
1390 }
1391 
1393  for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
1394  I != IE; ++I)
1395  if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
1396  return true;
1397  return false;
1398 }
1399 
1400 // We should make sure that, if we're going to predicate both sides of a
1401 // condition (a diamond), that both sides don't define the counter register. We
1402 // can predicate counter-decrement-based branches, but while that predicates
1403 // the branching, it does not predicate the counter decrement. If we tried to
1404 // merge the triangle into one predicated block, we'd decrement the counter
1405 // twice.
1407  unsigned NumT, unsigned ExtraT,
1408  MachineBasicBlock &FMBB,
1409  unsigned NumF, unsigned ExtraF,
1410  BranchProbability Probability) const {
1411  return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
1412 }
1413 
1414 
1416  // The predicated branches are identified by their type, not really by the
1417  // explicit presence of a predicate. Furthermore, some of them can be
1418  // predicated more than once. Because if conversion won't try to predicate
1419  // any instruction which already claims to be predicated (by returning true
1420  // here), always return false. In doing so, we let isPredicable() be the
1421  // final word on whether not the instruction can be (further) predicated.
1422 
1423  return false;
1424 }
1425 
1427  if (!MI.isTerminator())
1428  return false;
1429 
1430  // Conditional branch is a special case.
1431  if (MI.isBranch() && !MI.isBarrier())
1432  return true;
1433 
1434  return !isPredicated(MI);
1435 }
1436 
1438  ArrayRef<MachineOperand> Pred) const {
1439  unsigned OpC = MI.getOpcode();
1440  if (OpC == PPC::BLR || OpC == PPC::BLR8) {
1441  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1442  bool isPPC64 = Subtarget.isPPC64();
1443  MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR)
1444  : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
1445  } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1446  MI.setDesc(get(PPC::BCLR));
1447  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1448  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1449  MI.setDesc(get(PPC::BCLRn));
1450  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1451  } else {
1452  MI.setDesc(get(PPC::BCCLR));
1454  .addImm(Pred[0].getImm())
1455  .add(Pred[1]);
1456  }
1457 
1458  return true;
1459  } else if (OpC == PPC::B) {
1460  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1461  bool isPPC64 = Subtarget.isPPC64();
1462  MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
1463  : (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
1464  } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1465  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1466  MI.RemoveOperand(0);
1467 
1468  MI.setDesc(get(PPC::BC));
1470  .add(Pred[1])
1471  .addMBB(MBB);
1472  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1473  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1474  MI.RemoveOperand(0);
1475 
1476  MI.setDesc(get(PPC::BCn));
1478  .add(Pred[1])
1479  .addMBB(MBB);
1480  } else {
1481  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1482  MI.RemoveOperand(0);
1483 
1484  MI.setDesc(get(PPC::BCC));
1486  .addImm(Pred[0].getImm())
1487  .add(Pred[1])
1488  .addMBB(MBB);
1489  }
1490 
1491  return true;
1492  } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 || OpC == PPC::BCTRL ||
1493  OpC == PPC::BCTRL8) {
1494  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
1495  llvm_unreachable("Cannot predicate bctr[l] on the ctr register");
1496 
1497  bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
1498  bool isPPC64 = Subtarget.isPPC64();
1499 
1500  if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1501  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8)
1502  : (setLR ? PPC::BCCTRL : PPC::BCCTR)));
1503  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1504  return true;
1505  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1506  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n)
1507  : (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
1508  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1509  return true;
1510  }
1511 
1512  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8)
1513  : (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
1515  .addImm(Pred[0].getImm())
1516  .add(Pred[1]);
1517  return true;
1518  }
1519 
1520  return false;
1521 }
1522 
1524  ArrayRef<MachineOperand> Pred2) const {
1525  assert(Pred1.size() == 2 && "Invalid PPC first predicate");
1526  assert(Pred2.size() == 2 && "Invalid PPC second predicate");
1527 
1528  if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1529  return false;
1530  if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
1531  return false;
1532 
1533  // P1 can only subsume P2 if they test the same condition register.
1534  if (Pred1[1].getReg() != Pred2[1].getReg())
1535  return false;
1536 
1537  PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
1538  PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
1539 
1540  if (P1 == P2)
1541  return true;
1542 
1543  // Does P1 subsume P2, e.g. GE subsumes GT.
1544  if (P1 == PPC::PRED_LE &&
1545  (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
1546  return true;
1547  if (P1 == PPC::PRED_GE &&
1548  (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
1549  return true;
1550 
1551  return false;
1552 }
1553 
1555  std::vector<MachineOperand> &Pred) const {
1556  // Note: At the present time, the contents of Pred from this function is
1557  // unused by IfConversion. This implementation follows ARM by pushing the
1558  // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
1559  // predicate, instructions defining CTR or CTR8 are also included as
1560  // predicate-defining instructions.
1561 
1562  const TargetRegisterClass *RCs[] =
1563  { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1564  &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1565 
1566  bool Found = false;
1567  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1568  const MachineOperand &MO = MI.getOperand(i);
1569  for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
1570  const TargetRegisterClass *RC = RCs[c];
1571  if (MO.isReg()) {
1572  if (MO.isDef() && RC->contains(MO.getReg())) {
1573  Pred.push_back(MO);
1574  Found = true;
1575  }
1576  } else if (MO.isRegMask()) {
1577  for (TargetRegisterClass::iterator I = RC->begin(),
1578  IE = RC->end(); I != IE; ++I)
1579  if (MO.clobbersPhysReg(*I)) {
1580  Pred.push_back(MO);
1581  Found = true;
1582  }
1583  }
1584  }
1585  }
1586 
1587  return Found;
1588 }
1589 
1591  unsigned OpC = MI.getOpcode();
1592  switch (OpC) {
1593  default:
1594  return false;
1595  case PPC::B:
1596  case PPC::BLR:
1597  case PPC::BLR8:
1598  case PPC::BCTR:
1599  case PPC::BCTR8:
1600  case PPC::BCTRL:
1601  case PPC::BCTRL8:
1602  return true;
1603  }
1604 }
1605 
1606 bool PPCInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1607  unsigned &SrcReg2, int &Mask,
1608  int &Value) const {
1609  unsigned Opc = MI.getOpcode();
1610 
1611  switch (Opc) {
1612  default: return false;
1613  case PPC::CMPWI:
1614  case PPC::CMPLWI:
1615  case PPC::CMPDI:
1616  case PPC::CMPLDI:
1617  SrcReg = MI.getOperand(1).getReg();
1618  SrcReg2 = 0;
1619  Value = MI.getOperand(2).getImm();
1620  Mask = 0xFFFF;
1621  return true;
1622  case PPC::CMPW:
1623  case PPC::CMPLW:
1624  case PPC::CMPD:
1625  case PPC::CMPLD:
1626  case PPC::FCMPUS:
1627  case PPC::FCMPUD:
1628  SrcReg = MI.getOperand(1).getReg();
1629  SrcReg2 = MI.getOperand(2).getReg();
1630  Value = 0;
1631  Mask = 0;
1632  return true;
1633  }
1634 }
1635 
1636 bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1637  unsigned SrcReg2, int Mask, int Value,
1638  const MachineRegisterInfo *MRI) const {
1639  if (DisableCmpOpt)
1640  return false;
1641 
1642  int OpC = CmpInstr.getOpcode();
1643  Register CRReg = CmpInstr.getOperand(0).getReg();
1644 
1645  // FP record forms set CR1 based on the exception status bits, not a
1646  // comparison with zero.
1647  if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
1648  return false;
1649 
1651  // The record forms set the condition register based on a signed comparison
1652  // with zero (so says the ISA manual). This is not as straightforward as it
1653  // seems, however, because this is always a 64-bit comparison on PPC64, even
1654  // for instructions that are 32-bit in nature (like slw for example).
1655  // So, on PPC32, for unsigned comparisons, we can use the record forms only
1656  // for equality checks (as those don't depend on the sign). On PPC64,
1657  // we are restricted to equality for unsigned 64-bit comparisons and for
1658  // signed 32-bit comparisons the applicability is more restricted.
1659  bool isPPC64 = Subtarget.isPPC64();
1660  bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
1661  bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
1662  bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
1663 
1664  // Look through copies unless that gets us to a physical register.
1665  unsigned ActualSrc = TRI->lookThruCopyLike(SrcReg, MRI);
1666  if (Register::isVirtualRegister(ActualSrc))
1667  SrcReg = ActualSrc;
1668 
1669  // Get the unique definition of SrcReg.
1670  MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1671  if (!MI) return false;
1672 
1673  bool equalityOnly = false;
1674  bool noSub = false;
1675  if (isPPC64) {
1676  if (is32BitSignedCompare) {
1677  // We can perform this optimization only if MI is sign-extending.
1678  if (isSignExtended(*MI))
1679  noSub = true;
1680  else
1681  return false;
1682  } else if (is32BitUnsignedCompare) {
1683  // We can perform this optimization, equality only, if MI is
1684  // zero-extending.
1685  if (isZeroExtended(*MI)) {
1686  noSub = true;
1687  equalityOnly = true;
1688  } else
1689  return false;
1690  } else
1691  equalityOnly = is64BitUnsignedCompare;
1692  } else
1693  equalityOnly = is32BitUnsignedCompare;
1694 
1695  if (equalityOnly) {
1696  // We need to check the uses of the condition register in order to reject
1697  // non-equality comparisons.
1699  I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1700  I != IE; ++I) {
1701  MachineInstr *UseMI = &*I;
1702  if (UseMI->getOpcode() == PPC::BCC) {
1703  PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
1704  unsigned PredCond = PPC::getPredicateCondition(Pred);
1705  // We ignore hint bits when checking for non-equality comparisons.
1706  if (PredCond != PPC::PRED_EQ && PredCond != PPC::PRED_NE)
1707  return false;
1708  } else if (UseMI->getOpcode() == PPC::ISEL ||
1709  UseMI->getOpcode() == PPC::ISEL8) {
1710  unsigned SubIdx = UseMI->getOperand(3).getSubReg();
1711  if (SubIdx != PPC::sub_eq)
1712  return false;
1713  } else
1714  return false;
1715  }
1716  }
1717 
1718  MachineBasicBlock::iterator I = CmpInstr;
1719 
1720  // Scan forward to find the first use of the compare.
1721  for (MachineBasicBlock::iterator EL = CmpInstr.getParent()->end(); I != EL;
1722  ++I) {
1723  bool FoundUse = false;
1725  J = MRI->use_instr_begin(CRReg), JE = MRI->use_instr_end();
1726  J != JE; ++J)
1727  if (&*J == &*I) {
1728  FoundUse = true;
1729  break;
1730  }
1731 
1732  if (FoundUse)
1733  break;
1734  }
1735 
1738 
1739  // There are two possible candidates which can be changed to set CR[01].
1740  // One is MI, the other is a SUB instruction.
1741  // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
1742  MachineInstr *Sub = nullptr;
1743  if (SrcReg2 != 0)
1744  // MI is not a candidate for CMPrr.
1745  MI = nullptr;
1746  // FIXME: Conservatively refuse to convert an instruction which isn't in the
1747  // same BB as the comparison. This is to allow the check below to avoid calls
1748  // (and other explicit clobbers); instead we should really check for these
1749  // more explicitly (in at least a few predecessors).
1750  else if (MI->getParent() != CmpInstr.getParent())
1751  return false;
1752  else if (Value != 0) {
1753  // The record-form instructions set CR bit based on signed comparison
1754  // against 0. We try to convert a compare against 1 or -1 into a compare
1755  // against 0 to exploit record-form instructions. For example, we change
1756  // the condition "greater than -1" into "greater than or equal to 0"
1757  // and "less than 1" into "less than or equal to 0".
1758 
1759  // Since we optimize comparison based on a specific branch condition,
1760  // we don't optimize if condition code is used by more than once.
1761  if (equalityOnly || !MRI->hasOneUse(CRReg))
1762  return false;
1763 
1764  MachineInstr *UseMI = &*MRI->use_instr_begin(CRReg);
1765  if (UseMI->getOpcode() != PPC::BCC)
1766  return false;
1767 
1768  PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
1769  unsigned PredCond = PPC::getPredicateCondition(Pred);
1770  unsigned PredHint = PPC::getPredicateHint(Pred);
1771  int16_t Immed = (int16_t)Value;
1772 
1773  // When modifying the condition in the predicate, we propagate hint bits
1774  // from the original predicate to the new one.
1775  if (Immed == -1 && PredCond == PPC::PRED_GT)
1776  // We convert "greater than -1" into "greater than or equal to 0",
1777  // since we are assuming signed comparison by !equalityOnly
1778  Pred = PPC::getPredicate(PPC::PRED_GE, PredHint);
1779  else if (Immed == -1 && PredCond == PPC::PRED_LE)
1780  // We convert "less than or equal to -1" into "less than 0".
1781  Pred = PPC::getPredicate(PPC::PRED_LT, PredHint);
1782  else if (Immed == 1 && PredCond == PPC::PRED_LT)
1783  // We convert "less than 1" into "less than or equal to 0".
1784  Pred = PPC::getPredicate(PPC::PRED_LE, PredHint);
1785  else if (Immed == 1 && PredCond == PPC::PRED_GE)
1786  // We convert "greater than or equal to 1" into "greater than 0".
1787  Pred = PPC::getPredicate(PPC::PRED_GT, PredHint);
1788  else
1789  return false;
1790 
1791  PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)), Pred));
1792  }
1793 
1794  // Search for Sub.
1795  --I;
1796 
1797  // Get ready to iterate backward from CmpInstr.
1798  MachineBasicBlock::iterator E = MI, B = CmpInstr.getParent()->begin();
1799 
1800  for (; I != E && !noSub; --I) {
1801  const MachineInstr &Instr = *I;
1802  unsigned IOpC = Instr.getOpcode();
1803 
1804  if (&*I != &CmpInstr && (Instr.modifiesRegister(PPC::CR0, TRI) ||
1805  Instr.readsRegister(PPC::CR0, TRI)))
1806  // This instruction modifies or uses the record condition register after
1807  // the one we want to change. While we could do this transformation, it
1808  // would likely not be profitable. This transformation removes one
1809  // instruction, and so even forcing RA to generate one move probably
1810  // makes it unprofitable.
1811  return false;
1812 
1813  // Check whether CmpInstr can be made redundant by the current instruction.
1814  if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
1815  OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
1816  (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
1817  ((Instr.getOperand(1).getReg() == SrcReg &&
1818  Instr.getOperand(2).getReg() == SrcReg2) ||
1819  (Instr.getOperand(1).getReg() == SrcReg2 &&
1820  Instr.getOperand(2).getReg() == SrcReg))) {
1821  Sub = &*I;
1822  break;
1823  }
1824 
1825  if (I == B)
1826  // The 'and' is below the comparison instruction.
1827  return false;
1828  }
1829 
1830  // Return false if no candidates exist.
1831  if (!MI && !Sub)
1832  return false;
1833 
1834  // The single candidate is called MI.
1835  if (!MI) MI = Sub;
1836 
1837  int NewOpC = -1;
1838  int MIOpC = MI->getOpcode();
1839  if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8 ||
1840  MIOpC == PPC::ANDISo || MIOpC == PPC::ANDISo8)
1841  NewOpC = MIOpC;
1842  else {
1843  NewOpC = PPC::getRecordFormOpcode(MIOpC);
1844  if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
1845  NewOpC = MIOpC;
1846  }
1847 
1848  // FIXME: On the non-embedded POWER architectures, only some of the record
1849  // forms are fast, and we should use only the fast ones.
1850 
1851  // The defining instruction has a record form (or is already a record
1852  // form). It is possible, however, that we'll need to reverse the condition
1853  // code of the users.
1854  if (NewOpC == -1)
1855  return false;
1856 
1857  // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
1858  // needs to be updated to be based on SUB. Push the condition code
1859  // operands to OperandsToUpdate. If it is safe to remove CmpInstr, the
1860  // condition code of these operands will be modified.
1861  // Here, Value == 0 means we haven't converted comparison against 1 or -1 to
1862  // comparison against 0, which may modify predicate.
1863  bool ShouldSwap = false;
1864  if (Sub && Value == 0) {
1865  ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1866  Sub->getOperand(2).getReg() == SrcReg;
1867 
1868  // The operands to subf are the opposite of sub, so only in the fixed-point
1869  // case, invert the order.
1870  ShouldSwap = !ShouldSwap;
1871  }
1872 
1873  if (ShouldSwap)
1875  I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1876  I != IE; ++I) {
1877  MachineInstr *UseMI = &*I;
1878  if (UseMI->getOpcode() == PPC::BCC) {
1879  PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
1880  unsigned PredCond = PPC::getPredicateCondition(Pred);
1881  assert((!equalityOnly ||
1882  PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE) &&
1883  "Invalid predicate for equality-only optimization");
1884  (void)PredCond; // To suppress warning in release build.
1885  PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1886  PPC::getSwappedPredicate(Pred)));
1887  } else if (UseMI->getOpcode() == PPC::ISEL ||
1888  UseMI->getOpcode() == PPC::ISEL8) {
1889  unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
1890  assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
1891  "Invalid CR bit for equality-only optimization");
1892 
1893  if (NewSubReg == PPC::sub_lt)
1894  NewSubReg = PPC::sub_gt;
1895  else if (NewSubReg == PPC::sub_gt)
1896  NewSubReg = PPC::sub_lt;
1897 
1898  SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)),
1899  NewSubReg));
1900  } else // We need to abort on a user we don't understand.
1901  return false;
1902  }
1903  assert(!(Value != 0 && ShouldSwap) &&
1904  "Non-zero immediate support and ShouldSwap"
1905  "may conflict in updating predicate");
1906 
1907  // Create a new virtual register to hold the value of the CR set by the
1908  // record-form instruction. If the instruction was not previously in
1909  // record form, then set the kill flag on the CR.
1910  CmpInstr.eraseFromParent();
1911 
1913  BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
1914  get(TargetOpcode::COPY), CRReg)
1915  .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
1916 
1917  // Even if CR0 register were dead before, it is alive now since the
1918  // instruction we just built uses it.
1919  MI->clearRegisterDeads(PPC::CR0);
1920 
1921  if (MIOpC != NewOpC) {
1922  // We need to be careful here: we're replacing one instruction with
1923  // another, and we need to make sure that we get all of the right
1924  // implicit uses and defs. On the other hand, the caller may be holding
1925  // an iterator to this instruction, and so we can't delete it (this is
1926  // specifically the case if this is the instruction directly after the
1927  // compare).
1928 
1929  // Rotates are expensive instructions. If we're emitting a record-form
1930  // rotate that can just be an andi/andis, we should just emit that.
1931  if (MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINM8) {
1932  Register GPRRes = MI->getOperand(0).getReg();
1933  int64_t SH = MI->getOperand(2).getImm();
1934  int64_t MB = MI->getOperand(3).getImm();
1935  int64_t ME = MI->getOperand(4).getImm();
1936  // We can only do this if both the start and end of the mask are in the
1937  // same halfword.
1938  bool MBInLoHWord = MB >= 16;
1939  bool MEInLoHWord = ME >= 16;
1940  uint64_t Mask = ~0LLU;
1941 
1942  if (MB <= ME && MBInLoHWord == MEInLoHWord && SH == 0) {
1943  Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
1944  // The mask value needs to shift right 16 if we're emitting andis.
1945  Mask >>= MBInLoHWord ? 0 : 16;
1946  NewOpC = MIOpC == PPC::RLWINM ?
1947  (MBInLoHWord ? PPC::ANDIo : PPC::ANDISo) :
1948  (MBInLoHWord ? PPC::ANDIo8 :PPC::ANDISo8);
1949  } else if (MRI->use_empty(GPRRes) && (ME == 31) &&
1950  (ME - MB + 1 == SH) && (MB >= 16)) {
1951  // If we are rotating by the exact number of bits as are in the mask
1952  // and the mask is in the least significant bits of the register,
1953  // that's just an andis. (as long as the GPR result has no uses).
1954  Mask = ((1LLU << 32) - 1) & ~((1LLU << (32 - SH)) - 1);
1955  Mask >>= 16;
1956  NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDISo :PPC::ANDISo8;
1957  }
1958  // If we've set the mask, we can transform.
1959  if (Mask != ~0LLU) {
1960  MI->RemoveOperand(4);
1961  MI->RemoveOperand(3);
1962  MI->getOperand(2).setImm(Mask);
1963  NumRcRotatesConvertedToRcAnd++;
1964  }
1965  } else if (MIOpC == PPC::RLDICL && MI->getOperand(2).getImm() == 0) {
1966  int64_t MB = MI->getOperand(3).getImm();
1967  if (MB >= 48) {
1968  uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
1969  NewOpC = PPC::ANDIo8;
1970  MI->RemoveOperand(3);
1971  MI->getOperand(2).setImm(Mask);
1972  NumRcRotatesConvertedToRcAnd++;
1973  }
1974  }
1975 
1976  const MCInstrDesc &NewDesc = get(NewOpC);
1977  MI->setDesc(NewDesc);
1978 
1979  if (NewDesc.ImplicitDefs)
1980  for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs();
1981  *ImpDefs; ++ImpDefs)
1982  if (!MI->definesRegister(*ImpDefs))
1983  MI->addOperand(*MI->getParent()->getParent(),
1984  MachineOperand::CreateReg(*ImpDefs, true, true));
1985  if (NewDesc.ImplicitUses)
1986  for (const MCPhysReg *ImpUses = NewDesc.getImplicitUses();
1987  *ImpUses; ++ImpUses)
1988  if (!MI->readsRegister(*ImpUses))
1989  MI->addOperand(*MI->getParent()->getParent(),
1990  MachineOperand::CreateReg(*ImpUses, false, true));
1991  }
1992  assert(MI->definesRegister(PPC::CR0) &&
1993  "Record-form instruction does not define cr0?");
1994 
1995  // Modify the condition code of operands in OperandsToUpdate.
1996  // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
1997  // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
1998  for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
1999  PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
2000 
2001  for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
2002  SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
2003 
2004  return true;
2005 }
2006 
2007 /// GetInstSize - Return the number of bytes of code the specified
2008 /// instruction may be. This returns the maximum number of bytes.
2009 ///
2011  unsigned Opcode = MI.getOpcode();
2012 
2013  if (Opcode == PPC::INLINEASM || Opcode == PPC::INLINEASM_BR) {
2014  const MachineFunction *MF = MI.getParent()->getParent();
2015  const char *AsmStr = MI.getOperand(0).getSymbolName();
2016  return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
2017  } else if (Opcode == TargetOpcode::STACKMAP) {
2018  StackMapOpers Opers(&MI);
2019  return Opers.getNumPatchBytes();
2020  } else if (Opcode == TargetOpcode::PATCHPOINT) {
2021  PatchPointOpers Opers(&MI);
2022  return Opers.getNumPatchBytes();
2023  } else {
2024  return get(Opcode).getSize();
2025  }
2026 }
2027 
2028 std::pair<unsigned, unsigned>
2030  const unsigned Mask = PPCII::MO_ACCESS_MASK;
2031  return std::make_pair(TF & Mask, TF & ~Mask);
2032 }
2033 
2036  using namespace PPCII;
2037  static const std::pair<unsigned, const char *> TargetFlags[] = {
2038  {MO_LO, "ppc-lo"},
2039  {MO_HA, "ppc-ha"},
2040  {MO_TPREL_LO, "ppc-tprel-lo"},
2041  {MO_TPREL_HA, "ppc-tprel-ha"},
2042  {MO_DTPREL_LO, "ppc-dtprel-lo"},
2043  {MO_TLSLD_LO, "ppc-tlsld-lo"},
2044  {MO_TOC_LO, "ppc-toc-lo"},
2045  {MO_TLS, "ppc-tls"}};
2046  return makeArrayRef(TargetFlags);
2047 }
2048 
2051  using namespace PPCII;
2052  static const std::pair<unsigned, const char *> TargetFlags[] = {
2053  {MO_PLT, "ppc-plt"},
2054  {MO_PIC_FLAG, "ppc-pic"},
2055  {MO_NLP_FLAG, "ppc-nlp"},
2056  {MO_NLP_HIDDEN_FLAG, "ppc-nlp-hidden"}};
2057  return makeArrayRef(TargetFlags);
2058 }
2059 
2060 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
2061 // The VSX versions have the advantage of a full 64-register target whereas
2062 // the FP ones have the advantage of lower latency and higher throughput. So
2063 // what we are after is using the faster instructions in low register pressure
2064 // situations and using the larger register file in high register pressure
2065 // situations.
2067  unsigned UpperOpcode, LowerOpcode;
2068  switch (MI.getOpcode()) {
2069  case PPC::DFLOADf32:
2070  UpperOpcode = PPC::LXSSP;
2071  LowerOpcode = PPC::LFS;
2072  break;
2073  case PPC::DFLOADf64:
2074  UpperOpcode = PPC::LXSD;
2075  LowerOpcode = PPC::LFD;
2076  break;
2077  case PPC::DFSTOREf32:
2078  UpperOpcode = PPC::STXSSP;
2079  LowerOpcode = PPC::STFS;
2080  break;
2081  case PPC::DFSTOREf64:
2082  UpperOpcode = PPC::STXSD;
2083  LowerOpcode = PPC::STFD;
2084  break;
2085  case PPC::XFLOADf32:
2086  UpperOpcode = PPC::LXSSPX;
2087  LowerOpcode = PPC::LFSX;
2088  break;
2089  case PPC::XFLOADf64:
2090  UpperOpcode = PPC::LXSDX;
2091  LowerOpcode = PPC::LFDX;
2092  break;
2093  case PPC::XFSTOREf32:
2094  UpperOpcode = PPC::STXSSPX;
2095  LowerOpcode = PPC::STFSX;
2096  break;
2097  case PPC::XFSTOREf64:
2098  UpperOpcode = PPC::STXSDX;
2099  LowerOpcode = PPC::STFDX;
2100  break;
2101  case PPC::LIWAX:
2102  UpperOpcode = PPC::LXSIWAX;
2103  LowerOpcode = PPC::LFIWAX;
2104  break;
2105  case PPC::LIWZX:
2106  UpperOpcode = PPC::LXSIWZX;
2107  LowerOpcode = PPC::LFIWZX;
2108  break;
2109  case PPC::STIWX:
2110  UpperOpcode = PPC::STXSIWX;
2111  LowerOpcode = PPC::STFIWX;
2112  break;
2113  default:
2114  llvm_unreachable("Unknown Operation!");
2115  }
2116 
2117  Register TargetReg = MI.getOperand(0).getReg();
2118  unsigned Opcode;
2119  if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) ||
2120  (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31))
2121  Opcode = LowerOpcode;
2122  else
2123  Opcode = UpperOpcode;
2124  MI.setDesc(get(Opcode));
2125  return true;
2126 }
2127 
2128 static bool isAnImmediateOperand(const MachineOperand &MO) {
2129  return MO.isCPI() || MO.isGlobal() || MO.isImm();
2130 }
2131 
2133  auto &MBB = *MI.getParent();
2134  auto DL = MI.getDebugLoc();
2135 
2136  switch (MI.getOpcode()) {
2137  case TargetOpcode::LOAD_STACK_GUARD: {
2138  assert(Subtarget.isTargetLinux() &&
2139  "Only Linux target is expected to contain LOAD_STACK_GUARD");
2140  const int64_t Offset = Subtarget.isPPC64() ? -0x7010 : -0x7008;
2141  const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2;
2142  MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ));
2144  .addImm(Offset)
2145  .addReg(Reg);
2146  return true;
2147  }
2148  case PPC::DFLOADf32:
2149  case PPC::DFLOADf64:
2150  case PPC::DFSTOREf32:
2151  case PPC::DFSTOREf64: {
2152  assert(Subtarget.hasP9Vector() &&
2153  "Invalid D-Form Pseudo-ops on Pre-P9 target.");
2154  assert(MI.getOperand(2).isReg() &&
2156  "D-form op must have register and immediate operands");
2157  return expandVSXMemPseudo(MI);
2158  }
2159  case PPC::XFLOADf32:
2160  case PPC::XFSTOREf32:
2161  case PPC::LIWAX:
2162  case PPC::LIWZX:
2163  case PPC::STIWX: {
2164  assert(Subtarget.hasP8Vector() &&
2165  "Invalid X-Form Pseudo-ops on Pre-P8 target.");
2166  assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
2167  "X-form op must have register and register operands");
2168  return expandVSXMemPseudo(MI);
2169  }
2170  case PPC::XFLOADf64:
2171  case PPC::XFSTOREf64: {
2172  assert(Subtarget.hasVSX() &&
2173  "Invalid X-Form Pseudo-ops on target that has no VSX.");
2174  assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
2175  "X-form op must have register and register operands");
2176  return expandVSXMemPseudo(MI);
2177  }
2178  case PPC::SPILLTOVSR_LD: {
2179  Register TargetReg = MI.getOperand(0).getReg();
2180  if (PPC::VSFRCRegClass.contains(TargetReg)) {
2181  MI.setDesc(get(PPC::DFLOADf64));
2182  return expandPostRAPseudo(MI);
2183  }
2184  else
2185  MI.setDesc(get(PPC::LD));
2186  return true;
2187  }
2188  case PPC::SPILLTOVSR_ST: {
2189  Register SrcReg = MI.getOperand(0).getReg();
2190  if (PPC::VSFRCRegClass.contains(SrcReg)) {
2191  NumStoreSPILLVSRRCAsVec++;
2192  MI.setDesc(get(PPC::DFSTOREf64));
2193  return expandPostRAPseudo(MI);
2194  } else {
2195  NumStoreSPILLVSRRCAsGpr++;
2196  MI.setDesc(get(PPC::STD));
2197  }
2198  return true;
2199  }
2200  case PPC::SPILLTOVSR_LDX: {
2201  Register TargetReg = MI.getOperand(0).getReg();
2202  if (PPC::VSFRCRegClass.contains(TargetReg))
2203  MI.setDesc(get(PPC::LXSDX));
2204  else
2205  MI.setDesc(get(PPC::LDX));
2206  return true;
2207  }
2208  case PPC::SPILLTOVSR_STX: {
2209  Register SrcReg = MI.getOperand(0).getReg();
2210  if (PPC::VSFRCRegClass.contains(SrcReg)) {
2211  NumStoreSPILLVSRRCAsVec++;
2212  MI.setDesc(get(PPC::STXSDX));
2213  } else {
2214  NumStoreSPILLVSRRCAsGpr++;
2215  MI.setDesc(get(PPC::STDX));
2216  }
2217  return true;
2218  }
2219 
2220  case PPC::CFENCE8: {
2221  auto Val = MI.getOperand(0).getReg();
2222  BuildMI(MBB, MI, DL, get(PPC::CMPD), PPC::CR7).addReg(Val).addReg(Val);
2223  BuildMI(MBB, MI, DL, get(PPC::CTRL_DEP))
2225  .addReg(PPC::CR7)
2226  .addImm(1);
2227  MI.setDesc(get(PPC::ISYNC));
2228  MI.RemoveOperand(0);
2229  return true;
2230  }
2231  }
2232  return false;
2233 }
2234 
2235 // Essentially a compile-time implementation of a compare->isel sequence.
2236 // It takes two constants to compare, along with the true/false registers
2237 // and the comparison type (as a subreg to a CR field) and returns one
2238 // of the true/false registers, depending on the comparison results.
2239 static unsigned selectReg(int64_t Imm1, int64_t Imm2, unsigned CompareOpc,
2240  unsigned TrueReg, unsigned FalseReg,
2241  unsigned CRSubReg) {
2242  // Signed comparisons. The immediates are assumed to be sign-extended.
2243  if (CompareOpc == PPC::CMPWI || CompareOpc == PPC::CMPDI) {
2244  switch (CRSubReg) {
2245  default: llvm_unreachable("Unknown integer comparison type.");
2246  case PPC::sub_lt:
2247  return Imm1 < Imm2 ? TrueReg : FalseReg;
2248  case PPC::sub_gt:
2249  return Imm1 > Imm2 ? TrueReg : FalseReg;
2250  case PPC::sub_eq:
2251  return Imm1 == Imm2 ? TrueReg : FalseReg;
2252  }
2253  }
2254  // Unsigned comparisons.
2255  else if (CompareOpc == PPC::CMPLWI || CompareOpc == PPC::CMPLDI) {
2256  switch (CRSubReg) {
2257  default: llvm_unreachable("Unknown integer comparison type.");
2258  case PPC::sub_lt:
2259  return (uint64_t)Imm1 < (uint64_t)Imm2 ? TrueReg : FalseReg;
2260  case PPC::sub_gt:
2261  return (uint64_t)Imm1 > (uint64_t)Imm2 ? TrueReg : FalseReg;
2262  case PPC::sub_eq:
2263  return Imm1 == Imm2 ? TrueReg : FalseReg;
2264  }
2265  }
2266  return PPC::NoRegister;
2267 }
2268 
2270  unsigned OpNo,
2271  int64_t Imm) const {
2272  assert(MI.getOperand(OpNo).isReg() && "Operand must be a REG");
2273  // Replace the REG with the Immediate.
2274  Register InUseReg = MI.getOperand(OpNo).getReg();
2275  MI.getOperand(OpNo).ChangeToImmediate(Imm);
2276 
2277  if (MI.implicit_operands().empty())
2278  return;
2279 
2280  // We need to make sure that the MI didn't have any implicit use
2281  // of this REG any more.
2283  int UseOpIdx = MI.findRegisterUseOperandIdx(InUseReg, false, TRI);
2284  if (UseOpIdx >= 0) {
2285  MachineOperand &MO = MI.getOperand(UseOpIdx);
2286  if (MO.isImplicit())
2287  // The operands must always be in the following order:
2288  // - explicit reg defs,
2289  // - other explicit operands (reg uses, immediates, etc.),
2290  // - implicit reg defs
2291  // - implicit reg uses
2292  // Therefore, removing the implicit operand won't change the explicit
2293  // operands layout.
2294  MI.RemoveOperand(UseOpIdx);
2295  }
2296 }
2297 
2298 // Replace an instruction with one that materializes a constant (and sets
2299 // CR0 if the original instruction was a record-form instruction).
2301  const LoadImmediateInfo &LII) const {
2302  // Remove existing operands.
2303  int OperandToKeep = LII.SetCR ? 1 : 0;
2304  for (int i = MI.getNumOperands() - 1; i > OperandToKeep; i--)
2305  MI.RemoveOperand(i);
2306 
2307  // Replace the instruction.
2308  if (LII.SetCR) {
2309  MI.setDesc(get(LII.Is64Bit ? PPC::ANDIo8 : PPC::ANDIo));
2310  // Set the immediate.
2312  .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine);
2313  return;
2314  }
2315  else
2316  MI.setDesc(get(LII.Is64Bit ? PPC::LI8 : PPC::LI));
2317 
2318  // Set the immediate.
2320  .addImm(LII.Imm);
2321 }
2322 
2324  bool &SeenIntermediateUse) const {
2325  assert(!MI.getParent()->getParent()->getRegInfo().isSSA() &&
2326  "Should be called after register allocation.");
2329  It++;
2330  SeenIntermediateUse = false;
2331  for (; It != E; ++It) {
2332  if (It->modifiesRegister(Reg, TRI))
2333  return &*It;
2334  if (It->readsRegister(Reg, TRI))
2335  SeenIntermediateUse = true;
2336  }
2337  return nullptr;
2338 }
2339 
2340 MachineInstr *PPCInstrInfo::getForwardingDefMI(
2341  MachineInstr &MI,
2342  unsigned &OpNoForForwarding,
2343  bool &SeenIntermediateUse) const {
2344  OpNoForForwarding = ~0U;
2345  MachineInstr *DefMI = nullptr;
2348  // If we're in SSA, get the defs through the MRI. Otherwise, only look
2349  // within the basic block to see if the register is defined using an LI/LI8.
2350  if (MRI->isSSA()) {
2351  for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
2352  if (!MI.getOperand(i).isReg())
2353  continue;
2354  Register Reg = MI.getOperand(i).getReg();
2355  if (!Register::isVirtualRegister(Reg))
2356  continue;
2357  unsigned TrueReg = TRI->lookThruCopyLike(Reg, MRI);
2358  if (Register::isVirtualRegister(TrueReg)) {
2359  DefMI = MRI->getVRegDef(TrueReg);
2360  if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8) {
2361  OpNoForForwarding = i;
2362  break;
2363  }
2364  }
2365  }
2366  } else {
2367  // Looking back through the definition for each operand could be expensive,
2368  // so exit early if this isn't an instruction that either has an immediate
2369  // form or is already an immediate form that we can handle.
2370  ImmInstrInfo III;
2371  unsigned Opc = MI.getOpcode();
2372  bool ConvertibleImmForm =
2373  Opc == PPC::CMPWI || Opc == PPC::CMPLWI ||
2374  Opc == PPC::CMPDI || Opc == PPC::CMPLDI ||
2375  Opc == PPC::ADDI || Opc == PPC::ADDI8 ||
2376  Opc == PPC::ORI || Opc == PPC::ORI8 ||
2377  Opc == PPC::XORI || Opc == PPC::XORI8 ||
2378  Opc == PPC::RLDICL || Opc == PPC::RLDICLo ||
2379  Opc == PPC::RLDICL_32 || Opc == PPC::RLDICL_32_64 ||
2380  Opc == PPC::RLWINM || Opc == PPC::RLWINMo ||
2381  Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
2382  bool IsVFReg = (MI.getNumOperands() && MI.getOperand(0).isReg())
2383  ? isVFRegister(MI.getOperand(0).getReg())
2384  : false;
2385  if (!ConvertibleImmForm && !instrHasImmForm(Opc, IsVFReg, III, true))
2386  return nullptr;
2387 
2388  // Don't convert or %X, %Y, %Y since that's just a register move.
2389  if ((Opc == PPC::OR || Opc == PPC::OR8) &&
2390  MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
2391  return nullptr;
2392  for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
2393  MachineOperand &MO = MI.getOperand(i);
2394  SeenIntermediateUse = false;
2395  if (MO.isReg() && MO.isUse() && !MO.isImplicit()) {
2396  Register Reg = MI.getOperand(i).getReg();
2397  // If we see another use of this reg between the def and the MI,
2398  // we want to flat it so the def isn't deleted.
2399  MachineInstr *DefMI = getDefMIPostRA(Reg, MI, SeenIntermediateUse);
2400  if (DefMI) {
2401  // Is this register defined by some form of add-immediate (including
2402  // load-immediate) within this basic block?
2403  switch (DefMI->getOpcode()) {
2404  default:
2405  break;
2406  case PPC::LI:
2407  case PPC::LI8:
2408  case PPC::ADDItocL:
2409  case PPC::ADDI:
2410  case PPC::ADDI8:
2411  OpNoForForwarding = i;
2412  return DefMI;
2413  }
2414  }
2415  }
2416  }
2417  }
2418  return OpNoForForwarding == ~0U ? nullptr : DefMI;
2419 }
2420 
2421 const unsigned *PPCInstrInfo::getStoreOpcodesForSpillArray() const {
2422  static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = {
2423  // Power 8
2424  {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
2425  PPC::SPILL_CRBIT, PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX,
2426  PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb,
2427  PPC::SPILLTOVSR_ST, PPC::EVSTDD},
2428  // Power 9
2429  {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
2430  PPC::SPILL_CRBIT, PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32,
2431  PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb,
2432  PPC::SPILLTOVSR_ST}};
2433 
2434  return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0];
2435 }
2436 
2437 const unsigned *PPCInstrInfo::getLoadOpcodesForSpillArray() const {
2438  static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = {
2439  // Power 8
2440  {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
2441  PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX,
2442  PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
2443  PPC::SPILLTOVSR_LD, PPC::EVLDD},
2444  // Power 9
2445  {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
2446  PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, PPC::DFLOADf32,
2447  PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
2448  PPC::SPILLTOVSR_LD}};
2449 
2450  return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0];
2451 }
2452 
2454  unsigned RegNo) const {
2455  const MachineRegisterInfo &MRI =
2456  StartMI.getParent()->getParent()->getRegInfo();
2457  if (MRI.isSSA())
2458  return;
2459 
2460  // Instructions between [StartMI, EndMI] should be in same basic block.
2461  assert((StartMI.getParent() == EndMI.getParent()) &&
2462  "Instructions are not in same basic block");
2463 
2464  bool IsKillSet = false;
2465 
2466  auto clearOperandKillInfo = [=] (MachineInstr &MI, unsigned Index) {
2467  MachineOperand &MO = MI.getOperand(Index);
2468  if (MO.isReg() && MO.isUse() && MO.isKill() &&
2469  getRegisterInfo().regsOverlap(MO.getReg(), RegNo))
2470  MO.setIsKill(false);
2471  };
2472 
2473  // Set killed flag for EndMI.
2474  // No need to do anything if EndMI defines RegNo.
2475  int UseIndex =
2476  EndMI.findRegisterUseOperandIdx(RegNo, false, &getRegisterInfo());
2477  if (UseIndex != -1) {
2478  EndMI.getOperand(UseIndex).setIsKill(true);
2479  IsKillSet = true;
2480  // Clear killed flag for other EndMI operands related to RegNo. In some
2481  // upexpected cases, killed may be set multiple times for same register
2482  // operand in same MI.
2483  for (int i = 0, e = EndMI.getNumOperands(); i != e; ++i)
2484  if (i != UseIndex)
2485  clearOperandKillInfo(EndMI, i);
2486  }
2487 
2488  // Walking the inst in reverse order (EndMI -> StartMI].
2491  // EndMI has been handled above, skip it here.
2492  It++;
2493  MachineOperand *MO = nullptr;
2494  for (; It != E; ++It) {
2495  // Skip insturctions which could not be a def/use of RegNo.
2496  if (It->isDebugInstr() || It->isPosition())
2497  continue;
2498 
2499  // Clear killed flag for all It operands related to RegNo. In some
2500  // upexpected cases, killed may be set multiple times for same register
2501  // operand in same MI.
2502  for (int i = 0, e = It->getNumOperands(); i != e; ++i)
2503  clearOperandKillInfo(*It, i);
2504 
2505  // If killed is not set, set killed for its last use or set dead for its def
2506  // if no use found.
2507  if (!IsKillSet) {
2508  if ((MO = It->findRegisterUseOperand(RegNo, false, &getRegisterInfo()))) {
2509  // Use found, set it killed.
2510  IsKillSet = true;
2511  MO->setIsKill(true);
2512  continue;
2513  } else if ((MO = It->findRegisterDefOperand(RegNo, false, true,
2514  &getRegisterInfo()))) {
2515  // No use found, set dead for its def.
2516  assert(&*It == &StartMI && "No new def between StartMI and EndMI.");
2517  MO->setIsDead(true);
2518  break;
2519  }
2520  }
2521 
2522  if ((&*It) == &StartMI)
2523  break;
2524  }
2525  // Ensure RegMo liveness is killed after EndMI.
2526  assert((IsKillSet || (MO && MO->isDead())) &&
2527  "RegNo should be killed or dead");
2528 }
2529 
2530 // If this instruction has an immediate form and one of its operands is a
2531 // result of a load-immediate or an add-immediate, convert it to
2532 // the immediate form if the constant is in range.
2534  MachineInstr **KilledDef) const {
2535  MachineFunction *MF = MI.getParent()->getParent();
2537  bool PostRA = !MRI->isSSA();
2538  bool SeenIntermediateUse = true;
2539  unsigned ForwardingOperand = ~0U;
2540  MachineInstr *DefMI = getForwardingDefMI(MI, ForwardingOperand,
2541  SeenIntermediateUse);
2542  if (!DefMI)
2543  return false;
2544  assert(ForwardingOperand < MI.getNumOperands() &&
2545  "The forwarding operand needs to be valid at this point");
2546  bool IsForwardingOperandKilled = MI.getOperand(ForwardingOperand).isKill();
2547  bool KillFwdDefMI = !SeenIntermediateUse && IsForwardingOperandKilled;
2548  Register ForwardingOperandReg = MI.getOperand(ForwardingOperand).getReg();
2549  if (KilledDef && KillFwdDefMI)
2550  *KilledDef = DefMI;
2551 
2552  ImmInstrInfo III;
2553  bool IsVFReg = MI.getOperand(0).isReg()
2554  ? isVFRegister(MI.getOperand(0).getReg())
2555  : false;
2556  bool HasImmForm = instrHasImmForm(MI.getOpcode(), IsVFReg, III, PostRA);
2557  // If this is a reg+reg instruction that has a reg+imm form,
2558  // and one of the operands is produced by an add-immediate,
2559  // try to convert it.
2560  if (HasImmForm &&
2561  transformToImmFormFedByAdd(MI, III, ForwardingOperand, *DefMI,
2562  KillFwdDefMI))
2563  return true;
2564 
2565  if ((DefMI->getOpcode() != PPC::LI && DefMI->getOpcode() != PPC::LI8) ||
2566  !DefMI->getOperand(1).isImm())
2567  return false;
2568 
2569  int64_t Immediate = DefMI->getOperand(1).getImm();
2570  // Sign-extend to 64-bits.
2571  int64_t SExtImm = ((uint64_t)Immediate & ~0x7FFFuLL) != 0 ?
2572  (Immediate | 0xFFFFFFFFFFFF0000) : Immediate;
2573 
2574  // If this is a reg+reg instruction that has a reg+imm form,
2575  // and one of the operands is produced by LI, convert it now.
2576  if (HasImmForm)
2577  return transformToImmFormFedByLI(MI, III, ForwardingOperand, *DefMI, SExtImm);
2578 
2579  bool ReplaceWithLI = false;
2580  bool Is64BitLI = false;
2581  int64_t NewImm = 0;
2582  bool SetCR = false;
2583  unsigned Opc = MI.getOpcode();
2584  switch (Opc) {
2585  default: return false;
2586 
2587  // FIXME: Any branches conditional on such a comparison can be made
2588  // unconditional. At this time, this happens too infrequently to be worth
2589  // the implementation effort, but if that ever changes, we could convert
2590  // such a pattern here.
2591  case PPC::CMPWI:
2592  case PPC::CMPLWI:
2593  case PPC::CMPDI:
2594  case PPC::CMPLDI: {
2595  // Doing this post-RA would require dataflow analysis to reliably find uses
2596  // of the CR register set by the compare.
2597  // No need to fixup killed/dead flag since this transformation is only valid
2598  // before RA.
2599  if (PostRA)
2600  return false;
2601  // If a compare-immediate is fed by an immediate and is itself an input of
2602  // an ISEL (the most common case) into a COPY of the correct register.
2603  bool Changed = false;
2604  Register DefReg = MI.getOperand(0).getReg();
2605  int64_t Comparand = MI.getOperand(2).getImm();
2606  int64_t SExtComparand = ((uint64_t)Comparand & ~0x7FFFuLL) != 0 ?
2607  (Comparand | 0xFFFFFFFFFFFF0000) : Comparand;
2608 
2609  for (auto &CompareUseMI : MRI->use_instructions(DefReg)) {
2610  unsigned UseOpc = CompareUseMI.getOpcode();
2611  if (UseOpc != PPC::ISEL && UseOpc != PPC::ISEL8)
2612  continue;
2613  unsigned CRSubReg = CompareUseMI.getOperand(3).getSubReg();
2614  Register TrueReg = CompareUseMI.getOperand(1).getReg();
2615  Register FalseReg = CompareUseMI.getOperand(2).getReg();
2616  unsigned RegToCopy = selectReg(SExtImm, SExtComparand, Opc, TrueReg,
2617  FalseReg, CRSubReg);
2618  if (RegToCopy == PPC::NoRegister)
2619  continue;
2620  // Can't use PPC::COPY to copy PPC::ZERO[8]. Convert it to LI[8] 0.
2621  if (RegToCopy == PPC::ZERO || RegToCopy == PPC::ZERO8) {
2622  CompareUseMI.setDesc(get(UseOpc == PPC::ISEL8 ? PPC::LI8 : PPC::LI));
2623  replaceInstrOperandWithImm(CompareUseMI, 1, 0);
2624  CompareUseMI.RemoveOperand(3);
2625  CompareUseMI.RemoveOperand(2);
2626  continue;
2627  }
2628  LLVM_DEBUG(
2629  dbgs() << "Found LI -> CMPI -> ISEL, replacing with a copy.\n");
2630  LLVM_DEBUG(DefMI->dump(); MI.dump(); CompareUseMI.dump());
2631  LLVM_DEBUG(dbgs() << "Is converted to:\n");
2632  // Convert to copy and remove unneeded operands.
2633  CompareUseMI.setDesc(get(PPC::COPY));
2634  CompareUseMI.RemoveOperand(3);
2635  CompareUseMI.RemoveOperand(RegToCopy == TrueReg ? 2 : 1);
2636  CmpIselsConverted++;
2637  Changed = true;
2638  LLVM_DEBUG(CompareUseMI.dump());
2639  }
2640  if (Changed)
2641  return true;
2642  // This may end up incremented multiple times since this function is called
2643  // during a fixed-point transformation, but it is only meant to indicate the
2644  // presence of this opportunity.
2645  MissedConvertibleImmediateInstrs++;
2646  return false;
2647  }
2648 
2649  // Immediate forms - may simply be convertable to an LI.
2650  case PPC::ADDI:
2651  case PPC::ADDI8: {
2652  // Does the sum fit in a 16-bit signed field?
2653  int64_t Addend = MI.getOperand(2).getImm();
2654  if (isInt<16>(Addend + SExtImm)) {
2655  ReplaceWithLI = true;
2656  Is64BitLI = Opc == PPC::ADDI8;
2657  NewImm = Addend + SExtImm;
2658  break;
2659  }
2660  return false;
2661  }
2662  case PPC::RLDICL:
2663  case PPC::RLDICLo:
2664  case PPC::RLDICL_32:
2665  case PPC::RLDICL_32_64: {
2666  // Use APInt's rotate function.
2667  int64_t SH = MI.getOperand(2).getImm();
2668  int64_t MB = MI.getOperand(3).getImm();
2669  APInt InVal((Opc == PPC::RLDICL || Opc == PPC::RLDICLo) ?
2670  64 : 32, SExtImm, true);
2671  InVal = InVal.rotl(SH);
2672  uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
2673  InVal &= Mask;
2674  // Can't replace negative values with an LI as that will sign-extend
2675  // and not clear the left bits. If we're setting the CR bit, we will use
2676  // ANDIo which won't sign extend, so that's safe.
2677  if (isUInt<15>(InVal.getSExtValue()) ||
2678  (Opc == PPC::RLDICLo && isUInt<16>(InVal.getSExtValue()))) {
2679  ReplaceWithLI = true;
2680  Is64BitLI = Opc != PPC::RLDICL_32;
2681  NewImm = InVal.getSExtValue();
2682  SetCR = Opc == PPC::RLDICLo;
2683  break;
2684  }
2685  return false;
2686  }
2687  case PPC::RLWINM:
2688  case PPC::RLWINM8:
2689  case PPC::RLWINMo:
2690  case PPC::RLWINM8o: {
2691  int64_t SH = MI.getOperand(2).getImm();
2692  int64_t MB = MI.getOperand(3).getImm();
2693  int64_t ME = MI.getOperand(4).getImm();
2694  APInt InVal(32, SExtImm, true);
2695  InVal = InVal.rotl(SH);
2696  // Set the bits ( MB + 32 ) to ( ME + 32 ).
2697  uint64_t Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
2698  InVal &= Mask;
2699  // Can't replace negative values with an LI as that will sign-extend
2700  // and not clear the left bits. If we're setting the CR bit, we will use
2701  // ANDIo which won't sign extend, so that's safe.
2702  bool ValueFits = isUInt<15>(InVal.getSExtValue());
2703  ValueFits |= ((Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o) &&
2704  isUInt<16>(InVal.getSExtValue()));
2705  if (ValueFits) {
2706  ReplaceWithLI = true;
2707  Is64BitLI = Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
2708  NewImm = InVal.getSExtValue();
2709  SetCR = Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o;
2710  break;
2711  }
2712  return false;
2713  }
2714  case PPC::ORI:
2715  case PPC::ORI8:
2716  case PPC::XORI:
2717  case PPC::XORI8: {
2718  int64_t LogicalImm = MI.getOperand(2).getImm();
2719  int64_t Result = 0;
2720  if (Opc == PPC::ORI || Opc == PPC::ORI8)
2721  Result = LogicalImm | SExtImm;
2722  else
2723  Result = LogicalImm ^ SExtImm;
2724  if (isInt<16>(Result)) {
2725  ReplaceWithLI = true;
2726  Is64BitLI = Opc == PPC::ORI8 || Opc == PPC::XORI8;
2727  NewImm = Result;
2728  break;
2729  }
2730  return false;
2731  }
2732  }
2733 
2734  if (ReplaceWithLI) {
2735  // We need to be careful with CR-setting instructions we're replacing.
2736  if (SetCR) {
2737  // We don't know anything about uses when we're out of SSA, so only
2738  // replace if the new immediate will be reproduced.
2739  bool ImmChanged = (SExtImm & NewImm) != NewImm;
2740  if (PostRA && ImmChanged)
2741  return false;
2742 
2743  if (!PostRA) {
2744  // If the defining load-immediate has no other uses, we can just replace
2745  // the immediate with the new immediate.
2746  if (MRI->hasOneUse(DefMI->getOperand(0).getReg()))
2747  DefMI->getOperand(1).setImm(NewImm);
2748 
2749  // If we're not using the GPR result of the CR-setting instruction, we
2750  // just need to and with zero/non-zero depending on the new immediate.
2751  else if (MRI->use_empty(MI.getOperand(0).getReg())) {
2752  if (NewImm) {
2753  assert(Immediate && "Transformation converted zero to non-zero?");
2754  NewImm = Immediate;
2755  }
2756  }
2757  else if (ImmChanged)
2758  return false;
2759  }
2760  }
2761 
2762  LLVM_DEBUG(dbgs() << "Replacing instruction:\n");
2763  LLVM_DEBUG(MI.dump());
2764  LLVM_DEBUG(dbgs() << "Fed by:\n");
2765  LLVM_DEBUG(DefMI->dump());
2766  LoadImmediateInfo LII;
2767  LII.Imm = NewImm;
2768  LII.Is64Bit = Is64BitLI;
2769  LII.SetCR = SetCR;
2770  // If we're setting the CR, the original load-immediate must be kept (as an
2771  // operand to ANDIo/ANDI8o).
2772  if (KilledDef && SetCR)
2773  *KilledDef = nullptr;
2774  replaceInstrWithLI(MI, LII);
2775 
2776  // Fixup killed/dead flag after transformation.
2777  // Pattern:
2778  // ForwardingOperandReg = LI imm1
2779  // y = op2 imm2, ForwardingOperandReg(killed)
2780  if (IsForwardingOperandKilled)
2781  fixupIsDeadOrKill(*DefMI, MI, ForwardingOperandReg);
2782 
2783  LLVM_DEBUG(dbgs() << "With:\n");
2784  LLVM_DEBUG(MI.dump());
2785  return true;
2786  }
2787  return false;
2788 }
2789 
2790 bool PPCInstrInfo::instrHasImmForm(unsigned Opc, bool IsVFReg,
2791  ImmInstrInfo &III, bool PostRA) const {
2792  // The vast majority of the instructions would need their operand 2 replaced
2793  // with an immediate when switching to the reg+imm form. A marked exception
2794  // are the update form loads/stores for which a constant operand 2 would need
2795  // to turn into a displacement and move operand 1 to the operand 2 position.
2796  III.ImmOpNo = 2;
2797  III.OpNoForForwarding = 2;
2798  III.ImmWidth = 16;
2799  III.ImmMustBeMultipleOf = 1;
2800  III.TruncateImmTo = 0;
2801  III.IsSummingOperands = false;
2802  switch (Opc) {
2803  default: return false;
2804  case PPC::ADD4:
2805  case PPC::ADD8:
2806  III.SignedImm = true;
2807  III.ZeroIsSpecialOrig = 0;
2808  III.ZeroIsSpecialNew = 1;
2809  III.IsCommutative = true;
2810  III.IsSummingOperands = true;
2811  III.ImmOpcode = Opc == PPC::ADD4 ? PPC::ADDI : PPC::ADDI8;
2812  break;
2813  case PPC::ADDC:
2814  case PPC::ADDC8:
2815  III.SignedImm = true;
2816  III.ZeroIsSpecialOrig = 0;
2817  III.ZeroIsSpecialNew = 0;
2818  III.IsCommutative = true;
2819  III.IsSummingOperands = true;
2820  III.ImmOpcode = Opc == PPC::ADDC ? PPC::ADDIC : PPC::ADDIC8;
2821  break;
2822  case PPC::ADDCo:
2823  III.SignedImm = true;
2824  III.ZeroIsSpecialOrig = 0;
2825  III.ZeroIsSpecialNew = 0;
2826  III.IsCommutative = true;
2827  III.IsSummingOperands = true;
2828  III.ImmOpcode = PPC::ADDICo;
2829  break;
2830  case PPC::SUBFC:
2831  case PPC::SUBFC8:
2832  III.SignedImm = true;
2833  III.ZeroIsSpecialOrig = 0;
2834  III.ZeroIsSpecialNew = 0;
2835  III.IsCommutative = false;
2836  III.ImmOpcode = Opc == PPC::SUBFC ? PPC::SUBFIC : PPC::SUBFIC8;
2837  break;
2838  case PPC::CMPW:
2839  case PPC::CMPD:
2840  III.SignedImm = true;
2841  III.ZeroIsSpecialOrig = 0;
2842  III.ZeroIsSpecialNew = 0;
2843  III.IsCommutative = false;
2844  III.ImmOpcode = Opc == PPC::CMPW ? PPC::CMPWI : PPC::CMPDI;
2845  break;
2846  case PPC::CMPLW:
2847  case PPC::CMPLD:
2848  III.SignedImm = false;
2849  III.ZeroIsSpecialOrig = 0;
2850  III.ZeroIsSpecialNew = 0;
2851  III.IsCommutative = false;
2852  III.ImmOpcode = Opc == PPC::CMPLW ? PPC::CMPLWI : PPC::CMPLDI;
2853  break;
2854  case PPC::ANDo:
2855  case PPC::AND8o:
2856  case PPC::OR:
2857  case PPC::OR8:
2858  case PPC::XOR:
2859  case PPC::XOR8:
2860  III.SignedImm = false;
2861  III.ZeroIsSpecialOrig = 0;
2862  III.ZeroIsSpecialNew = 0;
2863  III.IsCommutative = true;
2864  switch(Opc) {
2865  default: llvm_unreachable("Unknown opcode");
2866  case PPC::ANDo: III.ImmOpcode = PPC::ANDIo; break;
2867  case PPC::AND8o: III.ImmOpcode = PPC::ANDIo8; break;
2868  case PPC::OR: III.ImmOpcode = PPC::ORI; break;
2869  case PPC::OR8: III.ImmOpcode = PPC::ORI8; break;
2870  case PPC::XOR: III.ImmOpcode = PPC::XORI; break;
2871  case PPC::XOR8: III.ImmOpcode = PPC::XORI8; break;
2872  }
2873  break;
2874  case PPC::RLWNM:
2875  case PPC::RLWNM8:
2876  case PPC::RLWNMo:
2877  case PPC::RLWNM8o:
2878  case PPC::SLW:
2879  case PPC::SLW8:
2880  case PPC::SLWo:
2881  case PPC::SLW8o:
2882  case PPC::SRW:
2883  case PPC::SRW8:
2884  case PPC::SRWo:
2885  case PPC::SRW8o:
2886  case PPC::SRAW:
2887  case PPC::SRAWo:
2888  III.SignedImm = false;
2889  III.ZeroIsSpecialOrig = 0;
2890  III.ZeroIsSpecialNew = 0;
2891  III.IsCommutative = false;
2892  // This isn't actually true, but the instructions ignore any of the
2893  // upper bits, so any immediate loaded with an LI is acceptable.
2894  // This does not apply to shift right algebraic because a value
2895  // out of range will produce a -1/0.
2896  III.ImmWidth = 16;
2897  if (Opc == PPC::RLWNM || Opc == PPC::RLWNM8 ||
2898  Opc == PPC::RLWNMo || Opc == PPC::RLWNM8o)
2899  III.TruncateImmTo = 5;
2900  else
2901  III.TruncateImmTo = 6;
2902  switch(Opc) {
2903  default: llvm_unreachable("Unknown opcode");
2904  case PPC::RLWNM: III.ImmOpcode = PPC::RLWINM; break;
2905  case PPC::RLWNM8: III.ImmOpcode = PPC::RLWINM8; break;
2906  case PPC::RLWNMo: III.ImmOpcode = PPC::RLWINMo; break;
2907  case PPC::RLWNM8o: III.ImmOpcode = PPC::RLWINM8o; break;
2908  case PPC::SLW: III.ImmOpcode = PPC::RLWINM; break;
2909  case PPC::SLW8: III.ImmOpcode = PPC::RLWINM8; break;
2910  case PPC::SLWo: III.ImmOpcode = PPC::RLWINMo; break;
2911  case PPC::SLW8o: III.ImmOpcode = PPC::RLWINM8o; break;
2912  case PPC::SRW: III.ImmOpcode = PPC::RLWINM; break;
2913  case PPC::SRW8: III.ImmOpcode = PPC::RLWINM8; break;
2914  case PPC::SRWo: III.ImmOpcode = PPC::RLWINMo; break;
2915  case PPC::SRW8o: III.ImmOpcode = PPC::RLWINM8o; break;
2916  case PPC::SRAW:
2917  III.ImmWidth = 5;
2918  III.TruncateImmTo = 0;
2919  III.ImmOpcode = PPC::SRAWI;
2920  break;
2921  case PPC::SRAWo:
2922  III.ImmWidth = 5;
2923  III.TruncateImmTo = 0;
2924  III.ImmOpcode = PPC::SRAWIo;
2925  break;
2926  }
2927  break;
2928  case PPC::RLDCL:
2929  case PPC::RLDCLo:
2930  case PPC::RLDCR:
2931  case PPC::RLDCRo:
2932  case PPC::SLD:
2933  case PPC::SLDo:
2934  case PPC::SRD:
2935  case PPC::SRDo:
2936  case PPC::SRAD:
2937  case PPC::SRADo:
2938  III.SignedImm = false;
2939  III.ZeroIsSpecialOrig = 0;
2940  III.ZeroIsSpecialNew = 0;
2941  III.IsCommutative = false;
2942  // This isn't actually true, but the instructions ignore any of the
2943  // upper bits, so any immediate loaded with an LI is acceptable.
2944  // This does not apply to shift right algebraic because a value
2945  // out of range will produce a -1/0.
2946  III.ImmWidth = 16;
2947  if (Opc == PPC::RLDCL || Opc == PPC::RLDCLo ||
2948  Opc == PPC::RLDCR || Opc == PPC::RLDCRo)
2949  III.TruncateImmTo = 6;
2950  else
2951  III.TruncateImmTo = 7;
2952  switch(Opc) {
2953  default: llvm_unreachable("Unknown opcode");
2954  case PPC::RLDCL: III.ImmOpcode = PPC::RLDICL; break;
2955  case PPC::RLDCLo: III.ImmOpcode = PPC::RLDICLo; break;
2956  case PPC::RLDCR: III.ImmOpcode = PPC::RLDICR; break;
2957  case PPC::RLDCRo: III.ImmOpcode = PPC::RLDICRo; break;
2958  case PPC::SLD: III.ImmOpcode = PPC::RLDICR; break;
2959  case PPC::SLDo: III.ImmOpcode = PPC::RLDICRo; break;
2960  case PPC::SRD: III.ImmOpcode = PPC::RLDICL; break;
2961  case PPC::SRDo: III.ImmOpcode = PPC::RLDICLo; break;
2962  case PPC::SRAD:
2963  III.ImmWidth = 6;
2964  III.TruncateImmTo = 0;
2965  III.ImmOpcode = PPC::SRADI;
2966  break;
2967  case PPC::SRADo:
2968  III.ImmWidth = 6;
2969  III.TruncateImmTo = 0;
2970  III.ImmOpcode = PPC::SRADIo;
2971  break;
2972  }
2973  break;
2974  // Loads and stores:
2975  case PPC::LBZX:
2976  case PPC::LBZX8:
2977  case PPC::LHZX:
2978  case PPC::LHZX8:
2979  case PPC::LHAX:
2980  case PPC::LHAX8:
2981  case PPC::LWZX:
2982  case PPC::LWZX8:
2983  case PPC::LWAX:
2984  case PPC::LDX:
2985  case PPC::LFSX:
2986  case PPC::LFDX:
2987  case PPC::STBX:
2988  case PPC::STBX8:
2989  case PPC::STHX:
2990  case PPC::STHX8:
2991  case PPC::STWX:
2992  case PPC::STWX8:
2993  case PPC::STDX:
2994  case PPC::STFSX:
2995  case PPC::STFDX:
2996  III.SignedImm = true;
2997  III.ZeroIsSpecialOrig = 1;
2998  III.ZeroIsSpecialNew = 2;
2999  III.IsCommutative = true;
3000  III.IsSummingOperands = true;
3001  III.ImmOpNo = 1;
3002  III.OpNoForForwarding = 2;
3003  switch(Opc) {
3004  default: llvm_unreachable("Unknown opcode");
3005  case PPC::LBZX: III.ImmOpcode = PPC::LBZ; break;
3006  case PPC::LBZX8: III.ImmOpcode = PPC::LBZ8; break;
3007  case PPC::LHZX: III.ImmOpcode = PPC::LHZ; break;
3008  case PPC::LHZX8: III.ImmOpcode = PPC::LHZ8; break;
3009  case PPC::LHAX: III.ImmOpcode = PPC::LHA; break;
3010  case PPC::LHAX8: III.ImmOpcode = PPC::LHA8; break;
3011  case PPC::LWZX: III.ImmOpcode = PPC::LWZ; break;
3012  case PPC::LWZX8: III.ImmOpcode = PPC::LWZ8; break;
3013  case PPC::LWAX:
3014  III.ImmOpcode = PPC::LWA;
3015  III.ImmMustBeMultipleOf = 4;
3016  break;
3017  case PPC::LDX: III.ImmOpcode = PPC::LD; III.ImmMustBeMultipleOf = 4; break;
3018  case PPC::LFSX: III.ImmOpcode = PPC::LFS; break;
3019  case PPC::LFDX: III.ImmOpcode = PPC::LFD; break;
3020  case PPC::STBX: III.ImmOpcode = PPC::STB; break;
3021  case PPC::STBX8: III.ImmOpcode = PPC::STB8; break;
3022  case PPC::STHX: III.ImmOpcode = PPC::STH; break;
3023  case PPC::STHX8: III.ImmOpcode = PPC::STH8; break;
3024  case PPC::STWX: III.ImmOpcode = PPC::STW; break;
3025  case PPC::STWX8: III.ImmOpcode = PPC::STW8; break;
3026  case PPC::STDX:
3027  III.ImmOpcode = PPC::STD;
3028  III.ImmMustBeMultipleOf = 4;
3029  break;
3030  case PPC::STFSX: III.ImmOpcode = PPC::STFS; break;
3031  case PPC::STFDX: III.ImmOpcode = PPC::STFD; break;
3032  }
3033  break;
3034  case PPC::LBZUX:
3035  case PPC::LBZUX8:
3036  case PPC::LHZUX:
3037  case PPC::LHZUX8:
3038  case PPC::LHAUX:
3039  case PPC::LHAUX8:
3040  case PPC::LWZUX:
3041  case PPC::LWZUX8:
3042  case PPC::LDUX:
3043  case PPC::LFSUX:
3044  case PPC::LFDUX:
3045  case PPC::STBUX:
3046  case PPC::STBUX8:
3047  case PPC::STHUX:
3048  case PPC::STHUX8:
3049  case PPC::STWUX:
3050  case PPC::STWUX8:
3051  case PPC::STDUX:
3052  case PPC::STFSUX:
3053  case PPC::STFDUX:
3054  III.SignedImm = true;
3055  III.ZeroIsSpecialOrig = 2;
3056  III.ZeroIsSpecialNew = 3;
3057  III.IsCommutative = false;
3058  III.IsSummingOperands = true;
3059  III.ImmOpNo = 2;
3060  III.OpNoForForwarding = 3;
3061  switch(Opc) {
3062  default: llvm_unreachable("Unknown opcode");
3063  case PPC::LBZUX: III.ImmOpcode = PPC::LBZU; break;
3064  case PPC::LBZUX8: III.ImmOpcode = PPC::LBZU8; break;
3065  case PPC::LHZUX: III.ImmOpcode = PPC::LHZU; break;
3066  case PPC::LHZUX8: III.ImmOpcode = PPC::LHZU8; break;
3067  case PPC::LHAUX: III.ImmOpcode = PPC::LHAU; break;
3068  case PPC::LHAUX8: III.ImmOpcode = PPC::LHAU8; break;
3069  case PPC::LWZUX: III.ImmOpcode = PPC::LWZU; break;
3070  case PPC::LWZUX8: III.ImmOpcode = PPC::LWZU8; break;
3071  case PPC::LDUX:
3072  III.ImmOpcode = PPC::LDU;
3073  III.ImmMustBeMultipleOf = 4;
3074  break;
3075  case PPC::LFSUX: III.ImmOpcode = PPC::LFSU; break;
3076  case PPC::LFDUX: III.ImmOpcode = PPC::LFDU; break;
3077  case PPC::STBUX: III.ImmOpcode = PPC::STBU; break;
3078  case PPC::STBUX8: III.ImmOpcode = PPC::STBU8; break;
3079  case PPC::STHUX: III.ImmOpcode = PPC::STHU; break;
3080  case PPC::STHUX8: III.ImmOpcode = PPC::STHU8; break;
3081  case PPC::STWUX: III.ImmOpcode = PPC::STWU; break;
3082  case PPC::STWUX8: III.ImmOpcode = PPC::STWU8; break;
3083  case PPC::STDUX:
3084  III.ImmOpcode = PPC::STDU;
3085  III.ImmMustBeMultipleOf = 4;
3086  break;
3087  case PPC::STFSUX: III.ImmOpcode = PPC::STFSU; break;
3088  case PPC::STFDUX: III.ImmOpcode = PPC::STFDU; break;
3089  }
3090  break;
3091  // Power9 and up only. For some of these, the X-Form version has access to all
3092  // 64 VSR's whereas the D-Form only has access to the VR's. We replace those
3093  // with pseudo-ops pre-ra and for post-ra, we check that the register loaded
3094  // into or stored from is one of the VR registers.
3095  case PPC::LXVX:
3096  case PPC::LXSSPX:
3097  case PPC::LXSDX:
3098  case PPC::STXVX:
3099  case PPC::STXSSPX:
3100  case PPC::STXSDX:
3101  case PPC::XFLOADf32:
3102  case PPC::XFLOADf64:
3103  case PPC::XFSTOREf32:
3104  case PPC::XFSTOREf64:
3105  if (!Subtarget.hasP9Vector())
3106  return false;
3107  III.SignedImm = true;
3108  III.ZeroIsSpecialOrig = 1;
3109  III.ZeroIsSpecialNew = 2;
3110  III.IsCommutative = true;
3111  III.IsSummingOperands = true;
3112  III.ImmOpNo = 1;
3113  III.OpNoForForwarding = 2;
3114  III.ImmMustBeMultipleOf = 4;
3115  switch(Opc) {
3116  default: llvm_unreachable("Unknown opcode");
3117  case PPC::LXVX:
3118  III.ImmOpcode = PPC::LXV;
3119  III.ImmMustBeMultipleOf = 16;
3120  break;
3121  case PPC::LXSSPX:
3122  if (PostRA) {
3123  if (IsVFReg)
3124  III.ImmOpcode = PPC::LXSSP;
3125  else {
3126  III.ImmOpcode = PPC::LFS;
3127  III.ImmMustBeMultipleOf = 1;
3128  }
3129  break;
3130  }
3132  case PPC::XFLOADf32:
3133  III.ImmOpcode = PPC::DFLOADf32;
3134  break;
3135  case PPC::LXSDX:
3136  if (PostRA) {
3137  if (IsVFReg)
3138  III.ImmOpcode = PPC::LXSD;
3139  else {
3140  III.ImmOpcode = PPC::LFD;
3141  III.ImmMustBeMultipleOf = 1;
3142  }
3143  break;
3144  }
3146  case PPC::XFLOADf64:
3147  III.ImmOpcode = PPC::DFLOADf64;
3148  break;
3149  case PPC::STXVX:
3150  III.ImmOpcode = PPC::STXV;
3151  III.ImmMustBeMultipleOf = 16;
3152  break;
3153  case PPC::STXSSPX:
3154  if (PostRA) {
3155  if (IsVFReg)
3156  III.ImmOpcode = PPC::STXSSP;
3157  else {
3158  III.ImmOpcode = PPC::STFS;
3159  III.ImmMustBeMultipleOf = 1;
3160  }
3161  break;
3162  }
3164  case PPC::XFSTOREf32:
3165  III.ImmOpcode = PPC::DFSTOREf32;
3166  break;
3167  case PPC::STXSDX:
3168  if (PostRA) {
3169  if (IsVFReg)
3170  III.ImmOpcode = PPC::STXSD;
3171  else {
3172  III.ImmOpcode = PPC::STFD;
3173  III.ImmMustBeMultipleOf = 1;
3174  }
3175  break;
3176  }
3178  case PPC::XFSTOREf64:
3179  III.ImmOpcode = PPC::DFSTOREf64;
3180  break;
3181  }
3182  break;
3183  }
3184  return true;
3185 }
3186 
3187 // Utility function for swaping two arbitrary operands of an instruction.
3188 static void swapMIOperands(MachineInstr &MI, unsigned Op1, unsigned Op2) {
3189  assert(Op1 != Op2 && "Cannot swap operand with itself.");
3190 
3191  unsigned MaxOp = std::max(Op1, Op2);
3192  unsigned MinOp = std::min(Op1, Op2);
3193  MachineOperand MOp1 = MI.getOperand(MinOp);
3194  MachineOperand MOp2 = MI.getOperand(MaxOp);
3195  MI.RemoveOperand(std::max(Op1, Op2));
3196  MI.RemoveOperand(std::min(Op1, Op2));
3197 
3198  // If the operands we are swapping are the two at the end (the common case)
3199  // we can just remove both and add them in the opposite order.
3200  if (MaxOp - MinOp == 1 && MI.getNumOperands() == MinOp) {
3201  MI.addOperand(MOp2);
3202  MI.addOperand(MOp1);
3203  } else {
3204  // Store all operands in a temporary vector, remove them and re-add in the
3205  // right order.
3207  unsigned TotalOps = MI.getNumOperands() + 2; // We've already removed 2 ops.
3208  for (unsigned i = MI.getNumOperands() - 1; i >= MinOp; i--) {
3209  MOps.push_back(MI.getOperand(i));
3210  MI.RemoveOperand(i);
3211  }
3212  // MOp2 needs to be added next.
3213  MI.addOperand(MOp2);
3214  // Now add the rest.
3215  for (unsigned i = MI.getNumOperands(); i < TotalOps; i++) {
3216  if (i == MaxOp)
3217  MI.addOperand(MOp1);
3218  else {
3219  MI.addOperand(MOps.back());
3220  MOps.pop_back();
3221  }
3222  }
3223  }
3224 }
3225 
3226 // Check if the 'MI' that has the index OpNoForForwarding
3227 // meets the requirement described in the ImmInstrInfo.
3228 bool PPCInstrInfo::isUseMIElgibleForForwarding(MachineInstr &MI,
3229  const ImmInstrInfo &III,
3230  unsigned OpNoForForwarding
3231  ) const {
3232  // As the algorithm of checking for PPC::ZERO/PPC::ZERO8
3233  // would not work pre-RA, we can only do the check post RA.
3235  if (MRI.isSSA())
3236  return false;
3237 
3238  // Cannot do the transform if MI isn't summing the operands.
3239  if (!III.IsSummingOperands)
3240  return false;
3241 
3242  // The instruction we are trying to replace must have the ZeroIsSpecialOrig set.
3243  if (!III.ZeroIsSpecialOrig)
3244  return false;
3245 
3246  // We cannot do the transform if the operand we are trying to replace
3247  // isn't the same as the operand the instruction allows.
3248  if (OpNoForForwarding != III.OpNoForForwarding)
3249  return false;
3250 
3251  // Check if the instruction we are trying to transform really has
3252  // the special zero register as its operand.
3253  if (MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO &&
3254  MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO8)
3255  return false;
3256 
3257  // This machine instruction is convertible if it is,
3258  // 1. summing the operands.
3259  // 2. one of the operands is special zero register.
3260  // 3. the operand we are trying to replace is allowed by the MI.
3261  return true;
3262 }
3263 
3264 // Check if the DefMI is the add inst and set the ImmMO and RegMO
3265 // accordingly.
3266 bool PPCInstrInfo::isDefMIElgibleForForwarding(MachineInstr &DefMI,
3267  const ImmInstrInfo &III,
3268  MachineOperand *&ImmMO,
3269  MachineOperand *&RegMO) const {
3270  unsigned Opc = DefMI.getOpcode();
3271  if (Opc != PPC::ADDItocL && Opc != PPC::ADDI && Opc != PPC::ADDI8)
3272  return false;
3273 
3274  assert(DefMI.getNumOperands() >= 3 &&
3275  "Add inst must have at least three operands");
3276  RegMO = &DefMI.getOperand(1);
3277  ImmMO = &DefMI.getOperand(2);
3278 
3279  // This DefMI is elgible for forwarding if it is:
3280  // 1. add inst
3281  // 2. one of the operands is Imm/CPI/Global.
3282  return isAnImmediateOperand(*ImmMO);
3283 }
3284 
3285 bool PPCInstrInfo::isRegElgibleForForwarding(
3286  const MachineOperand &RegMO, const MachineInstr &DefMI,
3287  const MachineInstr &MI, bool KillDefMI,
3288  bool &IsFwdFeederRegKilled) const {
3289  // x = addi y, imm
3290  // ...
3291  // z = lfdx 0, x -> z = lfd imm(y)
3292  // The Reg "y" can be forwarded to the MI(z) only when there is no DEF
3293  // of "y" between the DEF of "x" and "z".
3294  // The query is only valid post RA.
3296  if (MRI.isSSA())
3297  return false;
3298 
3299  Register Reg = RegMO.getReg();
3300 
3301  // Walking the inst in reverse(MI-->DefMI) to get the last DEF of the Reg.
3304  It++;
3305  for (; It != E; ++It) {
3306  if (It->modifiesRegister(Reg, &getRegisterInfo()) && (&*It) != &DefMI)
3307  return false;
3308  else if (It->killsRegister(Reg, &getRegisterInfo()) && (&*It) != &DefMI)
3309  IsFwdFeederRegKilled = true;
3310  // Made it to DefMI without encountering a clobber.
3311  if ((&*It) == &DefMI)
3312  break;
3313  }
3314  assert((&*It) == &DefMI && "DefMI is missing");
3315 
3316  // If DefMI also defines the register to be forwarded, we can only forward it
3317  // if DefMI is being erased.
3318  if (DefMI.modifiesRegister(Reg, &getRegisterInfo()))
3319  return KillDefMI;
3320 
3321  return true;
3322 }
3323 
3324 bool PPCInstrInfo::isImmElgibleForForwarding(const MachineOperand &ImmMO,
3325  const MachineInstr &DefMI,
3326  const ImmInstrInfo &III,
3327  int64_t &Imm) const {
3328  assert(isAnImmediateOperand(ImmMO) && "ImmMO is NOT an immediate");
3329  if (DefMI.getOpcode() == PPC::ADDItocL) {
3330  // The operand for ADDItocL is CPI, which isn't imm at compiling time,
3331  // However, we know that, it is 16-bit width, and has the alignment of 4.
3332  // Check if the instruction met the requirement.
3333  if (III.ImmMustBeMultipleOf > 4 ||
3334  III.TruncateImmTo || III.ImmWidth != 16)
3335  return false;
3336 
3337  // Going from XForm to DForm loads means that the displacement needs to be
3338  // not just an immediate but also a multiple of 4, or 16 depending on the
3339  // load. A DForm load cannot be represented if it is a multiple of say 2.
3340  // XForm loads do not have this restriction.
3341  if (ImmMO.isGlobal() &&
3342  ImmMO.getGlobal()->getAlignment() < III.ImmMustBeMultipleOf)
3343  return false;
3344 
3345  return true;
3346  }
3347 
3348  if (ImmMO.isImm()) {
3349  // It is Imm, we need to check if the Imm fit the range.
3350  int64_t Immediate = ImmMO.getImm();
3351  // Sign-extend to 64-bits.
3352  Imm = ((uint64_t)Immediate & ~0x7FFFuLL) != 0 ?
3353  (Immediate | 0xFFFFFFFFFFFF0000) : Immediate;
3354 
3355  if (Imm % III.ImmMustBeMultipleOf)
3356  return false;
3357  if (III.TruncateImmTo)
3358  Imm &= ((1 << III.TruncateImmTo) - 1);
3359  if (III.SignedImm) {
3360  APInt ActualValue(64, Imm, true);
3361  if (!ActualValue.isSignedIntN(III.ImmWidth))
3362  return false;
3363  } else {
3364  uint64_t UnsignedMax = (1 << III.ImmWidth) - 1;
3365  if ((uint64_t)Imm > UnsignedMax)
3366  return false;
3367  }
3368  }
3369  else
3370  return false;
3371 
3372  // This ImmMO is forwarded if it meets the requriement describle
3373  // in ImmInstrInfo
3374  return true;
3375 }
3376 
3377 // If an X-Form instruction is fed by an add-immediate and one of its operands
3378 // is the literal zero, attempt to forward the source of the add-immediate to
3379 // the corresponding D-Form instruction with the displacement coming from
3380 // the immediate being added.
3381 bool PPCInstrInfo::transformToImmFormFedByAdd(
3382  MachineInstr &MI, const ImmInstrInfo &III, unsigned OpNoForForwarding,
3383  MachineInstr &DefMI, bool KillDefMI) const {
3384  // RegMO ImmMO
3385  // | |
3386  // x = addi reg, imm <----- DefMI
3387  // y = op 0 , x <----- MI
3388  // |
3389  // OpNoForForwarding
3390  // Check if the MI meet the requirement described in the III.
3391  if (!isUseMIElgibleForForwarding(MI, III, OpNoForForwarding))
3392  return false;
3393 
3394  // Check if the DefMI meet the requirement
3395  // described in the III. If yes, set the ImmMO and RegMO accordingly.
3396  MachineOperand *ImmMO = nullptr;
3397  MachineOperand *RegMO = nullptr;
3398  if (!isDefMIElgibleForForwarding(DefMI, III, ImmMO, RegMO))
3399  return false;
3400  assert(ImmMO && RegMO && "Imm and Reg operand must have been set");
3401 
3402  // As we get the Imm operand now, we need to check if the ImmMO meet
3403  // the requirement described in the III. If yes set the Imm.
3404  int64_t Imm = 0;
3405  if (!isImmElgibleForForwarding(*ImmMO, DefMI, III, Imm))
3406  return false;
3407 
3408  bool IsFwdFeederRegKilled = false;
3409  // Check if the RegMO can be forwarded to MI.
3410  if (!isRegElgibleForForwarding(*RegMO, DefMI, MI, KillDefMI,
3411  IsFwdFeederRegKilled))
3412  return false;
3413 
3414  // Get killed info in case fixup needed after transformation.
3415  unsigned ForwardKilledOperandReg = ~0U;
3417  bool PostRA = !MRI.isSSA();
3418  if (PostRA && MI.getOperand(OpNoForForwarding).isKill())
3419  ForwardKilledOperandReg = MI.getOperand(OpNoForForwarding).getReg();
3420 
3421  // We know that, the MI and DefMI both meet the pattern, and
3422  // the Imm also meet the requirement with the new Imm-form.
3423  // It is safe to do the transformation now.
3424  LLVM_DEBUG(dbgs() << "Replacing instruction:\n");
3425  LLVM_DEBUG(MI.dump());
3426  LLVM_DEBUG(dbgs() << "Fed by:\n");
3427  LLVM_DEBUG(DefMI.dump());
3428 
3429  // Update the base reg first.
3431  false, false,
3432  RegMO->isKill());
3433 
3434  // Then, update the imm.
3435  if (ImmMO->isImm()) {
3436  // If the ImmMO is Imm, change the operand that has ZERO to that Imm
3437  // directly.
3439  }
3440  else {
3441  // Otherwise, it is Constant Pool Index(CPI) or Global,
3442  // which is relocation in fact. We need to replace the special zero
3443  // register with ImmMO.
3444  // Before that, we need to fixup the target flags for imm.
3445  // For some reason, we miss to set the flag for the ImmMO if it is CPI.
3446  if (DefMI.getOpcode() == PPC::ADDItocL)
3448 
3449  // MI didn't have the interface such as MI.setOperand(i) though
3450  // it has MI.getOperand(i). To repalce the ZERO MachineOperand with
3451  // ImmMO, we need to remove ZERO operand and all the operands behind it,
3452  // and, add the ImmMO, then, move back all the operands behind ZERO.
3454  for (unsigned i = MI.getNumOperands() - 1; i >= III.ZeroIsSpecialOrig; i--) {
3455  MOps.push_back(MI.getOperand(i));
3456  MI.RemoveOperand(i);
3457  }
3458 
3459  // Remove the last MO in the list, which is ZERO operand in fact.
3460  MOps.pop_back();
3461  // Add the imm operand.
3462  MI.addOperand(*ImmMO);
3463  // Now add the rest back.
3464  for (auto &MO : MOps)
3465  MI.addOperand(MO);
3466  }
3467 
3468  // Update the opcode.
3469  MI.setDesc(get(III.ImmOpcode));
3470 
3471  // Fix up killed/dead flag after transformation.
3472  // Pattern 1:
3473  // x = ADD KilledFwdFeederReg, imm
3474  // n = opn KilledFwdFeederReg(killed), regn
3475  // y = XOP 0, x
3476  // Pattern 2:
3477  // x = ADD reg(killed), imm
3478  // y = XOP 0, x
3479  if (IsFwdFeederRegKilled || RegMO->isKill())
3480  fixupIsDeadOrKill(DefMI, MI, RegMO->getReg());
3481  // Pattern 3:
3482  // ForwardKilledOperandReg = ADD reg, imm
3483  // y = XOP 0, ForwardKilledOperandReg(killed)
3484  if (ForwardKilledOperandReg != ~0U)
3485  fixupIsDeadOrKill(DefMI, MI, ForwardKilledOperandReg);
3486 
3487  LLVM_DEBUG(dbgs() << "With:\n");
3488  LLVM_DEBUG(MI.dump());
3489 
3490  return true;
3491 }
3492 
3493 bool PPCInstrInfo::transformToImmFormFedByLI(MachineInstr &MI,
3494  const ImmInstrInfo &III,
3495  unsigned ConstantOpNo,
3496  MachineInstr &DefMI,
3497  int64_t Imm) const {
3499  bool PostRA = !MRI.isSSA();
3500  // Exit early if we can't convert this.
3501  if ((ConstantOpNo != III.OpNoForForwarding) && !III.IsCommutative)
3502  return false;
3503  if (Imm % III.ImmMustBeMultipleOf)
3504  return false;
3505  if (III.TruncateImmTo)
3506  Imm &= ((1 << III.TruncateImmTo) - 1);
3507  if (III.SignedImm) {
3508  APInt ActualValue(64, Imm, true);
3509  if (!ActualValue.isSignedIntN(III.ImmWidth))
3510  return false;
3511  } else {
3512  uint64_t UnsignedMax = (1 << III.ImmWidth) - 1;
3513  if ((uint64_t)Imm > UnsignedMax)
3514  return false;
3515  }
3516 
3517  // If we're post-RA, the instructions don't agree on whether register zero is
3518  // special, we can transform this as long as the register operand that will
3519  // end up in the location where zero is special isn't R0.
3520  if (PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) {
3521  unsigned PosForOrigZero = III.ZeroIsSpecialOrig ? III.ZeroIsSpecialOrig :
3522  III.ZeroIsSpecialNew + 1;
3523  Register OrigZeroReg = MI.getOperand(PosForOrigZero).getReg();
3524  Register NewZeroReg = MI.getOperand(III.ZeroIsSpecialNew).getReg();
3525  // If R0 is in the operand where zero is special for the new instruction,
3526  // it is unsafe to transform if the constant operand isn't that operand.
3527  if ((NewZeroReg == PPC::R0 || NewZeroReg == PPC::X0) &&
3528  ConstantOpNo != III.ZeroIsSpecialNew)
3529  return false;
3530  if ((OrigZeroReg == PPC::R0 || OrigZeroReg == PPC::X0) &&
3531  ConstantOpNo != PosForOrigZero)
3532  return false;
3533  }
3534 
3535  // Get killed info in case fixup needed after transformation.
3536  unsigned ForwardKilledOperandReg = ~0U;
3537  if (PostRA && MI.getOperand(ConstantOpNo).isKill())
3538  ForwardKilledOperandReg = MI.getOperand(ConstantOpNo).getReg();
3539 
3540  unsigned Opc = MI.getOpcode();
3541  bool SpecialShift32 =
3542  Opc == PPC::SLW || Opc == PPC::SLWo || Opc == PPC::SRW || Opc == PPC::SRWo;
3543  bool SpecialShift64 =
3544  Opc == PPC::SLD || Opc == PPC::SLDo || Opc == PPC::SRD || Opc == PPC::SRDo;
3545  bool SetCR = Opc == PPC::SLWo || Opc == PPC::SRWo ||
3546  Opc == PPC::SLDo || Opc == PPC::SRDo;
3547  bool RightShift =
3548  Opc == PPC::SRW || Opc == PPC::SRWo || Opc == PPC::SRD || Opc == PPC::SRDo;
3549 
3550  MI.setDesc(get(III.ImmOpcode));
3551  if (ConstantOpNo == III.OpNoForForwarding) {
3552  // Converting shifts to immediate form is a bit tricky since they may do
3553  // one of three things:
3554  // 1. If the shift amount is between OpSize and 2*OpSize, the result is zero
3555  // 2. If the shift amount is zero, the result is unchanged (save for maybe
3556  // setting CR0)
3557  // 3. If the shift amount is in [1, OpSize), it's just a shift
3558  if (SpecialShift32 || SpecialShift64) {
3559  LoadImmediateInfo LII;
3560  LII.Imm = 0;
3561  LII.SetCR = SetCR;
3562  LII.Is64Bit = SpecialShift64;
3563  uint64_t ShAmt = Imm & (SpecialShift32 ? 0x1F : 0x3F);
3564  if (Imm & (SpecialShift32 ? 0x20 : 0x40))
3565  replaceInstrWithLI(MI, LII);
3566  // Shifts by zero don't change the value. If we don't need to set CR0,
3567  // just convert this to a COPY. Can't do this post-RA since we've already
3568  // cleaned up the copies.
3569  else if (!SetCR && ShAmt == 0 && !PostRA) {
3570  MI.RemoveOperand(2);
3571  MI.setDesc(get(PPC::COPY));
3572  } else {
3573  // The 32 bit and 64 bit instructions are quite different.
3574  if (SpecialShift32) {
3575  // Left shifts use (N, 0, 31-N).
3576  // Right shifts use (32-N, N, 31) if 0 < N < 32.
3577  // use (0, 0, 31) if N == 0.
3578  uint64_t SH = ShAmt == 0 ? 0 : RightShift ? 32 - ShAmt : ShAmt;
3579  uint64_t MB = RightShift ? ShAmt : 0;
3580  uint64_t ME = RightShift ? 31 : 31 - ShAmt;
3582  MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(MB)
3583  .addImm(ME);
3584  } else {
3585  // Left shifts use (N, 63-N).
3586  // Right shifts use (64-N, N) if 0 < N < 64.
3587  // use (0, 0) if N == 0.
3588  uint64_t SH = ShAmt == 0 ? 0 : RightShift ? 64 - ShAmt : ShAmt;
3589  uint64_t ME = RightShift ? ShAmt : 63 - ShAmt;
3591  MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(ME);
3592  }
3593  }
3594  } else
3595  replaceInstrOperandWithImm(MI, ConstantOpNo, Imm);
3596  }
3597  // Convert commutative instructions (switch the operands and convert the
3598  // desired one to an immediate.
3599  else if (III.IsCommutative) {
3600  replaceInstrOperandWithImm(MI, ConstantOpNo, Imm);
3601  swapMIOperands(MI, ConstantOpNo, III.OpNoForForwarding);
3602  } else
3603  llvm_unreachable("Should have exited early!");
3604 
3605  // For instructions for which the constant register replaces a different
3606  // operand than where the immediate goes, we need to swap them.
3607  if (III.OpNoForForwarding != III.ImmOpNo)
3609 
3610  // If the special R0/X0 register index are different for original instruction
3611  // and new instruction, we need to fix up the register class in new
3612  // instruction.
3613  if (!PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) {
3614  if (III.ZeroIsSpecialNew) {
3615  // If operand at III.ZeroIsSpecialNew is physical reg(eg: ZERO/ZERO8), no
3616  // need to fix up register class.
3617  Register RegToModify = MI.getOperand(III.ZeroIsSpecialNew).getReg();
3618  if (Register::isVirtualRegister(RegToModify)) {
3619  const TargetRegisterClass *NewRC =
3620  MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ?
3621  &PPC::GPRC_and_GPRC_NOR0RegClass : &PPC::G8RC_and_G8RC_NOX0RegClass;
3622  MRI.setRegClass(RegToModify, NewRC);
3623  }
3624  }
3625  }
3626 
3627  // Fix up killed/dead flag after transformation.
3628  // Pattern:
3629  // ForwardKilledOperandReg = LI imm
3630  // y = XOP reg, ForwardKilledOperandReg(killed)
3631  if (ForwardKilledOperandReg != ~0U)
3632  fixupIsDeadOrKill(DefMI, MI, ForwardKilledOperandReg);
3633  return true;
3634 }
3635 
3636 const TargetRegisterClass *
3638  if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
3639  return &PPC::VSRCRegClass;
3640  return RC;
3641 }
3642 
3644  return PPC::getRecordFormOpcode(Opcode);
3645 }
3646 
3647 // This function returns true if the machine instruction
3648 // always outputs a value by sign-extending a 32 bit value,
3649 // i.e. 0 to 31-th bits are same as 32-th bit.
3650 static bool isSignExtendingOp(const MachineInstr &MI) {
3651  int Opcode = MI.getOpcode();
3652  if (Opcode == PPC::LI || Opcode == PPC::LI8 ||
3653  Opcode == PPC::LIS || Opcode == PPC::LIS8 ||
3654  Opcode == PPC::SRAW || Opcode == PPC::SRAWo ||
3655  Opcode == PPC::SRAWI || Opcode == PPC::SRAWIo ||
3656  Opcode == PPC::LWA || Opcode == PPC::LWAX ||
3657  Opcode == PPC::LWA_32 || Opcode == PPC::LWAX_32 ||
3658  Opcode == PPC::LHA || Opcode == PPC::LHAX ||
3659  Opcode == PPC::LHA8 || Opcode == PPC::LHAX8 ||
3660  Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
3661  Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
3662  Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
3663  Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
3664  Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
3665  Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 ||
3666  Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
3667  Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 ||
3668  Opcode == PPC::EXTSB || Opcode == PPC::EXTSBo ||
3669  Opcode == PPC::EXTSH || Opcode == PPC::EXTSHo ||
3670  Opcode == PPC::EXTSB8 || Opcode == PPC::EXTSH8 ||
3671  Opcode == PPC::EXTSW || Opcode == PPC::EXTSWo ||
3672  Opcode == PPC::SETB || Opcode == PPC::SETB8 ||
3673  Opcode == PPC::EXTSH8_32_64 || Opcode == PPC::EXTSW_32_64 ||
3674  Opcode == PPC::EXTSB8_32_64)
3675  return true;
3676 
3677  if (Opcode == PPC::RLDICL && MI.getOperand(3).getImm() >= 33)
3678  return true;
3679 
3680  if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
3681  Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo) &&
3682  MI.getOperand(3).getImm() > 0 &&
3683  MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
3684  return true;
3685 
3686  return false;
3687 }
3688 
3689 // This function returns true if the machine instruction
3690 // always outputs zeros in higher 32 bits.
3691 static bool isZeroExtendingOp(const MachineInstr &MI) {
3692  int Opcode = MI.getOpcode();
3693  // The 16-bit immediate is sign-extended in li/lis.
3694  // If the most significant bit is zero, all higher bits are zero.
3695  if (Opcode == PPC::LI || Opcode == PPC::LI8 ||
3696  Opcode == PPC::LIS || Opcode == PPC::LIS8) {
3697  int64_t Imm = MI.getOperand(1).getImm();
3698  if (((uint64_t)Imm & ~0x7FFFuLL) == 0)
3699  return true;
3700  }
3701 
3702  // We have some variations of rotate-and-mask instructions
3703  // that clear higher 32-bits.
3704  if ((Opcode == PPC::RLDICL || Opcode == PPC::RLDICLo ||
3705  Opcode == PPC::RLDCL || Opcode == PPC::RLDCLo ||
3706  Opcode == PPC::RLDICL_32_64) &&
3707  MI.getOperand(3).getImm() >= 32)
3708  return true;
3709 
3710  if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDICo) &&
3711  MI.getOperand(3).getImm() >= 32 &&
3712  MI.getOperand(3).getImm() <= 63 - MI.getOperand(2).getImm())
3713  return true;
3714 
3715  if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
3716  Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo ||
3717  Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) &&
3718  MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
3719  return true;
3720 
3721  // There are other instructions that clear higher 32-bits.
3722  if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZWo ||
3723  Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZWo ||
3724  Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8 ||
3725  Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZDo ||
3726  Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZDo ||
3727  Opcode == PPC::POPCNTD || Opcode == PPC::POPCNTW ||
3728  Opcode == PPC::SLW || Opcode == PPC::SLWo ||
3729  Opcode == PPC::SRW || Opcode == PPC::SRWo ||
3730  Opcode == PPC::SLW8 || Opcode == PPC::SRW8 ||
3731  Opcode == PPC::SLWI || Opcode == PPC::SLWIo ||
3732  Opcode == PPC::SRWI || Opcode == PPC::SRWIo ||
3733  Opcode == PPC::LWZ || Opcode == PPC::LWZX ||
3734  Opcode == PPC::LWZU || Opcode == PPC::LWZUX ||
3735  Opcode == PPC::LWBRX || Opcode == PPC::LHBRX ||
3736  Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
3737  Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
3738  Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
3739  Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
3740  Opcode == PPC::LWZ8 || Opcode == PPC::LWZX8 ||
3741  Opcode == PPC::LWZU8 || Opcode == PPC::LWZUX8 ||
3742  Opcode == PPC::LWBRX8 || Opcode == PPC::LHBRX8 ||
3743  Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 ||
3744  Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 ||
3745  Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
3746  Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
3747  Opcode == PPC::ANDIo || Opcode == PPC::ANDISo ||
3748  Opcode == PPC::ROTRWI || Opcode == PPC::ROTRWIo ||
3749  Opcode == PPC::EXTLWI || Opcode == PPC::EXTLWIo ||
3750  Opcode == PPC::MFVSRWZ)
3751  return true;
3752 
3753  return false;
3754 }
3755 
3756 // This function returns true if the input MachineInstr is a TOC save
3757 // instruction.
3759  if (!MI.getOperand(1).isImm() || !MI.getOperand(2).isReg())
3760  return false;
3761  unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
3762  unsigned StackOffset = MI.getOperand(1).getImm();
3763  Register StackReg = MI.getOperand(2).getReg();
3764  if (StackReg == PPC::X1 && StackOffset == TOCSaveOffset)
3765  return true;
3766 
3767  return false;
3768 }
3769 
3770 // We limit the max depth to track incoming values of PHIs or binary ops
3771 // (e.g. AND) to avoid excessive cost.
3772 const unsigned MAX_DEPTH = 1;
3773 
3774 bool
3776  const unsigned Depth) const {
3777  const MachineFunction *MF = MI.getParent()->getParent();
3778  const MachineRegisterInfo *MRI = &MF->getRegInfo();
3779 
3780  // If we know this instruction returns sign- or zero-extended result,
3781  // return true.
3782  if (SignExt ? isSignExtendingOp(MI):
3783  isZeroExtendingOp(MI))
3784  return true;
3785 
3786  switch (MI.getOpcode()) {
3787  case PPC::COPY: {
3788  Register SrcReg = MI.getOperand(1).getReg();
3789 
3790  // In both ELFv1 and v2 ABI, method parameters and the return value
3791  // are sign- or zero-extended.
3792  if (MF->getSubtarget<PPCSubtarget>().isSVR4ABI()) {
3793  const PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
3794  // We check the ZExt/SExt flags for a method parameter.
3795  if (MI.getParent()->getBasicBlock() ==
3796  &MF->getFunction().getEntryBlock()) {
3797  Register VReg = MI.getOperand(0).getReg();
3798  if (MF->getRegInfo().isLiveIn(VReg))
3799  return SignExt ? FuncInfo->isLiveInSExt(VReg) :
3800  FuncInfo->isLiveInZExt(VReg);
3801  }
3802 
3803  // For a method return value, we check the ZExt/SExt flags in attribute.
3804  // We assume the following code sequence for method call.
3805  // ADJCALLSTACKDOWN 32, implicit dead %r1, implicit %r1
3806  // BL8_NOP @func,...
3807  // ADJCALLSTACKUP 32, 0, implicit dead %r1, implicit %r1
3808  // %5 = COPY %x3; G8RC:%5
3809  if (SrcReg == PPC::X3) {
3810  const MachineBasicBlock *MBB = MI.getParent();
3813  if (II != MBB->instr_begin() &&
3814  (--II)->getOpcode() == PPC::ADJCALLSTACKUP) {
3815  const MachineInstr &CallMI = *(--II);
3816  if (CallMI.isCall() && CallMI.getOperand(0).isGlobal()) {
3817  const Function *CalleeFn =
3818  dyn_cast<Function>(CallMI.getOperand(0).getGlobal());
3819  if (!CalleeFn)
3820  return false;
3821  const IntegerType *IntTy =
3822  dyn_cast<IntegerType>(CalleeFn->getReturnType());
3823  const AttributeSet &Attrs =
3824  CalleeFn->getAttributes().getRetAttributes();
3825  if (IntTy && IntTy->getBitWidth() <= 32)
3826  return Attrs.hasAttribute(SignExt ? Attribute::SExt :
3827  Attribute::ZExt);
3828  }
3829  }
3830  }
3831  }
3832 
3833  // If this is a copy from another register, we recursively check source.
3834  if (!Register::isVirtualRegister(SrcReg))
3835  return false;
3836  const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3837  if (SrcMI != NULL)
3838  return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
3839 
3840  return false;
3841  }
3842 
3843  case PPC::ANDIo:
3844  case PPC::ANDISo:
3845  case PPC::ORI:
3846  case PPC::ORIS:
3847  case PPC::XORI:
3848  case PPC::XORIS:
3849  case PPC::ANDIo8:
3850  case PPC::ANDISo8:
3851  case PPC::ORI8:
3852  case PPC::ORIS8:
3853  case PPC::XORI8:
3854  case PPC::XORIS8: {
3855  // logical operation with 16-bit immediate does not change the upper bits.
3856  // So, we track the operand register as we do for register copy.
3857  Register SrcReg = MI.getOperand(1).getReg();
3858  if (!Register::isVirtualRegister(SrcReg))
3859  return false;
3860  const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3861  if (SrcMI != NULL)
3862  return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
3863 
3864  return false;
3865  }
3866 
3867  // If all incoming values are sign-/zero-extended,
3868  // the output of OR, ISEL or PHI is also sign-/zero-extended.
3869  case PPC::OR:
3870  case PPC::OR8:
3871  case PPC::ISEL:
3872  case PPC::PHI: {
3873  if (Depth >= MAX_DEPTH)
3874  return false;
3875 
3876  // The input registers for PHI are operand 1, 3, ...
3877  // The input registers for others are operand 1 and 2.
3878  unsigned E = 3, D = 1;
3879  if (MI.getOpcode() == PPC::PHI) {
3880  E = MI.getNumOperands();
3881  D = 2;
3882  }
3883 
3884  for (unsigned I = 1; I != E; I += D) {
3885  if (MI.getOperand(I).isReg()) {
3886  Register SrcReg = MI.getOperand(I).getReg();
3887  if (!Register::isVirtualRegister(SrcReg))
3888  return false;
3889  const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3890  if (SrcMI == NULL || !isSignOrZeroExtended(*SrcMI, SignExt, Depth+1))
3891  return false;
3892  }
3893  else
3894  return false;
3895  }
3896  return true;
3897  }
3898 
3899  // If at least one of the incoming values of an AND is zero extended
3900  // then the output is also zero-extended. If both of the incoming values
3901  // are sign-extended then the output is also sign extended.
3902  case PPC::AND:
3903  case PPC::AND8: {
3904  if (Depth >= MAX_DEPTH)
3905  return false;
3906 
3907  assert(MI.getOperand(1).isReg() && MI.getOperand(2).isReg());
3908 
3909  Register SrcReg1 = MI.getOperand(1).getReg();
3910  Register SrcReg2 = MI.getOperand(2).getReg();
3911 
3912  if (!Register::isVirtualRegister(SrcReg1) ||
3913  !Register::isVirtualRegister(SrcReg2))
3914  return false;
3915 
3916  const MachineInstr *MISrc1 = MRI->getVRegDef(SrcReg1);
3917  const MachineInstr *MISrc2 = MRI->getVRegDef(SrcReg2);
3918  if (!MISrc1 || !MISrc2)
3919  return false;
3920 
3921  if(SignExt)
3922  return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) &&
3923  isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
3924  else
3925  return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) ||
3926  isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
3927  }
3928 
3929  default:
3930  break;
3931  }
3932  return false;
3933 }
3934 
3935 bool PPCInstrInfo::isBDNZ(unsigned Opcode) const {
3936  return (Opcode == (Subtarget.isPPC64() ? PPC::BDNZ8 : PPC::BDNZ));
3937 }
3938 
3939 namespace {
3940 class PPCPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
3941  MachineInstr *Loop, *EndLoop, *LoopCount;
3942  MachineFunction *MF;
3943  const TargetInstrInfo *TII;
3944  int64_t TripCount;
3945 
3946 public:
3947  PPCPipelinerLoopInfo(MachineInstr *Loop, MachineInstr *EndLoop,
3948  MachineInstr *LoopCount)
3949  : Loop(Loop), EndLoop(EndLoop), LoopCount(LoopCount),
3950  MF(Loop->getParent()->getParent()),
3951  TII(MF->getSubtarget().getInstrInfo()) {
3952  // Inspect the Loop instruction up-front, as it may be deleted when we call
3953  // createTripCountGreaterCondition.
3954  if (LoopCount->getOpcode() == PPC::LI8 || LoopCount->getOpcode() == PPC::LI)
3955  TripCount = LoopCount->getOperand(1).getImm();
3956  else
3957  TripCount = -1;
3958  }
3959 
3960  bool shouldIgnoreForPipelining(const MachineInstr *MI) const override {
3961  // Only ignore the terminator.
3962  return MI == EndLoop;
3963  }
3964 
3966  createTripCountGreaterCondition(int TC, MachineBasicBlock &MBB,
3967  SmallVectorImpl<MachineOperand> &Cond) override {
3968  if (TripCount == -1) {
3969  // Since BDZ/BDZ8 that we will insert will also decrease the ctr by 1,
3970  // so we don't need to generate any thing here.
3973  MF->getSubtarget<PPCSubtarget>().isPPC64() ? PPC::CTR8 : PPC::CTR,
3974  true));
3975  return {};
3976  }
3977 
3978  return TripCount > TC;
3979  }
3980 
3981  void setPreheader(MachineBasicBlock *NewPreheader) override {
3982  // Do nothing. We want the LOOP setup instruction to stay in the *old*
3983  // preheader, so we can use BDZ in the prologs to adapt the loop trip count.
3984  }
3985 
3986  void adjustTripCount(int TripCountAdjust) override {
3987  // If the loop trip count is a compile-time value, then just change the
3988  // value.
3989  if (LoopCount->getOpcode() == PPC::LI8 ||
3990  LoopCount->getOpcode() == PPC::LI) {
3991  int64_t TripCount = LoopCount->getOperand(1).getImm() + TripCountAdjust;
3992  LoopCount->getOperand(1).setImm(TripCount);
3993  return;
3994  }
3995 
3996  // Since BDZ/BDZ8 that we will insert will also decrease the ctr by 1,
3997  // so we don't need to generate any thing here.
3998  }
3999 
4000  void disposed() override {
4001  Loop->eraseFromParent();
4002  // Ensure the loop setup instruction is deleted too.
4003  LoopCount->eraseFromParent();
4004  }
4005 };
4006 } // namespace
4007 
4008 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
4010  // We really "analyze" only hardware loops right now.
4012  MachineBasicBlock *Preheader = *LoopBB->pred_begin();
4013  if (Preheader == LoopBB)
4014  Preheader = *std::next(LoopBB->pred_begin());
4015  MachineFunction *MF = Preheader->getParent();
4016 
4017  if (I != LoopBB->end() && isBDNZ(I->getOpcode())) {
4019  if (MachineInstr *LoopInst = findLoopInstr(*Preheader, Visited)) {
4020  Register LoopCountReg = LoopInst->getOperand(0).getReg();
4021  MachineRegisterInfo &MRI = MF->getRegInfo();
4022  MachineInstr *LoopCount = MRI.getUniqueVRegDef(LoopCountReg);
4023  return std::make_unique<PPCPipelinerLoopInfo>(LoopInst, &*I, LoopCount);
4024  }
4025  }
4026  return nullptr;
4027 }
4028 
4030  MachineBasicBlock &PreHeader,
4031  SmallPtrSet<MachineBasicBlock *, 8> &Visited) const {
4032 
4033  unsigned LOOPi = (Subtarget.isPPC64() ? PPC::MTCTR8loop : PPC::MTCTRloop);
4034 
4035  // The loop set-up instruction should be in preheader
4036  for (auto &I : PreHeader.instrs())
4037  if (I.getOpcode() == LOOPi)
4038  return &I;
4039  return nullptr;
4040 }
4041 
4042 // Return true if get the base operand, byte offset of an instruction and the
4043 // memory width. Width is the size of memory that is being loaded/stored.
4045  const MachineInstr &LdSt,
4046  const MachineOperand *&BaseReg,
4047  int64_t &Offset,
4048  unsigned &Width,
4049  const TargetRegisterInfo *TRI) const {
4050  assert(LdSt.mayLoadOrStore() && "Expected a memory operation.");
4051 
4052  // Handle only loads/stores with base register followed by immediate offset.
4053  if (LdSt.getNumExplicitOperands() != 3)
4054  return false;
4055  if (!LdSt.getOperand(1).isImm() || !LdSt.getOperand(2).isReg())
4056  return false;
4057 
4058  if (!LdSt.hasOneMemOperand())
4059  return false;
4060 
4061  Width = (*LdSt.memoperands_begin())->getSize();
4062  Offset = LdSt.getOperand(1).getImm();
4063  BaseReg = &LdSt.getOperand(2);
4064  return true;
4065 }
4066 
4068  const MachineInstr &MIa, const MachineInstr &MIb) const {
4069  assert(MIa.mayLoadOrStore() && "MIa must be a load or store.");
4070  assert(MIb.mayLoadOrStore() && "MIb must be a load or store.");
4071 
4072  if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
4074  return false;
4075 
4076  // Retrieve the base register, offset from the base register and width. Width
4077  // is the size of memory that is being loaded/stored (e.g. 1, 2, 4). If
4078  // base registers are identical, and the offset of a lower memory access +
4079  // the width doesn't overlap the offset of a higher memory access,
4080  // then the memory accesses are different.
4082  const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr;
4083  int64_t OffsetA = 0, OffsetB = 0;
4084  unsigned int WidthA = 0, WidthB = 0;
4085  if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) &&
4086  getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
4087  if (BaseOpA->isIdenticalTo(*BaseOpB)) {
4088  int LowOffset = std::min(OffsetA, OffsetB);
4089  int HighOffset = std::max(OffsetA, OffsetB);
4090  int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
4091  if (LowOffset + LowWidth <= HighOffset)
4092  return true;
4093  }
4094  }
4095  return false;
4096 }
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const
instr_iterator instr_begin()
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
StackOffset is a wrapper around scalable and non-scalable offsets and is used in several functions su...
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:656
int getNonRecordFormOpcode(uint16_t)
MachineBasicBlock * getMBB() const
Object returned by analyzeLoopForPipelining.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
uint64_t ZeroIsSpecialNew
Definition: PPCInstrInfo.h:86
void setTargetFlags(unsigned F)
iterator begin() const
begin/end - Return all of the registers in this class.
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:222
bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III, bool PostRA) const
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:384
MachineInstr * findLoopInstr(MachineBasicBlock &PreHeader, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const
Find the hardware loop instruction used to set-up the specified loop.
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:548
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:179
static int getRecordFormOpcode(unsigned Opcode)
unsigned Reg
unsigned getSubReg() const
bool hasVSX() const
Definition: PPCSubtarget.h:252
static cl::opt< bool > DisableCmpOpt("disable-ppc-cmp-opt", cl::desc("Disable compare instruction optimization"), cl::Hidden)
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
Return true if get the base operand, byte offset of an instruction and the memory width...
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
uint64_t IsCommutative
Definition: PPCInstrInfo.h:88
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
Definition: MachineInstr.h:853
uint64_t TruncateImmTo
Definition: PPCInstrInfo.h:98
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:342
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
void setIsDead(bool Val=true)
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool isPseudo() const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MCInstrDesc.h:262
CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
#define R2(n)
uint64_t OpNoForForwarding
Definition: PPCInstrInfo.h:90
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
uint64_t IsSummingOperands
Definition: PPCInstrInfo.h:100
bool isSignExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always a sign-extended, i.e.
Definition: PPCInstrInfo.h:413
void clearRegisterDeads(Register Reg)
Clear all dead flags on operands defining register Reg.
return AArch64::GPR64RegClass contains(Reg)
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling th...
MachineFunction & MF
Machine function.
Definition: ScheduleDAG.h:560
bool isXFormMemOp(unsigned Opcode) const
Definition: PPCInstrInfo.h:187
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
PPCDispatchGroupSBHazardRecognizer - This class implements a scoreboard-based hazard recognizer for P...
A description of a memory reference used in the backend.
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:226
const HexagonInstrInfo * TII
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:450
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:413
bool hasDirectMove() const
Definition: PPCSubtarget.h:281
static Optional< unsigned > getOpcode(ArrayRef< VPValue *> Values)
Returns the opcode of Values or ~0 if they do not all agree.
Definition: VPlanSLP.cpp:196
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:672
AttributeSet getRetAttributes() const
The attributes for the ret value are returned.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:410
const TargetRegisterClass * updatedRC(const TargetRegisterClass *RC) const
uint64_t ZeroIsSpecialOrig
Definition: PPCInstrInfo.h:83
const char * getSymbolName() const
static bool isZeroExtendingOp(const MachineInstr &MI)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:703
static void swapMIOperands(MachineInstr &MI, unsigned Op1, unsigned Op2)
void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo, int64_t Imm) const
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
bool isTOCSaveMI(const MachineInstr &MI) const
defusechain_iterator - This class provides iterator support for machine operands in the function that...
PPCInstrInfo(PPCSubtarget &STI)
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1583
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:407
CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based loops.
bool hasP9Vector() const
Definition: PPCSubtarget.h:257
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const override
MO_NLP_HIDDEN_FLAG - If this bit is set, the symbol reference is to a symbol with hidden visibility...
Definition: PPC.h:104
virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns) const
Return true when there is potentially a faster code sequence for an instruction chain ending in Root...
CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
Itinerary data supplied by a subtarget to be used by a target.
const PPCTargetMachine & getTargetMachine() const
Definition: PPCSubtarget.h:194
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:223
void setReg(Register Reg)
Change the register this operand corresponds to.
virtual const TargetInstrInfo * getInstrInfo() const
unsigned getAlignment() const
Definition: Globals.cpp:97
constexpr char Attrs[]
Key for Kernel::Metadata::mAttrs.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
unsigned getBitWidth() const
Get the number of bits in this IntegerType.
Definition: DerivedTypes.h:71
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
reverse_iterator rend()
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:680
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
unsigned getKillRegState(bool B)
bool hasAttribute(Attribute::AttrKind Kind) const
Return true if the attribute exists in this set.
Definition: Attributes.cpp:654
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:19
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
TargetInstrInfo - Interface to description of machine instruction set.
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
unsigned getDeadRegState(bool B)
VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
const BasicBlock & getEntryBlock() const
Definition: Function.h:664
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:601
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, const unsigned PhiDepth) const
Type * getReturnType() const
Returns the type of the ret val.
Definition: Function.h:168
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:570
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static unsigned selectReg(int64_t Imm1, int64_t Imm2, unsigned CompareOpc, unsigned TrueReg, unsigned FalseReg, unsigned CRSubReg)
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
unsigned const MachineRegisterInfo * MRI
bool isLiveInSExt(unsigned VReg) const
This function returns true if the specified vreg is a live-in register and sign-extended.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
int getAltVSXFMAOpcode(uint16_t Opcode)
Simple binary floating point operators.
Definition: ISDOpcodes.h:287
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineInstrBuilder & UseMI
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
MO_NLP_FLAG - If this bit is set, the symbol reference is actually to the non_lazy_ptr for the global...
Definition: PPC.h:99
const GlobalValue * getGlobal() const
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:30
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:189
STFIWX - The STFIWX instruction.
use_instr_iterator use_instr_begin(unsigned RegNo) const
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:566
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
constexpr double e
Definition: MathExtras.h:57
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
void setImm(int64_t immVal)
GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point load which sign-extends from a 32-bit inte...
MI-level patchpoint operands.
Definition: StackMaps.h:76
Class to represent integer types.
Definition: DerivedTypes.h:40
PPCHazardRecognizer970 - This class defines a finite state automata that models the dispatch logic on...
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
unsigned getStoreOpcodeForSpill(unsigned Reg, const TargetRegisterClass *RC=nullptr) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
size_t size() const
Definition: SmallVector.h:52
auto find(R &&Range, const T &Val) -> decltype(adl_begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1186
unsigned getPredicateHint(Predicate Opcode)
Return the hint bits of the predicate.
Definition: PPCPredicates.h:82
unsigned getDarwinDirective() const
getDarwinDirective - Returns the -m directive specified for the cpu.
Definition: PPCSubtarget.h:173
static unsigned getCRFromCRBit(unsigned SrcReg)
MO_TLS - Indicates that the operand being accessed is some kind of thread-local symbol.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
unsigned first
void setIsKill(bool Val=true)
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
The next are not flags but distinct values.
Definition: PPC.h:107
The memory access writes data.
static bool MBBDefinesCTR(MachineBasicBlock &MBB)
bool isBDNZ(unsigned Opcode) const
Check Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:203
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given stackmap should emit.
Definition: StackMaps.h:50
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Predicate getPredicate(unsigned Condition, unsigned Hint)
Return predicate consisting of specified condition and hint bits.
Definition: PPCPredicates.h:87
Iterator for intrusive lists based on ilist_node.
void setOpcode(unsigned Op)
Definition: MCInst.h:170
bool isUnpredicatedTerminator(const MachineInstr &MI) const override
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Definition: SmallPtrSet.h:417
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:390
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:551
static uint64_t add(uint64_t LeftOp, uint64_t RightOp)
Definition: FileCheck.cpp:215
void getNoop(MCInst &NopInst) const override
Return the noop instruction to use for a noop.
static unsigned getCRBitValue(unsigned CRBit)
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1023
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
static cl::opt< bool > VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy", cl::desc("Causes the backend to crash instead of generating a nop VSX copy"), cl::Hidden)
static cl::opt< bool > UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden, cl::desc("Use the old (incorrect) instruction latency calculation"))
APInt rotl(unsigned rotateAmt) const
Rotate left by rotateAmt.
Definition: APInt.cpp:1049
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
static bool isVFRegister(unsigned Reg)
Definition: PPCInstrInfo.h:397
int64_t getImm() const
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Class for arbitrary precision integers.
Definition: APInt.h:69
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
QVGPCI = This corresponds to the QPX qvgpci instruction.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
MachineInstr * getDefMIPostRA(unsigned Reg, MachineInstr &MI, bool &SeenIntermediateUse) const
iterator_range< mop_iterator > implicit_operands()
Definition: MachineInstr.h:490
bool use_empty(unsigned RegNo) const
use_empty - Return true if there are no instructions using the specified register.
int findRegisterUseOperandIdx(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found...
On a symbol operand, this represents the lo part.
Definition: AVRInstrInfo.h:52
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:255
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
TargetSubtargetInfo - Generic base class for all target subtargets.
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in <Root...
bool isPredicated(const MachineInstr &MI) const override
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
bool isLiveIn(unsigned Reg) const
Representation of each machine instruction.
Definition: MachineInstr.h:63
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Predicate InvertPredicate(Predicate Opcode)
Invert the specified predicate. != -> ==, < -> >=.
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AAResults *AA) const override
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:426
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
bool hasOneUse(unsigned RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MI-level stackmap operands.
Definition: StackMaps.h:35
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:509
virtual bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction...
TargetOptions Options
static bool isSignExtendingOp(const MachineInstr &MI)
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned getLoadOpcodeForSpill(unsigned Reg, const TargetRegisterClass *RC=nullptr) const
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
void setSubReg(unsigned subReg)
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void fixupIsDeadOrKill(MachineInstr &StartMI, MachineInstr &EndMI, unsigned RegNo) const
Fixup killed/dead flag for register RegNo between instructions [StartMI, EndMI].
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given patchpoint should emit.
Definition: StackMaps.h:104
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:558
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register...
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:382
bool isSignedIntN(unsigned N) const
Check if this APInt has an N-bits signed integer value.
Definition: APInt.h:455
const unsigned MAX_DEPTH
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Return true if two MIs access different memory addresses and false otherwise.
iterator_range< use_instr_iterator > use_instructions(unsigned Reg) const
uint64_t ImmMustBeMultipleOf
Definition: PPCInstrInfo.h:80
unsigned getPredicateCondition(Predicate Opcode)
Return the condition without hint bits.
Definition: PPCPredicates.h:77
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
bool isLiveInZExt(unsigned VReg) const
This function returns true if the specified vreg is a live-in register and zero-extended.
INLINEASM_BR - Terminator version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:706
LLVM Value Representation.
Definition: Value.h:74
static use_instr_iterator use_instr_end()
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:69
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:273
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:190
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when ...
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
IRTranslator LLVM IR MI
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:663
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
bool isPredicable(const MachineInstr &MI) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool isSVR4ABI() const
Definition: PPCSubtarget.h:320
Register getReg() const
getReg - Returns the register number.
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:70
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:415
On a symbol operand "FOO", this indicates that the reference is actually to "FOO@plt".
Definition: PPC.h:91
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: PPCInstrInfo.h:185
virtual unsigned lookThruCopyLike(unsigned SrcReg, const MachineRegisterInfo *MRI) const
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:313
static cl::opt< bool > DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden, cl::desc("Disable analysis for CTR loops"))
Instructions::const_iterator const_instr_iterator
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point load which zero-extends from a 32-bit inte...
SpillOpcodeKey
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...
MO_PIC_FLAG - If this bit is set, the symbol reference is relative to the function&#39;s picbase...
Definition: PPC.h:95
bool convertToImmediateForm(MachineInstr &MI, MachineInstr **KilledDef=nullptr) const
static bool isAnImmediateOperand(const MachineOperand &MO)
bool expandPostRAPseudo(MachineInstr &MI) const override
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:143
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:188
bool expandVSXMemPseudo(MachineInstr &MI) const
bool isImplicit() const
bool isZeroExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always zero-extended, i.e.
Definition: PPCInstrInfo.h:419
Predicate getSwappedPredicate(Predicate Opcode)
Assume the condition register is set by MI(a,b), return the predicate if we modify the instructions s...