LLVM  7.0.0svn
PPCRegisterInfo.cpp
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1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "PPCRegisterInfo.h"
16 #include "PPC.h"
17 #include "PPCFrameLowering.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCSubtarget.h"
21 #include "PPCTargetMachine.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/Statistic.h"
33 #include "llvm/IR/CallingConv.h"
34 #include "llvm/IR/Constants.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/IR/Type.h"
38 #include "llvm/Support/Debug.h"
44 #include <cstdlib>
45 
46 using namespace llvm;
47 
48 #define DEBUG_TYPE "reginfo"
49 
50 #define GET_REGINFO_TARGET_DESC
51 #include "PPCGenRegisterInfo.inc"
52 
53 STATISTIC(InflateGPRC, "Number of gprc inputs for getLargestLegalClass");
54 STATISTIC(InflateGP8RC, "Number of g8rc inputs for getLargestLegalClass");
55 
56 static cl::opt<bool>
57 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true),
58  cl::desc("Enable use of a base pointer for complex stack frames"));
59 
60 static cl::opt<bool>
61 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false),
62  cl::desc("Force the use of a base pointer in every function"));
63 
64 static cl::opt<bool>
65 EnableGPRToVecSpills("ppc-enable-gpr-to-vsr-spills", cl::Hidden, cl::init(false),
66  cl::desc("Enable spills from gpr to vsr rather than stack"));
67 
68 static cl::opt<bool>
69 StackPtrConst("ppc-stack-ptr-caller-preserved",
70  cl::desc("Consider R1 caller preserved so stack saves of "
71  "caller preserved registers can be LICM candidates"),
72  cl::init(true), cl::Hidden);
73 
75  : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR,
76  TM.isPPC64() ? 0 : 1,
77  TM.isPPC64() ? 0 : 1),
78  TM(TM) {
79  ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
80  ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
81  ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
82  ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
83  ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
84  ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
85  ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
86  ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
87  ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32;
88 
89  // 64-bit
90  ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
91  ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
92  ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
93  ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
94  ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
95 
96  // VSX
97  ImmToIdxMap[PPC::DFLOADf32] = PPC::LXSSPX;
98  ImmToIdxMap[PPC::DFLOADf64] = PPC::LXSDX;
99  ImmToIdxMap[PPC::SPILLTOVSR_LD] = PPC::SPILLTOVSR_LDX;
100  ImmToIdxMap[PPC::SPILLTOVSR_ST] = PPC::SPILLTOVSR_STX;
101  ImmToIdxMap[PPC::DFSTOREf32] = PPC::STXSSPX;
102  ImmToIdxMap[PPC::DFSTOREf64] = PPC::STXSDX;
103  ImmToIdxMap[PPC::LXV] = PPC::LXVX;
104  ImmToIdxMap[PPC::LXSD] = PPC::LXSDX;
105  ImmToIdxMap[PPC::LXSSP] = PPC::LXSSPX;
106  ImmToIdxMap[PPC::STXV] = PPC::STXVX;
107  ImmToIdxMap[PPC::STXSD] = PPC::STXSDX;
108  ImmToIdxMap[PPC::STXSSP] = PPC::STXSSPX;
109 }
110 
111 /// getPointerRegClass - Return the register class to use to hold pointers.
112 /// This is used for addressing modes.
113 const TargetRegisterClass *
115  const {
116  // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value
117  // when it checks for ZERO folding.
118  if (Kind == 1) {
119  if (TM.isPPC64())
120  return &PPC::G8RC_NOX0RegClass;
121  return &PPC::GPRC_NOR0RegClass;
122  }
123 
124  if (TM.isPPC64())
125  return &PPC::G8RCRegClass;
126  return &PPC::GPRCRegClass;
127 }
128 
129 const MCPhysReg*
131  const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
133  if (Subtarget.hasVSX())
134  return CSR_64_AllRegs_VSX_SaveList;
135  if (Subtarget.hasAltivec())
136  return CSR_64_AllRegs_Altivec_SaveList;
137  return CSR_64_AllRegs_SaveList;
138  }
139 
140  if (Subtarget.isDarwinABI())
141  return TM.isPPC64()
142  ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_SaveList
143  : CSR_Darwin64_SaveList)
144  : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_SaveList
145  : CSR_Darwin32_SaveList);
146 
147  if (TM.isPPC64() && MF->getInfo<PPCFunctionInfo>()->isSplitCSR())
148  return CSR_SRV464_TLS_PE_SaveList;
149 
150  // On PPC64, we might need to save r2 (but only if it is not reserved).
151  bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2);
152 
154  return TM.isPPC64()
155  ? (Subtarget.hasAltivec()
156  ? (SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList
157  : CSR_SVR64_ColdCC_Altivec_SaveList)
158  : (SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList
159  : CSR_SVR64_ColdCC_SaveList))
160  : (Subtarget.hasAltivec() ? CSR_SVR32_ColdCC_Altivec_SaveList
161  : CSR_SVR32_ColdCC_SaveList);
162  }
163 
164  return TM.isPPC64()
165  ? (Subtarget.hasAltivec()
166  ? (SaveR2 ? CSR_SVR464_R2_Altivec_SaveList
167  : CSR_SVR464_Altivec_SaveList)
168  : (SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList))
169  : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_SaveList
170  : CSR_SVR432_SaveList);
171 }
172 
173 const MCPhysReg *
175  assert(MF && "Invalid MachineFunction pointer.");
176  const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
177  if (Subtarget.isDarwinABI())
178  return nullptr;
179  if (!TM.isPPC64())
180  return nullptr;
182  return nullptr;
183  if (!MF->getInfo<PPCFunctionInfo>()->isSplitCSR())
184  return nullptr;
185 
186  // On PPC64, we might need to save r2 (but only if it is not reserved).
187  bool SaveR2 = !getReservedRegs(*MF).test(PPC::X2);
188  if (Subtarget.hasAltivec())
189  return SaveR2
190  ? CSR_SVR464_R2_Altivec_ViaCopy_SaveList
191  : CSR_SVR464_Altivec_ViaCopy_SaveList;
192  else
193  return SaveR2
194  ? CSR_SVR464_R2_ViaCopy_SaveList
195  : CSR_SVR464_ViaCopy_SaveList;
196 }
197 
198 const uint32_t *
200  CallingConv::ID CC) const {
201  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
202  if (CC == CallingConv::AnyReg) {
203  if (Subtarget.hasVSX())
204  return CSR_64_AllRegs_VSX_RegMask;
205  if (Subtarget.hasAltivec())
206  return CSR_64_AllRegs_Altivec_RegMask;
207  return CSR_64_AllRegs_RegMask;
208  }
209 
210  if (Subtarget.isDarwinABI())
211  return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_RegMask
212  : CSR_Darwin64_RegMask)
213  : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_RegMask
214  : CSR_Darwin32_RegMask);
215 
216  if (CC == CallingConv::Cold) {
217  return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR64_ColdCC_Altivec_RegMask
218  : CSR_SVR64_ColdCC_RegMask)
219  : (Subtarget.hasAltivec() ? CSR_SVR32_ColdCC_Altivec_RegMask
220  : CSR_SVR32_ColdCC_RegMask);
221  }
222 
223  return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask
224  : CSR_SVR464_RegMask)
225  : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask
226  : CSR_SVR432_RegMask);
227 }
228 
229 const uint32_t*
231  return CSR_NoRegs_RegMask;
232 }
233 
235  for (unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8, PPC::RM})
236  Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32));
237 }
238 
240  BitVector Reserved(getNumRegs());
241  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
242  const PPCFrameLowering *TFI = getFrameLowering(MF);
243 
244  // The ZERO register is not really a register, but the representation of r0
245  // when used in instructions that treat r0 as the constant 0.
246  markSuperRegs(Reserved, PPC::ZERO);
247 
248  // The FP register is also not really a register, but is the representation
249  // of the frame pointer register used by ISD::FRAMEADDR.
250  markSuperRegs(Reserved, PPC::FP);
251 
252  // The BP register is also not really a register, but is the representation
253  // of the base pointer register used by setjmp.
254  markSuperRegs(Reserved, PPC::BP);
255 
256  // The counter registers must be reserved so that counter-based loops can
257  // be correctly formed (and the mtctr instructions are not DCE'd).
258  markSuperRegs(Reserved, PPC::CTR);
259  markSuperRegs(Reserved, PPC::CTR8);
260 
261  markSuperRegs(Reserved, PPC::R1);
262  markSuperRegs(Reserved, PPC::LR);
263  markSuperRegs(Reserved, PPC::LR8);
264  markSuperRegs(Reserved, PPC::RM);
265 
266  if (!Subtarget.isDarwinABI() || !Subtarget.hasAltivec())
267  markSuperRegs(Reserved, PPC::VRSAVE);
268 
269  // The SVR4 ABI reserves r2 and r13
270  if (Subtarget.isSVR4ABI()) {
271  // We only reserve r2 if we need to use the TOC pointer. If we have no
272  // explicit uses of the TOC pointer (meaning we're a leaf function with
273  // no constant-pool loads, etc.) and we have no potential uses inside an
274  // inline asm block, then we can treat r2 has an ordinary callee-saved
275  // register.
276  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
277  if (!TM.isPPC64() || FuncInfo->usesTOCBasePtr() || MF.hasInlineAsm())
278  markSuperRegs(Reserved, PPC::R2); // System-reserved register
279  markSuperRegs(Reserved, PPC::R13); // Small Data Area pointer register
280  }
281 
282  // On PPC64, r13 is the thread pointer. Never allocate this register.
283  if (TM.isPPC64())
284  markSuperRegs(Reserved, PPC::R13);
285 
286  if (TFI->needsFP(MF))
287  markSuperRegs(Reserved, PPC::R31);
288 
289  bool IsPositionIndependent = TM.isPositionIndependent();
290  if (hasBasePointer(MF)) {
291  if (Subtarget.isSVR4ABI() && !TM.isPPC64() && IsPositionIndependent)
292  markSuperRegs(Reserved, PPC::R29);
293  else
294  markSuperRegs(Reserved, PPC::R30);
295  }
296 
297  if (Subtarget.isSVR4ABI() && !TM.isPPC64() && IsPositionIndependent)
298  markSuperRegs(Reserved, PPC::R30);
299 
300  // Reserve Altivec registers when Altivec is unavailable.
301  if (!Subtarget.hasAltivec())
302  for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(),
303  IE = PPC::VRRCRegClass.end(); I != IE; ++I)
304  markSuperRegs(Reserved, *I);
305 
306  assert(checkAllSuperRegsMarked(Reserved));
307  return Reserved;
308 }
309 
311  const MachineFunction &MF) const {
313  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
314  const MachineFrameInfo &MFI = MF.getFrameInfo();
315  if (!TM.isPPC64())
316  return false;
317 
318  if (!Subtarget.isSVR4ABI())
319  return false;
320  if (PhysReg == PPC::X2)
321  // X2 is guaranteed to be preserved within a function if it is reserved.
322  // The reason it's reserved is that it's the TOC pointer (and the function
323  // uses the TOC). In functions where it isn't reserved (i.e. leaf functions
324  // with no TOC access), we can't claim that it is preserved.
325  return (getReservedRegs(MF).test(PPC::X2));
326  if (StackPtrConst && (PhysReg == PPC::X1) && !MFI.hasVarSizedObjects()
327  && !MFI.hasOpaqueSPAdjustment())
328  // The value of the stack pointer does not change within a function after
329  // the prologue and before the epilogue if there are no dynamic allocations
330  // and no inline asm which clobbers X1.
331  return true;
332  return false;
333 }
334 
336  MachineFunction &MF) const {
337  const PPCFrameLowering *TFI = getFrameLowering(MF);
338  const unsigned DefaultSafety = 1;
339 
340  switch (RC->getID()) {
341  default:
342  return 0;
343  case PPC::G8RC_NOX0RegClassID:
344  case PPC::GPRC_NOR0RegClassID:
345  case PPC::G8RCRegClassID:
346  case PPC::GPRCRegClassID: {
347  unsigned FP = TFI->hasFP(MF) ? 1 : 0;
348  return 32 - FP - DefaultSafety;
349  }
350  case PPC::F8RCRegClassID:
351  case PPC::F4RCRegClassID:
352  case PPC::QFRCRegClassID:
353  case PPC::QSRCRegClassID:
354  case PPC::QBRCRegClassID:
355  case PPC::VRRCRegClassID:
356  case PPC::VFRCRegClassID:
357  case PPC::VSLRCRegClassID:
358  return 32 - DefaultSafety;
359  case PPC::VSRCRegClassID:
360  case PPC::VSFRCRegClassID:
361  case PPC::VSSRCRegClassID:
362  return 64 - DefaultSafety;
363  case PPC::CRRCRegClassID:
364  return 8 - DefaultSafety;
365  }
366 }
367 
368 const TargetRegisterClass *
370  const MachineFunction &MF) const {
371  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
372  if (Subtarget.hasVSX()) {
373  // With VSX, we can inflate various sub-register classes to the full VSX
374  // register set.
375 
376  // For Power9 we allow the user to enable GPR to vector spills.
377  // FIXME: Currently limited to spilling GP8RC. A follow on patch will add
378  // support to spill GPRC.
379  if (TM.isELFv2ABI()) {
380  if (Subtarget.hasP9Vector() && EnableGPRToVecSpills &&
381  RC == &PPC::G8RCRegClass) {
382  InflateGP8RC++;
383  return &PPC::SPILLTOVSRRCRegClass;
384  }
385  if (RC == &PPC::GPRCRegClass && EnableGPRToVecSpills)
386  InflateGPRC++;
387  }
388  if (RC == &PPC::F8RCRegClass)
389  return &PPC::VSFRCRegClass;
390  else if (RC == &PPC::VRRCRegClass)
391  return &PPC::VSRCRegClass;
392  else if (RC == &PPC::F4RCRegClass && Subtarget.hasP8Vector())
393  return &PPC::VSSRCRegClass;
394  }
395 
397 }
398 
399 //===----------------------------------------------------------------------===//
400 // Stack Frame Processing methods
401 //===----------------------------------------------------------------------===//
402 
403 /// lowerDynamicAlloc - Generate the code for allocating an object in the
404 /// current frame. The sequence of code will be in the general form
405 ///
406 /// addi R0, SP, \#frameSize ; get the address of the previous frame
407 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
408 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
409 ///
411  // Get the instruction.
412  MachineInstr &MI = *II;
413  // Get the instruction's basic block.
414  MachineBasicBlock &MBB = *MI.getParent();
415  // Get the basic block's function.
416  MachineFunction &MF = *MBB.getParent();
417  // Get the frame info.
418  MachineFrameInfo &MFI = MF.getFrameInfo();
419  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
420  // Get the instruction info.
421  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
422  // Determine whether 64-bit pointers are used.
423  bool LP64 = TM.isPPC64();
424  DebugLoc dl = MI.getDebugLoc();
425 
426  // Get the maximum call stack size.
427  unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
428  // Get the total frame size.
429  unsigned FrameSize = MFI.getStackSize();
430 
431  // Get stack alignments.
432  const PPCFrameLowering *TFI = getFrameLowering(MF);
433  unsigned TargetAlign = TFI->getStackAlignment();
434  unsigned MaxAlign = MFI.getMaxAlignment();
435  assert((maxCallFrameSize & (MaxAlign-1)) == 0 &&
436  "Maximum call-frame size not sufficiently aligned");
437 
438  // Determine the previous frame's address. If FrameSize can't be
439  // represented as 16 bits or we need special alignment, then we load the
440  // previous frame's address from 0(SP). Why not do an addis of the hi?
441  // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
442  // Constructing the constant and adding would take 3 instructions.
443  // Fortunately, a frame greater than 32K is rare.
444  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
445  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
446  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
447 
448  if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
449  if (LP64)
450  BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), Reg)
451  .addReg(PPC::X31)
452  .addImm(FrameSize);
453  else
454  BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
455  .addReg(PPC::R31)
456  .addImm(FrameSize);
457  } else if (LP64) {
458  BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
459  .addImm(0)
460  .addReg(PPC::X1);
461  } else {
462  BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
463  .addImm(0)
464  .addReg(PPC::R1);
465  }
466 
467  bool KillNegSizeReg = MI.getOperand(1).isKill();
468  unsigned NegSizeReg = MI.getOperand(1).getReg();
469 
470  // Grow the stack and update the stack pointer link, then determine the
471  // address of new allocated space.
472  if (LP64) {
473  if (MaxAlign > TargetAlign) {
474  unsigned UnalNegSizeReg = NegSizeReg;
475  NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
476 
477  // Unfortunately, there is no andi, only andi., and we can't insert that
478  // here because we might clobber cr0 while it is live.
479  BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
480  .addImm(~(MaxAlign-1));
481 
482  unsigned NegSizeReg1 = NegSizeReg;
483  NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
484  BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
485  .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
486  .addReg(NegSizeReg1, RegState::Kill);
487  KillNegSizeReg = true;
488  }
489 
490  BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
491  .addReg(Reg, RegState::Kill)
492  .addReg(PPC::X1)
493  .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
494  BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
495  .addReg(PPC::X1)
496  .addImm(maxCallFrameSize);
497  } else {
498  if (MaxAlign > TargetAlign) {
499  unsigned UnalNegSizeReg = NegSizeReg;
500  NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
501 
502  // Unfortunately, there is no andi, only andi., and we can't insert that
503  // here because we might clobber cr0 while it is live.
504  BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg)
505  .addImm(~(MaxAlign-1));
506 
507  unsigned NegSizeReg1 = NegSizeReg;
508  NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
509  BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg)
510  .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
511  .addReg(NegSizeReg1, RegState::Kill);
512  KillNegSizeReg = true;
513  }
514 
515  BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
516  .addReg(Reg, RegState::Kill)
517  .addReg(PPC::R1)
518  .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
519  BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
520  .addReg(PPC::R1)
521  .addImm(maxCallFrameSize);
522  }
523 
524  // Discard the DYNALLOC instruction.
525  MBB.erase(II);
526 }
527 
529  MachineBasicBlock::iterator II) const {
530  // Get the instruction.
531  MachineInstr &MI = *II;
532  // Get the instruction's basic block.
533  MachineBasicBlock &MBB = *MI.getParent();
534  // Get the basic block's function.
535  MachineFunction &MF = *MBB.getParent();
536  // Get the frame info.
537  MachineFrameInfo &MFI = MF.getFrameInfo();
538  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
539  // Get the instruction info.
540  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
541 
542  unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
543  bool is64Bit = TM.isPPC64();
544  DebugLoc dl = MI.getDebugLoc();
545  BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI),
546  MI.getOperand(0).getReg())
547  .addImm(maxCallFrameSize);
548  MBB.erase(II);
549 }
550 
551 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
552 /// reserving a whole register (R0), we scrounge for one here. This generates
553 /// code like this:
554 ///
555 /// mfcr rA ; Move the conditional register into GPR rA.
556 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
557 /// stw rA, FI ; Store rA to the frame.
558 ///
560  unsigned FrameIndex) const {
561  // Get the instruction.
562  MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
563  // Get the instruction's basic block.
564  MachineBasicBlock &MBB = *MI.getParent();
565  MachineFunction &MF = *MBB.getParent();
566  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
567  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
568  DebugLoc dl = MI.getDebugLoc();
569 
570  bool LP64 = TM.isPPC64();
571  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
572  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
573 
574  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
575  unsigned SrcReg = MI.getOperand(0).getReg();
576 
577  // We need to store the CR in the low 4-bits of the saved value. First, issue
578  // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg.
579  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
580  .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
581 
582  // If the saved register wasn't CR0, shift the bits left so that they are in
583  // CR0's slot.
584  if (SrcReg != PPC::CR0) {
585  unsigned Reg1 = Reg;
586  Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
587 
588  // rlwinm rA, rA, ShiftBits, 0, 31.
589  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
590  .addReg(Reg1, RegState::Kill)
591  .addImm(getEncodingValue(SrcReg) * 4)
592  .addImm(0)
593  .addImm(31);
594  }
595 
596  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
597  .addReg(Reg, RegState::Kill),
598  FrameIndex);
599 
600  // Discard the pseudo instruction.
601  MBB.erase(II);
602 }
603 
605  unsigned FrameIndex) const {
606  // Get the instruction.
607  MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
608  // Get the instruction's basic block.
609  MachineBasicBlock &MBB = *MI.getParent();
610  MachineFunction &MF = *MBB.getParent();
611  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
612  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
613  DebugLoc dl = MI.getDebugLoc();
614 
615  bool LP64 = TM.isPPC64();
616  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
617  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
618 
619  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
620  unsigned DestReg = MI.getOperand(0).getReg();
621  assert(MI.definesRegister(DestReg) &&
622  "RESTORE_CR does not define its destination");
623 
624  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
625  Reg), FrameIndex);
626 
627  // If the reloaded register isn't CR0, shift the bits right so that they are
628  // in the right CR's slot.
629  if (DestReg != PPC::CR0) {
630  unsigned Reg1 = Reg;
631  Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
632 
633  unsigned ShiftBits = getEncodingValue(DestReg)*4;
634  // rlwinm r11, r11, 32-ShiftBits, 0, 31.
635  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
636  .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
637  .addImm(31);
638  }
639 
640  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg)
641  .addReg(Reg, RegState::Kill);
642 
643  // Discard the pseudo instruction.
644  MBB.erase(II);
645 }
646 
648  unsigned FrameIndex) const {
649  // Get the instruction.
650  MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset>
651  // Get the instruction's basic block.
652  MachineBasicBlock &MBB = *MI.getParent();
653  MachineFunction &MF = *MBB.getParent();
654  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
655  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
656  DebugLoc dl = MI.getDebugLoc();
657 
658  bool LP64 = TM.isPPC64();
659  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
660  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
661 
662  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
663  unsigned SrcReg = MI.getOperand(0).getReg();
664 
665  BuildMI(MBB, II, dl, TII.get(TargetOpcode::KILL),
666  getCRFromCRBit(SrcReg))
667  .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
668 
669  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
670  .addReg(getCRFromCRBit(SrcReg));
671 
672  // If the saved register wasn't CR0LT, shift the bits left so that the bit to
673  // store is the first one. Mask all but that bit.
674  unsigned Reg1 = Reg;
675  Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
676 
677  // rlwinm rA, rA, ShiftBits, 0, 0.
678  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
679  .addReg(Reg1, RegState::Kill)
680  .addImm(getEncodingValue(SrcReg))
681  .addImm(0).addImm(0);
682 
683  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
684  .addReg(Reg, RegState::Kill),
685  FrameIndex);
686 
687  // Discard the pseudo instruction.
688  MBB.erase(II);
689 }
690 
692  unsigned FrameIndex) const {
693  // Get the instruction.
694  MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset>
695  // Get the instruction's basic block.
696  MachineBasicBlock &MBB = *MI.getParent();
697  MachineFunction &MF = *MBB.getParent();
698  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
699  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
700  DebugLoc dl = MI.getDebugLoc();
701 
702  bool LP64 = TM.isPPC64();
703  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
704  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
705 
706  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
707  unsigned DestReg = MI.getOperand(0).getReg();
708  assert(MI.definesRegister(DestReg) &&
709  "RESTORE_CRBIT does not define its destination");
710 
711  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
712  Reg), FrameIndex);
713 
714  BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg);
715 
716  unsigned RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
717  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO)
718  .addReg(getCRFromCRBit(DestReg));
719 
720  unsigned ShiftBits = getEncodingValue(DestReg);
721  // rlwimi r11, r10, 32-ShiftBits, ..., ...
722  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO)
723  .addReg(RegO, RegState::Kill)
724  .addReg(Reg, RegState::Kill)
725  .addImm(ShiftBits ? 32 - ShiftBits : 0)
726  .addImm(ShiftBits)
727  .addImm(ShiftBits);
728 
729  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF),
730  getCRFromCRBit(DestReg))
731  .addReg(RegO, RegState::Kill)
732  // Make sure we have a use dependency all the way through this
733  // sequence of instructions. We can't have the other bits in the CR
734  // modified in between the mfocrf and the mtocrf.
736 
737  // Discard the pseudo instruction.
738  MBB.erase(II);
739 }
740 
742  unsigned FrameIndex) const {
743  // Get the instruction.
744  MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset>
745  // Get the instruction's basic block.
746  MachineBasicBlock &MBB = *MI.getParent();
747  MachineFunction &MF = *MBB.getParent();
748  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
749  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
750  DebugLoc dl = MI.getDebugLoc();
751 
752  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
753  unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
754  unsigned SrcReg = MI.getOperand(0).getReg();
755 
756  BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg)
757  .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
758 
760  BuildMI(MBB, II, dl, TII.get(PPC::STW)).addReg(Reg, RegState::Kill),
761  FrameIndex);
762 
763  // Discard the pseudo instruction.
764  MBB.erase(II);
765 }
766 
768  unsigned FrameIndex) const {
769  // Get the instruction.
770  MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset>
771  // Get the instruction's basic block.
772  MachineBasicBlock &MBB = *MI.getParent();
773  MachineFunction &MF = *MBB.getParent();
774  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
775  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
776  DebugLoc dl = MI.getDebugLoc();
777 
778  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
779  unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
780  unsigned DestReg = MI.getOperand(0).getReg();
781  assert(MI.definesRegister(DestReg) &&
782  "RESTORE_VRSAVE does not define its destination");
783 
784  addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ),
785  Reg), FrameIndex);
786 
787  BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg)
788  .addReg(Reg, RegState::Kill);
789 
790  // Discard the pseudo instruction.
791  MBB.erase(II);
792 }
793 
795  unsigned Reg, int &FrameIdx) const {
796  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
797  // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4
798  // ABI, return true to prevent allocating an additional frame slot.
799  // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0
800  // is arbitrary and will be subsequently ignored. For 32-bit, we have
801  // previously created the stack slot if needed, so return its FrameIdx.
802  if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) {
803  if (TM.isPPC64())
804  FrameIdx = 0;
805  else {
806  const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
807  FrameIdx = FI->getCRSpillFrameIndex();
808  }
809  return true;
810  }
811  return false;
812 }
813 
814 // If the offset must be a multiple of some value, return what that value is.
815 static unsigned offsetMinAlign(const MachineInstr &MI) {
816  unsigned OpC = MI.getOpcode();
817 
818  switch (OpC) {
819  default:
820  return 1;
821  case PPC::LWA:
822  case PPC::LWA_32:
823  case PPC::LD:
824  case PPC::LDU:
825  case PPC::STD:
826  case PPC::STDU:
827  case PPC::DFLOADf32:
828  case PPC::DFLOADf64:
829  case PPC::DFSTOREf32:
830  case PPC::DFSTOREf64:
831  case PPC::LXSD:
832  case PPC::LXSSP:
833  case PPC::STXSD:
834  case PPC::STXSSP:
835  return 4;
836  case PPC::LXV:
837  case PPC::STXV:
838  return 16;
839  }
840 }
841 
842 // Return the OffsetOperandNo given the FIOperandNum (and the instruction).
843 static unsigned getOffsetONFromFION(const MachineInstr &MI,
844  unsigned FIOperandNum) {
845  // Take into account whether it's an add or mem instruction
846  unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
847  if (MI.isInlineAsm())
848  OffsetOperandNo = FIOperandNum - 1;
849  else if (MI.getOpcode() == TargetOpcode::STACKMAP ||
850  MI.getOpcode() == TargetOpcode::PATCHPOINT)
851  OffsetOperandNo = FIOperandNum + 1;
852 
853  return OffsetOperandNo;
854 }
855 
856 void
858  int SPAdj, unsigned FIOperandNum,
859  RegScavenger *RS) const {
860  assert(SPAdj == 0 && "Unexpected");
861 
862  // Get the instruction.
863  MachineInstr &MI = *II;
864  // Get the instruction's basic block.
865  MachineBasicBlock &MBB = *MI.getParent();
866  // Get the basic block's function.
867  MachineFunction &MF = *MBB.getParent();
868  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
869  // Get the instruction info.
870  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
871  // Get the frame info.
872  MachineFrameInfo &MFI = MF.getFrameInfo();
873  DebugLoc dl = MI.getDebugLoc();
874 
875  unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
876 
877  // Get the frame index.
878  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
879 
880  // Get the frame pointer save index. Users of this index are primarily
881  // DYNALLOC instructions.
883  int FPSI = FI->getFramePointerSaveIndex();
884  // Get the instruction opcode.
885  unsigned OpC = MI.getOpcode();
886 
887  if ((OpC == PPC::DYNAREAOFFSET || OpC == PPC::DYNAREAOFFSET8)) {
889  return;
890  }
891 
892  // Special case for dynamic alloca.
893  if (FPSI && FrameIndex == FPSI &&
894  (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
895  lowerDynamicAlloc(II);
896  return;
897  }
898 
899  // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc.
900  if (OpC == PPC::SPILL_CR) {
901  lowerCRSpilling(II, FrameIndex);
902  return;
903  } else if (OpC == PPC::RESTORE_CR) {
904  lowerCRRestore(II, FrameIndex);
905  return;
906  } else if (OpC == PPC::SPILL_CRBIT) {
907  lowerCRBitSpilling(II, FrameIndex);
908  return;
909  } else if (OpC == PPC::RESTORE_CRBIT) {
910  lowerCRBitRestore(II, FrameIndex);
911  return;
912  } else if (OpC == PPC::SPILL_VRSAVE) {
913  lowerVRSAVESpilling(II, FrameIndex);
914  return;
915  } else if (OpC == PPC::RESTORE_VRSAVE) {
916  lowerVRSAVERestore(II, FrameIndex);
917  return;
918  }
919 
920  // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
921  MI.getOperand(FIOperandNum).ChangeToRegister(
922  FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false);
923 
924  // If the instruction is not present in ImmToIdxMap, then it has no immediate
925  // form (and must be r+r).
926  bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP &&
927  OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(OpC);
928 
929  // Now add the frame object offset to the offset from r1.
930  int Offset = MFI.getObjectOffset(FrameIndex);
931  Offset += MI.getOperand(OffsetOperandNo).getImm();
932 
933  // If we're not using a Frame Pointer that has been set to the value of the
934  // SP before having the stack size subtracted from it, then add the stack size
935  // to Offset to get the correct offset.
936  // Naked functions have stack size 0, although getStackSize may not reflect
937  // that because we didn't call all the pieces that compute it for naked
938  // functions.
939  if (!MF.getFunction().hasFnAttribute(Attribute::Naked)) {
940  if (!(hasBasePointer(MF) && FrameIndex < 0))
941  Offset += MFI.getStackSize();
942  }
943 
944  // If we can, encode the offset directly into the instruction. If this is a
945  // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
946  // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
947  // clear can be encoded. This is extremely uncommon, because normally you
948  // only "std" to a stack slot that is at least 4-byte aligned, but it can
949  // happen in invalid code.
950  assert(OpC != PPC::DBG_VALUE &&
951  "This should be handled in a target-independent way");
952  if (!noImmForm && ((isInt<16>(Offset) &&
953  ((Offset % offsetMinAlign(MI)) == 0)) ||
954  OpC == TargetOpcode::STACKMAP ||
955  OpC == TargetOpcode::PATCHPOINT)) {
956  MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
957  return;
958  }
959 
960  // The offset doesn't fit into a single register, scavenge one to build the
961  // offset in.
962 
963  bool is64Bit = TM.isPPC64();
964  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
965  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
966  const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
967  unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC),
968  SReg = MF.getRegInfo().createVirtualRegister(RC);
969 
970  // Insert a set of rA with the full offset value before the ld, st, or add
971  if (isInt<16>(Offset))
972  BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), SReg)
973  .addImm(Offset);
974  else {
975  BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
976  .addImm(Offset >> 16);
977  BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
978  .addReg(SRegHi, RegState::Kill)
979  .addImm(Offset);
980  }
981 
982  // Convert into indexed form of the instruction:
983  //
984  // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
985  // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
986  unsigned OperandBase;
987 
988  if (noImmForm)
989  OperandBase = 1;
990  else if (OpC != TargetOpcode::INLINEASM) {
991  assert(ImmToIdxMap.count(OpC) &&
992  "No indexed form of load or store available!");
993  unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
994  MI.setDesc(TII.get(NewOpcode));
995  OperandBase = 1;
996  } else {
997  OperandBase = OffsetOperandNo;
998  }
999 
1000  unsigned StackReg = MI.getOperand(FIOperandNum).getReg();
1001  MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
1002  MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
1003 }
1004 
1006  const PPCFrameLowering *TFI = getFrameLowering(MF);
1007 
1008  if (!TM.isPPC64())
1009  return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
1010  else
1011  return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
1012 }
1013 
1015  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1016  if (!hasBasePointer(MF))
1017  return getFrameRegister(MF);
1018 
1019  if (TM.isPPC64())
1020  return PPC::X30;
1021 
1022  if (Subtarget.isSVR4ABI() && TM.isPositionIndependent())
1023  return PPC::R29;
1024 
1025  return PPC::R30;
1026 }
1027 
1029  if (!EnableBasePointer)
1030  return false;
1031  if (AlwaysBasePointer)
1032  return true;
1033 
1034  // If we need to realign the stack, then the stack pointer can no longer
1035  // serve as an offset into the caller's stack space. As a result, we need a
1036  // base pointer.
1037  return needsStackRealignment(MF);
1038 }
1039 
1040 /// Returns true if the instruction's frame index
1041 /// reference would be better served by a base register other than FP
1042 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
1043 /// references it should create new base registers for.
1044 bool PPCRegisterInfo::
1046  assert(Offset < 0 && "Local offset must be negative");
1047 
1048  // It's the load/store FI references that cause issues, as it can be difficult
1049  // to materialize the offset if it won't fit in the literal field. Estimate
1050  // based on the size of the local frame and some conservative assumptions
1051  // about the rest of the stack frame (note, this is pre-regalloc, so
1052  // we don't know everything for certain yet) whether this offset is likely
1053  // to be out of range of the immediate. Return true if so.
1054 
1055  // We only generate virtual base registers for loads and stores that have
1056  // an r+i form. Return false for everything else.
1057  unsigned OpC = MI->getOpcode();
1058  if (!ImmToIdxMap.count(OpC))
1059  return false;
1060 
1061  // Don't generate a new virtual base register just to add zero to it.
1062  if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) &&
1063  MI->getOperand(2).getImm() == 0)
1064  return false;
1065 
1066  MachineBasicBlock &MBB = *MI->getParent();
1067  MachineFunction &MF = *MBB.getParent();
1068  const PPCFrameLowering *TFI = getFrameLowering(MF);
1069  unsigned StackEst = TFI->determineFrameLayout(MF, false, true);
1070 
1071  // If we likely don't need a stack frame, then we probably don't need a
1072  // virtual base register either.
1073  if (!StackEst)
1074  return false;
1075 
1076  // Estimate an offset from the stack pointer.
1077  // The incoming offset is relating to the SP at the start of the function,
1078  // but when we access the local it'll be relative to the SP after local
1079  // allocation, so adjust our SP-relative offset by that allocation size.
1080  Offset += StackEst;
1081 
1082  // The frame pointer will point to the end of the stack, so estimate the
1083  // offset as the difference between the object offset and the FP location.
1084  return !isFrameOffsetLegal(MI, getBaseRegister(MF), Offset);
1085 }
1086 
1087 /// Insert defining instruction(s) for BaseReg to
1088 /// be a pointer to FrameIdx at the beginning of the basic block.
1089 void PPCRegisterInfo::
1091  unsigned BaseReg, int FrameIdx,
1092  int64_t Offset) const {
1093  unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI;
1094 
1096  DebugLoc DL; // Defaults to "unknown"
1097  if (Ins != MBB->end())
1098  DL = Ins->getDebugLoc();
1099 
1100  const MachineFunction &MF = *MBB->getParent();
1101  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1102  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1103  const MCInstrDesc &MCID = TII.get(ADDriOpc);
1105  MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
1106 
1107  BuildMI(*MBB, Ins, DL, MCID, BaseReg)
1108  .addFrameIndex(FrameIdx).addImm(Offset);
1109 }
1110 
1112  int64_t Offset) const {
1113  unsigned FIOperandNum = 0;
1114  while (!MI.getOperand(FIOperandNum).isFI()) {
1115  ++FIOperandNum;
1116  assert(FIOperandNum < MI.getNumOperands() &&
1117  "Instr doesn't have FrameIndex operand!");
1118  }
1119 
1120  MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false);
1121  unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
1122  Offset += MI.getOperand(OffsetOperandNo).getImm();
1123  MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
1124 
1125  MachineBasicBlock &MBB = *MI.getParent();
1126  MachineFunction &MF = *MBB.getParent();
1127  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1128  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1129  const MCInstrDesc &MCID = MI.getDesc();
1131  MRI.constrainRegClass(BaseReg,
1132  TII.getRegClass(MCID, FIOperandNum, this, MF));
1133 }
1134 
1136  unsigned BaseReg,
1137  int64_t Offset) const {
1138  unsigned FIOperandNum = 0;
1139  while (!MI->getOperand(FIOperandNum).isFI()) {
1140  ++FIOperandNum;
1141  assert(FIOperandNum < MI->getNumOperands() &&
1142  "Instr doesn't have FrameIndex operand!");
1143  }
1144 
1145  unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum);
1146  Offset += MI->getOperand(OffsetOperandNo).getImm();
1147 
1148  return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
1149  MI->getOpcode() == TargetOpcode::STACKMAP ||
1150  MI->getOpcode() == TargetOpcode::PATCHPOINT ||
1151  (isInt<16>(Offset) && (Offset % offsetMinAlign(*MI)) == 0);
1152 }
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
DILocation * get() const
Get the underlying DILocation.
Definition: DebugLoc.cpp:22
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:241
bool isAllocatable(unsigned PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn&#39;t been...
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
Returns true if the instruction&#39;s frame index reference would be better served by a base register oth...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:285
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:160
unsigned getReg() const
getReg - Returns the register number.
The following two target-specific nodes are used for calls through function pointers in the 64-bit SV...
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
unsigned Reg
bool hasVSX() const
Definition: PPCSubtarget.h:243
bool isInlineAsm() const
Definition: MachineInstr.h:855
bool test(unsigned Idx) const
Definition: BitVector.h:502
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:307
void lowerCRBitRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:298
STATISTIC(NumFunctions, "Total number of functions")
A debug info location.
Definition: DebugLoc.h:34
void lowerDynamicAreaOffset(MachineBasicBlock::iterator II) const
#define R2(n)
void lowerCRSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerCRSpilling - Generate the code for spilling a CR register.
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:314
static unsigned getOffsetONFromFION(const MachineInstr &MI, unsigned FIOperandNum)
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:311
void lowerCRRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
bool isCallerPreservedPhysReg(unsigned PhysReg, const MachineFunction &MF) const override
unsigned getID() const
Return the register class ID number.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:636
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:308
unsigned getFrameRegister(const MachineFunction &MF) const override
bool hasP9Vector() const
Definition: PPCSubtarget.h:247
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
void lowerVRSAVESpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
bool hasBasePointer(const MachineFunction &MF) const
void adjustStackMapLiveOutMask(uint32_t *Mask) const override
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to compute an offset from native ...
unsigned getKillRegState(bool B)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
TargetInstrInfo - Interface to description of machine instruction set.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:146
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getBaseRegister(const MachineFunction &MF) const
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:410
This file declares the machine register scavenger class.
void lowerVRSAVERestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static bool is64Bit(const char *name)
This file contains the declarations for the subclasses of Constant, which represent the different fla...
static unsigned offsetMinAlign(const MachineInstr &MI)
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
Definition: MachineInstr.h:983
Common code between 32-bit and 64-bit PowerPC targets.
const MachineInstrBuilder & addFrameIndex(int Idx) const
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
PPCRegisterInfo(const PPCTargetMachine &TM)
static unsigned getCRFromCRBit(unsigned SrcReg)
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
const uint32_t * getNoPreservedMask() const override
bool hasP8Vector() const
Definition: PPCSubtarget.h:244
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
static cl::opt< bool > EnableGPRToVecSpills("ppc-enable-gpr-to-vsr-spills", cl::Hidden, cl::init(false), cl::desc("Enable spills from gpr to vsr rather than stack"))
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
static cl::opt< bool > AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false), cl::desc("Force the use of a base pointer in every function"))
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:199
const PPCInstrInfo * getInstrInfo() const override
Definition: PPCSubtarget.h:180
bool isDarwinABI() const
Definition: PPCSubtarget.h:306
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
void lowerCRBitSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:156
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:60
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:363
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool isPositionIndependent() const
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Return the register class to use to hold pointers.
#define I(x, y, z)
Definition: MD5.cpp:58
bool hasInlineAsm() const
Returns true if the function contains any inline assembly.
static cl::opt< bool > StackPtrConst("ppc-stack-ptr-caller-preserved", cl::desc("Consider R1 caller preserved so stack saves of " "caller preserved registers can be LICM candidates"), cl::init(true), cl::Hidden)
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
bool hasAltivec() const
Definition: PPCSubtarget.h:240
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:141
const unsigned Kind
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void lowerDynamicAlloc(MachineBasicBlock::iterator II) const
lowerDynamicAlloc - Generate the code for allocating an object in the current frame.
static cl::opt< bool > EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true), cl::desc("Enable use of a base pointer for complex stack frames"))
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
unsigned determineFrameLayout(MachineFunction &MF, bool UpdateMF=true, bool UseEstimate=false) const
determineFrameLayout - Determine the size of the frame and maximum call frame size.
IRTranslator LLVM IR MI
bool isSVR4ABI() const
Definition: PPCSubtarget.h:307
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:316
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const override