LLVM  9.0.0svn
PPCRegisterInfo.cpp
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1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the PowerPC implementation of the TargetRegisterInfo
10 // class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCRegisterInfo.h"
15 #include "PPC.h"
16 #include "PPCFrameLowering.h"
17 #include "PPCInstrBuilder.h"
18 #include "PPCMachineFunctionInfo.h"
19 #include "PPCSubtarget.h"
20 #include "PPCTargetMachine.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/Statistic.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/Function.h"
35 #include "llvm/IR/Type.h"
37 #include "llvm/Support/Debug.h"
43 #include <cstdlib>
44 
45 using namespace llvm;
46 
47 #define DEBUG_TYPE "reginfo"
48 
49 #define GET_REGINFO_TARGET_DESC
50 #include "PPCGenRegisterInfo.inc"
51 
52 STATISTIC(InflateGPRC, "Number of gprc inputs for getLargestLegalClass");
53 STATISTIC(InflateGP8RC, "Number of g8rc inputs for getLargestLegalClass");
54 
55 static cl::opt<bool>
56 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true),
57  cl::desc("Enable use of a base pointer for complex stack frames"));
58 
59 static cl::opt<bool>
60 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false),
61  cl::desc("Force the use of a base pointer in every function"));
62 
63 static cl::opt<bool>
64 EnableGPRToVecSpills("ppc-enable-gpr-to-vsr-spills", cl::Hidden, cl::init(false),
65  cl::desc("Enable spills from gpr to vsr rather than stack"));
66 
67 static cl::opt<bool>
68 StackPtrConst("ppc-stack-ptr-caller-preserved",
69  cl::desc("Consider R1 caller preserved so stack saves of "
70  "caller preserved registers can be LICM candidates"),
71  cl::init(true), cl::Hidden);
72 
74  : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR,
75  TM.isPPC64() ? 0 : 1,
76  TM.isPPC64() ? 0 : 1),
77  TM(TM) {
78  ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
79  ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
80  ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
81  ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
82  ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
83  ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
84  ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
85  ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
86  ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32;
87 
88  // 64-bit
89  ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
90  ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
91  ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
92  ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
93  ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
94 
95  // VSX
96  ImmToIdxMap[PPC::DFLOADf32] = PPC::LXSSPX;
97  ImmToIdxMap[PPC::DFLOADf64] = PPC::LXSDX;
98  ImmToIdxMap[PPC::SPILLTOVSR_LD] = PPC::SPILLTOVSR_LDX;
99  ImmToIdxMap[PPC::SPILLTOVSR_ST] = PPC::SPILLTOVSR_STX;
100  ImmToIdxMap[PPC::DFSTOREf32] = PPC::STXSSPX;
101  ImmToIdxMap[PPC::DFSTOREf64] = PPC::STXSDX;
102  ImmToIdxMap[PPC::LXV] = PPC::LXVX;
103  ImmToIdxMap[PPC::LXSD] = PPC::LXSDX;
104  ImmToIdxMap[PPC::LXSSP] = PPC::LXSSPX;
105  ImmToIdxMap[PPC::STXV] = PPC::STXVX;
106  ImmToIdxMap[PPC::STXSD] = PPC::STXSDX;
107  ImmToIdxMap[PPC::STXSSP] = PPC::STXSSPX;
108 
109  // SPE
110  ImmToIdxMap[PPC::EVLDD] = PPC::EVLDDX;
111  ImmToIdxMap[PPC::EVSTDD] = PPC::EVSTDDX;
112  ImmToIdxMap[PPC::SPESTW] = PPC::SPESTWX;
113  ImmToIdxMap[PPC::SPELWZ] = PPC::SPELWZX;
114 }
115 
116 /// getPointerRegClass - Return the register class to use to hold pointers.
117 /// This is used for addressing modes.
118 const TargetRegisterClass *
120  const {
121  // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value
122  // when it checks for ZERO folding.
123  if (Kind == 1) {
124  if (TM.isPPC64())
125  return &PPC::G8RC_NOX0RegClass;
126  return &PPC::GPRC_NOR0RegClass;
127  }
128 
129  if (TM.isPPC64())
130  return &PPC::G8RCRegClass;
131  return &PPC::GPRCRegClass;
132 }
133 
134 const MCPhysReg*
136  const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
138  if (Subtarget.hasVSX())
139  return CSR_64_AllRegs_VSX_SaveList;
140  if (Subtarget.hasAltivec())
141  return CSR_64_AllRegs_Altivec_SaveList;
142  return CSR_64_AllRegs_SaveList;
143  }
144 
145  if (Subtarget.isDarwinABI())
146  return TM.isPPC64()
147  ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_SaveList
148  : CSR_Darwin64_SaveList)
149  : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_SaveList
150  : CSR_Darwin32_SaveList);
151 
152  if (TM.isPPC64() && MF->getInfo<PPCFunctionInfo>()->isSplitCSR())
153  return CSR_SRV464_TLS_PE_SaveList;
154 
155  if (Subtarget.hasSPE())
156  return CSR_SVR432_SPE_SaveList;
157 
158  // On PPC64, we might need to save r2 (but only if it is not reserved).
159  bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2);
160 
162  return TM.isPPC64()
163  ? (Subtarget.hasAltivec()
164  ? (SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList
165  : CSR_SVR64_ColdCC_Altivec_SaveList)
166  : (SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList
167  : CSR_SVR64_ColdCC_SaveList))
168  : (Subtarget.hasAltivec() ? CSR_SVR32_ColdCC_Altivec_SaveList
169  : CSR_SVR32_ColdCC_SaveList);
170  }
171 
172  return TM.isPPC64()
173  ? (Subtarget.hasAltivec()
174  ? (SaveR2 ? CSR_SVR464_R2_Altivec_SaveList
175  : CSR_SVR464_Altivec_SaveList)
176  : (SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList))
177  : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_SaveList
178  : CSR_SVR432_SaveList);
179 }
180 
181 const MCPhysReg *
183  assert(MF && "Invalid MachineFunction pointer.");
184  const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
185  if (Subtarget.isDarwinABI())
186  return nullptr;
187  if (!TM.isPPC64())
188  return nullptr;
190  return nullptr;
191  if (!MF->getInfo<PPCFunctionInfo>()->isSplitCSR())
192  return nullptr;
193 
194  // On PPC64, we might need to save r2 (but only if it is not reserved).
195  bool SaveR2 = !getReservedRegs(*MF).test(PPC::X2);
196  if (Subtarget.hasAltivec())
197  return SaveR2
198  ? CSR_SVR464_R2_Altivec_ViaCopy_SaveList
199  : CSR_SVR464_Altivec_ViaCopy_SaveList;
200  else
201  return SaveR2
202  ? CSR_SVR464_R2_ViaCopy_SaveList
203  : CSR_SVR464_ViaCopy_SaveList;
204 }
205 
206 const uint32_t *
208  CallingConv::ID CC) const {
209  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
210  if (CC == CallingConv::AnyReg) {
211  if (Subtarget.hasVSX())
212  return CSR_64_AllRegs_VSX_RegMask;
213  if (Subtarget.hasAltivec())
214  return CSR_64_AllRegs_Altivec_RegMask;
215  return CSR_64_AllRegs_RegMask;
216  }
217 
218  if (Subtarget.isDarwinABI())
219  return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_RegMask
220  : CSR_Darwin64_RegMask)
221  : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_RegMask
222  : CSR_Darwin32_RegMask);
223 
224  if (CC == CallingConv::Cold) {
225  return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR64_ColdCC_Altivec_RegMask
226  : CSR_SVR64_ColdCC_RegMask)
227  : (Subtarget.hasAltivec() ? CSR_SVR32_ColdCC_Altivec_RegMask
228  : CSR_SVR32_ColdCC_RegMask);
229  }
230 
231  return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask
232  : CSR_SVR464_RegMask)
233  : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask
234  : CSR_SVR432_RegMask);
235 }
236 
237 const uint32_t*
239  return CSR_NoRegs_RegMask;
240 }
241 
243  for (unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8, PPC::RM})
244  Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32));
245 }
246 
248  BitVector Reserved(getNumRegs());
249  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
250  const PPCFrameLowering *TFI = getFrameLowering(MF);
251 
252  // The ZERO register is not really a register, but the representation of r0
253  // when used in instructions that treat r0 as the constant 0.
254  markSuperRegs(Reserved, PPC::ZERO);
255 
256  // The FP register is also not really a register, but is the representation
257  // of the frame pointer register used by ISD::FRAMEADDR.
258  markSuperRegs(Reserved, PPC::FP);
259 
260  // The BP register is also not really a register, but is the representation
261  // of the base pointer register used by setjmp.
262  markSuperRegs(Reserved, PPC::BP);
263 
264  // The counter registers must be reserved so that counter-based loops can
265  // be correctly formed (and the mtctr instructions are not DCE'd).
266  markSuperRegs(Reserved, PPC::CTR);
267  markSuperRegs(Reserved, PPC::CTR8);
268 
269  markSuperRegs(Reserved, PPC::R1);
270  markSuperRegs(Reserved, PPC::LR);
271  markSuperRegs(Reserved, PPC::LR8);
272  markSuperRegs(Reserved, PPC::RM);
273 
274  if (!Subtarget.isDarwinABI() || !Subtarget.hasAltivec())
275  markSuperRegs(Reserved, PPC::VRSAVE);
276 
277  // The SVR4 ABI reserves r2 and r13
278  if (Subtarget.isSVR4ABI()) {
279  // We only reserve r2 if we need to use the TOC pointer. If we have no
280  // explicit uses of the TOC pointer (meaning we're a leaf function with
281  // no constant-pool loads, etc.) and we have no potential uses inside an
282  // inline asm block, then we can treat r2 has an ordinary callee-saved
283  // register.
284  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
285  if (!TM.isPPC64() || FuncInfo->usesTOCBasePtr() || MF.hasInlineAsm())
286  markSuperRegs(Reserved, PPC::R2); // System-reserved register
287  markSuperRegs(Reserved, PPC::R13); // Small Data Area pointer register
288  }
289 
290  // On PPC64, r13 is the thread pointer. Never allocate this register.
291  if (TM.isPPC64())
292  markSuperRegs(Reserved, PPC::R13);
293 
294  if (TFI->needsFP(MF))
295  markSuperRegs(Reserved, PPC::R31);
296 
297  bool IsPositionIndependent = TM.isPositionIndependent();
298  if (hasBasePointer(MF)) {
299  if (Subtarget.isSVR4ABI() && !TM.isPPC64() && IsPositionIndependent)
300  markSuperRegs(Reserved, PPC::R29);
301  else
302  markSuperRegs(Reserved, PPC::R30);
303  }
304 
305  if (Subtarget.isSVR4ABI() && !TM.isPPC64() && IsPositionIndependent)
306  markSuperRegs(Reserved, PPC::R30);
307 
308  // Reserve Altivec registers when Altivec is unavailable.
309  if (!Subtarget.hasAltivec())
310  for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(),
311  IE = PPC::VRRCRegClass.end(); I != IE; ++I)
312  markSuperRegs(Reserved, *I);
313 
314  assert(checkAllSuperRegsMarked(Reserved));
315  return Reserved;
316 }
317 
319  const MachineFunction &MF) const {
321  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
322  const MachineFrameInfo &MFI = MF.getFrameInfo();
323  if (!TM.isPPC64())
324  return false;
325 
326  if (!Subtarget.isSVR4ABI())
327  return false;
328  if (PhysReg == PPC::X2)
329  // X2 is guaranteed to be preserved within a function if it is reserved.
330  // The reason it's reserved is that it's the TOC pointer (and the function
331  // uses the TOC). In functions where it isn't reserved (i.e. leaf functions
332  // with no TOC access), we can't claim that it is preserved.
333  return (getReservedRegs(MF).test(PPC::X2));
334  if (StackPtrConst && (PhysReg == PPC::X1) && !MFI.hasVarSizedObjects()
335  && !MFI.hasOpaqueSPAdjustment())
336  // The value of the stack pointer does not change within a function after
337  // the prologue and before the epilogue if there are no dynamic allocations
338  // and no inline asm which clobbers X1.
339  return true;
340  return false;
341 }
342 
344  MachineFunction &MF) const {
345  const PPCFrameLowering *TFI = getFrameLowering(MF);
346  const unsigned DefaultSafety = 1;
347 
348  switch (RC->getID()) {
349  default:
350  return 0;
351  case PPC::G8RC_NOX0RegClassID:
352  case PPC::GPRC_NOR0RegClassID:
353  case PPC::SPERCRegClassID:
354  case PPC::SPE4RCRegClassID:
355  case PPC::G8RCRegClassID:
356  case PPC::GPRCRegClassID: {
357  unsigned FP = TFI->hasFP(MF) ? 1 : 0;
358  return 32 - FP - DefaultSafety;
359  }
360  case PPC::F8RCRegClassID:
361  case PPC::F4RCRegClassID:
362  case PPC::QFRCRegClassID:
363  case PPC::QSRCRegClassID:
364  case PPC::QBRCRegClassID:
365  case PPC::VRRCRegClassID:
366  case PPC::VFRCRegClassID:
367  case PPC::VSLRCRegClassID:
368  return 32 - DefaultSafety;
369  case PPC::VSRCRegClassID:
370  case PPC::VSFRCRegClassID:
371  case PPC::VSSRCRegClassID:
372  return 64 - DefaultSafety;
373  case PPC::CRRCRegClassID:
374  return 8 - DefaultSafety;
375  }
376 }
377 
378 const TargetRegisterClass *
380  const MachineFunction &MF) const {
381  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
382  if (Subtarget.hasVSX()) {
383  // With VSX, we can inflate various sub-register classes to the full VSX
384  // register set.
385 
386  // For Power9 we allow the user to enable GPR to vector spills.
387  // FIXME: Currently limited to spilling GP8RC. A follow on patch will add
388  // support to spill GPRC.
389  if (TM.isELFv2ABI()) {
390  if (Subtarget.hasP9Vector() && EnableGPRToVecSpills &&
391  RC == &PPC::G8RCRegClass) {
392  InflateGP8RC++;
393  return &PPC::SPILLTOVSRRCRegClass;
394  }
395  if (RC == &PPC::GPRCRegClass && EnableGPRToVecSpills)
396  InflateGPRC++;
397  }
398  if (RC == &PPC::F8RCRegClass)
399  return &PPC::VSFRCRegClass;
400  else if (RC == &PPC::VRRCRegClass)
401  return &PPC::VSRCRegClass;
402  else if (RC == &PPC::F4RCRegClass && Subtarget.hasP8Vector())
403  return &PPC::VSSRCRegClass;
404  }
405 
407 }
408 
409 //===----------------------------------------------------------------------===//
410 // Stack Frame Processing methods
411 //===----------------------------------------------------------------------===//
412 
413 /// lowerDynamicAlloc - Generate the code for allocating an object in the
414 /// current frame. The sequence of code will be in the general form
415 ///
416 /// addi R0, SP, \#frameSize ; get the address of the previous frame
417 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
418 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
419 ///
421  // Get the instruction.
422  MachineInstr &MI = *II;
423  // Get the instruction's basic block.
424  MachineBasicBlock &MBB = *MI.getParent();
425  // Get the basic block's function.
426  MachineFunction &MF = *MBB.getParent();
427  // Get the frame info.
428  MachineFrameInfo &MFI = MF.getFrameInfo();
429  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
430  // Get the instruction info.
431  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
432  // Determine whether 64-bit pointers are used.
433  bool LP64 = TM.isPPC64();
434  DebugLoc dl = MI.getDebugLoc();
435 
436  // Get the maximum call stack size.
437  unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
438  // Get the total frame size.
439  unsigned FrameSize = MFI.getStackSize();
440 
441  // Get stack alignments.
442  const PPCFrameLowering *TFI = getFrameLowering(MF);
443  unsigned TargetAlign = TFI->getStackAlignment();
444  unsigned MaxAlign = MFI.getMaxAlignment();
445  assert((maxCallFrameSize & (MaxAlign-1)) == 0 &&
446  "Maximum call-frame size not sufficiently aligned");
447 
448  // Determine the previous frame's address. If FrameSize can't be
449  // represented as 16 bits or we need special alignment, then we load the
450  // previous frame's address from 0(SP). Why not do an addis of the hi?
451  // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
452  // Constructing the constant and adding would take 3 instructions.
453  // Fortunately, a frame greater than 32K is rare.
454  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
455  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
456  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
457 
458  if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
459  if (LP64)
460  BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), Reg)
461  .addReg(PPC::X31)
462  .addImm(FrameSize);
463  else
464  BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
465  .addReg(PPC::R31)
466  .addImm(FrameSize);
467  } else if (LP64) {
468  BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
469  .addImm(0)
470  .addReg(PPC::X1);
471  } else {
472  BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
473  .addImm(0)
474  .addReg(PPC::R1);
475  }
476 
477  bool KillNegSizeReg = MI.getOperand(1).isKill();
478  unsigned NegSizeReg = MI.getOperand(1).getReg();
479 
480  // Grow the stack and update the stack pointer link, then determine the
481  // address of new allocated space.
482  if (LP64) {
483  if (MaxAlign > TargetAlign) {
484  unsigned UnalNegSizeReg = NegSizeReg;
485  NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
486 
487  // Unfortunately, there is no andi, only andi., and we can't insert that
488  // here because we might clobber cr0 while it is live.
489  BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
490  .addImm(~(MaxAlign-1));
491 
492  unsigned NegSizeReg1 = NegSizeReg;
493  NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
494  BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
495  .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
496  .addReg(NegSizeReg1, RegState::Kill);
497  KillNegSizeReg = true;
498  }
499 
500  BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
501  .addReg(Reg, RegState::Kill)
502  .addReg(PPC::X1)
503  .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
504  BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
505  .addReg(PPC::X1)
506  .addImm(maxCallFrameSize);
507  } else {
508  if (MaxAlign > TargetAlign) {
509  unsigned UnalNegSizeReg = NegSizeReg;
510  NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
511 
512  // Unfortunately, there is no andi, only andi., and we can't insert that
513  // here because we might clobber cr0 while it is live.
514  BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg)
515  .addImm(~(MaxAlign-1));
516 
517  unsigned NegSizeReg1 = NegSizeReg;
518  NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
519  BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg)
520  .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
521  .addReg(NegSizeReg1, RegState::Kill);
522  KillNegSizeReg = true;
523  }
524 
525  BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
526  .addReg(Reg, RegState::Kill)
527  .addReg(PPC::R1)
528  .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
529  BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
530  .addReg(PPC::R1)
531  .addImm(maxCallFrameSize);
532  }
533 
534  // Discard the DYNALLOC instruction.
535  MBB.erase(II);
536 }
537 
539  MachineBasicBlock::iterator II) const {
540  // Get the instruction.
541  MachineInstr &MI = *II;
542  // Get the instruction's basic block.
543  MachineBasicBlock &MBB = *MI.getParent();
544  // Get the basic block's function.
545  MachineFunction &MF = *MBB.getParent();
546  // Get the frame info.
547  MachineFrameInfo &MFI = MF.getFrameInfo();
548  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
549  // Get the instruction info.
550  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
551 
552  unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
553  bool is64Bit = TM.isPPC64();
554  DebugLoc dl = MI.getDebugLoc();
555  BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI),
556  MI.getOperand(0).getReg())
557  .addImm(maxCallFrameSize);
558  MBB.erase(II);
559 }
560 
561 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
562 /// reserving a whole register (R0), we scrounge for one here. This generates
563 /// code like this:
564 ///
565 /// mfcr rA ; Move the conditional register into GPR rA.
566 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
567 /// stw rA, FI ; Store rA to the frame.
568 ///
570  unsigned FrameIndex) const {
571  // Get the instruction.
572  MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
573  // Get the instruction's basic block.
574  MachineBasicBlock &MBB = *MI.getParent();
575  MachineFunction &MF = *MBB.getParent();
576  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
577  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
578  DebugLoc dl = MI.getDebugLoc();
579 
580  bool LP64 = TM.isPPC64();
581  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
582  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
583 
584  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
585  unsigned SrcReg = MI.getOperand(0).getReg();
586 
587  // We need to store the CR in the low 4-bits of the saved value. First, issue
588  // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg.
589  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
590  .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
591 
592  // If the saved register wasn't CR0, shift the bits left so that they are in
593  // CR0's slot.
594  if (SrcReg != PPC::CR0) {
595  unsigned Reg1 = Reg;
596  Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
597 
598  // rlwinm rA, rA, ShiftBits, 0, 31.
599  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
600  .addReg(Reg1, RegState::Kill)
601  .addImm(getEncodingValue(SrcReg) * 4)
602  .addImm(0)
603  .addImm(31);
604  }
605 
606  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
607  .addReg(Reg, RegState::Kill),
608  FrameIndex);
609 
610  // Discard the pseudo instruction.
611  MBB.erase(II);
612 }
613 
615  unsigned FrameIndex) const {
616  // Get the instruction.
617  MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
618  // Get the instruction's basic block.
619  MachineBasicBlock &MBB = *MI.getParent();
620  MachineFunction &MF = *MBB.getParent();
621  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
622  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
623  DebugLoc dl = MI.getDebugLoc();
624 
625  bool LP64 = TM.isPPC64();
626  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
627  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
628 
629  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
630  unsigned DestReg = MI.getOperand(0).getReg();
631  assert(MI.definesRegister(DestReg) &&
632  "RESTORE_CR does not define its destination");
633 
634  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
635  Reg), FrameIndex);
636 
637  // If the reloaded register isn't CR0, shift the bits right so that they are
638  // in the right CR's slot.
639  if (DestReg != PPC::CR0) {
640  unsigned Reg1 = Reg;
641  Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
642 
643  unsigned ShiftBits = getEncodingValue(DestReg)*4;
644  // rlwinm r11, r11, 32-ShiftBits, 0, 31.
645  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
646  .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
647  .addImm(31);
648  }
649 
650  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg)
651  .addReg(Reg, RegState::Kill);
652 
653  // Discard the pseudo instruction.
654  MBB.erase(II);
655 }
656 
658  unsigned FrameIndex) const {
659  // Get the instruction.
660  MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset>
661  // Get the instruction's basic block.
662  MachineBasicBlock &MBB = *MI.getParent();
663  MachineFunction &MF = *MBB.getParent();
664  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
665  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
666  DebugLoc dl = MI.getDebugLoc();
667 
668  bool LP64 = TM.isPPC64();
669  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
670  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
671 
672  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
673  unsigned SrcReg = MI.getOperand(0).getReg();
674 
675  // We need to move the CR field that contains the CR bit we are spilling.
676  // The super register may not be explicitly defined (i.e. it can be defined
677  // by a CR-logical that only defines the subreg) so we state that the CR
678  // field is undef. Also, in order to preserve the kill flag on the CR bit,
679  // we add it as an implicit use.
680  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
681  .addReg(getCRFromCRBit(SrcReg), RegState::Undef)
682  .addReg(SrcReg,
684 
685  // If the saved register wasn't CR0LT, shift the bits left so that the bit to
686  // store is the first one. Mask all but that bit.
687  unsigned Reg1 = Reg;
688  Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
689 
690  // rlwinm rA, rA, ShiftBits, 0, 0.
691  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
692  .addReg(Reg1, RegState::Kill)
693  .addImm(getEncodingValue(SrcReg))
694  .addImm(0).addImm(0);
695 
696  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
697  .addReg(Reg, RegState::Kill),
698  FrameIndex);
699 
700  // Discard the pseudo instruction.
701  MBB.erase(II);
702 }
703 
705  unsigned FrameIndex) const {
706  // Get the instruction.
707  MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset>
708  // Get the instruction's basic block.
709  MachineBasicBlock &MBB = *MI.getParent();
710  MachineFunction &MF = *MBB.getParent();
711  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
712  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
713  DebugLoc dl = MI.getDebugLoc();
714 
715  bool LP64 = TM.isPPC64();
716  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
717  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
718 
719  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
720  unsigned DestReg = MI.getOperand(0).getReg();
721  assert(MI.definesRegister(DestReg) &&
722  "RESTORE_CRBIT does not define its destination");
723 
724  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
725  Reg), FrameIndex);
726 
727  BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg);
728 
729  unsigned RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
730  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO)
731  .addReg(getCRFromCRBit(DestReg));
732 
733  unsigned ShiftBits = getEncodingValue(DestReg);
734  // rlwimi r11, r10, 32-ShiftBits, ..., ...
735  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO)
736  .addReg(RegO, RegState::Kill)
737  .addReg(Reg, RegState::Kill)
738  .addImm(ShiftBits ? 32 - ShiftBits : 0)
739  .addImm(ShiftBits)
740  .addImm(ShiftBits);
741 
742  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF),
743  getCRFromCRBit(DestReg))
744  .addReg(RegO, RegState::Kill)
745  // Make sure we have a use dependency all the way through this
746  // sequence of instructions. We can't have the other bits in the CR
747  // modified in between the mfocrf and the mtocrf.
749 
750  // Discard the pseudo instruction.
751  MBB.erase(II);
752 }
753 
755  unsigned FrameIndex) const {
756  // Get the instruction.
757  MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset>
758  // Get the instruction's basic block.
759  MachineBasicBlock &MBB = *MI.getParent();
760  MachineFunction &MF = *MBB.getParent();
761  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
762  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
763  DebugLoc dl = MI.getDebugLoc();
764 
765  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
766  unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
767  unsigned SrcReg = MI.getOperand(0).getReg();
768 
769  BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg)
770  .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
771 
773  BuildMI(MBB, II, dl, TII.get(PPC::STW)).addReg(Reg, RegState::Kill),
774  FrameIndex);
775 
776  // Discard the pseudo instruction.
777  MBB.erase(II);
778 }
779 
781  unsigned FrameIndex) const {
782  // Get the instruction.
783  MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset>
784  // Get the instruction's basic block.
785  MachineBasicBlock &MBB = *MI.getParent();
786  MachineFunction &MF = *MBB.getParent();
787  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
788  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
789  DebugLoc dl = MI.getDebugLoc();
790 
791  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
792  unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
793  unsigned DestReg = MI.getOperand(0).getReg();
794  assert(MI.definesRegister(DestReg) &&
795  "RESTORE_VRSAVE does not define its destination");
796 
797  addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ),
798  Reg), FrameIndex);
799 
800  BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg)
801  .addReg(Reg, RegState::Kill);
802 
803  // Discard the pseudo instruction.
804  MBB.erase(II);
805 }
806 
808  unsigned Reg, int &FrameIdx) const {
809  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
810  // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4
811  // ABI, return true to prevent allocating an additional frame slot.
812  // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0
813  // is arbitrary and will be subsequently ignored. For 32-bit, we have
814  // previously created the stack slot if needed, so return its FrameIdx.
815  if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) {
816  if (TM.isPPC64())
817  FrameIdx = 0;
818  else {
819  const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
820  FrameIdx = FI->getCRSpillFrameIndex();
821  }
822  return true;
823  }
824  return false;
825 }
826 
827 // If the offset must be a multiple of some value, return what that value is.
828 static unsigned offsetMinAlign(const MachineInstr &MI) {
829  unsigned OpC = MI.getOpcode();
830 
831  switch (OpC) {
832  default:
833  return 1;
834  case PPC::LWA:
835  case PPC::LWA_32:
836  case PPC::LD:
837  case PPC::LDU:
838  case PPC::STD:
839  case PPC::STDU:
840  case PPC::DFLOADf32:
841  case PPC::DFLOADf64:
842  case PPC::DFSTOREf32:
843  case PPC::DFSTOREf64:
844  case PPC::LXSD:
845  case PPC::LXSSP:
846  case PPC::STXSD:
847  case PPC::STXSSP:
848  return 4;
849  case PPC::LXV:
850  case PPC::STXV:
851  return 16;
852  }
853 }
854 
855 // Return the OffsetOperandNo given the FIOperandNum (and the instruction).
856 static unsigned getOffsetONFromFION(const MachineInstr &MI,
857  unsigned FIOperandNum) {
858  // Take into account whether it's an add or mem instruction
859  unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
860  if (MI.isInlineAsm())
861  OffsetOperandNo = FIOperandNum - 1;
862  else if (MI.getOpcode() == TargetOpcode::STACKMAP ||
863  MI.getOpcode() == TargetOpcode::PATCHPOINT)
864  OffsetOperandNo = FIOperandNum + 1;
865 
866  return OffsetOperandNo;
867 }
868 
869 void
871  int SPAdj, unsigned FIOperandNum,
872  RegScavenger *RS) const {
873  assert(SPAdj == 0 && "Unexpected");
874 
875  // Get the instruction.
876  MachineInstr &MI = *II;
877  // Get the instruction's basic block.
878  MachineBasicBlock &MBB = *MI.getParent();
879  // Get the basic block's function.
880  MachineFunction &MF = *MBB.getParent();
881  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
882  // Get the instruction info.
883  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
884  // Get the frame info.
885  MachineFrameInfo &MFI = MF.getFrameInfo();
886  DebugLoc dl = MI.getDebugLoc();
887 
888  unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
889 
890  // Get the frame index.
891  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
892 
893  // Get the frame pointer save index. Users of this index are primarily
894  // DYNALLOC instructions.
896  int FPSI = FI->getFramePointerSaveIndex();
897  // Get the instruction opcode.
898  unsigned OpC = MI.getOpcode();
899 
900  if ((OpC == PPC::DYNAREAOFFSET || OpC == PPC::DYNAREAOFFSET8)) {
902  return;
903  }
904 
905  // Special case for dynamic alloca.
906  if (FPSI && FrameIndex == FPSI &&
907  (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
908  lowerDynamicAlloc(II);
909  return;
910  }
911 
912  // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc.
913  if (OpC == PPC::SPILL_CR) {
914  lowerCRSpilling(II, FrameIndex);
915  return;
916  } else if (OpC == PPC::RESTORE_CR) {
917  lowerCRRestore(II, FrameIndex);
918  return;
919  } else if (OpC == PPC::SPILL_CRBIT) {
920  lowerCRBitSpilling(II, FrameIndex);
921  return;
922  } else if (OpC == PPC::RESTORE_CRBIT) {
923  lowerCRBitRestore(II, FrameIndex);
924  return;
925  } else if (OpC == PPC::SPILL_VRSAVE) {
926  lowerVRSAVESpilling(II, FrameIndex);
927  return;
928  } else if (OpC == PPC::RESTORE_VRSAVE) {
929  lowerVRSAVERestore(II, FrameIndex);
930  return;
931  }
932 
933  // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
934  MI.getOperand(FIOperandNum).ChangeToRegister(
935  FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false);
936 
937  // If the instruction is not present in ImmToIdxMap, then it has no immediate
938  // form (and must be r+r).
939  bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP &&
940  OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(OpC);
941 
942  // Now add the frame object offset to the offset from r1.
943  int Offset = MFI.getObjectOffset(FrameIndex);
944  Offset += MI.getOperand(OffsetOperandNo).getImm();
945 
946  // If we're not using a Frame Pointer that has been set to the value of the
947  // SP before having the stack size subtracted from it, then add the stack size
948  // to Offset to get the correct offset.
949  // Naked functions have stack size 0, although getStackSize may not reflect
950  // that because we didn't call all the pieces that compute it for naked
951  // functions.
952  if (!MF.getFunction().hasFnAttribute(Attribute::Naked)) {
953  if (!(hasBasePointer(MF) && FrameIndex < 0))
954  Offset += MFI.getStackSize();
955  }
956 
957  // If we can, encode the offset directly into the instruction. If this is a
958  // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
959  // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
960  // clear can be encoded. This is extremely uncommon, because normally you
961  // only "std" to a stack slot that is at least 4-byte aligned, but it can
962  // happen in invalid code.
963  assert(OpC != PPC::DBG_VALUE &&
964  "This should be handled in a target-independent way");
965  if (!noImmForm && ((isInt<16>(Offset) &&
966  ((Offset % offsetMinAlign(MI)) == 0)) ||
967  OpC == TargetOpcode::STACKMAP ||
968  OpC == TargetOpcode::PATCHPOINT)) {
969  MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
970  return;
971  }
972 
973  // The offset doesn't fit into a single register, scavenge one to build the
974  // offset in.
975 
976  bool is64Bit = TM.isPPC64();
977  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
978  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
979  const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
980  unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC),
981  SReg = MF.getRegInfo().createVirtualRegister(RC);
982 
983  // Insert a set of rA with the full offset value before the ld, st, or add
984  if (isInt<16>(Offset))
985  BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), SReg)
986  .addImm(Offset);
987  else {
988  BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
989  .addImm(Offset >> 16);
990  BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
991  .addReg(SRegHi, RegState::Kill)
992  .addImm(Offset);
993  }
994 
995  // Convert into indexed form of the instruction:
996  //
997  // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
998  // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
999  unsigned OperandBase;
1000 
1001  if (noImmForm)
1002  OperandBase = 1;
1003  else if (OpC != TargetOpcode::INLINEASM) {
1004  assert(ImmToIdxMap.count(OpC) &&
1005  "No indexed form of load or store available!");
1006  unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
1007  MI.setDesc(TII.get(NewOpcode));
1008  OperandBase = 1;
1009  } else {
1010  OperandBase = OffsetOperandNo;
1011  }
1012 
1013  unsigned StackReg = MI.getOperand(FIOperandNum).getReg();
1014  MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
1015  MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
1016 }
1017 
1019  const PPCFrameLowering *TFI = getFrameLowering(MF);
1020 
1021  if (!TM.isPPC64())
1022  return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
1023  else
1024  return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
1025 }
1026 
1028  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1029  if (!hasBasePointer(MF))
1030  return getFrameRegister(MF);
1031 
1032  if (TM.isPPC64())
1033  return PPC::X30;
1034 
1035  if (Subtarget.isSVR4ABI() && TM.isPositionIndependent())
1036  return PPC::R29;
1037 
1038  return PPC::R30;
1039 }
1040 
1042  if (!EnableBasePointer)
1043  return false;
1044  if (AlwaysBasePointer)
1045  return true;
1046 
1047  // If we need to realign the stack, then the stack pointer can no longer
1048  // serve as an offset into the caller's stack space. As a result, we need a
1049  // base pointer.
1050  return needsStackRealignment(MF);
1051 }
1052 
1053 /// Returns true if the instruction's frame index
1054 /// reference would be better served by a base register other than FP
1055 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
1056 /// references it should create new base registers for.
1057 bool PPCRegisterInfo::
1059  assert(Offset < 0 && "Local offset must be negative");
1060 
1061  // It's the load/store FI references that cause issues, as it can be difficult
1062  // to materialize the offset if it won't fit in the literal field. Estimate
1063  // based on the size of the local frame and some conservative assumptions
1064  // about the rest of the stack frame (note, this is pre-regalloc, so
1065  // we don't know everything for certain yet) whether this offset is likely
1066  // to be out of range of the immediate. Return true if so.
1067 
1068  // We only generate virtual base registers for loads and stores that have
1069  // an r+i form. Return false for everything else.
1070  unsigned OpC = MI->getOpcode();
1071  if (!ImmToIdxMap.count(OpC))
1072  return false;
1073 
1074  // Don't generate a new virtual base register just to add zero to it.
1075  if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) &&
1076  MI->getOperand(2).getImm() == 0)
1077  return false;
1078 
1079  MachineBasicBlock &MBB = *MI->getParent();
1080  MachineFunction &MF = *MBB.getParent();
1081  const PPCFrameLowering *TFI = getFrameLowering(MF);
1082  unsigned StackEst = TFI->determineFrameLayout(MF, false, true);
1083 
1084  // If we likely don't need a stack frame, then we probably don't need a
1085  // virtual base register either.
1086  if (!StackEst)
1087  return false;
1088 
1089  // Estimate an offset from the stack pointer.
1090  // The incoming offset is relating to the SP at the start of the function,
1091  // but when we access the local it'll be relative to the SP after local
1092  // allocation, so adjust our SP-relative offset by that allocation size.
1093  Offset += StackEst;
1094 
1095  // The frame pointer will point to the end of the stack, so estimate the
1096  // offset as the difference between the object offset and the FP location.
1097  return !isFrameOffsetLegal(MI, getBaseRegister(MF), Offset);
1098 }
1099 
1100 /// Insert defining instruction(s) for BaseReg to
1101 /// be a pointer to FrameIdx at the beginning of the basic block.
1102 void PPCRegisterInfo::
1104  unsigned BaseReg, int FrameIdx,
1105  int64_t Offset) const {
1106  unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI;
1107 
1109  DebugLoc DL; // Defaults to "unknown"
1110  if (Ins != MBB->end())
1111  DL = Ins->getDebugLoc();
1112 
1113  const MachineFunction &MF = *MBB->getParent();
1114  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1115  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1116  const MCInstrDesc &MCID = TII.get(ADDriOpc);
1118  MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
1119 
1120  BuildMI(*MBB, Ins, DL, MCID, BaseReg)
1121  .addFrameIndex(FrameIdx).addImm(Offset);
1122 }
1123 
1125  int64_t Offset) const {
1126  unsigned FIOperandNum = 0;
1127  while (!MI.getOperand(FIOperandNum).isFI()) {
1128  ++FIOperandNum;
1129  assert(FIOperandNum < MI.getNumOperands() &&
1130  "Instr doesn't have FrameIndex operand!");
1131  }
1132 
1133  MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false);
1134  unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
1135  Offset += MI.getOperand(OffsetOperandNo).getImm();
1136  MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
1137 
1138  MachineBasicBlock &MBB = *MI.getParent();
1139  MachineFunction &MF = *MBB.getParent();
1140  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1141  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1142  const MCInstrDesc &MCID = MI.getDesc();
1144  MRI.constrainRegClass(BaseReg,
1145  TII.getRegClass(MCID, FIOperandNum, this, MF));
1146 }
1147 
1149  unsigned BaseReg,
1150  int64_t Offset) const {
1151  unsigned FIOperandNum = 0;
1152  while (!MI->getOperand(FIOperandNum).isFI()) {
1153  ++FIOperandNum;
1154  assert(FIOperandNum < MI->getNumOperands() &&
1155  "Instr doesn't have FrameIndex operand!");
1156  }
1157 
1158  unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum);
1159  Offset += MI->getOperand(OffsetOperandNo).getImm();
1160 
1161  return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
1162  MI->getOpcode() == TargetOpcode::STACKMAP ||
1163  MI->getOpcode() == TargetOpcode::PATCHPOINT ||
1164  (isInt<16>(Offset) && (Offset % offsetMinAlign(*MI)) == 0);
1165 }
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
DILocation * get() const
Get the underlying DILocation.
Definition: DebugLoc.cpp:21
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:249
bool isAllocatable(unsigned PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn&#39;t been...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
Returns true if the instruction&#39;s frame index reference would be better served by a base register oth...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:382
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
The following two target-specific nodes are used for calls through function pointers in the 64-bit SV...
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
unsigned Reg
bool hasVSX() const
Definition: PPCSubtarget.h:245
bool isInlineAsm() const
bool test(unsigned Idx) const
Definition: BitVector.h:501
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:320
void lowerCRBitRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:305
STATISTIC(NumFunctions, "Total number of functions")
A debug info location.
Definition: DebugLoc.h:33
void lowerDynamicAreaOffset(MachineBasicBlock::iterator II) const
#define R2(n)
bool hasSPE() const
Definition: PPCSubtarget.h:242
void lowerCRSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerCRSpilling - Generate the code for spilling a CR register.
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:411
static unsigned getOffsetONFromFION(const MachineInstr &MI, unsigned FIOperandNum)
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
void lowerCRRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
bool isCallerPreservedPhysReg(unsigned PhysReg, const MachineFunction &MF) const override
unsigned getID() const
Return the register class ID number.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:666
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:405
unsigned getFrameRegister(const MachineFunction &MF) const override
bool hasP9Vector() const
Definition: PPCSubtarget.h:249
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
void lowerVRSAVESpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
bool hasBasePointer(const MachineFunction &MF) const
void adjustStackMapLiveOutMask(uint32_t *Mask) const override
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to compute an offset from native ...
unsigned getKillRegState(bool B)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
TargetInstrInfo - Interface to description of machine instruction set.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:176
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getBaseRegister(const MachineFunction &MF) const
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:422
This file declares the machine register scavenger class.
void lowerVRSAVERestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static bool is64Bit(const char *name)
This file contains the declarations for the subclasses of Constant, which represent the different fla...
static unsigned offsetMinAlign(const MachineInstr &MI)
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
Common code between 32-bit and 64-bit PowerPC targets.
const MachineInstrBuilder & addFrameIndex(int Idx) const
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
PPCRegisterInfo(const PPCTargetMachine &TM)
static unsigned getCRFromCRBit(unsigned SrcReg)
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
const uint32_t * getNoPreservedMask() const override
bool hasP8Vector() const
Definition: PPCSubtarget.h:246
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
static cl::opt< bool > EnableGPRToVecSpills("ppc-enable-gpr-to-vsr-spills", cl::Hidden, cl::init(false), cl::desc("Enable spills from gpr to vsr rather than stack"))
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
static cl::opt< bool > AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false), cl::desc("Force the use of a base pointer in every function"))
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
const PPCInstrInfo * getInstrInfo() const override
Definition: PPCSubtarget.h:181
bool isDarwinABI() const
Definition: PPCSubtarget.h:308
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
void lowerCRBitSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:253
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:63
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:386
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool isPositionIndependent() const
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Return the register class to use to hold pointers.
#define I(x, y, z)
Definition: MD5.cpp:58
bool hasInlineAsm() const
Returns true if the function contains any inline assembly.
static cl::opt< bool > StackPtrConst("ppc-stack-ptr-caller-preserved", cl::desc("Consider R1 caller preserved so stack saves of " "caller preserved registers can be LICM candidates"), cl::init(true), cl::Hidden)
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
bool hasAltivec() const
Definition: PPCSubtarget.h:241
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:171
const unsigned Kind
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void lowerDynamicAlloc(MachineBasicBlock::iterator II) const
lowerDynamicAlloc - Generate the code for allocating an object in the current frame.
static cl::opt< bool > EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true), cl::desc("Enable use of a base pointer for complex stack frames"))
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
unsigned determineFrameLayout(MachineFunction &MF, bool UpdateMF=true, bool UseEstimate=false) const
determineFrameLayout - Determine the size of the frame and maximum call frame size.
IRTranslator LLVM IR MI
bool isSVR4ABI() const
Definition: PPCSubtarget.h:309
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const override