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PPCHazardRecognizers.h
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1 //===-- PPCHazardRecognizers.h - PowerPC Hazard Recognizers -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines hazard recognizers for scheduling on PowerPC processors.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCHAZARDRECOGNIZERS_H
14 #define LLVM_LIB_TARGET_POWERPC_PPCHAZARDRECOGNIZERS_H
15 
16 #include "PPCInstrInfo.h"
20 
21 namespace llvm {
22 
23 /// PPCDispatchGroupSBHazardRecognizer - This class implements a scoreboard-based
24 /// hazard recognizer for PPC ooo processors with dispatch-group hazards.
26  const ScheduleDAG *DAG;
27  SmallVector<SUnit *, 7> CurGroup;
28  unsigned CurSlots, CurBranches;
29 
30  bool isLoadAfterStore(SUnit *SU);
31  bool isBCTRAfterSet(SUnit *SU);
32  bool mustComeFirst(const MCInstrDesc *MCID, unsigned &NSlots);
33 public:
35  const ScheduleDAG *DAG_) :
36  ScoreboardHazardRecognizer(ItinData, DAG_), DAG(DAG_),
37  CurSlots(0), CurBranches(0) {}
38 
39  HazardType getHazardType(SUnit *SU, int Stalls) override;
40  bool ShouldPreferAnother(SUnit* SU) override;
41  unsigned PreEmitNoops(SUnit *SU) override;
42  void EmitInstruction(SUnit *SU) override;
43  void AdvanceCycle() override;
44  void RecedeCycle() override;
45  void Reset() override;
46  void EmitNoop() override;
47 };
48 
49 /// PPCHazardRecognizer970 - This class defines a finite state automata that
50 /// models the dispatch logic on the PowerPC 970 (aka G5) processor. This
51 /// promotes good dispatch group formation and implements noop insertion to
52 /// avoid structural hazards that cause significant performance penalties (e.g.
53 /// setting the CTR register then branching through it within a dispatch group),
54 /// or storing then loading from the same address within a dispatch group.
56  const ScheduleDAG &DAG;
57 
58  unsigned NumIssued; // Number of insts issued, including advanced cycles.
59 
60  // Various things that can cause a structural hazard.
61 
62  // HasCTRSet - If the CTR register is set in this group, disallow BCTRL.
63  bool HasCTRSet;
64 
65  // StoredPtr - Keep track of the address of any store. If we see a load from
66  // the same address (or one that aliases it), disallow the store. We can have
67  // up to four stores in one dispatch group, hence we track up to 4.
68  //
69  // This is null if we haven't seen a store yet. We keep track of both
70  // operands of the store here, since we support [r+r] and [r+i] addressing.
71  const Value *StoreValue[4];
72  int64_t StoreOffset[4];
73  uint64_t StoreSize[4];
74  unsigned NumStores;
75 
76 public:
78  HazardType getHazardType(SUnit *SU, int Stalls) override;
79  void EmitInstruction(SUnit *SU) override;
80  void AdvanceCycle() override;
81  void Reset() override;
82 
83 private:
84  /// EndDispatchGroup - Called when we are finishing a new dispatch group.
85  ///
86  void EndDispatchGroup();
87 
88  /// GetInstrType - Classify the specified powerpc opcode according to its
89  /// pipeline.
90  PPCII::PPC970_Unit GetInstrType(unsigned Opcode,
91  bool &isFirst, bool &isSingle,bool &isCracked,
92  bool &isLoad, bool &isStore);
93 
94  bool isLoadOfStoredAddress(uint64_t LoadSize, int64_t LoadOffset,
95  const Value *LoadValue) const;
96 };
97 
98 } // end namespace llvm
99 
100 #endif
101 
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:179
void RecedeCycle() override
RecedeCycle - This callback is invoked whenever the next bottom-up instruction to be scheduled cannot...
unsigned PreEmitNoops(SUnit *SU) override
PreEmitNoops - This callback is invoked prior to emitting an instruction.
PPCDispatchGroupSBHazardRecognizer - This class implements a scoreboard-based hazard recognizer for P...
static bool isLoad(int Opcode)
static bool isStore(int Opcode)
Itinerary data supplied by a subtarget to be used by a target.
void EmitNoop() override
EmitNoop - This callback is invoked when a noop was added to the instruction stream.
void Reset() override
Reset - This callback is invoked when a new block of instructions is about to be schedule.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
PPCHazardRecognizer970 - This class defines a finite state automata that models the dispatch logic on...
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
bool ShouldPreferAnother(SUnit *SU) override
ShouldPreferAnother - This callback may be invoked if getHazardType returns NoHazard.
void AdvanceCycle() override
AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled cannot...
LLVM Value Representation.
Definition: Value.h:74
void EmitInstruction(SUnit *SU) override
EmitInstruction - This callback is invoked when an instruction is emitted, to advance the hazard stat...
PPCDispatchGroupSBHazardRecognizer(const InstrItineraryData *ItinData, const ScheduleDAG *DAG_)
HazardType getHazardType(SUnit *SU, int Stalls) override
getHazardType - Return the hazard type of emitting this node.
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242