94 struct MachineVerifier {
95 MachineVerifier(
Pass *
pass,
const char *b) : PASS(
pass), Banner(
b) {}
100 : Banner(
b), LiveVars(LiveVars), LiveInts(LiveInts), LiveStks(LiveStks),
105 Pass *
const PASS =
nullptr;
114 unsigned foundErrors = 0;
117 bool isFunctionRegBankSelected =
false;
118 bool isFunctionSelected =
false;
119 bool isFunctionTracksDebugUserValues =
false;
129 BlockSet FunctionBlocks;
133 RegVector regsDefined, regsDead, regsKilled;
134 RegMaskVector regMasks;
139 void addRegWithSubRegs(RegVector &RV,
Register Reg) {
141 if (
Reg.isPhysical())
147 bool reachable =
false;
168 RegSet vregsRequired;
171 BlockSet Preds, Succs;
178 if (!
Reg.isVirtual())
180 if (regsLiveOut.count(Reg))
182 return vregsRequired.insert(Reg).second;
186 bool addRequired(
const RegSet &RS) {
187 bool Changed =
false;
189 Changed |= addRequired(Reg);
194 bool addRequired(
const RegMap &RM) {
195 bool Changed =
false;
196 for (
const auto &
I : RM)
197 Changed |= addRequired(
I.first);
203 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
211 return Reg.id() < regsReserved.
size() && regsReserved.
test(
Reg.id());
214 bool isAllocatable(
Register Reg)
const {
215 return Reg.id() <
TRI->getNumRegs() &&
TRI->isInAllocatableClass(Reg) &&
230 void visitMachineFunctionBefore();
246 void visitMachineOperand(
const MachineOperand *MO,
unsigned MONum);
249 void visitMachineFunctionAfter();
254 void report(
const char *msg,
const MachineOperand *MO,
unsigned MONum,
262 void report_context(
const VNInfo &VNI)
const;
263 void report_context(
SlotIndex Pos)
const;
264 void report_context(
MCPhysReg PhysReg)
const;
265 void report_context_liverange(
const LiveRange &LR)
const;
266 void report_context_lanemask(
LaneBitmask LaneMask)
const;
267 void report_context_vreg(
Register VReg)
const;
268 void report_context_vreg_regunit(
Register VRegOrUnit)
const;
279 Register VRegOrUnit,
bool SubRangeCheck =
false,
283 void calcRegsPassed();
286 void calcRegsRequired();
287 void verifyLiveVariables();
288 void verifyLiveIntervals();
292 void verifyLiveRangeSegment(
const LiveRange &,
298 void verifyStackFrame();
300 void verifySlotIndexes()
const;
307 const std::string Banner;
309 MachineVerifierPass(std::string banner = std::string())
328 MachineFunctionProperties::Property::FailsVerification))
331 unsigned FoundErrors = MachineVerifier(
this, Banner.c_str()).verify(MF);
340char MachineVerifierPass::ID = 0;
343 "Verify generated machine code",
false,
false)
346 return new MachineVerifierPass(Banner);
356 unsigned FoundErrors = MachineVerifier(
nullptr, Banner.c_str()).verify(MF);
364 unsigned FoundErrors = MachineVerifier(p, Banner).verify(MF);
365 if (AbortOnErrors && FoundErrors)
367 return FoundErrors == 0;
371 const char *Banner,
bool AbortOnErrors)
const {
373 unsigned FoundErrors =
374 MachineVerifier(Banner,
nullptr, LiveInts,
nullptr, Indexes).verify(MF);
375 if (AbortOnErrors && FoundErrors)
377 return FoundErrors == 0;
380void MachineVerifier::verifySlotIndexes()
const {
381 if (Indexes ==
nullptr)
399 MRI->getNumVirtRegs())
400 report(
"Function has NoVRegs property but there are VReg operands", &MF);
419 if (isFunctionFailedISel)
440 verifyProperties(MF);
442 visitMachineFunctionBefore();
444 visitMachineBasicBlockBefore(&
MBB);
448 bool InBundle =
false;
451 if (
MI.getParent() != &
MBB) {
452 report(
"Bad instruction parent pointer", &
MBB);
453 errs() <<
"Instruction: " <<
MI;
458 if (InBundle && !
MI.isBundledWithPred())
459 report(
"Missing BundledPred flag, "
460 "BundledSucc was set on predecessor",
462 if (!InBundle &&
MI.isBundledWithPred())
463 report(
"BundledPred flag is set, "
464 "but BundledSucc not set on predecessor",
468 if (!
MI.isInsideBundle()) {
470 visitMachineBundleAfter(CurBundle);
472 visitMachineBundleBefore(CurBundle);
473 }
else if (!CurBundle)
474 report(
"No bundle header", &
MI);
475 visitMachineInstrBefore(&
MI);
476 for (
unsigned I = 0,
E =
MI.getNumOperands();
I !=
E; ++
I) {
478 if (
Op.getParent() != &
MI) {
481 report(
"Instruction has operand with wrong parent set", &
MI);
484 visitMachineOperand(&
Op,
I);
488 InBundle =
MI.isBundledWithSucc();
491 visitMachineBundleAfter(CurBundle);
493 report(
"BundledSucc flag set on last instruction in block", &
MBB.
back());
494 visitMachineBasicBlockAfter(&
MBB);
496 visitMachineFunctionAfter();
509void MachineVerifier::report(
const char *msg,
const MachineFunction *MF) {
512 if (!foundErrors++) {
514 errs() <<
"# " << Banner <<
'\n';
515 if (LiveInts !=
nullptr)
520 errs() <<
"*** Bad machine code: " << msg <<
" ***\n"
521 <<
"- function: " << MF->
getName() <<
"\n";
535void MachineVerifier::report(
const char *msg,
const MachineInstr *
MI) {
537 report(msg,
MI->getParent());
538 errs() <<
"- instruction: ";
544void MachineVerifier::report(
const char *msg,
const MachineOperand *MO,
545 unsigned MONum,
LLT MOVRegType) {
548 errs() <<
"- operand " << MONum <<
": ";
554 report(
Msg.str().c_str(),
MI);
557void MachineVerifier::report_context(
SlotIndex Pos)
const {
558 errs() <<
"- at: " << Pos <<
'\n';
561void MachineVerifier::report_context(
const LiveInterval &LI)
const {
562 errs() <<
"- interval: " << LI <<
'\n';
567 report_context_liverange(LR);
568 report_context_vreg_regunit(VRegUnit);
570 report_context_lanemask(LaneMask);
574 errs() <<
"- segment: " << S <<
'\n';
577void MachineVerifier::report_context(
const VNInfo &VNI)
const {
578 errs() <<
"- ValNo: " << VNI.
id <<
" (def " << VNI.
def <<
")\n";
581void MachineVerifier::report_context_liverange(
const LiveRange &LR)
const {
582 errs() <<
"- liverange: " << LR <<
'\n';
585void MachineVerifier::report_context(
MCPhysReg PReg)
const {
589void MachineVerifier::report_context_vreg(
Register VReg)
const {
593void MachineVerifier::report_context_vreg_regunit(
Register VRegOrUnit)
const {
595 report_context_vreg(VRegOrUnit);
601void MachineVerifier::report_context_lanemask(
LaneBitmask LaneMask)
const {
606 BBInfo &MInfo = MBBInfoMap[
MBB];
607 if (!MInfo.reachable) {
608 MInfo.reachable =
true;
614void MachineVerifier::visitMachineFunctionBefore() {
616 regsReserved =
MRI->reservedRegsFrozen() ?
MRI->getReservedRegs()
617 :
TRI->getReservedRegs(*MF);
620 markReachable(&MF->
front());
623 FunctionBlocks.clear();
624 for (
const auto &
MBB : *MF) {
625 FunctionBlocks.insert(&
MBB);
626 BBInfo &MInfo = MBBInfoMap[&
MBB];
630 report(
"MBB has duplicate entries in its predecessor list.", &
MBB);
634 report(
"MBB has duplicate entries in its successor list.", &
MBB);
638 MRI->verifyUseLists();
646 FirstTerminator =
nullptr;
647 FirstNonPHI =
nullptr;
649 if (!MF->getProperties().hasProperty(
654 if (isAllocatable(LI.PhysReg) && !
MBB->
isEHPad() &&
657 report(
"MBB has allocatable live-in, but isn't entry, landing-pad, or "
658 "inlineasm-br-indirect-target.",
660 report_context(LI.PhysReg);
667 report(
"ir-block-address-taken is associated with basic block not used by "
676 LandingPadSuccs.
insert(succ);
677 if (!FunctionBlocks.count(succ))
678 report(
"MBB has successor that isn't part of the function.",
MBB);
679 if (!MBBInfoMap[succ].Preds.count(
MBB)) {
680 report(
"Inconsistent CFG",
MBB);
681 errs() <<
"MBB is not in the predecessor list of the successor "
688 if (!FunctionBlocks.count(Pred))
689 report(
"MBB has predecessor that isn't part of the function.",
MBB);
690 if (!MBBInfoMap[Pred].Succs.count(
MBB)) {
691 report(
"Inconsistent CFG",
MBB);
692 errs() <<
"MBB is not in the successor list of the predecessor "
700 if (LandingPadSuccs.
size() > 1 &&
705 report(
"MBB has more than one landing pad successor",
MBB);
718 report(
"MBB exits via unconditional fall-through but ends with a "
719 "barrier instruction!",
MBB);
722 report(
"MBB exits via unconditional fall-through but has a condition!",
725 }
else if (
TBB && !FBB &&
Cond.empty()) {
728 report(
"MBB exits via unconditional branch but doesn't contain "
729 "any instructions!",
MBB);
731 report(
"MBB exits via unconditional branch but doesn't end with a "
732 "barrier instruction!",
MBB);
734 report(
"MBB exits via unconditional branch but the branch isn't a "
735 "terminator instruction!",
MBB);
737 }
else if (
TBB && !FBB && !
Cond.empty()) {
740 report(
"MBB exits via conditional branch/fall-through but doesn't "
741 "contain any instructions!",
MBB);
743 report(
"MBB exits via conditional branch/fall-through but ends with a "
744 "barrier instruction!",
MBB);
746 report(
"MBB exits via conditional branch/fall-through but the branch "
747 "isn't a terminator instruction!",
MBB);
749 }
else if (
TBB && FBB) {
753 report(
"MBB exits via conditional branch/branch but doesn't "
754 "contain any instructions!",
MBB);
756 report(
"MBB exits via conditional branch/branch but doesn't end with a "
757 "barrier instruction!",
MBB);
759 report(
"MBB exits via conditional branch/branch but the branch "
760 "isn't a terminator instruction!",
MBB);
763 report(
"MBB exits via conditional branch/branch but there's no "
767 report(
"analyzeBranch returned invalid data!",
MBB);
773 report(
"MBB exits via jump or conditional branch, but its target isn't a "
777 report(
"MBB exits via conditional branch, but its target isn't a CFG "
784 bool Fallthrough = !
TBB || (!
Cond.empty() && !FBB);
789 if (!
Cond.empty() && !FBB) {
792 report(
"MBB conditionally falls through out of function!",
MBB);
794 report(
"MBB exits via conditional branch/fall-through but the CFG "
795 "successors don't match the actual successors!",
802 if (SuccMBB ==
TBB || SuccMBB == FBB)
810 if (SuccMBB->isEHPad() || SuccMBB->isInlineAsmBrIndirectTarget())
812 report(
"MBB has unexpected successors which are not branch targets, "
813 "fallthrough, EHPads, or inlineasm_br targets.",
819 if (
MRI->tracksLiveness()) {
822 report(
"MBB live-in list contains non-physical register",
MBB);
846void MachineVerifier::visitMachineBundleBefore(
const MachineInstr *
MI) {
849 if (!(idx > lastIndex)) {
850 report(
"Instruction index out of order",
MI);
851 errs() <<
"Last instruction was at " << lastIndex <<
'\n';
857 if (
MI->isTerminator()) {
858 if (!FirstTerminator)
859 FirstTerminator =
MI;
860 }
else if (FirstTerminator) {
863 if (FirstTerminator->
getOpcode() != TargetOpcode::G_INVOKE_REGION_START) {
864 report(
"Non-terminator instruction after the first terminator",
MI);
865 errs() <<
"First terminator was:\t" << *FirstTerminator;
874 if (
MI->getNumOperands() < 2) {
875 report(
"Too few operands on inline asm",
MI);
878 if (!
MI->getOperand(0).isSymbol())
879 report(
"Asm string must be an external symbol",
MI);
880 if (!
MI->getOperand(1).isImm())
881 report(
"Asm flags must be an immediate",
MI);
885 if (!isUInt<6>(
MI->getOperand(1).getImm()))
886 report(
"Unknown asm flags", &
MI->getOperand(1), 1);
892 for (
unsigned e =
MI->getNumOperands(); OpNo <
e; OpNo += NumOps) {
898 NumOps = 1 +
F.getNumOperandRegisters();
901 if (OpNo >
MI->getNumOperands())
902 report(
"Missing operands in last group",
MI);
905 if (OpNo < MI->getNumOperands() &&
MI->getOperand(OpNo).isMetadata())
909 for (
unsigned e =
MI->getNumOperands(); OpNo < e; ++OpNo) {
912 report(
"Expected implicit register after groups", &MO, OpNo);
915 if (
MI->getOpcode() == TargetOpcode::INLINEASM_BR) {
928 if (!IndirectTargetMBB) {
929 report(
"INLINEASM_BR indirect target does not exist", &MO, i);
934 report(
"INLINEASM_BR indirect target missing from successor list", &MO,
938 report(
"INLINEASM_BR indirect target predecessor list missing parent",
944bool MachineVerifier::verifyAllRegOpsScalar(
const MachineInstr &
MI,
949 const auto Reg = Op.getReg();
950 if (Reg.isPhysical())
952 return !MRI.getType(Reg).isScalar();
955 report(
"All register operands must have scalar types", &
MI);
962bool MachineVerifier::verifyVectorElementMatch(
LLT Ty0,
LLT Ty1,
965 report(
"operand types must be all-vector or all-scalar",
MI);
975 report(
"operand types must preserve number of vector elements",
MI);
982bool MachineVerifier::verifyGIntrinsicSideEffects(
const MachineInstr *
MI) {
983 auto Opcode =
MI->getOpcode();
984 bool NoSideEffects = Opcode == TargetOpcode::G_INTRINSIC ||
985 Opcode == TargetOpcode::G_INTRINSIC_CONVERGENT;
986 unsigned IntrID = cast<GIntrinsic>(
MI)->getIntrinsicID();
987 if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
989 MF->getFunction().getContext(),
static_cast<Intrinsic::ID>(IntrID));
990 bool DeclHasSideEffects = !
Attrs.getMemoryEffects().doesNotAccessMemory();
991 if (NoSideEffects && DeclHasSideEffects) {
993 " used with intrinsic that accesses memory"),
997 if (!NoSideEffects && !DeclHasSideEffects) {
998 report(
Twine(
TII->getName(Opcode),
" used with readnone intrinsic"),
MI);
1006bool MachineVerifier::verifyGIntrinsicConvergence(
const MachineInstr *
MI) {
1007 auto Opcode =
MI->getOpcode();
1008 bool NotConvergent = Opcode == TargetOpcode::G_INTRINSIC ||
1009 Opcode == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS;
1010 unsigned IntrID = cast<GIntrinsic>(
MI)->getIntrinsicID();
1011 if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
1013 MF->getFunction().getContext(),
static_cast<Intrinsic::ID>(IntrID));
1014 bool DeclIsConvergent =
Attrs.hasFnAttr(Attribute::Convergent);
1015 if (NotConvergent && DeclIsConvergent) {
1016 report(
Twine(
TII->getName(Opcode),
" used with a convergent intrinsic"),
1020 if (!NotConvergent && !DeclIsConvergent) {
1022 Twine(
TII->getName(Opcode),
" used with a non-convergent intrinsic"),
1031void MachineVerifier::verifyPreISelGenericInstruction(
const MachineInstr *
MI) {
1032 if (isFunctionSelected)
1033 report(
"Unexpected generic instruction in a Selected function",
MI);
1036 unsigned NumOps =
MI->getNumOperands();
1039 if (
MI->isBranch() && !
MI->isIndirectBranch()) {
1040 bool HasMBB =
false;
1049 report(
"Branch instruction is missing a basic block operand or "
1050 "isIndirectBranch property",
1059 if (!MCID.
operands()[
I].isGenericType())
1063 size_t TypeIdx = MCID.
operands()[
I].getGenericTypeIndex();
1064 Types.resize(std::max(TypeIdx + 1,
Types.size()));
1068 report(
"generic instruction must use register operands",
MI);
1078 if (!Types[TypeIdx].
isValid())
1079 Types[TypeIdx] = OpTy;
1080 else if (Types[TypeIdx] != OpTy)
1081 report(
"Type mismatch in generic instruction", MO,
I, OpTy);
1084 report(
"Generic instruction is missing a virtual register type", MO,
I);
1089 for (
unsigned I = 0;
I <
MI->getNumOperands(); ++
I) {
1092 report(
"Generic instruction cannot have physical register", MO,
I);
1104 unsigned Opc =
MI->getOpcode();
1106 case TargetOpcode::G_ASSERT_SEXT:
1107 case TargetOpcode::G_ASSERT_ZEXT: {
1108 std::string OpcName =
1109 Opc == TargetOpcode::G_ASSERT_ZEXT ?
"G_ASSERT_ZEXT" :
"G_ASSERT_SEXT";
1110 if (!
MI->getOperand(2).isImm()) {
1111 report(
Twine(OpcName,
" expects an immediate operand #2"),
MI);
1117 LLT SrcTy =
MRI->getType(Src);
1118 int64_t
Imm =
MI->getOperand(2).getImm();
1120 report(
Twine(OpcName,
" size must be >= 1"),
MI);
1125 report(
Twine(OpcName,
" size must be less than source bit width"),
MI);
1133 if ((SrcRB && DstRB && SrcRB != DstRB) || (DstRB && !SrcRB)) {
1134 report(
Twine(OpcName,
" cannot change register bank"),
MI);
1140 if (DstRC && DstRC !=
MRI->getRegClassOrNull(Src)) {
1142 Twine(OpcName,
" source and destination register classes must match"),
1150 case TargetOpcode::G_CONSTANT:
1151 case TargetOpcode::G_FCONSTANT: {
1152 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1154 report(
"Instruction cannot use a vector result type",
MI);
1156 if (
MI->getOpcode() == TargetOpcode::G_CONSTANT) {
1157 if (!
MI->getOperand(1).isCImm()) {
1158 report(
"G_CONSTANT operand must be cimm",
MI);
1164 report(
"inconsistent constant size",
MI);
1166 if (!
MI->getOperand(1).isFPImm()) {
1167 report(
"G_FCONSTANT operand must be fpimm",
MI);
1174 report(
"inconsistent constant size",
MI);
1180 case TargetOpcode::G_LOAD:
1181 case TargetOpcode::G_STORE:
1182 case TargetOpcode::G_ZEXTLOAD:
1183 case TargetOpcode::G_SEXTLOAD: {
1184 LLT ValTy =
MRI->getType(
MI->getOperand(0).getReg());
1185 LLT PtrTy =
MRI->getType(
MI->getOperand(1).getReg());
1187 report(
"Generic memory instruction must access a pointer",
MI);
1191 if (!
MI->hasOneMemOperand()) {
1192 report(
"Generic instruction accessing memory must have one mem operand",
1196 if (
MI->getOpcode() == TargetOpcode::G_ZEXTLOAD ||
1197 MI->getOpcode() == TargetOpcode::G_SEXTLOAD) {
1199 report(
"Generic extload must have a narrower memory type",
MI);
1200 }
else if (
MI->getOpcode() == TargetOpcode::G_LOAD) {
1202 report(
"load memory size cannot exceed result size",
MI);
1203 }
else if (
MI->getOpcode() == TargetOpcode::G_STORE) {
1205 report(
"store memory size cannot exceed value size",
MI);
1209 if (Opc == TargetOpcode::G_STORE) {
1212 report(
"atomic store cannot use acquire ordering",
MI);
1217 report(
"atomic load cannot use release ordering",
MI);
1223 case TargetOpcode::G_PHI: {
1224 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1229 LLT Ty = MRI->getType(MO.getReg());
1230 if (!Ty.isValid() || (Ty != DstTy))
1234 report(
"Generic Instruction G_PHI has operands with incompatible/missing "
1239 case TargetOpcode::G_BITCAST: {
1240 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1241 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1246 report(
"bitcast cannot convert between pointers and other types",
MI);
1249 report(
"bitcast sizes must match",
MI);
1252 report(
"bitcast must change the type",
MI);
1256 case TargetOpcode::G_INTTOPTR:
1257 case TargetOpcode::G_PTRTOINT:
1258 case TargetOpcode::G_ADDRSPACE_CAST: {
1259 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1260 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1264 verifyVectorElementMatch(DstTy, SrcTy,
MI);
1269 if (
MI->getOpcode() == TargetOpcode::G_INTTOPTR) {
1271 report(
"inttoptr result type must be a pointer",
MI);
1273 report(
"inttoptr source type must not be a pointer",
MI);
1274 }
else if (
MI->getOpcode() == TargetOpcode::G_PTRTOINT) {
1276 report(
"ptrtoint source type must be a pointer",
MI);
1278 report(
"ptrtoint result type must not be a pointer",
MI);
1280 assert(
MI->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST);
1282 report(
"addrspacecast types must be pointers",
MI);
1285 report(
"addrspacecast must convert different address spaces",
MI);
1291 case TargetOpcode::G_PTR_ADD: {
1292 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1293 LLT PtrTy =
MRI->getType(
MI->getOperand(1).getReg());
1294 LLT OffsetTy =
MRI->getType(
MI->getOperand(2).getReg());
1299 report(
"gep first operand must be a pointer",
MI);
1302 report(
"gep offset operand must not be a pointer",
MI);
1307 unsigned IndexSizeInBits =
DL.getIndexSize(AS) * 8;
1309 report(
"gep offset operand must match index size for address space",
1317 case TargetOpcode::G_PTRMASK: {
1318 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1319 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1320 LLT MaskTy =
MRI->getType(
MI->getOperand(2).getReg());
1325 report(
"ptrmask result type must be a pointer",
MI);
1328 report(
"ptrmask mask type must be an integer",
MI);
1330 verifyVectorElementMatch(DstTy, MaskTy,
MI);
1333 case TargetOpcode::G_SEXT:
1334 case TargetOpcode::G_ZEXT:
1335 case TargetOpcode::G_ANYEXT:
1336 case TargetOpcode::G_TRUNC:
1337 case TargetOpcode::G_FPEXT:
1338 case TargetOpcode::G_FPTRUNC: {
1345 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1346 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1351 report(
"Generic extend/truncate can not operate on pointers",
MI);
1353 verifyVectorElementMatch(DstTy, SrcTy,
MI);
1357 switch (
MI->getOpcode()) {
1359 if (DstSize <= SrcSize)
1360 report(
"Generic extend has destination type no larger than source",
MI);
1362 case TargetOpcode::G_TRUNC:
1363 case TargetOpcode::G_FPTRUNC:
1364 if (DstSize >= SrcSize)
1365 report(
"Generic truncate has destination type no smaller than source",
1371 case TargetOpcode::G_SELECT: {
1372 LLT SelTy =
MRI->getType(
MI->getOperand(0).getReg());
1373 LLT CondTy =
MRI->getType(
MI->getOperand(1).getReg());
1379 verifyVectorElementMatch(SelTy, CondTy,
MI);
1382 case TargetOpcode::G_MERGE_VALUES: {
1387 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1388 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1390 report(
"G_MERGE_VALUES cannot operate on vectors",
MI);
1392 const unsigned NumOps =
MI->getNumOperands();
1394 report(
"G_MERGE_VALUES result size is inconsistent",
MI);
1396 for (
unsigned I = 2;
I != NumOps; ++
I) {
1397 if (
MRI->getType(
MI->getOperand(
I).getReg()) != SrcTy)
1398 report(
"G_MERGE_VALUES source types do not match",
MI);
1403 case TargetOpcode::G_UNMERGE_VALUES: {
1404 unsigned NumDsts =
MI->getNumOperands() - 1;
1405 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1406 for (
unsigned i = 1; i < NumDsts; ++i) {
1407 if (
MRI->getType(
MI->getOperand(i).getReg()) != DstTy) {
1408 report(
"G_UNMERGE_VALUES destination types do not match",
MI);
1413 LLT SrcTy =
MRI->getType(
MI->getOperand(NumDsts).getReg());
1419 report(
"G_UNMERGE_VALUES source operand does not match vector "
1420 "destination operands",
1427 report(
"G_UNMERGE_VALUES vector source operand does not match scalar "
1428 "destination operands",
1433 report(
"G_UNMERGE_VALUES scalar source operand does not match scalar "
1434 "destination operands",
1440 case TargetOpcode::G_BUILD_VECTOR: {
1443 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1444 LLT SrcEltTy =
MRI->getType(
MI->getOperand(1).getReg());
1446 report(
"G_BUILD_VECTOR must produce a vector from scalar operands",
MI);
1451 report(
"G_BUILD_VECTOR result element type must match source type",
MI);
1454 report(
"G_BUILD_VECTOR must have an operand for each elemement",
MI);
1457 if (
MRI->getType(
MI->getOperand(1).getReg()) !=
MRI->getType(MO.
getReg()))
1458 report(
"G_BUILD_VECTOR source operand types are not homogeneous",
MI);
1462 case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1465 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1466 LLT SrcEltTy =
MRI->getType(
MI->getOperand(1).getReg());
1468 report(
"G_BUILD_VECTOR_TRUNC must produce a vector from scalar operands",
1471 if (
MRI->getType(
MI->getOperand(1).getReg()) !=
MRI->getType(MO.
getReg()))
1472 report(
"G_BUILD_VECTOR_TRUNC source operand types are not homogeneous",
1475 report(
"G_BUILD_VECTOR_TRUNC source operand types are not larger than "
1480 case TargetOpcode::G_CONCAT_VECTORS: {
1483 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1484 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1486 report(
"G_CONCAT_VECTOR requires vector source and destination operands",
1489 if (
MI->getNumOperands() < 3)
1490 report(
"G_CONCAT_VECTOR requires at least 2 source operands",
MI);
1493 if (
MRI->getType(
MI->getOperand(1).getReg()) !=
MRI->getType(MO.
getReg()))
1494 report(
"G_CONCAT_VECTOR source operand types are not homogeneous",
MI);
1497 report(
"G_CONCAT_VECTOR num dest and source elements should match",
MI);
1500 case TargetOpcode::G_ICMP:
1501 case TargetOpcode::G_FCMP: {
1502 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1503 LLT SrcTy =
MRI->getType(
MI->getOperand(2).getReg());
1507 report(
"Generic vector icmp/fcmp must preserve number of lanes",
MI);
1511 case TargetOpcode::G_EXTRACT: {
1513 if (!
SrcOp.isReg()) {
1514 report(
"extract source must be a register",
MI);
1519 if (!OffsetOp.
isImm()) {
1520 report(
"extract offset must be a constant",
MI);
1524 unsigned DstSize =
MRI->getType(
MI->getOperand(0).getReg()).getSizeInBits();
1526 if (SrcSize == DstSize)
1527 report(
"extract source must be larger than result",
MI);
1529 if (DstSize + OffsetOp.
getImm() > SrcSize)
1530 report(
"extract reads past end of register",
MI);
1533 case TargetOpcode::G_INSERT: {
1535 if (!
SrcOp.isReg()) {
1536 report(
"insert source must be a register",
MI);
1541 if (!OffsetOp.
isImm()) {
1542 report(
"insert offset must be a constant",
MI);
1546 unsigned DstSize =
MRI->getType(
MI->getOperand(0).getReg()).getSizeInBits();
1549 if (DstSize <= SrcSize)
1550 report(
"inserted size must be smaller than total register",
MI);
1552 if (SrcSize + OffsetOp.
getImm() > DstSize)
1553 report(
"insert writes past end of register",
MI);
1557 case TargetOpcode::G_JUMP_TABLE: {
1558 if (!
MI->getOperand(1).isJTI())
1559 report(
"G_JUMP_TABLE source operand must be a jump table index",
MI);
1560 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1562 report(
"G_JUMP_TABLE dest operand must have a pointer type",
MI);
1565 case TargetOpcode::G_BRJT: {
1566 if (!
MRI->getType(
MI->getOperand(0).getReg()).isPointer())
1567 report(
"G_BRJT src operand 0 must be a pointer type",
MI);
1569 if (!
MI->getOperand(1).isJTI())
1570 report(
"G_BRJT src operand 1 must be a jump table index",
MI);
1572 const auto &IdxOp =
MI->getOperand(2);
1573 if (!IdxOp.isReg() ||
MRI->getType(IdxOp.getReg()).isPointer())
1574 report(
"G_BRJT src operand 2 must be a scalar reg type",
MI);
1577 case TargetOpcode::G_INTRINSIC:
1578 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
1579 case TargetOpcode::G_INTRINSIC_CONVERGENT:
1580 case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS: {
1585 report(
"G_INTRINSIC first src operand must be an intrinsic ID",
MI);
1589 if (!verifyGIntrinsicSideEffects(
MI))
1591 if (!verifyGIntrinsicConvergence(
MI))
1596 case TargetOpcode::G_SEXT_INREG: {
1597 if (!
MI->getOperand(2).isImm()) {
1598 report(
"G_SEXT_INREG expects an immediate operand #2",
MI);
1602 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1603 int64_t
Imm =
MI->getOperand(2).getImm();
1605 report(
"G_SEXT_INREG size must be >= 1",
MI);
1607 report(
"G_SEXT_INREG size must be less than source bit width",
MI);
1610 case TargetOpcode::G_BSWAP: {
1611 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1613 report(
"G_BSWAP size must be a multiple of 16 bits",
MI);
1616 case TargetOpcode::G_VSCALE: {
1617 if (!
MI->getOperand(1).isCImm()) {
1618 report(
"G_VSCALE operand must be cimm",
MI);
1621 if (
MI->getOperand(1).getCImm()->isZero()) {
1622 report(
"G_VSCALE immediate cannot be zero",
MI);
1627 case TargetOpcode::G_INSERT_SUBVECTOR: {
1629 if (!Src0Op.
isReg()) {
1630 report(
"G_INSERT_SUBVECTOR first source must be a register",
MI);
1635 if (!Src1Op.
isReg()) {
1636 report(
"G_INSERT_SUBVECTOR second source must be a register",
MI);
1641 if (!IndexOp.
isImm()) {
1642 report(
"G_INSERT_SUBVECTOR index must be an immediate",
MI);
1646 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1651 report(
"Destination type must be a vector",
MI);
1656 report(
"First source must be a vector",
MI);
1661 report(
"Second source must be a vector",
MI);
1665 if (DstTy != Src0Ty) {
1666 report(
"Destination type must match the first source vector type",
MI);
1671 report(
"Element type of source vectors must be the same",
MI);
1675 if (IndexOp.
getImm() != 0 &&
1677 report(
"Index must be a multiple of the second source vector's "
1678 "minimum vector length",
1684 case TargetOpcode::G_EXTRACT_SUBVECTOR: {
1686 if (!
SrcOp.isReg()) {
1687 report(
"G_EXTRACT_SUBVECTOR first source must be a register",
MI);
1692 if (!IndexOp.
isImm()) {
1693 report(
"G_EXTRACT_SUBVECTOR index must be an immediate",
MI);
1697 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1701 report(
"Destination type must be a vector",
MI);
1706 report(
"First source must be a vector",
MI);
1711 report(
"Element type of vectors must be the same",
MI);
1715 if (IndexOp.
getImm() != 0 &&
1717 report(
"Index must be a multiple of the source vector's minimum vector "
1725 case TargetOpcode::G_SHUFFLE_VECTOR: {
1728 report(
"Incorrect mask operand type for G_SHUFFLE_VECTOR",
MI);
1732 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1733 LLT Src0Ty =
MRI->getType(
MI->getOperand(1).getReg());
1734 LLT Src1Ty =
MRI->getType(
MI->getOperand(2).getReg());
1736 if (Src0Ty != Src1Ty)
1737 report(
"Source operands must be the same type",
MI);
1740 report(
"G_SHUFFLE_VECTOR cannot change element type",
MI);
1749 if (
static_cast<int>(MaskIdxes.
size()) != DstNumElts)
1750 report(
"Wrong result type for shufflemask",
MI);
1752 for (
int Idx : MaskIdxes) {
1756 if (
Idx >= 2 * SrcNumElts)
1757 report(
"Out of bounds shuffle index",
MI);
1763 case TargetOpcode::G_SPLAT_VECTOR: {
1764 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1765 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1768 report(
"Destination type must be a scalable vector",
MI);
1771 report(
"Source type must be a scalar",
MI);
1774 report(
"Element type of the destination must be the same type as the "
1780 case TargetOpcode::G_DYN_STACKALLOC: {
1786 report(
"dst operand 0 must be a pointer type",
MI);
1790 if (!AllocOp.
isReg() || !
MRI->getType(AllocOp.
getReg()).isScalar()) {
1791 report(
"src operand 1 must be a scalar reg type",
MI);
1795 if (!AlignOp.
isImm()) {
1796 report(
"src operand 2 must be an immediate type",
MI);
1801 case TargetOpcode::G_MEMCPY_INLINE:
1802 case TargetOpcode::G_MEMCPY:
1803 case TargetOpcode::G_MEMMOVE: {
1805 if (MMOs.
size() != 2) {
1806 report(
"memcpy/memmove must have 2 memory operands",
MI);
1812 report(
"wrong memory operand types",
MI);
1817 report(
"inconsistent memory operand sizes",
MI);
1819 LLT DstPtrTy =
MRI->getType(
MI->getOperand(0).getReg());
1820 LLT SrcPtrTy =
MRI->getType(
MI->getOperand(1).getReg());
1823 report(
"memory instruction operand must be a pointer",
MI);
1828 report(
"inconsistent store address space",
MI);
1830 report(
"inconsistent load address space",
MI);
1832 if (Opc != TargetOpcode::G_MEMCPY_INLINE)
1833 if (!
MI->getOperand(3).isImm() || (
MI->getOperand(3).getImm() & ~1LL))
1834 report(
"'tail' flag (operand 3) must be an immediate 0 or 1",
MI);
1838 case TargetOpcode::G_BZERO:
1839 case TargetOpcode::G_MEMSET: {
1841 std::string
Name = Opc == TargetOpcode::G_MEMSET ?
"memset" :
"bzero";
1842 if (MMOs.
size() != 1) {
1843 report(
Twine(
Name,
" must have 1 memory operand"),
MI);
1848 report(
Twine(
Name,
" memory operand must be a store"),
MI);
1852 LLT DstPtrTy =
MRI->getType(
MI->getOperand(0).getReg());
1854 report(
Twine(
Name,
" operand must be a pointer"),
MI);
1859 report(
"inconsistent " +
Twine(
Name,
" address space"),
MI);
1861 if (!
MI->getOperand(
MI->getNumOperands() - 1).isImm() ||
1862 (
MI->getOperand(
MI->getNumOperands() - 1).getImm() & ~1LL))
1863 report(
"'tail' flag (last operand) must be an immediate 0 or 1",
MI);
1867 case TargetOpcode::G_VECREDUCE_SEQ_FADD:
1868 case TargetOpcode::G_VECREDUCE_SEQ_FMUL: {
1869 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1870 LLT Src1Ty =
MRI->getType(
MI->getOperand(1).getReg());
1871 LLT Src2Ty =
MRI->getType(
MI->getOperand(2).getReg());
1873 report(
"Vector reduction requires a scalar destination type",
MI);
1875 report(
"Sequential FADD/FMUL vector reduction requires a scalar 1st operand",
MI);
1877 report(
"Sequential FADD/FMUL vector reduction must have a vector 2nd operand",
MI);
1880 case TargetOpcode::G_VECREDUCE_FADD:
1881 case TargetOpcode::G_VECREDUCE_FMUL:
1882 case TargetOpcode::G_VECREDUCE_FMAX:
1883 case TargetOpcode::G_VECREDUCE_FMIN:
1884 case TargetOpcode::G_VECREDUCE_FMAXIMUM:
1885 case TargetOpcode::G_VECREDUCE_FMINIMUM:
1886 case TargetOpcode::G_VECREDUCE_ADD:
1887 case TargetOpcode::G_VECREDUCE_MUL:
1888 case TargetOpcode::G_VECREDUCE_AND:
1889 case TargetOpcode::G_VECREDUCE_OR:
1890 case TargetOpcode::G_VECREDUCE_XOR:
1891 case TargetOpcode::G_VECREDUCE_SMAX:
1892 case TargetOpcode::G_VECREDUCE_SMIN:
1893 case TargetOpcode::G_VECREDUCE_UMAX:
1894 case TargetOpcode::G_VECREDUCE_UMIN: {
1895 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1897 report(
"Vector reduction requires a scalar destination type",
MI);
1901 case TargetOpcode::G_SBFX:
1902 case TargetOpcode::G_UBFX: {
1903 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1905 report(
"Bitfield extraction is not supported on vectors",
MI);
1910 case TargetOpcode::G_SHL:
1911 case TargetOpcode::G_LSHR:
1912 case TargetOpcode::G_ASHR:
1913 case TargetOpcode::G_ROTR:
1914 case TargetOpcode::G_ROTL: {
1915 LLT Src1Ty =
MRI->getType(
MI->getOperand(1).getReg());
1916 LLT Src2Ty =
MRI->getType(
MI->getOperand(2).getReg());
1918 report(
"Shifts and rotates require operands to be either all scalars or "
1925 case TargetOpcode::G_LLROUND:
1926 case TargetOpcode::G_LROUND: {
1927 verifyAllRegOpsScalar(*
MI, *
MRI);
1930 case TargetOpcode::G_IS_FPCLASS: {
1931 LLT DestTy =
MRI->getType(
MI->getOperand(0).getReg());
1934 report(
"Destination must be a scalar or vector of scalars",
MI);
1937 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1940 report(
"Source must be a scalar or vector of scalars",
MI);
1943 if (!verifyVectorElementMatch(DestTy, SrcTy,
MI))
1946 if (!TestMO.
isImm()) {
1947 report(
"floating-point class set (operand 2) must be an immediate",
MI);
1952 report(
"Incorrect floating-point class set (operand 2)",
MI);
1957 case TargetOpcode::G_PREFETCH: {
1959 if (!AddrOp.
isReg() || !
MRI->getType(AddrOp.
getReg()).isPointer()) {
1960 report(
"addr operand must be a pointer", &AddrOp, 0);
1965 report(
"rw operand must be an immediate 0-1", &RWOp, 1);
1970 report(
"locality operand must be an immediate 0-3", &LocalityOp, 2);
1975 report(
"cache type operand must be an immediate 0-1", &CacheTypeOp, 3);
1980 case TargetOpcode::G_ASSERT_ALIGN: {
1981 if (
MI->getOperand(2).getImm() < 1)
1982 report(
"alignment immediate must be >= 1",
MI);
1985 case TargetOpcode::G_CONSTANT_POOL: {
1986 if (!
MI->getOperand(1).isCPI())
1987 report(
"Src operand 1 must be a constant pool index",
MI);
1988 if (!
MRI->getType(
MI->getOperand(0).getReg()).isPointer())
1989 report(
"Dst operand 0 must be a pointer",
MI);
1997void MachineVerifier::visitMachineInstrBefore(
const MachineInstr *
MI) {
2000 report(
"Too few operands",
MI);
2002 <<
MI->getNumOperands() <<
" given.\n";
2006 report(
"NoConvergent flag expected only on convergent instructions.",
MI);
2009 if (MF->getProperties().hasProperty(
2011 report(
"Found PHI instruction with NoPHIs property set",
MI);
2014 report(
"Found PHI instruction after non-PHI",
MI);
2015 }
else if (FirstNonPHI ==
nullptr)
2019 if (
MI->isInlineAsm())
2020 verifyInlineAsm(
MI);
2023 if (
TII->isUnspillableTerminator(
MI)) {
2024 if (!
MI->getOperand(0).isReg() || !
MI->getOperand(0).isDef())
2025 report(
"Unspillable Terminator does not define a reg",
MI);
2027 if (
Def.isVirtual() &&
2028 !MF->getProperties().hasProperty(
2030 std::distance(
MRI->use_nodbg_begin(Def),
MRI->use_nodbg_end()) > 1)
2031 report(
"Unspillable Terminator expected to have at most one use!",
MI);
2037 if (
MI->isDebugValue() &&
MI->getNumOperands() == 4)
2038 if (!
MI->getDebugLoc())
2039 report(
"Missing DebugLoc for debug instruction",
MI);
2043 if (
MI->isMetaInstruction() &&
MI->peekDebugInstrNum())
2044 report(
"Metadata instruction should not have a value tracking number",
MI);
2048 if (
Op->isLoad() && !
MI->mayLoad())
2049 report(
"Missing mayLoad flag",
MI);
2050 if (
Op->isStore() && !
MI->mayStore())
2051 report(
"Missing mayStore flag",
MI);
2058 if (
MI->isDebugOrPseudoInstr()) {
2060 report(
"Debug instruction has a slot index",
MI);
2061 }
else if (
MI->isInsideBundle()) {
2063 report(
"Instruction inside bundle has a slot index",
MI);
2066 report(
"Missing slot index",
MI);
2072 verifyPreISelGenericInstruction(
MI);
2081 switch (
MI->getOpcode()) {
2082 case TargetOpcode::COPY: {
2088 LLT DstTy =
MRI->getType(DstReg);
2089 LLT SrcTy =
MRI->getType(SrcReg);
2092 if (SrcTy != DstTy) {
2093 report(
"Copy Instruction is illegal with mismatching types",
MI);
2094 errs() <<
"Def = " << DstTy <<
", Src = " << SrcTy <<
"\n";
2109 TRI->getMinimalPhysRegClassLLT(SrcReg, DstTy);
2111 SrcSize =
TRI->getRegSizeInBits(*SrcRC);
2116 TRI->getMinimalPhysRegClassLLT(DstReg, SrcTy);
2118 DstSize =
TRI->getRegSizeInBits(*DstRC);
2136 if (!
DstOp.getSubReg() && !
SrcOp.getSubReg()) {
2137 report(
"Copy Instruction is illegal with mismatching sizes",
MI);
2138 errs() <<
"Def Size = " << DstSize <<
", Src Size = " << SrcSize
2144 case TargetOpcode::STATEPOINT: {
2146 if (!
MI->getOperand(SO.getIDPos()).isImm() ||
2147 !
MI->getOperand(SO.getNBytesPos()).isImm() ||
2148 !
MI->getOperand(SO.getNCallArgsPos()).isImm()) {
2149 report(
"meta operands to STATEPOINT not constant!",
MI);
2153 auto VerifyStackMapConstant = [&](
unsigned Offset) {
2154 if (
Offset >=
MI->getNumOperands()) {
2155 report(
"stack map constant to STATEPOINT is out of range!",
MI);
2158 if (!
MI->getOperand(
Offset - 1).isImm() ||
2159 MI->getOperand(
Offset - 1).getImm() != StackMaps::ConstantOp ||
2161 report(
"stack map constant to STATEPOINT not well formed!",
MI);
2163 VerifyStackMapConstant(SO.getCCIdx());
2164 VerifyStackMapConstant(SO.getFlagsIdx());
2165 VerifyStackMapConstant(SO.getNumDeoptArgsIdx());
2166 VerifyStackMapConstant(SO.getNumGCPtrIdx());
2167 VerifyStackMapConstant(SO.getNumAllocaIdx());
2168 VerifyStackMapConstant(SO.getNumGcMapEntriesIdx());
2172 unsigned FirstGCPtrIdx = SO.getFirstGCPtrIdx();
2173 unsigned LastGCPtrIdx = SO.getNumAllocaIdx() - 2;
2174 for (
unsigned Idx = 0;
Idx <
MI->getNumDefs();
Idx++) {
2176 if (!
MI->isRegTiedToUseOperand(
Idx, &UseOpIdx)) {
2177 report(
"STATEPOINT defs expected to be tied",
MI);
2180 if (UseOpIdx < FirstGCPtrIdx || UseOpIdx > LastGCPtrIdx) {
2181 report(
"STATEPOINT def tied to non-gc operand",
MI);
2188 case TargetOpcode::INSERT_SUBREG: {
2189 unsigned InsertedSize;
2190 if (
unsigned SubIdx =
MI->getOperand(2).getSubReg())
2191 InsertedSize =
TRI->getSubRegIdxSize(SubIdx);
2193 InsertedSize =
TRI->getRegSizeInBits(
MI->getOperand(2).getReg(), *
MRI);
2194 unsigned SubRegSize =
TRI->getSubRegIdxSize(
MI->getOperand(3).getImm());
2195 if (SubRegSize < InsertedSize) {
2196 report(
"INSERT_SUBREG expected inserted value to have equal or lesser "
2197 "size than the subreg it was inserted into",
MI);
2201 case TargetOpcode::REG_SEQUENCE: {
2202 unsigned NumOps =
MI->getNumOperands();
2203 if (!(NumOps & 1)) {
2204 report(
"Invalid number of operands for REG_SEQUENCE",
MI);
2208 for (
unsigned I = 1;
I != NumOps;
I += 2) {
2213 report(
"Invalid register operand for REG_SEQUENCE", &RegOp,
I);
2215 if (!SubRegOp.
isImm() || SubRegOp.
getImm() == 0 ||
2216 SubRegOp.
getImm() >=
TRI->getNumSubRegIndices()) {
2217 report(
"Invalid subregister index operand for REG_SEQUENCE",
2222 Register DstReg =
MI->getOperand(0).getReg();
2224 report(
"REG_SEQUENCE does not support physical register results",
MI);
2226 if (
MI->getOperand(0).getSubReg())
2227 report(
"Invalid subreg result for REG_SEQUENCE",
MI);
2235MachineVerifier::visitMachineOperand(
const MachineOperand *MO,
unsigned MONum) {
2239 if (MCID.
getOpcode() == TargetOpcode::PATCHPOINT)
2240 NumDefs = (MONum == 0 && MO->
isReg()) ? NumDefs : 0;
2243 if (MONum < NumDefs) {
2246 report(
"Explicit definition must be a register", MO, MONum);
2248 report(
"Explicit definition marked as use", MO, MONum);
2250 report(
"Explicit definition marked as implicit", MO, MONum);
2259 report(
"Explicit operand marked as def", MO, MONum);
2261 report(
"Explicit operand marked as implicit", MO, MONum);
2267 report(
"Expected a register operand.", MO, MONum);
2271 !
TII->isPCRelRegisterOperandLegal(*MO)))
2272 report(
"Expected a non-register operand.", MO, MONum);
2279 report(
"Tied use must be a register", MO, MONum);
2281 report(
"Operand should be tied", MO, MONum);
2282 else if (
unsigned(TiedTo) !=
MI->findTiedOperandIdx(MONum))
2283 report(
"Tied def doesn't match MCInstrDesc", MO, MONum);
2286 if (!MOTied.
isReg())
2287 report(
"Tied counterpart must be a register", &MOTied, TiedTo);
2290 report(
"Tied physical registers must match.", &MOTied, TiedTo);
2293 report(
"Explicit operand should not be tied", MO, MONum);
2294 }
else if (!
MI->isVariadic()) {
2297 report(
"Extra explicit operand on non-variadic instruction", MO, MONum);
2304 if (
MI->isDebugInstr() && MO->
isUse()) {
2306 report(
"Register operand must be marked debug", MO, MONum);
2308 report(
"Register operand must not be marked debug", MO, MONum);
2314 if (
MRI->tracksLiveness() && !
MI->isDebugInstr())
2315 checkLiveness(MO, MONum);
2319 report(
"Undef virtual register def operands require a subregister", MO, MONum);
2323 unsigned OtherIdx =
MI->findTiedOperandIdx(MONum);
2325 if (!OtherMO.
isReg())
2326 report(
"Must be tied to a register", MO, MONum);
2328 report(
"Missing tie flags on tied operand", MO, MONum);
2329 if (
MI->findTiedOperandIdx(OtherIdx) != MONum)
2330 report(
"Inconsistent tie links", MO, MONum);
2334 report(
"Explicit def tied to explicit use without tie constraint",
2338 report(
"Explicit def should be tied to implicit use", MO, MONum);
2351 if (MF->getProperties().hasProperty(
2353 MO->
isUse() &&
MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
2354 Reg !=
MI->getOperand(DefIdx).getReg())
2355 report(
"Two-address instruction operands must be identical", MO, MONum);
2360 if (
Reg.isPhysical()) {
2362 report(
"Illegal subregister index for physical register", MO, MONum);
2367 TII->getRegClass(MCID, MONum,
TRI, *MF)) {
2368 if (!DRC->contains(Reg)) {
2369 report(
"Illegal physical register for instruction", MO, MONum);
2371 <<
TRI->getRegClassName(DRC) <<
" register.\n";
2376 if (
MRI->isReserved(Reg)) {
2377 report(
"isRenamable set on reserved register", MO, MONum);
2394 report(
"Generic virtual register use cannot be undef", MO, MONum);
2401 if (isFunctionTracksDebugUserValues || !MO->
isUse() ||
2402 !
MI->isDebugValue() || !
MRI->def_empty(Reg)) {
2404 if (isFunctionSelected) {
2405 report(
"Generic virtual register invalid in a Selected function",
2411 LLT Ty =
MRI->getType(Reg);
2413 report(
"Generic virtual register must have a valid type", MO,
2422 if (!RegBank && isFunctionRegBankSelected) {
2423 report(
"Generic virtual register must have a bank in a "
2424 "RegBankSelected function",
2432 report(
"Register bank is too small for virtual register", MO,
2434 errs() <<
"Register bank " << RegBank->
getName() <<
" too small("
2442 report(
"Generic virtual register does not allow subregister index", MO,
2452 TII->getRegClass(MCID, MONum,
TRI, *MF)) {
2453 report(
"Virtual register does not match instruction constraint", MO,
2455 errs() <<
"Expect register class "
2456 <<
TRI->getRegClassName(
2457 TII->getRegClass(MCID, MONum,
TRI, *MF))
2458 <<
" but got nothing\n";
2466 TRI->getSubClassWithSubReg(RC, SubIdx);
2468 report(
"Invalid subregister index for virtual register", MO, MONum);
2469 errs() <<
"Register class " <<
TRI->getRegClassName(RC)
2470 <<
" does not support subreg index " << SubIdx <<
"\n";
2474 report(
"Invalid register class for subregister index", MO, MONum);
2475 errs() <<
"Register class " <<
TRI->getRegClassName(RC)
2476 <<
" does not fully support subreg index " << SubIdx <<
"\n";
2482 TII->getRegClass(MCID, MONum,
TRI, *MF)) {
2485 TRI->getLargestLegalSuperClass(RC, *MF);
2487 report(
"No largest legal super class exists.", MO, MONum);
2490 DRC =
TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
2492 report(
"No matching super-reg register class.", MO, MONum);
2497 report(
"Illegal virtual register for instruction", MO, MONum);
2498 errs() <<
"Expected a " <<
TRI->getRegClassName(DRC)
2499 <<
" register, but got a " <<
TRI->getRegClassName(RC)
2514 report(
"PHI operand is not in the CFG", MO, MONum);
2525 bool loads =
MI->mayLoad();
2530 for (
auto *MMO :
MI->memoperands()) {
2532 if (PSV ==
nullptr)
continue;
2534 dyn_cast<FixedStackPseudoSourceValue>(PSV);
2535 if (
Value ==
nullptr)
continue;
2536 if (
Value->getFrameIndex() != FI)
continue;
2545 report(
"Missing fixed stack memoperand.",
MI);
2547 if (loads && !LI.
liveAt(
Idx.getRegSlot(
true))) {
2548 report(
"Instruction loads from dead spill slot", MO, MONum);
2549 errs() <<
"Live stack: " << LI <<
'\n';
2552 report(
"Instruction stores to dead spill slot", MO, MONum);
2553 errs() <<
"Live stack: " << LI <<
'\n';
2559 if (MO->
getCFIIndex() >= MF->getFrameInstructions().size())
2560 report(
"CFI instruction has invalid index", MO, MONum);
2568void MachineVerifier::checkLivenessAtUse(
const MachineOperand *MO,
2579 report(
"No live segment at use", MO, MONum);
2580 report_context_liverange(LR);
2581 report_context_vreg_regunit(VRegOrUnit);
2582 report_context(UseIdx);
2585 report(
"Live range continues after kill flag", MO, MONum);
2586 report_context_liverange(LR);
2587 report_context_vreg_regunit(VRegOrUnit);
2589 report_context_lanemask(LaneMask);
2590 report_context(UseIdx);
2594void MachineVerifier::checkLivenessAtDef(
const MachineOperand *MO,
2609 if (((SubRangeCheck || MO->
getSubReg() == 0) && VNI->def != DefIdx) ||
2611 (VNI->def != DefIdx &&
2612 (!VNI->def.isEarlyClobber() || !DefIdx.
isRegister()))) {
2613 report(
"Inconsistent valno->def", MO, MONum);
2614 report_context_liverange(LR);
2615 report_context_vreg_regunit(VRegOrUnit);
2617 report_context_lanemask(LaneMask);
2618 report_context(*VNI);
2619 report_context(DefIdx);
2622 report(
"No live segment at def", MO, MONum);
2623 report_context_liverange(LR);
2624 report_context_vreg_regunit(VRegOrUnit);
2626 report_context_lanemask(LaneMask);
2627 report_context(DefIdx);
2639 if (SubRangeCheck || MO->
getSubReg() == 0) {
2640 report(
"Live range continues after dead def flag", MO, MONum);
2641 report_context_liverange(LR);
2642 report_context_vreg_regunit(VRegOrUnit);
2644 report_context_lanemask(LaneMask);
2650void MachineVerifier::checkLiveness(
const MachineOperand *MO,
unsigned MONum) {
2653 const unsigned SubRegIdx = MO->
getSubReg();
2656 if (LiveInts &&
Reg.isVirtual()) {
2661 report(
"Live interval for subreg operand has no subranges", MO, MONum);
2663 report(
"Virtual register has no live interval", MO, MONum);
2670 addRegWithSubRegs(regsKilled, Reg);
2675 if (LiveVars &&
Reg.isVirtual() && MO->
isKill() &&
2676 !
MI->isBundledWithPred()) {
2679 report(
"Kill missing from LiveVariables", MO, MONum);
2693 if (
Reg.isPhysical() && !isReserved(Reg)) {
2695 if (
MRI->isReservedRegUnit(Unit))
2698 checkLivenessAtUse(MO, MONum, UseIdx, *LR, Unit);
2702 if (
Reg.isVirtual()) {
2704 checkLivenessAtUse(MO, MONum, UseIdx, *LI, Reg);
2708 ?
TRI->getSubRegIndexLaneMask(SubRegIdx)
2709 :
MRI->getMaxLaneMaskForVReg(Reg);
2712 if ((MOMask & SR.LaneMask).none())
2714 checkLivenessAtUse(MO, MONum, UseIdx, SR, Reg, SR.LaneMask);
2717 LiveInMask |= SR.LaneMask;
2720 if ((LiveInMask & MOMask).
none()) {
2721 report(
"No live subrange at use", MO, MONum);
2722 report_context(*LI);
2723 report_context(UseIdx);
2726 if (
MI->isPHI() && LiveInMask != MOMask) {
2727 report(
"Not all lanes of PHI source live at use", MO, MONum);
2728 report_context(*LI);
2729 report_context(UseIdx);
2736 if (!regsLive.count(Reg)) {
2737 if (
Reg.isPhysical()) {
2739 bool Bad = !isReserved(Reg);
2744 if (regsLive.count(
SubReg)) {
2756 if (!MOP.isReg() || !MOP.isImplicit())
2759 if (!MOP.getReg().isPhysical())
2767 report(
"Using an undefined physical register", MO, MONum);
2768 }
else if (
MRI->def_empty(Reg)) {
2769 report(
"Reading virtual register without a def", MO, MONum);
2771 BBInfo &MInfo = MBBInfoMap[
MI->getParent()];
2775 if (MInfo.regsKilled.count(Reg))
2776 report(
"Using a killed virtual register", MO, MONum);
2777 else if (!
MI->isPHI())
2778 MInfo.vregsLiveIn.insert(std::make_pair(Reg,
MI));
2787 addRegWithSubRegs(regsDead, Reg);
2789 addRegWithSubRegs(regsDefined, Reg);
2792 if (
MRI->isSSA() &&
Reg.isVirtual() &&
2793 std::next(
MRI->def_begin(Reg)) !=
MRI->def_end())
2794 report(
"Multiple virtual register defs in SSA form", MO, MONum);
2801 if (
Reg.isVirtual()) {
2802 checkLivenessAtDef(MO, MONum, DefIdx, *LI, Reg);
2806 ?
TRI->getSubRegIndexLaneMask(SubRegIdx)
2807 :
MRI->getMaxLaneMaskForVReg(Reg);
2809 if ((SR.LaneMask & MOMask).none())
2811 checkLivenessAtDef(MO, MONum, DefIdx, SR, Reg,
true, SR.LaneMask);
2823void MachineVerifier::visitMachineBundleAfter(
const MachineInstr *
MI) {
2824 BBInfo &MInfo = MBBInfoMap[
MI->getParent()];
2825 set_union(MInfo.regsKilled, regsKilled);
2826 set_subtract(regsLive, regsKilled); regsKilled.clear();
2828 while (!regMasks.empty()) {
2831 if (
Reg.isPhysical() &&
2833 regsDead.push_back(Reg);
2836 set_union(regsLive, regsDefined); regsDefined.clear();
2841 MBBInfoMap[
MBB].regsLiveOut = regsLive;
2846 if (!(stop > lastIndex)) {
2847 report(
"Block ends before last instruction index",
MBB);
2848 errs() <<
"Block ends at " << stop
2849 <<
" last instruction was at " << lastIndex <<
'\n';
2864 template <
typename RegSetT>
void add(
const RegSetT &FromRegSet) {
2866 filterAndAdd(FromRegSet, VRegsBuffer);
2871 template <
typename RegSetT>
2872 bool filterAndAdd(
const RegSetT &FromRegSet,
2874 unsigned SparseUniverse = Sparse.size();
2875 unsigned NewSparseUniverse = SparseUniverse;
2876 unsigned NewDenseSize =
Dense.size();
2877 size_t Begin = ToVRegs.
size();
2879 if (!
Reg.isVirtual())
2882 if (
Index < SparseUniverseMax) {
2883 if (
Index < SparseUniverse && Sparse.test(
Index))
2885 NewSparseUniverse = std::max(NewSparseUniverse,
Index + 1);
2900 Sparse.resize(NewSparseUniverse);
2901 Dense.reserve(NewDenseSize);
2902 for (
unsigned I = Begin;
I <
End; ++
I) {
2905 if (
Index < SparseUniverseMax)
2914 static constexpr unsigned SparseUniverseMax = 10 * 1024 * 8;
2934class FilteringVRegSet {
2941 template <
typename RegSetT>
void addToFilter(
const RegSetT &RS) {
2946 template <
typename RegSetT>
bool add(
const RegSetT &RS) {
2949 return Filter.filterAndAdd(RS, VRegs);
2954 size_t size()
const {
return VRegs.
size(); }
2961void MachineVerifier::calcRegsPassed() {
2968 FilteringVRegSet VRegs;
2969 BBInfo &
Info = MBBInfoMap[MB];
2972 VRegs.addToFilter(
Info.regsKilled);
2973 VRegs.addToFilter(
Info.regsLiveOut);
2975 const BBInfo &PredInfo = MBBInfoMap[Pred];
2976 if (!PredInfo.reachable)
2979 VRegs.add(PredInfo.regsLiveOut);
2980 VRegs.add(PredInfo.vregsPassed);
2982 Info.vregsPassed.reserve(VRegs.size());
2983 Info.vregsPassed.insert(VRegs.begin(), VRegs.end());
2990void MachineVerifier::calcRegsRequired() {
2993 for (
const auto &
MBB : *MF) {
2994 BBInfo &MInfo = MBBInfoMap[&
MBB];
2996 BBInfo &PInfo = MBBInfoMap[Pred];
2997 if (PInfo.addRequired(MInfo.vregsLiveIn))
3003 for (
unsigned i = 1, e =
MI.getNumOperands(); i != e; i += 2) {
3005 if (!
MI.getOperand(i).isReg() || !
MI.getOperand(i).readsReg())
3012 BBInfo &PInfo = MBBInfoMap[Pred];
3013 if (PInfo.addRequired(Reg))
3021 while (!todo.
empty()) {
3024 BBInfo &MInfo = MBBInfoMap[
MBB];
3028 BBInfo &SInfo = MBBInfoMap[Pred];
3029 if (SInfo.addRequired(MInfo.vregsRequired))
3038 BBInfo &MInfo = MBBInfoMap[&
MBB];
3048 report(
"Expected first PHI operand to be a register def", &MODef, 0);
3053 report(
"Unexpected flag on PHI operand", &MODef, 0);
3056 report(
"Expected first PHI operand to be a virtual register", &MODef, 0);
3058 for (
unsigned I = 1,
E =
Phi.getNumOperands();
I !=
E;
I += 2) {
3061 report(
"Expected PHI operand to be a register", &MO0,
I);
3066 report(
"Unexpected flag on PHI operand", &MO0,
I);
3070 report(
"Expected PHI operand to be a basic block", &MO1,
I + 1);
3076 report(
"PHI input is not a predecessor block", &MO1,
I + 1);
3080 if (MInfo.reachable) {
3082 BBInfo &PrInfo = MBBInfoMap[&Pre];
3083 if (!MO0.
isUndef() && PrInfo.reachable &&
3084 !PrInfo.isLiveOut(MO0.
getReg()))
3085 report(
"PHI operand is not live-out from predecessor", &MO0,
I);
3090 if (MInfo.reachable) {
3092 if (!seen.
count(Pred)) {
3093 report(
"Missing PHI operand", &Phi);
3095 <<
" is a predecessor according to the CFG.\n";
3104 std::function<
void(
const Twine &Message)> FailureCB) {
3108 for (
const auto &
MBB : MF) {
3120void MachineVerifier::visitMachineFunctionAfter() {
3121 auto FailureCB = [
this](
const Twine &Message) {
3122 report(Message.str().c_str(), MF);
3135 for (
const auto &
MBB : *MF) {
3136 BBInfo &MInfo = MBBInfoMap[&
MBB];
3137 for (
Register VReg : MInfo.vregsRequired)
3138 if (MInfo.regsKilled.count(VReg)) {
3139 report(
"Virtual register killed in block, but needed live out.", &
MBB);
3141 <<
" is used after the block.\n";
3146 BBInfo &MInfo = MBBInfoMap[&MF->front()];
3147 for (
Register VReg : MInfo.vregsRequired) {
3148 report(
"Virtual register defs don't dominate all uses.", MF);
3149 report_context_vreg(VReg);
3154 verifyLiveVariables();
3156 verifyLiveIntervals();
3165 if (
MRI->tracksLiveness())
3166 for (
const auto &
MBB : *MF)
3170 if (hasAliases || isAllocatable(LiveInReg) || isReserved(LiveInReg))
3173 BBInfo &PInfo = MBBInfoMap[Pred];
3174 if (!PInfo.regsLiveOut.count(LiveInReg)) {
3175 report(
"Live in register not found to be live out from predecessor.",
3177 errs() <<
TRI->getName(LiveInReg)
3178 <<
" not found to be live out from "
3184 for (
auto CSInfo : MF->getCallSitesInfo())
3185 if (!CSInfo.first->isCall())
3186 report(
"Call site info referencing instruction that is not call", MF);
3190 if (MF->getFunction().getSubprogram()) {
3192 for (
const auto &
MBB : *MF) {
3193 for (
const auto &
MI :
MBB) {
3194 if (
auto Num =
MI.peekDebugInstrNum()) {
3197 report(
"Instruction has a duplicated value tracking number", &
MI);
3204void MachineVerifier::verifyLiveVariables() {
3205 assert(LiveVars &&
"Don't call verifyLiveVariables without LiveVars");
3206 for (
unsigned I = 0,
E =
MRI->getNumVirtRegs();
I !=
E; ++
I) {
3209 for (
const auto &
MBB : *MF) {
3210 BBInfo &MInfo = MBBInfoMap[&
MBB];
3213 if (MInfo.vregsRequired.count(Reg)) {
3215 report(
"LiveVariables: Block missing from AliveBlocks", &
MBB);
3217 <<
" must be live through the block.\n";
3221 report(
"LiveVariables: Block should not be in AliveBlocks", &
MBB);
3223 <<
" is not needed live through the block.\n";
3230void MachineVerifier::verifyLiveIntervals() {
3231 assert(LiveInts &&
"Don't call verifyLiveIntervals without LiveInts");
3232 for (
unsigned I = 0,
E =
MRI->getNumVirtRegs();
I !=
E; ++
I) {
3236 if (
MRI->reg_nodbg_empty(Reg))
3240 report(
"Missing live interval for virtual register", MF);
3246 assert(Reg == LI.
reg() &&
"Invalid reg to interval mapping");
3247 verifyLiveInterval(LI);
3251 for (
unsigned i = 0, e =
TRI->getNumRegUnits(); i != e; ++i)
3253 verifyLiveRange(*LR, i);
3256void MachineVerifier::verifyLiveRangeValue(
const LiveRange &LR,
3265 report(
"Value not live at VNInfo def and not marked unused", MF);
3266 report_context(LR, Reg, LaneMask);
3267 report_context(*VNI);
3271 if (DefVNI != VNI) {
3272 report(
"Live segment at def has different VNInfo", MF);
3273 report_context(LR, Reg, LaneMask);
3274 report_context(*VNI);
3280 report(
"Invalid VNInfo definition index", MF);
3281 report_context(LR, Reg, LaneMask);
3282 report_context(*VNI);
3288 report(
"PHIDef VNInfo is not defined at MBB start",
MBB);
3289 report_context(LR, Reg, LaneMask);
3290 report_context(*VNI);
3298 report(
"No instruction at VNInfo def index",
MBB);
3299 report_context(LR, Reg, LaneMask);
3300 report_context(*VNI);
3305 bool hasDef =
false;
3306 bool isEarlyClobber =
false;
3308 if (!MOI->isReg() || !MOI->isDef())
3310 if (
Reg.isVirtual()) {
3311 if (MOI->getReg() != Reg)
3314 if (!MOI->getReg().isPhysical() || !
TRI->hasRegUnit(MOI->getReg(), Reg))
3317 if (LaneMask.
any() &&
3318 (
TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
3321 if (MOI->isEarlyClobber())
3322 isEarlyClobber =
true;
3326 report(
"Defining instruction does not modify register",
MI);
3327 report_context(LR, Reg, LaneMask);
3328 report_context(*VNI);
3333 if (isEarlyClobber) {
3335 report(
"Early clobber def must be at an early-clobber slot",
MBB);
3336 report_context(LR, Reg, LaneMask);
3337 report_context(*VNI);
3340 report(
"Non-PHI, non-early clobber def must be at a register slot",
MBB);
3341 report_context(LR, Reg, LaneMask);
3342 report_context(*VNI);
3347void MachineVerifier::verifyLiveRangeSegment(
const LiveRange &LR,
3353 assert(VNI &&
"Live segment has no valno");
3356 report(
"Foreign valno in live segment", MF);
3357 report_context(LR, Reg, LaneMask);
3359 report_context(*VNI);
3363 report(
"Live segment valno is marked unused", MF);
3364 report_context(LR, Reg, LaneMask);
3370 report(
"Bad start of live segment, no basic block", MF);
3371 report_context(LR, Reg, LaneMask);
3377 report(
"Live segment must begin at MBB entry or valno def",
MBB);
3378 report_context(LR, Reg, LaneMask);
3385 report(
"Bad end of live segment, no basic block", MF);
3386 report_context(LR, Reg, LaneMask);
3402 report(
"Live segment doesn't end at a valid instruction", EndMBB);
3403 report_context(LR, Reg, LaneMask);
3410 report(
"Live segment ends at B slot of an instruction", EndMBB);
3411 report_context(LR, Reg, LaneMask);
3419 report(
"Live segment ending at dead slot spans instructions", EndMBB);
3420 report_context(LR, Reg, LaneMask);
3429 if (MF->getProperties().hasProperty(
3432 if (
I + 1 == LR.
end() || (
I + 1)->start != S.
end) {
3433 report(
"Live segment ending at early clobber slot must be "
3434 "redefined by an EC def in the same instruction",
3436 report_context(LR, Reg, LaneMask);
3443 if (
Reg.isVirtual()) {
3446 bool hasRead =
false;
3447 bool hasSubRegDef =
false;
3448 bool hasDeadDef =
false;
3450 if (!MOI->isReg() || MOI->getReg() != Reg)
3452 unsigned Sub = MOI->getSubReg();
3457 hasSubRegDef =
true;
3466 if (LaneMask.
any() && (LaneMask & SLM).none())
3468 if (MOI->readsReg())
3475 if (LaneMask.
none() && !hasDeadDef) {
3477 "Instruction ending live segment on dead slot has no dead flag",
3479 report_context(LR, Reg, LaneMask);
3486 if (!
MRI->shouldTrackSubRegLiveness(Reg) || LaneMask.
any() ||
3488 report(
"Instruction ending live segment doesn't read the register",
3490 report_context(LR, Reg, LaneMask);
3510 if (LaneMask.
any()) {
3518 if (!
Reg.isVirtual() && MFI->isEHPad()) {
3519 if (&*MFI == EndMBB)
3533 if (MFI->isEHPad()) {
3547 if (!PVNI && (LaneMask.
none() || !IsPHI)) {
3550 report(
"Register not marked live out of predecessor", Pred);
3551 report_context(LR, Reg, LaneMask);
3552 report_context(*VNI);
3560 if (!IsPHI && PVNI != VNI) {
3561 report(
"Different value live out of predecessor", Pred);
3562 report_context(LR, Reg, LaneMask);
3563 errs() <<
"Valno #" << PVNI->
id <<
" live out of "
3569 if (&*MFI == EndMBB)
3578 verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
3581 verifyLiveRangeSegment(LR,
I, Reg, LaneMask);
3584void MachineVerifier::verifyLiveInterval(
const LiveInterval &LI) {
3587 verifyLiveRange(LI, Reg);
3593 if ((Mask & SR.LaneMask).any()) {
3594 report(
"Lane masks of sub ranges overlap in live interval", MF);
3597 if ((SR.LaneMask & ~MaxMask).any()) {
3598 report(
"Subrange lanemask is invalid", MF);
3602 report(
"Subrange must not be empty", MF);
3603 report_context(SR, LI.
reg(), SR.LaneMask);
3605 Mask |= SR.LaneMask;
3606 verifyLiveRange(SR, LI.
reg(), SR.LaneMask);
3608 report(
"A Subrange is not covered by the main range", MF);
3616 unsigned NumComp = ConEQ.Classify(LI);
3618 report(
"Multiple connected components in live interval", MF);
3620 for (
unsigned comp = 0; comp != NumComp; ++comp) {
3621 errs() << comp <<
": valnos";
3623 if (comp == ConEQ.getEqClass(
I))
3624 errs() <<
' ' <<
I->id;
3636 struct StackStateOfBB {
3637 StackStateOfBB() =
default;
3638 StackStateOfBB(
int EntryVal,
int ExitVal,
bool EntrySetup,
bool ExitSetup) :
3639 EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
3640 ExitIsSetup(ExitSetup) {}
3645 bool EntryIsSetup =
false;
3646 bool ExitIsSetup =
false;
3654void MachineVerifier::verifyStackFrame() {
3655 unsigned FrameSetupOpcode =
TII->getCallFrameSetupOpcode();
3656 unsigned FrameDestroyOpcode =
TII->getCallFrameDestroyOpcode();
3657 if (FrameSetupOpcode == ~0u && FrameDestroyOpcode == ~0u)
3661 SPState.
resize(MF->getNumBlockIDs());
3668 DFI != DFE; ++DFI) {
3671 StackStateOfBB BBState;
3673 if (DFI.getPathLength() >= 2) {
3676 "DFS stack predecessor is already visited.\n");
3677 BBState.EntryValue = SPState[StackPred->
getNumber()].ExitValue;
3678 BBState.EntryIsSetup = SPState[StackPred->
getNumber()].ExitIsSetup;
3679 BBState.ExitValue = BBState.EntryValue;
3680 BBState.ExitIsSetup = BBState.EntryIsSetup;
3684 report(
"Call frame size on entry does not match value computed from "
3688 <<
" does not match value computed from predecessor "
3689 << -BBState.EntryValue <<
'\n';
3693 for (
const auto &
I : *
MBB) {
3694 if (
I.getOpcode() == FrameSetupOpcode) {
3695 if (BBState.ExitIsSetup)
3696 report(
"FrameSetup is after another FrameSetup", &
I);
3697 BBState.ExitValue -=
TII->getFrameTotalSize(
I);
3698 BBState.ExitIsSetup =
true;
3701 if (
I.getOpcode() == FrameDestroyOpcode) {
3702 int Size =
TII->getFrameTotalSize(
I);
3703 if (!BBState.ExitIsSetup)
3704 report(
"FrameDestroy is not after a FrameSetup", &
I);
3705 int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
3707 if (BBState.ExitIsSetup && AbsSPAdj !=
Size) {
3708 report(
"FrameDestroy <n> is after FrameSetup <m>", &
I);
3709 errs() <<
"FrameDestroy <" <<
Size <<
"> is after FrameSetup <"
3710 << AbsSPAdj <<
">.\n";
3712 BBState.ExitValue +=
Size;
3713 BBState.ExitIsSetup =
false;
3721 if (Reachable.
count(Pred) &&
3722 (SPState[Pred->
getNumber()].ExitValue != BBState.EntryValue ||
3723 SPState[Pred->
getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
3724 report(
"The exit stack state of a predecessor is inconsistent.",
MBB);
3726 <<
" has exit state (" << SPState[Pred->
getNumber()].ExitValue
3727 <<
", " << SPState[Pred->
getNumber()].ExitIsSetup <<
"), while "
3729 << BBState.EntryValue <<
", " << BBState.EntryIsSetup <<
").\n";
3736 if (Reachable.
count(Succ) &&
3737 (SPState[Succ->getNumber()].EntryValue != BBState.ExitValue ||
3738 SPState[Succ->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
3739 report(
"The entry stack state of a successor is inconsistent.",
MBB);
3741 <<
" has entry state (" << SPState[Succ->getNumber()].EntryValue
3742 <<
", " << SPState[Succ->getNumber()].EntryIsSetup <<
"), while "
3744 << BBState.ExitValue <<
", " << BBState.ExitIsSetup <<
").\n";
3750 if (BBState.ExitIsSetup)
3751 report(
"A return block ends with a FrameSetup.",
MBB);
3752 if (BBState.ExitValue)
3753 report(
"A return block ends with a nonzero stack adjustment.",
MBB);
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static bool isLoad(int Opcode)
static bool isStore(int Opcode)
This file implements the BitVector class.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseMap class.
This file defines the DenseSet and SmallDenseSet classes.
This file builds on the ADT/GraphTraits.h file to build generic depth first graph iterator.
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
const HexagonInstrInfo * TII
A common definition of LaneBitmask for use in TableGen and CodeGen.
Implement a low-level type suitable for MachineInstr level instruction selection.
This file declares the MIR specialization of the GenericConvergenceVerifier template.
unsigned const TargetRegisterInfo * TRI
static void verifyConvergenceControl(const MachineFunction &MF, MachineDomTree &DT, std::function< void(const Twine &Message)> FailureCB)
modulo schedule Modulo Schedule test pass
const char LLVMTargetMachineRef TM
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg)
This file defines generic set operations that may be used on set's of different types,...
This file defines the SmallPtrSet class.
This file defines the SmallVector class.
static unsigned getSize(unsigned Kind)
const fltSemantics & getSemantics() const
Represent the analysis usage information of a pass.
AnalysisUsage & addUsedIfAvailable()
Add the specified Pass class to the set of analyses used by this pass.
void setPreservesAll()
Set by analyses that do not transform their input at all.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
LLVM Basic Block Representation.
bool hasAddressTaken() const
Returns true if there are any uses of this basic block other than direct branches,...
const Instruction * getTerminator() const LLVM_READONLY
Returns the terminator instruction if the block is well formed or null if the block is not well forme...
bool test(unsigned Idx) const
void clear()
clear - Removes all bits from the bitvector.
iterator_range< const_set_bits_iterator > set_bits() const
size_type size() const
size - Returns the number of bits in this bitvector.
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
ConstantFP - Floating Point Values [float, double].
const APFloat & getValueAPF() const
This is the shared class of boolean and integer constants.
unsigned getBitWidth() const
getBitWidth - Return the scalar bitwidth of this constant.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Implements a dense probed hash-table based set.
Core dominator tree base class.
void recalculate(ParentType &Func)
recalculate - compute a dominator tree for the given function
Base class for user error types.
A specialized PseudoSourceValue for holding FixedStack values, which must include a frame index.
FunctionPass class - This class is used to implement most global optimizations.
void initialize(raw_ostream *OS, function_ref< void(const Twine &Message)> FailureCB, const FunctionT &F)
void verify(const DominatorTreeT &DT)
void visit(const BlockT &BB)
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
constexpr bool isScalableVector() const
Returns true if the LLT is a scalable vector.
constexpr unsigned getScalarSizeInBits() const
constexpr bool isScalar() const
constexpr bool isValid() const
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
constexpr bool isVector() const
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
constexpr bool isPointer() const
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
constexpr ElementCount getElementCount() const
constexpr unsigned getAddressSpace() const
constexpr bool isPointerOrPointerVector() const
constexpr LLT getScalarType() const
constexpr TypeSize getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
A live range for subregisters.
LiveInterval - This class represents the liveness of a register, or stack slot.
bool hasSubRanges() const
Returns true if subregister liveness information is available.
iterator_range< subrange_iterator > subranges()
void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const
For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...
bool hasInterval(Register Reg) const
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
LiveRange * getCachedRegUnit(unsigned Unit)
Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn't...
LiveInterval & getInterval(Register Reg)
bool isNotInMIMap(const MachineInstr &Instr) const
Returns true if the specified machine instr has been removed or was never entered in the map.
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
void print(raw_ostream &O, const Module *=nullptr) const override
Implement the dump method.
Result of a LiveRange query.
bool isDeadDef() const
Return true if this instruction has a dead def.
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
VNInfo * valueOut() const
Return the value leaving the instruction, if any.
bool isKill() const
Return true if the live-in value is killed by this instruction.
static LLVM_ATTRIBUTE_UNUSED bool isJointlyDominated(const MachineBasicBlock *MBB, ArrayRef< SlotIndex > Defs, const SlotIndexes &Indexes)
A diagnostic function to check if the end of the block MBB is jointly dominated by the blocks corresp...
This class represents the liveness of a register, stack slot, etc.
VNInfo * getValNumInfo(unsigned ValNo)
getValNumInfo - Returns pointer to the specified val#.
bool liveAt(SlotIndex index) const
bool covers(const LiveRange &Other) const
Returns true if all segments of the Other live range are completely covered by this live range.
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarilly including Idx,...
unsigned getNumValNums() const
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
LiveInterval & getInterval(int Slot)
bool hasInterval(int Slot) const
VarInfo & getVarInfo(Register Reg)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
This class is intended to be used as a base class for asm properties and features specific to the tar...
ExceptionHandling getExceptionHandlingType() const
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
bool isConvergent() const
Return true if this instruction is convergent.
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
unsigned getOpcode() const
Return the opcode number for this descriptor.
This holds information about one operand of a machine instruction, indicating the register class for ...
bool isOptionalDef() const
Set if this operand is a optional def.
uint8_t OperandType
Information about the type of the operand.
MCRegAliasIterator enumerates all registers aliasing Reg.
bool isValid() const
isValid - Returns true until all the operands have been visited.
bool isInlineAsmBrIndirectTarget() const
Returns true if this is the indirect dest of an INLINEASM_BR.
unsigned pred_size() const
bool isEHPad() const
Returns true if the block is a landing pad.
iterator_range< livein_iterator > liveins() const
iterator_range< iterator > phis()
Returns a range that iterates over the phis in the basic block.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
succ_iterator succ_begin()
bool isIRBlockAddressTaken() const
Test whether this block is the target of an IR BlockAddress.
unsigned succ_size() const
BasicBlock * getAddressTakenIRBlock() const
Retrieves the BasicBlock which corresponds to this MachineBasicBlock.
bool isPredecessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a predecessor of this block.
pred_iterator pred_begin()
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
unsigned getCallFrameSize() const
Return the call frame size on entry to this basic block.
iterator_range< succ_iterator > successors()
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
iterator_range< pred_iterator > predecessors()
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool hasProperty(Property P) const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineFunctionProperties & getProperties() const
Get the function properties.
const MachineBasicBlock & front() const
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use.
void print(raw_ostream &OS, const SlotIndexes *=nullptr) const
print - Print out the MachineFunction in a format suitable for debugging to the specified stream.
BasicBlockListType::const_iterator const_iterator
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
bool isReturn(QueryType Type=AnyInBundle) const
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
A description of a memory reference used in the backend.
const PseudoSourceValue * getPseudoValue() const
uint64_t getSize() const
Return the size in bytes of the memory reference.
AtomicOrdering getSuccessOrdering() const
Return the atomic ordering requirements for this memory operation.
uint64_t getSizeInBits() const
Return the size in bits of the memory reference.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
bool isIntrinsicID() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
ArrayRef< int > getShuffleMask() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isValidExcessOperand() const
Return true if this operand can validly be appended to an arbitrary operand list.
bool isShuffleMask() const
unsigned getCFIIndex() const
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
bool isEarlyClobber() const
Register getReg() const
getReg - Returns the register number.
bool isInternalRead() const
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
@ MO_CFIIndex
MCCFIInstruction index.
@ MO_RegisterMask
Mask of preserved registers.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_FrameIndex
Abstract Stack Frame Index.
@ MO_Register
Register operand.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Pass interface - Implemented by all 'passes'.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
AnalysisType * getAnalysisIfAvailable() const
getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information tha...
Special value supplied for machine level alias analysis.
Holds all the information related to register banks.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getMaximumSize(unsigned RegBankID) const
Get the maximum size in bits that fits in the given register bank.
This class implements the register bank concept.
const char * getName() const
Get a user friendly name of this register bank.
unsigned getID() const
Get the identifier of this register bank.
Wrapper class representing virtual and physical registers.
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
static constexpr bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
SlotIndex - An opaque wrapper around machine indexes.
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
bool isBlock() const
isBlock - Returns true if this is a block boundary slot.
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
bool isEarlyClobber() const
isEarlyClobber - Returns true if this is an early-clobber slot.
bool isRegister() const
isRegister - Returns true if this is a normal register use/def slot.
SlotIndex getBoundaryIndex() const
Returns the boundary index for associated with this index.
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
bool isDead() const
isDead - Returns true if this is a dead def kill slot.
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
MBBIndexIterator MBBIndexBegin() const
Returns an iterator for the begin of the idx2MBBMap.
MBBIndexIterator MBBIndexEnd() const
Return an iterator for the end of the idx2MBBMap.
SmallVectorImpl< IdxMBBPair >::const_iterator MBBIndexIterator
Iterator over the idx2MBBMap (sorted pairs of slot index of basic block begin and basic block)
SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const
Returns the base index for the given instruction.
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
bool hasIndex(const MachineInstr &instr) const
Returns true if the given machine instr is mapped to an index, otherwise returns false.
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false.
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
MI-level Statepoint operands.
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
Primary interface to the complete machine description for the target machine.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
VNInfo - Value Number Information.
bool isUnused() const
Returns true if this value is unused.
unsigned id
The ID number of this value.
SlotIndex def
The index of the defining instruction.
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
LLVM Value Representation.
std::pair< iterator, bool > insert(const ValueT &V)
constexpr bool isNonZero() const
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
self_iterator getIterator()
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
constexpr char Attrs[]
Key for Kernel::Metadata::mAttrs.
const CustomOperand< const MCSubtargetInfo & > Msg[]
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
AttributeList getAttributes(LLVMContext &C, ID id)
Return the attributes for an intrinsic.
Reg
All possible values of the reg field in the ModR/M byte.
NodeAddr< PhiNode * > Phi
NodeAddr< DefNode * > Def
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
const_iterator end(StringRef path)
Get end iterator over path.
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
@ SjLj
setjmp/longjmp based exceptions
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
void append_range(Container &C, Range &&R)
Wrapper function to append range R to container C.
void set_subtract(S1Ty &S1, const S2Ty &S2)
set_subtract(A, B) - Compute A := A - B
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
bool isPreISelGenericOptimizationHint(unsigned Opcode)
bool isScopedEHPersonality(EHPersonality Pers)
Returns true if this personality uses scope-style EH IR instructions: catchswitch,...
void initializeMachineVerifierPassPass(PassRegistry &)
void verifyMachineFunction(const std::string &Banner, const MachineFunction &MF)
auto reverse(ContainerTy &&C)
detail::ValueMatchesPoly< M > HasValue(M Matcher)
df_ext_iterator< T, SetTy > df_ext_begin(const T &G, SetTy &S)
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
bool set_union(S1Ty &S1, const S2Ty &S2)
set_union(A, B) - Compute A := A u B, return whether A changed.
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
AtomicOrdering
Atomic ordering for LLVM's memory model.
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
df_ext_iterator< T, SetTy > df_ext_end(const T &G, SetTy &S)
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness.
Implement std::hash so that hash_code can be used in STL containers.
static unsigned getSizeInBits(const fltSemantics &Sem)
Returns the size of the floating point number (in bits) in the given semantics.
static constexpr LaneBitmask getAll()
constexpr bool none() const
constexpr bool any() const
static constexpr LaneBitmask getNone()
This represents a simple continuous liveness interval for a value.
VarInfo - This represents the regions where a virtual register is live in the program.
Pair of physical register and lane mask.