LLVM 19.0.0git
MachineVerifier.cpp
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1//===- MachineVerifier.cpp - Machine Code Verifier ------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Pass to verify generated machine code. The following is checked:
10//
11// Operand counts: All explicit operands must be present.
12//
13// Register classes: All physical and virtual register operands must be
14// compatible with the register class required by the instruction descriptor.
15//
16// Register live intervals: Registers must be defined only once, and must be
17// defined before use.
18//
19// The machine code verifier is enabled with the command-line option
20// -verify-machineinstrs.
21//===----------------------------------------------------------------------===//
22
23#include "llvm/ADT/BitVector.h"
24#include "llvm/ADT/DenseMap.h"
25#include "llvm/ADT/DenseSet.h"
28#include "llvm/ADT/STLExtras.h"
32#include "llvm/ADT/StringRef.h"
33#include "llvm/ADT/Twine.h"
62#include "llvm/IR/BasicBlock.h"
63#include "llvm/IR/Constants.h"
65#include "llvm/IR/Function.h"
66#include "llvm/IR/InlineAsm.h"
69#include "llvm/MC/LaneBitmask.h"
70#include "llvm/MC/MCAsmInfo.h"
71#include "llvm/MC/MCDwarf.h"
72#include "llvm/MC/MCInstrDesc.h"
75#include "llvm/Pass.h"
79#include "llvm/Support/ModRef.h"
82#include <algorithm>
83#include <cassert>
84#include <cstddef>
85#include <cstdint>
86#include <iterator>
87#include <string>
88#include <utility>
89
90using namespace llvm;
91
92namespace {
93
94 struct MachineVerifier {
95 MachineVerifier(Pass *pass, const char *b) : PASS(pass), Banner(b) {}
96
97 MachineVerifier(const char *b, LiveVariables *LiveVars,
98 LiveIntervals *LiveInts, LiveStacks *LiveStks,
99 SlotIndexes *Indexes)
100 : Banner(b), LiveVars(LiveVars), LiveInts(LiveInts), LiveStks(LiveStks),
101 Indexes(Indexes) {}
102
103 unsigned verify(const MachineFunction &MF);
104
105 Pass *const PASS = nullptr;
106 const char *Banner;
107 const MachineFunction *MF = nullptr;
108 const TargetMachine *TM = nullptr;
109 const TargetInstrInfo *TII = nullptr;
110 const TargetRegisterInfo *TRI = nullptr;
111 const MachineRegisterInfo *MRI = nullptr;
112 const RegisterBankInfo *RBI = nullptr;
113
114 unsigned foundErrors = 0;
115
116 // Avoid querying the MachineFunctionProperties for each operand.
117 bool isFunctionRegBankSelected = false;
118 bool isFunctionSelected = false;
119 bool isFunctionTracksDebugUserValues = false;
120
121 using RegVector = SmallVector<Register, 16>;
122 using RegMaskVector = SmallVector<const uint32_t *, 4>;
123 using RegSet = DenseSet<Register>;
126
127 const MachineInstr *FirstNonPHI = nullptr;
128 const MachineInstr *FirstTerminator = nullptr;
129 BlockSet FunctionBlocks;
130
131 BitVector regsReserved;
132 RegSet regsLive;
133 RegVector regsDefined, regsDead, regsKilled;
134 RegMaskVector regMasks;
135
136 SlotIndex lastIndex;
137
138 // Add Reg and any sub-registers to RV
139 void addRegWithSubRegs(RegVector &RV, Register Reg) {
140 RV.push_back(Reg);
141 if (Reg.isPhysical())
142 append_range(RV, TRI->subregs(Reg.asMCReg()));
143 }
144
145 struct BBInfo {
146 // Is this MBB reachable from the MF entry point?
147 bool reachable = false;
148
149 // Vregs that must be live in because they are used without being
150 // defined. Map value is the user. vregsLiveIn doesn't include regs
151 // that only are used by PHI nodes.
152 RegMap vregsLiveIn;
153
154 // Regs killed in MBB. They may be defined again, and will then be in both
155 // regsKilled and regsLiveOut.
156 RegSet regsKilled;
157
158 // Regs defined in MBB and live out. Note that vregs passing through may
159 // be live out without being mentioned here.
160 RegSet regsLiveOut;
161
162 // Vregs that pass through MBB untouched. This set is disjoint from
163 // regsKilled and regsLiveOut.
164 RegSet vregsPassed;
165
166 // Vregs that must pass through MBB because they are needed by a successor
167 // block. This set is disjoint from regsLiveOut.
168 RegSet vregsRequired;
169
170 // Set versions of block's predecessor and successor lists.
171 BlockSet Preds, Succs;
172
173 BBInfo() = default;
174
175 // Add register to vregsRequired if it belongs there. Return true if
176 // anything changed.
177 bool addRequired(Register Reg) {
178 if (!Reg.isVirtual())
179 return false;
180 if (regsLiveOut.count(Reg))
181 return false;
182 return vregsRequired.insert(Reg).second;
183 }
184
185 // Same for a full set.
186 bool addRequired(const RegSet &RS) {
187 bool Changed = false;
188 for (Register Reg : RS)
189 Changed |= addRequired(Reg);
190 return Changed;
191 }
192
193 // Same for a full map.
194 bool addRequired(const RegMap &RM) {
195 bool Changed = false;
196 for (const auto &I : RM)
197 Changed |= addRequired(I.first);
198 return Changed;
199 }
200
201 // Live-out registers are either in regsLiveOut or vregsPassed.
202 bool isLiveOut(Register Reg) const {
203 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
204 }
205 };
206
207 // Extra register info per MBB.
209
210 bool isReserved(Register Reg) {
211 return Reg.id() < regsReserved.size() && regsReserved.test(Reg.id());
212 }
213
214 bool isAllocatable(Register Reg) const {
215 return Reg.id() < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) &&
216 !regsReserved.test(Reg.id());
217 }
218
219 // Analysis information if available
220 LiveVariables *LiveVars = nullptr;
221 LiveIntervals *LiveInts = nullptr;
222 LiveStacks *LiveStks = nullptr;
223 SlotIndexes *Indexes = nullptr;
224
225 // This is calculated only when trying to verify convergence control tokens.
226 // Similar to the LLVM IR verifier, we calculate this locally instead of
227 // relying on the pass manager.
229
230 void visitMachineFunctionBefore();
231 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
232 void visitMachineBundleBefore(const MachineInstr *MI);
233
234 /// Verify that all of \p MI's virtual register operands are scalars.
235 /// \returns True if all virtual register operands are scalar. False
236 /// otherwise.
237 bool verifyAllRegOpsScalar(const MachineInstr &MI,
238 const MachineRegisterInfo &MRI);
239 bool verifyVectorElementMatch(LLT Ty0, LLT Ty1, const MachineInstr *MI);
240
241 bool verifyGIntrinsicSideEffects(const MachineInstr *MI);
242 bool verifyGIntrinsicConvergence(const MachineInstr *MI);
243 void verifyPreISelGenericInstruction(const MachineInstr *MI);
244
245 void visitMachineInstrBefore(const MachineInstr *MI);
246 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
247 void visitMachineBundleAfter(const MachineInstr *MI);
248 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
249 void visitMachineFunctionAfter();
250
251 void report(const char *msg, const MachineFunction *MF);
252 void report(const char *msg, const MachineBasicBlock *MBB);
253 void report(const char *msg, const MachineInstr *MI);
254 void report(const char *msg, const MachineOperand *MO, unsigned MONum,
255 LLT MOVRegType = LLT{});
256 void report(const Twine &Msg, const MachineInstr *MI);
257
258 void report_context(const LiveInterval &LI) const;
259 void report_context(const LiveRange &LR, Register VRegUnit,
260 LaneBitmask LaneMask) const;
261 void report_context(const LiveRange::Segment &S) const;
262 void report_context(const VNInfo &VNI) const;
263 void report_context(SlotIndex Pos) const;
264 void report_context(MCPhysReg PhysReg) const;
265 void report_context_liverange(const LiveRange &LR) const;
266 void report_context_lanemask(LaneBitmask LaneMask) const;
267 void report_context_vreg(Register VReg) const;
268 void report_context_vreg_regunit(Register VRegOrUnit) const;
269
270 void verifyInlineAsm(const MachineInstr *MI);
271
272 void checkLiveness(const MachineOperand *MO, unsigned MONum);
273 void checkLivenessAtUse(const MachineOperand *MO, unsigned MONum,
274 SlotIndex UseIdx, const LiveRange &LR,
275 Register VRegOrUnit,
276 LaneBitmask LaneMask = LaneBitmask::getNone());
277 void checkLivenessAtDef(const MachineOperand *MO, unsigned MONum,
278 SlotIndex DefIdx, const LiveRange &LR,
279 Register VRegOrUnit, bool SubRangeCheck = false,
280 LaneBitmask LaneMask = LaneBitmask::getNone());
281
282 void markReachable(const MachineBasicBlock *MBB);
283 void calcRegsPassed();
284 void checkPHIOps(const MachineBasicBlock &MBB);
285
286 void calcRegsRequired();
287 void verifyLiveVariables();
288 void verifyLiveIntervals();
289 void verifyLiveInterval(const LiveInterval&);
290 void verifyLiveRangeValue(const LiveRange &, const VNInfo *, Register,
292 void verifyLiveRangeSegment(const LiveRange &,
295 void verifyLiveRange(const LiveRange &, Register,
296 LaneBitmask LaneMask = LaneBitmask::getNone());
297
298 void verifyStackFrame();
299
300 void verifySlotIndexes() const;
301 void verifyProperties(const MachineFunction &MF);
302 };
303
304 struct MachineVerifierPass : public MachineFunctionPass {
305 static char ID; // Pass ID, replacement for typeid
306
307 const std::string Banner;
308
309 MachineVerifierPass(std::string banner = std::string())
310 : MachineFunctionPass(ID), Banner(std::move(banner)) {
312 }
313
314 void getAnalysisUsage(AnalysisUsage &AU) const override {
319 AU.setPreservesAll();
321 }
322
323 bool runOnMachineFunction(MachineFunction &MF) override {
324 // Skip functions that have known verification problems.
325 // FIXME: Remove this mechanism when all problematic passes have been
326 // fixed.
327 if (MF.getProperties().hasProperty(
328 MachineFunctionProperties::Property::FailsVerification))
329 return false;
330
331 unsigned FoundErrors = MachineVerifier(this, Banner.c_str()).verify(MF);
332 if (FoundErrors)
333 report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
334 return false;
335 }
336 };
337
338} // end anonymous namespace
339
340char MachineVerifierPass::ID = 0;
341
342INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
343 "Verify generated machine code", false, false)
344
346 return new MachineVerifierPass(Banner);
347}
348
349void llvm::verifyMachineFunction(const std::string &Banner,
350 const MachineFunction &MF) {
351 // TODO: Use MFAM after porting below analyses.
352 // LiveVariables *LiveVars;
353 // LiveIntervals *LiveInts;
354 // LiveStacks *LiveStks;
355 // SlotIndexes *Indexes;
356 unsigned FoundErrors = MachineVerifier(nullptr, Banner.c_str()).verify(MF);
357 if (FoundErrors)
358 report_fatal_error("Found " + Twine(FoundErrors) + " machine code errors.");
359}
360
361bool MachineFunction::verify(Pass *p, const char *Banner, bool AbortOnErrors)
362 const {
363 MachineFunction &MF = const_cast<MachineFunction&>(*this);
364 unsigned FoundErrors = MachineVerifier(p, Banner).verify(MF);
365 if (AbortOnErrors && FoundErrors)
366 report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
367 return FoundErrors == 0;
368}
369
371 const char *Banner, bool AbortOnErrors) const {
372 MachineFunction &MF = const_cast<MachineFunction &>(*this);
373 unsigned FoundErrors =
374 MachineVerifier(Banner, nullptr, LiveInts, nullptr, Indexes).verify(MF);
375 if (AbortOnErrors && FoundErrors)
376 report_fatal_error("Found " + Twine(FoundErrors) + " machine code errors.");
377 return FoundErrors == 0;
378}
379
380void MachineVerifier::verifySlotIndexes() const {
381 if (Indexes == nullptr)
382 return;
383
384 // Ensure the IdxMBB list is sorted by slot indexes.
387 E = Indexes->MBBIndexEnd(); I != E; ++I) {
388 assert(!Last.isValid() || I->first > Last);
389 Last = I->first;
390 }
391}
392
393void MachineVerifier::verifyProperties(const MachineFunction &MF) {
394 // If a pass has introduced virtual registers without clearing the
395 // NoVRegs property (or set it without allocating the vregs)
396 // then report an error.
397 if (MF.getProperties().hasProperty(
399 MRI->getNumVirtRegs())
400 report("Function has NoVRegs property but there are VReg operands", &MF);
401}
402
403unsigned MachineVerifier::verify(const MachineFunction &MF) {
404 foundErrors = 0;
405
406 this->MF = &MF;
407 TM = &MF.getTarget();
410 RBI = MF.getSubtarget().getRegBankInfo();
411 MRI = &MF.getRegInfo();
412
413 const bool isFunctionFailedISel = MF.getProperties().hasProperty(
415
416 // If we're mid-GlobalISel and we already triggered the fallback path then
417 // it's expected that the MIR is somewhat broken but that's ok since we'll
418 // reset it and clear the FailedISel attribute in ResetMachineFunctions.
419 if (isFunctionFailedISel)
420 return foundErrors;
421
422 isFunctionRegBankSelected = MF.getProperties().hasProperty(
424 isFunctionSelected = MF.getProperties().hasProperty(
426 isFunctionTracksDebugUserValues = MF.getProperties().hasProperty(
428
429 if (PASS) {
430 LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
431 // We don't want to verify LiveVariables if LiveIntervals is available.
432 if (!LiveInts)
433 LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
434 LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
435 Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
436 }
437
438 verifySlotIndexes();
439
440 verifyProperties(MF);
441
442 visitMachineFunctionBefore();
443 for (const MachineBasicBlock &MBB : MF) {
444 visitMachineBasicBlockBefore(&MBB);
445 // Keep track of the current bundle header.
446 const MachineInstr *CurBundle = nullptr;
447 // Do we expect the next instruction to be part of the same bundle?
448 bool InBundle = false;
449
450 for (const MachineInstr &MI : MBB.instrs()) {
451 if (MI.getParent() != &MBB) {
452 report("Bad instruction parent pointer", &MBB);
453 errs() << "Instruction: " << MI;
454 continue;
455 }
456
457 // Check for consistent bundle flags.
458 if (InBundle && !MI.isBundledWithPred())
459 report("Missing BundledPred flag, "
460 "BundledSucc was set on predecessor",
461 &MI);
462 if (!InBundle && MI.isBundledWithPred())
463 report("BundledPred flag is set, "
464 "but BundledSucc not set on predecessor",
465 &MI);
466
467 // Is this a bundle header?
468 if (!MI.isInsideBundle()) {
469 if (CurBundle)
470 visitMachineBundleAfter(CurBundle);
471 CurBundle = &MI;
472 visitMachineBundleBefore(CurBundle);
473 } else if (!CurBundle)
474 report("No bundle header", &MI);
475 visitMachineInstrBefore(&MI);
476 for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
477 const MachineOperand &Op = MI.getOperand(I);
478 if (Op.getParent() != &MI) {
479 // Make sure to use correct addOperand / removeOperand / ChangeTo
480 // functions when replacing operands of a MachineInstr.
481 report("Instruction has operand with wrong parent set", &MI);
482 }
483
484 visitMachineOperand(&Op, I);
485 }
486
487 // Was this the last bundled instruction?
488 InBundle = MI.isBundledWithSucc();
489 }
490 if (CurBundle)
491 visitMachineBundleAfter(CurBundle);
492 if (InBundle)
493 report("BundledSucc flag set on last instruction in block", &MBB.back());
494 visitMachineBasicBlockAfter(&MBB);
495 }
496 visitMachineFunctionAfter();
497
498 // Clean up.
499 regsLive.clear();
500 regsDefined.clear();
501 regsDead.clear();
502 regsKilled.clear();
503 regMasks.clear();
504 MBBInfoMap.clear();
505
506 return foundErrors;
507}
508
509void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
510 assert(MF);
511 errs() << '\n';
512 if (!foundErrors++) {
513 if (Banner)
514 errs() << "# " << Banner << '\n';
515 if (LiveInts != nullptr)
516 LiveInts->print(errs());
517 else
518 MF->print(errs(), Indexes);
519 }
520 errs() << "*** Bad machine code: " << msg << " ***\n"
521 << "- function: " << MF->getName() << "\n";
522}
523
524void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
525 assert(MBB);
526 report(msg, MBB->getParent());
527 errs() << "- basic block: " << printMBBReference(*MBB) << ' '
528 << MBB->getName() << " (" << (const void *)MBB << ')';
529 if (Indexes)
530 errs() << " [" << Indexes->getMBBStartIdx(MBB)
531 << ';' << Indexes->getMBBEndIdx(MBB) << ')';
532 errs() << '\n';
533}
534
535void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
536 assert(MI);
537 report(msg, MI->getParent());
538 errs() << "- instruction: ";
539 if (Indexes && Indexes->hasIndex(*MI))
540 errs() << Indexes->getInstructionIndex(*MI) << '\t';
541 MI->print(errs(), /*IsStandalone=*/true);
542}
543
544void MachineVerifier::report(const char *msg, const MachineOperand *MO,
545 unsigned MONum, LLT MOVRegType) {
546 assert(MO);
547 report(msg, MO->getParent());
548 errs() << "- operand " << MONum << ": ";
549 MO->print(errs(), MOVRegType, TRI);
550 errs() << "\n";
551}
552
553void MachineVerifier::report(const Twine &Msg, const MachineInstr *MI) {
554 report(Msg.str().c_str(), MI);
555}
556
557void MachineVerifier::report_context(SlotIndex Pos) const {
558 errs() << "- at: " << Pos << '\n';
559}
560
561void MachineVerifier::report_context(const LiveInterval &LI) const {
562 errs() << "- interval: " << LI << '\n';
563}
564
565void MachineVerifier::report_context(const LiveRange &LR, Register VRegUnit,
566 LaneBitmask LaneMask) const {
567 report_context_liverange(LR);
568 report_context_vreg_regunit(VRegUnit);
569 if (LaneMask.any())
570 report_context_lanemask(LaneMask);
571}
572
573void MachineVerifier::report_context(const LiveRange::Segment &S) const {
574 errs() << "- segment: " << S << '\n';
575}
576
577void MachineVerifier::report_context(const VNInfo &VNI) const {
578 errs() << "- ValNo: " << VNI.id << " (def " << VNI.def << ")\n";
579}
580
581void MachineVerifier::report_context_liverange(const LiveRange &LR) const {
582 errs() << "- liverange: " << LR << '\n';
583}
584
585void MachineVerifier::report_context(MCPhysReg PReg) const {
586 errs() << "- p. register: " << printReg(PReg, TRI) << '\n';
587}
588
589void MachineVerifier::report_context_vreg(Register VReg) const {
590 errs() << "- v. register: " << printReg(VReg, TRI) << '\n';
591}
592
593void MachineVerifier::report_context_vreg_regunit(Register VRegOrUnit) const {
594 if (VRegOrUnit.isVirtual()) {
595 report_context_vreg(VRegOrUnit);
596 } else {
597 errs() << "- regunit: " << printRegUnit(VRegOrUnit, TRI) << '\n';
598 }
599}
600
601void MachineVerifier::report_context_lanemask(LaneBitmask LaneMask) const {
602 errs() << "- lanemask: " << PrintLaneMask(LaneMask) << '\n';
603}
604
605void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
606 BBInfo &MInfo = MBBInfoMap[MBB];
607 if (!MInfo.reachable) {
608 MInfo.reachable = true;
609 for (const MachineBasicBlock *Succ : MBB->successors())
610 markReachable(Succ);
611 }
612}
613
614void MachineVerifier::visitMachineFunctionBefore() {
615 lastIndex = SlotIndex();
616 regsReserved = MRI->reservedRegsFrozen() ? MRI->getReservedRegs()
617 : TRI->getReservedRegs(*MF);
618
619 if (!MF->empty())
620 markReachable(&MF->front());
621
622 // Build a set of the basic blocks in the function.
623 FunctionBlocks.clear();
624 for (const auto &MBB : *MF) {
625 FunctionBlocks.insert(&MBB);
626 BBInfo &MInfo = MBBInfoMap[&MBB];
627
628 MInfo.Preds.insert(MBB.pred_begin(), MBB.pred_end());
629 if (MInfo.Preds.size() != MBB.pred_size())
630 report("MBB has duplicate entries in its predecessor list.", &MBB);
631
632 MInfo.Succs.insert(MBB.succ_begin(), MBB.succ_end());
633 if (MInfo.Succs.size() != MBB.succ_size())
634 report("MBB has duplicate entries in its successor list.", &MBB);
635 }
636
637 // Check that the register use lists are sane.
638 MRI->verifyUseLists();
639
640 if (!MF->empty())
641 verifyStackFrame();
642}
643
644void
645MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
646 FirstTerminator = nullptr;
647 FirstNonPHI = nullptr;
648
649 if (!MF->getProperties().hasProperty(
650 MachineFunctionProperties::Property::NoPHIs) && MRI->tracksLiveness()) {
651 // If this block has allocatable physical registers live-in, check that
652 // it is an entry block or landing pad.
653 for (const auto &LI : MBB->liveins()) {
654 if (isAllocatable(LI.PhysReg) && !MBB->isEHPad() &&
655 MBB->getIterator() != MBB->getParent()->begin() &&
657 report("MBB has allocatable live-in, but isn't entry, landing-pad, or "
658 "inlineasm-br-indirect-target.",
659 MBB);
660 report_context(LI.PhysReg);
661 }
662 }
663 }
664
665 if (MBB->isIRBlockAddressTaken()) {
667 report("ir-block-address-taken is associated with basic block not used by "
668 "a blockaddress.",
669 MBB);
670 }
671
672 // Count the number of landing pad successors.
674 for (const auto *succ : MBB->successors()) {
675 if (succ->isEHPad())
676 LandingPadSuccs.insert(succ);
677 if (!FunctionBlocks.count(succ))
678 report("MBB has successor that isn't part of the function.", MBB);
679 if (!MBBInfoMap[succ].Preds.count(MBB)) {
680 report("Inconsistent CFG", MBB);
681 errs() << "MBB is not in the predecessor list of the successor "
682 << printMBBReference(*succ) << ".\n";
683 }
684 }
685
686 // Check the predecessor list.
687 for (const MachineBasicBlock *Pred : MBB->predecessors()) {
688 if (!FunctionBlocks.count(Pred))
689 report("MBB has predecessor that isn't part of the function.", MBB);
690 if (!MBBInfoMap[Pred].Succs.count(MBB)) {
691 report("Inconsistent CFG", MBB);
692 errs() << "MBB is not in the successor list of the predecessor "
693 << printMBBReference(*Pred) << ".\n";
694 }
695 }
696
697 const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
698 const BasicBlock *BB = MBB->getBasicBlock();
699 const Function &F = MF->getFunction();
700 if (LandingPadSuccs.size() > 1 &&
701 !(AsmInfo &&
703 BB && isa<SwitchInst>(BB->getTerminator())) &&
704 !isScopedEHPersonality(classifyEHPersonality(F.getPersonalityFn())))
705 report("MBB has more than one landing pad successor", MBB);
706
707 // Call analyzeBranch. If it succeeds, there several more conditions to check.
708 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
710 if (!TII->analyzeBranch(*const_cast<MachineBasicBlock *>(MBB), TBB, FBB,
711 Cond)) {
712 // Ok, analyzeBranch thinks it knows what's going on with this block. Let's
713 // check whether its answers match up with reality.
714 if (!TBB && !FBB) {
715 // Block falls through to its successor.
716 if (!MBB->empty() && MBB->back().isBarrier() &&
717 !TII->isPredicated(MBB->back())) {
718 report("MBB exits via unconditional fall-through but ends with a "
719 "barrier instruction!", MBB);
720 }
721 if (!Cond.empty()) {
722 report("MBB exits via unconditional fall-through but has a condition!",
723 MBB);
724 }
725 } else if (TBB && !FBB && Cond.empty()) {
726 // Block unconditionally branches somewhere.
727 if (MBB->empty()) {
728 report("MBB exits via unconditional branch but doesn't contain "
729 "any instructions!", MBB);
730 } else if (!MBB->back().isBarrier()) {
731 report("MBB exits via unconditional branch but doesn't end with a "
732 "barrier instruction!", MBB);
733 } else if (!MBB->back().isTerminator()) {
734 report("MBB exits via unconditional branch but the branch isn't a "
735 "terminator instruction!", MBB);
736 }
737 } else if (TBB && !FBB && !Cond.empty()) {
738 // Block conditionally branches somewhere, otherwise falls through.
739 if (MBB->empty()) {
740 report("MBB exits via conditional branch/fall-through but doesn't "
741 "contain any instructions!", MBB);
742 } else if (MBB->back().isBarrier()) {
743 report("MBB exits via conditional branch/fall-through but ends with a "
744 "barrier instruction!", MBB);
745 } else if (!MBB->back().isTerminator()) {
746 report("MBB exits via conditional branch/fall-through but the branch "
747 "isn't a terminator instruction!", MBB);
748 }
749 } else if (TBB && FBB) {
750 // Block conditionally branches somewhere, otherwise branches
751 // somewhere else.
752 if (MBB->empty()) {
753 report("MBB exits via conditional branch/branch but doesn't "
754 "contain any instructions!", MBB);
755 } else if (!MBB->back().isBarrier()) {
756 report("MBB exits via conditional branch/branch but doesn't end with a "
757 "barrier instruction!", MBB);
758 } else if (!MBB->back().isTerminator()) {
759 report("MBB exits via conditional branch/branch but the branch "
760 "isn't a terminator instruction!", MBB);
761 }
762 if (Cond.empty()) {
763 report("MBB exits via conditional branch/branch but there's no "
764 "condition!", MBB);
765 }
766 } else {
767 report("analyzeBranch returned invalid data!", MBB);
768 }
769
770 // Now check that the successors match up with the answers reported by
771 // analyzeBranch.
772 if (TBB && !MBB->isSuccessor(TBB))
773 report("MBB exits via jump or conditional branch, but its target isn't a "
774 "CFG successor!",
775 MBB);
776 if (FBB && !MBB->isSuccessor(FBB))
777 report("MBB exits via conditional branch, but its target isn't a CFG "
778 "successor!",
779 MBB);
780
781 // There might be a fallthrough to the next block if there's either no
782 // unconditional true branch, or if there's a condition, and one of the
783 // branches is missing.
784 bool Fallthrough = !TBB || (!Cond.empty() && !FBB);
785
786 // A conditional fallthrough must be an actual CFG successor, not
787 // unreachable. (Conversely, an unconditional fallthrough might not really
788 // be a successor, because the block might end in unreachable.)
789 if (!Cond.empty() && !FBB) {
791 if (MBBI == MF->end()) {
792 report("MBB conditionally falls through out of function!", MBB);
793 } else if (!MBB->isSuccessor(&*MBBI))
794 report("MBB exits via conditional branch/fall-through but the CFG "
795 "successors don't match the actual successors!",
796 MBB);
797 }
798
799 // Verify that there aren't any extra un-accounted-for successors.
800 for (const MachineBasicBlock *SuccMBB : MBB->successors()) {
801 // If this successor is one of the branch targets, it's okay.
802 if (SuccMBB == TBB || SuccMBB == FBB)
803 continue;
804 // If we might have a fallthrough, and the successor is the fallthrough
805 // block, that's also ok.
806 if (Fallthrough && SuccMBB == MBB->getNextNode())
807 continue;
808 // Also accept successors which are for exception-handling or might be
809 // inlineasm_br targets.
810 if (SuccMBB->isEHPad() || SuccMBB->isInlineAsmBrIndirectTarget())
811 continue;
812 report("MBB has unexpected successors which are not branch targets, "
813 "fallthrough, EHPads, or inlineasm_br targets.",
814 MBB);
815 }
816 }
817
818 regsLive.clear();
819 if (MRI->tracksLiveness()) {
820 for (const auto &LI : MBB->liveins()) {
821 if (!Register::isPhysicalRegister(LI.PhysReg)) {
822 report("MBB live-in list contains non-physical register", MBB);
823 continue;
824 }
825 for (const MCPhysReg &SubReg : TRI->subregs_inclusive(LI.PhysReg))
826 regsLive.insert(SubReg);
827 }
828 }
829
830 const MachineFrameInfo &MFI = MF->getFrameInfo();
831 BitVector PR = MFI.getPristineRegs(*MF);
832 for (unsigned I : PR.set_bits()) {
833 for (const MCPhysReg &SubReg : TRI->subregs_inclusive(I))
834 regsLive.insert(SubReg);
835 }
836
837 regsKilled.clear();
838 regsDefined.clear();
839
840 if (Indexes)
841 lastIndex = Indexes->getMBBStartIdx(MBB);
842}
843
844// This function gets called for all bundle headers, including normal
845// stand-alone unbundled instructions.
846void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
847 if (Indexes && Indexes->hasIndex(*MI)) {
848 SlotIndex idx = Indexes->getInstructionIndex(*MI);
849 if (!(idx > lastIndex)) {
850 report("Instruction index out of order", MI);
851 errs() << "Last instruction was at " << lastIndex << '\n';
852 }
853 lastIndex = idx;
854 }
855
856 // Ensure non-terminators don't follow terminators.
857 if (MI->isTerminator()) {
858 if (!FirstTerminator)
859 FirstTerminator = MI;
860 } else if (FirstTerminator) {
861 // For GlobalISel, G_INVOKE_REGION_START is a terminator that we allow to
862 // precede non-terminators.
863 if (FirstTerminator->getOpcode() != TargetOpcode::G_INVOKE_REGION_START) {
864 report("Non-terminator instruction after the first terminator", MI);
865 errs() << "First terminator was:\t" << *FirstTerminator;
866 }
867 }
868}
869
870// The operands on an INLINEASM instruction must follow a template.
871// Verify that the flag operands make sense.
872void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) {
873 // The first two operands on INLINEASM are the asm string and global flags.
874 if (MI->getNumOperands() < 2) {
875 report("Too few operands on inline asm", MI);
876 return;
877 }
878 if (!MI->getOperand(0).isSymbol())
879 report("Asm string must be an external symbol", MI);
880 if (!MI->getOperand(1).isImm())
881 report("Asm flags must be an immediate", MI);
882 // Allowed flags are Extra_HasSideEffects = 1, Extra_IsAlignStack = 2,
883 // Extra_AsmDialect = 4, Extra_MayLoad = 8, and Extra_MayStore = 16,
884 // and Extra_IsConvergent = 32.
885 if (!isUInt<6>(MI->getOperand(1).getImm()))
886 report("Unknown asm flags", &MI->getOperand(1), 1);
887
888 static_assert(InlineAsm::MIOp_FirstOperand == 2, "Asm format changed");
889
890 unsigned OpNo = InlineAsm::MIOp_FirstOperand;
891 unsigned NumOps;
892 for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
893 const MachineOperand &MO = MI->getOperand(OpNo);
894 // There may be implicit ops after the fixed operands.
895 if (!MO.isImm())
896 break;
897 const InlineAsm::Flag F(MO.getImm());
898 NumOps = 1 + F.getNumOperandRegisters();
899 }
900
901 if (OpNo > MI->getNumOperands())
902 report("Missing operands in last group", MI);
903
904 // An optional MDNode follows the groups.
905 if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata())
906 ++OpNo;
907
908 // All trailing operands must be implicit registers.
909 for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) {
910 const MachineOperand &MO = MI->getOperand(OpNo);
911 if (!MO.isReg() || !MO.isImplicit())
912 report("Expected implicit register after groups", &MO, OpNo);
913 }
914
915 if (MI->getOpcode() == TargetOpcode::INLINEASM_BR) {
916 const MachineBasicBlock *MBB = MI->getParent();
917
918 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = MI->getNumOperands();
919 i != e; ++i) {
920 const MachineOperand &MO = MI->getOperand(i);
921
922 if (!MO.isMBB())
923 continue;
924
925 // Check the successor & predecessor lists look ok, assume they are
926 // not. Find the indirect target without going through the successors.
927 const MachineBasicBlock *IndirectTargetMBB = MO.getMBB();
928 if (!IndirectTargetMBB) {
929 report("INLINEASM_BR indirect target does not exist", &MO, i);
930 break;
931 }
932
933 if (!MBB->isSuccessor(IndirectTargetMBB))
934 report("INLINEASM_BR indirect target missing from successor list", &MO,
935 i);
936
937 if (!IndirectTargetMBB->isPredecessor(MBB))
938 report("INLINEASM_BR indirect target predecessor list missing parent",
939 &MO, i);
940 }
941 }
942}
943
944bool MachineVerifier::verifyAllRegOpsScalar(const MachineInstr &MI,
945 const MachineRegisterInfo &MRI) {
946 if (none_of(MI.explicit_operands(), [&MRI](const MachineOperand &Op) {
947 if (!Op.isReg())
948 return false;
949 const auto Reg = Op.getReg();
950 if (Reg.isPhysical())
951 return false;
952 return !MRI.getType(Reg).isScalar();
953 }))
954 return true;
955 report("All register operands must have scalar types", &MI);
956 return false;
957}
958
959/// Check that types are consistent when two operands need to have the same
960/// number of vector elements.
961/// \return true if the types are valid.
962bool MachineVerifier::verifyVectorElementMatch(LLT Ty0, LLT Ty1,
963 const MachineInstr *MI) {
964 if (Ty0.isVector() != Ty1.isVector()) {
965 report("operand types must be all-vector or all-scalar", MI);
966 // Generally we try to report as many issues as possible at once, but in
967 // this case it's not clear what should we be comparing the size of the
968 // scalar with: the size of the whole vector or its lane. Instead of
969 // making an arbitrary choice and emitting not so helpful message, let's
970 // avoid the extra noise and stop here.
971 return false;
972 }
973
974 if (Ty0.isVector() && Ty0.getElementCount() != Ty1.getElementCount()) {
975 report("operand types must preserve number of vector elements", MI);
976 return false;
977 }
978
979 return true;
980}
981
982bool MachineVerifier::verifyGIntrinsicSideEffects(const MachineInstr *MI) {
983 auto Opcode = MI->getOpcode();
984 bool NoSideEffects = Opcode == TargetOpcode::G_INTRINSIC ||
985 Opcode == TargetOpcode::G_INTRINSIC_CONVERGENT;
986 unsigned IntrID = cast<GIntrinsic>(MI)->getIntrinsicID();
987 if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
989 MF->getFunction().getContext(), static_cast<Intrinsic::ID>(IntrID));
990 bool DeclHasSideEffects = !Attrs.getMemoryEffects().doesNotAccessMemory();
991 if (NoSideEffects && DeclHasSideEffects) {
992 report(Twine(TII->getName(Opcode),
993 " used with intrinsic that accesses memory"),
994 MI);
995 return false;
996 }
997 if (!NoSideEffects && !DeclHasSideEffects) {
998 report(Twine(TII->getName(Opcode), " used with readnone intrinsic"), MI);
999 return false;
1000 }
1001 }
1002
1003 return true;
1004}
1005
1006bool MachineVerifier::verifyGIntrinsicConvergence(const MachineInstr *MI) {
1007 auto Opcode = MI->getOpcode();
1008 bool NotConvergent = Opcode == TargetOpcode::G_INTRINSIC ||
1009 Opcode == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS;
1010 unsigned IntrID = cast<GIntrinsic>(MI)->getIntrinsicID();
1011 if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
1013 MF->getFunction().getContext(), static_cast<Intrinsic::ID>(IntrID));
1014 bool DeclIsConvergent = Attrs.hasFnAttr(Attribute::Convergent);
1015 if (NotConvergent && DeclIsConvergent) {
1016 report(Twine(TII->getName(Opcode), " used with a convergent intrinsic"),
1017 MI);
1018 return false;
1019 }
1020 if (!NotConvergent && !DeclIsConvergent) {
1021 report(
1022 Twine(TII->getName(Opcode), " used with a non-convergent intrinsic"),
1023 MI);
1024 return false;
1025 }
1026 }
1027
1028 return true;
1029}
1030
1031void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
1032 if (isFunctionSelected)
1033 report("Unexpected generic instruction in a Selected function", MI);
1034
1035 const MCInstrDesc &MCID = MI->getDesc();
1036 unsigned NumOps = MI->getNumOperands();
1037
1038 // Branches must reference a basic block if they are not indirect
1039 if (MI->isBranch() && !MI->isIndirectBranch()) {
1040 bool HasMBB = false;
1041 for (const MachineOperand &Op : MI->operands()) {
1042 if (Op.isMBB()) {
1043 HasMBB = true;
1044 break;
1045 }
1046 }
1047
1048 if (!HasMBB) {
1049 report("Branch instruction is missing a basic block operand or "
1050 "isIndirectBranch property",
1051 MI);
1052 }
1053 }
1054
1055 // Check types.
1057 for (unsigned I = 0, E = std::min(MCID.getNumOperands(), NumOps);
1058 I != E; ++I) {
1059 if (!MCID.operands()[I].isGenericType())
1060 continue;
1061 // Generic instructions specify type equality constraints between some of
1062 // their operands. Make sure these are consistent.
1063 size_t TypeIdx = MCID.operands()[I].getGenericTypeIndex();
1064 Types.resize(std::max(TypeIdx + 1, Types.size()));
1065
1066 const MachineOperand *MO = &MI->getOperand(I);
1067 if (!MO->isReg()) {
1068 report("generic instruction must use register operands", MI);
1069 continue;
1070 }
1071
1072 LLT OpTy = MRI->getType(MO->getReg());
1073 // Don't report a type mismatch if there is no actual mismatch, only a
1074 // type missing, to reduce noise:
1075 if (OpTy.isValid()) {
1076 // Only the first valid type for a type index will be printed: don't
1077 // overwrite it later so it's always clear which type was expected:
1078 if (!Types[TypeIdx].isValid())
1079 Types[TypeIdx] = OpTy;
1080 else if (Types[TypeIdx] != OpTy)
1081 report("Type mismatch in generic instruction", MO, I, OpTy);
1082 } else {
1083 // Generic instructions must have types attached to their operands.
1084 report("Generic instruction is missing a virtual register type", MO, I);
1085 }
1086 }
1087
1088 // Generic opcodes must not have physical register operands.
1089 for (unsigned I = 0; I < MI->getNumOperands(); ++I) {
1090 const MachineOperand *MO = &MI->getOperand(I);
1091 if (MO->isReg() && MO->getReg().isPhysical())
1092 report("Generic instruction cannot have physical register", MO, I);
1093 }
1094
1095 // Avoid out of bounds in checks below. This was already reported earlier.
1096 if (MI->getNumOperands() < MCID.getNumOperands())
1097 return;
1098
1100 if (!TII->verifyInstruction(*MI, ErrorInfo))
1101 report(ErrorInfo.data(), MI);
1102
1103 // Verify properties of various specific instruction types
1104 unsigned Opc = MI->getOpcode();
1105 switch (Opc) {
1106 case TargetOpcode::G_ASSERT_SEXT:
1107 case TargetOpcode::G_ASSERT_ZEXT: {
1108 std::string OpcName =
1109 Opc == TargetOpcode::G_ASSERT_ZEXT ? "G_ASSERT_ZEXT" : "G_ASSERT_SEXT";
1110 if (!MI->getOperand(2).isImm()) {
1111 report(Twine(OpcName, " expects an immediate operand #2"), MI);
1112 break;
1113 }
1114
1115 Register Dst = MI->getOperand(0).getReg();
1116 Register Src = MI->getOperand(1).getReg();
1117 LLT SrcTy = MRI->getType(Src);
1118 int64_t Imm = MI->getOperand(2).getImm();
1119 if (Imm <= 0) {
1120 report(Twine(OpcName, " size must be >= 1"), MI);
1121 break;
1122 }
1123
1124 if (Imm >= SrcTy.getScalarSizeInBits()) {
1125 report(Twine(OpcName, " size must be less than source bit width"), MI);
1126 break;
1127 }
1128
1129 const RegisterBank *SrcRB = RBI->getRegBank(Src, *MRI, *TRI);
1130 const RegisterBank *DstRB = RBI->getRegBank(Dst, *MRI, *TRI);
1131
1132 // Allow only the source bank to be set.
1133 if ((SrcRB && DstRB && SrcRB != DstRB) || (DstRB && !SrcRB)) {
1134 report(Twine(OpcName, " cannot change register bank"), MI);
1135 break;
1136 }
1137
1138 // Don't allow a class change. Do allow member class->regbank.
1139 const TargetRegisterClass *DstRC = MRI->getRegClassOrNull(Dst);
1140 if (DstRC && DstRC != MRI->getRegClassOrNull(Src)) {
1141 report(
1142 Twine(OpcName, " source and destination register classes must match"),
1143 MI);
1144 break;
1145 }
1146
1147 break;
1148 }
1149
1150 case TargetOpcode::G_CONSTANT:
1151 case TargetOpcode::G_FCONSTANT: {
1152 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1153 if (DstTy.isVector())
1154 report("Instruction cannot use a vector result type", MI);
1155
1156 if (MI->getOpcode() == TargetOpcode::G_CONSTANT) {
1157 if (!MI->getOperand(1).isCImm()) {
1158 report("G_CONSTANT operand must be cimm", MI);
1159 break;
1160 }
1161
1162 const ConstantInt *CI = MI->getOperand(1).getCImm();
1163 if (CI->getBitWidth() != DstTy.getSizeInBits())
1164 report("inconsistent constant size", MI);
1165 } else {
1166 if (!MI->getOperand(1).isFPImm()) {
1167 report("G_FCONSTANT operand must be fpimm", MI);
1168 break;
1169 }
1170 const ConstantFP *CF = MI->getOperand(1).getFPImm();
1171
1173 DstTy.getSizeInBits()) {
1174 report("inconsistent constant size", MI);
1175 }
1176 }
1177
1178 break;
1179 }
1180 case TargetOpcode::G_LOAD:
1181 case TargetOpcode::G_STORE:
1182 case TargetOpcode::G_ZEXTLOAD:
1183 case TargetOpcode::G_SEXTLOAD: {
1184 LLT ValTy = MRI->getType(MI->getOperand(0).getReg());
1185 LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
1186 if (!PtrTy.isPointer())
1187 report("Generic memory instruction must access a pointer", MI);
1188
1189 // Generic loads and stores must have a single MachineMemOperand
1190 // describing that access.
1191 if (!MI->hasOneMemOperand()) {
1192 report("Generic instruction accessing memory must have one mem operand",
1193 MI);
1194 } else {
1195 const MachineMemOperand &MMO = **MI->memoperands_begin();
1196 if (MI->getOpcode() == TargetOpcode::G_ZEXTLOAD ||
1197 MI->getOpcode() == TargetOpcode::G_SEXTLOAD) {
1198 if (MMO.getSizeInBits() >= ValTy.getSizeInBits())
1199 report("Generic extload must have a narrower memory type", MI);
1200 } else if (MI->getOpcode() == TargetOpcode::G_LOAD) {
1201 if (MMO.getSize() > ValTy.getSizeInBytes())
1202 report("load memory size cannot exceed result size", MI);
1203 } else if (MI->getOpcode() == TargetOpcode::G_STORE) {
1204 if (ValTy.getSizeInBytes() < MMO.getSize())
1205 report("store memory size cannot exceed value size", MI);
1206 }
1207
1208 const AtomicOrdering Order = MMO.getSuccessOrdering();
1209 if (Opc == TargetOpcode::G_STORE) {
1210 if (Order == AtomicOrdering::Acquire ||
1212 report("atomic store cannot use acquire ordering", MI);
1213
1214 } else {
1215 if (Order == AtomicOrdering::Release ||
1217 report("atomic load cannot use release ordering", MI);
1218 }
1219 }
1220
1221 break;
1222 }
1223 case TargetOpcode::G_PHI: {
1224 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1225 if (!DstTy.isValid() || !all_of(drop_begin(MI->operands()),
1226 [this, &DstTy](const MachineOperand &MO) {
1227 if (!MO.isReg())
1228 return true;
1229 LLT Ty = MRI->getType(MO.getReg());
1230 if (!Ty.isValid() || (Ty != DstTy))
1231 return false;
1232 return true;
1233 }))
1234 report("Generic Instruction G_PHI has operands with incompatible/missing "
1235 "types",
1236 MI);
1237 break;
1238 }
1239 case TargetOpcode::G_BITCAST: {
1240 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1241 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1242 if (!DstTy.isValid() || !SrcTy.isValid())
1243 break;
1244
1245 if (SrcTy.isPointer() != DstTy.isPointer())
1246 report("bitcast cannot convert between pointers and other types", MI);
1247
1248 if (SrcTy.getSizeInBits() != DstTy.getSizeInBits())
1249 report("bitcast sizes must match", MI);
1250
1251 if (SrcTy == DstTy)
1252 report("bitcast must change the type", MI);
1253
1254 break;
1255 }
1256 case TargetOpcode::G_INTTOPTR:
1257 case TargetOpcode::G_PTRTOINT:
1258 case TargetOpcode::G_ADDRSPACE_CAST: {
1259 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1260 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1261 if (!DstTy.isValid() || !SrcTy.isValid())
1262 break;
1263
1264 verifyVectorElementMatch(DstTy, SrcTy, MI);
1265
1266 DstTy = DstTy.getScalarType();
1267 SrcTy = SrcTy.getScalarType();
1268
1269 if (MI->getOpcode() == TargetOpcode::G_INTTOPTR) {
1270 if (!DstTy.isPointer())
1271 report("inttoptr result type must be a pointer", MI);
1272 if (SrcTy.isPointer())
1273 report("inttoptr source type must not be a pointer", MI);
1274 } else if (MI->getOpcode() == TargetOpcode::G_PTRTOINT) {
1275 if (!SrcTy.isPointer())
1276 report("ptrtoint source type must be a pointer", MI);
1277 if (DstTy.isPointer())
1278 report("ptrtoint result type must not be a pointer", MI);
1279 } else {
1280 assert(MI->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST);
1281 if (!SrcTy.isPointer() || !DstTy.isPointer())
1282 report("addrspacecast types must be pointers", MI);
1283 else {
1284 if (SrcTy.getAddressSpace() == DstTy.getAddressSpace())
1285 report("addrspacecast must convert different address spaces", MI);
1286 }
1287 }
1288
1289 break;
1290 }
1291 case TargetOpcode::G_PTR_ADD: {
1292 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1293 LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
1294 LLT OffsetTy = MRI->getType(MI->getOperand(2).getReg());
1295 if (!DstTy.isValid() || !PtrTy.isValid() || !OffsetTy.isValid())
1296 break;
1297
1298 if (!PtrTy.isPointerOrPointerVector())
1299 report("gep first operand must be a pointer", MI);
1300
1301 if (OffsetTy.isPointerOrPointerVector())
1302 report("gep offset operand must not be a pointer", MI);
1303
1304 if (PtrTy.isPointerOrPointerVector()) {
1305 const DataLayout &DL = MF->getDataLayout();
1306 unsigned AS = PtrTy.getAddressSpace();
1307 unsigned IndexSizeInBits = DL.getIndexSize(AS) * 8;
1308 if (OffsetTy.getScalarSizeInBits() != IndexSizeInBits) {
1309 report("gep offset operand must match index size for address space",
1310 MI);
1311 }
1312 }
1313
1314 // TODO: Is the offset allowed to be a scalar with a vector?
1315 break;
1316 }
1317 case TargetOpcode::G_PTRMASK: {
1318 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1319 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1320 LLT MaskTy = MRI->getType(MI->getOperand(2).getReg());
1321 if (!DstTy.isValid() || !SrcTy.isValid() || !MaskTy.isValid())
1322 break;
1323
1324 if (!DstTy.isPointerOrPointerVector())
1325 report("ptrmask result type must be a pointer", MI);
1326
1327 if (!MaskTy.getScalarType().isScalar())
1328 report("ptrmask mask type must be an integer", MI);
1329
1330 verifyVectorElementMatch(DstTy, MaskTy, MI);
1331 break;
1332 }
1333 case TargetOpcode::G_SEXT:
1334 case TargetOpcode::G_ZEXT:
1335 case TargetOpcode::G_ANYEXT:
1336 case TargetOpcode::G_TRUNC:
1337 case TargetOpcode::G_FPEXT:
1338 case TargetOpcode::G_FPTRUNC: {
1339 // Number of operands and presense of types is already checked (and
1340 // reported in case of any issues), so no need to report them again. As
1341 // we're trying to report as many issues as possible at once, however, the
1342 // instructions aren't guaranteed to have the right number of operands or
1343 // types attached to them at this point
1344 assert(MCID.getNumOperands() == 2 && "Expected 2 operands G_*{EXT,TRUNC}");
1345 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1346 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1347 if (!DstTy.isValid() || !SrcTy.isValid())
1348 break;
1349
1351 report("Generic extend/truncate can not operate on pointers", MI);
1352
1353 verifyVectorElementMatch(DstTy, SrcTy, MI);
1354
1355 unsigned DstSize = DstTy.getScalarSizeInBits();
1356 unsigned SrcSize = SrcTy.getScalarSizeInBits();
1357 switch (MI->getOpcode()) {
1358 default:
1359 if (DstSize <= SrcSize)
1360 report("Generic extend has destination type no larger than source", MI);
1361 break;
1362 case TargetOpcode::G_TRUNC:
1363 case TargetOpcode::G_FPTRUNC:
1364 if (DstSize >= SrcSize)
1365 report("Generic truncate has destination type no smaller than source",
1366 MI);
1367 break;
1368 }
1369 break;
1370 }
1371 case TargetOpcode::G_SELECT: {
1372 LLT SelTy = MRI->getType(MI->getOperand(0).getReg());
1373 LLT CondTy = MRI->getType(MI->getOperand(1).getReg());
1374 if (!SelTy.isValid() || !CondTy.isValid())
1375 break;
1376
1377 // Scalar condition select on a vector is valid.
1378 if (CondTy.isVector())
1379 verifyVectorElementMatch(SelTy, CondTy, MI);
1380 break;
1381 }
1382 case TargetOpcode::G_MERGE_VALUES: {
1383 // G_MERGE_VALUES should only be used to merge scalars into a larger scalar,
1384 // e.g. s2N = MERGE sN, sN
1385 // Merging multiple scalars into a vector is not allowed, should use
1386 // G_BUILD_VECTOR for that.
1387 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1388 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1389 if (DstTy.isVector() || SrcTy.isVector())
1390 report("G_MERGE_VALUES cannot operate on vectors", MI);
1391
1392 const unsigned NumOps = MI->getNumOperands();
1393 if (DstTy.getSizeInBits() != SrcTy.getSizeInBits() * (NumOps - 1))
1394 report("G_MERGE_VALUES result size is inconsistent", MI);
1395
1396 for (unsigned I = 2; I != NumOps; ++I) {
1397 if (MRI->getType(MI->getOperand(I).getReg()) != SrcTy)
1398 report("G_MERGE_VALUES source types do not match", MI);
1399 }
1400
1401 break;
1402 }
1403 case TargetOpcode::G_UNMERGE_VALUES: {
1404 unsigned NumDsts = MI->getNumOperands() - 1;
1405 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1406 for (unsigned i = 1; i < NumDsts; ++i) {
1407 if (MRI->getType(MI->getOperand(i).getReg()) != DstTy) {
1408 report("G_UNMERGE_VALUES destination types do not match", MI);
1409 break;
1410 }
1411 }
1412
1413 LLT SrcTy = MRI->getType(MI->getOperand(NumDsts).getReg());
1414 if (DstTy.isVector()) {
1415 // This case is the converse of G_CONCAT_VECTORS.
1416 if (!SrcTy.isVector() || SrcTy.getScalarType() != DstTy.getScalarType() ||
1417 SrcTy.isScalableVector() != DstTy.isScalableVector() ||
1418 SrcTy.getSizeInBits() != NumDsts * DstTy.getSizeInBits())
1419 report("G_UNMERGE_VALUES source operand does not match vector "
1420 "destination operands",
1421 MI);
1422 } else if (SrcTy.isVector()) {
1423 // This case is the converse of G_BUILD_VECTOR, but relaxed to allow
1424 // mismatched types as long as the total size matches:
1425 // %0:_(s64), %1:_(s64) = G_UNMERGE_VALUES %2:_(<4 x s32>)
1426 if (SrcTy.getSizeInBits() != NumDsts * DstTy.getSizeInBits())
1427 report("G_UNMERGE_VALUES vector source operand does not match scalar "
1428 "destination operands",
1429 MI);
1430 } else {
1431 // This case is the converse of G_MERGE_VALUES.
1432 if (SrcTy.getSizeInBits() != NumDsts * DstTy.getSizeInBits()) {
1433 report("G_UNMERGE_VALUES scalar source operand does not match scalar "
1434 "destination operands",
1435 MI);
1436 }
1437 }
1438 break;
1439 }
1440 case TargetOpcode::G_BUILD_VECTOR: {
1441 // Source types must be scalars, dest type a vector. Total size of scalars
1442 // must match the dest vector size.
1443 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1444 LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1445 if (!DstTy.isVector() || SrcEltTy.isVector()) {
1446 report("G_BUILD_VECTOR must produce a vector from scalar operands", MI);
1447 break;
1448 }
1449
1450 if (DstTy.getElementType() != SrcEltTy)
1451 report("G_BUILD_VECTOR result element type must match source type", MI);
1452
1453 if (DstTy.getNumElements() != MI->getNumOperands() - 1)
1454 report("G_BUILD_VECTOR must have an operand for each elemement", MI);
1455
1456 for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
1457 if (MRI->getType(MI->getOperand(1).getReg()) != MRI->getType(MO.getReg()))
1458 report("G_BUILD_VECTOR source operand types are not homogeneous", MI);
1459
1460 break;
1461 }
1462 case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1463 // Source types must be scalars, dest type a vector. Scalar types must be
1464 // larger than the dest vector elt type, as this is a truncating operation.
1465 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1466 LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1467 if (!DstTy.isVector() || SrcEltTy.isVector())
1468 report("G_BUILD_VECTOR_TRUNC must produce a vector from scalar operands",
1469 MI);
1470 for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
1471 if (MRI->getType(MI->getOperand(1).getReg()) != MRI->getType(MO.getReg()))
1472 report("G_BUILD_VECTOR_TRUNC source operand types are not homogeneous",
1473 MI);
1474 if (SrcEltTy.getSizeInBits() <= DstTy.getElementType().getSizeInBits())
1475 report("G_BUILD_VECTOR_TRUNC source operand types are not larger than "
1476 "dest elt type",
1477 MI);
1478 break;
1479 }
1480 case TargetOpcode::G_CONCAT_VECTORS: {
1481 // Source types should be vectors, and total size should match the dest
1482 // vector size.
1483 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1484 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1485 if (!DstTy.isVector() || !SrcTy.isVector())
1486 report("G_CONCAT_VECTOR requires vector source and destination operands",
1487 MI);
1488
1489 if (MI->getNumOperands() < 3)
1490 report("G_CONCAT_VECTOR requires at least 2 source operands", MI);
1491
1492 for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
1493 if (MRI->getType(MI->getOperand(1).getReg()) != MRI->getType(MO.getReg()))
1494 report("G_CONCAT_VECTOR source operand types are not homogeneous", MI);
1495 if (DstTy.getElementCount() !=
1496 SrcTy.getElementCount() * (MI->getNumOperands() - 1))
1497 report("G_CONCAT_VECTOR num dest and source elements should match", MI);
1498 break;
1499 }
1500 case TargetOpcode::G_ICMP:
1501 case TargetOpcode::G_FCMP: {
1502 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1503 LLT SrcTy = MRI->getType(MI->getOperand(2).getReg());
1504
1505 if ((DstTy.isVector() != SrcTy.isVector()) ||
1506 (DstTy.isVector() && DstTy.getNumElements() != SrcTy.getNumElements()))
1507 report("Generic vector icmp/fcmp must preserve number of lanes", MI);
1508
1509 break;
1510 }
1511 case TargetOpcode::G_EXTRACT: {
1512 const MachineOperand &SrcOp = MI->getOperand(1);
1513 if (!SrcOp.isReg()) {
1514 report("extract source must be a register", MI);
1515 break;
1516 }
1517
1518 const MachineOperand &OffsetOp = MI->getOperand(2);
1519 if (!OffsetOp.isImm()) {
1520 report("extract offset must be a constant", MI);
1521 break;
1522 }
1523
1524 unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1525 unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
1526 if (SrcSize == DstSize)
1527 report("extract source must be larger than result", MI);
1528
1529 if (DstSize + OffsetOp.getImm() > SrcSize)
1530 report("extract reads past end of register", MI);
1531 break;
1532 }
1533 case TargetOpcode::G_INSERT: {
1534 const MachineOperand &SrcOp = MI->getOperand(2);
1535 if (!SrcOp.isReg()) {
1536 report("insert source must be a register", MI);
1537 break;
1538 }
1539
1540 const MachineOperand &OffsetOp = MI->getOperand(3);
1541 if (!OffsetOp.isImm()) {
1542 report("insert offset must be a constant", MI);
1543 break;
1544 }
1545
1546 unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1547 unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
1548
1549 if (DstSize <= SrcSize)
1550 report("inserted size must be smaller than total register", MI);
1551
1552 if (SrcSize + OffsetOp.getImm() > DstSize)
1553 report("insert writes past end of register", MI);
1554
1555 break;
1556 }
1557 case TargetOpcode::G_JUMP_TABLE: {
1558 if (!MI->getOperand(1).isJTI())
1559 report("G_JUMP_TABLE source operand must be a jump table index", MI);
1560 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1561 if (!DstTy.isPointer())
1562 report("G_JUMP_TABLE dest operand must have a pointer type", MI);
1563 break;
1564 }
1565 case TargetOpcode::G_BRJT: {
1566 if (!MRI->getType(MI->getOperand(0).getReg()).isPointer())
1567 report("G_BRJT src operand 0 must be a pointer type", MI);
1568
1569 if (!MI->getOperand(1).isJTI())
1570 report("G_BRJT src operand 1 must be a jump table index", MI);
1571
1572 const auto &IdxOp = MI->getOperand(2);
1573 if (!IdxOp.isReg() || MRI->getType(IdxOp.getReg()).isPointer())
1574 report("G_BRJT src operand 2 must be a scalar reg type", MI);
1575 break;
1576 }
1577 case TargetOpcode::G_INTRINSIC:
1578 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
1579 case TargetOpcode::G_INTRINSIC_CONVERGENT:
1580 case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS: {
1581 // TODO: Should verify number of def and use operands, but the current
1582 // interface requires passing in IR types for mangling.
1583 const MachineOperand &IntrIDOp = MI->getOperand(MI->getNumExplicitDefs());
1584 if (!IntrIDOp.isIntrinsicID()) {
1585 report("G_INTRINSIC first src operand must be an intrinsic ID", MI);
1586 break;
1587 }
1588
1589 if (!verifyGIntrinsicSideEffects(MI))
1590 break;
1591 if (!verifyGIntrinsicConvergence(MI))
1592 break;
1593
1594 break;
1595 }
1596 case TargetOpcode::G_SEXT_INREG: {
1597 if (!MI->getOperand(2).isImm()) {
1598 report("G_SEXT_INREG expects an immediate operand #2", MI);
1599 break;
1600 }
1601
1602 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1603 int64_t Imm = MI->getOperand(2).getImm();
1604 if (Imm <= 0)
1605 report("G_SEXT_INREG size must be >= 1", MI);
1606 if (Imm >= SrcTy.getScalarSizeInBits())
1607 report("G_SEXT_INREG size must be less than source bit width", MI);
1608 break;
1609 }
1610 case TargetOpcode::G_BSWAP: {
1611 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1612 if (DstTy.getScalarSizeInBits() % 16 != 0)
1613 report("G_BSWAP size must be a multiple of 16 bits", MI);
1614 break;
1615 }
1616 case TargetOpcode::G_VSCALE: {
1617 if (!MI->getOperand(1).isCImm()) {
1618 report("G_VSCALE operand must be cimm", MI);
1619 break;
1620 }
1621 if (MI->getOperand(1).getCImm()->isZero()) {
1622 report("G_VSCALE immediate cannot be zero", MI);
1623 break;
1624 }
1625 break;
1626 }
1627 case TargetOpcode::G_INSERT_SUBVECTOR: {
1628 const MachineOperand &Src0Op = MI->getOperand(1);
1629 if (!Src0Op.isReg()) {
1630 report("G_INSERT_SUBVECTOR first source must be a register", MI);
1631 break;
1632 }
1633
1634 const MachineOperand &Src1Op = MI->getOperand(2);
1635 if (!Src1Op.isReg()) {
1636 report("G_INSERT_SUBVECTOR second source must be a register", MI);
1637 break;
1638 }
1639
1640 const MachineOperand &IndexOp = MI->getOperand(3);
1641 if (!IndexOp.isImm()) {
1642 report("G_INSERT_SUBVECTOR index must be an immediate", MI);
1643 break;
1644 }
1645
1646 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1647 LLT Src0Ty = MRI->getType(Src0Op.getReg());
1648 LLT Src1Ty = MRI->getType(Src1Op.getReg());
1649
1650 if (!DstTy.isVector()) {
1651 report("Destination type must be a vector", MI);
1652 break;
1653 }
1654
1655 if (!Src0Ty.isVector()) {
1656 report("First source must be a vector", MI);
1657 break;
1658 }
1659
1660 if (!Src1Ty.isVector()) {
1661 report("Second source must be a vector", MI);
1662 break;
1663 }
1664
1665 if (DstTy != Src0Ty) {
1666 report("Destination type must match the first source vector type", MI);
1667 break;
1668 }
1669
1670 if (Src0Ty.getElementType() != Src1Ty.getElementType()) {
1671 report("Element type of source vectors must be the same", MI);
1672 break;
1673 }
1674
1675 if (IndexOp.getImm() != 0 &&
1676 Src1Ty.getElementCount().getKnownMinValue() % IndexOp.getImm() != 0) {
1677 report("Index must be a multiple of the second source vector's "
1678 "minimum vector length",
1679 MI);
1680 break;
1681 }
1682 break;
1683 }
1684 case TargetOpcode::G_EXTRACT_SUBVECTOR: {
1685 const MachineOperand &SrcOp = MI->getOperand(1);
1686 if (!SrcOp.isReg()) {
1687 report("G_EXTRACT_SUBVECTOR first source must be a register", MI);
1688 break;
1689 }
1690
1691 const MachineOperand &IndexOp = MI->getOperand(2);
1692 if (!IndexOp.isImm()) {
1693 report("G_EXTRACT_SUBVECTOR index must be an immediate", MI);
1694 break;
1695 }
1696
1697 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1698 LLT SrcTy = MRI->getType(SrcOp.getReg());
1699
1700 if (!DstTy.isVector()) {
1701 report("Destination type must be a vector", MI);
1702 break;
1703 }
1704
1705 if (!SrcTy.isVector()) {
1706 report("First source must be a vector", MI);
1707 break;
1708 }
1709
1710 if (DstTy.getElementType() != SrcTy.getElementType()) {
1711 report("Element type of vectors must be the same", MI);
1712 break;
1713 }
1714
1715 if (IndexOp.getImm() != 0 &&
1716 SrcTy.getElementCount().getKnownMinValue() % IndexOp.getImm() != 0) {
1717 report("Index must be a multiple of the source vector's minimum vector "
1718 "length",
1719 MI);
1720 break;
1721 }
1722
1723 break;
1724 }
1725 case TargetOpcode::G_SHUFFLE_VECTOR: {
1726 const MachineOperand &MaskOp = MI->getOperand(3);
1727 if (!MaskOp.isShuffleMask()) {
1728 report("Incorrect mask operand type for G_SHUFFLE_VECTOR", MI);
1729 break;
1730 }
1731
1732 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1733 LLT Src0Ty = MRI->getType(MI->getOperand(1).getReg());
1734 LLT Src1Ty = MRI->getType(MI->getOperand(2).getReg());
1735
1736 if (Src0Ty != Src1Ty)
1737 report("Source operands must be the same type", MI);
1738
1739 if (Src0Ty.getScalarType() != DstTy.getScalarType())
1740 report("G_SHUFFLE_VECTOR cannot change element type", MI);
1741
1742 // Don't check that all operands are vector because scalars are used in
1743 // place of 1 element vectors.
1744 int SrcNumElts = Src0Ty.isVector() ? Src0Ty.getNumElements() : 1;
1745 int DstNumElts = DstTy.isVector() ? DstTy.getNumElements() : 1;
1746
1747 ArrayRef<int> MaskIdxes = MaskOp.getShuffleMask();
1748
1749 if (static_cast<int>(MaskIdxes.size()) != DstNumElts)
1750 report("Wrong result type for shufflemask", MI);
1751
1752 for (int Idx : MaskIdxes) {
1753 if (Idx < 0)
1754 continue;
1755
1756 if (Idx >= 2 * SrcNumElts)
1757 report("Out of bounds shuffle index", MI);
1758 }
1759
1760 break;
1761 }
1762
1763 case TargetOpcode::G_SPLAT_VECTOR: {
1764 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1765 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1766
1767 if (!DstTy.isScalableVector())
1768 report("Destination type must be a scalable vector", MI);
1769
1770 if (!SrcTy.isScalar())
1771 report("Source type must be a scalar", MI);
1772
1773 if (DstTy.getScalarType() != SrcTy)
1774 report("Element type of the destination must be the same type as the "
1775 "source type",
1776 MI);
1777
1778 break;
1779 }
1780 case TargetOpcode::G_DYN_STACKALLOC: {
1781 const MachineOperand &DstOp = MI->getOperand(0);
1782 const MachineOperand &AllocOp = MI->getOperand(1);
1783 const MachineOperand &AlignOp = MI->getOperand(2);
1784
1785 if (!DstOp.isReg() || !MRI->getType(DstOp.getReg()).isPointer()) {
1786 report("dst operand 0 must be a pointer type", MI);
1787 break;
1788 }
1789
1790 if (!AllocOp.isReg() || !MRI->getType(AllocOp.getReg()).isScalar()) {
1791 report("src operand 1 must be a scalar reg type", MI);
1792 break;
1793 }
1794
1795 if (!AlignOp.isImm()) {
1796 report("src operand 2 must be an immediate type", MI);
1797 break;
1798 }
1799 break;
1800 }
1801 case TargetOpcode::G_MEMCPY_INLINE:
1802 case TargetOpcode::G_MEMCPY:
1803 case TargetOpcode::G_MEMMOVE: {
1804 ArrayRef<MachineMemOperand *> MMOs = MI->memoperands();
1805 if (MMOs.size() != 2) {
1806 report("memcpy/memmove must have 2 memory operands", MI);
1807 break;
1808 }
1809
1810 if ((!MMOs[0]->isStore() || MMOs[0]->isLoad()) ||
1811 (MMOs[1]->isStore() || !MMOs[1]->isLoad())) {
1812 report("wrong memory operand types", MI);
1813 break;
1814 }
1815
1816 if (MMOs[0]->getSize() != MMOs[1]->getSize())
1817 report("inconsistent memory operand sizes", MI);
1818
1819 LLT DstPtrTy = MRI->getType(MI->getOperand(0).getReg());
1820 LLT SrcPtrTy = MRI->getType(MI->getOperand(1).getReg());
1821
1822 if (!DstPtrTy.isPointer() || !SrcPtrTy.isPointer()) {
1823 report("memory instruction operand must be a pointer", MI);
1824 break;
1825 }
1826
1827 if (DstPtrTy.getAddressSpace() != MMOs[0]->getAddrSpace())
1828 report("inconsistent store address space", MI);
1829 if (SrcPtrTy.getAddressSpace() != MMOs[1]->getAddrSpace())
1830 report("inconsistent load address space", MI);
1831
1832 if (Opc != TargetOpcode::G_MEMCPY_INLINE)
1833 if (!MI->getOperand(3).isImm() || (MI->getOperand(3).getImm() & ~1LL))
1834 report("'tail' flag (operand 3) must be an immediate 0 or 1", MI);
1835
1836 break;
1837 }
1838 case TargetOpcode::G_BZERO:
1839 case TargetOpcode::G_MEMSET: {
1840 ArrayRef<MachineMemOperand *> MMOs = MI->memoperands();
1841 std::string Name = Opc == TargetOpcode::G_MEMSET ? "memset" : "bzero";
1842 if (MMOs.size() != 1) {
1843 report(Twine(Name, " must have 1 memory operand"), MI);
1844 break;
1845 }
1846
1847 if ((!MMOs[0]->isStore() || MMOs[0]->isLoad())) {
1848 report(Twine(Name, " memory operand must be a store"), MI);
1849 break;
1850 }
1851
1852 LLT DstPtrTy = MRI->getType(MI->getOperand(0).getReg());
1853 if (!DstPtrTy.isPointer()) {
1854 report(Twine(Name, " operand must be a pointer"), MI);
1855 break;
1856 }
1857
1858 if (DstPtrTy.getAddressSpace() != MMOs[0]->getAddrSpace())
1859 report("inconsistent " + Twine(Name, " address space"), MI);
1860
1861 if (!MI->getOperand(MI->getNumOperands() - 1).isImm() ||
1862 (MI->getOperand(MI->getNumOperands() - 1).getImm() & ~1LL))
1863 report("'tail' flag (last operand) must be an immediate 0 or 1", MI);
1864
1865 break;
1866 }
1867 case TargetOpcode::G_VECREDUCE_SEQ_FADD:
1868 case TargetOpcode::G_VECREDUCE_SEQ_FMUL: {
1869 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1870 LLT Src1Ty = MRI->getType(MI->getOperand(1).getReg());
1871 LLT Src2Ty = MRI->getType(MI->getOperand(2).getReg());
1872 if (!DstTy.isScalar())
1873 report("Vector reduction requires a scalar destination type", MI);
1874 if (!Src1Ty.isScalar())
1875 report("Sequential FADD/FMUL vector reduction requires a scalar 1st operand", MI);
1876 if (!Src2Ty.isVector())
1877 report("Sequential FADD/FMUL vector reduction must have a vector 2nd operand", MI);
1878 break;
1879 }
1880 case TargetOpcode::G_VECREDUCE_FADD:
1881 case TargetOpcode::G_VECREDUCE_FMUL:
1882 case TargetOpcode::G_VECREDUCE_FMAX:
1883 case TargetOpcode::G_VECREDUCE_FMIN:
1884 case TargetOpcode::G_VECREDUCE_FMAXIMUM:
1885 case TargetOpcode::G_VECREDUCE_FMINIMUM:
1886 case TargetOpcode::G_VECREDUCE_ADD:
1887 case TargetOpcode::G_VECREDUCE_MUL:
1888 case TargetOpcode::G_VECREDUCE_AND:
1889 case TargetOpcode::G_VECREDUCE_OR:
1890 case TargetOpcode::G_VECREDUCE_XOR:
1891 case TargetOpcode::G_VECREDUCE_SMAX:
1892 case TargetOpcode::G_VECREDUCE_SMIN:
1893 case TargetOpcode::G_VECREDUCE_UMAX:
1894 case TargetOpcode::G_VECREDUCE_UMIN: {
1895 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1896 if (!DstTy.isScalar())
1897 report("Vector reduction requires a scalar destination type", MI);
1898 break;
1899 }
1900
1901 case TargetOpcode::G_SBFX:
1902 case TargetOpcode::G_UBFX: {
1903 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1904 if (DstTy.isVector()) {
1905 report("Bitfield extraction is not supported on vectors", MI);
1906 break;
1907 }
1908 break;
1909 }
1910 case TargetOpcode::G_SHL:
1911 case TargetOpcode::G_LSHR:
1912 case TargetOpcode::G_ASHR:
1913 case TargetOpcode::G_ROTR:
1914 case TargetOpcode::G_ROTL: {
1915 LLT Src1Ty = MRI->getType(MI->getOperand(1).getReg());
1916 LLT Src2Ty = MRI->getType(MI->getOperand(2).getReg());
1917 if (Src1Ty.isVector() != Src2Ty.isVector()) {
1918 report("Shifts and rotates require operands to be either all scalars or "
1919 "all vectors",
1920 MI);
1921 break;
1922 }
1923 break;
1924 }
1925 case TargetOpcode::G_LLROUND:
1926 case TargetOpcode::G_LROUND: {
1927 verifyAllRegOpsScalar(*MI, *MRI);
1928 break;
1929 }
1930 case TargetOpcode::G_IS_FPCLASS: {
1931 LLT DestTy = MRI->getType(MI->getOperand(0).getReg());
1932 LLT DestEltTy = DestTy.getScalarType();
1933 if (!DestEltTy.isScalar()) {
1934 report("Destination must be a scalar or vector of scalars", MI);
1935 break;
1936 }
1937 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1938 LLT SrcEltTy = SrcTy.getScalarType();
1939 if (!SrcEltTy.isScalar()) {
1940 report("Source must be a scalar or vector of scalars", MI);
1941 break;
1942 }
1943 if (!verifyVectorElementMatch(DestTy, SrcTy, MI))
1944 break;
1945 const MachineOperand &TestMO = MI->getOperand(2);
1946 if (!TestMO.isImm()) {
1947 report("floating-point class set (operand 2) must be an immediate", MI);
1948 break;
1949 }
1950 int64_t Test = TestMO.getImm();
1951 if (Test < 0 || Test > fcAllFlags) {
1952 report("Incorrect floating-point class set (operand 2)", MI);
1953 break;
1954 }
1955 break;
1956 }
1957 case TargetOpcode::G_PREFETCH: {
1958 const MachineOperand &AddrOp = MI->getOperand(0);
1959 if (!AddrOp.isReg() || !MRI->getType(AddrOp.getReg()).isPointer()) {
1960 report("addr operand must be a pointer", &AddrOp, 0);
1961 break;
1962 }
1963 const MachineOperand &RWOp = MI->getOperand(1);
1964 if (!RWOp.isImm() || (uint64_t)RWOp.getImm() >= 2) {
1965 report("rw operand must be an immediate 0-1", &RWOp, 1);
1966 break;
1967 }
1968 const MachineOperand &LocalityOp = MI->getOperand(2);
1969 if (!LocalityOp.isImm() || (uint64_t)LocalityOp.getImm() >= 4) {
1970 report("locality operand must be an immediate 0-3", &LocalityOp, 2);
1971 break;
1972 }
1973 const MachineOperand &CacheTypeOp = MI->getOperand(3);
1974 if (!CacheTypeOp.isImm() || (uint64_t)CacheTypeOp.getImm() >= 2) {
1975 report("cache type operand must be an immediate 0-1", &CacheTypeOp, 3);
1976 break;
1977 }
1978 break;
1979 }
1980 case TargetOpcode::G_ASSERT_ALIGN: {
1981 if (MI->getOperand(2).getImm() < 1)
1982 report("alignment immediate must be >= 1", MI);
1983 break;
1984 }
1985 case TargetOpcode::G_CONSTANT_POOL: {
1986 if (!MI->getOperand(1).isCPI())
1987 report("Src operand 1 must be a constant pool index", MI);
1988 if (!MRI->getType(MI->getOperand(0).getReg()).isPointer())
1989 report("Dst operand 0 must be a pointer", MI);
1990 break;
1991 }
1992 default:
1993 break;
1994 }
1995}
1996
1997void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
1998 const MCInstrDesc &MCID = MI->getDesc();
1999 if (MI->getNumOperands() < MCID.getNumOperands()) {
2000 report("Too few operands", MI);
2001 errs() << MCID.getNumOperands() << " operands expected, but "
2002 << MI->getNumOperands() << " given.\n";
2003 }
2004
2005 if (MI->getFlag(MachineInstr::NoConvergent) && !MCID.isConvergent())
2006 report("NoConvergent flag expected only on convergent instructions.", MI);
2007
2008 if (MI->isPHI()) {
2009 if (MF->getProperties().hasProperty(
2011 report("Found PHI instruction with NoPHIs property set", MI);
2012
2013 if (FirstNonPHI)
2014 report("Found PHI instruction after non-PHI", MI);
2015 } else if (FirstNonPHI == nullptr)
2016 FirstNonPHI = MI;
2017
2018 // Check the tied operands.
2019 if (MI->isInlineAsm())
2020 verifyInlineAsm(MI);
2021
2022 // Check that unspillable terminators define a reg and have at most one use.
2023 if (TII->isUnspillableTerminator(MI)) {
2024 if (!MI->getOperand(0).isReg() || !MI->getOperand(0).isDef())
2025 report("Unspillable Terminator does not define a reg", MI);
2026 Register Def = MI->getOperand(0).getReg();
2027 if (Def.isVirtual() &&
2028 !MF->getProperties().hasProperty(
2030 std::distance(MRI->use_nodbg_begin(Def), MRI->use_nodbg_end()) > 1)
2031 report("Unspillable Terminator expected to have at most one use!", MI);
2032 }
2033
2034 // A fully-formed DBG_VALUE must have a location. Ignore partially formed
2035 // DBG_VALUEs: these are convenient to use in tests, but should never get
2036 // generated.
2037 if (MI->isDebugValue() && MI->getNumOperands() == 4)
2038 if (!MI->getDebugLoc())
2039 report("Missing DebugLoc for debug instruction", MI);
2040
2041 // Meta instructions should never be the subject of debug value tracking,
2042 // they don't create a value in the output program at all.
2043 if (MI->isMetaInstruction() && MI->peekDebugInstrNum())
2044 report("Metadata instruction should not have a value tracking number", MI);
2045
2046 // Check the MachineMemOperands for basic consistency.
2047 for (MachineMemOperand *Op : MI->memoperands()) {
2048 if (Op->isLoad() && !MI->mayLoad())
2049 report("Missing mayLoad flag", MI);
2050 if (Op->isStore() && !MI->mayStore())
2051 report("Missing mayStore flag", MI);
2052 }
2053
2054 // Debug values must not have a slot index.
2055 // Other instructions must have one, unless they are inside a bundle.
2056 if (LiveInts) {
2057 bool mapped = !LiveInts->isNotInMIMap(*MI);
2058 if (MI->isDebugOrPseudoInstr()) {
2059 if (mapped)
2060 report("Debug instruction has a slot index", MI);
2061 } else if (MI->isInsideBundle()) {
2062 if (mapped)
2063 report("Instruction inside bundle has a slot index", MI);
2064 } else {
2065 if (!mapped)
2066 report("Missing slot index", MI);
2067 }
2068 }
2069
2070 unsigned Opc = MCID.getOpcode();
2072 verifyPreISelGenericInstruction(MI);
2073 return;
2074 }
2075
2077 if (!TII->verifyInstruction(*MI, ErrorInfo))
2078 report(ErrorInfo.data(), MI);
2079
2080 // Verify properties of various specific instruction types
2081 switch (MI->getOpcode()) {
2082 case TargetOpcode::COPY: {
2083 const MachineOperand &DstOp = MI->getOperand(0);
2084 const MachineOperand &SrcOp = MI->getOperand(1);
2085 const Register SrcReg = SrcOp.getReg();
2086 const Register DstReg = DstOp.getReg();
2087
2088 LLT DstTy = MRI->getType(DstReg);
2089 LLT SrcTy = MRI->getType(SrcReg);
2090 if (SrcTy.isValid() && DstTy.isValid()) {
2091 // If both types are valid, check that the types are the same.
2092 if (SrcTy != DstTy) {
2093 report("Copy Instruction is illegal with mismatching types", MI);
2094 errs() << "Def = " << DstTy << ", Src = " << SrcTy << "\n";
2095 }
2096
2097 break;
2098 }
2099
2100 if (!SrcTy.isValid() && !DstTy.isValid())
2101 break;
2102
2103 // If we have only one valid type, this is likely a copy between a virtual
2104 // and physical register.
2105 TypeSize SrcSize = TRI->getRegSizeInBits(SrcReg, *MRI);
2106 TypeSize DstSize = TRI->getRegSizeInBits(DstReg, *MRI);
2107 if (SrcReg.isPhysical() && DstTy.isValid()) {
2108 const TargetRegisterClass *SrcRC =
2109 TRI->getMinimalPhysRegClassLLT(SrcReg, DstTy);
2110 if (SrcRC)
2111 SrcSize = TRI->getRegSizeInBits(*SrcRC);
2112 }
2113
2114 if (DstReg.isPhysical() && SrcTy.isValid()) {
2115 const TargetRegisterClass *DstRC =
2116 TRI->getMinimalPhysRegClassLLT(DstReg, SrcTy);
2117 if (DstRC)
2118 DstSize = TRI->getRegSizeInBits(*DstRC);
2119 }
2120
2121 // The next two checks allow COPY between physical and virtual registers,
2122 // when the virtual register has a scalable size and the physical register
2123 // has a fixed size. These checks allow COPY between *potentialy* mismatched
2124 // sizes. However, once RegisterBankSelection occurs, MachineVerifier should
2125 // be able to resolve a fixed size for the scalable vector, and at that
2126 // point this function will know for sure whether the sizes are mismatched
2127 // and correctly report a size mismatch.
2128 if (SrcReg.isPhysical() && DstReg.isVirtual() && DstSize.isScalable() &&
2129 !SrcSize.isScalable())
2130 break;
2131 if (SrcReg.isVirtual() && DstReg.isPhysical() && SrcSize.isScalable() &&
2132 !DstSize.isScalable())
2133 break;
2134
2135 if (SrcSize.isNonZero() && DstSize.isNonZero() && SrcSize != DstSize) {
2136 if (!DstOp.getSubReg() && !SrcOp.getSubReg()) {
2137 report("Copy Instruction is illegal with mismatching sizes", MI);
2138 errs() << "Def Size = " << DstSize << ", Src Size = " << SrcSize
2139 << "\n";
2140 }
2141 }
2142 break;
2143 }
2144 case TargetOpcode::STATEPOINT: {
2145 StatepointOpers SO(MI);
2146 if (!MI->getOperand(SO.getIDPos()).isImm() ||
2147 !MI->getOperand(SO.getNBytesPos()).isImm() ||
2148 !MI->getOperand(SO.getNCallArgsPos()).isImm()) {
2149 report("meta operands to STATEPOINT not constant!", MI);
2150 break;
2151 }
2152
2153 auto VerifyStackMapConstant = [&](unsigned Offset) {
2154 if (Offset >= MI->getNumOperands()) {
2155 report("stack map constant to STATEPOINT is out of range!", MI);
2156 return;
2157 }
2158 if (!MI->getOperand(Offset - 1).isImm() ||
2159 MI->getOperand(Offset - 1).getImm() != StackMaps::ConstantOp ||
2160 !MI->getOperand(Offset).isImm())
2161 report("stack map constant to STATEPOINT not well formed!", MI);
2162 };
2163 VerifyStackMapConstant(SO.getCCIdx());
2164 VerifyStackMapConstant(SO.getFlagsIdx());
2165 VerifyStackMapConstant(SO.getNumDeoptArgsIdx());
2166 VerifyStackMapConstant(SO.getNumGCPtrIdx());
2167 VerifyStackMapConstant(SO.getNumAllocaIdx());
2168 VerifyStackMapConstant(SO.getNumGcMapEntriesIdx());
2169
2170 // Verify that all explicit statepoint defs are tied to gc operands as
2171 // they are expected to be a relocation of gc operands.
2172 unsigned FirstGCPtrIdx = SO.getFirstGCPtrIdx();
2173 unsigned LastGCPtrIdx = SO.getNumAllocaIdx() - 2;
2174 for (unsigned Idx = 0; Idx < MI->getNumDefs(); Idx++) {
2175 unsigned UseOpIdx;
2176 if (!MI->isRegTiedToUseOperand(Idx, &UseOpIdx)) {
2177 report("STATEPOINT defs expected to be tied", MI);
2178 break;
2179 }
2180 if (UseOpIdx < FirstGCPtrIdx || UseOpIdx > LastGCPtrIdx) {
2181 report("STATEPOINT def tied to non-gc operand", MI);
2182 break;
2183 }
2184 }
2185
2186 // TODO: verify we have properly encoded deopt arguments
2187 } break;
2188 case TargetOpcode::INSERT_SUBREG: {
2189 unsigned InsertedSize;
2190 if (unsigned SubIdx = MI->getOperand(2).getSubReg())
2191 InsertedSize = TRI->getSubRegIdxSize(SubIdx);
2192 else
2193 InsertedSize = TRI->getRegSizeInBits(MI->getOperand(2).getReg(), *MRI);
2194 unsigned SubRegSize = TRI->getSubRegIdxSize(MI->getOperand(3).getImm());
2195 if (SubRegSize < InsertedSize) {
2196 report("INSERT_SUBREG expected inserted value to have equal or lesser "
2197 "size than the subreg it was inserted into", MI);
2198 break;
2199 }
2200 } break;
2201 case TargetOpcode::REG_SEQUENCE: {
2202 unsigned NumOps = MI->getNumOperands();
2203 if (!(NumOps & 1)) {
2204 report("Invalid number of operands for REG_SEQUENCE", MI);
2205 break;
2206 }
2207
2208 for (unsigned I = 1; I != NumOps; I += 2) {
2209 const MachineOperand &RegOp = MI->getOperand(I);
2210 const MachineOperand &SubRegOp = MI->getOperand(I + 1);
2211
2212 if (!RegOp.isReg())
2213 report("Invalid register operand for REG_SEQUENCE", &RegOp, I);
2214
2215 if (!SubRegOp.isImm() || SubRegOp.getImm() == 0 ||
2216 SubRegOp.getImm() >= TRI->getNumSubRegIndices()) {
2217 report("Invalid subregister index operand for REG_SEQUENCE",
2218 &SubRegOp, I + 1);
2219 }
2220 }
2221
2222 Register DstReg = MI->getOperand(0).getReg();
2223 if (DstReg.isPhysical())
2224 report("REG_SEQUENCE does not support physical register results", MI);
2225
2226 if (MI->getOperand(0).getSubReg())
2227 report("Invalid subreg result for REG_SEQUENCE", MI);
2228
2229 break;
2230 }
2231 }
2232}
2233
2234void
2235MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
2236 const MachineInstr *MI = MO->getParent();
2237 const MCInstrDesc &MCID = MI->getDesc();
2238 unsigned NumDefs = MCID.getNumDefs();
2239 if (MCID.getOpcode() == TargetOpcode::PATCHPOINT)
2240 NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0;
2241
2242 // The first MCID.NumDefs operands must be explicit register defines
2243 if (MONum < NumDefs) {
2244 const MCOperandInfo &MCOI = MCID.operands()[MONum];
2245 if (!MO->isReg())
2246 report("Explicit definition must be a register", MO, MONum);
2247 else if (!MO->isDef() && !MCOI.isOptionalDef())
2248 report("Explicit definition marked as use", MO, MONum);
2249 else if (MO->isImplicit())
2250 report("Explicit definition marked as implicit", MO, MONum);
2251 } else if (MONum < MCID.getNumOperands()) {
2252 const MCOperandInfo &MCOI = MCID.operands()[MONum];
2253 // Don't check if it's the last operand in a variadic instruction. See,
2254 // e.g., LDM_RET in the arm back end. Check non-variadic operands only.
2255 bool IsOptional = MI->isVariadic() && MONum == MCID.getNumOperands() - 1;
2256 if (!IsOptional) {
2257 if (MO->isReg()) {
2258 if (MO->isDef() && !MCOI.isOptionalDef() && !MCID.variadicOpsAreDefs())
2259 report("Explicit operand marked as def", MO, MONum);
2260 if (MO->isImplicit())
2261 report("Explicit operand marked as implicit", MO, MONum);
2262 }
2263
2264 // Check that an instruction has register operands only as expected.
2265 if (MCOI.OperandType == MCOI::OPERAND_REGISTER &&
2266 !MO->isReg() && !MO->isFI())
2267 report("Expected a register operand.", MO, MONum);
2268 if (MO->isReg()) {
2271 !TII->isPCRelRegisterOperandLegal(*MO)))
2272 report("Expected a non-register operand.", MO, MONum);
2273 }
2274 }
2275
2276 int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO);
2277 if (TiedTo != -1) {
2278 if (!MO->isReg())
2279 report("Tied use must be a register", MO, MONum);
2280 else if (!MO->isTied())
2281 report("Operand should be tied", MO, MONum);
2282 else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
2283 report("Tied def doesn't match MCInstrDesc", MO, MONum);
2284 else if (MO->getReg().isPhysical()) {
2285 const MachineOperand &MOTied = MI->getOperand(TiedTo);
2286 if (!MOTied.isReg())
2287 report("Tied counterpart must be a register", &MOTied, TiedTo);
2288 else if (MOTied.getReg().isPhysical() &&
2289 MO->getReg() != MOTied.getReg())
2290 report("Tied physical registers must match.", &MOTied, TiedTo);
2291 }
2292 } else if (MO->isReg() && MO->isTied())
2293 report("Explicit operand should not be tied", MO, MONum);
2294 } else if (!MI->isVariadic()) {
2295 // ARM adds %reg0 operands to indicate predicates. We'll allow that.
2296 if (!MO->isValidExcessOperand())
2297 report("Extra explicit operand on non-variadic instruction", MO, MONum);
2298 }
2299
2300 switch (MO->getType()) {
2302 // Verify debug flag on debug instructions. Check this first because reg0
2303 // indicates an undefined debug value.
2304 if (MI->isDebugInstr() && MO->isUse()) {
2305 if (!MO->isDebug())
2306 report("Register operand must be marked debug", MO, MONum);
2307 } else if (MO->isDebug()) {
2308 report("Register operand must not be marked debug", MO, MONum);
2309 }
2310
2311 const Register Reg = MO->getReg();
2312 if (!Reg)
2313 return;
2314 if (MRI->tracksLiveness() && !MI->isDebugInstr())
2315 checkLiveness(MO, MONum);
2316
2317 if (MO->isDef() && MO->isUndef() && !MO->getSubReg() &&
2318 MO->getReg().isVirtual()) // TODO: Apply to physregs too
2319 report("Undef virtual register def operands require a subregister", MO, MONum);
2320
2321 // Verify the consistency of tied operands.
2322 if (MO->isTied()) {
2323 unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
2324 const MachineOperand &OtherMO = MI->getOperand(OtherIdx);
2325 if (!OtherMO.isReg())
2326 report("Must be tied to a register", MO, MONum);
2327 if (!OtherMO.isTied())
2328 report("Missing tie flags on tied operand", MO, MONum);
2329 if (MI->findTiedOperandIdx(OtherIdx) != MONum)
2330 report("Inconsistent tie links", MO, MONum);
2331 if (MONum < MCID.getNumDefs()) {
2332 if (OtherIdx < MCID.getNumOperands()) {
2333 if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO))
2334 report("Explicit def tied to explicit use without tie constraint",
2335 MO, MONum);
2336 } else {
2337 if (!OtherMO.isImplicit())
2338 report("Explicit def should be tied to implicit use", MO, MONum);
2339 }
2340 }
2341 }
2342
2343 // Verify two-address constraints after the twoaddressinstruction pass.
2344 // Both twoaddressinstruction pass and phi-node-elimination pass call
2345 // MRI->leaveSSA() to set MF as not IsSSA, we should do the verification
2346 // after twoaddressinstruction pass not after phi-node-elimination pass. So
2347 // we shouldn't use the IsSSA as the condition, we should based on
2348 // TiedOpsRewritten property to verify two-address constraints, this
2349 // property will be set in twoaddressinstruction pass.
2350 unsigned DefIdx;
2351 if (MF->getProperties().hasProperty(
2353 MO->isUse() && MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
2354 Reg != MI->getOperand(DefIdx).getReg())
2355 report("Two-address instruction operands must be identical", MO, MONum);
2356
2357 // Check register classes.
2358 unsigned SubIdx = MO->getSubReg();
2359
2360 if (Reg.isPhysical()) {
2361 if (SubIdx) {
2362 report("Illegal subregister index for physical register", MO, MONum);
2363 return;
2364 }
2365 if (MONum < MCID.getNumOperands()) {
2366 if (const TargetRegisterClass *DRC =
2367 TII->getRegClass(MCID, MONum, TRI, *MF)) {
2368 if (!DRC->contains(Reg)) {
2369 report("Illegal physical register for instruction", MO, MONum);
2370 errs() << printReg(Reg, TRI) << " is not a "
2371 << TRI->getRegClassName(DRC) << " register.\n";
2372 }
2373 }
2374 }
2375 if (MO->isRenamable()) {
2376 if (MRI->isReserved(Reg)) {
2377 report("isRenamable set on reserved register", MO, MONum);
2378 return;
2379 }
2380 }
2381 } else {
2382 // Virtual register.
2383 const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg);
2384 if (!RC) {
2385 // This is a generic virtual register.
2386
2387 // Do not allow undef uses for generic virtual registers. This ensures
2388 // getVRegDef can never fail and return null on a generic register.
2389 //
2390 // FIXME: This restriction should probably be broadened to all SSA
2391 // MIR. However, DetectDeadLanes/ProcessImplicitDefs technically still
2392 // run on the SSA function just before phi elimination.
2393 if (MO->isUndef())
2394 report("Generic virtual register use cannot be undef", MO, MONum);
2395
2396 // Debug value instruction is permitted to use undefined vregs.
2397 // This is a performance measure to skip the overhead of immediately
2398 // pruning unused debug operands. The final undef substitution occurs
2399 // when debug values are allocated in LDVImpl::handleDebugValue, so
2400 // these verifications always apply after this pass.
2401 if (isFunctionTracksDebugUserValues || !MO->isUse() ||
2402 !MI->isDebugValue() || !MRI->def_empty(Reg)) {
2403 // If we're post-Select, we can't have gvregs anymore.
2404 if (isFunctionSelected) {
2405 report("Generic virtual register invalid in a Selected function",
2406 MO, MONum);
2407 return;
2408 }
2409
2410 // The gvreg must have a type and it must not have a SubIdx.
2411 LLT Ty = MRI->getType(Reg);
2412 if (!Ty.isValid()) {
2413 report("Generic virtual register must have a valid type", MO,
2414 MONum);
2415 return;
2416 }
2417
2418 const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg);
2419 const RegisterBankInfo *RBI = MF->getSubtarget().getRegBankInfo();
2420
2421 // If we're post-RegBankSelect, the gvreg must have a bank.
2422 if (!RegBank && isFunctionRegBankSelected) {
2423 report("Generic virtual register must have a bank in a "
2424 "RegBankSelected function",
2425 MO, MONum);
2426 return;
2427 }
2428
2429 // Make sure the register fits into its register bank if any.
2430 if (RegBank && Ty.isValid() && !Ty.isScalableVector() &&
2431 RBI->getMaximumSize(RegBank->getID()) < Ty.getSizeInBits()) {
2432 report("Register bank is too small for virtual register", MO,
2433 MONum);
2434 errs() << "Register bank " << RegBank->getName() << " too small("
2435 << RBI->getMaximumSize(RegBank->getID()) << ") to fit "
2436 << Ty.getSizeInBits() << "-bits\n";
2437 return;
2438 }
2439 }
2440
2441 if (SubIdx) {
2442 report("Generic virtual register does not allow subregister index", MO,
2443 MONum);
2444 return;
2445 }
2446
2447 // If this is a target specific instruction and this operand
2448 // has register class constraint, the virtual register must
2449 // comply to it.
2450 if (!isPreISelGenericOpcode(MCID.getOpcode()) &&
2451 MONum < MCID.getNumOperands() &&
2452 TII->getRegClass(MCID, MONum, TRI, *MF)) {
2453 report("Virtual register does not match instruction constraint", MO,
2454 MONum);
2455 errs() << "Expect register class "
2456 << TRI->getRegClassName(
2457 TII->getRegClass(MCID, MONum, TRI, *MF))
2458 << " but got nothing\n";
2459 return;
2460 }
2461
2462 break;
2463 }
2464 if (SubIdx) {
2465 const TargetRegisterClass *SRC =
2466 TRI->getSubClassWithSubReg(RC, SubIdx);
2467 if (!SRC) {
2468 report("Invalid subregister index for virtual register", MO, MONum);
2469 errs() << "Register class " << TRI->getRegClassName(RC)
2470 << " does not support subreg index " << SubIdx << "\n";
2471 return;
2472 }
2473 if (RC != SRC) {
2474 report("Invalid register class for subregister index", MO, MONum);
2475 errs() << "Register class " << TRI->getRegClassName(RC)
2476 << " does not fully support subreg index " << SubIdx << "\n";
2477 return;
2478 }
2479 }
2480 if (MONum < MCID.getNumOperands()) {
2481 if (const TargetRegisterClass *DRC =
2482 TII->getRegClass(MCID, MONum, TRI, *MF)) {
2483 if (SubIdx) {
2484 const TargetRegisterClass *SuperRC =
2485 TRI->getLargestLegalSuperClass(RC, *MF);
2486 if (!SuperRC) {
2487 report("No largest legal super class exists.", MO, MONum);
2488 return;
2489 }
2490 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
2491 if (!DRC) {
2492 report("No matching super-reg register class.", MO, MONum);
2493 return;
2494 }
2495 }
2496 if (!RC->hasSuperClassEq(DRC)) {
2497 report("Illegal virtual register for instruction", MO, MONum);
2498 errs() << "Expected a " << TRI->getRegClassName(DRC)
2499 << " register, but got a " << TRI->getRegClassName(RC)
2500 << " register\n";
2501 }
2502 }
2503 }
2504 }
2505 break;
2506 }
2507
2509 regMasks.push_back(MO->getRegMask());
2510 break;
2511
2513 if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
2514 report("PHI operand is not in the CFG", MO, MONum);
2515 break;
2516
2518 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
2519 LiveInts && !LiveInts->isNotInMIMap(*MI)) {
2520 int FI = MO->getIndex();
2521 LiveInterval &LI = LiveStks->getInterval(FI);
2522 SlotIndex Idx = LiveInts->getInstructionIndex(*MI);
2523
2524 bool stores = MI->mayStore();
2525 bool loads = MI->mayLoad();
2526 // For a memory-to-memory move, we need to check if the frame
2527 // index is used for storing or loading, by inspecting the
2528 // memory operands.
2529 if (stores && loads) {
2530 for (auto *MMO : MI->memoperands()) {
2531 const PseudoSourceValue *PSV = MMO->getPseudoValue();
2532 if (PSV == nullptr) continue;
2534 dyn_cast<FixedStackPseudoSourceValue>(PSV);
2535 if (Value == nullptr) continue;
2536 if (Value->getFrameIndex() != FI) continue;
2537
2538 if (MMO->isStore())
2539 loads = false;
2540 else
2541 stores = false;
2542 break;
2543 }
2544 if (loads == stores)
2545 report("Missing fixed stack memoperand.", MI);
2546 }
2547 if (loads && !LI.liveAt(Idx.getRegSlot(true))) {
2548 report("Instruction loads from dead spill slot", MO, MONum);
2549 errs() << "Live stack: " << LI << '\n';
2550 }
2551 if (stores && !LI.liveAt(Idx.getRegSlot())) {
2552 report("Instruction stores to dead spill slot", MO, MONum);
2553 errs() << "Live stack: " << LI << '\n';
2554 }
2555 }
2556 break;
2557
2559 if (MO->getCFIIndex() >= MF->getFrameInstructions().size())
2560 report("CFI instruction has invalid index", MO, MONum);
2561 break;
2562
2563 default:
2564 break;
2565 }
2566}
2567
2568void MachineVerifier::checkLivenessAtUse(const MachineOperand *MO,
2569 unsigned MONum, SlotIndex UseIdx,
2570 const LiveRange &LR,
2571 Register VRegOrUnit,
2572 LaneBitmask LaneMask) {
2573 const MachineInstr *MI = MO->getParent();
2574 LiveQueryResult LRQ = LR.Query(UseIdx);
2575 bool HasValue = LRQ.valueIn() || (MI->isPHI() && LRQ.valueOut());
2576 // Check if we have a segment at the use, note however that we only need one
2577 // live subregister range, the others may be dead.
2578 if (!HasValue && LaneMask.none()) {
2579 report("No live segment at use", MO, MONum);
2580 report_context_liverange(LR);
2581 report_context_vreg_regunit(VRegOrUnit);
2582 report_context(UseIdx);
2583 }
2584 if (MO->isKill() && !LRQ.isKill()) {
2585 report("Live range continues after kill flag", MO, MONum);
2586 report_context_liverange(LR);
2587 report_context_vreg_regunit(VRegOrUnit);
2588 if (LaneMask.any())
2589 report_context_lanemask(LaneMask);
2590 report_context(UseIdx);
2591 }
2592}
2593
2594void MachineVerifier::checkLivenessAtDef(const MachineOperand *MO,
2595 unsigned MONum, SlotIndex DefIdx,
2596 const LiveRange &LR,
2597 Register VRegOrUnit,
2598 bool SubRangeCheck,
2599 LaneBitmask LaneMask) {
2600 if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) {
2601 // The LR can correspond to the whole reg and its def slot is not obliged
2602 // to be the same as the MO' def slot. E.g. when we check here "normal"
2603 // subreg MO but there is other EC subreg MO in the same instruction so the
2604 // whole reg has EC def slot and differs from the currently checked MO' def
2605 // slot. For example:
2606 // %0 [16e,32r:0) 0@16e L..3 [16e,32r:0) 0@16e L..C [16r,32r:0) 0@16r
2607 // Check that there is an early-clobber def of the same superregister
2608 // somewhere is performed in visitMachineFunctionAfter()
2609 if (((SubRangeCheck || MO->getSubReg() == 0) && VNI->def != DefIdx) ||
2610 !SlotIndex::isSameInstr(VNI->def, DefIdx) ||
2611 (VNI->def != DefIdx &&
2612 (!VNI->def.isEarlyClobber() || !DefIdx.isRegister()))) {
2613 report("Inconsistent valno->def", MO, MONum);
2614 report_context_liverange(LR);
2615 report_context_vreg_regunit(VRegOrUnit);
2616 if (LaneMask.any())
2617 report_context_lanemask(LaneMask);
2618 report_context(*VNI);
2619 report_context(DefIdx);
2620 }
2621 } else {
2622 report("No live segment at def", MO, MONum);
2623 report_context_liverange(LR);
2624 report_context_vreg_regunit(VRegOrUnit);
2625 if (LaneMask.any())
2626 report_context_lanemask(LaneMask);
2627 report_context(DefIdx);
2628 }
2629 // Check that, if the dead def flag is present, LiveInts agree.
2630 if (MO->isDead()) {
2631 LiveQueryResult LRQ = LR.Query(DefIdx);
2632 if (!LRQ.isDeadDef()) {
2633 assert(VRegOrUnit.isVirtual() && "Expecting a virtual register.");
2634 // A dead subreg def only tells us that the specific subreg is dead. There
2635 // could be other non-dead defs of other subregs, or we could have other
2636 // parts of the register being live through the instruction. So unless we
2637 // are checking liveness for a subrange it is ok for the live range to
2638 // continue, given that we have a dead def of a subregister.
2639 if (SubRangeCheck || MO->getSubReg() == 0) {
2640 report("Live range continues after dead def flag", MO, MONum);
2641 report_context_liverange(LR);
2642 report_context_vreg_regunit(VRegOrUnit);
2643 if (LaneMask.any())
2644 report_context_lanemask(LaneMask);
2645 }
2646 }
2647 }
2648}
2649
2650void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
2651 const MachineInstr *MI = MO->getParent();
2652 const Register Reg = MO->getReg();
2653 const unsigned SubRegIdx = MO->getSubReg();
2654
2655 const LiveInterval *LI = nullptr;
2656 if (LiveInts && Reg.isVirtual()) {
2657 if (LiveInts->hasInterval(Reg)) {
2658 LI = &LiveInts->getInterval(Reg);
2659 if (SubRegIdx != 0 && (MO->isDef() || !MO->isUndef()) && !LI->empty() &&
2660 !LI->hasSubRanges() && MRI->shouldTrackSubRegLiveness(Reg))
2661 report("Live interval for subreg operand has no subranges", MO, MONum);
2662 } else {
2663 report("Virtual register has no live interval", MO, MONum);
2664 }
2665 }
2666
2667 // Both use and def operands can read a register.
2668 if (MO->readsReg()) {
2669 if (MO->isKill())
2670 addRegWithSubRegs(regsKilled, Reg);
2671
2672 // Check that LiveVars knows this kill (unless we are inside a bundle, in
2673 // which case we have already checked that LiveVars knows any kills on the
2674 // bundle header instead).
2675 if (LiveVars && Reg.isVirtual() && MO->isKill() &&
2676 !MI->isBundledWithPred()) {
2677 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
2678 if (!is_contained(VI.Kills, MI))
2679 report("Kill missing from LiveVariables", MO, MONum);
2680 }
2681
2682 // Check LiveInts liveness and kill.
2683 if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
2684 SlotIndex UseIdx;
2685 if (MI->isPHI()) {
2686 // PHI use occurs on the edge, so check for live out here instead.
2687 UseIdx = LiveInts->getMBBEndIdx(
2688 MI->getOperand(MONum + 1).getMBB()).getPrevSlot();
2689 } else {
2690 UseIdx = LiveInts->getInstructionIndex(*MI);
2691 }
2692 // Check the cached regunit intervals.
2693 if (Reg.isPhysical() && !isReserved(Reg)) {
2694 for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg())) {
2695 if (MRI->isReservedRegUnit(Unit))
2696 continue;
2697 if (const LiveRange *LR = LiveInts->getCachedRegUnit(Unit))
2698 checkLivenessAtUse(MO, MONum, UseIdx, *LR, Unit);
2699 }
2700 }
2701
2702 if (Reg.isVirtual()) {
2703 // This is a virtual register interval.
2704 checkLivenessAtUse(MO, MONum, UseIdx, *LI, Reg);
2705
2706 if (LI->hasSubRanges() && !MO->isDef()) {
2707 LaneBitmask MOMask = SubRegIdx != 0
2708 ? TRI->getSubRegIndexLaneMask(SubRegIdx)
2709 : MRI->getMaxLaneMaskForVReg(Reg);
2710 LaneBitmask LiveInMask;
2711 for (const LiveInterval::SubRange &SR : LI->subranges()) {
2712 if ((MOMask & SR.LaneMask).none())
2713 continue;
2714 checkLivenessAtUse(MO, MONum, UseIdx, SR, Reg, SR.LaneMask);
2715 LiveQueryResult LRQ = SR.Query(UseIdx);
2716 if (LRQ.valueIn() || (MI->isPHI() && LRQ.valueOut()))
2717 LiveInMask |= SR.LaneMask;
2718 }
2719 // At least parts of the register has to be live at the use.
2720 if ((LiveInMask & MOMask).none()) {
2721 report("No live subrange at use", MO, MONum);
2722 report_context(*LI);
2723 report_context(UseIdx);
2724 }
2725 // For PHIs all lanes should be live
2726 if (MI->isPHI() && LiveInMask != MOMask) {
2727 report("Not all lanes of PHI source live at use", MO, MONum);
2728 report_context(*LI);
2729 report_context(UseIdx);
2730 }
2731 }
2732 }
2733 }
2734
2735 // Use of a dead register.
2736 if (!regsLive.count(Reg)) {
2737 if (Reg.isPhysical()) {
2738 // Reserved registers may be used even when 'dead'.
2739 bool Bad = !isReserved(Reg);
2740 // We are fine if just any subregister has a defined value.
2741 if (Bad) {
2742
2743 for (const MCPhysReg &SubReg : TRI->subregs(Reg)) {
2744 if (regsLive.count(SubReg)) {
2745 Bad = false;
2746 break;
2747 }
2748 }
2749 }
2750 // If there is an additional implicit-use of a super register we stop
2751 // here. By definition we are fine if the super register is not
2752 // (completely) dead, if the complete super register is dead we will
2753 // get a report for its operand.
2754 if (Bad) {
2755 for (const MachineOperand &MOP : MI->uses()) {
2756 if (!MOP.isReg() || !MOP.isImplicit())
2757 continue;
2758
2759 if (!MOP.getReg().isPhysical())
2760 continue;
2761
2762 if (llvm::is_contained(TRI->subregs(MOP.getReg()), Reg))
2763 Bad = false;
2764 }
2765 }
2766 if (Bad)
2767 report("Using an undefined physical register", MO, MONum);
2768 } else if (MRI->def_empty(Reg)) {
2769 report("Reading virtual register without a def", MO, MONum);
2770 } else {
2771 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
2772 // We don't know which virtual registers are live in, so only complain
2773 // if vreg was killed in this MBB. Otherwise keep track of vregs that
2774 // must be live in. PHI instructions are handled separately.
2775 if (MInfo.regsKilled.count(Reg))
2776 report("Using a killed virtual register", MO, MONum);
2777 else if (!MI->isPHI())
2778 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
2779 }
2780 }
2781 }
2782
2783 if (MO->isDef()) {
2784 // Register defined.
2785 // TODO: verify that earlyclobber ops are not used.
2786 if (MO->isDead())
2787 addRegWithSubRegs(regsDead, Reg);
2788 else
2789 addRegWithSubRegs(regsDefined, Reg);
2790
2791 // Verify SSA form.
2792 if (MRI->isSSA() && Reg.isVirtual() &&
2793 std::next(MRI->def_begin(Reg)) != MRI->def_end())
2794 report("Multiple virtual register defs in SSA form", MO, MONum);
2795
2796 // Check LiveInts for a live segment, but only for virtual registers.
2797 if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
2798 SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI);
2799 DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
2800
2801 if (Reg.isVirtual()) {
2802 checkLivenessAtDef(MO, MONum, DefIdx, *LI, Reg);
2803
2804 if (LI->hasSubRanges()) {
2805 LaneBitmask MOMask = SubRegIdx != 0
2806 ? TRI->getSubRegIndexLaneMask(SubRegIdx)
2807 : MRI->getMaxLaneMaskForVReg(Reg);
2808 for (const LiveInterval::SubRange &SR : LI->subranges()) {
2809 if ((SR.LaneMask & MOMask).none())
2810 continue;
2811 checkLivenessAtDef(MO, MONum, DefIdx, SR, Reg, true, SR.LaneMask);
2812 }
2813 }
2814 }
2815 }
2816 }
2817}
2818
2819// This function gets called after visiting all instructions in a bundle. The
2820// argument points to the bundle header.
2821// Normal stand-alone instructions are also considered 'bundles', and this
2822// function is called for all of them.
2823void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
2824 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
2825 set_union(MInfo.regsKilled, regsKilled);
2826 set_subtract(regsLive, regsKilled); regsKilled.clear();
2827 // Kill any masked registers.
2828 while (!regMasks.empty()) {
2829 const uint32_t *Mask = regMasks.pop_back_val();
2830 for (Register Reg : regsLive)
2831 if (Reg.isPhysical() &&
2832 MachineOperand::clobbersPhysReg(Mask, Reg.asMCReg()))
2833 regsDead.push_back(Reg);
2834 }
2835 set_subtract(regsLive, regsDead); regsDead.clear();
2836 set_union(regsLive, regsDefined); regsDefined.clear();
2837}
2838
2839void
2840MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
2841 MBBInfoMap[MBB].regsLiveOut = regsLive;
2842 regsLive.clear();
2843
2844 if (Indexes) {
2845 SlotIndex stop = Indexes->getMBBEndIdx(MBB);
2846 if (!(stop > lastIndex)) {
2847 report("Block ends before last instruction index", MBB);
2848 errs() << "Block ends at " << stop
2849 << " last instruction was at " << lastIndex << '\n';
2850 }
2851 lastIndex = stop;
2852 }
2853}
2854
2855namespace {
2856// This implements a set of registers that serves as a filter: can filter other
2857// sets by passing through elements not in the filter and blocking those that
2858// are. Any filter implicitly includes the full set of physical registers upon
2859// creation, thus filtering them all out. The filter itself as a set only grows,
2860// and needs to be as efficient as possible.
2861struct VRegFilter {
2862 // Add elements to the filter itself. \pre Input set \p FromRegSet must have
2863 // no duplicates. Both virtual and physical registers are fine.
2864 template <typename RegSetT> void add(const RegSetT &FromRegSet) {
2865 SmallVector<Register, 0> VRegsBuffer;
2866 filterAndAdd(FromRegSet, VRegsBuffer);
2867 }
2868 // Filter \p FromRegSet through the filter and append passed elements into \p
2869 // ToVRegs. All elements appended are then added to the filter itself.
2870 // \returns true if anything changed.
2871 template <typename RegSetT>
2872 bool filterAndAdd(const RegSetT &FromRegSet,
2873 SmallVectorImpl<Register> &ToVRegs) {
2874 unsigned SparseUniverse = Sparse.size();
2875 unsigned NewSparseUniverse = SparseUniverse;
2876 unsigned NewDenseSize = Dense.size();
2877 size_t Begin = ToVRegs.size();
2878 for (Register Reg : FromRegSet) {
2879 if (!Reg.isVirtual())
2880 continue;
2881 unsigned Index = Register::virtReg2Index(Reg);
2882 if (Index < SparseUniverseMax) {
2883 if (Index < SparseUniverse && Sparse.test(Index))
2884 continue;
2885 NewSparseUniverse = std::max(NewSparseUniverse, Index + 1);
2886 } else {
2887 if (Dense.count(Reg))
2888 continue;
2889 ++NewDenseSize;
2890 }
2891 ToVRegs.push_back(Reg);
2892 }
2893 size_t End = ToVRegs.size();
2894 if (Begin == End)
2895 return false;
2896 // Reserving space in sets once performs better than doing so continuously
2897 // and pays easily for double look-ups (even in Dense with SparseUniverseMax
2898 // tuned all the way down) and double iteration (the second one is over a
2899 // SmallVector, which is a lot cheaper compared to DenseSet or BitVector).
2900 Sparse.resize(NewSparseUniverse);
2901 Dense.reserve(NewDenseSize);
2902 for (unsigned I = Begin; I < End; ++I) {
2903 Register Reg = ToVRegs[I];
2904 unsigned Index = Register::virtReg2Index(Reg);
2905 if (Index < SparseUniverseMax)
2906 Sparse.set(Index);
2907 else
2908 Dense.insert(Reg);
2909 }
2910 return true;
2911 }
2912
2913private:
2914 static constexpr unsigned SparseUniverseMax = 10 * 1024 * 8;
2915 // VRegs indexed within SparseUniverseMax are tracked by Sparse, those beyound
2916 // are tracked by Dense. The only purpose of the threashold and the Dense set
2917 // is to have a reasonably growing memory usage in pathological cases (large
2918 // number of very sparse VRegFilter instances live at the same time). In
2919 // practice even in the worst-by-execution time cases having all elements
2920 // tracked by Sparse (very large SparseUniverseMax scenario) tends to be more
2921 // space efficient than if tracked by Dense. The threashold is set to keep the
2922 // worst-case memory usage within 2x of figures determined empirically for
2923 // "all Dense" scenario in such worst-by-execution-time cases.
2924 BitVector Sparse;
2926};
2927
2928// Implements both a transfer function and a (binary, in-place) join operator
2929// for a dataflow over register sets with set union join and filtering transfer
2930// (out_b = in_b \ filter_b). filter_b is expected to be set-up ahead of time.
2931// Maintains out_b as its state, allowing for O(n) iteration over it at any
2932// time, where n is the size of the set (as opposed to O(U) where U is the
2933// universe). filter_b implicitly contains all physical registers at all times.
2934class FilteringVRegSet {
2935 VRegFilter Filter;
2937
2938public:
2939 // Set-up the filter_b. \pre Input register set \p RS must have no duplicates.
2940 // Both virtual and physical registers are fine.
2941 template <typename RegSetT> void addToFilter(const RegSetT &RS) {
2942 Filter.add(RS);
2943 }
2944 // Passes \p RS through the filter_b (transfer function) and adds what's left
2945 // to itself (out_b).
2946 template <typename RegSetT> bool add(const RegSetT &RS) {
2947 // Double-duty the Filter: to maintain VRegs a set (and the join operation
2948 // a set union) just add everything being added here to the Filter as well.
2949 return Filter.filterAndAdd(RS, VRegs);
2950 }
2951 using const_iterator = decltype(VRegs)::const_iterator;
2952 const_iterator begin() const { return VRegs.begin(); }
2953 const_iterator end() const { return VRegs.end(); }
2954 size_t size() const { return VRegs.size(); }
2955};
2956} // namespace
2957
2958// Calculate the largest possible vregsPassed sets. These are the registers that
2959// can pass through an MBB live, but may not be live every time. It is assumed
2960// that all vregsPassed sets are empty before the call.
2961void MachineVerifier::calcRegsPassed() {
2962 if (MF->empty())
2963 // ReversePostOrderTraversal doesn't handle empty functions.
2964 return;
2965
2966 for (const MachineBasicBlock *MB :
2968 FilteringVRegSet VRegs;
2969 BBInfo &Info = MBBInfoMap[MB];
2970 assert(Info.reachable);
2971
2972 VRegs.addToFilter(Info.regsKilled);
2973 VRegs.addToFilter(Info.regsLiveOut);
2974 for (const MachineBasicBlock *Pred : MB->predecessors()) {
2975 const BBInfo &PredInfo = MBBInfoMap[Pred];
2976 if (!PredInfo.reachable)
2977 continue;
2978
2979 VRegs.add(PredInfo.regsLiveOut);
2980 VRegs.add(PredInfo.vregsPassed);
2981 }
2982 Info.vregsPassed.reserve(VRegs.size());
2983 Info.vregsPassed.insert(VRegs.begin(), VRegs.end());
2984 }
2985}
2986
2987// Calculate the set of virtual registers that must be passed through each basic
2988// block in order to satisfy the requirements of successor blocks. This is very
2989// similar to calcRegsPassed, only backwards.
2990void MachineVerifier::calcRegsRequired() {
2991 // First push live-in regs to predecessors' vregsRequired.
2993 for (const auto &MBB : *MF) {
2994 BBInfo &MInfo = MBBInfoMap[&MBB];
2995 for (const MachineBasicBlock *Pred : MBB.predecessors()) {
2996 BBInfo &PInfo = MBBInfoMap[Pred];
2997 if (PInfo.addRequired(MInfo.vregsLiveIn))
2998 todo.insert(Pred);
2999 }
3000
3001 // Handle the PHI node.
3002 for (const MachineInstr &MI : MBB.phis()) {
3003 for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) {
3004 // Skip those Operands which are undef regs or not regs.
3005 if (!MI.getOperand(i).isReg() || !MI.getOperand(i).readsReg())
3006 continue;
3007
3008 // Get register and predecessor for one PHI edge.
3009 Register Reg = MI.getOperand(i).getReg();
3010 const MachineBasicBlock *Pred = MI.getOperand(i + 1).getMBB();
3011
3012 BBInfo &PInfo = MBBInfoMap[Pred];
3013 if (PInfo.addRequired(Reg))
3014 todo.insert(Pred);
3015 }
3016 }
3017 }
3018
3019 // Iteratively push vregsRequired to predecessors. This will converge to the
3020 // same final state regardless of DenseSet iteration order.
3021 while (!todo.empty()) {
3022 const MachineBasicBlock *MBB = *todo.begin();
3023 todo.erase(MBB);
3024 BBInfo &MInfo = MBBInfoMap[MBB];
3025 for (const MachineBasicBlock *Pred : MBB->predecessors()) {
3026 if (Pred == MBB)
3027 continue;
3028 BBInfo &SInfo = MBBInfoMap[Pred];
3029 if (SInfo.addRequired(MInfo.vregsRequired))
3030 todo.insert(Pred);
3031 }
3032 }
3033}
3034
3035// Check PHI instructions at the beginning of MBB. It is assumed that
3036// calcRegsPassed has been run so BBInfo::isLiveOut is valid.
3037void MachineVerifier::checkPHIOps(const MachineBasicBlock &MBB) {
3038 BBInfo &MInfo = MBBInfoMap[&MBB];
3039
3041 for (const MachineInstr &Phi : MBB) {
3042 if (!Phi.isPHI())
3043 break;
3044 seen.clear();
3045
3046 const MachineOperand &MODef = Phi.getOperand(0);
3047 if (!MODef.isReg() || !MODef.isDef()) {
3048 report("Expected first PHI operand to be a register def", &MODef, 0);
3049 continue;
3050 }
3051 if (MODef.isTied() || MODef.isImplicit() || MODef.isInternalRead() ||
3052 MODef.isEarlyClobber() || MODef.isDebug())
3053 report("Unexpected flag on PHI operand", &MODef, 0);
3054 Register DefReg = MODef.getReg();
3055 if (!DefReg.isVirtual())
3056 report("Expected first PHI operand to be a virtual register", &MODef, 0);
3057
3058 for (unsigned I = 1, E = Phi.getNumOperands(); I != E; I += 2) {
3059 const MachineOperand &MO0 = Phi.getOperand(I);
3060 if (!MO0.isReg()) {
3061 report("Expected PHI operand to be a register", &MO0, I);
3062 continue;
3063 }
3064 if (MO0.isImplicit() || MO0.isInternalRead() || MO0.isEarlyClobber() ||
3065 MO0.isDebug() || MO0.isTied())
3066 report("Unexpected flag on PHI operand", &MO0, I);
3067
3068 const MachineOperand &MO1 = Phi.getOperand(I + 1);
3069 if (!MO1.isMBB()) {
3070 report("Expected PHI operand to be a basic block", &MO1, I + 1);
3071 continue;
3072 }
3073
3074 const MachineBasicBlock &Pre = *MO1.getMBB();
3075 if (!Pre.isSuccessor(&MBB)) {
3076 report("PHI input is not a predecessor block", &MO1, I + 1);
3077 continue;
3078 }
3079
3080 if (MInfo.reachable) {
3081 seen.insert(&Pre);
3082 BBInfo &PrInfo = MBBInfoMap[&Pre];
3083 if (!MO0.isUndef() && PrInfo.reachable &&
3084 !PrInfo.isLiveOut(MO0.getReg()))
3085 report("PHI operand is not live-out from predecessor", &MO0, I);
3086 }
3087 }
3088
3089 // Did we see all predecessors?
3090 if (MInfo.reachable) {
3091 for (MachineBasicBlock *Pred : MBB.predecessors()) {
3092 if (!seen.count(Pred)) {
3093 report("Missing PHI operand", &Phi);
3094 errs() << printMBBReference(*Pred)
3095 << " is a predecessor according to the CFG.\n";
3096 }
3097 }
3098 }
3099 }
3100}
3101
3102static void
3104 std::function<void(const Twine &Message)> FailureCB) {
3106 CV.initialize(&errs(), FailureCB, MF);
3107
3108 for (const auto &MBB : MF) {
3109 CV.visit(MBB);
3110 for (const auto &MI : MBB.instrs())
3111 CV.visit(MI);
3112 }
3113
3114 if (CV.sawTokens()) {
3115 DT.recalculate(const_cast<MachineFunction &>(MF));
3116 CV.verify(DT);
3117 }
3118}
3119
3120void MachineVerifier::visitMachineFunctionAfter() {
3121 auto FailureCB = [this](const Twine &Message) {
3122 report(Message.str().c_str(), MF);
3123 };
3124 verifyConvergenceControl(*MF, DT, FailureCB);
3125
3126 calcRegsPassed();
3127
3128 for (const MachineBasicBlock &MBB : *MF)
3129 checkPHIOps(MBB);
3130
3131 // Now check liveness info if available
3132 calcRegsRequired();
3133
3134 // Check for killed virtual registers that should be live out.
3135 for (const auto &MBB : *MF) {
3136 BBInfo &MInfo = MBBInfoMap[&MBB];
3137 for (Register VReg : MInfo.vregsRequired)
3138 if (MInfo.regsKilled.count(VReg)) {
3139 report("Virtual register killed in block, but needed live out.", &MBB);
3140 errs() << "Virtual register " << printReg(VReg)
3141 << " is used after the block.\n";
3142 }
3143 }
3144
3145 if (!MF->empty()) {
3146 BBInfo &MInfo = MBBInfoMap[&MF->front()];
3147 for (Register VReg : MInfo.vregsRequired) {
3148 report("Virtual register defs don't dominate all uses.", MF);
3149 report_context_vreg(VReg);
3150 }
3151 }
3152
3153 if (LiveVars)
3154 verifyLiveVariables();
3155 if (LiveInts)
3156 verifyLiveIntervals();
3157
3158 // Check live-in list of each MBB. If a register is live into MBB, check
3159 // that the register is in regsLiveOut of each predecessor block. Since
3160 // this must come from a definition in the predecesssor or its live-in
3161 // list, this will catch a live-through case where the predecessor does not
3162 // have the register in its live-in list. This currently only checks
3163 // registers that have no aliases, are not allocatable and are not
3164 // reserved, which could mean a condition code register for instance.
3165 if (MRI->tracksLiveness())
3166 for (const auto &MBB : *MF)
3168 MCPhysReg LiveInReg = P.PhysReg;
3169 bool hasAliases = MCRegAliasIterator(LiveInReg, TRI, false).isValid();
3170 if (hasAliases || isAllocatable(LiveInReg) || isReserved(LiveInReg))
3171 continue;
3172 for (const MachineBasicBlock *Pred : MBB.predecessors()) {
3173 BBInfo &PInfo = MBBInfoMap[Pred];
3174 if (!PInfo.regsLiveOut.count(LiveInReg)) {
3175 report("Live in register not found to be live out from predecessor.",
3176 &MBB);
3177 errs() << TRI->getName(LiveInReg)
3178 << " not found to be live out from "
3179 << printMBBReference(*Pred) << "\n";
3180 }
3181 }
3182 }
3183
3184 for (auto CSInfo : MF->getCallSitesInfo())
3185 if (!CSInfo.first->isCall())
3186 report("Call site info referencing instruction that is not call", MF);
3187
3188 // If there's debug-info, check that we don't have any duplicate value
3189 // tracking numbers.
3190 if (MF->getFunction().getSubprogram()) {
3191 DenseSet<unsigned> SeenNumbers;
3192 for (const auto &MBB : *MF) {
3193 for (const auto &MI : MBB) {
3194 if (auto Num = MI.peekDebugInstrNum()) {
3195 auto Result = SeenNumbers.insert((unsigned)Num);
3196 if (!Result.second)
3197 report("Instruction has a duplicated value tracking number", &MI);
3198 }
3199 }
3200 }
3201 }
3202}
3203
3204void MachineVerifier::verifyLiveVariables() {
3205 assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
3206 for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
3208 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
3209 for (const auto &MBB : *MF) {
3210 BBInfo &MInfo = MBBInfoMap[&MBB];
3211
3212 // Our vregsRequired should be identical to LiveVariables' AliveBlocks
3213 if (MInfo.vregsRequired.count(Reg)) {
3214 if (!VI.AliveBlocks.test(MBB.getNumber())) {
3215 report("LiveVariables: Block missing from AliveBlocks", &MBB);
3216 errs() << "Virtual register " << printReg(Reg)
3217 << " must be live through the block.\n";
3218 }
3219 } else {
3220 if (VI.AliveBlocks.test(MBB.getNumber())) {
3221 report("LiveVariables: Block should not be in AliveBlocks", &MBB);
3222 errs() << "Virtual register " << printReg(Reg)
3223 << " is not needed live through the block.\n";
3224 }
3225 }
3226 }
3227 }
3228}
3229
3230void MachineVerifier::verifyLiveIntervals() {
3231 assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
3232 for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
3234
3235 // Spilling and splitting may leave unused registers around. Skip them.
3236 if (MRI->reg_nodbg_empty(Reg))
3237 continue;
3238
3239 if (!LiveInts->hasInterval(Reg)) {
3240 report("Missing live interval for virtual register", MF);
3241 errs() << printReg(Reg, TRI) << " still has defs or uses\n";
3242 continue;
3243 }
3244
3245 const LiveInterval &LI = LiveInts->getInterval(Reg);
3246 assert(Reg == LI.reg() && "Invalid reg to interval mapping");
3247 verifyLiveInterval(LI);
3248 }
3249
3250 // Verify all the cached regunit intervals.
3251 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
3252 if (const LiveRange *LR = LiveInts->getCachedRegUnit(i))
3253 verifyLiveRange(*LR, i);
3254}
3255
3256void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
3257 const VNInfo *VNI, Register Reg,
3258 LaneBitmask LaneMask) {
3259 if (VNI->isUnused())
3260 return;
3261
3262 const VNInfo *DefVNI = LR.getVNInfoAt(VNI->def);
3263
3264 if (!DefVNI) {
3265 report("Value not live at VNInfo def and not marked unused", MF);
3266 report_context(LR, Reg, LaneMask);
3267 report_context(*VNI);
3268 return;
3269 }
3270
3271 if (DefVNI != VNI) {
3272 report("Live segment at def has different VNInfo", MF);
3273 report_context(LR, Reg, LaneMask);
3274 report_context(*VNI);
3275 return;
3276 }
3277
3278 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
3279 if (!MBB) {
3280 report("Invalid VNInfo definition index", MF);
3281 report_context(LR, Reg, LaneMask);
3282 report_context(*VNI);
3283 return;
3284 }
3285
3286 if (VNI->isPHIDef()) {
3287 if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
3288 report("PHIDef VNInfo is not defined at MBB start", MBB);
3289 report_context(LR, Reg, LaneMask);
3290 report_context(*VNI);
3291 }
3292 return;
3293 }
3294
3295 // Non-PHI def.
3296 const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
3297 if (!MI) {
3298 report("No instruction at VNInfo def index", MBB);
3299 report_context(LR, Reg, LaneMask);
3300 report_context(*VNI);
3301 return;
3302 }
3303
3304 if (Reg != 0) {
3305 bool hasDef = false;
3306 bool isEarlyClobber = false;
3307 for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
3308 if (!MOI->isReg() || !MOI->isDef())
3309 continue;
3310 if (Reg.isVirtual()) {
3311 if (MOI->getReg() != Reg)
3312 continue;
3313 } else {
3314 if (!MOI->getReg().isPhysical() || !TRI->hasRegUnit(MOI->getReg(), Reg))
3315 continue;
3316 }
3317 if (LaneMask.any() &&
3318 (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
3319 continue;
3320 hasDef = true;
3321 if (MOI->isEarlyClobber())
3322 isEarlyClobber = true;
3323 }
3324
3325 if (!hasDef) {
3326 report("Defining instruction does not modify register", MI);
3327 report_context(LR, Reg, LaneMask);
3328 report_context(*VNI);
3329 }
3330
3331 // Early clobber defs begin at USE slots, but other defs must begin at
3332 // DEF slots.
3333 if (isEarlyClobber) {
3334 if (!VNI->def.isEarlyClobber()) {
3335 report("Early clobber def must be at an early-clobber slot", MBB);
3336 report_context(LR, Reg, LaneMask);
3337 report_context(*VNI);
3338 }
3339 } else if (!VNI->def.isRegister()) {
3340 report("Non-PHI, non-early clobber def must be at a register slot", MBB);
3341 report_context(LR, Reg, LaneMask);
3342 report_context(*VNI);
3343 }
3344 }
3345}
3346
3347void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
3349 Register Reg,
3350 LaneBitmask LaneMask) {
3351 const LiveRange::Segment &S = *I;
3352 const VNInfo *VNI = S.valno;
3353 assert(VNI && "Live segment has no valno");
3354
3355 if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) {
3356 report("Foreign valno in live segment", MF);
3357 report_context(LR, Reg, LaneMask);
3358 report_context(S);
3359 report_context(*VNI);
3360 }
3361
3362 if (VNI->isUnused()) {
3363 report("Live segment valno is marked unused", MF);
3364 report_context(LR, Reg, LaneMask);
3365 report_context(S);
3366 }
3367
3368 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(S.start);
3369 if (!MBB) {
3370 report("Bad start of live segment, no basic block", MF);
3371 report_context(LR, Reg, LaneMask);
3372 report_context(S);
3373 return;
3374 }
3375 SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
3376 if (S.start != MBBStartIdx && S.start != VNI->def) {
3377 report("Live segment must begin at MBB entry or valno def", MBB);
3378 report_context(LR, Reg, LaneMask);
3379 report_context(S);
3380 }
3381
3382 const MachineBasicBlock *EndMBB =
3383 LiveInts->getMBBFromIndex(S.end.getPrevSlot());
3384 if (!EndMBB) {
3385 report("Bad end of live segment, no basic block", MF);
3386 report_context(LR, Reg, LaneMask);
3387 report_context(S);
3388 return;
3389 }
3390
3391 // Checks for non-live-out segments.
3392 if (S.end != LiveInts->getMBBEndIdx(EndMBB)) {
3393 // RegUnit intervals are allowed dead phis.
3394 if (!Reg.isVirtual() && VNI->isPHIDef() && S.start == VNI->def &&
3395 S.end == VNI->def.getDeadSlot())
3396 return;
3397
3398 // The live segment is ending inside EndMBB
3399 const MachineInstr *MI =
3401 if (!MI) {
3402 report("Live segment doesn't end at a valid instruction", EndMBB);
3403 report_context(LR, Reg, LaneMask);
3404 report_context(S);
3405 return;
3406 }
3407
3408 // The block slot must refer to a basic block boundary.
3409 if (S.end.isBlock()) {
3410 report("Live segment ends at B slot of an instruction", EndMBB);
3411 report_context(LR, Reg, LaneMask);
3412 report_context(S);
3413 }
3414
3415 if (S.end.isDead()) {
3416 // Segment ends on the dead slot.
3417 // That means there must be a dead def.
3418 if (!SlotIndex::isSameInstr(S.start, S.end)) {
3419 report("Live segment ending at dead slot spans instructions", EndMBB);
3420 report_context(LR, Reg, LaneMask);
3421 report_context(S);
3422 }
3423 }
3424
3425 // After tied operands are rewritten, a live segment can only end at an
3426 // early-clobber slot if it is being redefined by an early-clobber def.
3427 // TODO: Before tied operands are rewritten, a live segment can only end at
3428 // an early-clobber slot if the last use is tied to an early-clobber def.
3429 if (MF->getProperties().hasProperty(
3431 S.end.isEarlyClobber()) {
3432 if (I + 1 == LR.end() || (I + 1)->start != S.end) {
3433 report("Live segment ending at early clobber slot must be "
3434 "redefined by an EC def in the same instruction",
3435 EndMBB);
3436 report_context(LR, Reg, LaneMask);
3437 report_context(S);
3438 }
3439 }
3440
3441 // The following checks only apply to virtual registers. Physreg liveness
3442 // is too weird to check.
3443 if (Reg.isVirtual()) {
3444 // A live segment can end with either a redefinition, a kill flag on a
3445 // use, or a dead flag on a def.
3446 bool hasRead = false;
3447 bool hasSubRegDef = false;
3448 bool hasDeadDef = false;
3449 for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
3450 if (!MOI->isReg() || MOI->getReg() != Reg)
3451 continue;
3452 unsigned Sub = MOI->getSubReg();
3453 LaneBitmask SLM =
3454 Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub) : LaneBitmask::getAll();
3455 if (MOI->isDef()) {
3456 if (Sub != 0) {
3457 hasSubRegDef = true;
3458 // An operand %0:sub0 reads %0:sub1..n. Invert the lane
3459 // mask for subregister defs. Read-undef defs will be handled by
3460 // readsReg below.
3461 SLM = ~SLM;
3462 }
3463 if (MOI->isDead())
3464 hasDeadDef = true;
3465 }
3466 if (LaneMask.any() && (LaneMask & SLM).none())
3467 continue;
3468 if (MOI->readsReg())
3469 hasRead = true;
3470 }
3471 if (S.end.isDead()) {
3472 // Make sure that the corresponding machine operand for a "dead" live
3473 // range has the dead flag. We cannot perform this check for subregister
3474 // liveranges as partially dead values are allowed.
3475 if (LaneMask.none() && !hasDeadDef) {
3476 report(
3477 "Instruction ending live segment on dead slot has no dead flag",
3478 MI);
3479 report_context(LR, Reg, LaneMask);
3480 report_context(S);
3481 }
3482 } else {
3483 if (!hasRead) {
3484 // When tracking subregister liveness, the main range must start new
3485 // values on partial register writes, even if there is no read.
3486 if (!MRI->shouldTrackSubRegLiveness(Reg) || LaneMask.any() ||
3487 !hasSubRegDef) {
3488 report("Instruction ending live segment doesn't read the register",
3489 MI);
3490 report_context(LR, Reg, LaneMask);
3491 report_context(S);
3492 }
3493 }
3494 }
3495 }
3496 }
3497
3498 // Now check all the basic blocks in this live segment.
3500 // Is this live segment the beginning of a non-PHIDef VN?
3501 if (S.start == VNI->def && !VNI->isPHIDef()) {
3502 // Not live-in to any blocks.
3503 if (MBB == EndMBB)
3504 return;
3505 // Skip this block.
3506 ++MFI;
3507 }
3508
3510 if (LaneMask.any()) {
3511 LiveInterval &OwnerLI = LiveInts->getInterval(Reg);
3512 OwnerLI.computeSubRangeUndefs(Undefs, LaneMask, *MRI, *Indexes);
3513 }
3514
3515 while (true) {
3516 assert(LiveInts->isLiveInToMBB(LR, &*MFI));
3517 // We don't know how to track physregs into a landing pad.
3518 if (!Reg.isVirtual() && MFI->isEHPad()) {
3519 if (&*MFI == EndMBB)
3520 break;
3521 ++MFI;
3522 continue;
3523 }
3524
3525 // Is VNI a PHI-def in the current block?
3526 bool IsPHI = VNI->isPHIDef() &&
3527 VNI->def == LiveInts->getMBBStartIdx(&*MFI);
3528
3529 // Check that VNI is live-out of all predecessors.
3530 for (const MachineBasicBlock *Pred : MFI->predecessors()) {
3531 SlotIndex PEnd = LiveInts->getMBBEndIdx(Pred);
3532 // Predecessor of landing pad live-out on last call.
3533 if (MFI->isEHPad()) {
3534 for (const MachineInstr &MI : llvm::reverse(*Pred)) {
3535 if (MI.isCall()) {
3536 PEnd = Indexes->getInstructionIndex(MI).getBoundaryIndex();
3537 break;
3538 }
3539 }
3540 }
3541 const VNInfo *PVNI = LR.getVNInfoBefore(PEnd);
3542
3543 // All predecessors must have a live-out value. However for a phi
3544 // instruction with subregister intervals
3545 // only one of the subregisters (not necessarily the current one) needs to
3546 // be defined.
3547 if (!PVNI && (LaneMask.none() || !IsPHI)) {
3548 if (LiveRangeCalc::isJointlyDominated(Pred, Undefs, *Indexes))
3549 continue;
3550 report("Register not marked live out of predecessor", Pred);
3551 report_context(LR, Reg, LaneMask);
3552 report_context(*VNI);
3553 errs() << " live into " << printMBBReference(*MFI) << '@'
3554 << LiveInts->getMBBStartIdx(&*MFI) << ", not live before "
3555 << PEnd << '\n';
3556 continue;
3557 }
3558
3559 // Only PHI-defs can take different predecessor values.
3560 if (!IsPHI && PVNI != VNI) {
3561 report("Different value live out of predecessor", Pred);
3562 report_context(LR, Reg, LaneMask);
3563 errs() << "Valno #" << PVNI->id << " live out of "
3564 << printMBBReference(*Pred) << '@' << PEnd << "\nValno #"
3565 << VNI->id << " live into " << printMBBReference(*MFI) << '@'
3566 << LiveInts->getMBBStartIdx(&*MFI) << '\n';
3567 }
3568 }
3569 if (&*MFI == EndMBB)
3570 break;
3571 ++MFI;
3572 }
3573}
3574
3575void MachineVerifier::verifyLiveRange(const LiveRange &LR, Register Reg,
3576 LaneBitmask LaneMask) {
3577 for (const VNInfo *VNI : LR.valnos)
3578 verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
3579
3580 for (LiveRange::const_iterator I = LR.begin(), E = LR.end(); I != E; ++I)
3581 verifyLiveRangeSegment(LR, I, Reg, LaneMask);
3582}
3583
3584void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
3585 Register Reg = LI.reg();
3586 assert(Reg.isVirtual());
3587 verifyLiveRange(LI, Reg);
3588
3589 if (LI.hasSubRanges()) {
3591 LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
3592 for (const LiveInterval::SubRange &SR : LI.subranges()) {
3593 if ((Mask & SR.LaneMask).any()) {
3594 report("Lane masks of sub ranges overlap in live interval", MF);
3595 report_context(LI);
3596 }
3597 if ((SR.LaneMask & ~MaxMask).any()) {
3598 report("Subrange lanemask is invalid", MF);
3599 report_context(LI);
3600 }
3601 if (SR.empty()) {
3602 report("Subrange must not be empty", MF);
3603 report_context(SR, LI.reg(), SR.LaneMask);
3604 }
3605 Mask |= SR.LaneMask;
3606 verifyLiveRange(SR, LI.reg(), SR.LaneMask);
3607 if (!LI.covers(SR)) {
3608 report("A Subrange is not covered by the main range", MF);
3609 report_context(LI);
3610 }
3611 }
3612 }
3613
3614 // Check the LI only has one connected component.
3615 ConnectedVNInfoEqClasses ConEQ(*LiveInts);
3616 unsigned NumComp = ConEQ.Classify(LI);
3617 if (NumComp > 1) {
3618 report("Multiple connected components in live interval", MF);
3619 report_context(LI);
3620 for (unsigned comp = 0; comp != NumComp; ++comp) {
3621 errs() << comp << ": valnos";
3622 for (const VNInfo *I : LI.valnos)
3623 if (comp == ConEQ.getEqClass(I))
3624 errs() << ' ' << I->id;
3625 errs() << '\n';
3626 }
3627 }
3628}
3629
3630namespace {
3631
3632 // FrameSetup and FrameDestroy can have zero adjustment, so using a single
3633 // integer, we can't tell whether it is a FrameSetup or FrameDestroy if the
3634 // value is zero.
3635 // We use a bool plus an integer to capture the stack state.
3636 struct StackStateOfBB {
3637 StackStateOfBB() = default;
3638 StackStateOfBB(int EntryVal, int ExitVal, bool EntrySetup, bool ExitSetup) :
3639 EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
3640 ExitIsSetup(ExitSetup) {}
3641
3642 // Can be negative, which means we are setting up a frame.
3643 int EntryValue = 0;
3644 int ExitValue = 0;
3645 bool EntryIsSetup = false;
3646 bool ExitIsSetup = false;
3647 };
3648
3649} // end anonymous namespace
3650
3651/// Make sure on every path through the CFG, a FrameSetup <n> is always followed
3652/// by a FrameDestroy <n>, stack adjustments are identical on all
3653/// CFG edges to a merge point, and frame is destroyed at end of a return block.
3654void MachineVerifier::verifyStackFrame() {
3655 unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode();
3656 unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
3657 if (FrameSetupOpcode == ~0u && FrameDestroyOpcode == ~0u)
3658 return;
3659
3661 SPState.resize(MF->getNumBlockIDs());
3663
3664 // Visit the MBBs in DFS order.
3665 for (df_ext_iterator<const MachineFunction *,
3667 DFI = df_ext_begin(MF, Reachable), DFE = df_ext_end(MF, Reachable);
3668 DFI != DFE; ++DFI) {
3669 const MachineBasicBlock *MBB = *DFI;
3670
3671 StackStateOfBB BBState;
3672 // Check the exit state of the DFS stack predecessor.
3673 if (DFI.getPathLength() >= 2) {
3674 const MachineBasicBlock *StackPred = DFI.getPath(DFI.getPathLength() - 2);
3675 assert(Reachable.count(StackPred) &&
3676 "DFS stack predecessor is already visited.\n");
3677 BBState.EntryValue = SPState[StackPred->getNumber()].ExitValue;
3678 BBState.EntryIsSetup = SPState[StackPred->getNumber()].ExitIsSetup;
3679 BBState.ExitValue = BBState.EntryValue;
3680 BBState.ExitIsSetup = BBState.EntryIsSetup;
3681 }
3682
3683 if ((int)MBB->getCallFrameSize() != -BBState.EntryValue) {
3684 report("Call frame size on entry does not match value computed from "
3685 "predecessor",
3686 MBB);
3687 errs() << "Call frame size on entry " << MBB->getCallFrameSize()
3688 << " does not match value computed from predecessor "
3689 << -BBState.EntryValue << '\n';
3690 }
3691
3692 // Update stack state by checking contents of MBB.
3693 for (const auto &I : *MBB) {
3694 if (I.getOpcode() == FrameSetupOpcode) {
3695 if (BBState.ExitIsSetup)
3696 report("FrameSetup is after another FrameSetup", &I);
3697 BBState.ExitValue -= TII->getFrameTotalSize(I);
3698 BBState.ExitIsSetup = true;
3699 }
3700
3701 if (I.getOpcode() == FrameDestroyOpcode) {
3702 int Size = TII->getFrameTotalSize(I);
3703 if (!BBState.ExitIsSetup)
3704 report("FrameDestroy is not after a FrameSetup", &I);
3705 int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
3706 BBState.ExitValue;
3707 if (BBState.ExitIsSetup && AbsSPAdj != Size) {
3708 report("FrameDestroy <n> is after FrameSetup <m>", &I);
3709 errs() << "FrameDestroy <" << Size << "> is after FrameSetup <"
3710 << AbsSPAdj << ">.\n";
3711 }
3712 BBState.ExitValue += Size;
3713 BBState.ExitIsSetup = false;
3714 }
3715 }
3716 SPState[MBB->getNumber()] = BBState;
3717
3718 // Make sure the exit state of any predecessor is consistent with the entry
3719 // state.
3720 for (const MachineBasicBlock *Pred : MBB->predecessors()) {
3721 if (Reachable.count(Pred) &&
3722 (SPState[Pred->getNumber()].ExitValue != BBState.EntryValue ||
3723 SPState[Pred->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
3724 report("The exit stack state of a predecessor is inconsistent.", MBB);
3725 errs() << "Predecessor " << printMBBReference(*Pred)
3726 << " has exit state (" << SPState[Pred->getNumber()].ExitValue
3727 << ", " << SPState[Pred->getNumber()].ExitIsSetup << "), while "
3728 << printMBBReference(*MBB) << " has entry state ("
3729 << BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n";
3730 }
3731 }
3732
3733 // Make sure the entry state of any successor is consistent with the exit
3734 // state.
3735 for (const MachineBasicBlock *Succ : MBB->successors()) {
3736 if (Reachable.count(Succ) &&
3737 (SPState[Succ->getNumber()].EntryValue != BBState.ExitValue ||
3738 SPState[Succ->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
3739 report("The entry stack state of a successor is inconsistent.", MBB);
3740 errs() << "Successor " << printMBBReference(*Succ)
3741 << " has entry state (" << SPState[Succ->getNumber()].EntryValue
3742 << ", " << SPState[Succ->getNumber()].EntryIsSetup << "), while "
3743 << printMBBReference(*MBB) << " has exit state ("
3744 << BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n";
3745 }
3746 }
3747
3748 // Make sure a basic block with return ends with zero stack adjustment.
3749 if (!MBB->empty() && MBB->back().isReturn()) {
3750 if (BBState.ExitIsSetup)
3751 report("A return block ends with a FrameSetup.", MBB);
3752 if (BBState.ExitValue)
3753 report("A return block ends with a nonzero stack adjustment.", MBB);
3754 }
3755 }
3756}
unsigned SubReg
unsigned const MachineRegisterInfo * MRI
aarch64 promote const
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static bool isLoad(int Opcode)
static bool isStore(int Opcode)
This file implements the BitVector class.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseMap class.
This file defines the DenseSet and SmallDenseSet classes.
This file builds on the ADT/GraphTraits.h file to build generic depth first graph iterator.
std::string Name
uint64_t Size
bool End
Definition: ELF_riscv.cpp:480
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
const HexagonInstrInfo * TII
hexagon widen stores
IRTranslator LLVM IR MI
A common definition of LaneBitmask for use in TableGen and CodeGen.
Implement a low-level type suitable for MachineInstr level instruction selection.
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
This file declares the MIR specialization of the GenericConvergenceVerifier template.
unsigned const TargetRegisterInfo * TRI
unsigned Reg
static void verifyConvergenceControl(const MachineFunction &MF, MachineDomTree &DT, std::function< void(const Twine &Message)> FailureCB)
modulo schedule Modulo Schedule test pass
#define P(N)
ppc ctr loops verify
const char LLVMTargetMachineRef TM
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg)
This file contains some templates that are useful if you are working with the STL at all.
This file defines generic set operations that may be used on set's of different types,...
This file defines the SmallPtrSet class.
This file defines the SmallVector class.
static unsigned getSize(unsigned Kind)
const fltSemantics & getSemantics() const
Definition: APFloat.h:1303
Represent the analysis usage information of a pass.
AnalysisUsage & addUsedIfAvailable()
Add the specified Pass class to the set of analyses used by this pass.
void setPreservesAll()
Set by analyses that do not transform their input at all.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
LLVM Basic Block Representation.
Definition: BasicBlock.h:60
bool hasAddressTaken() const
Returns true if there are any uses of this basic block other than direct branches,...
Definition: BasicBlock.h:639
const Instruction * getTerminator() const LLVM_READONLY
Returns the terminator instruction if the block is well formed or null if the block is not well forme...
Definition: BasicBlock.h:220
bool test(unsigned Idx) const
Definition: BitVector.h:461
void clear()
clear - Removes all bits from the bitvector.
Definition: BitVector.h:335
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:140
size_type size() const
size - Returns the number of bits in this bitvector.
Definition: BitVector.h:159
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:267
const APFloat & getValueAPF() const
Definition: Constants.h:310
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
unsigned getBitWidth() const
getBitWidth - Return the scalar bitwidth of this constant.
Definition: Constants.h:147
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:220
Implements a dense probed hash-table based set.
Definition: DenseSet.h:271
Core dominator tree base class.
void recalculate(ParentType &Func)
recalculate - compute a dominator tree for the given function
Register getReg() const
Base class for user error types.
Definition: Error.h:352
A specialized PseudoSourceValue for holding FixedStack values, which must include a frame index.
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:311
void initialize(raw_ostream *OS, function_ref< void(const Twine &Message)> FailureCB, const FunctionT &F)
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
constexpr bool isScalableVector() const
Returns true if the LLT is a scalable vector.
Definition: LowLevelType.h:182
constexpr unsigned getScalarSizeInBits() const
Definition: LowLevelType.h:267
constexpr bool isScalar() const
Definition: LowLevelType.h:146
constexpr bool isValid() const
Definition: LowLevelType.h:145
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
Definition: LowLevelType.h:159
constexpr bool isVector() const
Definition: LowLevelType.h:148
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelType.h:193
constexpr bool isPointer() const
Definition: LowLevelType.h:149
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
Definition: LowLevelType.h:290
constexpr ElementCount getElementCount() const
Definition: LowLevelType.h:184
constexpr unsigned getAddressSpace() const
Definition: LowLevelType.h:280
constexpr bool isPointerOrPointerVector() const
Definition: LowLevelType.h:153
constexpr LLT getScalarType() const
Definition: LowLevelType.h:208
constexpr TypeSize getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
Definition: LowLevelType.h:203
A live range for subregisters.
Definition: LiveInterval.h:694
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:687
Register reg() const
Definition: LiveInterval.h:718
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Definition: LiveInterval.h:810
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:782
void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const
For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...
bool hasInterval(Register Reg) const
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
LiveRange * getCachedRegUnit(unsigned Unit)
Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn't...
LiveInterval & getInterval(Register Reg)
bool isNotInMIMap(const MachineInstr &Instr) const
Returns true if the specified machine instr has been removed or was never entered in the map.
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
void print(raw_ostream &O, const Module *=nullptr) const override
Implement the dump method.
Result of a LiveRange query.
Definition: LiveInterval.h:90
bool isDeadDef() const
Return true if this instruction has a dead def.
Definition: LiveInterval.h:117
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
Definition: LiveInterval.h:105
VNInfo * valueOut() const
Return the value leaving the instruction, if any.
Definition: LiveInterval.h:123
bool isKill() const
Return true if the live-in value is killed by this instruction.
Definition: LiveInterval.h:112
static LLVM_ATTRIBUTE_UNUSED bool isJointlyDominated(const MachineBasicBlock *MBB, ArrayRef< SlotIndex > Defs, const SlotIndexes &Indexes)
A diagnostic function to check if the end of the block MBB is jointly dominated by the blocks corresp...
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:157
VNInfo * getValNumInfo(unsigned ValNo)
getValNumInfo - Returns pointer to the specified val#.
Definition: LiveInterval.h:317
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:401
bool covers(const LiveRange &Other) const
Returns true if all segments of the Other live range are completely covered by this live range.
bool empty() const
Definition: LiveInterval.h:382
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
Definition: LiveInterval.h:542
iterator end()
Definition: LiveInterval.h:216
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarilly including Idx,...
Definition: LiveInterval.h:429
unsigned getNumValNums() const
Definition: LiveInterval.h:313
iterator begin()
Definition: LiveInterval.h:215
VNInfoList valnos
Definition: LiveInterval.h:204
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:421
LiveInterval & getInterval(int Slot)
Definition: LiveStacks.h:68
bool hasInterval(int Slot) const
Definition: LiveStacks.h:82
VarInfo & getVarInfo(Register Reg)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:780
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:237
ArrayRef< MCOperandInfo > operands() const
Definition: MCInstrDesc.h:239
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:248
bool isConvergent() const
Return true if this instruction is convergent.
Definition: MCInstrDesc.h:415
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
Definition: MCInstrDesc.h:418
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
Definition: MCInstrDesc.h:219
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:230
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:85
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:113
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:97
MCRegAliasIterator enumerates all registers aliasing Reg.
bool isValid() const
isValid - Returns true until all the operands have been visited.
bool isInlineAsmBrIndirectTarget() const
Returns true if this is the indirect dest of an INLINEASM_BR.
unsigned pred_size() const
bool isEHPad() const
Returns true if the block is a landing pad.
iterator_range< livein_iterator > liveins() const
iterator_range< iterator > phis()
Returns a range that iterates over the phis in the basic block.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
bool isIRBlockAddressTaken() const
Test whether this block is the target of an IR BlockAddress.
unsigned succ_size() const
BasicBlock * getAddressTakenIRBlock() const
Retrieves the BasicBlock which corresponds to this MachineBasicBlock.
bool isPredecessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a predecessor of this block.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
unsigned getCallFrameSize() const
Return the call frame size on entry to this basic block.
iterator_range< succ_iterator > successors()
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
iterator_range< pred_iterator > predecessors()
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool hasProperty(Property P) const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineFunctionProperties & getProperties() const
Get the function properties.
const MachineBasicBlock & front() const
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use.
void print(raw_ostream &OS, const SlotIndexes *=nullptr) const
print - Print out the MachineFunction in a format suitable for debugging to the specified stream.
BasicBlockListType::const_iterator const_iterator
Representation of each machine instruction.
Definition: MachineInstr.h:69
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:544
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:906
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:940
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:931
A description of a memory reference used in the backend.
const PseudoSourceValue * getPseudoValue() const
uint64_t getSize() const
Return the size in bytes of the memory reference.
AtomicOrdering getSuccessOrdering() const
Return the atomic ordering requirements for this memory operation.
uint64_t getSizeInBits() const
Return the size in bits of the memory reference.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
int64_t getImm() const
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
bool isImplicit() const
bool isIntrinsicID() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
ArrayRef< int > getShuffleMask() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isValidExcessOperand() const
Return true if this operand can validly be appended to an arbitrary operand list.
bool isShuffleMask() const
unsigned getCFIIndex() const
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
bool isEarlyClobber() const
Register getReg() const
getReg - Returns the register number.
bool isInternalRead() const
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
@ MO_CFIIndex
MCCFIInstruction index.
@ MO_RegisterMask
Mask of preserved registers.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_FrameIndex
Abstract Stack Frame Index.
@ MO_Register
Register operand.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:94
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:130
AnalysisType * getAnalysisIfAvailable() const
getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information tha...
Special value supplied for machine level alias analysis.
Holds all the information related to register banks.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getMaximumSize(unsigned RegBankID) const
Get the maximum size in bits that fits in the given register bank.
This class implements the register bank concept.
Definition: RegisterBank.h:28
const char * getName() const
Get a user friendly name of this register bank.
Definition: RegisterBank.h:49
unsigned getID() const
Get the identifier of this register bank.
Definition: RegisterBank.h:45
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
Definition: Register.h:77
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
static constexpr bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:95
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:68
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
Definition: SlotIndexes.h:179
bool isBlock() const
isBlock - Returns true if this is a block boundary slot.
Definition: SlotIndexes.h:212
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
Definition: SlotIndexes.h:245
bool isEarlyClobber() const
isEarlyClobber - Returns true if this is an early-clobber slot.
Definition: SlotIndexes.h:215
bool isRegister() const
isRegister - Returns true if this is a normal register use/def slot.
Definition: SlotIndexes.h:219
SlotIndex getBoundaryIndex() const
Returns the boundary index for associated with this index.
Definition: SlotIndexes.h:234
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
Definition: SlotIndexes.h:275
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
Definition: SlotIndexes.h:240
bool isDead() const
isDead - Returns true if this is a dead def kill slot.
Definition: SlotIndexes.h:222
SlotIndexes pass.
Definition: SlotIndexes.h:300
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
Definition: SlotIndexes.h:462
MBBIndexIterator MBBIndexBegin() const
Returns an iterator for the begin of the idx2MBBMap.
Definition: SlotIndexes.h:497
MBBIndexIterator MBBIndexEnd() const
Return an iterator for the end of the idx2MBBMap.
Definition: SlotIndexes.h:502
SmallVectorImpl< IdxMBBPair >::const_iterator MBBIndexIterator
Iterator over the idx2MBBMap (sorted pairs of slot index of basic block begin and basic block)
Definition: SlotIndexes.h:473
SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const
Returns the base index for the given instruction.
Definition: SlotIndexes.h:371
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
Definition: SlotIndexes.h:452
bool hasIndex(const MachineInstr &instr) const
Returns true if the given machine instr is mapped to an index, otherwise returns false.
Definition: SlotIndexes.h:366
size_type size() const
Definition: SmallPtrSet.h:94
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false.
Definition: SmallPtrSet.h:356
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
Definition: SmallPtrSet.h:360
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:342
iterator begin() const
Definition: SmallPtrSet.h:380
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:427
size_t size() const
Definition: SmallVector.h:91
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
void resize(size_type N)
Definition: SmallVector.h:651
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
Register getReg() const
MI-level Statepoint operands.
Definition: StackMaps.h:158
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetInstrInfo - Interface to description of machine instruction set.
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
VNInfo - Value Number Information.
Definition: LiveInterval.h:53
bool isUnused() const
Returns true if this value is unused.
Definition: LiveInterval.h:81
unsigned id
The ID number of this value.
Definition: LiveInterval.h:58
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:61
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
Definition: LiveInterval.h:78
LLVM Value Representation.
Definition: Value.h:74
std::pair< iterator, bool > insert(const ValueT &V)
Definition: DenseSet.h:206
constexpr bool isNonZero() const
Definition: TypeSize.h:158
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:171
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
Definition: TypeSize.h:168
self_iterator getIterator()
Definition: ilist_node.h:109
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
Definition: ilist_node.h:316
constexpr char Attrs[]
Key for Kernel::Metadata::mAttrs.
const CustomOperand< const MCSubtargetInfo & > Msg[]
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:121
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
AttributeList getAttributes(LLVMContext &C, ID id)
Return the attributes for an intrinsic.
@ OPERAND_REGISTER
Definition: MCInstrDesc.h:61
@ OPERAND_IMMEDIATE
Definition: MCInstrDesc.h:60
Reg
All possible values of the reg field in the ModR/M byte.
constexpr double e
Definition: MathExtras.h:31
NodeAddr< PhiNode * > Phi
Definition: RDFGraph.h:390
NodeAddr< DefNode * > Def
Definition: RDFGraph.h:384
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:227
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:236
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:329
@ Offset
Definition: DWP.cpp:456
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1731
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1689
@ SjLj
setjmp/longjmp based exceptions
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Definition: TargetOpcodes.h:30
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
void append_range(Container &C, Range &&R)
Wrapper function to append range R to container C.
Definition: STLExtras.h:2082
void set_subtract(S1Ty &S1, const S2Ty &S2)
set_subtract(A, B) - Compute A := A - B
Definition: SetOperations.h:82
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
Definition: LaneBitmask.h:92
bool isPreISelGenericOptimizationHint(unsigned Opcode)
Definition: TargetOpcodes.h:42
bool isScopedEHPersonality(EHPersonality Pers)
Returns true if this personality uses scope-style EH IR instructions: catchswitch,...
void initializeMachineVerifierPassPass(PassRegistry &)
void verifyMachineFunction(const std::string &Banner, const MachineFunction &MF)
auto reverse(ContainerTy &&C)
Definition: STLExtras.h:428
detail::ValueMatchesPoly< M > HasValue(M Matcher)
Definition: Error.h:221
df_ext_iterator< T, SetTy > df_ext_begin(const T &G, SetTy &S)
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1745
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
bool set_union(S1Ty &S1, const S2Ty &S2)
set_union(A, B) - Compute A := A u B, return whether A changed.
Definition: SetOperations.h:23
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
AtomicOrdering
Atomic ordering for LLVM's memory model.
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1858
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Definition: STLExtras.h:1888
df_ext_iterator< T, SetTy > df_ext_end(const T &G, SetTy &S)
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness.
Implement std::hash so that hash_code can be used in STL containers.
Definition: BitVector.h:858
static unsigned getSizeInBits(const fltSemantics &Sem)
Returns the size of the floating point number (in bits) in the given semantics.
Definition: APFloat.cpp:331
static constexpr LaneBitmask getAll()
Definition: LaneBitmask.h:82
constexpr bool none() const
Definition: LaneBitmask.h:52
constexpr bool any() const
Definition: LaneBitmask.h:53
static constexpr LaneBitmask getNone()
Definition: LaneBitmask.h:81
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:162
VarInfo - This represents the regions where a virtual register is live in the program.
Definition: LiveVariables.h:80
Pair of physical register and lane mask.