LLVM  9.0.0svn
MachineVerifier.cpp
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1 //===- MachineVerifier.cpp - Machine Code Verifier ------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Pass to verify generated machine code. The following is checked:
10 //
11 // Operand counts: All explicit operands must be present.
12 //
13 // Register classes: All physical and virtual register operands must be
14 // compatible with the register class required by the instruction descriptor.
15 //
16 // Register live intervals: Registers must be defined only once, and must be
17 // defined before use.
18 //
19 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
20 // command-line option -verify-machineinstrs, or by defining the environment
21 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
22 // the verifier errors.
23 //===----------------------------------------------------------------------===//
24 
25 #include "LiveRangeCalc.h"
26 #include "llvm/ADT/BitVector.h"
27 #include "llvm/ADT/DenseMap.h"
28 #include "llvm/ADT/DenseSet.h"
30 #include "llvm/ADT/STLExtras.h"
31 #include "llvm/ADT/SetOperations.h"
32 #include "llvm/ADT/SmallPtrSet.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/StringRef.h"
35 #include "llvm/ADT/Twine.h"
53 #include "llvm/CodeGen/StackMaps.h"
58 #include "llvm/IR/BasicBlock.h"
59 #include "llvm/IR/Function.h"
60 #include "llvm/IR/InlineAsm.h"
61 #include "llvm/IR/Instructions.h"
62 #include "llvm/MC/LaneBitmask.h"
63 #include "llvm/MC/MCAsmInfo.h"
64 #include "llvm/MC/MCInstrDesc.h"
65 #include "llvm/MC/MCRegisterInfo.h"
67 #include "llvm/Pass.h"
68 #include "llvm/Support/Casting.h"
74 #include <algorithm>
75 #include <cassert>
76 #include <cstddef>
77 #include <cstdint>
78 #include <iterator>
79 #include <string>
80 #include <utility>
81 
82 using namespace llvm;
83 
84 namespace {
85 
86  struct MachineVerifier {
87  MachineVerifier(Pass *pass, const char *b) : PASS(pass), Banner(b) {}
88 
89  unsigned verify(MachineFunction &MF);
90 
91  Pass *const PASS;
92  const char *Banner;
93  const MachineFunction *MF;
94  const TargetMachine *TM;
95  const TargetInstrInfo *TII;
96  const TargetRegisterInfo *TRI;
97  const MachineRegisterInfo *MRI;
98 
99  unsigned foundErrors;
100 
101  // Avoid querying the MachineFunctionProperties for each operand.
102  bool isFunctionRegBankSelected;
103  bool isFunctionSelected;
104 
105  using RegVector = SmallVector<unsigned, 16>;
106  using RegMaskVector = SmallVector<const uint32_t *, 4>;
107  using RegSet = DenseSet<unsigned>;
110 
111  const MachineInstr *FirstNonPHI;
112  const MachineInstr *FirstTerminator;
113  BlockSet FunctionBlocks;
114 
115  BitVector regsReserved;
116  RegSet regsLive;
117  RegVector regsDefined, regsDead, regsKilled;
118  RegMaskVector regMasks;
119 
120  SlotIndex lastIndex;
121 
122  // Add Reg and any sub-registers to RV
123  void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
124  RV.push_back(Reg);
126  for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
127  RV.push_back(*SubRegs);
128  }
129 
130  struct BBInfo {
131  // Is this MBB reachable from the MF entry point?
132  bool reachable = false;
133 
134  // Vregs that must be live in because they are used without being
135  // defined. Map value is the user.
136  RegMap vregsLiveIn;
137 
138  // Regs killed in MBB. They may be defined again, and will then be in both
139  // regsKilled and regsLiveOut.
140  RegSet regsKilled;
141 
142  // Regs defined in MBB and live out. Note that vregs passing through may
143  // be live out without being mentioned here.
144  RegSet regsLiveOut;
145 
146  // Vregs that pass through MBB untouched. This set is disjoint from
147  // regsKilled and regsLiveOut.
148  RegSet vregsPassed;
149 
150  // Vregs that must pass through MBB because they are needed by a successor
151  // block. This set is disjoint from regsLiveOut.
152  RegSet vregsRequired;
153 
154  // Set versions of block's predecessor and successor lists.
155  BlockSet Preds, Succs;
156 
157  BBInfo() = default;
158 
159  // Add register to vregsPassed if it belongs there. Return true if
160  // anything changed.
161  bool addPassed(unsigned Reg) {
163  return false;
164  if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
165  return false;
166  return vregsPassed.insert(Reg).second;
167  }
168 
169  // Same for a full set.
170  bool addPassed(const RegSet &RS) {
171  bool changed = false;
172  for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
173  if (addPassed(*I))
174  changed = true;
175  return changed;
176  }
177 
178  // Add register to vregsRequired if it belongs there. Return true if
179  // anything changed.
180  bool addRequired(unsigned Reg) {
182  return false;
183  if (regsLiveOut.count(Reg))
184  return false;
185  return vregsRequired.insert(Reg).second;
186  }
187 
188  // Same for a full set.
189  bool addRequired(const RegSet &RS) {
190  bool changed = false;
191  for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
192  if (addRequired(*I))
193  changed = true;
194  return changed;
195  }
196 
197  // Same for a full map.
198  bool addRequired(const RegMap &RM) {
199  bool changed = false;
200  for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
201  if (addRequired(I->first))
202  changed = true;
203  return changed;
204  }
205 
206  // Live-out registers are either in regsLiveOut or vregsPassed.
207  bool isLiveOut(unsigned Reg) const {
208  return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
209  }
210  };
211 
212  // Extra register info per MBB.
214 
215  bool isReserved(unsigned Reg) {
216  return Reg < regsReserved.size() && regsReserved.test(Reg);
217  }
218 
219  bool isAllocatable(unsigned Reg) const {
220  return Reg < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) &&
221  !regsReserved.test(Reg);
222  }
223 
224  // Analysis information if available
225  LiveVariables *LiveVars;
226  LiveIntervals *LiveInts;
227  LiveStacks *LiveStks;
228  SlotIndexes *Indexes;
229 
230  void visitMachineFunctionBefore();
231  void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
232  void visitMachineBundleBefore(const MachineInstr *MI);
233 
234  bool verifyVectorElementMatch(LLT Ty0, LLT Ty1, const MachineInstr *MI);
235  void verifyPreISelGenericInstruction(const MachineInstr *MI);
236  void visitMachineInstrBefore(const MachineInstr *MI);
237  void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
238  void visitMachineInstrAfter(const MachineInstr *MI);
239  void visitMachineBundleAfter(const MachineInstr *MI);
240  void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
241  void visitMachineFunctionAfter();
242 
243  void report(const char *msg, const MachineFunction *MF);
244  void report(const char *msg, const MachineBasicBlock *MBB);
245  void report(const char *msg, const MachineInstr *MI);
246  void report(const char *msg, const MachineOperand *MO, unsigned MONum,
247  LLT MOVRegType = LLT{});
248 
249  void report_context(const LiveInterval &LI) const;
250  void report_context(const LiveRange &LR, unsigned VRegUnit,
251  LaneBitmask LaneMask) const;
252  void report_context(const LiveRange::Segment &S) const;
253  void report_context(const VNInfo &VNI) const;
254  void report_context(SlotIndex Pos) const;
255  void report_context(MCPhysReg PhysReg) const;
256  void report_context_liverange(const LiveRange &LR) const;
257  void report_context_lanemask(LaneBitmask LaneMask) const;
258  void report_context_vreg(unsigned VReg) const;
259  void report_context_vreg_regunit(unsigned VRegOrUnit) const;
260 
261  void verifyInlineAsm(const MachineInstr *MI);
262 
263  void checkLiveness(const MachineOperand *MO, unsigned MONum);
264  void checkLivenessAtUse(const MachineOperand *MO, unsigned MONum,
265  SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit,
266  LaneBitmask LaneMask = LaneBitmask::getNone());
267  void checkLivenessAtDef(const MachineOperand *MO, unsigned MONum,
268  SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit,
269  bool SubRangeCheck = false,
270  LaneBitmask LaneMask = LaneBitmask::getNone());
271 
272  void markReachable(const MachineBasicBlock *MBB);
273  void calcRegsPassed();
274  void checkPHIOps(const MachineBasicBlock &MBB);
275 
276  void calcRegsRequired();
277  void verifyLiveVariables();
278  void verifyLiveIntervals();
279  void verifyLiveInterval(const LiveInterval&);
280  void verifyLiveRangeValue(const LiveRange&, const VNInfo*, unsigned,
281  LaneBitmask);
282  void verifyLiveRangeSegment(const LiveRange&,
283  const LiveRange::const_iterator I, unsigned,
284  LaneBitmask);
285  void verifyLiveRange(const LiveRange&, unsigned,
286  LaneBitmask LaneMask = LaneBitmask::getNone());
287 
288  void verifyStackFrame();
289 
290  void verifySlotIndexes() const;
291  void verifyProperties(const MachineFunction &MF);
292  };
293 
294  struct MachineVerifierPass : public MachineFunctionPass {
295  static char ID; // Pass ID, replacement for typeid
296 
297  const std::string Banner;
298 
299  MachineVerifierPass(std::string banner = std::string())
300  : MachineFunctionPass(ID), Banner(std::move(banner)) {
302  }
303 
304  void getAnalysisUsage(AnalysisUsage &AU) const override {
305  AU.setPreservesAll();
307  }
308 
309  bool runOnMachineFunction(MachineFunction &MF) override {
310  unsigned FoundErrors = MachineVerifier(this, Banner.c_str()).verify(MF);
311  if (FoundErrors)
312  report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
313  return false;
314  }
315  };
316 
317 } // end anonymous namespace
318 
319 char MachineVerifierPass::ID = 0;
320 
321 INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
322  "Verify generated machine code", false, false)
323 
325  return new MachineVerifierPass(Banner);
326 }
327 
328 bool MachineFunction::verify(Pass *p, const char *Banner, bool AbortOnErrors)
329  const {
330  MachineFunction &MF = const_cast<MachineFunction&>(*this);
331  unsigned FoundErrors = MachineVerifier(p, Banner).verify(MF);
332  if (AbortOnErrors && FoundErrors)
333  report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
334  return FoundErrors == 0;
335 }
336 
337 void MachineVerifier::verifySlotIndexes() const {
338  if (Indexes == nullptr)
339  return;
340 
341  // Ensure the IdxMBB list is sorted by slot indexes.
342  SlotIndex Last;
344  E = Indexes->MBBIndexEnd(); I != E; ++I) {
345  assert(!Last.isValid() || I->first > Last);
346  Last = I->first;
347  }
348 }
349 
350 void MachineVerifier::verifyProperties(const MachineFunction &MF) {
351  // If a pass has introduced virtual registers without clearing the
352  // NoVRegs property (or set it without allocating the vregs)
353  // then report an error.
354  if (MF.getProperties().hasProperty(
356  MRI->getNumVirtRegs())
357  report("Function has NoVRegs property but there are VReg operands", &MF);
358 }
359 
361  foundErrors = 0;
362 
363  this->MF = &MF;
364  TM = &MF.getTarget();
365  TII = MF.getSubtarget().getInstrInfo();
366  TRI = MF.getSubtarget().getRegisterInfo();
367  MRI = &MF.getRegInfo();
368 
369  const bool isFunctionFailedISel = MF.getProperties().hasProperty(
371 
372  // If we're mid-GlobalISel and we already triggered the fallback path then
373  // it's expected that the MIR is somewhat broken but that's ok since we'll
374  // reset it and clear the FailedISel attribute in ResetMachineFunctions.
375  if (isFunctionFailedISel)
376  return foundErrors;
377 
378  isFunctionRegBankSelected =
379  !isFunctionFailedISel &&
382  isFunctionSelected = !isFunctionFailedISel &&
385  LiveVars = nullptr;
386  LiveInts = nullptr;
387  LiveStks = nullptr;
388  Indexes = nullptr;
389  if (PASS) {
390  LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
391  // We don't want to verify LiveVariables if LiveIntervals is available.
392  if (!LiveInts)
393  LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
394  LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
395  Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
396  }
397 
398  verifySlotIndexes();
399 
400  verifyProperties(MF);
401 
402  visitMachineFunctionBefore();
403  for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
404  MFI!=MFE; ++MFI) {
405  visitMachineBasicBlockBefore(&*MFI);
406  // Keep track of the current bundle header.
407  const MachineInstr *CurBundle = nullptr;
408  // Do we expect the next instruction to be part of the same bundle?
409  bool InBundle = false;
410 
411  for (MachineBasicBlock::const_instr_iterator MBBI = MFI->instr_begin(),
412  MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) {
413  if (MBBI->getParent() != &*MFI) {
414  report("Bad instruction parent pointer", &*MFI);
415  errs() << "Instruction: " << *MBBI;
416  continue;
417  }
418 
419  // Check for consistent bundle flags.
420  if (InBundle && !MBBI->isBundledWithPred())
421  report("Missing BundledPred flag, "
422  "BundledSucc was set on predecessor",
423  &*MBBI);
424  if (!InBundle && MBBI->isBundledWithPred())
425  report("BundledPred flag is set, "
426  "but BundledSucc not set on predecessor",
427  &*MBBI);
428 
429  // Is this a bundle header?
430  if (!MBBI->isInsideBundle()) {
431  if (CurBundle)
432  visitMachineBundleAfter(CurBundle);
433  CurBundle = &*MBBI;
434  visitMachineBundleBefore(CurBundle);
435  } else if (!CurBundle)
436  report("No bundle header", &*MBBI);
437  visitMachineInstrBefore(&*MBBI);
438  for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
439  const MachineInstr &MI = *MBBI;
440  const MachineOperand &Op = MI.getOperand(I);
441  if (Op.getParent() != &MI) {
442  // Make sure to use correct addOperand / RemoveOperand / ChangeTo
443  // functions when replacing operands of a MachineInstr.
444  report("Instruction has operand with wrong parent set", &MI);
445  }
446 
447  visitMachineOperand(&Op, I);
448  }
449 
450  visitMachineInstrAfter(&*MBBI);
451 
452  // Was this the last bundled instruction?
453  InBundle = MBBI->isBundledWithSucc();
454  }
455  if (CurBundle)
456  visitMachineBundleAfter(CurBundle);
457  if (InBundle)
458  report("BundledSucc flag set on last instruction in block", &MFI->back());
459  visitMachineBasicBlockAfter(&*MFI);
460  }
461  visitMachineFunctionAfter();
462 
463  // Clean up.
464  regsLive.clear();
465  regsDefined.clear();
466  regsDead.clear();
467  regsKilled.clear();
468  regMasks.clear();
469  MBBInfoMap.clear();
470 
471  return foundErrors;
472 }
473 
474 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
475  assert(MF);
476  errs() << '\n';
477  if (!foundErrors++) {
478  if (Banner)
479  errs() << "# " << Banner << '\n';
480  if (LiveInts != nullptr)
481  LiveInts->print(errs());
482  else
483  MF->print(errs(), Indexes);
484  }
485  errs() << "*** Bad machine code: " << msg << " ***\n"
486  << "- function: " << MF->getName() << "\n";
487 }
488 
489 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
490  assert(MBB);
491  report(msg, MBB->getParent());
492  errs() << "- basic block: " << printMBBReference(*MBB) << ' '
493  << MBB->getName() << " (" << (const void *)MBB << ')';
494  if (Indexes)
495  errs() << " [" << Indexes->getMBBStartIdx(MBB)
496  << ';' << Indexes->getMBBEndIdx(MBB) << ')';
497  errs() << '\n';
498 }
499 
500 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
501  assert(MI);
502  report(msg, MI->getParent());
503  errs() << "- instruction: ";
504  if (Indexes && Indexes->hasIndex(*MI))
505  errs() << Indexes->getInstructionIndex(*MI) << '\t';
506  MI->print(errs(), /*SkipOpers=*/true);
507 }
508 
509 void MachineVerifier::report(const char *msg, const MachineOperand *MO,
510  unsigned MONum, LLT MOVRegType) {
511  assert(MO);
512  report(msg, MO->getParent());
513  errs() << "- operand " << MONum << ": ";
514  MO->print(errs(), MOVRegType, TRI);
515  errs() << "\n";
516 }
517 
518 void MachineVerifier::report_context(SlotIndex Pos) const {
519  errs() << "- at: " << Pos << '\n';
520 }
521 
522 void MachineVerifier::report_context(const LiveInterval &LI) const {
523  errs() << "- interval: " << LI << '\n';
524 }
525 
526 void MachineVerifier::report_context(const LiveRange &LR, unsigned VRegUnit,
527  LaneBitmask LaneMask) const {
528  report_context_liverange(LR);
529  report_context_vreg_regunit(VRegUnit);
530  if (LaneMask.any())
531  report_context_lanemask(LaneMask);
532 }
533 
534 void MachineVerifier::report_context(const LiveRange::Segment &S) const {
535  errs() << "- segment: " << S << '\n';
536 }
537 
538 void MachineVerifier::report_context(const VNInfo &VNI) const {
539  errs() << "- ValNo: " << VNI.id << " (def " << VNI.def << ")\n";
540 }
541 
542 void MachineVerifier::report_context_liverange(const LiveRange &LR) const {
543  errs() << "- liverange: " << LR << '\n';
544 }
545 
546 void MachineVerifier::report_context(MCPhysReg PReg) const {
547  errs() << "- p. register: " << printReg(PReg, TRI) << '\n';
548 }
549 
550 void MachineVerifier::report_context_vreg(unsigned VReg) const {
551  errs() << "- v. register: " << printReg(VReg, TRI) << '\n';
552 }
553 
554 void MachineVerifier::report_context_vreg_regunit(unsigned VRegOrUnit) const {
555  if (TargetRegisterInfo::isVirtualRegister(VRegOrUnit)) {
556  report_context_vreg(VRegOrUnit);
557  } else {
558  errs() << "- regunit: " << printRegUnit(VRegOrUnit, TRI) << '\n';
559  }
560 }
561 
562 void MachineVerifier::report_context_lanemask(LaneBitmask LaneMask) const {
563  errs() << "- lanemask: " << PrintLaneMask(LaneMask) << '\n';
564 }
565 
566 void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
567  BBInfo &MInfo = MBBInfoMap[MBB];
568  if (!MInfo.reachable) {
569  MInfo.reachable = true;
571  SuE = MBB->succ_end(); SuI != SuE; ++SuI)
572  markReachable(*SuI);
573  }
574 }
575 
576 void MachineVerifier::visitMachineFunctionBefore() {
577  lastIndex = SlotIndex();
578  regsReserved = MRI->reservedRegsFrozen() ? MRI->getReservedRegs()
579  : TRI->getReservedRegs(*MF);
580 
581  if (!MF->empty())
582  markReachable(&MF->front());
583 
584  // Build a set of the basic blocks in the function.
585  FunctionBlocks.clear();
586  for (const auto &MBB : *MF) {
587  FunctionBlocks.insert(&MBB);
588  BBInfo &MInfo = MBBInfoMap[&MBB];
589 
590  MInfo.Preds.insert(MBB.pred_begin(), MBB.pred_end());
591  if (MInfo.Preds.size() != MBB.pred_size())
592  report("MBB has duplicate entries in its predecessor list.", &MBB);
593 
594  MInfo.Succs.insert(MBB.succ_begin(), MBB.succ_end());
595  if (MInfo.Succs.size() != MBB.succ_size())
596  report("MBB has duplicate entries in its successor list.", &MBB);
597  }
598 
599  // Check that the register use lists are sane.
600  MRI->verifyUseLists();
601 
602  if (!MF->empty())
603  verifyStackFrame();
604 }
605 
606 // Does iterator point to a and b as the first two elements?
608  const MachineBasicBlock *a, const MachineBasicBlock *b) {
609  if (*i == a)
610  return *++i == b;
611  if (*i == b)
612  return *++i == a;
613  return false;
614 }
615 
616 void
617 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
618  FirstTerminator = nullptr;
619  FirstNonPHI = nullptr;
620 
621  if (!MF->getProperties().hasProperty(
623  // If this block has allocatable physical registers live-in, check that
624  // it is an entry block or landing pad.
625  for (const auto &LI : MBB->liveins()) {
626  if (isAllocatable(LI.PhysReg) && !MBB->isEHPad() &&
627  MBB->getIterator() != MBB->getParent()->begin()) {
628  report("MBB has allocatable live-in, but isn't entry or landing-pad.", MBB);
629  report_context(LI.PhysReg);
630  }
631  }
632  }
633 
634  // Count the number of landing pad successors.
635  SmallPtrSet<MachineBasicBlock*, 4> LandingPadSuccs;
637  E = MBB->succ_end(); I != E; ++I) {
638  if ((*I)->isEHPad())
639  LandingPadSuccs.insert(*I);
640  if (!FunctionBlocks.count(*I))
641  report("MBB has successor that isn't part of the function.", MBB);
642  if (!MBBInfoMap[*I].Preds.count(MBB)) {
643  report("Inconsistent CFG", MBB);
644  errs() << "MBB is not in the predecessor list of the successor "
645  << printMBBReference(*(*I)) << ".\n";
646  }
647  }
648 
649  // Check the predecessor list.
651  E = MBB->pred_end(); I != E; ++I) {
652  if (!FunctionBlocks.count(*I))
653  report("MBB has predecessor that isn't part of the function.", MBB);
654  if (!MBBInfoMap[*I].Succs.count(MBB)) {
655  report("Inconsistent CFG", MBB);
656  errs() << "MBB is not in the successor list of the predecessor "
657  << printMBBReference(*(*I)) << ".\n";
658  }
659  }
660 
661  const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
662  const BasicBlock *BB = MBB->getBasicBlock();
663  const Function &F = MF->getFunction();
664  if (LandingPadSuccs.size() > 1 &&
665  !(AsmInfo &&
667  BB && isa<SwitchInst>(BB->getTerminator())) &&
669  report("MBB has more than one landing pad successor", MBB);
670 
671  // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
672  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
674  if (!TII->analyzeBranch(*const_cast<MachineBasicBlock *>(MBB), TBB, FBB,
675  Cond)) {
676  // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
677  // check whether its answers match up with reality.
678  if (!TBB && !FBB) {
679  // Block falls through to its successor.
681  ++MBBI;
682  if (MBBI == MF->end()) {
683  // It's possible that the block legitimately ends with a noreturn
684  // call or an unreachable, in which case it won't actually fall
685  // out the bottom of the function.
686  } else if (MBB->succ_size() == LandingPadSuccs.size()) {
687  // It's possible that the block legitimately ends with a noreturn
688  // call or an unreachable, in which case it won't actually fall
689  // out of the block.
690  } else if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
691  report("MBB exits via unconditional fall-through but doesn't have "
692  "exactly one CFG successor!", MBB);
693  } else if (!MBB->isSuccessor(&*MBBI)) {
694  report("MBB exits via unconditional fall-through but its successor "
695  "differs from its CFG successor!", MBB);
696  }
697  if (!MBB->empty() && MBB->back().isBarrier() &&
698  !TII->isPredicated(MBB->back())) {
699  report("MBB exits via unconditional fall-through but ends with a "
700  "barrier instruction!", MBB);
701  }
702  if (!Cond.empty()) {
703  report("MBB exits via unconditional fall-through but has a condition!",
704  MBB);
705  }
706  } else if (TBB && !FBB && Cond.empty()) {
707  // Block unconditionally branches somewhere.
708  // If the block has exactly one successor, that happens to be a
709  // landingpad, accept it as valid control flow.
710  if (MBB->succ_size() != 1+LandingPadSuccs.size() &&
711  (MBB->succ_size() != 1 || LandingPadSuccs.size() != 1 ||
712  *MBB->succ_begin() != *LandingPadSuccs.begin())) {
713  report("MBB exits via unconditional branch but doesn't have "
714  "exactly one CFG successor!", MBB);
715  } else if (!MBB->isSuccessor(TBB)) {
716  report("MBB exits via unconditional branch but the CFG "
717  "successor doesn't match the actual successor!", MBB);
718  }
719  if (MBB->empty()) {
720  report("MBB exits via unconditional branch but doesn't contain "
721  "any instructions!", MBB);
722  } else if (!MBB->back().isBarrier()) {
723  report("MBB exits via unconditional branch but doesn't end with a "
724  "barrier instruction!", MBB);
725  } else if (!MBB->back().isTerminator()) {
726  report("MBB exits via unconditional branch but the branch isn't a "
727  "terminator instruction!", MBB);
728  }
729  } else if (TBB && !FBB && !Cond.empty()) {
730  // Block conditionally branches somewhere, otherwise falls through.
732  ++MBBI;
733  if (MBBI == MF->end()) {
734  report("MBB conditionally falls through out of function!", MBB);
735  } else if (MBB->succ_size() == 1) {
736  // A conditional branch with only one successor is weird, but allowed.
737  if (&*MBBI != TBB)
738  report("MBB exits via conditional branch/fall-through but only has "
739  "one CFG successor!", MBB);
740  else if (TBB != *MBB->succ_begin())
741  report("MBB exits via conditional branch/fall-through but the CFG "
742  "successor don't match the actual successor!", MBB);
743  } else if (MBB->succ_size() != 2) {
744  report("MBB exits via conditional branch/fall-through but doesn't have "
745  "exactly two CFG successors!", MBB);
746  } else if (!matchPair(MBB->succ_begin(), TBB, &*MBBI)) {
747  report("MBB exits via conditional branch/fall-through but the CFG "
748  "successors don't match the actual successors!", MBB);
749  }
750  if (MBB->empty()) {
751  report("MBB exits via conditional branch/fall-through but doesn't "
752  "contain any instructions!", MBB);
753  } else if (MBB->back().isBarrier()) {
754  report("MBB exits via conditional branch/fall-through but ends with a "
755  "barrier instruction!", MBB);
756  } else if (!MBB->back().isTerminator()) {
757  report("MBB exits via conditional branch/fall-through but the branch "
758  "isn't a terminator instruction!", MBB);
759  }
760  } else if (TBB && FBB) {
761  // Block conditionally branches somewhere, otherwise branches
762  // somewhere else.
763  if (MBB->succ_size() == 1) {
764  // A conditional branch with only one successor is weird, but allowed.
765  if (FBB != TBB)
766  report("MBB exits via conditional branch/branch through but only has "
767  "one CFG successor!", MBB);
768  else if (TBB != *MBB->succ_begin())
769  report("MBB exits via conditional branch/branch through but the CFG "
770  "successor don't match the actual successor!", MBB);
771  } else if (MBB->succ_size() != 2) {
772  report("MBB exits via conditional branch/branch but doesn't have "
773  "exactly two CFG successors!", MBB);
774  } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
775  report("MBB exits via conditional branch/branch but the CFG "
776  "successors don't match the actual successors!", MBB);
777  }
778  if (MBB->empty()) {
779  report("MBB exits via conditional branch/branch but doesn't "
780  "contain any instructions!", MBB);
781  } else if (!MBB->back().isBarrier()) {
782  report("MBB exits via conditional branch/branch but doesn't end with a "
783  "barrier instruction!", MBB);
784  } else if (!MBB->back().isTerminator()) {
785  report("MBB exits via conditional branch/branch but the branch "
786  "isn't a terminator instruction!", MBB);
787  }
788  if (Cond.empty()) {
789  report("MBB exits via conditional branch/branch but there's no "
790  "condition!", MBB);
791  }
792  } else {
793  report("AnalyzeBranch returned invalid data!", MBB);
794  }
795  }
796 
797  regsLive.clear();
798  if (MRI->tracksLiveness()) {
799  for (const auto &LI : MBB->liveins()) {
800  if (!TargetRegisterInfo::isPhysicalRegister(LI.PhysReg)) {
801  report("MBB live-in list contains non-physical register", MBB);
802  continue;
803  }
804  for (MCSubRegIterator SubRegs(LI.PhysReg, TRI, /*IncludeSelf=*/true);
805  SubRegs.isValid(); ++SubRegs)
806  regsLive.insert(*SubRegs);
807  }
808  }
809 
810  const MachineFrameInfo &MFI = MF->getFrameInfo();
811  BitVector PR = MFI.getPristineRegs(*MF);
812  for (unsigned I : PR.set_bits()) {
813  for (MCSubRegIterator SubRegs(I, TRI, /*IncludeSelf=*/true);
814  SubRegs.isValid(); ++SubRegs)
815  regsLive.insert(*SubRegs);
816  }
817 
818  regsKilled.clear();
819  regsDefined.clear();
820 
821  if (Indexes)
822  lastIndex = Indexes->getMBBStartIdx(MBB);
823 }
824 
825 // This function gets called for all bundle headers, including normal
826 // stand-alone unbundled instructions.
827 void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
828  if (Indexes && Indexes->hasIndex(*MI)) {
829  SlotIndex idx = Indexes->getInstructionIndex(*MI);
830  if (!(idx > lastIndex)) {
831  report("Instruction index out of order", MI);
832  errs() << "Last instruction was at " << lastIndex << '\n';
833  }
834  lastIndex = idx;
835  }
836 
837  // Ensure non-terminators don't follow terminators.
838  // Ignore predicated terminators formed by if conversion.
839  // FIXME: If conversion shouldn't need to violate this rule.
840  if (MI->isTerminator() && !TII->isPredicated(*MI)) {
841  if (!FirstTerminator)
842  FirstTerminator = MI;
843  } else if (FirstTerminator) {
844  report("Non-terminator instruction after the first terminator", MI);
845  errs() << "First terminator was:\t" << *FirstTerminator;
846  }
847 }
848 
849 // The operands on an INLINEASM instruction must follow a template.
850 // Verify that the flag operands make sense.
851 void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) {
852  // The first two operands on INLINEASM are the asm string and global flags.
853  if (MI->getNumOperands() < 2) {
854  report("Too few operands on inline asm", MI);
855  return;
856  }
857  if (!MI->getOperand(0).isSymbol())
858  report("Asm string must be an external symbol", MI);
859  if (!MI->getOperand(1).isImm())
860  report("Asm flags must be an immediate", MI);
861  // Allowed flags are Extra_HasSideEffects = 1, Extra_IsAlignStack = 2,
862  // Extra_AsmDialect = 4, Extra_MayLoad = 8, and Extra_MayStore = 16,
863  // and Extra_IsConvergent = 32.
864  if (!isUInt<6>(MI->getOperand(1).getImm()))
865  report("Unknown asm flags", &MI->getOperand(1), 1);
866 
867  static_assert(InlineAsm::MIOp_FirstOperand == 2, "Asm format changed");
868 
869  unsigned OpNo = InlineAsm::MIOp_FirstOperand;
870  unsigned NumOps;
871  for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
872  const MachineOperand &MO = MI->getOperand(OpNo);
873  // There may be implicit ops after the fixed operands.
874  if (!MO.isImm())
875  break;
876  NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
877  }
878 
879  if (OpNo > MI->getNumOperands())
880  report("Missing operands in last group", MI);
881 
882  // An optional MDNode follows the groups.
883  if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata())
884  ++OpNo;
885 
886  // All trailing operands must be implicit registers.
887  for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) {
888  const MachineOperand &MO = MI->getOperand(OpNo);
889  if (!MO.isReg() || !MO.isImplicit())
890  report("Expected implicit register after groups", &MO, OpNo);
891  }
892 }
893 
894 /// Check that types are consistent when two operands need to have the same
895 /// number of vector elements.
896 /// \return true if the types are valid.
897 bool MachineVerifier::verifyVectorElementMatch(LLT Ty0, LLT Ty1,
898  const MachineInstr *MI) {
899  if (Ty0.isVector() != Ty1.isVector()) {
900  report("operand types must be all-vector or all-scalar", MI);
901  // Generally we try to report as many issues as possible at once, but in
902  // this case it's not clear what should we be comparing the size of the
903  // scalar with: the size of the whole vector or its lane. Instead of
904  // making an arbitrary choice and emitting not so helpful message, let's
905  // avoid the extra noise and stop here.
906  return false;
907  }
908 
909  if (Ty0.isVector() && Ty0.getNumElements() != Ty1.getNumElements()) {
910  report("operand types must preserve number of vector elements", MI);
911  return false;
912  }
913 
914  return true;
915 }
916 
917 void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
918  if (isFunctionSelected)
919  report("Unexpected generic instruction in a Selected function", MI);
920 
921  const MCInstrDesc &MCID = MI->getDesc();
922  unsigned NumOps = MI->getNumOperands();
923 
924  // Check types.
925  SmallVector<LLT, 4> Types;
926  for (unsigned I = 0, E = std::min(MCID.getNumOperands(), NumOps);
927  I != E; ++I) {
928  if (!MCID.OpInfo[I].isGenericType())
929  continue;
930  // Generic instructions specify type equality constraints between some of
931  // their operands. Make sure these are consistent.
932  size_t TypeIdx = MCID.OpInfo[I].getGenericTypeIndex();
933  Types.resize(std::max(TypeIdx + 1, Types.size()));
934 
935  const MachineOperand *MO = &MI->getOperand(I);
936  if (!MO->isReg()) {
937  report("generic instruction must use register operands", MI);
938  continue;
939  }
940 
941  LLT OpTy = MRI->getType(MO->getReg());
942  // Don't report a type mismatch if there is no actual mismatch, only a
943  // type missing, to reduce noise:
944  if (OpTy.isValid()) {
945  // Only the first valid type for a type index will be printed: don't
946  // overwrite it later so it's always clear which type was expected:
947  if (!Types[TypeIdx].isValid())
948  Types[TypeIdx] = OpTy;
949  else if (Types[TypeIdx] != OpTy)
950  report("Type mismatch in generic instruction", MO, I, OpTy);
951  } else {
952  // Generic instructions must have types attached to their operands.
953  report("Generic instruction is missing a virtual register type", MO, I);
954  }
955  }
956 
957  // Generic opcodes must not have physical register operands.
958  for (unsigned I = 0; I < MI->getNumOperands(); ++I) {
959  const MachineOperand *MO = &MI->getOperand(I);
961  report("Generic instruction cannot have physical register", MO, I);
962  }
963 
964  // Avoid out of bounds in checks below. This was already reported earlier.
965  if (MI->getNumOperands() < MCID.getNumOperands())
966  return;
967 
969  if (!TII->verifyInstruction(*MI, ErrorInfo))
970  report(ErrorInfo.data(), MI);
971 
972  // Verify properties of various specific instruction types
973  switch (MI->getOpcode()) {
974  case TargetOpcode::G_CONSTANT:
975  case TargetOpcode::G_FCONSTANT: {
976  if (MI->getNumOperands() < MCID.getNumOperands())
977  break;
978 
979  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
980  if (DstTy.isVector())
981  report("Instruction cannot use a vector result type", MI);
982 
983  if (MI->getOpcode() == TargetOpcode::G_CONSTANT) {
984  if (!MI->getOperand(1).isCImm()) {
985  report("G_CONSTANT operand must be cimm", MI);
986  break;
987  }
988 
989  const ConstantInt *CI = MI->getOperand(1).getCImm();
990  if (CI->getBitWidth() != DstTy.getSizeInBits())
991  report("inconsistent constant size", MI);
992  } else {
993  if (!MI->getOperand(1).isFPImm()) {
994  report("G_FCONSTANT operand must be fpimm", MI);
995  break;
996  }
997  const ConstantFP *CF = MI->getOperand(1).getFPImm();
998 
1000  DstTy.getSizeInBits()) {
1001  report("inconsistent constant size", MI);
1002  }
1003  }
1004 
1005  break;
1006  }
1007  case TargetOpcode::G_LOAD:
1008  case TargetOpcode::G_STORE:
1009  case TargetOpcode::G_ZEXTLOAD:
1010  case TargetOpcode::G_SEXTLOAD: {
1011  LLT ValTy = MRI->getType(MI->getOperand(0).getReg());
1012  LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
1013  if (!PtrTy.isPointer())
1014  report("Generic memory instruction must access a pointer", MI);
1015 
1016  // Generic loads and stores must have a single MachineMemOperand
1017  // describing that access.
1018  if (!MI->hasOneMemOperand()) {
1019  report("Generic instruction accessing memory must have one mem operand",
1020  MI);
1021  } else {
1022  const MachineMemOperand &MMO = **MI->memoperands_begin();
1023  if (MI->getOpcode() == TargetOpcode::G_ZEXTLOAD ||
1024  MI->getOpcode() == TargetOpcode::G_SEXTLOAD) {
1025  if (MMO.getSizeInBits() >= ValTy.getSizeInBits())
1026  report("Generic extload must have a narrower memory type", MI);
1027  } else if (MI->getOpcode() == TargetOpcode::G_LOAD) {
1028  if (MMO.getSize() > ValTy.getSizeInBytes())
1029  report("load memory size cannot exceed result size", MI);
1030  } else if (MI->getOpcode() == TargetOpcode::G_STORE) {
1031  if (ValTy.getSizeInBytes() < MMO.getSize())
1032  report("store memory size cannot exceed value size", MI);
1033  }
1034  }
1035 
1036  break;
1037  }
1038  case TargetOpcode::G_PHI: {
1039  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1040  if (!DstTy.isValid() ||
1041  !std::all_of(MI->operands_begin() + 1, MI->operands_end(),
1042  [this, &DstTy](const MachineOperand &MO) {
1043  if (!MO.isReg())
1044  return true;
1045  LLT Ty = MRI->getType(MO.getReg());
1046  if (!Ty.isValid() || (Ty != DstTy))
1047  return false;
1048  return true;
1049  }))
1050  report("Generic Instruction G_PHI has operands with incompatible/missing "
1051  "types",
1052  MI);
1053  break;
1054  }
1055  case TargetOpcode::G_BITCAST: {
1056  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1057  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1058  if (!DstTy.isValid() || !SrcTy.isValid())
1059  break;
1060 
1061  if (SrcTy.isPointer() != DstTy.isPointer())
1062  report("bitcast cannot convert between pointers and other types", MI);
1063 
1064  if (SrcTy.getSizeInBits() != DstTy.getSizeInBits())
1065  report("bitcast sizes must match", MI);
1066  break;
1067  }
1068  case TargetOpcode::G_INTTOPTR:
1069  case TargetOpcode::G_PTRTOINT:
1070  case TargetOpcode::G_ADDRSPACE_CAST: {
1071  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1072  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1073  if (!DstTy.isValid() || !SrcTy.isValid())
1074  break;
1075 
1076  verifyVectorElementMatch(DstTy, SrcTy, MI);
1077 
1078  DstTy = DstTy.getScalarType();
1079  SrcTy = SrcTy.getScalarType();
1080 
1081  if (MI->getOpcode() == TargetOpcode::G_INTTOPTR) {
1082  if (!DstTy.isPointer())
1083  report("inttoptr result type must be a pointer", MI);
1084  if (SrcTy.isPointer())
1085  report("inttoptr source type must not be a pointer", MI);
1086  } else if (MI->getOpcode() == TargetOpcode::G_PTRTOINT) {
1087  if (!SrcTy.isPointer())
1088  report("ptrtoint source type must be a pointer", MI);
1089  if (DstTy.isPointer())
1090  report("ptrtoint result type must not be a pointer", MI);
1091  } else {
1092  assert(MI->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST);
1093  if (!SrcTy.isPointer() || !DstTy.isPointer())
1094  report("addrspacecast types must be pointers", MI);
1095  else {
1096  if (SrcTy.getAddressSpace() == DstTy.getAddressSpace())
1097  report("addrspacecast must convert different address spaces", MI);
1098  }
1099  }
1100 
1101  break;
1102  }
1103  case TargetOpcode::G_GEP: {
1104  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1105  LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
1106  LLT OffsetTy = MRI->getType(MI->getOperand(2).getReg());
1107  if (!DstTy.isValid() || !PtrTy.isValid() || !OffsetTy.isValid())
1108  break;
1109 
1110  if (!PtrTy.getScalarType().isPointer())
1111  report("gep first operand must be a pointer", MI);
1112 
1113  if (OffsetTy.getScalarType().isPointer())
1114  report("gep offset operand must not be a pointer", MI);
1115 
1116  // TODO: Is the offset allowed to be a scalar with a vector?
1117  break;
1118  }
1119  case TargetOpcode::G_SEXT:
1120  case TargetOpcode::G_ZEXT:
1121  case TargetOpcode::G_ANYEXT:
1122  case TargetOpcode::G_TRUNC:
1123  case TargetOpcode::G_FPEXT:
1124  case TargetOpcode::G_FPTRUNC: {
1125  // Number of operands and presense of types is already checked (and
1126  // reported in case of any issues), so no need to report them again. As
1127  // we're trying to report as many issues as possible at once, however, the
1128  // instructions aren't guaranteed to have the right number of operands or
1129  // types attached to them at this point
1130  assert(MCID.getNumOperands() == 2 && "Expected 2 operands G_*{EXT,TRUNC}");
1131  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1132  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1133  if (!DstTy.isValid() || !SrcTy.isValid())
1134  break;
1135 
1136  LLT DstElTy = DstTy.getScalarType();
1137  LLT SrcElTy = SrcTy.getScalarType();
1138  if (DstElTy.isPointer() || SrcElTy.isPointer())
1139  report("Generic extend/truncate can not operate on pointers", MI);
1140 
1141  verifyVectorElementMatch(DstTy, SrcTy, MI);
1142 
1143  unsigned DstSize = DstElTy.getSizeInBits();
1144  unsigned SrcSize = SrcElTy.getSizeInBits();
1145  switch (MI->getOpcode()) {
1146  default:
1147  if (DstSize <= SrcSize)
1148  report("Generic extend has destination type no larger than source", MI);
1149  break;
1150  case TargetOpcode::G_TRUNC:
1151  case TargetOpcode::G_FPTRUNC:
1152  if (DstSize >= SrcSize)
1153  report("Generic truncate has destination type no smaller than source",
1154  MI);
1155  break;
1156  }
1157  break;
1158  }
1159  case TargetOpcode::G_SELECT: {
1160  LLT SelTy = MRI->getType(MI->getOperand(0).getReg());
1161  LLT CondTy = MRI->getType(MI->getOperand(1).getReg());
1162  if (!SelTy.isValid() || !CondTy.isValid())
1163  break;
1164 
1165  // Scalar condition select on a vector is valid.
1166  if (CondTy.isVector())
1167  verifyVectorElementMatch(SelTy, CondTy, MI);
1168  break;
1169  }
1170  case TargetOpcode::G_MERGE_VALUES: {
1171  // G_MERGE_VALUES should only be used to merge scalars into a larger scalar,
1172  // e.g. s2N = MERGE sN, sN
1173  // Merging multiple scalars into a vector is not allowed, should use
1174  // G_BUILD_VECTOR for that.
1175  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1176  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1177  if (DstTy.isVector() || SrcTy.isVector())
1178  report("G_MERGE_VALUES cannot operate on vectors", MI);
1179  break;
1180  }
1181  case TargetOpcode::G_UNMERGE_VALUES: {
1182  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1183  LLT SrcTy = MRI->getType(MI->getOperand(MI->getNumOperands()-1).getReg());
1184  // For now G_UNMERGE can split vectors.
1185  for (unsigned i = 0; i < MI->getNumOperands()-1; ++i) {
1186  if (MRI->getType(MI->getOperand(i).getReg()) != DstTy)
1187  report("G_UNMERGE_VALUES destination types do not match", MI);
1188  }
1189  if (SrcTy.getSizeInBits() !=
1190  (DstTy.getSizeInBits() * (MI->getNumOperands() - 1))) {
1191  report("G_UNMERGE_VALUES source operand does not cover dest operands",
1192  MI);
1193  }
1194  break;
1195  }
1196  case TargetOpcode::G_BUILD_VECTOR: {
1197  // Source types must be scalars, dest type a vector. Total size of scalars
1198  // must match the dest vector size.
1199  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1200  LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1201  if (!DstTy.isVector() || SrcEltTy.isVector()) {
1202  report("G_BUILD_VECTOR must produce a vector from scalar operands", MI);
1203  break;
1204  }
1205 
1206  if (DstTy.getElementType() != SrcEltTy)
1207  report("G_BUILD_VECTOR result element type must match source type", MI);
1208 
1209  if (DstTy.getNumElements() != MI->getNumOperands() - 1)
1210  report("G_BUILD_VECTOR must have an operand for each elemement", MI);
1211 
1212  for (unsigned i = 2; i < MI->getNumOperands(); ++i) {
1213  if (MRI->getType(MI->getOperand(1).getReg()) !=
1214  MRI->getType(MI->getOperand(i).getReg()))
1215  report("G_BUILD_VECTOR source operand types are not homogeneous", MI);
1216  }
1217 
1218  break;
1219  }
1220  case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1221  // Source types must be scalars, dest type a vector. Scalar types must be
1222  // larger than the dest vector elt type, as this is a truncating operation.
1223  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1224  LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1225  if (!DstTy.isVector() || SrcEltTy.isVector())
1226  report("G_BUILD_VECTOR_TRUNC must produce a vector from scalar operands",
1227  MI);
1228  for (unsigned i = 2; i < MI->getNumOperands(); ++i) {
1229  if (MRI->getType(MI->getOperand(1).getReg()) !=
1230  MRI->getType(MI->getOperand(i).getReg()))
1231  report("G_BUILD_VECTOR_TRUNC source operand types are not homogeneous",
1232  MI);
1233  }
1234  if (SrcEltTy.getSizeInBits() <= DstTy.getElementType().getSizeInBits())
1235  report("G_BUILD_VECTOR_TRUNC source operand types are not larger than "
1236  "dest elt type",
1237  MI);
1238  break;
1239  }
1240  case TargetOpcode::G_CONCAT_VECTORS: {
1241  // Source types should be vectors, and total size should match the dest
1242  // vector size.
1243  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1244  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1245  if (!DstTy.isVector() || !SrcTy.isVector())
1246  report("G_CONCAT_VECTOR requires vector source and destination operands",
1247  MI);
1248  for (unsigned i = 2; i < MI->getNumOperands(); ++i) {
1249  if (MRI->getType(MI->getOperand(1).getReg()) !=
1250  MRI->getType(MI->getOperand(i).getReg()))
1251  report("G_CONCAT_VECTOR source operand types are not homogeneous", MI);
1252  }
1253  if (DstTy.getNumElements() !=
1254  SrcTy.getNumElements() * (MI->getNumOperands() - 1))
1255  report("G_CONCAT_VECTOR num dest and source elements should match", MI);
1256  break;
1257  }
1258  case TargetOpcode::G_ICMP:
1259  case TargetOpcode::G_FCMP: {
1260  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1261  LLT SrcTy = MRI->getType(MI->getOperand(2).getReg());
1262 
1263  if ((DstTy.isVector() != SrcTy.isVector()) ||
1264  (DstTy.isVector() && DstTy.getNumElements() != SrcTy.getNumElements()))
1265  report("Generic vector icmp/fcmp must preserve number of lanes", MI);
1266 
1267  break;
1268  }
1269  case TargetOpcode::G_EXTRACT: {
1270  const MachineOperand &SrcOp = MI->getOperand(1);
1271  if (!SrcOp.isReg()) {
1272  report("extract source must be a register", MI);
1273  break;
1274  }
1275 
1276  const MachineOperand &OffsetOp = MI->getOperand(2);
1277  if (!OffsetOp.isImm()) {
1278  report("extract offset must be a constant", MI);
1279  break;
1280  }
1281 
1282  unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1283  unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
1284  if (SrcSize == DstSize)
1285  report("extract source must be larger than result", MI);
1286 
1287  if (DstSize + OffsetOp.getImm() > SrcSize)
1288  report("extract reads past end of register", MI);
1289  break;
1290  }
1291  case TargetOpcode::G_INSERT: {
1292  const MachineOperand &SrcOp = MI->getOperand(2);
1293  if (!SrcOp.isReg()) {
1294  report("insert source must be a register", MI);
1295  break;
1296  }
1297 
1298  const MachineOperand &OffsetOp = MI->getOperand(3);
1299  if (!OffsetOp.isImm()) {
1300  report("insert offset must be a constant", MI);
1301  break;
1302  }
1303 
1304  unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1305  unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
1306 
1307  if (DstSize <= SrcSize)
1308  report("inserted size must be smaller than total register", MI);
1309 
1310  if (SrcSize + OffsetOp.getImm() > DstSize)
1311  report("insert writes past end of register", MI);
1312 
1313  break;
1314  }
1315  default:
1316  break;
1317  }
1318 }
1319 
1320 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
1321  const MCInstrDesc &MCID = MI->getDesc();
1322  if (MI->getNumOperands() < MCID.getNumOperands()) {
1323  report("Too few operands", MI);
1324  errs() << MCID.getNumOperands() << " operands expected, but "
1325  << MI->getNumOperands() << " given.\n";
1326  }
1327 
1328  if (MI->isPHI()) {
1329  if (MF->getProperties().hasProperty(
1331  report("Found PHI instruction with NoPHIs property set", MI);
1332 
1333  if (FirstNonPHI)
1334  report("Found PHI instruction after non-PHI", MI);
1335  } else if (FirstNonPHI == nullptr)
1336  FirstNonPHI = MI;
1337 
1338  // Check the tied operands.
1339  if (MI->isInlineAsm())
1340  verifyInlineAsm(MI);
1341 
1342  // Check the MachineMemOperands for basic consistency.
1344  E = MI->memoperands_end();
1345  I != E; ++I) {
1346  if ((*I)->isLoad() && !MI->mayLoad())
1347  report("Missing mayLoad flag", MI);
1348  if ((*I)->isStore() && !MI->mayStore())
1349  report("Missing mayStore flag", MI);
1350  }
1351 
1352  // Debug values must not have a slot index.
1353  // Other instructions must have one, unless they are inside a bundle.
1354  if (LiveInts) {
1355  bool mapped = !LiveInts->isNotInMIMap(*MI);
1356  if (MI->isDebugInstr()) {
1357  if (mapped)
1358  report("Debug instruction has a slot index", MI);
1359  } else if (MI->isInsideBundle()) {
1360  if (mapped)
1361  report("Instruction inside bundle has a slot index", MI);
1362  } else {
1363  if (!mapped)
1364  report("Missing slot index", MI);
1365  }
1366  }
1367 
1368  if (isPreISelGenericOpcode(MCID.getOpcode())) {
1369  verifyPreISelGenericInstruction(MI);
1370  return;
1371  }
1372 
1374  if (!TII->verifyInstruction(*MI, ErrorInfo))
1375  report(ErrorInfo.data(), MI);
1376 
1377  // Verify properties of various specific instruction types
1378  switch (MI->getOpcode()) {
1379  case TargetOpcode::COPY: {
1380  if (foundErrors)
1381  break;
1382  const MachineOperand &DstOp = MI->getOperand(0);
1383  const MachineOperand &SrcOp = MI->getOperand(1);
1384  LLT DstTy = MRI->getType(DstOp.getReg());
1385  LLT SrcTy = MRI->getType(SrcOp.getReg());
1386  if (SrcTy.isValid() && DstTy.isValid()) {
1387  // If both types are valid, check that the types are the same.
1388  if (SrcTy != DstTy) {
1389  report("Copy Instruction is illegal with mismatching types", MI);
1390  errs() << "Def = " << DstTy << ", Src = " << SrcTy << "\n";
1391  }
1392  }
1393  if (SrcTy.isValid() || DstTy.isValid()) {
1394  // If one of them have valid types, let's just check they have the same
1395  // size.
1396  unsigned SrcSize = TRI->getRegSizeInBits(SrcOp.getReg(), *MRI);
1397  unsigned DstSize = TRI->getRegSizeInBits(DstOp.getReg(), *MRI);
1398  assert(SrcSize && "Expecting size here");
1399  assert(DstSize && "Expecting size here");
1400  if (SrcSize != DstSize)
1401  if (!DstOp.getSubReg() && !SrcOp.getSubReg()) {
1402  report("Copy Instruction is illegal with mismatching sizes", MI);
1403  errs() << "Def Size = " << DstSize << ", Src Size = " << SrcSize
1404  << "\n";
1405  }
1406  }
1407  break;
1408  }
1409  case TargetOpcode::STATEPOINT:
1410  if (!MI->getOperand(StatepointOpers::IDPos).isImm() ||
1413  report("meta operands to STATEPOINT not constant!", MI);
1414  break;
1415 
1416  auto VerifyStackMapConstant = [&](unsigned Offset) {
1417  if (!MI->getOperand(Offset).isImm() ||
1418  MI->getOperand(Offset).getImm() != StackMaps::ConstantOp ||
1419  !MI->getOperand(Offset + 1).isImm())
1420  report("stack map constant to STATEPOINT not well formed!", MI);
1421  };
1422  const unsigned VarStart = StatepointOpers(MI).getVarIdx();
1423  VerifyStackMapConstant(VarStart + StatepointOpers::CCOffset);
1424  VerifyStackMapConstant(VarStart + StatepointOpers::FlagsOffset);
1425  VerifyStackMapConstant(VarStart + StatepointOpers::NumDeoptOperandsOffset);
1426 
1427  // TODO: verify we have properly encoded deopt arguments
1428  break;
1429  }
1430 }
1431 
1432 void
1433 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
1434  const MachineInstr *MI = MO->getParent();
1435  const MCInstrDesc &MCID = MI->getDesc();
1436  unsigned NumDefs = MCID.getNumDefs();
1437  if (MCID.getOpcode() == TargetOpcode::PATCHPOINT)
1438  NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0;
1439 
1440  // The first MCID.NumDefs operands must be explicit register defines
1441  if (MONum < NumDefs) {
1442  const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
1443  if (!MO->isReg())
1444  report("Explicit definition must be a register", MO, MONum);
1445  else if (!MO->isDef() && !MCOI.isOptionalDef())
1446  report("Explicit definition marked as use", MO, MONum);
1447  else if (MO->isImplicit())
1448  report("Explicit definition marked as implicit", MO, MONum);
1449  } else if (MONum < MCID.getNumOperands()) {
1450  const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
1451  // Don't check if it's the last operand in a variadic instruction. See,
1452  // e.g., LDM_RET in the arm back end.
1453  if (MO->isReg() &&
1454  !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) {
1455  if (MO->isDef() && !MCOI.isOptionalDef())
1456  report("Explicit operand marked as def", MO, MONum);
1457  if (MO->isImplicit())
1458  report("Explicit operand marked as implicit", MO, MONum);
1459  }
1460 
1461  int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO);
1462  if (TiedTo != -1) {
1463  if (!MO->isReg())
1464  report("Tied use must be a register", MO, MONum);
1465  else if (!MO->isTied())
1466  report("Operand should be tied", MO, MONum);
1467  else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
1468  report("Tied def doesn't match MCInstrDesc", MO, MONum);
1470  const MachineOperand &MOTied = MI->getOperand(TiedTo);
1471  if (!MOTied.isReg())
1472  report("Tied counterpart must be a register", &MOTied, TiedTo);
1473  else if (TargetRegisterInfo::isPhysicalRegister(MOTied.getReg()) &&
1474  MO->getReg() != MOTied.getReg())
1475  report("Tied physical registers must match.", &MOTied, TiedTo);
1476  }
1477  } else if (MO->isReg() && MO->isTied())
1478  report("Explicit operand should not be tied", MO, MONum);
1479  } else {
1480  // ARM adds %reg0 operands to indicate predicates. We'll allow that.
1481  if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
1482  report("Extra explicit operand on non-variadic instruction", MO, MONum);
1483  }
1484 
1485  switch (MO->getType()) {
1487  const unsigned Reg = MO->getReg();
1488  if (!Reg)
1489  return;
1490  if (MRI->tracksLiveness() && !MI->isDebugValue())
1491  checkLiveness(MO, MONum);
1492 
1493  // Verify the consistency of tied operands.
1494  if (MO->isTied()) {
1495  unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
1496  const MachineOperand &OtherMO = MI->getOperand(OtherIdx);
1497  if (!OtherMO.isReg())
1498  report("Must be tied to a register", MO, MONum);
1499  if (!OtherMO.isTied())
1500  report("Missing tie flags on tied operand", MO, MONum);
1501  if (MI->findTiedOperandIdx(OtherIdx) != MONum)
1502  report("Inconsistent tie links", MO, MONum);
1503  if (MONum < MCID.getNumDefs()) {
1504  if (OtherIdx < MCID.getNumOperands()) {
1505  if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO))
1506  report("Explicit def tied to explicit use without tie constraint",
1507  MO, MONum);
1508  } else {
1509  if (!OtherMO.isImplicit())
1510  report("Explicit def should be tied to implicit use", MO, MONum);
1511  }
1512  }
1513  }
1514 
1515  // Verify two-address constraints after leaving SSA form.
1516  unsigned DefIdx;
1517  if (!MRI->isSSA() && MO->isUse() &&
1518  MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
1519  Reg != MI->getOperand(DefIdx).getReg())
1520  report("Two-address instruction operands must be identical", MO, MONum);
1521 
1522  // Check register classes.
1523  unsigned SubIdx = MO->getSubReg();
1524 
1526  if (SubIdx) {
1527  report("Illegal subregister index for physical register", MO, MONum);
1528  return;
1529  }
1530  if (MONum < MCID.getNumOperands()) {
1531  if (const TargetRegisterClass *DRC =
1532  TII->getRegClass(MCID, MONum, TRI, *MF)) {
1533  if (!DRC->contains(Reg)) {
1534  report("Illegal physical register for instruction", MO, MONum);
1535  errs() << printReg(Reg, TRI) << " is not a "
1536  << TRI->getRegClassName(DRC) << " register.\n";
1537  }
1538  }
1539  }
1540  if (MO->isRenamable()) {
1541  if (MRI->isReserved(Reg)) {
1542  report("isRenamable set on reserved register", MO, MONum);
1543  return;
1544  }
1545  }
1546  if (MI->isDebugValue() && MO->isUse() && !MO->isDebug()) {
1547  report("Use-reg is not IsDebug in a DBG_VALUE", MO, MONum);
1548  return;
1549  }
1550  } else {
1551  // Virtual register.
1552  const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg);
1553  if (!RC) {
1554  // This is a generic virtual register.
1555 
1556  // If we're post-Select, we can't have gvregs anymore.
1557  if (isFunctionSelected) {
1558  report("Generic virtual register invalid in a Selected function",
1559  MO, MONum);
1560  return;
1561  }
1562 
1563  // The gvreg must have a type and it must not have a SubIdx.
1564  LLT Ty = MRI->getType(Reg);
1565  if (!Ty.isValid()) {
1566  report("Generic virtual register must have a valid type", MO,
1567  MONum);
1568  return;
1569  }
1570 
1571  const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg);
1572 
1573  // If we're post-RegBankSelect, the gvreg must have a bank.
1574  if (!RegBank && isFunctionRegBankSelected) {
1575  report("Generic virtual register must have a bank in a "
1576  "RegBankSelected function",
1577  MO, MONum);
1578  return;
1579  }
1580 
1581  // Make sure the register fits into its register bank if any.
1582  if (RegBank && Ty.isValid() &&
1583  RegBank->getSize() < Ty.getSizeInBits()) {
1584  report("Register bank is too small for virtual register", MO,
1585  MONum);
1586  errs() << "Register bank " << RegBank->getName() << " too small("
1587  << RegBank->getSize() << ") to fit " << Ty.getSizeInBits()
1588  << "-bits\n";
1589  return;
1590  }
1591  if (SubIdx) {
1592  report("Generic virtual register does not allow subregister index", MO,
1593  MONum);
1594  return;
1595  }
1596 
1597  // If this is a target specific instruction and this operand
1598  // has register class constraint, the virtual register must
1599  // comply to it.
1600  if (!isPreISelGenericOpcode(MCID.getOpcode()) &&
1601  MONum < MCID.getNumOperands() &&
1602  TII->getRegClass(MCID, MONum, TRI, *MF)) {
1603  report("Virtual register does not match instruction constraint", MO,
1604  MONum);
1605  errs() << "Expect register class "
1606  << TRI->getRegClassName(
1607  TII->getRegClass(MCID, MONum, TRI, *MF))
1608  << " but got nothing\n";
1609  return;
1610  }
1611 
1612  break;
1613  }
1614  if (SubIdx) {
1615  const TargetRegisterClass *SRC =
1616  TRI->getSubClassWithSubReg(RC, SubIdx);
1617  if (!SRC) {
1618  report("Invalid subregister index for virtual register", MO, MONum);
1619  errs() << "Register class " << TRI->getRegClassName(RC)
1620  << " does not support subreg index " << SubIdx << "\n";
1621  return;
1622  }
1623  if (RC != SRC) {
1624  report("Invalid register class for subregister index", MO, MONum);
1625  errs() << "Register class " << TRI->getRegClassName(RC)
1626  << " does not fully support subreg index " << SubIdx << "\n";
1627  return;
1628  }
1629  }
1630  if (MONum < MCID.getNumOperands()) {
1631  if (const TargetRegisterClass *DRC =
1632  TII->getRegClass(MCID, MONum, TRI, *MF)) {
1633  if (SubIdx) {
1634  const TargetRegisterClass *SuperRC =
1635  TRI->getLargestLegalSuperClass(RC, *MF);
1636  if (!SuperRC) {
1637  report("No largest legal super class exists.", MO, MONum);
1638  return;
1639  }
1640  DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
1641  if (!DRC) {
1642  report("No matching super-reg register class.", MO, MONum);
1643  return;
1644  }
1645  }
1646  if (!RC->hasSuperClassEq(DRC)) {
1647  report("Illegal virtual register for instruction", MO, MONum);
1648  errs() << "Expected a " << TRI->getRegClassName(DRC)
1649  << " register, but got a " << TRI->getRegClassName(RC)
1650  << " register\n";
1651  }
1652  }
1653  }
1654  }
1655  break;
1656  }
1657 
1659  regMasks.push_back(MO->getRegMask());
1660  break;
1661 
1663  if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
1664  report("PHI operand is not in the CFG", MO, MONum);
1665  break;
1666 
1668  if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
1669  LiveInts && !LiveInts->isNotInMIMap(*MI)) {
1670  int FI = MO->getIndex();
1671  LiveInterval &LI = LiveStks->getInterval(FI);
1672  SlotIndex Idx = LiveInts->getInstructionIndex(*MI);
1673 
1674  bool stores = MI->mayStore();
1675  bool loads = MI->mayLoad();
1676  // For a memory-to-memory move, we need to check if the frame
1677  // index is used for storing or loading, by inspecting the
1678  // memory operands.
1679  if (stores && loads) {
1680  for (auto *MMO : MI->memoperands()) {
1681  const PseudoSourceValue *PSV = MMO->getPseudoValue();
1682  if (PSV == nullptr) continue;
1685  if (Value == nullptr) continue;
1686  if (Value->getFrameIndex() != FI) continue;
1687 
1688  if (MMO->isStore())
1689  loads = false;
1690  else
1691  stores = false;
1692  break;
1693  }
1694  if (loads == stores)
1695  report("Missing fixed stack memoperand.", MI);
1696  }
1697  if (loads && !LI.liveAt(Idx.getRegSlot(true))) {
1698  report("Instruction loads from dead spill slot", MO, MONum);
1699  errs() << "Live stack: " << LI << '\n';
1700  }
1701  if (stores && !LI.liveAt(Idx.getRegSlot())) {
1702  report("Instruction stores to dead spill slot", MO, MONum);
1703  errs() << "Live stack: " << LI << '\n';
1704  }
1705  }
1706  break;
1707 
1708  default:
1709  break;
1710  }
1711 }
1712 
1713 void MachineVerifier::checkLivenessAtUse(const MachineOperand *MO,
1714  unsigned MONum, SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit,
1715  LaneBitmask LaneMask) {
1716  LiveQueryResult LRQ = LR.Query(UseIdx);
1717  // Check if we have a segment at the use, note however that we only need one
1718  // live subregister range, the others may be dead.
1719  if (!LRQ.valueIn() && LaneMask.none()) {
1720  report("No live segment at use", MO, MONum);
1721  report_context_liverange(LR);
1722  report_context_vreg_regunit(VRegOrUnit);
1723  report_context(UseIdx);
1724  }
1725  if (MO->isKill() && !LRQ.isKill()) {
1726  report("Live range continues after kill flag", MO, MONum);
1727  report_context_liverange(LR);
1728  report_context_vreg_regunit(VRegOrUnit);
1729  if (LaneMask.any())
1730  report_context_lanemask(LaneMask);
1731  report_context(UseIdx);
1732  }
1733 }
1734 
1735 void MachineVerifier::checkLivenessAtDef(const MachineOperand *MO,
1736  unsigned MONum, SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit,
1737  bool SubRangeCheck, LaneBitmask LaneMask) {
1738  if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) {
1739  assert(VNI && "NULL valno is not allowed");
1740  if (VNI->def != DefIdx) {
1741  report("Inconsistent valno->def", MO, MONum);
1742  report_context_liverange(LR);
1743  report_context_vreg_regunit(VRegOrUnit);
1744  if (LaneMask.any())
1745  report_context_lanemask(LaneMask);
1746  report_context(*VNI);
1747  report_context(DefIdx);
1748  }
1749  } else {
1750  report("No live segment at def", MO, MONum);
1751  report_context_liverange(LR);
1752  report_context_vreg_regunit(VRegOrUnit);
1753  if (LaneMask.any())
1754  report_context_lanemask(LaneMask);
1755  report_context(DefIdx);
1756  }
1757  // Check that, if the dead def flag is present, LiveInts agree.
1758  if (MO->isDead()) {
1759  LiveQueryResult LRQ = LR.Query(DefIdx);
1760  if (!LRQ.isDeadDef()) {
1762  "Expecting a virtual register.");
1763  // A dead subreg def only tells us that the specific subreg is dead. There
1764  // could be other non-dead defs of other subregs, or we could have other
1765  // parts of the register being live through the instruction. So unless we
1766  // are checking liveness for a subrange it is ok for the live range to
1767  // continue, given that we have a dead def of a subregister.
1768  if (SubRangeCheck || MO->getSubReg() == 0) {
1769  report("Live range continues after dead def flag", MO, MONum);
1770  report_context_liverange(LR);
1771  report_context_vreg_regunit(VRegOrUnit);
1772  if (LaneMask.any())
1773  report_context_lanemask(LaneMask);
1774  }
1775  }
1776  }
1777 }
1778 
1779 void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
1780  const MachineInstr *MI = MO->getParent();
1781  const unsigned Reg = MO->getReg();
1782 
1783  // Both use and def operands can read a register.
1784  if (MO->readsReg()) {
1785  if (MO->isKill())
1786  addRegWithSubRegs(regsKilled, Reg);
1787 
1788  // Check that LiveVars knows this kill.
1789  if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) &&
1790  MO->isKill()) {
1791  LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
1792  if (!is_contained(VI.Kills, MI))
1793  report("Kill missing from LiveVariables", MO, MONum);
1794  }
1795 
1796  // Check LiveInts liveness and kill.
1797  if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
1798  SlotIndex UseIdx = LiveInts->getInstructionIndex(*MI);
1799  // Check the cached regunit intervals.
1800  if (TargetRegisterInfo::isPhysicalRegister(Reg) && !isReserved(Reg)) {
1801  for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
1802  if (MRI->isReservedRegUnit(*Units))
1803  continue;
1804  if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units))
1805  checkLivenessAtUse(MO, MONum, UseIdx, *LR, *Units);
1806  }
1807  }
1808 
1810  if (LiveInts->hasInterval(Reg)) {
1811  // This is a virtual register interval.
1812  const LiveInterval &LI = LiveInts->getInterval(Reg);
1813  checkLivenessAtUse(MO, MONum, UseIdx, LI, Reg);
1814 
1815  if (LI.hasSubRanges() && !MO->isDef()) {
1816  unsigned SubRegIdx = MO->getSubReg();
1817  LaneBitmask MOMask = SubRegIdx != 0
1818  ? TRI->getSubRegIndexLaneMask(SubRegIdx)
1819  : MRI->getMaxLaneMaskForVReg(Reg);
1820  LaneBitmask LiveInMask;
1821  for (const LiveInterval::SubRange &SR : LI.subranges()) {
1822  if ((MOMask & SR.LaneMask).none())
1823  continue;
1824  checkLivenessAtUse(MO, MONum, UseIdx, SR, Reg, SR.LaneMask);
1825  LiveQueryResult LRQ = SR.Query(UseIdx);
1826  if (LRQ.valueIn())
1827  LiveInMask |= SR.LaneMask;
1828  }
1829  // At least parts of the register has to be live at the use.
1830  if ((LiveInMask & MOMask).none()) {
1831  report("No live subrange at use", MO, MONum);
1832  report_context(LI);
1833  report_context(UseIdx);
1834  }
1835  }
1836  } else {
1837  report("Virtual register has no live interval", MO, MONum);
1838  }
1839  }
1840  }
1841 
1842  // Use of a dead register.
1843  if (!regsLive.count(Reg)) {
1845  // Reserved registers may be used even when 'dead'.
1846  bool Bad = !isReserved(Reg);
1847  // We are fine if just any subregister has a defined value.
1848  if (Bad) {
1849  for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid();
1850  ++SubRegs) {
1851  if (regsLive.count(*SubRegs)) {
1852  Bad = false;
1853  break;
1854  }
1855  }
1856  }
1857  // If there is an additional implicit-use of a super register we stop
1858  // here. By definition we are fine if the super register is not
1859  // (completely) dead, if the complete super register is dead we will
1860  // get a report for its operand.
1861  if (Bad) {
1862  for (const MachineOperand &MOP : MI->uses()) {
1863  if (!MOP.isReg() || !MOP.isImplicit())
1864  continue;
1865 
1866  if (!TargetRegisterInfo::isPhysicalRegister(MOP.getReg()))
1867  continue;
1868 
1869  for (MCSubRegIterator SubRegs(MOP.getReg(), TRI); SubRegs.isValid();
1870  ++SubRegs) {
1871  if (*SubRegs == Reg) {
1872  Bad = false;
1873  break;
1874  }
1875  }
1876  }
1877  }
1878  if (Bad)
1879  report("Using an undefined physical register", MO, MONum);
1880  } else if (MRI->def_empty(Reg)) {
1881  report("Reading virtual register without a def", MO, MONum);
1882  } else {
1883  BBInfo &MInfo = MBBInfoMap[MI->getParent()];
1884  // We don't know which virtual registers are live in, so only complain
1885  // if vreg was killed in this MBB. Otherwise keep track of vregs that
1886  // must be live in. PHI instructions are handled separately.
1887  if (MInfo.regsKilled.count(Reg))
1888  report("Using a killed virtual register", MO, MONum);
1889  else if (!MI->isPHI())
1890  MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
1891  }
1892  }
1893  }
1894 
1895  if (MO->isDef()) {
1896  // Register defined.
1897  // TODO: verify that earlyclobber ops are not used.
1898  if (MO->isDead())
1899  addRegWithSubRegs(regsDead, Reg);
1900  else
1901  addRegWithSubRegs(regsDefined, Reg);
1902 
1903  // Verify SSA form.
1904  if (MRI->isSSA() && TargetRegisterInfo::isVirtualRegister(Reg) &&
1905  std::next(MRI->def_begin(Reg)) != MRI->def_end())
1906  report("Multiple virtual register defs in SSA form", MO, MONum);
1907 
1908  // Check LiveInts for a live segment, but only for virtual registers.
1909  if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
1910  SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI);
1911  DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
1912 
1914  if (LiveInts->hasInterval(Reg)) {
1915  const LiveInterval &LI = LiveInts->getInterval(Reg);
1916  checkLivenessAtDef(MO, MONum, DefIdx, LI, Reg);
1917 
1918  if (LI.hasSubRanges()) {
1919  unsigned SubRegIdx = MO->getSubReg();
1920  LaneBitmask MOMask = SubRegIdx != 0
1921  ? TRI->getSubRegIndexLaneMask(SubRegIdx)
1922  : MRI->getMaxLaneMaskForVReg(Reg);
1923  for (const LiveInterval::SubRange &SR : LI.subranges()) {
1924  if ((SR.LaneMask & MOMask).none())
1925  continue;
1926  checkLivenessAtDef(MO, MONum, DefIdx, SR, Reg, true, SR.LaneMask);
1927  }
1928  }
1929  } else {
1930  report("Virtual register has no Live interval", MO, MONum);
1931  }
1932  }
1933  }
1934  }
1935 }
1936 
1937 void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {}
1938 
1939 // This function gets called after visiting all instructions in a bundle. The
1940 // argument points to the bundle header.
1941 // Normal stand-alone instructions are also considered 'bundles', and this
1942 // function is called for all of them.
1943 void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
1944  BBInfo &MInfo = MBBInfoMap[MI->getParent()];
1945  set_union(MInfo.regsKilled, regsKilled);
1946  set_subtract(regsLive, regsKilled); regsKilled.clear();
1947  // Kill any masked registers.
1948  while (!regMasks.empty()) {
1949  const uint32_t *Mask = regMasks.pop_back_val();
1950  for (RegSet::iterator I = regsLive.begin(), E = regsLive.end(); I != E; ++I)
1953  regsDead.push_back(*I);
1954  }
1955  set_subtract(regsLive, regsDead); regsDead.clear();
1956  set_union(regsLive, regsDefined); regsDefined.clear();
1957 }
1958 
1959 void
1960 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
1961  MBBInfoMap[MBB].regsLiveOut = regsLive;
1962  regsLive.clear();
1963 
1964  if (Indexes) {
1965  SlotIndex stop = Indexes->getMBBEndIdx(MBB);
1966  if (!(stop > lastIndex)) {
1967  report("Block ends before last instruction index", MBB);
1968  errs() << "Block ends at " << stop
1969  << " last instruction was at " << lastIndex << '\n';
1970  }
1971  lastIndex = stop;
1972  }
1973 }
1974 
1975 // Calculate the largest possible vregsPassed sets. These are the registers that
1976 // can pass through an MBB live, but may not be live every time. It is assumed
1977 // that all vregsPassed sets are empty before the call.
1978 void MachineVerifier::calcRegsPassed() {
1979  // First push live-out regs to successors' vregsPassed. Remember the MBBs that
1980  // have any vregsPassed.
1982  for (const auto &MBB : *MF) {
1983  BBInfo &MInfo = MBBInfoMap[&MBB];
1984  if (!MInfo.reachable)
1985  continue;
1987  SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
1988  BBInfo &SInfo = MBBInfoMap[*SuI];
1989  if (SInfo.addPassed(MInfo.regsLiveOut))
1990  todo.insert(*SuI);
1991  }
1992  }
1993 
1994  // Iteratively push vregsPassed to successors. This will converge to the same
1995  // final state regardless of DenseSet iteration order.
1996  while (!todo.empty()) {
1997  const MachineBasicBlock *MBB = *todo.begin();
1998  todo.erase(MBB);
1999  BBInfo &MInfo = MBBInfoMap[MBB];
2001  SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
2002  if (*SuI == MBB)
2003  continue;
2004  BBInfo &SInfo = MBBInfoMap[*SuI];
2005  if (SInfo.addPassed(MInfo.vregsPassed))
2006  todo.insert(*SuI);
2007  }
2008  }
2009 }
2010 
2011 // Calculate the set of virtual registers that must be passed through each basic
2012 // block in order to satisfy the requirements of successor blocks. This is very
2013 // similar to calcRegsPassed, only backwards.
2014 void MachineVerifier::calcRegsRequired() {
2015  // First push live-in regs to predecessors' vregsRequired.
2017  for (const auto &MBB : *MF) {
2018  BBInfo &MInfo = MBBInfoMap[&MBB];
2020  PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
2021  BBInfo &PInfo = MBBInfoMap[*PrI];
2022  if (PInfo.addRequired(MInfo.vregsLiveIn))
2023  todo.insert(*PrI);
2024  }
2025  }
2026 
2027  // Iteratively push vregsRequired to predecessors. This will converge to the
2028  // same final state regardless of DenseSet iteration order.
2029  while (!todo.empty()) {
2030  const MachineBasicBlock *MBB = *todo.begin();
2031  todo.erase(MBB);
2032  BBInfo &MInfo = MBBInfoMap[MBB];
2034  PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
2035  if (*PrI == MBB)
2036  continue;
2037  BBInfo &SInfo = MBBInfoMap[*PrI];
2038  if (SInfo.addRequired(MInfo.vregsRequired))
2039  todo.insert(*PrI);
2040  }
2041  }
2042 }
2043 
2044 // Check PHI instructions at the beginning of MBB. It is assumed that
2045 // calcRegsPassed has been run so BBInfo::isLiveOut is valid.
2046 void MachineVerifier::checkPHIOps(const MachineBasicBlock &MBB) {
2047  BBInfo &MInfo = MBBInfoMap[&MBB];
2048 
2050  for (const MachineInstr &Phi : MBB) {
2051  if (!Phi.isPHI())
2052  break;
2053  seen.clear();
2054 
2055  const MachineOperand &MODef = Phi.getOperand(0);
2056  if (!MODef.isReg() || !MODef.isDef()) {
2057  report("Expected first PHI operand to be a register def", &MODef, 0);
2058  continue;
2059  }
2060  if (MODef.isTied() || MODef.isImplicit() || MODef.isInternalRead() ||
2061  MODef.isEarlyClobber() || MODef.isDebug())
2062  report("Unexpected flag on PHI operand", &MODef, 0);
2063  unsigned DefReg = MODef.getReg();
2065  report("Expected first PHI operand to be a virtual register", &MODef, 0);
2066 
2067  for (unsigned I = 1, E = Phi.getNumOperands(); I != E; I += 2) {
2068  const MachineOperand &MO0 = Phi.getOperand(I);
2069  if (!MO0.isReg()) {
2070  report("Expected PHI operand to be a register", &MO0, I);
2071  continue;
2072  }
2073  if (MO0.isImplicit() || MO0.isInternalRead() || MO0.isEarlyClobber() ||
2074  MO0.isDebug() || MO0.isTied())
2075  report("Unexpected flag on PHI operand", &MO0, I);
2076 
2077  const MachineOperand &MO1 = Phi.getOperand(I + 1);
2078  if (!MO1.isMBB()) {
2079  report("Expected PHI operand to be a basic block", &MO1, I + 1);
2080  continue;
2081  }
2082 
2083  const MachineBasicBlock &Pre = *MO1.getMBB();
2084  if (!Pre.isSuccessor(&MBB)) {
2085  report("PHI input is not a predecessor block", &MO1, I + 1);
2086  continue;
2087  }
2088 
2089  if (MInfo.reachable) {
2090  seen.insert(&Pre);
2091  BBInfo &PrInfo = MBBInfoMap[&Pre];
2092  if (!MO0.isUndef() && PrInfo.reachable &&
2093  !PrInfo.isLiveOut(MO0.getReg()))
2094  report("PHI operand is not live-out from predecessor", &MO0, I);
2095  }
2096  }
2097 
2098  // Did we see all predecessors?
2099  if (MInfo.reachable) {
2100  for (MachineBasicBlock *Pred : MBB.predecessors()) {
2101  if (!seen.count(Pred)) {
2102  report("Missing PHI operand", &Phi);
2103  errs() << printMBBReference(*Pred)
2104  << " is a predecessor according to the CFG.\n";
2105  }
2106  }
2107  }
2108  }
2109 }
2110 
2111 void MachineVerifier::visitMachineFunctionAfter() {
2112  calcRegsPassed();
2113 
2114  for (const MachineBasicBlock &MBB : *MF)
2115  checkPHIOps(MBB);
2116 
2117  // Now check liveness info if available
2118  calcRegsRequired();
2119 
2120  // Check for killed virtual registers that should be live out.
2121  for (const auto &MBB : *MF) {
2122  BBInfo &MInfo = MBBInfoMap[&MBB];
2123  for (RegSet::iterator
2124  I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
2125  ++I)
2126  if (MInfo.regsKilled.count(*I)) {
2127  report("Virtual register killed in block, but needed live out.", &MBB);
2128  errs() << "Virtual register " << printReg(*I)
2129  << " is used after the block.\n";
2130  }
2131  }
2132 
2133  if (!MF->empty()) {
2134  BBInfo &MInfo = MBBInfoMap[&MF->front()];
2135  for (RegSet::iterator
2136  I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
2137  ++I) {
2138  report("Virtual register defs don't dominate all uses.", MF);
2139  report_context_vreg(*I);
2140  }
2141  }
2142 
2143  if (LiveVars)
2144  verifyLiveVariables();
2145  if (LiveInts)
2146  verifyLiveIntervals();
2147 }
2148 
2149 void MachineVerifier::verifyLiveVariables() {
2150  assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
2151  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
2152  unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
2153  LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
2154  for (const auto &MBB : *MF) {
2155  BBInfo &MInfo = MBBInfoMap[&MBB];
2156 
2157  // Our vregsRequired should be identical to LiveVariables' AliveBlocks
2158  if (MInfo.vregsRequired.count(Reg)) {
2159  if (!VI.AliveBlocks.test(MBB.getNumber())) {
2160  report("LiveVariables: Block missing from AliveBlocks", &MBB);
2161  errs() << "Virtual register " << printReg(Reg)
2162  << " must be live through the block.\n";
2163  }
2164  } else {
2165  if (VI.AliveBlocks.test(MBB.getNumber())) {
2166  report("LiveVariables: Block should not be in AliveBlocks", &MBB);
2167  errs() << "Virtual register " << printReg(Reg)
2168  << " is not needed live through the block.\n";
2169  }
2170  }
2171  }
2172  }
2173 }
2174 
2175 void MachineVerifier::verifyLiveIntervals() {
2176  assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
2177  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
2178  unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
2179 
2180  // Spilling and splitting may leave unused registers around. Skip them.
2181  if (MRI->reg_nodbg_empty(Reg))
2182  continue;
2183 
2184  if (!LiveInts->hasInterval(Reg)) {
2185  report("Missing live interval for virtual register", MF);
2186  errs() << printReg(Reg, TRI) << " still has defs or uses\n";
2187  continue;
2188  }
2189 
2190  const LiveInterval &LI = LiveInts->getInterval(Reg);
2191  assert(Reg == LI.reg && "Invalid reg to interval mapping");
2192  verifyLiveInterval(LI);
2193  }
2194 
2195  // Verify all the cached regunit intervals.
2196  for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
2197  if (const LiveRange *LR = LiveInts->getCachedRegUnit(i))
2198  verifyLiveRange(*LR, i);
2199 }
2200 
2201 void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
2202  const VNInfo *VNI, unsigned Reg,
2203  LaneBitmask LaneMask) {
2204  if (VNI->isUnused())
2205  return;
2206 
2207  const VNInfo *DefVNI = LR.getVNInfoAt(VNI->def);
2208 
2209  if (!DefVNI) {
2210  report("Value not live at VNInfo def and not marked unused", MF);
2211  report_context(LR, Reg, LaneMask);
2212  report_context(*VNI);
2213  return;
2214  }
2215 
2216  if (DefVNI != VNI) {
2217  report("Live segment at def has different VNInfo", MF);
2218  report_context(LR, Reg, LaneMask);
2219  report_context(*VNI);
2220  return;
2221  }
2222 
2223  const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
2224  if (!MBB) {
2225  report("Invalid VNInfo definition index", MF);
2226  report_context(LR, Reg, LaneMask);
2227  report_context(*VNI);
2228  return;
2229  }
2230 
2231  if (VNI->isPHIDef()) {
2232  if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
2233  report("PHIDef VNInfo is not defined at MBB start", MBB);
2234  report_context(LR, Reg, LaneMask);
2235  report_context(*VNI);
2236  }
2237  return;
2238  }
2239 
2240  // Non-PHI def.
2241  const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
2242  if (!MI) {
2243  report("No instruction at VNInfo def index", MBB);
2244  report_context(LR, Reg, LaneMask);
2245  report_context(*VNI);
2246  return;
2247  }
2248 
2249  if (Reg != 0) {
2250  bool hasDef = false;
2251  bool isEarlyClobber = false;
2252  for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
2253  if (!MOI->isReg() || !MOI->isDef())
2254  continue;
2256  if (MOI->getReg() != Reg)
2257  continue;
2258  } else {
2259  if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) ||
2260  !TRI->hasRegUnit(MOI->getReg(), Reg))
2261  continue;
2262  }
2263  if (LaneMask.any() &&
2264  (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
2265  continue;
2266  hasDef = true;
2267  if (MOI->isEarlyClobber())
2268  isEarlyClobber = true;
2269  }
2270 
2271  if (!hasDef) {
2272  report("Defining instruction does not modify register", MI);
2273  report_context(LR, Reg, LaneMask);
2274  report_context(*VNI);
2275  }
2276 
2277  // Early clobber defs begin at USE slots, but other defs must begin at
2278  // DEF slots.
2279  if (isEarlyClobber) {
2280  if (!VNI->def.isEarlyClobber()) {
2281  report("Early clobber def must be at an early-clobber slot", MBB);
2282  report_context(LR, Reg, LaneMask);
2283  report_context(*VNI);
2284  }
2285  } else if (!VNI->def.isRegister()) {
2286  report("Non-PHI, non-early clobber def must be at a register slot", MBB);
2287  report_context(LR, Reg, LaneMask);
2288  report_context(*VNI);
2289  }
2290  }
2291 }
2292 
2293 void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
2295  unsigned Reg, LaneBitmask LaneMask)
2296 {
2297  const LiveRange::Segment &S = *I;
2298  const VNInfo *VNI = S.valno;
2299  assert(VNI && "Live segment has no valno");
2300 
2301  if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) {
2302  report("Foreign valno in live segment", MF);
2303  report_context(LR, Reg, LaneMask);
2304  report_context(S);
2305  report_context(*VNI);
2306  }
2307 
2308  if (VNI->isUnused()) {
2309  report("Live segment valno is marked unused", MF);
2310  report_context(LR, Reg, LaneMask);
2311  report_context(S);
2312  }
2313 
2314  const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(S.start);
2315  if (!MBB) {
2316  report("Bad start of live segment, no basic block", MF);
2317  report_context(LR, Reg, LaneMask);
2318  report_context(S);
2319  return;
2320  }
2321  SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
2322  if (S.start != MBBStartIdx && S.start != VNI->def) {
2323  report("Live segment must begin at MBB entry or valno def", MBB);
2324  report_context(LR, Reg, LaneMask);
2325  report_context(S);
2326  }
2327 
2328  const MachineBasicBlock *EndMBB =
2329  LiveInts->getMBBFromIndex(S.end.getPrevSlot());
2330  if (!EndMBB) {
2331  report("Bad end of live segment, no basic block", MF);
2332  report_context(LR, Reg, LaneMask);
2333  report_context(S);
2334  return;
2335  }
2336 
2337  // No more checks for live-out segments.
2338  if (S.end == LiveInts->getMBBEndIdx(EndMBB))
2339  return;
2340 
2341  // RegUnit intervals are allowed dead phis.
2342  if (!TargetRegisterInfo::isVirtualRegister(Reg) && VNI->isPHIDef() &&
2343  S.start == VNI->def && S.end == VNI->def.getDeadSlot())
2344  return;
2345 
2346  // The live segment is ending inside EndMBB
2347  const MachineInstr *MI =
2348  LiveInts->getInstructionFromIndex(S.end.getPrevSlot());
2349  if (!MI) {
2350  report("Live segment doesn't end at a valid instruction", EndMBB);
2351  report_context(LR, Reg, LaneMask);
2352  report_context(S);
2353  return;
2354  }
2355 
2356  // The block slot must refer to a basic block boundary.
2357  if (S.end.isBlock()) {
2358  report("Live segment ends at B slot of an instruction", EndMBB);
2359  report_context(LR, Reg, LaneMask);
2360  report_context(S);
2361  }
2362 
2363  if (S.end.isDead()) {
2364  // Segment ends on the dead slot.
2365  // That means there must be a dead def.
2366  if (!SlotIndex::isSameInstr(S.start, S.end)) {
2367  report("Live segment ending at dead slot spans instructions", EndMBB);
2368  report_context(LR, Reg, LaneMask);
2369  report_context(S);
2370  }
2371  }
2372 
2373  // A live segment can only end at an early-clobber slot if it is being
2374  // redefined by an early-clobber def.
2375  if (S.end.isEarlyClobber()) {
2376  if (I+1 == LR.end() || (I+1)->start != S.end) {
2377  report("Live segment ending at early clobber slot must be "
2378  "redefined by an EC def in the same instruction", EndMBB);
2379  report_context(LR, Reg, LaneMask);
2380  report_context(S);
2381  }
2382  }
2383 
2384  // The following checks only apply to virtual registers. Physreg liveness
2385  // is too weird to check.
2387  // A live segment can end with either a redefinition, a kill flag on a
2388  // use, or a dead flag on a def.
2389  bool hasRead = false;
2390  bool hasSubRegDef = false;
2391  bool hasDeadDef = false;
2392  for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
2393  if (!MOI->isReg() || MOI->getReg() != Reg)
2394  continue;
2395  unsigned Sub = MOI->getSubReg();
2396  LaneBitmask SLM = Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub)
2397  : LaneBitmask::getAll();
2398  if (MOI->isDef()) {
2399  if (Sub != 0) {
2400  hasSubRegDef = true;
2401  // An operand %0:sub0 reads %0:sub1..n. Invert the lane
2402  // mask for subregister defs. Read-undef defs will be handled by
2403  // readsReg below.
2404  SLM = ~SLM;
2405  }
2406  if (MOI->isDead())
2407  hasDeadDef = true;
2408  }
2409  if (LaneMask.any() && (LaneMask & SLM).none())
2410  continue;
2411  if (MOI->readsReg())
2412  hasRead = true;
2413  }
2414  if (S.end.isDead()) {
2415  // Make sure that the corresponding machine operand for a "dead" live
2416  // range has the dead flag. We cannot perform this check for subregister
2417  // liveranges as partially dead values are allowed.
2418  if (LaneMask.none() && !hasDeadDef) {
2419  report("Instruction ending live segment on dead slot has no dead flag",
2420  MI);
2421  report_context(LR, Reg, LaneMask);
2422  report_context(S);
2423  }
2424  } else {
2425  if (!hasRead) {
2426  // When tracking subregister liveness, the main range must start new
2427  // values on partial register writes, even if there is no read.
2428  if (!MRI->shouldTrackSubRegLiveness(Reg) || LaneMask.any() ||
2429  !hasSubRegDef) {
2430  report("Instruction ending live segment doesn't read the register",
2431  MI);
2432  report_context(LR, Reg, LaneMask);
2433  report_context(S);
2434  }
2435  }
2436  }
2437  }
2438 
2439  // Now check all the basic blocks in this live segment.
2441  // Is this live segment the beginning of a non-PHIDef VN?
2442  if (S.start == VNI->def && !VNI->isPHIDef()) {
2443  // Not live-in to any blocks.
2444  if (MBB == EndMBB)
2445  return;
2446  // Skip this block.
2447  ++MFI;
2448  }
2449 
2451  if (LaneMask.any()) {
2452  LiveInterval &OwnerLI = LiveInts->getInterval(Reg);
2453  OwnerLI.computeSubRangeUndefs(Undefs, LaneMask, *MRI, *Indexes);
2454  }
2455 
2456  while (true) {
2457  assert(LiveInts->isLiveInToMBB(LR, &*MFI));
2458  // We don't know how to track physregs into a landing pad.
2460  MFI->isEHPad()) {
2461  if (&*MFI == EndMBB)
2462  break;
2463  ++MFI;
2464  continue;
2465  }
2466 
2467  // Is VNI a PHI-def in the current block?
2468  bool IsPHI = VNI->isPHIDef() &&
2469  VNI->def == LiveInts->getMBBStartIdx(&*MFI);
2470 
2471  // Check that VNI is live-out of all predecessors.
2472  for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
2473  PE = MFI->pred_end(); PI != PE; ++PI) {
2474  SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
2475  const VNInfo *PVNI = LR.getVNInfoBefore(PEnd);
2476 
2477  // All predecessors must have a live-out value. However for a phi
2478  // instruction with subregister intervals
2479  // only one of the subregisters (not necessarily the current one) needs to
2480  // be defined.
2481  if (!PVNI && (LaneMask.none() || !IsPHI)) {
2482  if (LiveRangeCalc::isJointlyDominated(*PI, Undefs, *Indexes))
2483  continue;
2484  report("Register not marked live out of predecessor", *PI);
2485  report_context(LR, Reg, LaneMask);
2486  report_context(*VNI);
2487  errs() << " live into " << printMBBReference(*MFI) << '@'
2488  << LiveInts->getMBBStartIdx(&*MFI) << ", not live before "
2489  << PEnd << '\n';
2490  continue;
2491  }
2492 
2493  // Only PHI-defs can take different predecessor values.
2494  if (!IsPHI && PVNI != VNI) {
2495  report("Different value live out of predecessor", *PI);
2496  report_context(LR, Reg, LaneMask);
2497  errs() << "Valno #" << PVNI->id << " live out of "
2498  << printMBBReference(*(*PI)) << '@' << PEnd << "\nValno #"
2499  << VNI->id << " live into " << printMBBReference(*MFI) << '@'
2500  << LiveInts->getMBBStartIdx(&*MFI) << '\n';
2501  }
2502  }
2503  if (&*MFI == EndMBB)
2504  break;
2505  ++MFI;
2506  }
2507 }
2508 
2509 void MachineVerifier::verifyLiveRange(const LiveRange &LR, unsigned Reg,
2510  LaneBitmask LaneMask) {
2511  for (const VNInfo *VNI : LR.valnos)
2512  verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
2513 
2514  for (LiveRange::const_iterator I = LR.begin(), E = LR.end(); I != E; ++I)
2515  verifyLiveRangeSegment(LR, I, Reg, LaneMask);
2516 }
2517 
2518 void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
2519  unsigned Reg = LI.reg;
2521  verifyLiveRange(LI, Reg);
2522 
2523  LaneBitmask Mask;
2524  LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
2525  for (const LiveInterval::SubRange &SR : LI.subranges()) {
2526  if ((Mask & SR.LaneMask).any()) {
2527  report("Lane masks of sub ranges overlap in live interval", MF);
2528  report_context(LI);
2529  }
2530  if ((SR.LaneMask & ~MaxMask).any()) {
2531  report("Subrange lanemask is invalid", MF);
2532  report_context(LI);
2533  }
2534  if (SR.empty()) {
2535  report("Subrange must not be empty", MF);
2536  report_context(SR, LI.reg, SR.LaneMask);
2537  }
2538  Mask |= SR.LaneMask;
2539  verifyLiveRange(SR, LI.reg, SR.LaneMask);
2540  if (!LI.covers(SR)) {
2541  report("A Subrange is not covered by the main range", MF);
2542  report_context(LI);
2543  }
2544  }
2545 
2546  // Check the LI only has one connected component.
2547  ConnectedVNInfoEqClasses ConEQ(*LiveInts);
2548  unsigned NumComp = ConEQ.Classify(LI);
2549  if (NumComp > 1) {
2550  report("Multiple connected components in live interval", MF);
2551  report_context(LI);
2552  for (unsigned comp = 0; comp != NumComp; ++comp) {
2553  errs() << comp << ": valnos";
2555  E = LI.vni_end(); I!=E; ++I)
2556  if (comp == ConEQ.getEqClass(*I))
2557  errs() << ' ' << (*I)->id;
2558  errs() << '\n';
2559  }
2560  }
2561 }
2562 
2563 namespace {
2564 
2565  // FrameSetup and FrameDestroy can have zero adjustment, so using a single
2566  // integer, we can't tell whether it is a FrameSetup or FrameDestroy if the
2567  // value is zero.
2568  // We use a bool plus an integer to capture the stack state.
2569  struct StackStateOfBB {
2570  StackStateOfBB() = default;
2571  StackStateOfBB(int EntryVal, int ExitVal, bool EntrySetup, bool ExitSetup) :
2572  EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
2573  ExitIsSetup(ExitSetup) {}
2574 
2575  // Can be negative, which means we are setting up a frame.
2576  int EntryValue = 0;
2577  int ExitValue = 0;
2578  bool EntryIsSetup = false;
2579  bool ExitIsSetup = false;
2580  };
2581 
2582 } // end anonymous namespace
2583 
2584 /// Make sure on every path through the CFG, a FrameSetup <n> is always followed
2585 /// by a FrameDestroy <n>, stack adjustments are identical on all
2586 /// CFG edges to a merge point, and frame is destroyed at end of a return block.
2587 void MachineVerifier::verifyStackFrame() {
2588  unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode();
2589  unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
2590  if (FrameSetupOpcode == ~0u && FrameDestroyOpcode == ~0u)
2591  return;
2592 
2594  SPState.resize(MF->getNumBlockIDs());
2596 
2597  // Visit the MBBs in DFS order.
2598  for (df_ext_iterator<const MachineFunction *,
2600  DFI = df_ext_begin(MF, Reachable), DFE = df_ext_end(MF, Reachable);
2601  DFI != DFE; ++DFI) {
2602  const MachineBasicBlock *MBB = *DFI;
2603 
2604  StackStateOfBB BBState;
2605  // Check the exit state of the DFS stack predecessor.
2606  if (DFI.getPathLength() >= 2) {
2607  const MachineBasicBlock *StackPred = DFI.getPath(DFI.getPathLength() - 2);
2608  assert(Reachable.count(StackPred) &&
2609  "DFS stack predecessor is already visited.\n");
2610  BBState.EntryValue = SPState[StackPred->getNumber()].ExitValue;
2611  BBState.EntryIsSetup = SPState[StackPred->getNumber()].ExitIsSetup;
2612  BBState.ExitValue = BBState.EntryValue;
2613  BBState.ExitIsSetup = BBState.EntryIsSetup;
2614  }
2615 
2616  // Update stack state by checking contents of MBB.
2617  for (const auto &I : *MBB) {
2618  if (I.getOpcode() == FrameSetupOpcode) {
2619  if (BBState.ExitIsSetup)
2620  report("FrameSetup is after another FrameSetup", &I);
2621  BBState.ExitValue -= TII->getFrameTotalSize(I);
2622  BBState.ExitIsSetup = true;
2623  }
2624 
2625  if (I.getOpcode() == FrameDestroyOpcode) {
2626  int Size = TII->getFrameTotalSize(I);
2627  if (!BBState.ExitIsSetup)
2628  report("FrameDestroy is not after a FrameSetup", &I);
2629  int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
2630  BBState.ExitValue;
2631  if (BBState.ExitIsSetup && AbsSPAdj != Size) {
2632  report("FrameDestroy <n> is after FrameSetup <m>", &I);
2633  errs() << "FrameDestroy <" << Size << "> is after FrameSetup <"
2634  << AbsSPAdj << ">.\n";
2635  }
2636  BBState.ExitValue += Size;
2637  BBState.ExitIsSetup = false;
2638  }
2639  }
2640  SPState[MBB->getNumber()] = BBState;
2641 
2642  // Make sure the exit state of any predecessor is consistent with the entry
2643  // state.
2644  for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
2645  E = MBB->pred_end(); I != E; ++I) {
2646  if (Reachable.count(*I) &&
2647  (SPState[(*I)->getNumber()].ExitValue != BBState.EntryValue ||
2648  SPState[(*I)->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
2649  report("The exit stack state of a predecessor is inconsistent.", MBB);
2650  errs() << "Predecessor " << printMBBReference(*(*I))
2651  << " has exit state (" << SPState[(*I)->getNumber()].ExitValue
2652  << ", " << SPState[(*I)->getNumber()].ExitIsSetup << "), while "
2653  << printMBBReference(*MBB) << " has entry state ("
2654  << BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n";
2655  }
2656  }
2657 
2658  // Make sure the entry state of any successor is consistent with the exit
2659  // state.
2660  for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
2661  E = MBB->succ_end(); I != E; ++I) {
2662  if (Reachable.count(*I) &&
2663  (SPState[(*I)->getNumber()].EntryValue != BBState.ExitValue ||
2664  SPState[(*I)->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
2665  report("The entry stack state of a successor is inconsistent.", MBB);
2666  errs() << "Successor " << printMBBReference(*(*I))
2667  << " has entry state (" << SPState[(*I)->getNumber()].EntryValue
2668  << ", " << SPState[(*I)->getNumber()].EntryIsSetup << "), while "
2669  << printMBBReference(*MBB) << " has exit state ("
2670  << BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n";
2671  }
2672  }
2673 
2674  // Make sure a basic block with return ends with zero stack adjustment.
2675  if (!MBB->empty() && MBB->back().isReturn()) {
2676  if (BBState.ExitIsSetup)
2677  report("A return block ends with a FrameSetup.", MBB);
2678  if (BBState.ExitValue)
2679  report("A return block ends with a nonzero stack adjustment.", MBB);
2680  }
2681  }
2682 }
bool reg_nodbg_empty(unsigned RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions...
Pass interface - Implemented by all &#39;passes&#39;.
Definition: Pass.h:80
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
Definition: LiveInterval.h:77
bool isRegister() const
isRegister - Returns true if this is a normal register use/def slot.
Definition: SlotIndexes.h:233
mop_iterator operands_end()
Definition: MachineInstr.h:453
Safe Stack instrumentation pass
Definition: SafeStack.cpp:907
A common definition of LaneBitmask for use in TableGen and CodeGen.
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
const unsigned reg
Definition: LiveInterval.h:666
MachineBasicBlock * getMBB() const
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:60
LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:491
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
const char * getName() const
Get a user friendly name of this register bank.
Definition: RegisterBank.h:51
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID&#39;s allocated.
const MachineFunctionProperties & getProperties() const
Get the function properties.
int64_t getFrameTotalSize(const MachineInstr &I) const
Returns the total frame size, which is made up of the space set up inside the pair of frame start-sto...
setjmp/longjmp based exceptions
vni_iterator vni_begin()
Definition: LiveInterval.h:219
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:637
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
static bool matchPair(MachineBasicBlock::const_succ_iterator i, const MachineBasicBlock *a, const MachineBasicBlock *b)
unsigned Reg
unsigned getSubReg() const
bool isInlineAsm() const
MBBIndexIterator MBBIndexEnd() const
Return an iterator for the end of the idx2MBBMap.
Definition: SlotIndexes.h:531
bool test(unsigned Idx) const
Definition: BitVector.h:501
LLT getScalarType() const
bool isDead() const
isDead - Returns true if this is a dead def kill slot.
Definition: SlotIndexes.h:236
LiveInterval & getInterval(int Slot)
Definition: LiveStacks.h:63
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
uint64_t getSize() const
Return the size in bytes of the memory reference.
bool isDeadDef() const
Return true if this instruction has a dead def.
Definition: LiveInterval.h:116
static unsigned getSizeInBits(const fltSemantics &Sem)
Returns the size of the floating point number (in bits) in the given semantics.
Definition: APFloat.cpp:169
A live range for subregisters.
Definition: LiveInterval.h:644
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1185
bool isValid() const
Returns true if this is a valid index.
Definition: SlotIndexes.h:151
MachineBasicBlock reference.
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:161
VarInfo - This represents the regions where a virtual register is live in the program.
Definition: LiveVariables.h:78
unsigned const TargetRegisterInfo * TRI
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
Definition: LaneBitmask.h:93
F(f)
const fltSemantics & getSemantics() const
Definition: APFloat.h:1154
unsigned getCallFrameDestroyOpcode() const
const Instruction * getTerminator() const LLVM_READONLY
Returns the terminator instruction if the block is well formed or null if the block is not well forme...
Definition: BasicBlock.cpp:137
bool reservedRegsFrozen() const
reservedRegsFrozen - Returns true after freezeReservedRegs() was called to ensure the set of reserved...
std::vector< MachineBasicBlock * >::const_iterator const_pred_iterator
VNInfo - Value Number Information.
Definition: LiveInterval.h:52
void print(raw_ostream &O, const Module *=nullptr) const override
Implement the dump method.
bool isPHI() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void verifyUseLists() const
Verify the use list of all registers.
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
unsigned getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
unsigned getBitWidth() const
getBitWidth - Return the bitwidth of this constant.
Definition: Constants.h:142
bool isInternalRead() const
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:156
void initializeMachineVerifierPassPass(PassRegistry &)
bool isUnused() const
Returns true if this value is unused.
Definition: LiveInterval.h:80
Mask of preserved registers.
bool isEarlyClobber() const
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
bool test(unsigned Idx) const
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness...
bool isVector() const
bool isNotInMIMap(const MachineInstr &Instr) const
Returns true if the specified machine instr has been removed or was never entered in the map...
bool isBlock() const
isBlock - Returns true if this is a block boundary slot.
Definition: SlotIndexes.h:226
A description of a memory reference used in the backend.
Definition: BitVector.h:937
void clear()
clear - Removes all bits from the bitvector. Does not change capacity.
Definition: BitVector.h:366
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
Definition: SlotIndexes.h:259
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
const HexagonInstrInfo * TII
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
unsigned getVarIdx() const
Get starting index of non call related arguments (calling convention, statepoint flags, vm state and gc state).
Definition: StackMaps.h:172
bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
const ConstantFP * getFPImm() const
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:411
const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
iterator end()
Definition: LiveInterval.h:211
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:722
Result of a LiveRange query.
Definition: LiveInterval.h:89
static constexpr LaneBitmask getAll()
Definition: LaneBitmask.h:83
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:648
SlotIndex getInstructionIndex(const MachineInstr &MI) const
Returns the base index for the given instruction.
Definition: SlotIndexes.h:411
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Definition: LiveInterval.h:750
SmallVectorImpl< IdxMBBPair >::const_iterator MBBIndexIterator
Iterator over the idx2MBBMap (sorted pairs of slot index of basic block begin and basic block) ...
Definition: SlotIndexes.h:511
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
def_iterator def_begin(unsigned RegNo) const
SparseBitVector AliveBlocks
AliveBlocks - Set of blocks in which this value is alive completely through.
Definition: LiveVariables.h:83
static constexpr LaneBitmask getNone()
Definition: LaneBitmask.h:82
LLT getElementType() const
Returns the vector&#39;s element type. Only valid for vector types.
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
unsigned getEqClass(const VNInfo *VNI) const
getEqClass - Classify creates equivalence classes numbered 0..N.
Definition: LiveInterval.h:937
bool isScopedEHPersonality(EHPersonality Pers)
Returns true if this personality uses scope-style EH IR instructions: catchswitch, catchpad/ret, and cleanuppad/ret.
bool hasRegUnit(unsigned Reg, unsigned RegUnit) const
Returns true if Reg contains RegUnit.
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register. ...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:405
bool isValid() const
isValid - Returns true until all the operands have been visited.
SlotIndexes pass.
Definition: SlotIndexes.h:328
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
Definition: SlotIndexes.h:254
uint64_t getSizeInBits() const
Return the size in bits of the memory reference.
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they&#39;re not in a MachineFuncti...
virtual const TargetInstrInfo * getInstrInfo() const
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
Definition: MachineInstr.h:349
bool isKill() const
Return true if the live-in value is killed by this instruction.
Definition: LiveInterval.h:111
LiveRange * getCachedRegUnit(unsigned Unit)
Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn&#39;t...
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
Definition: LiveInterval.h:104
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
Definition: LiveInterval.h:528
TargetInstrInfo - Interface to description of machine instruction set.
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:408
bool isGenericType() const
Definition: MCInstrDesc.h:97
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:819
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
unsigned const MachineRegisterInfo * MRI
VNInfoList::const_iterator const_vni_iterator
Definition: LiveInterval.h:217
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
bool hasInterval(unsigned Reg) const
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:515
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:95
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
df_ext_iterator< T, SetTy > df_ext_end(const T &G, SetTy &S)
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:388
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
LLVM_NODISCARD bool empty() const
Definition: SmallPtrSet.h:91
unsigned Classify(const LiveRange &LR)
Classify the values in LR into connected components.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:370
bool hasIndex(const MachineInstr &instr) const
Returns true if the given machine instr is mapped to an index, otherwise returns false.
Definition: SlotIndexes.h:406
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:335
virtual bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const
Perform target-specific instruction verification.
unsigned getCallFrameSetupOpcode() const
These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise)...
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
Definition: SlotIndexes.h:490
Represent the analysis usage information of a pass.
df_ext_iterator< T, SetTy > df_ext_begin(const T &G, SetTy &S)
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:548
bool isValid() const
constexpr bool none() const
Definition: LaneBitmask.h:51
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
bool def_empty(unsigned RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
MBBIndexIterator MBBIndexBegin() const
Returns an iterator for the begin of the idx2MBBMap.
Definition: SlotIndexes.h:526
const RegisterBank * getRegBankOrNull(unsigned Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
std::vector< MachineBasicBlock * >::const_iterator const_succ_iterator
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
Definition: SmallPtrSet.h:381
self_iterator getIterator()
Definition: ilist_node.h:81
unsigned getAddressSpace() const
iterator_range< pred_iterator > predecessors()
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
Definition: SlotIndexes.h:500
VarInfo & getVarInfo(unsigned RegIdx)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MachineBasicBlock & front() const
MCSubRegIterator enumerates all sub-registers of Reg.
size_t size() const
Definition: SmallVector.h:52
virtual bool isPredicated(const MachineInstr &MI) const
Returns true if the instruction is already predicated.
bool isDebugInstr() const
Definition: MachineInstr.h:998
void print(raw_ostream &OS, const SlotIndexes *=nullptr) const
print - Print out the MachineFunction in a format suitable for debugging to the specified stream...
bool verify(const TargetRegisterInfo &TRI) const
Check that information hold by this instance make sense for the given TRI.
const APFloat & getValueAPF() const
Definition: Constants.h:302
std::vector< MachineInstr * > Kills
Kills - List of MachineInstruction&#39;s which are the last use of this virtual register (kill it) in the...
Definition: LiveVariables.h:88
size_type size() const
Definition: SmallPtrSet.h:92
unsigned id
The ID number of this value.
Definition: LiveInterval.h:57
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:187
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
Iterator for intrusive lists based on ilist_node.
bool covers(const LiveRange &Other) const
Returns true if all segments of the Other live range are completely covered by this live range...
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false...
Definition: SmallPtrSet.h:377
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
Definition: SlotIndexes.h:197
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:533
Segments::const_iterator const_iterator
Definition: LiveInterval.h:208
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
bool isDebugValue() const
Definition: MachineInstr.h:996
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
Definition: LiveInterval.h:924
MachineOperand class - Representation of each machine instruction operand.
bool isInAllocatableClass(unsigned RegNo) const
Return true if the register is in the allocation of any register class.
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
bool isReservedRegUnit(unsigned Unit) const
Returns true when the given register unit is considered reserved.
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx. ...
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:225
LiveInterval & getInterval(unsigned Reg)
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:606
This class implements the register bank concept.
Definition: RegisterBank.h:28
int64_t getImm() const
unsigned pred_size() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
INITIALIZE_PASS(MachineVerifierPass, "machineverifier", "Verify generated machine code", false, false) FunctionPass *llvm
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarilly including Idx...
Definition: LiveInterval.h:416
void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const
For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
Special value supplied for machine level alias analysis.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
void setPreservesAll()
Set by analyses that do not transform their input at all.
bool isEarlyClobber() const
isEarlyClobber - Returns true if this is an early-clobber slot.
Definition: SlotIndexes.h:229
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
Base class for user error types.
Definition: Error.h:344
VNInfoList valnos
Definition: LiveInterval.h:199
const BitVector & getReservedRegs() const
getReservedRegs - Returns a reference to the frozen set of reserved registers.
unsigned succ_size() const
VNInfo * getValNumInfo(unsigned ValNo)
getValNumInfo - Returns pointer to the specified val#.
Definition: LiveInterval.h:304
bool isPointer() const
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:253
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
unsigned getNumValNums() const
Definition: LiveInterval.h:300
void set_subtract(S1Ty &S1, const S2Ty &S2)
set_subtract(A, B) - Compute A := A - B
Definition: SetOperations.h:62
Representation of each machine instruction.
Definition: MachineInstr.h:63
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
iterator begin() const
Definition: SmallPtrSet.h:396
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
Definition: SlotIndexes.h:289
bool isEHPad() const
Returns true if the block is a landing pad.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use...
#define I(x, y, z)
Definition: MD5.cpp:58
constexpr bool any() const
Definition: LaneBitmask.h:52
MI-level Statepoint operands.
Definition: StackMaps.h:154
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
bool tracksLiveness() const
tracksLiveness - Returns true when tracking register liveness accurately.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
uint32_t Size
Definition: Profile.cpp:46
size_type size() const
size - Returns the number of bits in this bitvector.
Definition: BitVector.h:169
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
Abstract Stack Frame Index.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const
Returns true if liveness for register class RC should be tracked at the subregister level...
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:171
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
iterator_range< livein_iterator > liveins() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator begin()
Definition: LiveInterval.h:210
LLVM_NODISCARD const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:122
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:806
const TargetRegisterClass * getRegClassOrNull(unsigned Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool hasProperty(Property P) const
bool hasInterval(int Slot) const
Definition: LiveStacks.h:77
static def_iterator def_end()
unsigned getSize() const
Get the maximal size in bits that fits in this register bank.
Definition: RegisterBank.h:54
aarch64 promote const
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel...
Definition: TargetOpcodes.h:30
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:129
LLVM Value Representation.
Definition: Value.h:72
Constant * getPersonalityFn() const
Get the personality function associated with this function.
Definition: Function.cpp:1306
mop_iterator operands_begin()
Definition: MachineInstr.h:452
unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
AnalysisType * getAnalysisIfAvailable() const
getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information tha...
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:576
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:203
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg)
unsigned getGenericTypeIndex() const
Definition: MCInstrDesc.h:102
IRTranslator LLVM IR MI
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:639
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
A specialized PseudoSourceValue for holding FixedStack values, which must include a frame index...
ppc ctr loops verify
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:66
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
const ConstantInt * getCImm() const
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:83
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
vni_iterator vni_end()
Definition: LiveInterval.h:220
bool set_union(S1Ty &S1, const S2Ty &S2)
set_union(A, B) - Compute A := A u B, return whether A changed.
Definition: SetOperations.h:22
static LLVM_ATTRIBUTE_UNUSED bool isJointlyDominated(const MachineBasicBlock *MBB, ArrayRef< SlotIndex > Defs, const SlotIndexes &Indexes)
A diagnostic function to check if the end of the block MBB is jointly dominated by the blocks corresp...
hexagon widen stores
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:540
bool isImplicit() const
void resize(size_type N)
Definition: SmallVector.h:344
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1244