LLVM  9.0.0svn
MachineVerifier.cpp
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1 //===- MachineVerifier.cpp - Machine Code Verifier ------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Pass to verify generated machine code. The following is checked:
10 //
11 // Operand counts: All explicit operands must be present.
12 //
13 // Register classes: All physical and virtual register operands must be
14 // compatible with the register class required by the instruction descriptor.
15 //
16 // Register live intervals: Registers must be defined only once, and must be
17 // defined before use.
18 //
19 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
20 // command-line option -verify-machineinstrs, or by defining the environment
21 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
22 // the verifier errors.
23 //===----------------------------------------------------------------------===//
24 
25 #include "LiveRangeCalc.h"
26 #include "llvm/ADT/BitVector.h"
27 #include "llvm/ADT/DenseMap.h"
28 #include "llvm/ADT/DenseSet.h"
30 #include "llvm/ADT/STLExtras.h"
31 #include "llvm/ADT/SetOperations.h"
32 #include "llvm/ADT/SmallPtrSet.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/StringRef.h"
35 #include "llvm/ADT/Twine.h"
53 #include "llvm/CodeGen/StackMaps.h"
58 #include "llvm/IR/BasicBlock.h"
59 #include "llvm/IR/Function.h"
60 #include "llvm/IR/InlineAsm.h"
61 #include "llvm/IR/Instructions.h"
62 #include "llvm/MC/LaneBitmask.h"
63 #include "llvm/MC/MCAsmInfo.h"
64 #include "llvm/MC/MCInstrDesc.h"
65 #include "llvm/MC/MCRegisterInfo.h"
67 #include "llvm/Pass.h"
68 #include "llvm/Support/Casting.h"
74 #include <algorithm>
75 #include <cassert>
76 #include <cstddef>
77 #include <cstdint>
78 #include <iterator>
79 #include <string>
80 #include <utility>
81 
82 using namespace llvm;
83 
84 namespace {
85 
86  struct MachineVerifier {
87  MachineVerifier(Pass *pass, const char *b) : PASS(pass), Banner(b) {}
88 
89  unsigned verify(MachineFunction &MF);
90 
91  Pass *const PASS;
92  const char *Banner;
93  const MachineFunction *MF;
94  const TargetMachine *TM;
95  const TargetInstrInfo *TII;
96  const TargetRegisterInfo *TRI;
97  const MachineRegisterInfo *MRI;
98 
99  unsigned foundErrors;
100 
101  // Avoid querying the MachineFunctionProperties for each operand.
102  bool isFunctionRegBankSelected;
103  bool isFunctionSelected;
104 
105  using RegVector = SmallVector<unsigned, 16>;
106  using RegMaskVector = SmallVector<const uint32_t *, 4>;
107  using RegSet = DenseSet<unsigned>;
110 
111  const MachineInstr *FirstNonPHI;
112  const MachineInstr *FirstTerminator;
113  BlockSet FunctionBlocks;
114 
115  BitVector regsReserved;
116  RegSet regsLive;
117  RegVector regsDefined, regsDead, regsKilled;
118  RegMaskVector regMasks;
119 
120  SlotIndex lastIndex;
121 
122  // Add Reg and any sub-registers to RV
123  void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
124  RV.push_back(Reg);
126  for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
127  RV.push_back(*SubRegs);
128  }
129 
130  struct BBInfo {
131  // Is this MBB reachable from the MF entry point?
132  bool reachable = false;
133 
134  // Vregs that must be live in because they are used without being
135  // defined. Map value is the user.
136  RegMap vregsLiveIn;
137 
138  // Regs killed in MBB. They may be defined again, and will then be in both
139  // regsKilled and regsLiveOut.
140  RegSet regsKilled;
141 
142  // Regs defined in MBB and live out. Note that vregs passing through may
143  // be live out without being mentioned here.
144  RegSet regsLiveOut;
145 
146  // Vregs that pass through MBB untouched. This set is disjoint from
147  // regsKilled and regsLiveOut.
148  RegSet vregsPassed;
149 
150  // Vregs that must pass through MBB because they are needed by a successor
151  // block. This set is disjoint from regsLiveOut.
152  RegSet vregsRequired;
153 
154  // Set versions of block's predecessor and successor lists.
155  BlockSet Preds, Succs;
156 
157  BBInfo() = default;
158 
159  // Add register to vregsPassed if it belongs there. Return true if
160  // anything changed.
161  bool addPassed(unsigned Reg) {
163  return false;
164  if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
165  return false;
166  return vregsPassed.insert(Reg).second;
167  }
168 
169  // Same for a full set.
170  bool addPassed(const RegSet &RS) {
171  bool changed = false;
172  for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
173  if (addPassed(*I))
174  changed = true;
175  return changed;
176  }
177 
178  // Add register to vregsRequired if it belongs there. Return true if
179  // anything changed.
180  bool addRequired(unsigned Reg) {
182  return false;
183  if (regsLiveOut.count(Reg))
184  return false;
185  return vregsRequired.insert(Reg).second;
186  }
187 
188  // Same for a full set.
189  bool addRequired(const RegSet &RS) {
190  bool changed = false;
191  for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
192  if (addRequired(*I))
193  changed = true;
194  return changed;
195  }
196 
197  // Same for a full map.
198  bool addRequired(const RegMap &RM) {
199  bool changed = false;
200  for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
201  if (addRequired(I->first))
202  changed = true;
203  return changed;
204  }
205 
206  // Live-out registers are either in regsLiveOut or vregsPassed.
207  bool isLiveOut(unsigned Reg) const {
208  return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
209  }
210  };
211 
212  // Extra register info per MBB.
214 
215  bool isReserved(unsigned Reg) {
216  return Reg < regsReserved.size() && regsReserved.test(Reg);
217  }
218 
219  bool isAllocatable(unsigned Reg) const {
220  return Reg < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) &&
221  !regsReserved.test(Reg);
222  }
223 
224  // Analysis information if available
225  LiveVariables *LiveVars;
226  LiveIntervals *LiveInts;
227  LiveStacks *LiveStks;
228  SlotIndexes *Indexes;
229 
230  void visitMachineFunctionBefore();
231  void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
232  void visitMachineBundleBefore(const MachineInstr *MI);
233  void visitMachineInstrBefore(const MachineInstr *MI);
234  void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
235  void visitMachineInstrAfter(const MachineInstr *MI);
236  void visitMachineBundleAfter(const MachineInstr *MI);
237  void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
238  void visitMachineFunctionAfter();
239 
240  void report(const char *msg, const MachineFunction *MF);
241  void report(const char *msg, const MachineBasicBlock *MBB);
242  void report(const char *msg, const MachineInstr *MI);
243  void report(const char *msg, const MachineOperand *MO, unsigned MONum,
244  LLT MOVRegType = LLT{});
245 
246  void report_context(const LiveInterval &LI) const;
247  void report_context(const LiveRange &LR, unsigned VRegUnit,
248  LaneBitmask LaneMask) const;
249  void report_context(const LiveRange::Segment &S) const;
250  void report_context(const VNInfo &VNI) const;
251  void report_context(SlotIndex Pos) const;
252  void report_context(MCPhysReg PhysReg) const;
253  void report_context_liverange(const LiveRange &LR) const;
254  void report_context_lanemask(LaneBitmask LaneMask) const;
255  void report_context_vreg(unsigned VReg) const;
256  void report_context_vreg_regunit(unsigned VRegOrUnit) const;
257 
258  void verifyInlineAsm(const MachineInstr *MI);
259 
260  void checkLiveness(const MachineOperand *MO, unsigned MONum);
261  void checkLivenessAtUse(const MachineOperand *MO, unsigned MONum,
262  SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit,
263  LaneBitmask LaneMask = LaneBitmask::getNone());
264  void checkLivenessAtDef(const MachineOperand *MO, unsigned MONum,
265  SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit,
266  bool SubRangeCheck = false,
267  LaneBitmask LaneMask = LaneBitmask::getNone());
268 
269  void markReachable(const MachineBasicBlock *MBB);
270  void calcRegsPassed();
271  void checkPHIOps(const MachineBasicBlock &MBB);
272 
273  void calcRegsRequired();
274  void verifyLiveVariables();
275  void verifyLiveIntervals();
276  void verifyLiveInterval(const LiveInterval&);
277  void verifyLiveRangeValue(const LiveRange&, const VNInfo*, unsigned,
278  LaneBitmask);
279  void verifyLiveRangeSegment(const LiveRange&,
280  const LiveRange::const_iterator I, unsigned,
281  LaneBitmask);
282  void verifyLiveRange(const LiveRange&, unsigned,
283  LaneBitmask LaneMask = LaneBitmask::getNone());
284 
285  void verifyStackFrame();
286 
287  void verifySlotIndexes() const;
288  void verifyProperties(const MachineFunction &MF);
289  };
290 
291  struct MachineVerifierPass : public MachineFunctionPass {
292  static char ID; // Pass ID, replacement for typeid
293 
294  const std::string Banner;
295 
296  MachineVerifierPass(std::string banner = std::string())
297  : MachineFunctionPass(ID), Banner(std::move(banner)) {
299  }
300 
301  void getAnalysisUsage(AnalysisUsage &AU) const override {
302  AU.setPreservesAll();
304  }
305 
306  bool runOnMachineFunction(MachineFunction &MF) override {
307  unsigned FoundErrors = MachineVerifier(this, Banner.c_str()).verify(MF);
308  if (FoundErrors)
309  report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
310  return false;
311  }
312  };
313 
314 } // end anonymous namespace
315 
316 char MachineVerifierPass::ID = 0;
317 
318 INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
319  "Verify generated machine code", false, false)
320 
322  return new MachineVerifierPass(Banner);
323 }
324 
325 bool MachineFunction::verify(Pass *p, const char *Banner, bool AbortOnErrors)
326  const {
327  MachineFunction &MF = const_cast<MachineFunction&>(*this);
328  unsigned FoundErrors = MachineVerifier(p, Banner).verify(MF);
329  if (AbortOnErrors && FoundErrors)
330  report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
331  return FoundErrors == 0;
332 }
333 
334 void MachineVerifier::verifySlotIndexes() const {
335  if (Indexes == nullptr)
336  return;
337 
338  // Ensure the IdxMBB list is sorted by slot indexes.
339  SlotIndex Last;
341  E = Indexes->MBBIndexEnd(); I != E; ++I) {
342  assert(!Last.isValid() || I->first > Last);
343  Last = I->first;
344  }
345 }
346 
347 void MachineVerifier::verifyProperties(const MachineFunction &MF) {
348  // If a pass has introduced virtual registers without clearing the
349  // NoVRegs property (or set it without allocating the vregs)
350  // then report an error.
351  if (MF.getProperties().hasProperty(
353  MRI->getNumVirtRegs())
354  report("Function has NoVRegs property but there are VReg operands", &MF);
355 }
356 
358  foundErrors = 0;
359 
360  this->MF = &MF;
361  TM = &MF.getTarget();
362  TII = MF.getSubtarget().getInstrInfo();
363  TRI = MF.getSubtarget().getRegisterInfo();
364  MRI = &MF.getRegInfo();
365 
366  const bool isFunctionFailedISel = MF.getProperties().hasProperty(
368 
369  // If we're mid-GlobalISel and we already triggered the fallback path then
370  // it's expected that the MIR is somewhat broken but that's ok since we'll
371  // reset it and clear the FailedISel attribute in ResetMachineFunctions.
372  if (isFunctionFailedISel)
373  return foundErrors;
374 
375  isFunctionRegBankSelected =
376  !isFunctionFailedISel &&
379  isFunctionSelected = !isFunctionFailedISel &&
382  LiveVars = nullptr;
383  LiveInts = nullptr;
384  LiveStks = nullptr;
385  Indexes = nullptr;
386  if (PASS) {
387  LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
388  // We don't want to verify LiveVariables if LiveIntervals is available.
389  if (!LiveInts)
390  LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
391  LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
392  Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
393  }
394 
395  verifySlotIndexes();
396 
397  verifyProperties(MF);
398 
399  visitMachineFunctionBefore();
400  for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
401  MFI!=MFE; ++MFI) {
402  visitMachineBasicBlockBefore(&*MFI);
403  // Keep track of the current bundle header.
404  const MachineInstr *CurBundle = nullptr;
405  // Do we expect the next instruction to be part of the same bundle?
406  bool InBundle = false;
407 
408  for (MachineBasicBlock::const_instr_iterator MBBI = MFI->instr_begin(),
409  MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) {
410  if (MBBI->getParent() != &*MFI) {
411  report("Bad instruction parent pointer", &*MFI);
412  errs() << "Instruction: " << *MBBI;
413  continue;
414  }
415 
416  // Check for consistent bundle flags.
417  if (InBundle && !MBBI->isBundledWithPred())
418  report("Missing BundledPred flag, "
419  "BundledSucc was set on predecessor",
420  &*MBBI);
421  if (!InBundle && MBBI->isBundledWithPred())
422  report("BundledPred flag is set, "
423  "but BundledSucc not set on predecessor",
424  &*MBBI);
425 
426  // Is this a bundle header?
427  if (!MBBI->isInsideBundle()) {
428  if (CurBundle)
429  visitMachineBundleAfter(CurBundle);
430  CurBundle = &*MBBI;
431  visitMachineBundleBefore(CurBundle);
432  } else if (!CurBundle)
433  report("No bundle header", &*MBBI);
434  visitMachineInstrBefore(&*MBBI);
435  for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
436  const MachineInstr &MI = *MBBI;
437  const MachineOperand &Op = MI.getOperand(I);
438  if (Op.getParent() != &MI) {
439  // Make sure to use correct addOperand / RemoveOperand / ChangeTo
440  // functions when replacing operands of a MachineInstr.
441  report("Instruction has operand with wrong parent set", &MI);
442  }
443 
444  visitMachineOperand(&Op, I);
445  }
446 
447  visitMachineInstrAfter(&*MBBI);
448 
449  // Was this the last bundled instruction?
450  InBundle = MBBI->isBundledWithSucc();
451  }
452  if (CurBundle)
453  visitMachineBundleAfter(CurBundle);
454  if (InBundle)
455  report("BundledSucc flag set on last instruction in block", &MFI->back());
456  visitMachineBasicBlockAfter(&*MFI);
457  }
458  visitMachineFunctionAfter();
459 
460  // Clean up.
461  regsLive.clear();
462  regsDefined.clear();
463  regsDead.clear();
464  regsKilled.clear();
465  regMasks.clear();
466  MBBInfoMap.clear();
467 
468  return foundErrors;
469 }
470 
471 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
472  assert(MF);
473  errs() << '\n';
474  if (!foundErrors++) {
475  if (Banner)
476  errs() << "# " << Banner << '\n';
477  if (LiveInts != nullptr)
478  LiveInts->print(errs());
479  else
480  MF->print(errs(), Indexes);
481  }
482  errs() << "*** Bad machine code: " << msg << " ***\n"
483  << "- function: " << MF->getName() << "\n";
484 }
485 
486 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
487  assert(MBB);
488  report(msg, MBB->getParent());
489  errs() << "- basic block: " << printMBBReference(*MBB) << ' '
490  << MBB->getName() << " (" << (const void *)MBB << ')';
491  if (Indexes)
492  errs() << " [" << Indexes->getMBBStartIdx(MBB)
493  << ';' << Indexes->getMBBEndIdx(MBB) << ')';
494  errs() << '\n';
495 }
496 
497 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
498  assert(MI);
499  report(msg, MI->getParent());
500  errs() << "- instruction: ";
501  if (Indexes && Indexes->hasIndex(*MI))
502  errs() << Indexes->getInstructionIndex(*MI) << '\t';
503  MI->print(errs(), /*SkipOpers=*/true);
504 }
505 
506 void MachineVerifier::report(const char *msg, const MachineOperand *MO,
507  unsigned MONum, LLT MOVRegType) {
508  assert(MO);
509  report(msg, MO->getParent());
510  errs() << "- operand " << MONum << ": ";
511  MO->print(errs(), MOVRegType, TRI);
512  errs() << "\n";
513 }
514 
515 void MachineVerifier::report_context(SlotIndex Pos) const {
516  errs() << "- at: " << Pos << '\n';
517 }
518 
519 void MachineVerifier::report_context(const LiveInterval &LI) const {
520  errs() << "- interval: " << LI << '\n';
521 }
522 
523 void MachineVerifier::report_context(const LiveRange &LR, unsigned VRegUnit,
524  LaneBitmask LaneMask) const {
525  report_context_liverange(LR);
526  report_context_vreg_regunit(VRegUnit);
527  if (LaneMask.any())
528  report_context_lanemask(LaneMask);
529 }
530 
531 void MachineVerifier::report_context(const LiveRange::Segment &S) const {
532  errs() << "- segment: " << S << '\n';
533 }
534 
535 void MachineVerifier::report_context(const VNInfo &VNI) const {
536  errs() << "- ValNo: " << VNI.id << " (def " << VNI.def << ")\n";
537 }
538 
539 void MachineVerifier::report_context_liverange(const LiveRange &LR) const {
540  errs() << "- liverange: " << LR << '\n';
541 }
542 
543 void MachineVerifier::report_context(MCPhysReg PReg) const {
544  errs() << "- p. register: " << printReg(PReg, TRI) << '\n';
545 }
546 
547 void MachineVerifier::report_context_vreg(unsigned VReg) const {
548  errs() << "- v. register: " << printReg(VReg, TRI) << '\n';
549 }
550 
551 void MachineVerifier::report_context_vreg_regunit(unsigned VRegOrUnit) const {
552  if (TargetRegisterInfo::isVirtualRegister(VRegOrUnit)) {
553  report_context_vreg(VRegOrUnit);
554  } else {
555  errs() << "- regunit: " << printRegUnit(VRegOrUnit, TRI) << '\n';
556  }
557 }
558 
559 void MachineVerifier::report_context_lanemask(LaneBitmask LaneMask) const {
560  errs() << "- lanemask: " << PrintLaneMask(LaneMask) << '\n';
561 }
562 
563 void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
564  BBInfo &MInfo = MBBInfoMap[MBB];
565  if (!MInfo.reachable) {
566  MInfo.reachable = true;
568  SuE = MBB->succ_end(); SuI != SuE; ++SuI)
569  markReachable(*SuI);
570  }
571 }
572 
573 void MachineVerifier::visitMachineFunctionBefore() {
574  lastIndex = SlotIndex();
575  regsReserved = MRI->reservedRegsFrozen() ? MRI->getReservedRegs()
576  : TRI->getReservedRegs(*MF);
577 
578  if (!MF->empty())
579  markReachable(&MF->front());
580 
581  // Build a set of the basic blocks in the function.
582  FunctionBlocks.clear();
583  for (const auto &MBB : *MF) {
584  FunctionBlocks.insert(&MBB);
585  BBInfo &MInfo = MBBInfoMap[&MBB];
586 
587  MInfo.Preds.insert(MBB.pred_begin(), MBB.pred_end());
588  if (MInfo.Preds.size() != MBB.pred_size())
589  report("MBB has duplicate entries in its predecessor list.", &MBB);
590 
591  MInfo.Succs.insert(MBB.succ_begin(), MBB.succ_end());
592  if (MInfo.Succs.size() != MBB.succ_size())
593  report("MBB has duplicate entries in its successor list.", &MBB);
594  }
595 
596  // Check that the register use lists are sane.
597  MRI->verifyUseLists();
598 
599  if (!MF->empty())
600  verifyStackFrame();
601 }
602 
603 // Does iterator point to a and b as the first two elements?
605  const MachineBasicBlock *a, const MachineBasicBlock *b) {
606  if (*i == a)
607  return *++i == b;
608  if (*i == b)
609  return *++i == a;
610  return false;
611 }
612 
613 void
614 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
615  FirstTerminator = nullptr;
616  FirstNonPHI = nullptr;
617 
618  if (!MF->getProperties().hasProperty(
620  // If this block has allocatable physical registers live-in, check that
621  // it is an entry block or landing pad.
622  for (const auto &LI : MBB->liveins()) {
623  if (isAllocatable(LI.PhysReg) && !MBB->isEHPad() &&
624  MBB->getIterator() != MBB->getParent()->begin()) {
625  report("MBB has allocatable live-in, but isn't entry or landing-pad.", MBB);
626  report_context(LI.PhysReg);
627  }
628  }
629  }
630 
631  // Count the number of landing pad successors.
632  SmallPtrSet<MachineBasicBlock*, 4> LandingPadSuccs;
634  E = MBB->succ_end(); I != E; ++I) {
635  if ((*I)->isEHPad())
636  LandingPadSuccs.insert(*I);
637  if (!FunctionBlocks.count(*I))
638  report("MBB has successor that isn't part of the function.", MBB);
639  if (!MBBInfoMap[*I].Preds.count(MBB)) {
640  report("Inconsistent CFG", MBB);
641  errs() << "MBB is not in the predecessor list of the successor "
642  << printMBBReference(*(*I)) << ".\n";
643  }
644  }
645 
646  // Check the predecessor list.
648  E = MBB->pred_end(); I != E; ++I) {
649  if (!FunctionBlocks.count(*I))
650  report("MBB has predecessor that isn't part of the function.", MBB);
651  if (!MBBInfoMap[*I].Succs.count(MBB)) {
652  report("Inconsistent CFG", MBB);
653  errs() << "MBB is not in the successor list of the predecessor "
654  << printMBBReference(*(*I)) << ".\n";
655  }
656  }
657 
658  const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
659  const BasicBlock *BB = MBB->getBasicBlock();
660  const Function &F = MF->getFunction();
661  if (LandingPadSuccs.size() > 1 &&
662  !(AsmInfo &&
664  BB && isa<SwitchInst>(BB->getTerminator())) &&
666  report("MBB has more than one landing pad successor", MBB);
667 
668  // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
669  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
671  if (!TII->analyzeBranch(*const_cast<MachineBasicBlock *>(MBB), TBB, FBB,
672  Cond)) {
673  // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
674  // check whether its answers match up with reality.
675  if (!TBB && !FBB) {
676  // Block falls through to its successor.
678  ++MBBI;
679  if (MBBI == MF->end()) {
680  // It's possible that the block legitimately ends with a noreturn
681  // call or an unreachable, in which case it won't actually fall
682  // out the bottom of the function.
683  } else if (MBB->succ_size() == LandingPadSuccs.size()) {
684  // It's possible that the block legitimately ends with a noreturn
685  // call or an unreachable, in which case it won't actually fall
686  // out of the block.
687  } else if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
688  report("MBB exits via unconditional fall-through but doesn't have "
689  "exactly one CFG successor!", MBB);
690  } else if (!MBB->isSuccessor(&*MBBI)) {
691  report("MBB exits via unconditional fall-through but its successor "
692  "differs from its CFG successor!", MBB);
693  }
694  if (!MBB->empty() && MBB->back().isBarrier() &&
695  !TII->isPredicated(MBB->back())) {
696  report("MBB exits via unconditional fall-through but ends with a "
697  "barrier instruction!", MBB);
698  }
699  if (!Cond.empty()) {
700  report("MBB exits via unconditional fall-through but has a condition!",
701  MBB);
702  }
703  } else if (TBB && !FBB && Cond.empty()) {
704  // Block unconditionally branches somewhere.
705  // If the block has exactly one successor, that happens to be a
706  // landingpad, accept it as valid control flow.
707  if (MBB->succ_size() != 1+LandingPadSuccs.size() &&
708  (MBB->succ_size() != 1 || LandingPadSuccs.size() != 1 ||
709  *MBB->succ_begin() != *LandingPadSuccs.begin())) {
710  report("MBB exits via unconditional branch but doesn't have "
711  "exactly one CFG successor!", MBB);
712  } else if (!MBB->isSuccessor(TBB)) {
713  report("MBB exits via unconditional branch but the CFG "
714  "successor doesn't match the actual successor!", MBB);
715  }
716  if (MBB->empty()) {
717  report("MBB exits via unconditional branch but doesn't contain "
718  "any instructions!", MBB);
719  } else if (!MBB->back().isBarrier()) {
720  report("MBB exits via unconditional branch but doesn't end with a "
721  "barrier instruction!", MBB);
722  } else if (!MBB->back().isTerminator()) {
723  report("MBB exits via unconditional branch but the branch isn't a "
724  "terminator instruction!", MBB);
725  }
726  } else if (TBB && !FBB && !Cond.empty()) {
727  // Block conditionally branches somewhere, otherwise falls through.
729  ++MBBI;
730  if (MBBI == MF->end()) {
731  report("MBB conditionally falls through out of function!", MBB);
732  } else if (MBB->succ_size() == 1) {
733  // A conditional branch with only one successor is weird, but allowed.
734  if (&*MBBI != TBB)
735  report("MBB exits via conditional branch/fall-through but only has "
736  "one CFG successor!", MBB);
737  else if (TBB != *MBB->succ_begin())
738  report("MBB exits via conditional branch/fall-through but the CFG "
739  "successor don't match the actual successor!", MBB);
740  } else if (MBB->succ_size() != 2) {
741  report("MBB exits via conditional branch/fall-through but doesn't have "
742  "exactly two CFG successors!", MBB);
743  } else if (!matchPair(MBB->succ_begin(), TBB, &*MBBI)) {
744  report("MBB exits via conditional branch/fall-through but the CFG "
745  "successors don't match the actual successors!", MBB);
746  }
747  if (MBB->empty()) {
748  report("MBB exits via conditional branch/fall-through but doesn't "
749  "contain any instructions!", MBB);
750  } else if (MBB->back().isBarrier()) {
751  report("MBB exits via conditional branch/fall-through but ends with a "
752  "barrier instruction!", MBB);
753  } else if (!MBB->back().isTerminator()) {
754  report("MBB exits via conditional branch/fall-through but the branch "
755  "isn't a terminator instruction!", MBB);
756  }
757  } else if (TBB && FBB) {
758  // Block conditionally branches somewhere, otherwise branches
759  // somewhere else.
760  if (MBB->succ_size() == 1) {
761  // A conditional branch with only one successor is weird, but allowed.
762  if (FBB != TBB)
763  report("MBB exits via conditional branch/branch through but only has "
764  "one CFG successor!", MBB);
765  else if (TBB != *MBB->succ_begin())
766  report("MBB exits via conditional branch/branch through but the CFG "
767  "successor don't match the actual successor!", MBB);
768  } else if (MBB->succ_size() != 2) {
769  report("MBB exits via conditional branch/branch but doesn't have "
770  "exactly two CFG successors!", MBB);
771  } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
772  report("MBB exits via conditional branch/branch but the CFG "
773  "successors don't match the actual successors!", MBB);
774  }
775  if (MBB->empty()) {
776  report("MBB exits via conditional branch/branch but doesn't "
777  "contain any instructions!", MBB);
778  } else if (!MBB->back().isBarrier()) {
779  report("MBB exits via conditional branch/branch but doesn't end with a "
780  "barrier instruction!", MBB);
781  } else if (!MBB->back().isTerminator()) {
782  report("MBB exits via conditional branch/branch but the branch "
783  "isn't a terminator instruction!", MBB);
784  }
785  if (Cond.empty()) {
786  report("MBB exits via conditional branch/branch but there's no "
787  "condition!", MBB);
788  }
789  } else {
790  report("AnalyzeBranch returned invalid data!", MBB);
791  }
792  }
793 
794  regsLive.clear();
795  if (MRI->tracksLiveness()) {
796  for (const auto &LI : MBB->liveins()) {
797  if (!TargetRegisterInfo::isPhysicalRegister(LI.PhysReg)) {
798  report("MBB live-in list contains non-physical register", MBB);
799  continue;
800  }
801  for (MCSubRegIterator SubRegs(LI.PhysReg, TRI, /*IncludeSelf=*/true);
802  SubRegs.isValid(); ++SubRegs)
803  regsLive.insert(*SubRegs);
804  }
805  }
806 
807  const MachineFrameInfo &MFI = MF->getFrameInfo();
808  BitVector PR = MFI.getPristineRegs(*MF);
809  for (unsigned I : PR.set_bits()) {
810  for (MCSubRegIterator SubRegs(I, TRI, /*IncludeSelf=*/true);
811  SubRegs.isValid(); ++SubRegs)
812  regsLive.insert(*SubRegs);
813  }
814 
815  regsKilled.clear();
816  regsDefined.clear();
817 
818  if (Indexes)
819  lastIndex = Indexes->getMBBStartIdx(MBB);
820 }
821 
822 // This function gets called for all bundle headers, including normal
823 // stand-alone unbundled instructions.
824 void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
825  if (Indexes && Indexes->hasIndex(*MI)) {
826  SlotIndex idx = Indexes->getInstructionIndex(*MI);
827  if (!(idx > lastIndex)) {
828  report("Instruction index out of order", MI);
829  errs() << "Last instruction was at " << lastIndex << '\n';
830  }
831  lastIndex = idx;
832  }
833 
834  // Ensure non-terminators don't follow terminators.
835  // Ignore predicated terminators formed by if conversion.
836  // FIXME: If conversion shouldn't need to violate this rule.
837  if (MI->isTerminator() && !TII->isPredicated(*MI)) {
838  if (!FirstTerminator)
839  FirstTerminator = MI;
840  } else if (FirstTerminator) {
841  report("Non-terminator instruction after the first terminator", MI);
842  errs() << "First terminator was:\t" << *FirstTerminator;
843  }
844 }
845 
846 // The operands on an INLINEASM instruction must follow a template.
847 // Verify that the flag operands make sense.
848 void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) {
849  // The first two operands on INLINEASM are the asm string and global flags.
850  if (MI->getNumOperands() < 2) {
851  report("Too few operands on inline asm", MI);
852  return;
853  }
854  if (!MI->getOperand(0).isSymbol())
855  report("Asm string must be an external symbol", MI);
856  if (!MI->getOperand(1).isImm())
857  report("Asm flags must be an immediate", MI);
858  // Allowed flags are Extra_HasSideEffects = 1, Extra_IsAlignStack = 2,
859  // Extra_AsmDialect = 4, Extra_MayLoad = 8, and Extra_MayStore = 16,
860  // and Extra_IsConvergent = 32.
861  if (!isUInt<6>(MI->getOperand(1).getImm()))
862  report("Unknown asm flags", &MI->getOperand(1), 1);
863 
864  static_assert(InlineAsm::MIOp_FirstOperand == 2, "Asm format changed");
865 
866  unsigned OpNo = InlineAsm::MIOp_FirstOperand;
867  unsigned NumOps;
868  for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
869  const MachineOperand &MO = MI->getOperand(OpNo);
870  // There may be implicit ops after the fixed operands.
871  if (!MO.isImm())
872  break;
873  NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
874  }
875 
876  if (OpNo > MI->getNumOperands())
877  report("Missing operands in last group", MI);
878 
879  // An optional MDNode follows the groups.
880  if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata())
881  ++OpNo;
882 
883  // All trailing operands must be implicit registers.
884  for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) {
885  const MachineOperand &MO = MI->getOperand(OpNo);
886  if (!MO.isReg() || !MO.isImplicit())
887  report("Expected implicit register after groups", &MO, OpNo);
888  }
889 }
890 
891 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
892  const MCInstrDesc &MCID = MI->getDesc();
893  if (MI->getNumOperands() < MCID.getNumOperands()) {
894  report("Too few operands", MI);
895  errs() << MCID.getNumOperands() << " operands expected, but "
896  << MI->getNumOperands() << " given.\n";
897  }
898 
899  if (MI->isPHI()) {
900  if (MF->getProperties().hasProperty(
902  report("Found PHI instruction with NoPHIs property set", MI);
903 
904  if (FirstNonPHI)
905  report("Found PHI instruction after non-PHI", MI);
906  } else if (FirstNonPHI == nullptr)
907  FirstNonPHI = MI;
908 
909  // Check the tied operands.
910  if (MI->isInlineAsm())
911  verifyInlineAsm(MI);
912 
913  // Check the MachineMemOperands for basic consistency.
915  E = MI->memoperands_end();
916  I != E; ++I) {
917  if ((*I)->isLoad() && !MI->mayLoad())
918  report("Missing mayLoad flag", MI);
919  if ((*I)->isStore() && !MI->mayStore())
920  report("Missing mayStore flag", MI);
921  }
922 
923  // Debug values must not have a slot index.
924  // Other instructions must have one, unless they are inside a bundle.
925  if (LiveInts) {
926  bool mapped = !LiveInts->isNotInMIMap(*MI);
927  if (MI->isDebugInstr()) {
928  if (mapped)
929  report("Debug instruction has a slot index", MI);
930  } else if (MI->isInsideBundle()) {
931  if (mapped)
932  report("Instruction inside bundle has a slot index", MI);
933  } else {
934  if (!mapped)
935  report("Missing slot index", MI);
936  }
937  }
938 
939  if (isPreISelGenericOpcode(MCID.getOpcode())) {
940  if (isFunctionSelected)
941  report("Unexpected generic instruction in a Selected function", MI);
942 
943  // Check types.
944  SmallVector<LLT, 4> Types;
945  for (unsigned I = 0; I < MCID.getNumOperands(); ++I) {
946  if (!MCID.OpInfo[I].isGenericType())
947  continue;
948  // Generic instructions specify type equality constraints between some of
949  // their operands. Make sure these are consistent.
950  size_t TypeIdx = MCID.OpInfo[I].getGenericTypeIndex();
951  Types.resize(std::max(TypeIdx + 1, Types.size()));
952 
953  const MachineOperand *MO = &MI->getOperand(I);
954  LLT OpTy = MRI->getType(MO->getReg());
955  // Don't report a type mismatch if there is no actual mismatch, only a
956  // type missing, to reduce noise:
957  if (OpTy.isValid()) {
958  // Only the first valid type for a type index will be printed: don't
959  // overwrite it later so it's always clear which type was expected:
960  if (!Types[TypeIdx].isValid())
961  Types[TypeIdx] = OpTy;
962  else if (Types[TypeIdx] != OpTy)
963  report("Type mismatch in generic instruction", MO, I, OpTy);
964  } else {
965  // Generic instructions must have types attached to their operands.
966  report("Generic instruction is missing a virtual register type", MO, I);
967  }
968  }
969 
970  // Generic opcodes must not have physical register operands.
971  for (unsigned I = 0; I < MI->getNumOperands(); ++I) {
972  const MachineOperand *MO = &MI->getOperand(I);
974  report("Generic instruction cannot have physical register", MO, I);
975  }
976  }
977 
979  if (!TII->verifyInstruction(*MI, ErrorInfo))
980  report(ErrorInfo.data(), MI);
981 
982  // Verify properties of various specific instruction types
983  switch(MI->getOpcode()) {
984  default:
985  break;
986  case TargetOpcode::G_LOAD:
987  case TargetOpcode::G_STORE:
988  // Generic loads and stores must have a single MachineMemOperand
989  // describing that access.
990  if (!MI->hasOneMemOperand())
991  report("Generic instruction accessing memory must have one mem operand",
992  MI);
993  break;
994  case TargetOpcode::G_PHI: {
995  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
996  if (!DstTy.isValid() ||
997  !std::all_of(MI->operands_begin() + 1, MI->operands_end(),
998  [this, &DstTy](const MachineOperand &MO) {
999  if (!MO.isReg())
1000  return true;
1001  LLT Ty = MRI->getType(MO.getReg());
1002  if (!Ty.isValid() || (Ty != DstTy))
1003  return false;
1004  return true;
1005  }))
1006  report("Generic Instruction G_PHI has operands with incompatible/missing "
1007  "types",
1008  MI);
1009  break;
1010  }
1011  case TargetOpcode::G_BITCAST: {
1012  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1013  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1014  if (!DstTy.isValid() || !SrcTy.isValid())
1015  break;
1016 
1017  if (SrcTy.isPointer() != DstTy.isPointer())
1018  report("bitcast cannot convert between pointers and other types", MI);
1019 
1020  if (SrcTy.getSizeInBits() != DstTy.getSizeInBits())
1021  report("bitcast sizes must match", MI);
1022  break;
1023  }
1024  case TargetOpcode::G_SEXT:
1025  case TargetOpcode::G_ZEXT:
1026  case TargetOpcode::G_ANYEXT:
1027  case TargetOpcode::G_TRUNC:
1028  case TargetOpcode::G_FPEXT:
1029  case TargetOpcode::G_FPTRUNC: {
1030  // Number of operands and presense of types is already checked (and
1031  // reported in case of any issues), so no need to report them again. As
1032  // we're trying to report as many issues as possible at once, however, the
1033  // instructions aren't guaranteed to have the right number of operands or
1034  // types attached to them at this point
1035  assert(MCID.getNumOperands() == 2 && "Expected 2 operands G_*{EXT,TRUNC}");
1036  if (MI->getNumOperands() < MCID.getNumOperands())
1037  break;
1038  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1039  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1040  if (!DstTy.isValid() || !SrcTy.isValid())
1041  break;
1042 
1043  LLT DstElTy = DstTy.isVector() ? DstTy.getElementType() : DstTy;
1044  LLT SrcElTy = SrcTy.isVector() ? SrcTy.getElementType() : SrcTy;
1045  if (DstElTy.isPointer() || SrcElTy.isPointer())
1046  report("Generic extend/truncate can not operate on pointers", MI);
1047 
1048  if (DstTy.isVector() != SrcTy.isVector()) {
1049  report("Generic extend/truncate must be all-vector or all-scalar", MI);
1050  // Generally we try to report as many issues as possible at once, but in
1051  // this case it's not clear what should we be comparing the size of the
1052  // scalar with: the size of the whole vector or its lane. Instead of
1053  // making an arbitrary choice and emitting not so helpful message, let's
1054  // avoid the extra noise and stop here.
1055  break;
1056  }
1057  if (DstTy.isVector() && DstTy.getNumElements() != SrcTy.getNumElements())
1058  report("Generic vector extend/truncate must preserve number of lanes",
1059  MI);
1060  unsigned DstSize = DstElTy.getSizeInBits();
1061  unsigned SrcSize = SrcElTy.getSizeInBits();
1062  switch (MI->getOpcode()) {
1063  default:
1064  if (DstSize <= SrcSize)
1065  report("Generic extend has destination type no larger than source", MI);
1066  break;
1067  case TargetOpcode::G_TRUNC:
1068  case TargetOpcode::G_FPTRUNC:
1069  if (DstSize >= SrcSize)
1070  report("Generic truncate has destination type no smaller than source",
1071  MI);
1072  break;
1073  }
1074  break;
1075  }
1076  case TargetOpcode::G_MERGE_VALUES: {
1077  // G_MERGE_VALUES should only be used to merge scalars into a larger scalar,
1078  // e.g. s2N = MERGE sN, sN
1079  // Merging multiple scalars into a vector is not allowed, should use
1080  // G_BUILD_VECTOR for that.
1081  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1082  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1083  if (DstTy.isVector() || SrcTy.isVector())
1084  report("G_MERGE_VALUES cannot operate on vectors", MI);
1085  break;
1086  }
1087  case TargetOpcode::G_UNMERGE_VALUES: {
1088  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1089  LLT SrcTy = MRI->getType(MI->getOperand(MI->getNumOperands()-1).getReg());
1090  // For now G_UNMERGE can split vectors.
1091  for (unsigned i = 0; i < MI->getNumOperands()-1; ++i) {
1092  if (MRI->getType(MI->getOperand(i).getReg()) != DstTy)
1093  report("G_UNMERGE_VALUES destination types do not match", MI);
1094  }
1095  if (SrcTy.getSizeInBits() !=
1096  (DstTy.getSizeInBits() * (MI->getNumOperands() - 1))) {
1097  report("G_UNMERGE_VALUES source operand does not cover dest operands",
1098  MI);
1099  }
1100  break;
1101  }
1102  case TargetOpcode::G_BUILD_VECTOR: {
1103  // Source types must be scalars, dest type a vector. Total size of scalars
1104  // must match the dest vector size.
1105  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1106  LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1107  if (!DstTy.isVector() || SrcEltTy.isVector())
1108  report("G_BUILD_VECTOR must produce a vector from scalar operands", MI);
1109  for (unsigned i = 2; i < MI->getNumOperands(); ++i) {
1110  if (MRI->getType(MI->getOperand(1).getReg()) !=
1111  MRI->getType(MI->getOperand(i).getReg()))
1112  report("G_BUILD_VECTOR source operand types are not homogeneous", MI);
1113  }
1114  if (DstTy.getSizeInBits() !=
1115  SrcEltTy.getSizeInBits() * (MI->getNumOperands() - 1))
1116  report("G_BUILD_VECTOR src operands total size don't match dest "
1117  "size.",
1118  MI);
1119  break;
1120  }
1121  case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1122  // Source types must be scalars, dest type a vector. Scalar types must be
1123  // larger than the dest vector elt type, as this is a truncating operation.
1124  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1125  LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1126  if (!DstTy.isVector() || SrcEltTy.isVector())
1127  report("G_BUILD_VECTOR_TRUNC must produce a vector from scalar operands",
1128  MI);
1129  for (unsigned i = 2; i < MI->getNumOperands(); ++i) {
1130  if (MRI->getType(MI->getOperand(1).getReg()) !=
1131  MRI->getType(MI->getOperand(i).getReg()))
1132  report("G_BUILD_VECTOR_TRUNC source operand types are not homogeneous",
1133  MI);
1134  }
1135  if (SrcEltTy.getSizeInBits() <= DstTy.getElementType().getSizeInBits())
1136  report("G_BUILD_VECTOR_TRUNC source operand types are not larger than "
1137  "dest elt type",
1138  MI);
1139  break;
1140  }
1141  case TargetOpcode::G_CONCAT_VECTORS: {
1142  // Source types should be vectors, and total size should match the dest
1143  // vector size.
1144  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1145  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1146  if (!DstTy.isVector() || !SrcTy.isVector())
1147  report("G_CONCAT_VECTOR requires vector source and destination operands",
1148  MI);
1149  for (unsigned i = 2; i < MI->getNumOperands(); ++i) {
1150  if (MRI->getType(MI->getOperand(1).getReg()) !=
1151  MRI->getType(MI->getOperand(i).getReg()))
1152  report("G_CONCAT_VECTOR source operand types are not homogeneous", MI);
1153  }
1154  if (DstTy.getNumElements() !=
1155  SrcTy.getNumElements() * (MI->getNumOperands() - 1))
1156  report("G_CONCAT_VECTOR num dest and source elements should match", MI);
1157  break;
1158  }
1159  case TargetOpcode::COPY: {
1160  if (foundErrors)
1161  break;
1162  const MachineOperand &DstOp = MI->getOperand(0);
1163  const MachineOperand &SrcOp = MI->getOperand(1);
1164  LLT DstTy = MRI->getType(DstOp.getReg());
1165  LLT SrcTy = MRI->getType(SrcOp.getReg());
1166  if (SrcTy.isValid() && DstTy.isValid()) {
1167  // If both types are valid, check that the types are the same.
1168  if (SrcTy != DstTy) {
1169  report("Copy Instruction is illegal with mismatching types", MI);
1170  errs() << "Def = " << DstTy << ", Src = " << SrcTy << "\n";
1171  }
1172  }
1173  if (SrcTy.isValid() || DstTy.isValid()) {
1174  // If one of them have valid types, let's just check they have the same
1175  // size.
1176  unsigned SrcSize = TRI->getRegSizeInBits(SrcOp.getReg(), *MRI);
1177  unsigned DstSize = TRI->getRegSizeInBits(DstOp.getReg(), *MRI);
1178  assert(SrcSize && "Expecting size here");
1179  assert(DstSize && "Expecting size here");
1180  if (SrcSize != DstSize)
1181  if (!DstOp.getSubReg() && !SrcOp.getSubReg()) {
1182  report("Copy Instruction is illegal with mismatching sizes", MI);
1183  errs() << "Def Size = " << DstSize << ", Src Size = " << SrcSize
1184  << "\n";
1185  }
1186  }
1187  break;
1188  }
1189  case TargetOpcode::G_ICMP:
1190  case TargetOpcode::G_FCMP: {
1191  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1192  LLT SrcTy = MRI->getType(MI->getOperand(2).getReg());
1193 
1194  if ((DstTy.isVector() != SrcTy.isVector()) ||
1195  (DstTy.isVector() && DstTy.getNumElements() != SrcTy.getNumElements()))
1196  report("Generic vector icmp/fcmp must preserve number of lanes", MI);
1197 
1198  break;
1199  }
1200  case TargetOpcode::STATEPOINT:
1201  if (!MI->getOperand(StatepointOpers::IDPos).isImm() ||
1204  report("meta operands to STATEPOINT not constant!", MI);
1205  break;
1206 
1207  auto VerifyStackMapConstant = [&](unsigned Offset) {
1208  if (!MI->getOperand(Offset).isImm() ||
1209  MI->getOperand(Offset).getImm() != StackMaps::ConstantOp ||
1210  !MI->getOperand(Offset + 1).isImm())
1211  report("stack map constant to STATEPOINT not well formed!", MI);
1212  };
1213  const unsigned VarStart = StatepointOpers(MI).getVarIdx();
1214  VerifyStackMapConstant(VarStart + StatepointOpers::CCOffset);
1215  VerifyStackMapConstant(VarStart + StatepointOpers::FlagsOffset);
1216  VerifyStackMapConstant(VarStart + StatepointOpers::NumDeoptOperandsOffset);
1217 
1218  // TODO: verify we have properly encoded deopt arguments
1219  };
1220 }
1221 
1222 void
1223 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
1224  const MachineInstr *MI = MO->getParent();
1225  const MCInstrDesc &MCID = MI->getDesc();
1226  unsigned NumDefs = MCID.getNumDefs();
1227  if (MCID.getOpcode() == TargetOpcode::PATCHPOINT)
1228  NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0;
1229 
1230  // The first MCID.NumDefs operands must be explicit register defines
1231  if (MONum < NumDefs) {
1232  const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
1233  if (!MO->isReg())
1234  report("Explicit definition must be a register", MO, MONum);
1235  else if (!MO->isDef() && !MCOI.isOptionalDef())
1236  report("Explicit definition marked as use", MO, MONum);
1237  else if (MO->isImplicit())
1238  report("Explicit definition marked as implicit", MO, MONum);
1239  } else if (MONum < MCID.getNumOperands()) {
1240  const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
1241  // Don't check if it's the last operand in a variadic instruction. See,
1242  // e.g., LDM_RET in the arm back end.
1243  if (MO->isReg() &&
1244  !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) {
1245  if (MO->isDef() && !MCOI.isOptionalDef())
1246  report("Explicit operand marked as def", MO, MONum);
1247  if (MO->isImplicit())
1248  report("Explicit operand marked as implicit", MO, MONum);
1249  }
1250 
1251  int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO);
1252  if (TiedTo != -1) {
1253  if (!MO->isReg())
1254  report("Tied use must be a register", MO, MONum);
1255  else if (!MO->isTied())
1256  report("Operand should be tied", MO, MONum);
1257  else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
1258  report("Tied def doesn't match MCInstrDesc", MO, MONum);
1260  const MachineOperand &MOTied = MI->getOperand(TiedTo);
1261  if (!MOTied.isReg())
1262  report("Tied counterpart must be a register", &MOTied, TiedTo);
1263  else if (TargetRegisterInfo::isPhysicalRegister(MOTied.getReg()) &&
1264  MO->getReg() != MOTied.getReg())
1265  report("Tied physical registers must match.", &MOTied, TiedTo);
1266  }
1267  } else if (MO->isReg() && MO->isTied())
1268  report("Explicit operand should not be tied", MO, MONum);
1269  } else {
1270  // ARM adds %reg0 operands to indicate predicates. We'll allow that.
1271  if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
1272  report("Extra explicit operand on non-variadic instruction", MO, MONum);
1273  }
1274 
1275  switch (MO->getType()) {
1277  const unsigned Reg = MO->getReg();
1278  if (!Reg)
1279  return;
1280  if (MRI->tracksLiveness() && !MI->isDebugValue())
1281  checkLiveness(MO, MONum);
1282 
1283  // Verify the consistency of tied operands.
1284  if (MO->isTied()) {
1285  unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
1286  const MachineOperand &OtherMO = MI->getOperand(OtherIdx);
1287  if (!OtherMO.isReg())
1288  report("Must be tied to a register", MO, MONum);
1289  if (!OtherMO.isTied())
1290  report("Missing tie flags on tied operand", MO, MONum);
1291  if (MI->findTiedOperandIdx(OtherIdx) != MONum)
1292  report("Inconsistent tie links", MO, MONum);
1293  if (MONum < MCID.getNumDefs()) {
1294  if (OtherIdx < MCID.getNumOperands()) {
1295  if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO))
1296  report("Explicit def tied to explicit use without tie constraint",
1297  MO, MONum);
1298  } else {
1299  if (!OtherMO.isImplicit())
1300  report("Explicit def should be tied to implicit use", MO, MONum);
1301  }
1302  }
1303  }
1304 
1305  // Verify two-address constraints after leaving SSA form.
1306  unsigned DefIdx;
1307  if (!MRI->isSSA() && MO->isUse() &&
1308  MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
1309  Reg != MI->getOperand(DefIdx).getReg())
1310  report("Two-address instruction operands must be identical", MO, MONum);
1311 
1312  // Check register classes.
1313  unsigned SubIdx = MO->getSubReg();
1314 
1316  if (SubIdx) {
1317  report("Illegal subregister index for physical register", MO, MONum);
1318  return;
1319  }
1320  if (MONum < MCID.getNumOperands()) {
1321  if (const TargetRegisterClass *DRC =
1322  TII->getRegClass(MCID, MONum, TRI, *MF)) {
1323  if (!DRC->contains(Reg)) {
1324  report("Illegal physical register for instruction", MO, MONum);
1325  errs() << printReg(Reg, TRI) << " is not a "
1326  << TRI->getRegClassName(DRC) << " register.\n";
1327  }
1328  }
1329  }
1330  if (MO->isRenamable()) {
1331  if (MRI->isReserved(Reg)) {
1332  report("isRenamable set on reserved register", MO, MONum);
1333  return;
1334  }
1335  }
1336  if (MI->isDebugValue() && MO->isUse() && !MO->isDebug()) {
1337  report("Use-reg is not IsDebug in a DBG_VALUE", MO, MONum);
1338  return;
1339  }
1340  } else {
1341  // Virtual register.
1342  const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg);
1343  if (!RC) {
1344  // This is a generic virtual register.
1345 
1346  // If we're post-Select, we can't have gvregs anymore.
1347  if (isFunctionSelected) {
1348  report("Generic virtual register invalid in a Selected function",
1349  MO, MONum);
1350  return;
1351  }
1352 
1353  // The gvreg must have a type and it must not have a SubIdx.
1354  LLT Ty = MRI->getType(Reg);
1355  if (!Ty.isValid()) {
1356  report("Generic virtual register must have a valid type", MO,
1357  MONum);
1358  return;
1359  }
1360 
1361  const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg);
1362 
1363  // If we're post-RegBankSelect, the gvreg must have a bank.
1364  if (!RegBank && isFunctionRegBankSelected) {
1365  report("Generic virtual register must have a bank in a "
1366  "RegBankSelected function",
1367  MO, MONum);
1368  return;
1369  }
1370 
1371  // Make sure the register fits into its register bank if any.
1372  if (RegBank && Ty.isValid() &&
1373  RegBank->getSize() < Ty.getSizeInBits()) {
1374  report("Register bank is too small for virtual register", MO,
1375  MONum);
1376  errs() << "Register bank " << RegBank->getName() << " too small("
1377  << RegBank->getSize() << ") to fit " << Ty.getSizeInBits()
1378  << "-bits\n";
1379  return;
1380  }
1381  if (SubIdx) {
1382  report("Generic virtual register does not subregister index", MO,
1383  MONum);
1384  return;
1385  }
1386 
1387  // If this is a target specific instruction and this operand
1388  // has register class constraint, the virtual register must
1389  // comply to it.
1390  if (!isPreISelGenericOpcode(MCID.getOpcode()) &&
1391  MONum < MCID.getNumOperands() &&
1392  TII->getRegClass(MCID, MONum, TRI, *MF)) {
1393  report("Virtual register does not match instruction constraint", MO,
1394  MONum);
1395  errs() << "Expect register class "
1396  << TRI->getRegClassName(
1397  TII->getRegClass(MCID, MONum, TRI, *MF))
1398  << " but got nothing\n";
1399  return;
1400  }
1401 
1402  break;
1403  }
1404  if (SubIdx) {
1405  const TargetRegisterClass *SRC =
1406  TRI->getSubClassWithSubReg(RC, SubIdx);
1407  if (!SRC) {
1408  report("Invalid subregister index for virtual register", MO, MONum);
1409  errs() << "Register class " << TRI->getRegClassName(RC)
1410  << " does not support subreg index " << SubIdx << "\n";
1411  return;
1412  }
1413  if (RC != SRC) {
1414  report("Invalid register class for subregister index", MO, MONum);
1415  errs() << "Register class " << TRI->getRegClassName(RC)
1416  << " does not fully support subreg index " << SubIdx << "\n";
1417  return;
1418  }
1419  }
1420  if (MONum < MCID.getNumOperands()) {
1421  if (const TargetRegisterClass *DRC =
1422  TII->getRegClass(MCID, MONum, TRI, *MF)) {
1423  if (SubIdx) {
1424  const TargetRegisterClass *SuperRC =
1425  TRI->getLargestLegalSuperClass(RC, *MF);
1426  if (!SuperRC) {
1427  report("No largest legal super class exists.", MO, MONum);
1428  return;
1429  }
1430  DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
1431  if (!DRC) {
1432  report("No matching super-reg register class.", MO, MONum);
1433  return;
1434  }
1435  }
1436  if (!RC->hasSuperClassEq(DRC)) {
1437  report("Illegal virtual register for instruction", MO, MONum);
1438  errs() << "Expected a " << TRI->getRegClassName(DRC)
1439  << " register, but got a " << TRI->getRegClassName(RC)
1440  << " register\n";
1441  }
1442  }
1443  }
1444  }
1445  break;
1446  }
1447 
1449  regMasks.push_back(MO->getRegMask());
1450  break;
1451 
1453  if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
1454  report("PHI operand is not in the CFG", MO, MONum);
1455  break;
1456 
1458  if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
1459  LiveInts && !LiveInts->isNotInMIMap(*MI)) {
1460  int FI = MO->getIndex();
1461  LiveInterval &LI = LiveStks->getInterval(FI);
1462  SlotIndex Idx = LiveInts->getInstructionIndex(*MI);
1463 
1464  bool stores = MI->mayStore();
1465  bool loads = MI->mayLoad();
1466  // For a memory-to-memory move, we need to check if the frame
1467  // index is used for storing or loading, by inspecting the
1468  // memory operands.
1469  if (stores && loads) {
1470  for (auto *MMO : MI->memoperands()) {
1471  const PseudoSourceValue *PSV = MMO->getPseudoValue();
1472  if (PSV == nullptr) continue;
1475  if (Value == nullptr) continue;
1476  if (Value->getFrameIndex() != FI) continue;
1477 
1478  if (MMO->isStore())
1479  loads = false;
1480  else
1481  stores = false;
1482  break;
1483  }
1484  if (loads == stores)
1485  report("Missing fixed stack memoperand.", MI);
1486  }
1487  if (loads && !LI.liveAt(Idx.getRegSlot(true))) {
1488  report("Instruction loads from dead spill slot", MO, MONum);
1489  errs() << "Live stack: " << LI << '\n';
1490  }
1491  if (stores && !LI.liveAt(Idx.getRegSlot())) {
1492  report("Instruction stores to dead spill slot", MO, MONum);
1493  errs() << "Live stack: " << LI << '\n';
1494  }
1495  }
1496  break;
1497 
1498  default:
1499  break;
1500  }
1501 }
1502 
1503 void MachineVerifier::checkLivenessAtUse(const MachineOperand *MO,
1504  unsigned MONum, SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit,
1505  LaneBitmask LaneMask) {
1506  LiveQueryResult LRQ = LR.Query(UseIdx);
1507  // Check if we have a segment at the use, note however that we only need one
1508  // live subregister range, the others may be dead.
1509  if (!LRQ.valueIn() && LaneMask.none()) {
1510  report("No live segment at use", MO, MONum);
1511  report_context_liverange(LR);
1512  report_context_vreg_regunit(VRegOrUnit);
1513  report_context(UseIdx);
1514  }
1515  if (MO->isKill() && !LRQ.isKill()) {
1516  report("Live range continues after kill flag", MO, MONum);
1517  report_context_liverange(LR);
1518  report_context_vreg_regunit(VRegOrUnit);
1519  if (LaneMask.any())
1520  report_context_lanemask(LaneMask);
1521  report_context(UseIdx);
1522  }
1523 }
1524 
1525 void MachineVerifier::checkLivenessAtDef(const MachineOperand *MO,
1526  unsigned MONum, SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit,
1527  bool SubRangeCheck, LaneBitmask LaneMask) {
1528  if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) {
1529  assert(VNI && "NULL valno is not allowed");
1530  if (VNI->def != DefIdx) {
1531  report("Inconsistent valno->def", MO, MONum);
1532  report_context_liverange(LR);
1533  report_context_vreg_regunit(VRegOrUnit);
1534  if (LaneMask.any())
1535  report_context_lanemask(LaneMask);
1536  report_context(*VNI);
1537  report_context(DefIdx);
1538  }
1539  } else {
1540  report("No live segment at def", MO, MONum);
1541  report_context_liverange(LR);
1542  report_context_vreg_regunit(VRegOrUnit);
1543  if (LaneMask.any())
1544  report_context_lanemask(LaneMask);
1545  report_context(DefIdx);
1546  }
1547  // Check that, if the dead def flag is present, LiveInts agree.
1548  if (MO->isDead()) {
1549  LiveQueryResult LRQ = LR.Query(DefIdx);
1550  if (!LRQ.isDeadDef()) {
1552  "Expecting a virtual register.");
1553  // A dead subreg def only tells us that the specific subreg is dead. There
1554  // could be other non-dead defs of other subregs, or we could have other
1555  // parts of the register being live through the instruction. So unless we
1556  // are checking liveness for a subrange it is ok for the live range to
1557  // continue, given that we have a dead def of a subregister.
1558  if (SubRangeCheck || MO->getSubReg() == 0) {
1559  report("Live range continues after dead def flag", MO, MONum);
1560  report_context_liverange(LR);
1561  report_context_vreg_regunit(VRegOrUnit);
1562  if (LaneMask.any())
1563  report_context_lanemask(LaneMask);
1564  }
1565  }
1566  }
1567 }
1568 
1569 void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
1570  const MachineInstr *MI = MO->getParent();
1571  const unsigned Reg = MO->getReg();
1572 
1573  // Both use and def operands can read a register.
1574  if (MO->readsReg()) {
1575  if (MO->isKill())
1576  addRegWithSubRegs(regsKilled, Reg);
1577 
1578  // Check that LiveVars knows this kill.
1579  if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) &&
1580  MO->isKill()) {
1581  LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
1582  if (!is_contained(VI.Kills, MI))
1583  report("Kill missing from LiveVariables", MO, MONum);
1584  }
1585 
1586  // Check LiveInts liveness and kill.
1587  if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
1588  SlotIndex UseIdx = LiveInts->getInstructionIndex(*MI);
1589  // Check the cached regunit intervals.
1590  if (TargetRegisterInfo::isPhysicalRegister(Reg) && !isReserved(Reg)) {
1591  for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
1592  if (MRI->isReservedRegUnit(*Units))
1593  continue;
1594  if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units))
1595  checkLivenessAtUse(MO, MONum, UseIdx, *LR, *Units);
1596  }
1597  }
1598 
1600  if (LiveInts->hasInterval(Reg)) {
1601  // This is a virtual register interval.
1602  const LiveInterval &LI = LiveInts->getInterval(Reg);
1603  checkLivenessAtUse(MO, MONum, UseIdx, LI, Reg);
1604 
1605  if (LI.hasSubRanges() && !MO->isDef()) {
1606  unsigned SubRegIdx = MO->getSubReg();
1607  LaneBitmask MOMask = SubRegIdx != 0
1608  ? TRI->getSubRegIndexLaneMask(SubRegIdx)
1609  : MRI->getMaxLaneMaskForVReg(Reg);
1610  LaneBitmask LiveInMask;
1611  for (const LiveInterval::SubRange &SR : LI.subranges()) {
1612  if ((MOMask & SR.LaneMask).none())
1613  continue;
1614  checkLivenessAtUse(MO, MONum, UseIdx, SR, Reg, SR.LaneMask);
1615  LiveQueryResult LRQ = SR.Query(UseIdx);
1616  if (LRQ.valueIn())
1617  LiveInMask |= SR.LaneMask;
1618  }
1619  // At least parts of the register has to be live at the use.
1620  if ((LiveInMask & MOMask).none()) {
1621  report("No live subrange at use", MO, MONum);
1622  report_context(LI);
1623  report_context(UseIdx);
1624  }
1625  }
1626  } else {
1627  report("Virtual register has no live interval", MO, MONum);
1628  }
1629  }
1630  }
1631 
1632  // Use of a dead register.
1633  if (!regsLive.count(Reg)) {
1635  // Reserved registers may be used even when 'dead'.
1636  bool Bad = !isReserved(Reg);
1637  // We are fine if just any subregister has a defined value.
1638  if (Bad) {
1639  for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid();
1640  ++SubRegs) {
1641  if (regsLive.count(*SubRegs)) {
1642  Bad = false;
1643  break;
1644  }
1645  }
1646  }
1647  // If there is an additional implicit-use of a super register we stop
1648  // here. By definition we are fine if the super register is not
1649  // (completely) dead, if the complete super register is dead we will
1650  // get a report for its operand.
1651  if (Bad) {
1652  for (const MachineOperand &MOP : MI->uses()) {
1653  if (!MOP.isReg() || !MOP.isImplicit())
1654  continue;
1655 
1656  if (!TargetRegisterInfo::isPhysicalRegister(MOP.getReg()))
1657  continue;
1658 
1659  for (MCSubRegIterator SubRegs(MOP.getReg(), TRI); SubRegs.isValid();
1660  ++SubRegs) {
1661  if (*SubRegs == Reg) {
1662  Bad = false;
1663  break;
1664  }
1665  }
1666  }
1667  }
1668  if (Bad)
1669  report("Using an undefined physical register", MO, MONum);
1670  } else if (MRI->def_empty(Reg)) {
1671  report("Reading virtual register without a def", MO, MONum);
1672  } else {
1673  BBInfo &MInfo = MBBInfoMap[MI->getParent()];
1674  // We don't know which virtual registers are live in, so only complain
1675  // if vreg was killed in this MBB. Otherwise keep track of vregs that
1676  // must be live in. PHI instructions are handled separately.
1677  if (MInfo.regsKilled.count(Reg))
1678  report("Using a killed virtual register", MO, MONum);
1679  else if (!MI->isPHI())
1680  MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
1681  }
1682  }
1683  }
1684 
1685  if (MO->isDef()) {
1686  // Register defined.
1687  // TODO: verify that earlyclobber ops are not used.
1688  if (MO->isDead())
1689  addRegWithSubRegs(regsDead, Reg);
1690  else
1691  addRegWithSubRegs(regsDefined, Reg);
1692 
1693  // Verify SSA form.
1694  if (MRI->isSSA() && TargetRegisterInfo::isVirtualRegister(Reg) &&
1695  std::next(MRI->def_begin(Reg)) != MRI->def_end())
1696  report("Multiple virtual register defs in SSA form", MO, MONum);
1697 
1698  // Check LiveInts for a live segment, but only for virtual registers.
1699  if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
1700  SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI);
1701  DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
1702 
1704  if (LiveInts->hasInterval(Reg)) {
1705  const LiveInterval &LI = LiveInts->getInterval(Reg);
1706  checkLivenessAtDef(MO, MONum, DefIdx, LI, Reg);
1707 
1708  if (LI.hasSubRanges()) {
1709  unsigned SubRegIdx = MO->getSubReg();
1710  LaneBitmask MOMask = SubRegIdx != 0
1711  ? TRI->getSubRegIndexLaneMask(SubRegIdx)
1712  : MRI->getMaxLaneMaskForVReg(Reg);
1713  for (const LiveInterval::SubRange &SR : LI.subranges()) {
1714  if ((SR.LaneMask & MOMask).none())
1715  continue;
1716  checkLivenessAtDef(MO, MONum, DefIdx, SR, Reg, true, SR.LaneMask);
1717  }
1718  }
1719  } else {
1720  report("Virtual register has no Live interval", MO, MONum);
1721  }
1722  }
1723  }
1724  }
1725 }
1726 
1727 void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {}
1728 
1729 // This function gets called after visiting all instructions in a bundle. The
1730 // argument points to the bundle header.
1731 // Normal stand-alone instructions are also considered 'bundles', and this
1732 // function is called for all of them.
1733 void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
1734  BBInfo &MInfo = MBBInfoMap[MI->getParent()];
1735  set_union(MInfo.regsKilled, regsKilled);
1736  set_subtract(regsLive, regsKilled); regsKilled.clear();
1737  // Kill any masked registers.
1738  while (!regMasks.empty()) {
1739  const uint32_t *Mask = regMasks.pop_back_val();
1740  for (RegSet::iterator I = regsLive.begin(), E = regsLive.end(); I != E; ++I)
1743  regsDead.push_back(*I);
1744  }
1745  set_subtract(regsLive, regsDead); regsDead.clear();
1746  set_union(regsLive, regsDefined); regsDefined.clear();
1747 }
1748 
1749 void
1750 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
1751  MBBInfoMap[MBB].regsLiveOut = regsLive;
1752  regsLive.clear();
1753 
1754  if (Indexes) {
1755  SlotIndex stop = Indexes->getMBBEndIdx(MBB);
1756  if (!(stop > lastIndex)) {
1757  report("Block ends before last instruction index", MBB);
1758  errs() << "Block ends at " << stop
1759  << " last instruction was at " << lastIndex << '\n';
1760  }
1761  lastIndex = stop;
1762  }
1763 }
1764 
1765 // Calculate the largest possible vregsPassed sets. These are the registers that
1766 // can pass through an MBB live, but may not be live every time. It is assumed
1767 // that all vregsPassed sets are empty before the call.
1768 void MachineVerifier::calcRegsPassed() {
1769  // First push live-out regs to successors' vregsPassed. Remember the MBBs that
1770  // have any vregsPassed.
1772  for (const auto &MBB : *MF) {
1773  BBInfo &MInfo = MBBInfoMap[&MBB];
1774  if (!MInfo.reachable)
1775  continue;
1777  SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
1778  BBInfo &SInfo = MBBInfoMap[*SuI];
1779  if (SInfo.addPassed(MInfo.regsLiveOut))
1780  todo.insert(*SuI);
1781  }
1782  }
1783 
1784  // Iteratively push vregsPassed to successors. This will converge to the same
1785  // final state regardless of DenseSet iteration order.
1786  while (!todo.empty()) {
1787  const MachineBasicBlock *MBB = *todo.begin();
1788  todo.erase(MBB);
1789  BBInfo &MInfo = MBBInfoMap[MBB];
1791  SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
1792  if (*SuI == MBB)
1793  continue;
1794  BBInfo &SInfo = MBBInfoMap[*SuI];
1795  if (SInfo.addPassed(MInfo.vregsPassed))
1796  todo.insert(*SuI);
1797  }
1798  }
1799 }
1800 
1801 // Calculate the set of virtual registers that must be passed through each basic
1802 // block in order to satisfy the requirements of successor blocks. This is very
1803 // similar to calcRegsPassed, only backwards.
1804 void MachineVerifier::calcRegsRequired() {
1805  // First push live-in regs to predecessors' vregsRequired.
1807  for (const auto &MBB : *MF) {
1808  BBInfo &MInfo = MBBInfoMap[&MBB];
1810  PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
1811  BBInfo &PInfo = MBBInfoMap[*PrI];
1812  if (PInfo.addRequired(MInfo.vregsLiveIn))
1813  todo.insert(*PrI);
1814  }
1815  }
1816 
1817  // Iteratively push vregsRequired to predecessors. This will converge to the
1818  // same final state regardless of DenseSet iteration order.
1819  while (!todo.empty()) {
1820  const MachineBasicBlock *MBB = *todo.begin();
1821  todo.erase(MBB);
1822  BBInfo &MInfo = MBBInfoMap[MBB];
1824  PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
1825  if (*PrI == MBB)
1826  continue;
1827  BBInfo &SInfo = MBBInfoMap[*PrI];
1828  if (SInfo.addRequired(MInfo.vregsRequired))
1829  todo.insert(*PrI);
1830  }
1831  }
1832 }
1833 
1834 // Check PHI instructions at the beginning of MBB. It is assumed that
1835 // calcRegsPassed has been run so BBInfo::isLiveOut is valid.
1836 void MachineVerifier::checkPHIOps(const MachineBasicBlock &MBB) {
1837  BBInfo &MInfo = MBBInfoMap[&MBB];
1838 
1840  for (const MachineInstr &Phi : MBB) {
1841  if (!Phi.isPHI())
1842  break;
1843  seen.clear();
1844 
1845  const MachineOperand &MODef = Phi.getOperand(0);
1846  if (!MODef.isReg() || !MODef.isDef()) {
1847  report("Expected first PHI operand to be a register def", &MODef, 0);
1848  continue;
1849  }
1850  if (MODef.isTied() || MODef.isImplicit() || MODef.isInternalRead() ||
1851  MODef.isEarlyClobber() || MODef.isDebug())
1852  report("Unexpected flag on PHI operand", &MODef, 0);
1853  unsigned DefReg = MODef.getReg();
1855  report("Expected first PHI operand to be a virtual register", &MODef, 0);
1856 
1857  for (unsigned I = 1, E = Phi.getNumOperands(); I != E; I += 2) {
1858  const MachineOperand &MO0 = Phi.getOperand(I);
1859  if (!MO0.isReg()) {
1860  report("Expected PHI operand to be a register", &MO0, I);
1861  continue;
1862  }
1863  if (MO0.isImplicit() || MO0.isInternalRead() || MO0.isEarlyClobber() ||
1864  MO0.isDebug() || MO0.isTied())
1865  report("Unexpected flag on PHI operand", &MO0, I);
1866 
1867  const MachineOperand &MO1 = Phi.getOperand(I + 1);
1868  if (!MO1.isMBB()) {
1869  report("Expected PHI operand to be a basic block", &MO1, I + 1);
1870  continue;
1871  }
1872 
1873  const MachineBasicBlock &Pre = *MO1.getMBB();
1874  if (!Pre.isSuccessor(&MBB)) {
1875  report("PHI input is not a predecessor block", &MO1, I + 1);
1876  continue;
1877  }
1878 
1879  if (MInfo.reachable) {
1880  seen.insert(&Pre);
1881  BBInfo &PrInfo = MBBInfoMap[&Pre];
1882  if (!MO0.isUndef() && PrInfo.reachable &&
1883  !PrInfo.isLiveOut(MO0.getReg()))
1884  report("PHI operand is not live-out from predecessor", &MO0, I);
1885  }
1886  }
1887 
1888  // Did we see all predecessors?
1889  if (MInfo.reachable) {
1890  for (MachineBasicBlock *Pred : MBB.predecessors()) {
1891  if (!seen.count(Pred)) {
1892  report("Missing PHI operand", &Phi);
1893  errs() << printMBBReference(*Pred)
1894  << " is a predecessor according to the CFG.\n";
1895  }
1896  }
1897  }
1898  }
1899 }
1900 
1901 void MachineVerifier::visitMachineFunctionAfter() {
1902  calcRegsPassed();
1903 
1904  for (const MachineBasicBlock &MBB : *MF)
1905  checkPHIOps(MBB);
1906 
1907  // Now check liveness info if available
1908  calcRegsRequired();
1909 
1910  // Check for killed virtual registers that should be live out.
1911  for (const auto &MBB : *MF) {
1912  BBInfo &MInfo = MBBInfoMap[&MBB];
1913  for (RegSet::iterator
1914  I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
1915  ++I)
1916  if (MInfo.regsKilled.count(*I)) {
1917  report("Virtual register killed in block, but needed live out.", &MBB);
1918  errs() << "Virtual register " << printReg(*I)
1919  << " is used after the block.\n";
1920  }
1921  }
1922 
1923  if (!MF->empty()) {
1924  BBInfo &MInfo = MBBInfoMap[&MF->front()];
1925  for (RegSet::iterator
1926  I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
1927  ++I) {
1928  report("Virtual register defs don't dominate all uses.", MF);
1929  report_context_vreg(*I);
1930  }
1931  }
1932 
1933  if (LiveVars)
1934  verifyLiveVariables();
1935  if (LiveInts)
1936  verifyLiveIntervals();
1937 }
1938 
1939 void MachineVerifier::verifyLiveVariables() {
1940  assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
1941  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1942  unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
1943  LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
1944  for (const auto &MBB : *MF) {
1945  BBInfo &MInfo = MBBInfoMap[&MBB];
1946 
1947  // Our vregsRequired should be identical to LiveVariables' AliveBlocks
1948  if (MInfo.vregsRequired.count(Reg)) {
1949  if (!VI.AliveBlocks.test(MBB.getNumber())) {
1950  report("LiveVariables: Block missing from AliveBlocks", &MBB);
1951  errs() << "Virtual register " << printReg(Reg)
1952  << " must be live through the block.\n";
1953  }
1954  } else {
1955  if (VI.AliveBlocks.test(MBB.getNumber())) {
1956  report("LiveVariables: Block should not be in AliveBlocks", &MBB);
1957  errs() << "Virtual register " << printReg(Reg)
1958  << " is not needed live through the block.\n";
1959  }
1960  }
1961  }
1962  }
1963 }
1964 
1965 void MachineVerifier::verifyLiveIntervals() {
1966  assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
1967  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1968  unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
1969 
1970  // Spilling and splitting may leave unused registers around. Skip them.
1971  if (MRI->reg_nodbg_empty(Reg))
1972  continue;
1973 
1974  if (!LiveInts->hasInterval(Reg)) {
1975  report("Missing live interval for virtual register", MF);
1976  errs() << printReg(Reg, TRI) << " still has defs or uses\n";
1977  continue;
1978  }
1979 
1980  const LiveInterval &LI = LiveInts->getInterval(Reg);
1981  assert(Reg == LI.reg && "Invalid reg to interval mapping");
1982  verifyLiveInterval(LI);
1983  }
1984 
1985  // Verify all the cached regunit intervals.
1986  for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
1987  if (const LiveRange *LR = LiveInts->getCachedRegUnit(i))
1988  verifyLiveRange(*LR, i);
1989 }
1990 
1991 void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
1992  const VNInfo *VNI, unsigned Reg,
1993  LaneBitmask LaneMask) {
1994  if (VNI->isUnused())
1995  return;
1996 
1997  const VNInfo *DefVNI = LR.getVNInfoAt(VNI->def);
1998 
1999  if (!DefVNI) {
2000  report("Value not live at VNInfo def and not marked unused", MF);
2001  report_context(LR, Reg, LaneMask);
2002  report_context(*VNI);
2003  return;
2004  }
2005 
2006  if (DefVNI != VNI) {
2007  report("Live segment at def has different VNInfo", MF);
2008  report_context(LR, Reg, LaneMask);
2009  report_context(*VNI);
2010  return;
2011  }
2012 
2013  const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
2014  if (!MBB) {
2015  report("Invalid VNInfo definition index", MF);
2016  report_context(LR, Reg, LaneMask);
2017  report_context(*VNI);
2018  return;
2019  }
2020 
2021  if (VNI->isPHIDef()) {
2022  if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
2023  report("PHIDef VNInfo is not defined at MBB start", MBB);
2024  report_context(LR, Reg, LaneMask);
2025  report_context(*VNI);
2026  }
2027  return;
2028  }
2029 
2030  // Non-PHI def.
2031  const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
2032  if (!MI) {
2033  report("No instruction at VNInfo def index", MBB);
2034  report_context(LR, Reg, LaneMask);
2035  report_context(*VNI);
2036  return;
2037  }
2038 
2039  if (Reg != 0) {
2040  bool hasDef = false;
2041  bool isEarlyClobber = false;
2042  for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
2043  if (!MOI->isReg() || !MOI->isDef())
2044  continue;
2046  if (MOI->getReg() != Reg)
2047  continue;
2048  } else {
2049  if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) ||
2050  !TRI->hasRegUnit(MOI->getReg(), Reg))
2051  continue;
2052  }
2053  if (LaneMask.any() &&
2054  (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
2055  continue;
2056  hasDef = true;
2057  if (MOI->isEarlyClobber())
2058  isEarlyClobber = true;
2059  }
2060 
2061  if (!hasDef) {
2062  report("Defining instruction does not modify register", MI);
2063  report_context(LR, Reg, LaneMask);
2064  report_context(*VNI);
2065  }
2066 
2067  // Early clobber defs begin at USE slots, but other defs must begin at
2068  // DEF slots.
2069  if (isEarlyClobber) {
2070  if (!VNI->def.isEarlyClobber()) {
2071  report("Early clobber def must be at an early-clobber slot", MBB);
2072  report_context(LR, Reg, LaneMask);
2073  report_context(*VNI);
2074  }
2075  } else if (!VNI->def.isRegister()) {
2076  report("Non-PHI, non-early clobber def must be at a register slot", MBB);
2077  report_context(LR, Reg, LaneMask);
2078  report_context(*VNI);
2079  }
2080  }
2081 }
2082 
2083 void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
2085  unsigned Reg, LaneBitmask LaneMask)
2086 {
2087  const LiveRange::Segment &S = *I;
2088  const VNInfo *VNI = S.valno;
2089  assert(VNI && "Live segment has no valno");
2090 
2091  if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) {
2092  report("Foreign valno in live segment", MF);
2093  report_context(LR, Reg, LaneMask);
2094  report_context(S);
2095  report_context(*VNI);
2096  }
2097 
2098  if (VNI->isUnused()) {
2099  report("Live segment valno is marked unused", MF);
2100  report_context(LR, Reg, LaneMask);
2101  report_context(S);
2102  }
2103 
2104  const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(S.start);
2105  if (!MBB) {
2106  report("Bad start of live segment, no basic block", MF);
2107  report_context(LR, Reg, LaneMask);
2108  report_context(S);
2109  return;
2110  }
2111  SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
2112  if (S.start != MBBStartIdx && S.start != VNI->def) {
2113  report("Live segment must begin at MBB entry or valno def", MBB);
2114  report_context(LR, Reg, LaneMask);
2115  report_context(S);
2116  }
2117 
2118  const MachineBasicBlock *EndMBB =
2119  LiveInts->getMBBFromIndex(S.end.getPrevSlot());
2120  if (!EndMBB) {
2121  report("Bad end of live segment, no basic block", MF);
2122  report_context(LR, Reg, LaneMask);
2123  report_context(S);
2124  return;
2125  }
2126 
2127  // No more checks for live-out segments.
2128  if (S.end == LiveInts->getMBBEndIdx(EndMBB))
2129  return;
2130 
2131  // RegUnit intervals are allowed dead phis.
2132  if (!TargetRegisterInfo::isVirtualRegister(Reg) && VNI->isPHIDef() &&
2133  S.start == VNI->def && S.end == VNI->def.getDeadSlot())
2134  return;
2135 
2136  // The live segment is ending inside EndMBB
2137  const MachineInstr *MI =
2138  LiveInts->getInstructionFromIndex(S.end.getPrevSlot());
2139  if (!MI) {
2140  report("Live segment doesn't end at a valid instruction", EndMBB);
2141  report_context(LR, Reg, LaneMask);
2142  report_context(S);
2143  return;
2144  }
2145 
2146  // The block slot must refer to a basic block boundary.
2147  if (S.end.isBlock()) {
2148  report("Live segment ends at B slot of an instruction", EndMBB);
2149  report_context(LR, Reg, LaneMask);
2150  report_context(S);
2151  }
2152 
2153  if (S.end.isDead()) {
2154  // Segment ends on the dead slot.
2155  // That means there must be a dead def.
2156  if (!SlotIndex::isSameInstr(S.start, S.end)) {
2157  report("Live segment ending at dead slot spans instructions", EndMBB);
2158  report_context(LR, Reg, LaneMask);
2159  report_context(S);
2160  }
2161  }
2162 
2163  // A live segment can only end at an early-clobber slot if it is being
2164  // redefined by an early-clobber def.
2165  if (S.end.isEarlyClobber()) {
2166  if (I+1 == LR.end() || (I+1)->start != S.end) {
2167  report("Live segment ending at early clobber slot must be "
2168  "redefined by an EC def in the same instruction", EndMBB);
2169  report_context(LR, Reg, LaneMask);
2170  report_context(S);
2171  }
2172  }
2173 
2174  // The following checks only apply to virtual registers. Physreg liveness
2175  // is too weird to check.
2177  // A live segment can end with either a redefinition, a kill flag on a
2178  // use, or a dead flag on a def.
2179  bool hasRead = false;
2180  bool hasSubRegDef = false;
2181  bool hasDeadDef = false;
2182  for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
2183  if (!MOI->isReg() || MOI->getReg() != Reg)
2184  continue;
2185  unsigned Sub = MOI->getSubReg();
2186  LaneBitmask SLM = Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub)
2187  : LaneBitmask::getAll();
2188  if (MOI->isDef()) {
2189  if (Sub != 0) {
2190  hasSubRegDef = true;
2191  // An operand %0:sub0 reads %0:sub1..n. Invert the lane
2192  // mask for subregister defs. Read-undef defs will be handled by
2193  // readsReg below.
2194  SLM = ~SLM;
2195  }
2196  if (MOI->isDead())
2197  hasDeadDef = true;
2198  }
2199  if (LaneMask.any() && (LaneMask & SLM).none())
2200  continue;
2201  if (MOI->readsReg())
2202  hasRead = true;
2203  }
2204  if (S.end.isDead()) {
2205  // Make sure that the corresponding machine operand for a "dead" live
2206  // range has the dead flag. We cannot perform this check for subregister
2207  // liveranges as partially dead values are allowed.
2208  if (LaneMask.none() && !hasDeadDef) {
2209  report("Instruction ending live segment on dead slot has no dead flag",
2210  MI);
2211  report_context(LR, Reg, LaneMask);
2212  report_context(S);
2213  }
2214  } else {
2215  if (!hasRead) {
2216  // When tracking subregister liveness, the main range must start new
2217  // values on partial register writes, even if there is no read.
2218  if (!MRI->shouldTrackSubRegLiveness(Reg) || LaneMask.any() ||
2219  !hasSubRegDef) {
2220  report("Instruction ending live segment doesn't read the register",
2221  MI);
2222  report_context(LR, Reg, LaneMask);
2223  report_context(S);
2224  }
2225  }
2226  }
2227  }
2228 
2229  // Now check all the basic blocks in this live segment.
2231  // Is this live segment the beginning of a non-PHIDef VN?
2232  if (S.start == VNI->def && !VNI->isPHIDef()) {
2233  // Not live-in to any blocks.
2234  if (MBB == EndMBB)
2235  return;
2236  // Skip this block.
2237  ++MFI;
2238  }
2239 
2241  if (LaneMask.any()) {
2242  LiveInterval &OwnerLI = LiveInts->getInterval(Reg);
2243  OwnerLI.computeSubRangeUndefs(Undefs, LaneMask, *MRI, *Indexes);
2244  }
2245 
2246  while (true) {
2247  assert(LiveInts->isLiveInToMBB(LR, &*MFI));
2248  // We don't know how to track physregs into a landing pad.
2250  MFI->isEHPad()) {
2251  if (&*MFI == EndMBB)
2252  break;
2253  ++MFI;
2254  continue;
2255  }
2256 
2257  // Is VNI a PHI-def in the current block?
2258  bool IsPHI = VNI->isPHIDef() &&
2259  VNI->def == LiveInts->getMBBStartIdx(&*MFI);
2260 
2261  // Check that VNI is live-out of all predecessors.
2262  for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
2263  PE = MFI->pred_end(); PI != PE; ++PI) {
2264  SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
2265  const VNInfo *PVNI = LR.getVNInfoBefore(PEnd);
2266 
2267  // All predecessors must have a live-out value. However for a phi
2268  // instruction with subregister intervals
2269  // only one of the subregisters (not necessarily the current one) needs to
2270  // be defined.
2271  if (!PVNI && (LaneMask.none() || !IsPHI)) {
2272  if (LiveRangeCalc::isJointlyDominated(*PI, Undefs, *Indexes))
2273  continue;
2274  report("Register not marked live out of predecessor", *PI);
2275  report_context(LR, Reg, LaneMask);
2276  report_context(*VNI);
2277  errs() << " live into " << printMBBReference(*MFI) << '@'
2278  << LiveInts->getMBBStartIdx(&*MFI) << ", not live before "
2279  << PEnd << '\n';
2280  continue;
2281  }
2282 
2283  // Only PHI-defs can take different predecessor values.
2284  if (!IsPHI && PVNI != VNI) {
2285  report("Different value live out of predecessor", *PI);
2286  report_context(LR, Reg, LaneMask);
2287  errs() << "Valno #" << PVNI->id << " live out of "
2288  << printMBBReference(*(*PI)) << '@' << PEnd << "\nValno #"
2289  << VNI->id << " live into " << printMBBReference(*MFI) << '@'
2290  << LiveInts->getMBBStartIdx(&*MFI) << '\n';
2291  }
2292  }
2293  if (&*MFI == EndMBB)
2294  break;
2295  ++MFI;
2296  }
2297 }
2298 
2299 void MachineVerifier::verifyLiveRange(const LiveRange &LR, unsigned Reg,
2300  LaneBitmask LaneMask) {
2301  for (const VNInfo *VNI : LR.valnos)
2302  verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
2303 
2304  for (LiveRange::const_iterator I = LR.begin(), E = LR.end(); I != E; ++I)
2305  verifyLiveRangeSegment(LR, I, Reg, LaneMask);
2306 }
2307 
2308 void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
2309  unsigned Reg = LI.reg;
2311  verifyLiveRange(LI, Reg);
2312 
2313  LaneBitmask Mask;
2314  LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
2315  for (const LiveInterval::SubRange &SR : LI.subranges()) {
2316  if ((Mask & SR.LaneMask).any()) {
2317  report("Lane masks of sub ranges overlap in live interval", MF);
2318  report_context(LI);
2319  }
2320  if ((SR.LaneMask & ~MaxMask).any()) {
2321  report("Subrange lanemask is invalid", MF);
2322  report_context(LI);
2323  }
2324  if (SR.empty()) {
2325  report("Subrange must not be empty", MF);
2326  report_context(SR, LI.reg, SR.LaneMask);
2327  }
2328  Mask |= SR.LaneMask;
2329  verifyLiveRange(SR, LI.reg, SR.LaneMask);
2330  if (!LI.covers(SR)) {
2331  report("A Subrange is not covered by the main range", MF);
2332  report_context(LI);
2333  }
2334  }
2335 
2336  // Check the LI only has one connected component.
2337  ConnectedVNInfoEqClasses ConEQ(*LiveInts);
2338  unsigned NumComp = ConEQ.Classify(LI);
2339  if (NumComp > 1) {
2340  report("Multiple connected components in live interval", MF);
2341  report_context(LI);
2342  for (unsigned comp = 0; comp != NumComp; ++comp) {
2343  errs() << comp << ": valnos";
2345  E = LI.vni_end(); I!=E; ++I)
2346  if (comp == ConEQ.getEqClass(*I))
2347  errs() << ' ' << (*I)->id;
2348  errs() << '\n';
2349  }
2350  }
2351 }
2352 
2353 namespace {
2354 
2355  // FrameSetup and FrameDestroy can have zero adjustment, so using a single
2356  // integer, we can't tell whether it is a FrameSetup or FrameDestroy if the
2357  // value is zero.
2358  // We use a bool plus an integer to capture the stack state.
2359  struct StackStateOfBB {
2360  StackStateOfBB() = default;
2361  StackStateOfBB(int EntryVal, int ExitVal, bool EntrySetup, bool ExitSetup) :
2362  EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
2363  ExitIsSetup(ExitSetup) {}
2364 
2365  // Can be negative, which means we are setting up a frame.
2366  int EntryValue = 0;
2367  int ExitValue = 0;
2368  bool EntryIsSetup = false;
2369  bool ExitIsSetup = false;
2370  };
2371 
2372 } // end anonymous namespace
2373 
2374 /// Make sure on every path through the CFG, a FrameSetup <n> is always followed
2375 /// by a FrameDestroy <n>, stack adjustments are identical on all
2376 /// CFG edges to a merge point, and frame is destroyed at end of a return block.
2377 void MachineVerifier::verifyStackFrame() {
2378  unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode();
2379  unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
2380  if (FrameSetupOpcode == ~0u && FrameDestroyOpcode == ~0u)
2381  return;
2382 
2384  SPState.resize(MF->getNumBlockIDs());
2386 
2387  // Visit the MBBs in DFS order.
2388  for (df_ext_iterator<const MachineFunction *,
2390  DFI = df_ext_begin(MF, Reachable), DFE = df_ext_end(MF, Reachable);
2391  DFI != DFE; ++DFI) {
2392  const MachineBasicBlock *MBB = *DFI;
2393 
2394  StackStateOfBB BBState;
2395  // Check the exit state of the DFS stack predecessor.
2396  if (DFI.getPathLength() >= 2) {
2397  const MachineBasicBlock *StackPred = DFI.getPath(DFI.getPathLength() - 2);
2398  assert(Reachable.count(StackPred) &&
2399  "DFS stack predecessor is already visited.\n");
2400  BBState.EntryValue = SPState[StackPred->getNumber()].ExitValue;
2401  BBState.EntryIsSetup = SPState[StackPred->getNumber()].ExitIsSetup;
2402  BBState.ExitValue = BBState.EntryValue;
2403  BBState.ExitIsSetup = BBState.EntryIsSetup;
2404  }
2405 
2406  // Update stack state by checking contents of MBB.
2407  for (const auto &I : *MBB) {
2408  if (I.getOpcode() == FrameSetupOpcode) {
2409  if (BBState.ExitIsSetup)
2410  report("FrameSetup is after another FrameSetup", &I);
2411  BBState.ExitValue -= TII->getFrameTotalSize(I);
2412  BBState.ExitIsSetup = true;
2413  }
2414 
2415  if (I.getOpcode() == FrameDestroyOpcode) {
2416  int Size = TII->getFrameTotalSize(I);
2417  if (!BBState.ExitIsSetup)
2418  report("FrameDestroy is not after a FrameSetup", &I);
2419  int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
2420  BBState.ExitValue;
2421  if (BBState.ExitIsSetup && AbsSPAdj != Size) {
2422  report("FrameDestroy <n> is after FrameSetup <m>", &I);
2423  errs() << "FrameDestroy <" << Size << "> is after FrameSetup <"
2424  << AbsSPAdj << ">.\n";
2425  }
2426  BBState.ExitValue += Size;
2427  BBState.ExitIsSetup = false;
2428  }
2429  }
2430  SPState[MBB->getNumber()] = BBState;
2431 
2432  // Make sure the exit state of any predecessor is consistent with the entry
2433  // state.
2434  for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
2435  E = MBB->pred_end(); I != E; ++I) {
2436  if (Reachable.count(*I) &&
2437  (SPState[(*I)->getNumber()].ExitValue != BBState.EntryValue ||
2438  SPState[(*I)->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
2439  report("The exit stack state of a predecessor is inconsistent.", MBB);
2440  errs() << "Predecessor " << printMBBReference(*(*I))
2441  << " has exit state (" << SPState[(*I)->getNumber()].ExitValue
2442  << ", " << SPState[(*I)->getNumber()].ExitIsSetup << "), while "
2443  << printMBBReference(*MBB) << " has entry state ("
2444  << BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n";
2445  }
2446  }
2447 
2448  // Make sure the entry state of any successor is consistent with the exit
2449  // state.
2450  for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
2451  E = MBB->succ_end(); I != E; ++I) {
2452  if (Reachable.count(*I) &&
2453  (SPState[(*I)->getNumber()].EntryValue != BBState.ExitValue ||
2454  SPState[(*I)->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
2455  report("The entry stack state of a successor is inconsistent.", MBB);
2456  errs() << "Successor " << printMBBReference(*(*I))
2457  << " has entry state (" << SPState[(*I)->getNumber()].EntryValue
2458  << ", " << SPState[(*I)->getNumber()].EntryIsSetup << "), while "
2459  << printMBBReference(*MBB) << " has exit state ("
2460  << BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n";
2461  }
2462  }
2463 
2464  // Make sure a basic block with return ends with zero stack adjustment.
2465  if (!MBB->empty() && MBB->back().isReturn()) {
2466  if (BBState.ExitIsSetup)
2467  report("A return block ends with a FrameSetup.", MBB);
2468  if (BBState.ExitValue)
2469  report("A return block ends with a nonzero stack adjustment.", MBB);
2470  }
2471  }
2472 }
bool reg_nodbg_empty(unsigned RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions...
Pass interface - Implemented by all &#39;passes&#39;.
Definition: Pass.h:80
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
Definition: LiveInterval.h:77
bool isRegister() const
isRegister - Returns true if this is a normal register use/def slot.
Definition: SlotIndexes.h:233
mop_iterator operands_end()
Definition: MachineInstr.h:453
Safe Stack instrumentation pass
Definition: SafeStack.cpp:906
A common definition of LaneBitmask for use in TableGen and CodeGen.
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
const unsigned reg
Definition: LiveInterval.h:666
MachineBasicBlock * getMBB() const
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:60
LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:491
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
const char * getName() const
Get a user friendly name of this register bank.
Definition: RegisterBank.h:51
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID&#39;s allocated.
const MachineFunctionProperties & getProperties() const
Get the function properties.
int64_t getFrameTotalSize(const MachineInstr &I) const
Returns the total frame size, which is made up of the space set up inside the pair of frame start-sto...
DWARF-like instruction based exceptions.
vni_iterator vni_begin()
Definition: LiveInterval.h:219
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:637
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
static bool matchPair(MachineBasicBlock::const_succ_iterator i, const MachineBasicBlock *a, const MachineBasicBlock *b)
unsigned Reg
unsigned getSubReg() const
bool isInlineAsm() const
MBBIndexIterator MBBIndexEnd() const
Return an iterator for the end of the idx2MBBMap.
Definition: SlotIndexes.h:533
bool test(unsigned Idx) const
Definition: BitVector.h:501
bool isDead() const
isDead - Returns true if this is a dead def kill slot.
Definition: SlotIndexes.h:236
LiveInterval & getInterval(int Slot)
Definition: LiveStacks.h:63
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
bool isDeadDef() const
Return true if this instruction has a dead def.
Definition: LiveInterval.h:116
A live range for subregisters.
Definition: LiveInterval.h:644
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1185
bool isValid() const
Returns true if this is a valid index.
Definition: SlotIndexes.h:151
MachineBasicBlock reference.
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:161
VarInfo - This represents the regions where a virtual register is live in the program.
Definition: LiveVariables.h:78
unsigned const TargetRegisterInfo * TRI
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
Definition: LaneBitmask.h:93
F(f)
unsigned getCallFrameDestroyOpcode() const
const Instruction * getTerminator() const LLVM_READONLY
Returns the terminator instruction if the block is well formed or null if the block is not well forme...
Definition: BasicBlock.cpp:137
bool reservedRegsFrozen() const
reservedRegsFrozen - Returns true after freezeReservedRegs() was called to ensure the set of reserved...
std::vector< MachineBasicBlock * >::const_iterator const_pred_iterator
VNInfo - Value Number Information.
Definition: LiveInterval.h:52
void print(raw_ostream &O, const Module *=nullptr) const override
Implement the dump method.
bool isPHI() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void verifyUseLists() const
Verify the use list of all registers.
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:127
bool isInternalRead() const
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:156
void initializeMachineVerifierPassPass(PassRegistry &)
bool isUnused() const
Returns true if this value is unused.
Definition: LiveInterval.h:80
Mask of preserved registers.
bool isEarlyClobber() const
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
bool test(unsigned Idx) const
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness...
bool isVector() const
bool isNotInMIMap(const MachineInstr &Instr) const
Returns true if the specified machine instr has been removed or was never entered in the map...
bool isBlock() const
isBlock - Returns true if this is a block boundary slot.
Definition: SlotIndexes.h:226
Definition: BitVector.h:937
void clear()
clear - Removes all bits from the bitvector. Does not change capacity.
Definition: BitVector.h:366
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
Definition: SlotIndexes.h:259
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
const HexagonInstrInfo * TII
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
unsigned getVarIdx() const
Get starting index of non call related arguments (calling convention, statepoint flags, vm state and gc state).
Definition: StackMaps.h:172
bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:411
const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
iterator end()
Definition: LiveInterval.h:211
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:722
Result of a LiveRange query.
Definition: LiveInterval.h:89
static constexpr LaneBitmask getAll()
Definition: LaneBitmask.h:83
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:648
SlotIndex getInstructionIndex(const MachineInstr &MI) const
Returns the base index for the given instruction.
Definition: SlotIndexes.h:413
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Definition: LiveInterval.h:750
SmallVectorImpl< IdxMBBPair >::const_iterator MBBIndexIterator
Iterator over the idx2MBBMap (sorted pairs of slot index of basic block begin and basic block) ...
Definition: SlotIndexes.h:513
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
def_iterator def_begin(unsigned RegNo) const
SparseBitVector AliveBlocks
AliveBlocks - Set of blocks in which this value is alive completely through.
Definition: LiveVariables.h:83
static constexpr LaneBitmask getNone()
Definition: LaneBitmask.h:82
LLT getElementType() const
Returns the vector&#39;s element type. Only valid for vector types.
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
unsigned getEqClass(const VNInfo *VNI) const
getEqClass - Classify creates equivalence classes numbered 0..N.
Definition: LiveInterval.h:930
bool isScopedEHPersonality(EHPersonality Pers)
Returns true if this personality uses scope-style EH IR instructions: catchswitch, catchpad/ret, and cleanuppad/ret.
bool hasRegUnit(unsigned Reg, unsigned RegUnit) const
Returns true if Reg contains RegUnit.
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register. ...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:405
bool isValid() const
isValid - Returns true until all the operands have been visited.
SlotIndexes pass.
Definition: SlotIndexes.h:330
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
Definition: SlotIndexes.h:254
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they&#39;re not in a MachineFuncti...
virtual const TargetInstrInfo * getInstrInfo() const
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
Definition: MachineInstr.h:349
bool isKill() const
Return true if the live-in value is killed by this instruction.
Definition: LiveInterval.h:111
LiveRange * getCachedRegUnit(unsigned Unit)
Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn&#39;t...
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
Definition: LiveInterval.h:104
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
Definition: LiveInterval.h:528
TargetInstrInfo - Interface to description of machine instruction set.
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:55
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:408
bool isGenericType() const
Definition: MCInstrDesc.h:97
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:819
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
unsigned const MachineRegisterInfo * MRI
VNInfoList::const_iterator const_vni_iterator
Definition: LiveInterval.h:217
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
bool hasInterval(unsigned Reg) const
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:515
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:95
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
df_ext_iterator< T, SetTy > df_ext_end(const T &G, SetTy &S)
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:388
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
LLVM_NODISCARD bool empty() const
Definition: SmallPtrSet.h:91
unsigned Classify(const LiveRange &LR)
Classify the values in LR into connected components.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:370
bool hasIndex(const MachineInstr &instr) const
Returns true if the given machine instr is mapped to an index, otherwise returns false.
Definition: SlotIndexes.h:408
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:335
virtual bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const
Perform target-specific instruction verification.
unsigned getCallFrameSetupOpcode() const
These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise)...
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
Definition: SlotIndexes.h:492
Represent the analysis usage information of a pass.
df_ext_iterator< T, SetTy > df_ext_begin(const T &G, SetTy &S)
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:548
bool isValid() const
constexpr bool none() const
Definition: LaneBitmask.h:51
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
bool def_empty(unsigned RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
MBBIndexIterator MBBIndexBegin() const
Returns an iterator for the begin of the idx2MBBMap.
Definition: SlotIndexes.h:528
const RegisterBank * getRegBankOrNull(unsigned Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
std::vector< MachineBasicBlock * >::const_iterator const_succ_iterator
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
Definition: SmallPtrSet.h:381
self_iterator getIterator()
Definition: ilist_node.h:81
iterator_range< pred_iterator > predecessors()
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
Definition: SlotIndexes.h:502
VarInfo & getVarInfo(unsigned RegIdx)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MachineBasicBlock & front() const
MCSubRegIterator enumerates all sub-registers of Reg.
size_t size() const
Definition: SmallVector.h:52
virtual bool isPredicated(const MachineInstr &MI) const
Returns true if the instruction is already predicated.
bool isDebugInstr() const
Definition: MachineInstr.h:998
void print(raw_ostream &OS, const SlotIndexes *=nullptr) const
print - Print out the MachineFunction in a format suitable for debugging to the specified stream...
bool verify(const TargetRegisterInfo &TRI) const
Check that information hold by this instance make sense for the given TRI.
std::vector< MachineInstr * > Kills
Kills - List of MachineInstruction&#39;s which are the last use of this virtual register (kill it) in the...
Definition: LiveVariables.h:88
size_type size() const
Definition: SmallPtrSet.h:92
unsigned id
The ID number of this value.
Definition: LiveInterval.h:57
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:187
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
Iterator for intrusive lists based on ilist_node.
bool covers(const LiveRange &Other) const
Returns true if all segments of the Other live range are completely covered by this live range...
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false...
Definition: SmallPtrSet.h:377
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
Definition: SlotIndexes.h:197
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:533
Segments::const_iterator const_iterator
Definition: LiveInterval.h:208
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
bool isDebugValue() const
Definition: MachineInstr.h:996
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
Definition: LiveInterval.h:917
MachineOperand class - Representation of each machine instruction operand.
bool isInAllocatableClass(unsigned RegNo) const
Return true if the register is in the allocation of any register class.
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
bool isReservedRegUnit(unsigned Unit) const
Returns true when the given register unit is considered reserved.
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx. ...
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:225
LiveInterval & getInterval(unsigned Reg)
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:606
This class implements the register bank concept.
Definition: RegisterBank.h:28
int64_t getImm() const
unsigned pred_size() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
INITIALIZE_PASS(MachineVerifierPass, "machineverifier", "Verify generated machine code", false, false) FunctionPass *llvm
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarilly including Idx...
Definition: LiveInterval.h:416
void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const
For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
Special value supplied for machine level alias analysis.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
void setPreservesAll()
Set by analyses that do not transform their input at all.
bool isEarlyClobber() const
isEarlyClobber - Returns true if this is an early-clobber slot.
Definition: SlotIndexes.h:229
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
Base class for user error types.
Definition: Error.h:344
VNInfoList valnos
Definition: LiveInterval.h:199
const BitVector & getReservedRegs() const
getReservedRegs - Returns a reference to the frozen set of reserved registers.
unsigned succ_size() const
VNInfo * getValNumInfo(unsigned ValNo)
getValNumInfo - Returns pointer to the specified val#.
Definition: LiveInterval.h:304
bool isPointer() const
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:253
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
unsigned getNumValNums() const
Definition: LiveInterval.h:300
void set_subtract(S1Ty &S1, const S2Ty &S2)
set_subtract(A, B) - Compute A := A - B
Definition: SetOperations.h:62
Representation of each machine instruction.
Definition: MachineInstr.h:63
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
iterator begin() const
Definition: SmallPtrSet.h:396
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
Definition: SlotIndexes.h:289
bool isEHPad() const
Returns true if the block is a landing pad.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use...
#define I(x, y, z)
Definition: MD5.cpp:58
constexpr bool any() const
Definition: LaneBitmask.h:52
MI-level Statepoint operands.
Definition: StackMaps.h:154
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
bool tracksLiveness() const
tracksLiveness - Returns true when tracking register liveness accurately.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:322
uint32_t Size
Definition: Profile.cpp:46
size_type size() const
size - Returns the number of bits in this bitvector.
Definition: BitVector.h:169
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
Abstract Stack Frame Index.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const
Returns true if liveness for register class RC should be tracked at the subregister level...
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:170
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
iterator_range< livein_iterator > liveins() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator begin()
Definition: LiveInterval.h:210
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:806
const TargetRegisterClass * getRegClassOrNull(unsigned Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool hasProperty(Property P) const
bool hasInterval(int Slot) const
Definition: LiveStacks.h:77
static def_iterator def_end()
unsigned getSize() const
Get the maximal size in bits that fits in this register bank.
Definition: RegisterBank.h:54
aarch64 promote const
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel...
Definition: TargetOpcodes.h:30
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:129
LLVM Value Representation.
Definition: Value.h:72
Constant * getPersonalityFn() const
Get the personality function associated with this function.
Definition: Function.cpp:1298
mop_iterator operands_begin()
Definition: MachineInstr.h:452
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
AnalysisType * getAnalysisIfAvailable() const
getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information tha...
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:569
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:203
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:58
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg)
unsigned getGenericTypeIndex() const
Definition: MCInstrDesc.h:102
IRTranslator LLVM IR MI
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:639
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
A specialized PseudoSourceValue for holding FixedStack values, which must include a frame index...
ppc ctr loops verify
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:66
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:83
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
vni_iterator vni_end()
Definition: LiveInterval.h:220
bool set_union(S1Ty &S1, const S2Ty &S2)
set_union(A, B) - Compute A := A u B, return whether A changed.
Definition: SetOperations.h:22
static LLVM_ATTRIBUTE_UNUSED bool isJointlyDominated(const MachineBasicBlock *MBB, ArrayRef< SlotIndex > Defs, const SlotIndexes &Indexes)
A diagnostic function to check if the end of the block MBB is jointly dominated by the blocks corresp...
hexagon widen stores
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:540
bool isImplicit() const
void resize(size_type N)
Definition: SmallVector.h:350
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1244