LLVM  10.0.0svn
ARCRegisterInfo.cpp
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1 //===- ARCRegisterInfo.cpp - ARC Register Information -----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the ARC implementation of the MRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARCRegisterInfo.h"
14 #include "ARC.h"
15 #include "ARCInstrInfo.h"
16 #include "ARCMachineFunctionInfo.h"
17 #include "ARCSubtarget.h"
18 #include "llvm/ADT/BitVector.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/Support/Debug.h"
30 
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "arc-reg-info"
34 
35 #define GET_REGINFO_TARGET_DESC
36 #include "ARCGenRegisterInfo.inc"
37 
39  const ARCInstrInfo &TII, unsigned Reg,
40  unsigned FrameReg, int Offset, int StackSize,
41  int ObjSize, RegScavenger *RS, int SPAdj) {
42  assert(RS && "Need register scavenger.");
43  MachineInstr &MI = *II;
44  MachineBasicBlock &MBB = *MI.getParent();
45  DebugLoc dl = MI.getDebugLoc();
46  unsigned BaseReg = FrameReg;
47  unsigned KillState = 0;
48  if (MI.getOpcode() == ARC::LD_rs9 && (Offset >= 256 || Offset < -256)) {
49  // Loads can always be reached with LD_rlimm.
50  BuildMI(MBB, II, dl, TII.get(ARC::LD_rlimm), Reg)
51  .addReg(BaseReg)
52  .addImm(Offset)
54  MBB.erase(II);
55  return;
56  }
57 
58  if (MI.getOpcode() != ARC::GETFI && (Offset >= 256 || Offset < -256)) {
59  // We need to use a scratch register to reach the far-away frame indexes.
60  BaseReg = RS->FindUnusedReg(&ARC::GPR32RegClass);
61  if (!BaseReg) {
62  // We can be sure that the scavenged-register slot is within the range
63  // of the load offset.
64  const TargetRegisterInfo *TRI =
66  BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj);
67  assert(BaseReg && "Register scavenging failed.");
68  LLVM_DEBUG(dbgs() << "Scavenged register " << printReg(BaseReg, TRI)
69  << " for FrameReg=" << printReg(FrameReg, TRI)
70  << "+Offset=" << Offset << "\n");
71  (void)TRI;
72  RS->setRegUsed(BaseReg);
73  }
74  unsigned AddOpc = isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm;
75  BuildMI(MBB, II, dl, TII.get(AddOpc))
76  .addReg(BaseReg, RegState::Define)
77  .addReg(FrameReg)
78  .addImm(Offset);
79  Offset = 0;
80  KillState = RegState::Kill;
81  }
82  switch (MI.getOpcode()) {
83  case ARC::LD_rs9:
84  assert((Offset % 4 == 0) && "LD needs 4 byte alignment.");
86  case ARC::LDH_rs9:
87  case ARC::LDH_X_rs9:
88  assert((Offset % 2 == 0) && "LDH needs 2 byte alignment.");
90  case ARC::LDB_rs9:
91  case ARC::LDB_X_rs9:
92  LLVM_DEBUG(dbgs() << "Building LDFI\n");
93  BuildMI(MBB, II, dl, TII.get(MI.getOpcode()), Reg)
94  .addReg(BaseReg, KillState)
95  .addImm(Offset)
97  break;
98  case ARC::ST_rs9:
99  assert((Offset % 4 == 0) && "ST needs 4 byte alignment.");
101  case ARC::STH_rs9:
102  assert((Offset % 2 == 0) && "STH needs 2 byte alignment.");
104  case ARC::STB_rs9:
105  LLVM_DEBUG(dbgs() << "Building STFI\n");
106  BuildMI(MBB, II, dl, TII.get(MI.getOpcode()))
107  .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
108  .addReg(BaseReg, KillState)
109  .addImm(Offset)
111  break;
112  case ARC::GETFI:
113  LLVM_DEBUG(dbgs() << "Building GETFI\n");
114  BuildMI(MBB, II, dl,
115  TII.get(isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm))
116  .addReg(Reg, RegState::Define)
117  .addReg(FrameReg)
118  .addImm(Offset);
119  break;
120  default:
121  llvm_unreachable("Unhandled opcode.");
122  }
123 
124  // Erase old instruction.
125  MBB.erase(II);
126 }
127 
129 
131  return MF.getMMI().hasDebugInfo() || MF.getFunction().needsUnwindTableEntry();
132 }
133 
134 const MCPhysReg *
136  return CSR_ARC_SaveList;
137 }
138 
140  BitVector Reserved(getNumRegs());
141 
142  Reserved.set(ARC::ILINK);
143  Reserved.set(ARC::SP);
144  Reserved.set(ARC::GP);
145  Reserved.set(ARC::R25);
146  Reserved.set(ARC::BLINK);
147  Reserved.set(ARC::FP);
148  return Reserved;
149 }
150 
152  const MachineFunction &MF) const {
153  return true;
154 }
155 
157  const MachineFunction &MF) const {
158  return true;
159 }
160 
162  return true;
163 }
164 
166  int SPAdj, unsigned FIOperandNum,
167  RegScavenger *RS) const {
168  assert(SPAdj == 0 && "Unexpected");
169  MachineInstr &MI = *II;
170  MachineOperand &FrameOp = MI.getOperand(FIOperandNum);
171  int FrameIndex = FrameOp.getIndex();
172 
173  MachineFunction &MF = *MI.getParent()->getParent();
174  const ARCInstrInfo &TII = *MF.getSubtarget<ARCSubtarget>().getInstrInfo();
175  const ARCFrameLowering *TFI = getFrameLowering(MF);
176  int Offset = MF.getFrameInfo().getObjectOffset(FrameIndex);
177  int ObjSize = MF.getFrameInfo().getObjectSize(FrameIndex);
178  int StackSize = MF.getFrameInfo().getStackSize();
179  int LocalFrameSize = MF.getFrameInfo().getLocalFrameSize();
180 
181  LLVM_DEBUG(dbgs() << "\nFunction : " << MF.getName() << "\n");
182  LLVM_DEBUG(dbgs() << "<--------->\n");
183  LLVM_DEBUG(dbgs() << MI << "\n");
184  LLVM_DEBUG(dbgs() << "FrameIndex : " << FrameIndex << "\n");
185  LLVM_DEBUG(dbgs() << "ObjSize : " << ObjSize << "\n");
186  LLVM_DEBUG(dbgs() << "FrameOffset : " << Offset << "\n");
187  LLVM_DEBUG(dbgs() << "StackSize : " << StackSize << "\n");
188  LLVM_DEBUG(dbgs() << "LocalFrameSize : " << LocalFrameSize << "\n");
189  (void)LocalFrameSize;
190 
191  // Special handling of DBG_VALUE instructions.
192  if (MI.isDebugValue()) {
193  Register FrameReg = getFrameRegister(MF);
194  MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
195  MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
196  return;
197  }
198 
199  // fold constant into offset.
200  Offset += MI.getOperand(FIOperandNum + 1).getImm();
201 
202  // TODO: assert based on the load type:
203  // ldb needs no alignment,
204  // ldh needs 2 byte alignment
205  // ld needs 4 byte alignment
206  LLVM_DEBUG(dbgs() << "Offset : " << Offset << "\n"
207  << "<--------->\n");
208 
209  Register Reg = MI.getOperand(0).getReg();
210  assert(ARC::GPR32RegClass.contains(Reg) && "Unexpected register operand");
211 
212  if (!TFI->hasFP(MF)) {
213  Offset = StackSize + Offset;
214  if (FrameIndex >= 0)
215  assert((Offset >= 0 && Offset < StackSize) && "SP Offset not in bounds.");
216  } else {
217  if (FrameIndex >= 0) {
218  assert((Offset < 0 && -Offset <= StackSize) &&
219  "FP Offset not in bounds.");
220  }
221  }
222  ReplaceFrameIndex(II, TII, Reg, getFrameRegister(MF), Offset, StackSize,
223  ObjSize, RS, SPAdj);
224 }
225 
227  const ARCFrameLowering *TFI = getFrameLowering(MF);
228  return TFI->hasFP(MF) ? ARC::FP : ARC::SP;
229 }
230 
231 const uint32_t *
233  CallingConv::ID CC) const {
234  return CSR_ARC_RegMask;
235 }
BitVector & set()
Definition: BitVector.h:397
bool hasDebugInfo() const
Returns true if valid debug info is present.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:385
int64_t getLocalFrameSize() const
Get the size of the local object blob.
unsigned Reg
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
MachineModuleInfo & getMMI() const
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
return AArch64::GPR64RegClass contains(Reg)
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
const HexagonInstrInfo * TII
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
BitVector getReservedRegs(const MachineFunction &MF) const override
unsigned FindUnusedReg(const TargetRegisterClass *RC) const
Find an unused register of the specified register class.
bool useFPForScavengingIndex(const MachineFunction &MF) const override
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
unsigned getKillRegState(bool B)
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:19
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
This file declares the machine register scavenger class.
static bool needsFrameMoves(const MachineFunction &MF)
Return whether to emit frame moves.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
Register getFrameRegister(const MachineFunction &MF) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:536
bool isDebugValue() const
MachineOperand class - Representation of each machine instruction operand.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
bool needsUnwindTableEntry() const
True if this function needs an unwind table.
Definition: Function.h:594
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:256
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
bool requiresRegisterScavenging(const MachineFunction &MF) const override
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned scavengeRegister(const TargetRegisterClass *RC, MachineBasicBlock::iterator I, int SPAdj, bool AllowSpill=true)
Make a register of the specific register class available and do the appropriate bookkeeping.
void setRegUsed(unsigned Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Tell the scavenger a register is used.
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:258
IRTranslator LLVM IR MI
static void ReplaceFrameIndex(MachineBasicBlock::iterator II, const ARCInstrInfo &TII, unsigned Reg, unsigned FrameReg, int Offset, int StackSize, int ObjSize, RegScavenger *RS, int SPAdj)
Register getReg() const
getReg - Returns the register number.
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19