LLVM  6.0.0svn
ARCRegisterInfo.cpp
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1 //===- ARCRegisterInfo.cpp - ARC Register Information -----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the ARC implementation of the MRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARCRegisterInfo.h"
15 #include "ARC.h"
16 #include "ARCInstrInfo.h"
17 #include "ARCMachineFunctionInfo.h"
18 #include "ARCSubtarget.h"
19 #include "llvm/ADT/BitVector.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/Support/Debug.h"
31 
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "arc-reg-info"
35 
36 #define GET_REGINFO_TARGET_DESC
37 #include "ARCGenRegisterInfo.inc"
38 
40  const ARCInstrInfo &TII, unsigned Reg,
41  unsigned FrameReg, int Offset, int StackSize,
42  int ObjSize, RegScavenger *RS, int SPAdj) {
43  assert(RS && "Need register scavenger.");
44  MachineInstr &MI = *II;
45  MachineBasicBlock &MBB = *MI.getParent();
46  DebugLoc dl = MI.getDebugLoc();
47  unsigned BaseReg = FrameReg;
48  unsigned KillState = 0;
49  if (MI.getOpcode() == ARC::LD_rs9 && (Offset >= 256 || Offset < -256)) {
50  // Loads can always be reached with LD_rlimm.
51  BuildMI(MBB, II, dl, TII.get(ARC::LD_rlimm), Reg)
52  .addReg(BaseReg)
53  .addImm(Offset)
55  MBB.erase(II);
56  return;
57  }
58 
59  if (MI.getOpcode() != ARC::GETFI && (Offset >= 256 || Offset < -256)) {
60  // We need to use a scratch register to reach the far-away frame indexes.
61  BaseReg = RS->FindUnusedReg(&ARC::GPR32RegClass);
62  if (!BaseReg) {
63  // We can be sure that the scavenged-register slot is within the range
64  // of the load offset.
65  const TargetRegisterInfo *TRI =
67  BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj);
68  assert(BaseReg && "Register scavenging failed.");
69  DEBUG(dbgs() << "Scavenged register " << PrintReg(BaseReg, TRI)
70  << " for FrameReg=" << PrintReg(FrameReg, TRI)
71  << "+Offset=" << Offset << "\n");
72  (void)TRI;
73  RS->setRegUsed(BaseReg);
74  }
75  unsigned AddOpc = isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm;
76  BuildMI(MBB, II, dl, TII.get(AddOpc))
77  .addReg(BaseReg, RegState::Define)
78  .addReg(FrameReg)
79  .addImm(Offset);
80  Offset = 0;
81  KillState = RegState::Kill;
82  }
83  switch (MI.getOpcode()) {
84  case ARC::LD_rs9:
85  assert((Offset % 4 == 0) && "LD needs 4 byte alignment.");
86  case ARC::LDH_rs9:
87  case ARC::LDH_X_rs9:
88  assert((Offset % 2 == 0) && "LDH needs 2 byte alignment.");
89  case ARC::LDB_rs9:
90  case ARC::LDB_X_rs9:
91  DEBUG(dbgs() << "Building LDFI\n");
92  BuildMI(MBB, II, dl, TII.get(MI.getOpcode()), Reg)
93  .addReg(BaseReg, KillState)
94  .addImm(Offset)
96  break;
97  case ARC::ST_rs9:
98  assert((Offset % 4 == 0) && "ST needs 4 byte alignment.");
99  case ARC::STH_rs9:
100  assert((Offset % 2 == 0) && "STH needs 2 byte alignment.");
101  case ARC::STB_rs9:
102  DEBUG(dbgs() << "Building STFI\n");
103  BuildMI(MBB, II, dl, TII.get(MI.getOpcode()))
104  .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
105  .addReg(BaseReg, KillState)
106  .addImm(Offset)
108  break;
109  case ARC::GETFI:
110  DEBUG(dbgs() << "Building GETFI\n");
111  BuildMI(MBB, II, dl,
112  TII.get(isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm))
113  .addReg(Reg, RegState::Define)
114  .addReg(FrameReg)
115  .addImm(Offset);
116  break;
117  default:
118  llvm_unreachable("Unhandled opcode.");
119  }
120 
121  // Erase old instruction.
122  MBB.erase(II);
123 }
124 
126 
128  return MF.getMMI().hasDebugInfo() ||
130 }
131 
132 const MCPhysReg *
134  return CSR_ARC_SaveList;
135 }
136 
138  BitVector Reserved(getNumRegs());
139 
140  Reserved.set(ARC::ILINK);
141  Reserved.set(ARC::SP);
142  Reserved.set(ARC::GP);
143  Reserved.set(ARC::R25);
144  Reserved.set(ARC::BLINK);
145  Reserved.set(ARC::FP);
146  return Reserved;
147 }
148 
150  const MachineFunction &MF) const {
151  return true;
152 }
153 
155  const MachineFunction &MF) const {
156  return true;
157 }
158 
160  return true;
161 }
162 
164  int SPAdj, unsigned FIOperandNum,
165  RegScavenger *RS) const {
166  assert(SPAdj == 0 && "Unexpected");
167  MachineInstr &MI = *II;
168  MachineOperand &FrameOp = MI.getOperand(FIOperandNum);
169  int FrameIndex = FrameOp.getIndex();
170 
171  MachineFunction &MF = *MI.getParent()->getParent();
172  const ARCInstrInfo &TII = *MF.getSubtarget<ARCSubtarget>().getInstrInfo();
173  const ARCFrameLowering *TFI = getFrameLowering(MF);
174  int Offset = MF.getFrameInfo().getObjectOffset(FrameIndex);
175  int ObjSize = MF.getFrameInfo().getObjectSize(FrameIndex);
176  int StackSize = MF.getFrameInfo().getStackSize();
177  int LocalFrameSize = MF.getFrameInfo().getLocalFrameSize();
178 
179  DEBUG(dbgs() << "\nFunction : " << MF.getName() << "\n");
180  DEBUG(dbgs() << "<--------->\n");
181  DEBUG(dbgs() << MI << "\n");
182  DEBUG(dbgs() << "FrameIndex : " << FrameIndex << "\n");
183  DEBUG(dbgs() << "ObjSize : " << ObjSize << "\n");
184  DEBUG(dbgs() << "FrameOffset : " << Offset << "\n");
185  DEBUG(dbgs() << "StackSize : " << StackSize << "\n");
186  DEBUG(dbgs() << "LocalFrameSize : " << LocalFrameSize << "\n");
187  (void)LocalFrameSize;
188 
189  // Special handling of DBG_VALUE instructions.
190  if (MI.isDebugValue()) {
191  unsigned FrameReg = getFrameRegister(MF);
192  MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
193  MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
194  return;
195  }
196 
197  // fold constant into offset.
198  Offset += MI.getOperand(FIOperandNum + 1).getImm();
199 
200  // TODO: assert based on the load type:
201  // ldb needs no alignment,
202  // ldh needs 2 byte alignment
203  // ld needs 4 byte alignment
204  DEBUG(dbgs() << "Offset : " << Offset << "\n"
205  << "<--------->\n");
206 
207  unsigned Reg = MI.getOperand(0).getReg();
208  assert(ARC::GPR32RegClass.contains(Reg) && "Unexpected register operand");
209 
210  if (!TFI->hasFP(MF)) {
211  Offset = StackSize + Offset;
212  if (FrameIndex >= 0)
213  assert((Offset >= 0 && Offset < StackSize) && "SP Offset not in bounds.");
214  } else {
215  if (FrameIndex >= 0) {
216  assert((Offset < 0 && -Offset <= StackSize) &&
217  "FP Offset not in bounds.");
218  }
219  }
220  ReplaceFrameIndex(II, TII, Reg, getFrameRegister(MF), Offset, StackSize,
221  ObjSize, RS, SPAdj);
222 }
223 
225  const ARCFrameLowering *TFI = getFrameLowering(MF);
226  return TFI->hasFP(MF) ? ARC::FP : ARC::SP;
227 }
228 
229 const uint32_t *
231  CallingConv::ID CC) const {
232  return CSR_ARC_RegMask;
233 }
BitVector & set()
Definition: BitVector.h:398
bool hasDebugInfo() const
Returns true if valid debug info is present.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:268
unsigned getReg() const
getReg - Returns the register number.
int64_t getLocalFrameSize() const
Get the size of the local object blob.
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
A debug info location.
Definition: DebugLoc.h:34
MachineModuleInfo & getMMI() const
unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const
Find an unused register of the specified register class.
return AArch64::GPR64RegClass contains(Reg)
unsigned getFrameRegister(const MachineFunction &MF) const override
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
const HexagonInstrInfo * TII
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
BitVector getReservedRegs(const MachineFunction &MF) const override
bool useFPForScavengingIndex(const MachineFunction &MF) const override
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
unsigned getKillRegState(bool B)
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
This file declares the machine register scavenger class.
static bool needsFrameMoves(const MachineFunction &MF)
Return whether to emit frame moves.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:389
bool isDebugValue() const
Definition: MachineInstr.h:816
MachineOperand class - Representation of each machine instruction operand.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
int64_t getImm() const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
bool needsUnwindTableEntry() const
True if this function needs an unwind table.
Definition: Function.h:505
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
Representation of each machine instruction.
Definition: MachineInstr.h:59
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
bool requiresRegisterScavenging(const MachineFunction &MF) const override
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void setRegUsed(unsigned Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Tell the scavenger a register is used.
#define DEBUG(X)
Definition: Debug.h:118
IRTranslator LLVM IR MI
static void ReplaceFrameIndex(MachineBasicBlock::iterator II, const ARCInstrInfo &TII, unsigned Reg, unsigned FrameReg, int Offset, int StackSize, int ObjSize, RegScavenger *RS, int SPAdj)
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
unsigned scavengeRegister(const TargetRegisterClass *RegClass, MachineBasicBlock::iterator I, int SPAdj)
Make a register of the specific register class available and do the appropriate bookkeeping.