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HexagonVLIWPacketizer.cpp
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1 //===- HexagonPacketizer.cpp - VLIW packetizer ----------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements a simple VLIW packetizer using DFA. The packetizer works on
11 // machine basic blocks. For each instruction I in BB, the packetizer consults
12 // the DFA to see if machine resources are available to execute I. If so, the
13 // packetizer checks if I depends on any instruction J in the current packet.
14 // If no dependency is found, I is added to current packet and machine resource
15 // is marked as taken. If any dependency is found, a target API call is made to
16 // prune the dependence.
17 //
18 //===----------------------------------------------------------------------===//
19 
20 #include "HexagonVLIWPacketizer.h"
21 #include "Hexagon.h"
22 #include "HexagonInstrInfo.h"
23 #include "HexagonRegisterInfo.h"
24 #include "HexagonSubtarget.h"
25 #include "llvm/ADT/BitVector.h"
26 #include "llvm/ADT/DenseSet.h"
27 #include "llvm/ADT/STLExtras.h"
42 #include "llvm/IR/DebugLoc.h"
43 #include "llvm/MC/MCInstrDesc.h"
44 #include "llvm/Pass.h"
46 #include "llvm/Support/Debug.h"
49 #include <cassert>
50 #include <cstdint>
51 #include <iterator>
52 
53 using namespace llvm;
54 
55 #define DEBUG_TYPE "packets"
56 
57 static cl::opt<bool> DisablePacketizer("disable-packetizer", cl::Hidden,
58  cl::ZeroOrMore, cl::init(false),
59  cl::desc("Disable Hexagon packetizer pass"));
60 
61 cl::opt<bool> Slot1Store("slot1-store-slot0-load", cl::Hidden,
62  cl::ZeroOrMore, cl::init(true),
63  cl::desc("Allow slot1 store and slot0 load"));
64 
65 static cl::opt<bool> PacketizeVolatiles("hexagon-packetize-volatiles",
67  cl::desc("Allow non-solo packetization of volatile memory references"));
68 
69 static cl::opt<bool> EnableGenAllInsnClass("enable-gen-insn", cl::init(false),
70  cl::Hidden, cl::ZeroOrMore, cl::desc("Generate all instruction with TC"));
71 
72 static cl::opt<bool> DisableVecDblNVStores("disable-vecdbl-nv-stores",
74  cl::desc("Disable vector double new-value-stores"));
75 
77 
78 namespace llvm {
79 
82 
83 } // end namespace llvm
84 
85 namespace {
86 
87  class HexagonPacketizer : public MachineFunctionPass {
88  public:
89  static char ID;
90 
91  HexagonPacketizer(bool Min = false)
92  : MachineFunctionPass(ID), Minimal(Min) {}
93 
94  void getAnalysisUsage(AnalysisUsage &AU) const override {
95  AU.setPreservesCFG();
103  }
104 
105  StringRef getPassName() const override { return "Hexagon Packetizer"; }
106  bool runOnMachineFunction(MachineFunction &Fn) override;
107 
108  MachineFunctionProperties getRequiredProperties() const override {
111  }
112 
113  private:
114  const HexagonInstrInfo *HII;
115  const HexagonRegisterInfo *HRI;
116  const bool Minimal;
117  };
118 
119 } // end anonymous namespace
120 
121 char HexagonPacketizer::ID = 0;
122 
123 INITIALIZE_PASS_BEGIN(HexagonPacketizer, "hexagon-packetizer",
124  "Hexagon Packetizer", false, false)
129 INITIALIZE_PASS_END(HexagonPacketizer, "hexagon-packetizer",
130  "Hexagon Packetizer", false, false)
131 
133  MachineLoopInfo &MLI, AliasAnalysis *AA,
134  const MachineBranchProbabilityInfo *MBPI, bool Minimal)
135  : VLIWPacketizerList(MF, MLI, AA), MBPI(MBPI), MLI(&MLI),
136  Minimal(Minimal) {
137  HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
138  HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
139 
140  addMutation(llvm::make_unique<HexagonSubtarget::UsrOverflowMutation>());
141  addMutation(llvm::make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
142  addMutation(llvm::make_unique<HexagonSubtarget::BankConflictMutation>());
143 }
144 
145 // Check if FirstI modifies a register that SecondI reads.
146 static bool hasWriteToReadDep(const MachineInstr &FirstI,
147  const MachineInstr &SecondI,
148  const TargetRegisterInfo *TRI) {
149  for (auto &MO : FirstI.operands()) {
150  if (!MO.isReg() || !MO.isDef())
151  continue;
152  unsigned R = MO.getReg();
153  if (SecondI.readsRegister(R, TRI))
154  return true;
155  }
156  return false;
157 }
158 
159 
161  MachineBasicBlock::iterator BundleIt, bool Before) {
163  if (Before)
164  InsertPt = BundleIt.getInstrIterator();
165  else
166  InsertPt = std::next(BundleIt).getInstrIterator();
167 
168  MachineBasicBlock &B = *MI.getParent();
169  // The instruction should at least be bundled with the preceding instruction
170  // (there will always be one, i.e. BUNDLE, if nothing else).
172  if (MI.isBundledWithSucc()) {
175  } else {
176  // If it's not bundled with the successor (i.e. it is the last one
177  // in the bundle), then we can simply unbundle it from the predecessor,
178  // which will take care of updating the predecessor's flag.
179  MI.unbundleFromPred();
180  }
181  B.splice(InsertPt, &B, MI.getIterator());
182 
183  // Get the size of the bundle without asserting.
186  unsigned Size = 0;
187  for (++I; I != E && I->isBundledWithPred(); ++I)
188  ++Size;
189 
190  // If there are still two or more instructions, then there is nothing
191  // else to be done.
192  if (Size > 1)
193  return BundleIt;
194 
195  // Otherwise, extract the single instruction out and delete the bundle.
196  MachineBasicBlock::iterator NextIt = std::next(BundleIt);
197  MachineInstr &SingleI = *BundleIt->getNextNode();
198  SingleI.unbundleFromPred();
199  assert(!SingleI.isBundledWithSucc());
200  BundleIt->eraseFromParent();
201  return NextIt;
202 }
203 
204 bool HexagonPacketizer::runOnMachineFunction(MachineFunction &MF) {
205  auto &HST = MF.getSubtarget<HexagonSubtarget>();
206  HII = HST.getInstrInfo();
207  HRI = HST.getRegisterInfo();
208  auto &MLI = getAnalysis<MachineLoopInfo>();
209  auto *AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
210  auto *MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
211 
213  HII->genAllInsnTimingClasses(MF);
214 
215  // Instantiate the packetizer.
216  bool MinOnly = Minimal || DisablePacketizer || !HST.usePackets() ||
217  skipFunction(MF.getFunction());
218  HexagonPacketizerList Packetizer(MF, MLI, AA, MBPI, MinOnly);
219 
220  // DFA state table should not be empty.
221  assert(Packetizer.getResourceTracker() && "Empty DFA table!");
222 
223  // Loop over all basic blocks and remove KILL pseudo-instructions
224  // These instructions confuse the dependence analysis. Consider:
225  // D0 = ... (Insn 0)
226  // R0 = KILL R0, D0 (Insn 1)
227  // R0 = ... (Insn 2)
228  // Here, Insn 1 will result in the dependence graph not emitting an output
229  // dependence between Insn 0 and Insn 2. This can lead to incorrect
230  // packetization
231  for (MachineBasicBlock &MB : MF) {
232  auto End = MB.end();
233  auto MI = MB.begin();
234  while (MI != End) {
235  auto NextI = std::next(MI);
236  if (MI->isKill()) {
237  MB.erase(MI);
238  End = MB.end();
239  }
240  MI = NextI;
241  }
242  }
243 
244  // Loop over all of the basic blocks.
245  for (auto &MB : MF) {
246  auto Begin = MB.begin(), End = MB.end();
247  while (Begin != End) {
248  // Find the first non-boundary starting from the end of the last
249  // scheduling region.
250  MachineBasicBlock::iterator RB = Begin;
251  while (RB != End && HII->isSchedulingBoundary(*RB, &MB, MF))
252  ++RB;
253  // Find the first boundary starting from the beginning of the new
254  // region.
256  while (RE != End && !HII->isSchedulingBoundary(*RE, &MB, MF))
257  ++RE;
258  // Add the scheduling boundary if it's not block end.
259  if (RE != End)
260  ++RE;
261  // If RB == End, then RE == End.
262  if (RB != End)
263  Packetizer.PacketizeMIs(&MB, RB, RE);
264 
265  Begin = RE;
266  }
267  }
268 
269  Packetizer.unpacketizeSoloInstrs(MF);
270  return true;
271 }
272 
273 // Reserve resources for a constant extender. Trigger an assertion if the
274 // reservation fails.
276  if (!tryAllocateResourcesForConstExt(true))
277  llvm_unreachable("Resources not available");
278 }
279 
281  return tryAllocateResourcesForConstExt(false);
282 }
283 
284 // Allocate resources (i.e. 4 bytes) for constant extender. If succeeded,
285 // return true, otherwise, return false.
287  auto *ExtMI = MF.CreateMachineInstr(HII->get(Hexagon::A4_ext), DebugLoc());
288  bool Avail = ResourceTracker->canReserveResources(*ExtMI);
289  if (Reserve && Avail)
290  ResourceTracker->reserveResources(*ExtMI);
291  MF.DeleteMachineInstr(ExtMI);
292  return Avail;
293 }
294 
296  SDep::Kind DepType, unsigned DepReg) {
297  // Check for LR dependence.
298  if (DepReg == HRI->getRARegister())
299  return true;
300 
301  if (HII->isDeallocRet(MI))
302  if (DepReg == HRI->getFrameRegister() || DepReg == HRI->getStackRegister())
303  return true;
304 
305  // Call-like instructions can be packetized with preceding instructions
306  // that define registers implicitly used or modified by the call. Explicit
307  // uses are still prohibited, as in the case of indirect calls:
308  // r0 = ...
309  // J2_jumpr r0
310  if (DepType == SDep::Data) {
311  for (const MachineOperand MO : MI.operands())
312  if (MO.isReg() && MO.getReg() == DepReg && !MO.isImplicit())
313  return true;
314  }
315 
316  return false;
317 }
318 
319 static bool isRegDependence(const SDep::Kind DepType) {
320  return DepType == SDep::Data || DepType == SDep::Anti ||
321  DepType == SDep::Output;
322 }
323 
324 static bool isDirectJump(const MachineInstr &MI) {
325  return MI.getOpcode() == Hexagon::J2_jump;
326 }
327 
328 static bool isSchedBarrier(const MachineInstr &MI) {
329  switch (MI.getOpcode()) {
330  case Hexagon::Y2_barrier:
331  return true;
332  }
333  return false;
334 }
335 
336 static bool isControlFlow(const MachineInstr &MI) {
337  return MI.getDesc().isTerminator() || MI.getDesc().isCall();
338 }
339 
340 /// Returns true if the instruction modifies a callee-saved register.
342  const TargetRegisterInfo *TRI) {
343  const MachineFunction &MF = *MI.getParent()->getParent();
344  for (auto *CSR = TRI->getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR)
345  if (MI.modifiesRegister(*CSR, TRI))
346  return true;
347  return false;
348 }
349 
350 // Returns true if an instruction can be promoted to .new predicate or
351 // new-value store.
353  const TargetRegisterClass *NewRC) {
354  // Vector stores can be predicated, and can be new-value stores, but
355  // they cannot be predicated on a .new predicate value.
356  if (NewRC == &Hexagon::PredRegsRegClass) {
357  if (HII->isHVXVec(MI) && MI.mayStore())
358  return false;
359  return HII->isPredicated(MI) && HII->getDotNewPredOp(MI, nullptr) > 0;
360  }
361  // If the class is not PredRegs, it could only apply to new-value stores.
362  return HII->mayBeNewStore(MI);
363 }
364 
365 // Promote an instructiont to its .cur form.
366 // At this time, we have already made a call to canPromoteToDotCur and made
367 // sure that it can *indeed* be promoted.
370  const TargetRegisterClass* RC) {
371  assert(DepType == SDep::Data);
372  int CurOpcode = HII->getDotCurOp(MI);
373  MI.setDesc(HII->get(CurOpcode));
374  return true;
375 }
376 
378  MachineInstr *MI = nullptr;
379  for (auto BI : CurrentPacketMIs) {
380  LLVM_DEBUG(dbgs() << "Cleanup packet has "; BI->dump(););
381  if (HII->isDotCurInst(*BI)) {
382  MI = BI;
383  continue;
384  }
385  if (MI) {
386  for (auto &MO : BI->operands())
387  if (MO.isReg() && MO.getReg() == MI->getOperand(0).getReg())
388  return;
389  }
390  }
391  if (!MI)
392  return;
393  // We did not find a use of the CUR, so de-cur it.
394  MI->setDesc(HII->get(HII->getNonDotCurOp(*MI)));
395  LLVM_DEBUG(dbgs() << "Demoted CUR "; MI->dump(););
396 }
397 
398 // Check to see if an instruction can be dot cur.
400  const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII,
401  const TargetRegisterClass *RC) {
402  if (!HII->isHVXVec(MI))
403  return false;
404  if (!HII->isHVXVec(*MII))
405  return false;
406 
407  // Already a dot new instruction.
408  if (HII->isDotCurInst(MI) && !HII->mayBeCurLoad(MI))
409  return false;
410 
411  if (!HII->mayBeCurLoad(MI))
412  return false;
413 
414  // The "cur value" cannot come from inline asm.
415  if (PacketSU->getInstr()->isInlineAsm())
416  return false;
417 
418  // Make sure candidate instruction uses cur.
419  LLVM_DEBUG(dbgs() << "Can we DOT Cur Vector MI\n"; MI.dump();
420  dbgs() << "in packet\n";);
421  MachineInstr &MJ = *MII;
422  LLVM_DEBUG({
423  dbgs() << "Checking CUR against ";
424  MJ.dump();
425  });
426  unsigned DestReg = MI.getOperand(0).getReg();
427  bool FoundMatch = false;
428  for (auto &MO : MJ.operands())
429  if (MO.isReg() && MO.getReg() == DestReg)
430  FoundMatch = true;
431  if (!FoundMatch)
432  return false;
433 
434  // Check for existing uses of a vector register within the packet which
435  // would be affected by converting a vector load into .cur formt.
436  for (auto BI : CurrentPacketMIs) {
437  LLVM_DEBUG(dbgs() << "packet has "; BI->dump(););
438  if (BI->readsRegister(DepReg, MF.getSubtarget().getRegisterInfo()))
439  return false;
440  }
441 
442  LLVM_DEBUG(dbgs() << "Can Dot CUR MI\n"; MI.dump(););
443  // We can convert the opcode into a .cur.
444  return true;
445 }
446 
447 // Promote an instruction to its .new form. At this time, we have already
448 // made a call to canPromoteToDotNew and made sure that it can *indeed* be
449 // promoted.
452  const TargetRegisterClass* RC) {
453  assert(DepType == SDep::Data);
454  int NewOpcode;
455  if (RC == &Hexagon::PredRegsRegClass)
456  NewOpcode = HII->getDotNewPredOp(MI, MBPI);
457  else
458  NewOpcode = HII->getDotNewOp(MI);
459  MI.setDesc(HII->get(NewOpcode));
460  return true;
461 }
462 
464  int NewOpcode = HII->getDotOldOp(MI);
465  MI.setDesc(HII->get(NewOpcode));
466  return true;
467 }
468 
470  unsigned Opc = MI.getOpcode();
471  switch (Opc) {
472  case Hexagon::S2_storerd_io:
473  case Hexagon::S2_storeri_io:
474  case Hexagon::S2_storerh_io:
475  case Hexagon::S2_storerb_io:
476  break;
477  default:
478  llvm_unreachable("Unexpected instruction");
479  }
480  unsigned FrameSize = MF.getFrameInfo().getStackSize();
481  MachineOperand &Off = MI.getOperand(1);
482  int64_t NewOff = Off.getImm() - (FrameSize + HEXAGON_LRFP_SIZE);
483  if (HII->isValidOffset(Opc, NewOff, HRI)) {
484  Off.setImm(NewOff);
485  return true;
486  }
487  return false;
488 }
489 
491  unsigned Opc = MI.getOpcode();
492  switch (Opc) {
493  case Hexagon::S2_storerd_io:
494  case Hexagon::S2_storeri_io:
495  case Hexagon::S2_storerh_io:
496  case Hexagon::S2_storerb_io:
497  break;
498  default:
499  llvm_unreachable("Unexpected instruction");
500  }
501  unsigned FrameSize = MF.getFrameInfo().getStackSize();
502  MachineOperand &Off = MI.getOperand(1);
503  Off.setImm(Off.getImm() + FrameSize + HEXAGON_LRFP_SIZE);
504 }
505 
506 /// Return true if we can update the offset in MI so that MI and MJ
507 /// can be packetized together.
509  assert(SUI->getInstr() && SUJ->getInstr());
510  MachineInstr &MI = *SUI->getInstr();
511  MachineInstr &MJ = *SUJ->getInstr();
512 
513  unsigned BPI, OPI;
514  if (!HII->getBaseAndOffsetPosition(MI, BPI, OPI))
515  return false;
516  unsigned BPJ, OPJ;
517  if (!HII->getBaseAndOffsetPosition(MJ, BPJ, OPJ))
518  return false;
519  unsigned Reg = MI.getOperand(BPI).getReg();
520  if (Reg != MJ.getOperand(BPJ).getReg())
521  return false;
522  // Make sure that the dependences do not restrict adding MI to the packet.
523  // That is, ignore anti dependences, and make sure the only data dependence
524  // involves the specific register.
525  for (const auto &PI : SUI->Preds)
526  if (PI.getKind() != SDep::Anti &&
527  (PI.getKind() != SDep::Data || PI.getReg() != Reg))
528  return false;
529  int Incr;
530  if (!HII->getIncrementValue(MJ, Incr))
531  return false;
532 
533  int64_t Offset = MI.getOperand(OPI).getImm();
534  if (!HII->isValidOffset(MI.getOpcode(), Offset+Incr, HRI))
535  return false;
536 
537  MI.getOperand(OPI).setImm(Offset + Incr);
538  ChangedOffset = Offset;
539  return true;
540 }
541 
542 /// Undo the changed offset. This is needed if the instruction cannot be
543 /// added to the current packet due to a different instruction.
545  unsigned BP, OP;
546  if (!HII->getBaseAndOffsetPosition(MI, BP, OP))
547  llvm_unreachable("Unable to find base and offset operands.");
548  MI.getOperand(OP).setImm(ChangedOffset);
549 }
550 
555 };
556 
557 /// Returns true if an instruction is predicated on p0 and false if it's
558 /// predicated on !p0.
560  const HexagonInstrInfo *HII) {
561  if (!HII->isPredicated(MI))
562  return PK_Unknown;
563  if (HII->isPredicatedTrue(MI))
564  return PK_True;
565  return PK_False;
566 }
567 
569  const HexagonInstrInfo *HII) {
570  assert(HII->isPostIncrement(MI) && "Not a post increment operation.");
571 #ifndef NDEBUG
572  // Post Increment means duplicates. Use dense map to find duplicates in the
573  // list. Caution: Densemap initializes with the minimum of 64 buckets,
574  // whereas there are at most 5 operands in the post increment.
575  DenseSet<unsigned> DefRegsSet;
576  for (auto &MO : MI.operands())
577  if (MO.isReg() && MO.isDef())
578  DefRegsSet.insert(MO.getReg());
579 
580  for (auto &MO : MI.operands())
581  if (MO.isReg() && MO.isUse() && DefRegsSet.count(MO.getReg()))
582  return MO;
583 #else
584  if (MI.mayLoad()) {
585  const MachineOperand &Op1 = MI.getOperand(1);
586  // The 2nd operand is always the post increment operand in load.
587  assert(Op1.isReg() && "Post increment operand has be to a register.");
588  return Op1;
589  }
590  if (MI.getDesc().mayStore()) {
591  const MachineOperand &Op0 = MI.getOperand(0);
592  // The 1st operand is always the post increment operand in store.
593  assert(Op0.isReg() && "Post increment operand has be to a register.");
594  return Op0;
595  }
596 #endif
597  // we should never come here.
598  llvm_unreachable("mayLoad or mayStore not set for Post Increment operation");
599 }
600 
601 // Get the value being stored.
603  // value being stored is always the last operand.
604  return MI.getOperand(MI.getNumOperands()-1);
605 }
606 
607 static bool isLoadAbsSet(const MachineInstr &MI) {
608  unsigned Opc = MI.getOpcode();
609  switch (Opc) {
610  case Hexagon::L4_loadrd_ap:
611  case Hexagon::L4_loadrb_ap:
612  case Hexagon::L4_loadrh_ap:
613  case Hexagon::L4_loadrub_ap:
614  case Hexagon::L4_loadruh_ap:
615  case Hexagon::L4_loadri_ap:
616  return true;
617  }
618  return false;
619 }
620 
622  assert(isLoadAbsSet(MI));
623  return MI.getOperand(1);
624 }
625 
626 // Can be new value store?
627 // Following restrictions are to be respected in convert a store into
628 // a new value store.
629 // 1. If an instruction uses auto-increment, its address register cannot
630 // be a new-value register. Arch Spec 5.4.2.1
631 // 2. If an instruction uses absolute-set addressing mode, its address
632 // register cannot be a new-value register. Arch Spec 5.4.2.1.
633 // 3. If an instruction produces a 64-bit result, its registers cannot be used
634 // as new-value registers. Arch Spec 5.4.2.2.
635 // 4. If the instruction that sets the new-value register is conditional, then
636 // the instruction that uses the new-value register must also be conditional,
637 // and both must always have their predicates evaluate identically.
638 // Arch Spec 5.4.2.3.
639 // 5. There is an implied restriction that a packet cannot have another store,
640 // if there is a new value store in the packet. Corollary: if there is
641 // already a store in a packet, there can not be a new value store.
642 // Arch Spec: 3.4.4.2
644  const MachineInstr &PacketMI, unsigned DepReg) {
645  // Make sure we are looking at the store, that can be promoted.
646  if (!HII->mayBeNewStore(MI))
647  return false;
648 
649  // Make sure there is dependency and can be new value'd.
650  const MachineOperand &Val = getStoreValueOperand(MI);
651  if (Val.isReg() && Val.getReg() != DepReg)
652  return false;
653 
654  const MCInstrDesc& MCID = PacketMI.getDesc();
655 
656  // First operand is always the result.
657  const TargetRegisterClass *PacketRC = HII->getRegClass(MCID, 0, HRI, MF);
658  // Double regs can not feed into new value store: PRM section: 5.4.2.2.
659  if (PacketRC == &Hexagon::DoubleRegsRegClass)
660  return false;
661 
662  // New-value stores are of class NV (slot 0), dual stores require class ST
663  // in slot 0 (PRM 5.5).
664  for (auto I : CurrentPacketMIs) {
665  SUnit *PacketSU = MIToSUnit.find(I)->second;
666  if (PacketSU->getInstr()->mayStore())
667  return false;
668  }
669 
670  // Make sure it's NOT the post increment register that we are going to
671  // new value.
672  if (HII->isPostIncrement(MI) &&
673  getPostIncrementOperand(MI, HII).getReg() == DepReg) {
674  return false;
675  }
676 
677  if (HII->isPostIncrement(PacketMI) && PacketMI.mayLoad() &&
678  getPostIncrementOperand(PacketMI, HII).getReg() == DepReg) {
679  // If source is post_inc, or absolute-set addressing, it can not feed
680  // into new value store
681  // r3 = memw(r2++#4)
682  // memw(r30 + #-1404) = r2.new -> can not be new value store
683  // arch spec section: 5.4.2.1.
684  return false;
685  }
686 
687  if (isLoadAbsSet(PacketMI) && getAbsSetOperand(PacketMI).getReg() == DepReg)
688  return false;
689 
690  // If the source that feeds the store is predicated, new value store must
691  // also be predicated.
692  if (HII->isPredicated(PacketMI)) {
693  if (!HII->isPredicated(MI))
694  return false;
695 
696  // Check to make sure that they both will have their predicates
697  // evaluate identically.
698  unsigned predRegNumSrc = 0;
699  unsigned predRegNumDst = 0;
700  const TargetRegisterClass* predRegClass = nullptr;
701 
702  // Get predicate register used in the source instruction.
703  for (auto &MO : PacketMI.operands()) {
704  if (!MO.isReg())
705  continue;
706  predRegNumSrc = MO.getReg();
707  predRegClass = HRI->getMinimalPhysRegClass(predRegNumSrc);
708  if (predRegClass == &Hexagon::PredRegsRegClass)
709  break;
710  }
711  assert((predRegClass == &Hexagon::PredRegsRegClass) &&
712  "predicate register not found in a predicated PacketMI instruction");
713 
714  // Get predicate register used in new-value store instruction.
715  for (auto &MO : MI.operands()) {
716  if (!MO.isReg())
717  continue;
718  predRegNumDst = MO.getReg();
719  predRegClass = HRI->getMinimalPhysRegClass(predRegNumDst);
720  if (predRegClass == &Hexagon::PredRegsRegClass)
721  break;
722  }
723  assert((predRegClass == &Hexagon::PredRegsRegClass) &&
724  "predicate register not found in a predicated MI instruction");
725 
726  // New-value register producer and user (store) need to satisfy these
727  // constraints:
728  // 1) Both instructions should be predicated on the same register.
729  // 2) If producer of the new-value register is .new predicated then store
730  // should also be .new predicated and if producer is not .new predicated
731  // then store should not be .new predicated.
732  // 3) Both new-value register producer and user should have same predicate
733  // sense, i.e, either both should be negated or both should be non-negated.
734  if (predRegNumDst != predRegNumSrc ||
735  HII->isDotNewInst(PacketMI) != HII->isDotNewInst(MI) ||
736  getPredicateSense(MI, HII) != getPredicateSense(PacketMI, HII))
737  return false;
738  }
739 
740  // Make sure that other than the new-value register no other store instruction
741  // register has been modified in the same packet. Predicate registers can be
742  // modified by they should not be modified between the producer and the store
743  // instruction as it will make them both conditional on different values.
744  // We already know this to be true for all the instructions before and
745  // including PacketMI. Howerver, we need to perform the check for the
746  // remaining instructions in the packet.
747 
748  unsigned StartCheck = 0;
749 
750  for (auto I : CurrentPacketMIs) {
751  SUnit *TempSU = MIToSUnit.find(I)->second;
752  MachineInstr &TempMI = *TempSU->getInstr();
753 
754  // Following condition is true for all the instructions until PacketMI is
755  // reached (StartCheck is set to 0 before the for loop).
756  // StartCheck flag is 1 for all the instructions after PacketMI.
757  if (&TempMI != &PacketMI && !StartCheck) // Start processing only after
758  continue; // encountering PacketMI.
759 
760  StartCheck = 1;
761  if (&TempMI == &PacketMI) // We don't want to check PacketMI for dependence.
762  continue;
763 
764  for (auto &MO : MI.operands())
765  if (MO.isReg() && TempSU->getInstr()->modifiesRegister(MO.getReg(), HRI))
766  return false;
767  }
768 
769  // Make sure that for non-POST_INC stores:
770  // 1. The only use of reg is DepReg and no other registers.
771  // This handles V4 base+index registers.
772  // The following store can not be dot new.
773  // Eg. r0 = add(r0, #3)
774  // memw(r1+r0<<#2) = r0
775  if (!HII->isPostIncrement(MI)) {
776  for (unsigned opNum = 0; opNum < MI.getNumOperands()-1; opNum++) {
777  const MachineOperand &MO = MI.getOperand(opNum);
778  if (MO.isReg() && MO.getReg() == DepReg)
779  return false;
780  }
781  }
782 
783  // If data definition is because of implicit definition of the register,
784  // do not newify the store. Eg.
785  // %r9 = ZXTH %r12, implicit %d6, implicit-def %r12
786  // S2_storerh_io %r8, 2, killed %r12; mem:ST2[%scevgep343]
787  for (auto &MO : PacketMI.operands()) {
788  if (MO.isRegMask() && MO.clobbersPhysReg(DepReg))
789  return false;
790  if (!MO.isReg() || !MO.isDef() || !MO.isImplicit())
791  continue;
792  unsigned R = MO.getReg();
793  if (R == DepReg || HRI->isSuperRegister(DepReg, R))
794  return false;
795  }
796 
797  // Handle imp-use of super reg case. There is a target independent side
798  // change that should prevent this situation but I am handling it for
799  // just-in-case. For example, we cannot newify R2 in the following case:
800  // %r3 = A2_tfrsi 0;
801  // S2_storeri_io killed %r0, 0, killed %r2, implicit killed %d1;
802  for (auto &MO : MI.operands()) {
803  if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == DepReg)
804  return false;
805  }
806 
807  // Can be dot new store.
808  return true;
809 }
810 
811 // Can this MI to promoted to either new value store or new value jump.
813  const SUnit *PacketSU, unsigned DepReg,
815  if (!HII->mayBeNewStore(MI))
816  return false;
817 
818  // Check to see the store can be new value'ed.
819  MachineInstr &PacketMI = *PacketSU->getInstr();
820  if (canPromoteToNewValueStore(MI, PacketMI, DepReg))
821  return true;
822 
823  // Check to see the compare/jump can be new value'ed.
824  // This is done as a pass on its own. Don't need to check it here.
825  return false;
826 }
827 
828 static bool isImplicitDependency(const MachineInstr &I, bool CheckDef,
829  unsigned DepReg) {
830  for (auto &MO : I.operands()) {
831  if (CheckDef && MO.isRegMask() && MO.clobbersPhysReg(DepReg))
832  return true;
833  if (!MO.isReg() || MO.getReg() != DepReg || !MO.isImplicit())
834  continue;
835  if (CheckDef == MO.isDef())
836  return true;
837  }
838  return false;
839 }
840 
841 // Check to see if an instruction can be dot new
842 // There are three kinds.
843 // 1. dot new on predicate - V2/V3/V4
844 // 2. dot new on stores NV/ST - V4
845 // 3. dot new on jump NV/J - V4 -- This is generated in a pass.
847  const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII,
848  const TargetRegisterClass* RC) {
849  // Already a dot new instruction.
850  if (HII->isDotNewInst(MI) && !HII->mayBeNewStore(MI))
851  return false;
852 
853  if (!isNewifiable(MI, RC))
854  return false;
855 
856  const MachineInstr &PI = *PacketSU->getInstr();
857 
858  // The "new value" cannot come from inline asm.
859  if (PI.isInlineAsm())
860  return false;
861 
862  // IMPLICIT_DEFs won't materialize as real instructions, so .new makes no
863  // sense.
864  if (PI.isImplicitDef())
865  return false;
866 
867  // If dependency is trough an implicitly defined register, we should not
868  // newify the use.
869  if (isImplicitDependency(PI, true, DepReg) ||
870  isImplicitDependency(MI, false, DepReg))
871  return false;
872 
873  const MCInstrDesc& MCID = PI.getDesc();
874  const TargetRegisterClass *VecRC = HII->getRegClass(MCID, 0, HRI, MF);
875  if (DisableVecDblNVStores && VecRC == &Hexagon::HvxWRRegClass)
876  return false;
877 
878  // predicate .new
879  if (RC == &Hexagon::PredRegsRegClass)
880  return HII->predCanBeUsedAsDotNew(PI, DepReg);
881 
882  if (RC != &Hexagon::PredRegsRegClass && !HII->mayBeNewStore(MI))
883  return false;
884 
885  // Create a dot new machine instruction to see if resources can be
886  // allocated. If not, bail out now.
887  int NewOpcode = HII->getDotNewOp(MI);
888  const MCInstrDesc &D = HII->get(NewOpcode);
889  MachineInstr *NewMI = MF.CreateMachineInstr(D, DebugLoc());
890  bool ResourcesAvailable = ResourceTracker->canReserveResources(*NewMI);
891  MF.DeleteMachineInstr(NewMI);
892  if (!ResourcesAvailable)
893  return false;
894 
895  // New Value Store only. New Value Jump generated as a separate pass.
896  if (!canPromoteToNewValue(MI, PacketSU, DepReg, MII))
897  return false;
898 
899  return true;
900 }
901 
902 // Go through the packet instructions and search for an anti dependency between
903 // them and DepReg from MI. Consider this case:
904 // Trying to add
905 // a) %r1 = TFRI_cdNotPt %p3, 2
906 // to this packet:
907 // {
908 // b) %p0 = C2_or killed %p3, killed %p0
909 // c) %p3 = C2_tfrrp %r23
910 // d) %r1 = C2_cmovenewit %p3, 4
911 // }
912 // The P3 from a) and d) will be complements after
913 // a)'s P3 is converted to .new form
914 // Anti-dep between c) and b) is irrelevant for this case
916  unsigned DepReg) {
917  SUnit *PacketSUDep = MIToSUnit.find(&MI)->second;
918 
919  for (auto I : CurrentPacketMIs) {
920  // We only care for dependencies to predicated instructions
921  if (!HII->isPredicated(*I))
922  continue;
923 
924  // Scheduling Unit for current insn in the packet
925  SUnit *PacketSU = MIToSUnit.find(I)->second;
926 
927  // Look at dependencies between current members of the packet and
928  // predicate defining instruction MI. Make sure that dependency is
929  // on the exact register we care about.
930  if (PacketSU->isSucc(PacketSUDep)) {
931  for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
932  auto &Dep = PacketSU->Succs[i];
933  if (Dep.getSUnit() == PacketSUDep && Dep.getKind() == SDep::Anti &&
934  Dep.getReg() == DepReg)
935  return true;
936  }
937  }
938  }
939 
940  return false;
941 }
942 
943 /// Gets the predicate register of a predicated instruction.
945  const HexagonInstrInfo *QII) {
946  /// We use the following rule: The first predicate register that is a use is
947  /// the predicate register of a predicated instruction.
948  assert(QII->isPredicated(MI) && "Must be predicated instruction");
949 
950  for (auto &Op : MI.operands()) {
951  if (Op.isReg() && Op.getReg() && Op.isUse() &&
952  Hexagon::PredRegsRegClass.contains(Op.getReg()))
953  return Op.getReg();
954  }
955 
956  llvm_unreachable("Unknown instruction operand layout");
957  return 0;
958 }
959 
960 // Given two predicated instructions, this function detects whether
961 // the predicates are complements.
963  MachineInstr &MI2) {
964  // If we don't know the predicate sense of the instructions bail out early, we
965  // need it later.
966  if (getPredicateSense(MI1, HII) == PK_Unknown ||
967  getPredicateSense(MI2, HII) == PK_Unknown)
968  return false;
969 
970  // Scheduling unit for candidate.
971  SUnit *SU = MIToSUnit[&MI1];
972 
973  // One corner case deals with the following scenario:
974  // Trying to add
975  // a) %r24 = A2_tfrt %p0, %r25
976  // to this packet:
977  // {
978  // b) %r25 = A2_tfrf %p0, %r24
979  // c) %p0 = C2_cmpeqi %r26, 1
980  // }
981  //
982  // On general check a) and b) are complements, but presence of c) will
983  // convert a) to .new form, and then it is not a complement.
984  // We attempt to detect it by analyzing existing dependencies in the packet.
985 
986  // Analyze relationships between all existing members of the packet.
987  // Look for Anti dependecy on the same predicate reg as used in the
988  // candidate.
989  for (auto I : CurrentPacketMIs) {
990  // Scheduling Unit for current insn in the packet.
991  SUnit *PacketSU = MIToSUnit.find(I)->second;
992 
993  // If this instruction in the packet is succeeded by the candidate...
994  if (PacketSU->isSucc(SU)) {
995  for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
996  auto Dep = PacketSU->Succs[i];
997  // The corner case exist when there is true data dependency between
998  // candidate and one of current packet members, this dep is on
999  // predicate reg, and there already exist anti dep on the same pred in
1000  // the packet.
1001  if (Dep.getSUnit() == SU && Dep.getKind() == SDep::Data &&
1002  Hexagon::PredRegsRegClass.contains(Dep.getReg())) {
1003  // Here I know that I is predicate setting instruction with true
1004  // data dep to candidate on the register we care about - c) in the
1005  // above example. Now I need to see if there is an anti dependency
1006  // from c) to any other instruction in the same packet on the pred
1007  // reg of interest.
1008  if (restrictingDepExistInPacket(*I, Dep.getReg()))
1009  return false;
1010  }
1011  }
1012  }
1013  }
1014 
1015  // If the above case does not apply, check regular complement condition.
1016  // Check that the predicate register is the same and that the predicate
1017  // sense is different We also need to differentiate .old vs. .new: !p0
1018  // is not complementary to p0.new.
1019  unsigned PReg1 = getPredicatedRegister(MI1, HII);
1020  unsigned PReg2 = getPredicatedRegister(MI2, HII);
1021  return PReg1 == PReg2 &&
1022  Hexagon::PredRegsRegClass.contains(PReg1) &&
1023  Hexagon::PredRegsRegClass.contains(PReg2) &&
1024  getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) &&
1025  HII->isDotNewInst(MI1) == HII->isDotNewInst(MI2);
1026 }
1027 
1028 // Initialize packetizer flags.
1030  Dependence = false;
1031  PromotedToDotNew = false;
1032  GlueToNewValueJump = false;
1033  GlueAllocframeStore = false;
1034  FoundSequentialDependence = false;
1035  ChangedOffset = INT64_MAX;
1036 }
1037 
1038 // Ignore bundling of pseudo instructions.
1040  const MachineBasicBlock *) {
1041  if (MI.isDebugInstr())
1042  return true;
1043 
1044  if (MI.isCFIInstruction())
1045  return false;
1046 
1047  // We must print out inline assembly.
1048  if (MI.isInlineAsm())
1049  return false;
1050 
1051  if (MI.isImplicitDef())
1052  return false;
1053 
1054  // We check if MI has any functional units mapped to it. If it doesn't,
1055  // we ignore the instruction.
1056  const MCInstrDesc& TID = MI.getDesc();
1057  auto *IS = ResourceTracker->getInstrItins()->beginStage(TID.getSchedClass());
1058  unsigned FuncUnits = IS->getUnits();
1059  return !FuncUnits;
1060 }
1061 
1063  // Ensure any bundles created by gather packetize remain seperate.
1064  if (MI.isBundle())
1065  return true;
1066 
1067  if (MI.isEHLabel() || MI.isCFIInstruction())
1068  return true;
1069 
1070  // Consider inline asm to not be a solo instruction by default.
1071  // Inline asm will be put in a packet temporarily, but then it will be
1072  // removed, and placed outside of the packet (before or after, depending
1073  // on dependencies). This is to reduce the impact of inline asm as a
1074  // "packet splitting" instruction.
1075  if (MI.isInlineAsm() && !ScheduleInlineAsm)
1076  return true;
1077 
1078  // From Hexagon V4 Programmer's Reference Manual 3.4.4 Grouping constraints:
1079  // trap, pause, barrier, icinva, isync, and syncht are solo instructions.
1080  // They must not be grouped with other instructions in a packet.
1081  if (isSchedBarrier(MI))
1082  return true;
1083 
1084  if (HII->isSolo(MI))
1085  return true;
1086 
1087  if (MI.getOpcode() == Hexagon::A2_nop)
1088  return true;
1089 
1090  return false;
1091 }
1092 
1093 // Quick check if instructions MI and MJ cannot coexist in the same packet.
1094 // Limit the tests to be "one-way", e.g. "if MI->isBranch and MJ->isInlineAsm",
1095 // but not the symmetric case: "if MJ->isBranch and MI->isInlineAsm".
1096 // For full test call this function twice:
1097 // cannotCoexistAsymm(MI, MJ) || cannotCoexistAsymm(MJ, MI)
1098 // Doing the test only one way saves the amount of code in this function,
1099 // since every test would need to be repeated with the MI and MJ reversed.
1100 static bool cannotCoexistAsymm(const MachineInstr &MI, const MachineInstr &MJ,
1101  const HexagonInstrInfo &HII) {
1102  const MachineFunction *MF = MI.getParent()->getParent();
1104  HII.isHVXMemWithAIndirect(MI, MJ))
1105  return true;
1106 
1107  // An inline asm cannot be together with a branch, because we may not be
1108  // able to remove the asm out after packetizing (i.e. if the asm must be
1109  // moved past the bundle). Similarly, two asms cannot be together to avoid
1110  // complications when determining their relative order outside of a bundle.
1111  if (MI.isInlineAsm())
1112  return MJ.isInlineAsm() || MJ.isBranch() || MJ.isBarrier() ||
1113  MJ.isCall() || MJ.isTerminator();
1114 
1115  // New-value stores cannot coexist with any other stores.
1116  if (HII.isNewValueStore(MI) && MJ.mayStore())
1117  return true;
1118 
1119  switch (MI.getOpcode()) {
1120  case Hexagon::S2_storew_locked:
1121  case Hexagon::S4_stored_locked:
1122  case Hexagon::L2_loadw_locked:
1123  case Hexagon::L4_loadd_locked:
1124  case Hexagon::Y2_dccleana:
1125  case Hexagon::Y2_dccleaninva:
1126  case Hexagon::Y2_dcinva:
1127  case Hexagon::Y2_dczeroa:
1128  case Hexagon::Y4_l2fetch:
1129  case Hexagon::Y5_l2fetch: {
1130  // These instructions can only be grouped with ALU32 or non-floating-point
1131  // XTYPE instructions. Since there is no convenient way of identifying fp
1132  // XTYPE instructions, only allow grouping with ALU32 for now.
1133  unsigned TJ = HII.getType(MJ);
1134  if (TJ != HexagonII::TypeALU32_2op &&
1135  TJ != HexagonII::TypeALU32_3op &&
1137  return true;
1138  break;
1139  }
1140  default:
1141  break;
1142  }
1143 
1144  // "False" really means that the quick check failed to determine if
1145  // I and J cannot coexist.
1146  return false;
1147 }
1148 
1149 // Full, symmetric check.
1151  const MachineInstr &MJ) {
1152  return cannotCoexistAsymm(MI, MJ, *HII) || cannotCoexistAsymm(MJ, MI, *HII);
1153 }
1154 
1156  for (auto &B : MF) {
1157  MachineBasicBlock::iterator BundleIt;
1159  for (auto I = B.instr_begin(), E = B.instr_end(); I != E; I = NextI) {
1160  NextI = std::next(I);
1161  MachineInstr &MI = *I;
1162  if (MI.isBundle())
1163  BundleIt = I;
1164  if (!MI.isInsideBundle())
1165  continue;
1166 
1167  // Decide on where to insert the instruction that we are pulling out.
1168  // Debug instructions always go before the bundle, but the placement of
1169  // INLINE_ASM depends on potential dependencies. By default, try to
1170  // put it before the bundle, but if the asm writes to a register that
1171  // other instructions in the bundle read, then we need to place it
1172  // after the bundle (to preserve the bundle semantics).
1173  bool InsertBeforeBundle;
1174  if (MI.isInlineAsm())
1175  InsertBeforeBundle = !hasWriteToReadDep(MI, *BundleIt, HRI);
1176  else if (MI.isDebugValue())
1177  InsertBeforeBundle = true;
1178  else
1179  continue;
1180 
1181  BundleIt = moveInstrOut(MI, BundleIt, InsertBeforeBundle);
1182  }
1183  }
1184 }
1185 
1186 // Check if a given instruction is of class "system".
1187 static bool isSystemInstr(const MachineInstr &MI) {
1188  unsigned Opc = MI.getOpcode();
1189  switch (Opc) {
1190  case Hexagon::Y2_barrier:
1191  case Hexagon::Y2_dcfetchbo:
1192  case Hexagon::Y4_l2fetch:
1193  case Hexagon::Y5_l2fetch:
1194  return true;
1195  }
1196  return false;
1197 }
1198 
1200  const MachineInstr &J) {
1201  // The dependence graph may not include edges between dead definitions,
1202  // so without extra checks, we could end up packetizing two instruction
1203  // defining the same (dead) register.
1204  if (I.isCall() || J.isCall())
1205  return false;
1206  if (HII->isPredicated(I) || HII->isPredicated(J))
1207  return false;
1208 
1209  BitVector DeadDefs(Hexagon::NUM_TARGET_REGS);
1210  for (auto &MO : I.operands()) {
1211  if (!MO.isReg() || !MO.isDef() || !MO.isDead())
1212  continue;
1213  DeadDefs[MO.getReg()] = true;
1214  }
1215 
1216  for (auto &MO : J.operands()) {
1217  if (!MO.isReg() || !MO.isDef() || !MO.isDead())
1218  continue;
1219  unsigned R = MO.getReg();
1220  if (R != Hexagon::USR_OVF && DeadDefs[R])
1221  return true;
1222  }
1223  return false;
1224 }
1225 
1227  const MachineInstr &J) {
1228  // A save callee-save register function call can only be in a packet
1229  // with instructions that don't write to the callee-save registers.
1230  if ((HII->isSaveCalleeSavedRegsCall(I) &&
1231  doesModifyCalleeSavedReg(J, HRI)) ||
1232  (HII->isSaveCalleeSavedRegsCall(J) &&
1233  doesModifyCalleeSavedReg(I, HRI)))
1234  return true;
1235 
1236  // Two control flow instructions cannot go in the same packet.
1237  if (isControlFlow(I) && isControlFlow(J))
1238  return true;
1239 
1240  // \ref-manual (7.3.4) A loop setup packet in loopN or spNloop0 cannot
1241  // contain a speculative indirect jump,
1242  // a new-value compare jump or a dealloc_return.
1243  auto isBadForLoopN = [this] (const MachineInstr &MI) -> bool {
1244  if (MI.isCall() || HII->isDeallocRet(MI) || HII->isNewValueJump(MI))
1245  return true;
1246  if (HII->isPredicated(MI) && HII->isPredicatedNew(MI) && HII->isJumpR(MI))
1247  return true;
1248  return false;
1249  };
1250 
1251  if (HII->isLoopN(I) && isBadForLoopN(J))
1252  return true;
1253  if (HII->isLoopN(J) && isBadForLoopN(I))
1254  return true;
1255 
1256  // dealloc_return cannot appear in the same packet as a conditional or
1257  // unconditional jump.
1258  return HII->isDeallocRet(I) &&
1259  (J.isBranch() || J.isCall() || J.isBarrier());
1260 }
1261 
1263  const MachineInstr &J) {
1264  // Adding I to a packet that has J.
1265 
1266  // Regmasks are not reflected in the scheduling dependency graph, so
1267  // we need to check them manually. This code assumes that regmasks only
1268  // occur on calls, and the problematic case is when we add an instruction
1269  // defining a register R to a packet that has a call that clobbers R via
1270  // a regmask. Those cannot be packetized together, because the call will
1271  // be executed last. That's also a reson why it is ok to add a call
1272  // clobbering R to a packet that defines R.
1273 
1274  // Look for regmasks in J.
1275  for (const MachineOperand &OpJ : J.operands()) {
1276  if (!OpJ.isRegMask())
1277  continue;
1278  assert((J.isCall() || HII->isTailCall(J)) && "Regmask on a non-call");
1279  for (const MachineOperand &OpI : I.operands()) {
1280  if (OpI.isReg()) {
1281  if (OpJ.clobbersPhysReg(OpI.getReg()))
1282  return true;
1283  } else if (OpI.isRegMask()) {
1284  // Both are regmasks. Assume that they intersect.
1285  return true;
1286  }
1287  }
1288  }
1289  return false;
1290 }
1291 
1293  const MachineInstr &J) {
1294  bool SysI = isSystemInstr(I), SysJ = isSystemInstr(J);
1295  bool StoreI = I.mayStore(), StoreJ = J.mayStore();
1296  if ((SysI && StoreJ) || (SysJ && StoreI))
1297  return true;
1298 
1299  if (StoreI && StoreJ) {
1300  if (HII->isNewValueInst(J) || HII->isMemOp(J) || HII->isMemOp(I))
1301  return true;
1302  } else {
1303  // A memop cannot be in the same packet with another memop or a store.
1304  // Two stores can be together, but here I and J cannot both be stores.
1305  bool MopStI = HII->isMemOp(I) || StoreI;
1306  bool MopStJ = HII->isMemOp(J) || StoreJ;
1307  if (MopStI && MopStJ)
1308  return true;
1309  }
1310 
1311  return (StoreJ && HII->isDeallocRet(I)) || (StoreI && HII->isDeallocRet(J));
1312 }
1313 
1314 // SUI is the current instruction that is out side of the current packet.
1315 // SUJ is the current instruction inside the current packet against which that
1316 // SUI will be packetized.
1318  assert(SUI->getInstr() && SUJ->getInstr());
1319  MachineInstr &I = *SUI->getInstr();
1320  MachineInstr &J = *SUJ->getInstr();
1321 
1322  // Clear IgnoreDepMIs when Packet starts.
1323  if (CurrentPacketMIs.size() == 1)
1324  IgnoreDepMIs.clear();
1325 
1326  MachineBasicBlock::iterator II = I.getIterator();
1327 
1328  // Solo instructions cannot go in the packet.
1329  assert(!isSoloInstruction(I) && "Unexpected solo instr!");
1330 
1331  if (cannotCoexist(I, J))
1332  return false;
1333 
1334  Dependence = hasDeadDependence(I, J) || hasControlDependence(I, J);
1335  if (Dependence)
1336  return false;
1337 
1338  // Regmasks are not accounted for in the scheduling graph, so we need
1339  // to explicitly check for dependencies caused by them. They should only
1340  // appear on calls, so it's not too pessimistic to reject all regmask
1341  // dependencies.
1342  Dependence = hasRegMaskDependence(I, J);
1343  if (Dependence)
1344  return false;
1345 
1346  // V4 allows dual stores. It does not allow second store, if the first
1347  // store is not in SLOT0. New value store, new value jump, dealloc_return
1348  // and memop always take SLOT0. Arch spec 3.4.4.2.
1349  Dependence = hasV4SpecificDependence(I, J);
1350  if (Dependence)
1351  return false;
1352 
1353  // If an instruction feeds new value jump, glue it.
1354  MachineBasicBlock::iterator NextMII = I.getIterator();
1355  ++NextMII;
1356  if (NextMII != I.getParent()->end() && HII->isNewValueJump(*NextMII)) {
1357  MachineInstr &NextMI = *NextMII;
1358 
1359  bool secondRegMatch = false;
1360  const MachineOperand &NOp0 = NextMI.getOperand(0);
1361  const MachineOperand &NOp1 = NextMI.getOperand(1);
1362 
1363  if (NOp1.isReg() && I.getOperand(0).getReg() == NOp1.getReg())
1364  secondRegMatch = true;
1365 
1366  for (MachineInstr *PI : CurrentPacketMIs) {
1367  // NVJ can not be part of the dual jump - Arch Spec: section 7.8.
1368  if (PI->isCall()) {
1369  Dependence = true;
1370  break;
1371  }
1372  // Validate:
1373  // 1. Packet does not have a store in it.
1374  // 2. If the first operand of the nvj is newified, and the second
1375  // operand is also a reg, it (second reg) is not defined in
1376  // the same packet.
1377  // 3. If the second operand of the nvj is newified, (which means
1378  // first operand is also a reg), first reg is not defined in
1379  // the same packet.
1380  if (PI->getOpcode() == Hexagon::S2_allocframe || PI->mayStore() ||
1381  HII->isLoopN(*PI)) {
1382  Dependence = true;
1383  break;
1384  }
1385  // Check #2/#3.
1386  const MachineOperand &OpR = secondRegMatch ? NOp0 : NOp1;
1387  if (OpR.isReg() && PI->modifiesRegister(OpR.getReg(), HRI)) {
1388  Dependence = true;
1389  break;
1390  }
1391  }
1392 
1393  GlueToNewValueJump = true;
1394  if (Dependence)
1395  return false;
1396  }
1397 
1398  // There no dependency between a prolog instruction and its successor.
1399  if (!SUJ->isSucc(SUI))
1400  return true;
1401 
1402  for (unsigned i = 0; i < SUJ->Succs.size(); ++i) {
1403  if (FoundSequentialDependence)
1404  break;
1405 
1406  if (SUJ->Succs[i].getSUnit() != SUI)
1407  continue;
1408 
1409  SDep::Kind DepType = SUJ->Succs[i].getKind();
1410  // For direct calls:
1411  // Ignore register dependences for call instructions for packetization
1412  // purposes except for those due to r31 and predicate registers.
1413  //
1414  // For indirect calls:
1415  // Same as direct calls + check for true dependences to the register
1416  // used in the indirect call.
1417  //
1418  // We completely ignore Order dependences for call instructions.
1419  //
1420  // For returns:
1421  // Ignore register dependences for return instructions like jumpr,
1422  // dealloc return unless we have dependencies on the explicit uses
1423  // of the registers used by jumpr (like r31) or dealloc return
1424  // (like r29 or r30).
1425  unsigned DepReg = 0;
1426  const TargetRegisterClass *RC = nullptr;
1427  if (DepType == SDep::Data) {
1428  DepReg = SUJ->Succs[i].getReg();
1429  RC = HRI->getMinimalPhysRegClass(DepReg);
1430  }
1431 
1432  if (I.isCall() || HII->isJumpR(I) || I.isReturn() || HII->isTailCall(I)) {
1433  if (!isRegDependence(DepType))
1434  continue;
1435  if (!isCallDependent(I, DepType, SUJ->Succs[i].getReg()))
1436  continue;
1437  }
1438 
1439  if (DepType == SDep::Data) {
1440  if (canPromoteToDotCur(J, SUJ, DepReg, II, RC))
1441  if (promoteToDotCur(J, DepType, II, RC))
1442  continue;
1443  }
1444 
1445  // Data dpendence ok if we have load.cur.
1446  if (DepType == SDep::Data && HII->isDotCurInst(J)) {
1447  if (HII->isHVXVec(I))
1448  continue;
1449  }
1450 
1451  // For instructions that can be promoted to dot-new, try to promote.
1452  if (DepType == SDep::Data) {
1453  if (canPromoteToDotNew(I, SUJ, DepReg, II, RC)) {
1454  if (promoteToDotNew(I, DepType, II, RC)) {
1455  PromotedToDotNew = true;
1456  if (cannotCoexist(I, J))
1457  FoundSequentialDependence = true;
1458  continue;
1459  }
1460  }
1461  if (HII->isNewValueJump(I))
1462  continue;
1463  }
1464 
1465  // For predicated instructions, if the predicates are complements then
1466  // there can be no dependence.
1467  if (HII->isPredicated(I) && HII->isPredicated(J) &&
1468  arePredicatesComplements(I, J)) {
1469  // Not always safe to do this translation.
1470  // DAG Builder attempts to reduce dependence edges using transitive
1471  // nature of dependencies. Here is an example:
1472  //
1473  // r0 = tfr_pt ... (1)
1474  // r0 = tfr_pf ... (2)
1475  // r0 = tfr_pt ... (3)
1476  //
1477  // There will be an output dependence between (1)->(2) and (2)->(3).
1478  // However, there is no dependence edge between (1)->(3). This results
1479  // in all 3 instructions going in the same packet. We ignore dependce
1480  // only once to avoid this situation.
1481  auto Itr = find(IgnoreDepMIs, &J);
1482  if (Itr != IgnoreDepMIs.end()) {
1483  Dependence = true;
1484  return false;
1485  }
1486  IgnoreDepMIs.push_back(&I);
1487  continue;
1488  }
1489 
1490  // Ignore Order dependences between unconditional direct branches
1491  // and non-control-flow instructions.
1492  if (isDirectJump(I) && !J.isBranch() && !J.isCall() &&
1493  DepType == SDep::Order)
1494  continue;
1495 
1496  // Ignore all dependences for jumps except for true and output
1497  // dependences.
1498  if (I.isConditionalBranch() && DepType != SDep::Data &&
1499  DepType != SDep::Output)
1500  continue;
1501 
1502  if (DepType == SDep::Output) {
1503  FoundSequentialDependence = true;
1504  break;
1505  }
1506 
1507  // For Order dependences:
1508  // 1. On V4 or later, volatile loads/stores can be packetized together,
1509  // unless other rules prevent is.
1510  // 2. Store followed by a load is not allowed.
1511  // 3. Store followed by a store is only valid on V4 or later.
1512  // 4. Load followed by any memory operation is allowed.
1513  if (DepType == SDep::Order) {
1514  if (!PacketizeVolatiles) {
1515  bool OrdRefs = I.hasOrderedMemoryRef() || J.hasOrderedMemoryRef();
1516  if (OrdRefs) {
1517  FoundSequentialDependence = true;
1518  break;
1519  }
1520  }
1521  // J is first, I is second.
1522  bool LoadJ = J.mayLoad(), StoreJ = J.mayStore();
1523  bool LoadI = I.mayLoad(), StoreI = I.mayStore();
1524  bool NVStoreJ = HII->isNewValueStore(J);
1525  bool NVStoreI = HII->isNewValueStore(I);
1526  bool IsVecJ = HII->isHVXVec(J);
1527  bool IsVecI = HII->isHVXVec(I);
1528 
1530  ((LoadJ && StoreI && !NVStoreI) ||
1531  (StoreJ && LoadI && !NVStoreJ)) &&
1532  (J.getOpcode() != Hexagon::S2_allocframe &&
1533  I.getOpcode() != Hexagon::S2_allocframe) &&
1534  (J.getOpcode() != Hexagon::L2_deallocframe &&
1535  I.getOpcode() != Hexagon::L2_deallocframe) &&
1536  (!HII->isMemOp(J) && !HII->isMemOp(I)) && (!IsVecJ && !IsVecI))
1537  setmemShufDisabled(true);
1538  else
1539  if (StoreJ && LoadI && alias(J, I)) {
1540  FoundSequentialDependence = true;
1541  break;
1542  }
1543 
1544  if (!StoreJ)
1545  if (!LoadJ || (!LoadI && !StoreI)) {
1546  // If J is neither load nor store, assume a dependency.
1547  // If J is a load, but I is neither, also assume a dependency.
1548  FoundSequentialDependence = true;
1549  break;
1550  }
1551  // Store followed by store: not OK on V2.
1552  // Store followed by load: not OK on all.
1553  // Load followed by store: OK on all.
1554  // Load followed by load: OK on all.
1555  continue;
1556  }
1557 
1558  // For V4, special case ALLOCFRAME. Even though there is dependency
1559  // between ALLOCFRAME and subsequent store, allow it to be packetized
1560  // in a same packet. This implies that the store is using the caller's
1561  // SP. Hence, offset needs to be updated accordingly.
1562  if (DepType == SDep::Data && J.getOpcode() == Hexagon::S2_allocframe) {
1563  unsigned Opc = I.getOpcode();
1564  switch (Opc) {
1565  case Hexagon::S2_storerd_io:
1566  case Hexagon::S2_storeri_io:
1567  case Hexagon::S2_storerh_io:
1568  case Hexagon::S2_storerb_io:
1569  if (I.getOperand(0).getReg() == HRI->getStackRegister()) {
1570  // Since this store is to be glued with allocframe in the same
1571  // packet, it will use SP of the previous stack frame, i.e.
1572  // caller's SP. Therefore, we need to recalculate offset
1573  // according to this change.
1574  GlueAllocframeStore = useCallersSP(I);
1575  if (GlueAllocframeStore)
1576  continue;
1577  }
1578  default:
1579  break;
1580  }
1581  }
1582 
1583  // There are certain anti-dependencies that cannot be ignored.
1584  // Specifically:
1585  // J2_call ... implicit-def %r0 ; SUJ
1586  // R0 = ... ; SUI
1587  // Those cannot be packetized together, since the call will observe
1588  // the effect of the assignment to R0.
1589  if ((DepType == SDep::Anti || DepType == SDep::Output) && J.isCall()) {
1590  // Check if I defines any volatile register. We should also check
1591  // registers that the call may read, but these happen to be a
1592  // subset of the volatile register set.
1593  for (const MachineOperand &Op : I.operands()) {
1594  if (Op.isReg() && Op.isDef()) {
1595  unsigned R = Op.getReg();
1596  if (!J.readsRegister(R, HRI) && !J.modifiesRegister(R, HRI))
1597  continue;
1598  } else if (!Op.isRegMask()) {
1599  // If I has a regmask assume dependency.
1600  continue;
1601  }
1602  FoundSequentialDependence = true;
1603  break;
1604  }
1605  }
1606 
1607  // Skip over remaining anti-dependences. Two instructions that are
1608  // anti-dependent can share a packet, since in most such cases all
1609  // operands are read before any modifications take place.
1610  // The exceptions are branch and call instructions, since they are
1611  // executed after all other instructions have completed (at least
1612  // conceptually).
1613  if (DepType != SDep::Anti) {
1614  FoundSequentialDependence = true;
1615  break;
1616  }
1617  }
1618 
1619  if (FoundSequentialDependence) {
1620  Dependence = true;
1621  return false;
1622  }
1623 
1624  return true;
1625 }
1626 
1628  assert(SUI->getInstr() && SUJ->getInstr());
1629  MachineInstr &I = *SUI->getInstr();
1630  MachineInstr &J = *SUJ->getInstr();
1631 
1632  bool Coexist = !cannotCoexist(I, J);
1633 
1634  if (Coexist && !Dependence)
1635  return true;
1636 
1637  // Check if the instruction was promoted to a dot-new. If so, demote it
1638  // back into a dot-old.
1639  if (PromotedToDotNew)
1640  demoteToDotOld(I);
1641 
1642  cleanUpDotCur();
1643  // Check if the instruction (must be a store) was glued with an allocframe
1644  // instruction. If so, restore its offset to its original value, i.e. use
1645  // current SP instead of caller's SP.
1646  if (GlueAllocframeStore) {
1647  useCalleesSP(I);
1648  GlueAllocframeStore = false;
1649  }
1650 
1651  if (ChangedOffset != INT64_MAX)
1652  undoChangedOffset(I);
1653 
1654  if (GlueToNewValueJump) {
1655  // Putting I and J together would prevent the new-value jump from being
1656  // packetized with the producer. In that case I and J must be separated.
1657  GlueToNewValueJump = false;
1658  return false;
1659  }
1660 
1661  if (!Coexist)
1662  return false;
1663 
1664  if (ChangedOffset == INT64_MAX && updateOffset(SUI, SUJ)) {
1665  FoundSequentialDependence = false;
1666  Dependence = false;
1667  return true;
1668  }
1669 
1670  return false;
1671 }
1672 
1673 
1675  bool FoundLoad = false;
1676  bool FoundStore = false;
1677 
1678  for (auto MJ : CurrentPacketMIs) {
1679  unsigned Opc = MJ->getOpcode();
1680  if (Opc == Hexagon::S2_allocframe || Opc == Hexagon::L2_deallocframe)
1681  continue;
1682  if (HII->isMemOp(*MJ))
1683  continue;
1684  if (MJ->mayLoad())
1685  FoundLoad = true;
1686  if (MJ->mayStore() && !HII->isNewValueStore(*MJ))
1687  FoundStore = true;
1688  }
1689  return FoundLoad && FoundStore;
1690 }
1691 
1692 
1696  MachineBasicBlock *MBB = MI.getParent();
1697 
1698  if (CurrentPacketMIs.empty())
1699  PacketStalls = false;
1700  PacketStalls |= producesStall(MI);
1701 
1702  if (MI.isImplicitDef()) {
1703  // Add to the packet to allow subsequent instructions to be checked
1704  // properly.
1705  CurrentPacketMIs.push_back(&MI);
1706  return MII;
1707  }
1708  assert(ResourceTracker->canReserveResources(MI));
1709 
1710  bool ExtMI = HII->isExtended(MI) || HII->isConstExtended(MI);
1711  bool Good = true;
1712 
1713  if (GlueToNewValueJump) {
1714  MachineInstr &NvjMI = *++MII;
1715  // We need to put both instructions in the same packet: MI and NvjMI.
1716  // Either of them can require a constant extender. Try to add both to
1717  // the current packet, and if that fails, end the packet and start a
1718  // new one.
1719  ResourceTracker->reserveResources(MI);
1720  if (ExtMI)
1721  Good = tryAllocateResourcesForConstExt(true);
1722 
1723  bool ExtNvjMI = HII->isExtended(NvjMI) || HII->isConstExtended(NvjMI);
1724  if (Good) {
1725  if (ResourceTracker->canReserveResources(NvjMI))
1726  ResourceTracker->reserveResources(NvjMI);
1727  else
1728  Good = false;
1729  }
1730  if (Good && ExtNvjMI)
1731  Good = tryAllocateResourcesForConstExt(true);
1732 
1733  if (!Good) {
1734  endPacket(MBB, MI);
1735  assert(ResourceTracker->canReserveResources(MI));
1736  ResourceTracker->reserveResources(MI);
1737  if (ExtMI) {
1738  assert(canReserveResourcesForConstExt());
1739  tryAllocateResourcesForConstExt(true);
1740  }
1741  assert(ResourceTracker->canReserveResources(NvjMI));
1742  ResourceTracker->reserveResources(NvjMI);
1743  if (ExtNvjMI) {
1744  assert(canReserveResourcesForConstExt());
1745  reserveResourcesForConstExt();
1746  }
1747  }
1748  CurrentPacketMIs.push_back(&MI);
1749  CurrentPacketMIs.push_back(&NvjMI);
1750  return MII;
1751  }
1752 
1753  ResourceTracker->reserveResources(MI);
1754  if (ExtMI && !tryAllocateResourcesForConstExt(true)) {
1755  endPacket(MBB, MI);
1756  if (PromotedToDotNew)
1757  demoteToDotOld(MI);
1758  if (GlueAllocframeStore) {
1759  useCalleesSP(MI);
1760  GlueAllocframeStore = false;
1761  }
1762  ResourceTracker->reserveResources(MI);
1763  reserveResourcesForConstExt();
1764  }
1765 
1766  CurrentPacketMIs.push_back(&MI);
1767  return MII;
1768 }
1769 
1772  // Replace VLIWPacketizerList::endPacket(MBB, EndMI).
1773 
1774  bool memShufDisabled = getmemShufDisabled();
1775  if (memShufDisabled && !foundLSInPacket()) {
1776  setmemShufDisabled(false);
1777  LLVM_DEBUG(dbgs() << " Not added to NoShufPacket\n");
1778  }
1779  memShufDisabled = getmemShufDisabled();
1780 
1781  OldPacketMIs.clear();
1782  for (MachineInstr *MI : CurrentPacketMIs) {
1783  MachineBasicBlock::instr_iterator NextMI = std::next(MI->getIterator());
1784  for (auto &I : make_range(HII->expandVGatherPseudo(*MI), NextMI))
1785  OldPacketMIs.push_back(&I);
1786  }
1787  CurrentPacketMIs.clear();
1788 
1789  if (OldPacketMIs.size() > 1) {
1790  MachineBasicBlock::instr_iterator FirstMI(OldPacketMIs.front());
1792  finalizeBundle(*MBB, FirstMI, LastMI);
1793  auto BundleMII = std::prev(FirstMI);
1794  if (memShufDisabled)
1795  HII->setBundleNoShuf(BundleMII);
1796 
1797  setmemShufDisabled(false);
1798  }
1799 
1800  ResourceTracker->clearResources();
1801  LLVM_DEBUG(dbgs() << "End packet\n");
1802 }
1803 
1805  if (Minimal)
1806  return false;
1807  return !producesStall(MI);
1808 }
1809 
1810 // V60 forward scheduling.
1812  // If the packet already stalls, then ignore the stall from a subsequent
1813  // instruction in the same packet.
1814  if (PacketStalls)
1815  return false;
1816 
1817  // Check whether the previous packet is in a different loop. If this is the
1818  // case, there is little point in trying to avoid a stall because that would
1819  // favor the rare case (loop entry) over the common case (loop iteration).
1820  //
1821  // TODO: We should really be able to check all the incoming edges if this is
1822  // the first packet in a basic block, so we can avoid stalls from the loop
1823  // backedge.
1824  if (!OldPacketMIs.empty()) {
1825  auto *OldBB = OldPacketMIs.front()->getParent();
1826  auto *ThisBB = I.getParent();
1827  if (MLI->getLoopFor(OldBB) != MLI->getLoopFor(ThisBB))
1828  return false;
1829  }
1830 
1831  SUnit *SUI = MIToSUnit[const_cast<MachineInstr *>(&I)];
1832 
1833  // If the latency is 0 and there is a data dependence between this
1834  // instruction and any instruction in the current packet, we disregard any
1835  // potential stalls due to the instructions in the previous packet. Most of
1836  // the instruction pairs that can go together in the same packet have 0
1837  // latency between them. The exceptions are
1838  // 1. NewValueJumps as they're generated much later and the latencies can't
1839  // be changed at that point.
1840  // 2. .cur instructions, if its consumer has a 0 latency successor (such as
1841  // .new). In this case, the latency between .cur and the consumer stays
1842  // non-zero even though we can have both .cur and .new in the same packet.
1843  // Changing the latency to 0 is not an option as it causes software pipeliner
1844  // to not pipeline in some cases.
1845 
1846  // For Example:
1847  // {
1848  // I1: v6.cur = vmem(r0++#1)
1849  // I2: v7 = valign(v6,v4,r2)
1850  // I3: vmem(r5++#1) = v7.new
1851  // }
1852  // Here I2 and I3 has 0 cycle latency, but I1 and I2 has 2.
1853 
1854  for (auto J : CurrentPacketMIs) {
1855  SUnit *SUJ = MIToSUnit[J];
1856  for (auto &Pred : SUI->Preds)
1857  if (Pred.getSUnit() == SUJ)
1858  if ((Pred.getLatency() == 0 && Pred.isAssignedRegDep()) ||
1859  HII->isNewValueJump(I) || HII->isToBeScheduledASAP(*J, I))
1860  return false;
1861  }
1862 
1863  // Check if the latency is greater than one between this instruction and any
1864  // instruction in the previous packet.
1865  for (auto J : OldPacketMIs) {
1866  SUnit *SUJ = MIToSUnit[J];
1867  for (auto &Pred : SUI->Preds)
1868  if (Pred.getSUnit() == SUJ && Pred.getLatency() > 1)
1869  return true;
1870  }
1871 
1872  return false;
1873 }
1874 
1875 //===----------------------------------------------------------------------===//
1876 // Public Constructor Functions
1877 //===----------------------------------------------------------------------===//
1878 
1880  return new HexagonPacketizer(Minimal);
1881 }
bool canPromoteToNewValueStore(const MachineInstr &MI, const MachineInstr &PacketMI, unsigned DepReg)
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
static bool hasWriteToReadDep(const MachineInstr &FirstI, const MachineInstr &SecondI, const TargetRegisterInfo *TRI)
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:633
instr_iterator instr_end()
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool canPromoteToDotNew(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
static bool cannotCoexistAsymm(const MachineInstr &MI, const MachineInstr &MJ, const HexagonInstrInfo &HII)
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
bool isCFIInstruction() const
Definition: MachineInstr.h:990
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:362
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
static bool isImplicitDependency(const MachineInstr &I, bool CheckDef, unsigned DepReg)
unsigned Reg
bool isInlineAsm() const
bool demoteToDotOld(MachineInstr &MI)
static cl::opt< bool > PacketizeVolatiles("hexagon-packetize-volatiles", cl::ZeroOrMore, cl::Hidden, cl::init(true), cl::desc("Allow non-solo packetization of volatile memory references"))
void undoChangedOffset(MachineInstr &MI)
Undo the changed offset.
static cl::opt< bool > DisablePacketizer("disable-packetizer", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon packetizer pass"))
INITIALIZE_PASS_BEGIN(HexagonPacketizer, "hexagon-packetizer", "Hexagon Packetizer", false, false) INITIALIZE_PASS_END(HexagonPacketizer
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
Kind
These are the different kinds of scheduling dependencies.
Definition: ScheduleDAG.h:53
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:459
MachineInstr * CreateMachineInstr(const MCInstrDesc &MCID, const DebugLoc &DL, bool NoImp=false)
CreateMachineInstr - Allocate a new MachineInstr.
#define HEXAGON_LRFP_SIZE
SmallVector< SDep, 4 > Preds
All sunit predecessors.
Definition: ScheduleDAG.h:260
A register anti-dependence (aka WAR).
Definition: ScheduleDAG.h:55
bool restrictingDepExistInPacket(MachineInstr &, unsigned)
bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:51
static cl::opt< bool > EnableGenAllInsnClass("enable-gen-insn", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Generate all instruction with TC"))
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:412
cl::opt< bool > Slot1Store("slot1-store-slot0-load", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Allow slot1 store and slot0 load"))
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:366
bool shouldAddToPacket(const MachineInstr &MI) override
Regular data dependence (aka true-dependence).
Definition: ScheduleDAG.h:54
#define INT64_MAX
Definition: DataTypes.h:77
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:649
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:409
void endPacket(MachineBasicBlock *MBB, MachineBasicBlock::iterator MI) override
bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2)
static bool doesModifyCalleeSavedReg(const MachineInstr &MI, const TargetRegisterInfo *TRI)
Returns true if the instruction modifies a callee-saved register.
void unbundleFromPred()
Break bundle above this instruction.
A register output-dependence (aka WAW).
Definition: ScheduleDAG.h:56
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:406
static bool isControlFlow(const MachineInstr &MI)
bool isBundle() const
void initializeHexagonPacketizerPass(PassRegistry &)
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
Definition: MachineInstr.h:350
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
hexagon Hexagon Packetizer
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:657
static MachineBasicBlock::iterator moveInstrOut(MachineInstr &MI, MachineBasicBlock::iterator BundleIt, bool Before)
static unsigned getPredicatedRegister(MachineInstr &MI, const HexagonInstrInfo *QII)
Gets the predicate register of a predicated instruction.
static const MachineOperand & getAbsSetOperand(const MachineInstr &MI)
bool isSoloInstruction(const MachineInstr &MI) override
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:571
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:820
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:410
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
Definition: ScheduleDAG.h:377
static bool isSystemInstr(const MachineInstr &MI)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
std::pair< iterator, bool > insert(const ValueT &V)
Definition: DenseSet.h:187
Represent the analysis usage information of a pass.
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:311
bool isEHLabel() const
Definition: MachineInstr.h:979
void setImm(int64_t immVal)
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
self_iterator getIterator()
Definition: ilist_node.h:82
static bool isRegDependence(const SDep::Kind DepType)
bool tryAllocateResourcesForConstExt(bool Reserve)
void DeleteMachineInstr(MachineInstr *MI)
DeleteMachineInstr - Delete the given MachineInstr.
bool isImplicitDef() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Any other ordering dependency.
Definition: ScheduleDAG.h:57
auto find(R &&Range, const T &Val) -> decltype(adl_begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1063
bool isPostIncrement(const MachineInstr &MI) const override
Return true for post-incremented instructions.
bool isDebugInstr() const
Definition: MachineInstr.h:999
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
static const MachineOperand & getPostIncrementOperand(const MachineInstr &MI, const HexagonInstrInfo *HII)
Iterator for intrusive lists based on ilist_node.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
bool isNewValueStore(const MachineInstr &MI) const
bool isDebugValue() const
Definition: MachineInstr.h:997
MachineOperand class - Representation of each machine instruction operand.
uint64_t getType(const MachineInstr &MI) const
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
static cl::opt< bool > DisableVecDblNVStores("disable-vecdbl-nv-stores", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Disable vector double new-value-stores"))
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:286
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
bool mayStore() const
Return true if this instruction could possibly modify memory.
Definition: MCInstrDesc.h:399
static const MachineOperand & getStoreValueOperand(const MachineInstr &MI)
static bool isLoadAbsSet(const MachineInstr &MI)
static PredicateKind getPredicateSense(const MachineInstr &MI, const HexagonInstrInfo *HII)
Returns true if an instruction is predicated on p0 and false if it&#39;s predicated on !p0...
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:254
MachineFunctionProperties & set(Property P)
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
static bool isSchedBarrier(const MachineInstr &MI)
bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType, unsigned DepReg)
bool ignorePseudoInstruction(const MachineInstr &MI, const MachineBasicBlock *MBB) override
bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC)
bool updateOffset(SUnit *SUI, SUnit *SUJ)
Return true if we can update the offset in MI so that MI and MJ can be packetized together...
cl::opt< bool > ScheduleInlineAsm
#define I(x, y, z)
Definition: MD5.cpp:58
bool isCall() const
Return true if the instruction is a call.
Definition: MCInstrDesc.h:257
bool isPredicatedTrue(const MachineInstr &MI) const
uint32_t Size
Definition: Profile.cpp:47
bool hasControlDependence(const MachineInstr &I, const MachineInstr &J)
bool useCallersSP(MachineInstr &MI)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
hexagon packetizer
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:807
bool promoteToDotNew(MachineInstr &MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool hasDeadDependence(const MachineInstr &I, const MachineInstr &J)
bool isHVXMemWithAIndirect(const MachineInstr &I, const MachineInstr &J) const
bool isTerminator() const
Returns true if this instruction part of the terminator for a basic block.
Definition: MCInstrDesc.h:270
aarch64 promote const
bool cannotCoexist(const MachineInstr &MI, const MachineInstr &MJ)
bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override
FunctionPass * createHexagonPacketizer(bool Minimal)
const HexagonInstrInfo * getInstrInfo() const override
SmallVector< SDep, 4 > Succs
All sunit successors.
Definition: ScheduleDAG.h:261
void useCalleesSP(MachineInstr &MI)
bool hasRegMaskDependence(const MachineInstr &I, const MachineInstr &J)
IRTranslator LLVM IR MI
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:640
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:39
void unpacketizeSoloInstrs(MachineFunction &MF)
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object...
Dependence - This class represents a dependence between two memory memory references in a function...
#define LLVM_DEBUG(X)
Definition: Debug.h:123
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
void finalizeBundle(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
finalizeBundle - Finalize a machine instruction bundle which includes a sequence of instructions star...
bool canPromoteToNewValue(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII)
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
bool isSucc(const SUnit *N) const
Tests if node N is a successor of this node.
Definition: ScheduleDAG.h:443
#define OP(n)
Definition: regex2.h:73
static bool isDirectJump(const MachineInstr &MI)
bool producesStall(const MachineInstr &MI)
Properties which a MachineFunction may have at a given point in time.
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:246
bool hasV4SpecificDependence(const MachineInstr &I, const MachineInstr &J)