LLVM  10.0.0svn
HexagonVLIWPacketizer.cpp
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1 //===- HexagonPacketizer.cpp - VLIW packetizer ----------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements a simple VLIW packetizer using DFA. The packetizer works on
10 // machine basic blocks. For each instruction I in BB, the packetizer consults
11 // the DFA to see if machine resources are available to execute I. If so, the
12 // packetizer checks if I depends on any instruction J in the current packet.
13 // If no dependency is found, I is added to current packet and machine resource
14 // is marked as taken. If any dependency is found, a target API call is made to
15 // prune the dependence.
16 //
17 //===----------------------------------------------------------------------===//
18 
19 #include "HexagonVLIWPacketizer.h"
20 #include "Hexagon.h"
21 #include "HexagonInstrInfo.h"
22 #include "HexagonRegisterInfo.h"
23 #include "HexagonSubtarget.h"
24 #include "llvm/ADT/BitVector.h"
25 #include "llvm/ADT/DenseSet.h"
26 #include "llvm/ADT/STLExtras.h"
41 #include "llvm/IR/DebugLoc.h"
42 #include "llvm/MC/MCInstrDesc.h"
43 #include "llvm/Pass.h"
45 #include "llvm/Support/Debug.h"
48 #include <cassert>
49 #include <cstdint>
50 #include <iterator>
51 
52 using namespace llvm;
53 
54 #define DEBUG_TYPE "packets"
55 
56 static cl::opt<bool> DisablePacketizer("disable-packetizer", cl::Hidden,
57  cl::ZeroOrMore, cl::init(false),
58  cl::desc("Disable Hexagon packetizer pass"));
59 
60 cl::opt<bool> Slot1Store("slot1-store-slot0-load", cl::Hidden,
61  cl::ZeroOrMore, cl::init(true),
62  cl::desc("Allow slot1 store and slot0 load"));
63 
64 static cl::opt<bool> PacketizeVolatiles("hexagon-packetize-volatiles",
66  cl::desc("Allow non-solo packetization of volatile memory references"));
67 
68 static cl::opt<bool> EnableGenAllInsnClass("enable-gen-insn", cl::init(false),
69  cl::Hidden, cl::ZeroOrMore, cl::desc("Generate all instruction with TC"));
70 
71 static cl::opt<bool> DisableVecDblNVStores("disable-vecdbl-nv-stores",
73  cl::desc("Disable vector double new-value-stores"));
74 
76 
77 namespace llvm {
78 
81 
82 } // end namespace llvm
83 
84 namespace {
85 
86  class HexagonPacketizer : public MachineFunctionPass {
87  public:
88  static char ID;
89 
90  HexagonPacketizer(bool Min = false)
91  : MachineFunctionPass(ID), Minimal(Min) {}
92 
93  void getAnalysisUsage(AnalysisUsage &AU) const override {
94  AU.setPreservesCFG();
102  }
103 
104  StringRef getPassName() const override { return "Hexagon Packetizer"; }
105  bool runOnMachineFunction(MachineFunction &Fn) override;
106 
107  MachineFunctionProperties getRequiredProperties() const override {
110  }
111 
112  private:
113  const HexagonInstrInfo *HII;
114  const HexagonRegisterInfo *HRI;
115  const bool Minimal;
116  };
117 
118 } // end anonymous namespace
119 
120 char HexagonPacketizer::ID = 0;
121 
122 INITIALIZE_PASS_BEGIN(HexagonPacketizer, "hexagon-packetizer",
123  "Hexagon Packetizer", false, false)
128 INITIALIZE_PASS_END(HexagonPacketizer, "hexagon-packetizer",
129  "Hexagon Packetizer", false, false)
130 
132  MachineLoopInfo &MLI, AliasAnalysis *AA,
133  const MachineBranchProbabilityInfo *MBPI, bool Minimal)
134  : VLIWPacketizerList(MF, MLI, AA), MBPI(MBPI), MLI(&MLI),
135  Minimal(Minimal) {
136  HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
137  HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
138 
139  addMutation(std::make_unique<HexagonSubtarget::UsrOverflowMutation>());
140  addMutation(std::make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
141  addMutation(std::make_unique<HexagonSubtarget::BankConflictMutation>());
142 }
143 
144 // Check if FirstI modifies a register that SecondI reads.
145 static bool hasWriteToReadDep(const MachineInstr &FirstI,
146  const MachineInstr &SecondI,
147  const TargetRegisterInfo *TRI) {
148  for (auto &MO : FirstI.operands()) {
149  if (!MO.isReg() || !MO.isDef())
150  continue;
151  Register R = MO.getReg();
152  if (SecondI.readsRegister(R, TRI))
153  return true;
154  }
155  return false;
156 }
157 
158 
160  MachineBasicBlock::iterator BundleIt, bool Before) {
162  if (Before)
163  InsertPt = BundleIt.getInstrIterator();
164  else
165  InsertPt = std::next(BundleIt).getInstrIterator();
166 
167  MachineBasicBlock &B = *MI.getParent();
168  // The instruction should at least be bundled with the preceding instruction
169  // (there will always be one, i.e. BUNDLE, if nothing else).
171  if (MI.isBundledWithSucc()) {
174  } else {
175  // If it's not bundled with the successor (i.e. it is the last one
176  // in the bundle), then we can simply unbundle it from the predecessor,
177  // which will take care of updating the predecessor's flag.
178  MI.unbundleFromPred();
179  }
180  B.splice(InsertPt, &B, MI.getIterator());
181 
182  // Get the size of the bundle without asserting.
185  unsigned Size = 0;
186  for (++I; I != E && I->isBundledWithPred(); ++I)
187  ++Size;
188 
189  // If there are still two or more instructions, then there is nothing
190  // else to be done.
191  if (Size > 1)
192  return BundleIt;
193 
194  // Otherwise, extract the single instruction out and delete the bundle.
195  MachineBasicBlock::iterator NextIt = std::next(BundleIt);
196  MachineInstr &SingleI = *BundleIt->getNextNode();
197  SingleI.unbundleFromPred();
198  assert(!SingleI.isBundledWithSucc());
199  BundleIt->eraseFromParent();
200  return NextIt;
201 }
202 
203 bool HexagonPacketizer::runOnMachineFunction(MachineFunction &MF) {
204  auto &HST = MF.getSubtarget<HexagonSubtarget>();
205  HII = HST.getInstrInfo();
206  HRI = HST.getRegisterInfo();
207  auto &MLI = getAnalysis<MachineLoopInfo>();
208  auto *AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
209  auto *MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
210 
212  HII->genAllInsnTimingClasses(MF);
213 
214  // Instantiate the packetizer.
215  bool MinOnly = Minimal || DisablePacketizer || !HST.usePackets() ||
216  skipFunction(MF.getFunction());
217  HexagonPacketizerList Packetizer(MF, MLI, AA, MBPI, MinOnly);
218 
219  // DFA state table should not be empty.
220  assert(Packetizer.getResourceTracker() && "Empty DFA table!");
221 
222  // Loop over all basic blocks and remove KILL pseudo-instructions
223  // These instructions confuse the dependence analysis. Consider:
224  // D0 = ... (Insn 0)
225  // R0 = KILL R0, D0 (Insn 1)
226  // R0 = ... (Insn 2)
227  // Here, Insn 1 will result in the dependence graph not emitting an output
228  // dependence between Insn 0 and Insn 2. This can lead to incorrect
229  // packetization
230  for (MachineBasicBlock &MB : MF) {
231  auto End = MB.end();
232  auto MI = MB.begin();
233  while (MI != End) {
234  auto NextI = std::next(MI);
235  if (MI->isKill()) {
236  MB.erase(MI);
237  End = MB.end();
238  }
239  MI = NextI;
240  }
241  }
242 
243  // Loop over all of the basic blocks.
244  for (auto &MB : MF) {
245  auto Begin = MB.begin(), End = MB.end();
246  while (Begin != End) {
247  // Find the first non-boundary starting from the end of the last
248  // scheduling region.
249  MachineBasicBlock::iterator RB = Begin;
250  while (RB != End && HII->isSchedulingBoundary(*RB, &MB, MF))
251  ++RB;
252  // Find the first boundary starting from the beginning of the new
253  // region.
255  while (RE != End && !HII->isSchedulingBoundary(*RE, &MB, MF))
256  ++RE;
257  // Add the scheduling boundary if it's not block end.
258  if (RE != End)
259  ++RE;
260  // If RB == End, then RE == End.
261  if (RB != End)
262  Packetizer.PacketizeMIs(&MB, RB, RE);
263 
264  Begin = RE;
265  }
266  }
267 
268  Packetizer.unpacketizeSoloInstrs(MF);
269  return true;
270 }
271 
272 // Reserve resources for a constant extender. Trigger an assertion if the
273 // reservation fails.
275  if (!tryAllocateResourcesForConstExt(true))
276  llvm_unreachable("Resources not available");
277 }
278 
280  return tryAllocateResourcesForConstExt(false);
281 }
282 
283 // Allocate resources (i.e. 4 bytes) for constant extender. If succeeded,
284 // return true, otherwise, return false.
286  auto *ExtMI = MF.CreateMachineInstr(HII->get(Hexagon::A4_ext), DebugLoc());
287  bool Avail = ResourceTracker->canReserveResources(*ExtMI);
288  if (Reserve && Avail)
289  ResourceTracker->reserveResources(*ExtMI);
290  MF.DeleteMachineInstr(ExtMI);
291  return Avail;
292 }
293 
295  SDep::Kind DepType, unsigned DepReg) {
296  // Check for LR dependence.
297  if (DepReg == HRI->getRARegister())
298  return true;
299 
300  if (HII->isDeallocRet(MI))
301  if (DepReg == HRI->getFrameRegister() || DepReg == HRI->getStackRegister())
302  return true;
303 
304  // Call-like instructions can be packetized with preceding instructions
305  // that define registers implicitly used or modified by the call. Explicit
306  // uses are still prohibited, as in the case of indirect calls:
307  // r0 = ...
308  // J2_jumpr r0
309  if (DepType == SDep::Data) {
310  for (const MachineOperand MO : MI.operands())
311  if (MO.isReg() && MO.getReg() == DepReg && !MO.isImplicit())
312  return true;
313  }
314 
315  return false;
316 }
317 
318 static bool isRegDependence(const SDep::Kind DepType) {
319  return DepType == SDep::Data || DepType == SDep::Anti ||
320  DepType == SDep::Output;
321 }
322 
323 static bool isDirectJump(const MachineInstr &MI) {
324  return MI.getOpcode() == Hexagon::J2_jump;
325 }
326 
327 static bool isSchedBarrier(const MachineInstr &MI) {
328  switch (MI.getOpcode()) {
329  case Hexagon::Y2_barrier:
330  return true;
331  }
332  return false;
333 }
334 
335 static bool isControlFlow(const MachineInstr &MI) {
336  return MI.getDesc().isTerminator() || MI.getDesc().isCall();
337 }
338 
339 /// Returns true if the instruction modifies a callee-saved register.
341  const TargetRegisterInfo *TRI) {
342  const MachineFunction &MF = *MI.getParent()->getParent();
343  for (auto *CSR = TRI->getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR)
344  if (MI.modifiesRegister(*CSR, TRI))
345  return true;
346  return false;
347 }
348 
349 // Returns true if an instruction can be promoted to .new predicate or
350 // new-value store.
352  const TargetRegisterClass *NewRC) {
353  // Vector stores can be predicated, and can be new-value stores, but
354  // they cannot be predicated on a .new predicate value.
355  if (NewRC == &Hexagon::PredRegsRegClass) {
356  if (HII->isHVXVec(MI) && MI.mayStore())
357  return false;
358  return HII->isPredicated(MI) && HII->getDotNewPredOp(MI, nullptr) > 0;
359  }
360  // If the class is not PredRegs, it could only apply to new-value stores.
361  return HII->mayBeNewStore(MI);
362 }
363 
364 // Promote an instructiont to its .cur form.
365 // At this time, we have already made a call to canPromoteToDotCur and made
366 // sure that it can *indeed* be promoted.
369  const TargetRegisterClass* RC) {
370  assert(DepType == SDep::Data);
371  int CurOpcode = HII->getDotCurOp(MI);
372  MI.setDesc(HII->get(CurOpcode));
373  return true;
374 }
375 
377  MachineInstr *MI = nullptr;
378  for (auto BI : CurrentPacketMIs) {
379  LLVM_DEBUG(dbgs() << "Cleanup packet has "; BI->dump(););
380  if (HII->isDotCurInst(*BI)) {
381  MI = BI;
382  continue;
383  }
384  if (MI) {
385  for (auto &MO : BI->operands())
386  if (MO.isReg() && MO.getReg() == MI->getOperand(0).getReg())
387  return;
388  }
389  }
390  if (!MI)
391  return;
392  // We did not find a use of the CUR, so de-cur it.
393  MI->setDesc(HII->get(HII->getNonDotCurOp(*MI)));
394  LLVM_DEBUG(dbgs() << "Demoted CUR "; MI->dump(););
395 }
396 
397 // Check to see if an instruction can be dot cur.
399  const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII,
400  const TargetRegisterClass *RC) {
401  if (!HII->isHVXVec(MI))
402  return false;
403  if (!HII->isHVXVec(*MII))
404  return false;
405 
406  // Already a dot new instruction.
407  if (HII->isDotCurInst(MI) && !HII->mayBeCurLoad(MI))
408  return false;
409 
410  if (!HII->mayBeCurLoad(MI))
411  return false;
412 
413  // The "cur value" cannot come from inline asm.
414  if (PacketSU->getInstr()->isInlineAsm())
415  return false;
416 
417  // Make sure candidate instruction uses cur.
418  LLVM_DEBUG(dbgs() << "Can we DOT Cur Vector MI\n"; MI.dump();
419  dbgs() << "in packet\n";);
420  MachineInstr &MJ = *MII;
421  LLVM_DEBUG({
422  dbgs() << "Checking CUR against ";
423  MJ.dump();
424  });
425  Register DestReg = MI.getOperand(0).getReg();
426  bool FoundMatch = false;
427  for (auto &MO : MJ.operands())
428  if (MO.isReg() && MO.getReg() == DestReg)
429  FoundMatch = true;
430  if (!FoundMatch)
431  return false;
432 
433  // Check for existing uses of a vector register within the packet which
434  // would be affected by converting a vector load into .cur formt.
435  for (auto BI : CurrentPacketMIs) {
436  LLVM_DEBUG(dbgs() << "packet has "; BI->dump(););
437  if (BI->readsRegister(DepReg, MF.getSubtarget().getRegisterInfo()))
438  return false;
439  }
440 
441  LLVM_DEBUG(dbgs() << "Can Dot CUR MI\n"; MI.dump(););
442  // We can convert the opcode into a .cur.
443  return true;
444 }
445 
446 // Promote an instruction to its .new form. At this time, we have already
447 // made a call to canPromoteToDotNew and made sure that it can *indeed* be
448 // promoted.
451  const TargetRegisterClass* RC) {
452  assert(DepType == SDep::Data);
453  int NewOpcode;
454  if (RC == &Hexagon::PredRegsRegClass)
455  NewOpcode = HII->getDotNewPredOp(MI, MBPI);
456  else
457  NewOpcode = HII->getDotNewOp(MI);
458  MI.setDesc(HII->get(NewOpcode));
459  return true;
460 }
461 
463  int NewOpcode = HII->getDotOldOp(MI);
464  MI.setDesc(HII->get(NewOpcode));
465  return true;
466 }
467 
469  unsigned Opc = MI.getOpcode();
470  switch (Opc) {
471  case Hexagon::S2_storerd_io:
472  case Hexagon::S2_storeri_io:
473  case Hexagon::S2_storerh_io:
474  case Hexagon::S2_storerb_io:
475  break;
476  default:
477  llvm_unreachable("Unexpected instruction");
478  }
479  unsigned FrameSize = MF.getFrameInfo().getStackSize();
480  MachineOperand &Off = MI.getOperand(1);
481  int64_t NewOff = Off.getImm() - (FrameSize + HEXAGON_LRFP_SIZE);
482  if (HII->isValidOffset(Opc, NewOff, HRI)) {
483  Off.setImm(NewOff);
484  return true;
485  }
486  return false;
487 }
488 
490  unsigned Opc = MI.getOpcode();
491  switch (Opc) {
492  case Hexagon::S2_storerd_io:
493  case Hexagon::S2_storeri_io:
494  case Hexagon::S2_storerh_io:
495  case Hexagon::S2_storerb_io:
496  break;
497  default:
498  llvm_unreachable("Unexpected instruction");
499  }
500  unsigned FrameSize = MF.getFrameInfo().getStackSize();
501  MachineOperand &Off = MI.getOperand(1);
502  Off.setImm(Off.getImm() + FrameSize + HEXAGON_LRFP_SIZE);
503 }
504 
505 /// Return true if we can update the offset in MI so that MI and MJ
506 /// can be packetized together.
508  assert(SUI->getInstr() && SUJ->getInstr());
509  MachineInstr &MI = *SUI->getInstr();
510  MachineInstr &MJ = *SUJ->getInstr();
511 
512  unsigned BPI, OPI;
513  if (!HII->getBaseAndOffsetPosition(MI, BPI, OPI))
514  return false;
515  unsigned BPJ, OPJ;
516  if (!HII->getBaseAndOffsetPosition(MJ, BPJ, OPJ))
517  return false;
518  Register Reg = MI.getOperand(BPI).getReg();
519  if (Reg != MJ.getOperand(BPJ).getReg())
520  return false;
521  // Make sure that the dependences do not restrict adding MI to the packet.
522  // That is, ignore anti dependences, and make sure the only data dependence
523  // involves the specific register.
524  for (const auto &PI : SUI->Preds)
525  if (PI.getKind() != SDep::Anti &&
526  (PI.getKind() != SDep::Data || PI.getReg() != Reg))
527  return false;
528  int Incr;
529  if (!HII->getIncrementValue(MJ, Incr))
530  return false;
531 
532  int64_t Offset = MI.getOperand(OPI).getImm();
533  if (!HII->isValidOffset(MI.getOpcode(), Offset+Incr, HRI))
534  return false;
535 
536  MI.getOperand(OPI).setImm(Offset + Incr);
537  ChangedOffset = Offset;
538  return true;
539 }
540 
541 /// Undo the changed offset. This is needed if the instruction cannot be
542 /// added to the current packet due to a different instruction.
544  unsigned BP, OP;
545  if (!HII->getBaseAndOffsetPosition(MI, BP, OP))
546  llvm_unreachable("Unable to find base and offset operands.");
547  MI.getOperand(OP).setImm(ChangedOffset);
548 }
549 
554 };
555 
556 /// Returns true if an instruction is predicated on p0 and false if it's
557 /// predicated on !p0.
559  const HexagonInstrInfo *HII) {
560  if (!HII->isPredicated(MI))
561  return PK_Unknown;
562  if (HII->isPredicatedTrue(MI))
563  return PK_True;
564  return PK_False;
565 }
566 
568  const HexagonInstrInfo *HII) {
569  assert(HII->isPostIncrement(MI) && "Not a post increment operation.");
570 #ifndef NDEBUG
571  // Post Increment means duplicates. Use dense map to find duplicates in the
572  // list. Caution: Densemap initializes with the minimum of 64 buckets,
573  // whereas there are at most 5 operands in the post increment.
574  DenseSet<unsigned> DefRegsSet;
575  for (auto &MO : MI.operands())
576  if (MO.isReg() && MO.isDef())
577  DefRegsSet.insert(MO.getReg());
578 
579  for (auto &MO : MI.operands())
580  if (MO.isReg() && MO.isUse() && DefRegsSet.count(MO.getReg()))
581  return MO;
582 #else
583  if (MI.mayLoad()) {
584  const MachineOperand &Op1 = MI.getOperand(1);
585  // The 2nd operand is always the post increment operand in load.
586  assert(Op1.isReg() && "Post increment operand has be to a register.");
587  return Op1;
588  }
589  if (MI.getDesc().mayStore()) {
590  const MachineOperand &Op0 = MI.getOperand(0);
591  // The 1st operand is always the post increment operand in store.
592  assert(Op0.isReg() && "Post increment operand has be to a register.");
593  return Op0;
594  }
595 #endif
596  // we should never come here.
597  llvm_unreachable("mayLoad or mayStore not set for Post Increment operation");
598 }
599 
600 // Get the value being stored.
602  // value being stored is always the last operand.
603  return MI.getOperand(MI.getNumOperands()-1);
604 }
605 
606 static bool isLoadAbsSet(const MachineInstr &MI) {
607  unsigned Opc = MI.getOpcode();
608  switch (Opc) {
609  case Hexagon::L4_loadrd_ap:
610  case Hexagon::L4_loadrb_ap:
611  case Hexagon::L4_loadrh_ap:
612  case Hexagon::L4_loadrub_ap:
613  case Hexagon::L4_loadruh_ap:
614  case Hexagon::L4_loadri_ap:
615  return true;
616  }
617  return false;
618 }
619 
621  assert(isLoadAbsSet(MI));
622  return MI.getOperand(1);
623 }
624 
625 // Can be new value store?
626 // Following restrictions are to be respected in convert a store into
627 // a new value store.
628 // 1. If an instruction uses auto-increment, its address register cannot
629 // be a new-value register. Arch Spec 5.4.2.1
630 // 2. If an instruction uses absolute-set addressing mode, its address
631 // register cannot be a new-value register. Arch Spec 5.4.2.1.
632 // 3. If an instruction produces a 64-bit result, its registers cannot be used
633 // as new-value registers. Arch Spec 5.4.2.2.
634 // 4. If the instruction that sets the new-value register is conditional, then
635 // the instruction that uses the new-value register must also be conditional,
636 // and both must always have their predicates evaluate identically.
637 // Arch Spec 5.4.2.3.
638 // 5. There is an implied restriction that a packet cannot have another store,
639 // if there is a new value store in the packet. Corollary: if there is
640 // already a store in a packet, there can not be a new value store.
641 // Arch Spec: 3.4.4.2
643  const MachineInstr &PacketMI, unsigned DepReg) {
644  // Make sure we are looking at the store, that can be promoted.
645  if (!HII->mayBeNewStore(MI))
646  return false;
647 
648  // Make sure there is dependency and can be new value'd.
649  const MachineOperand &Val = getStoreValueOperand(MI);
650  if (Val.isReg() && Val.getReg() != DepReg)
651  return false;
652 
653  const MCInstrDesc& MCID = PacketMI.getDesc();
654 
655  // First operand is always the result.
656  const TargetRegisterClass *PacketRC = HII->getRegClass(MCID, 0, HRI, MF);
657  // Double regs can not feed into new value store: PRM section: 5.4.2.2.
658  if (PacketRC == &Hexagon::DoubleRegsRegClass)
659  return false;
660 
661  // New-value stores are of class NV (slot 0), dual stores require class ST
662  // in slot 0 (PRM 5.5).
663  for (auto I : CurrentPacketMIs) {
664  SUnit *PacketSU = MIToSUnit.find(I)->second;
665  if (PacketSU->getInstr()->mayStore())
666  return false;
667  }
668 
669  // Make sure it's NOT the post increment register that we are going to
670  // new value.
671  if (HII->isPostIncrement(MI) &&
672  getPostIncrementOperand(MI, HII).getReg() == DepReg) {
673  return false;
674  }
675 
676  if (HII->isPostIncrement(PacketMI) && PacketMI.mayLoad() &&
677  getPostIncrementOperand(PacketMI, HII).getReg() == DepReg) {
678  // If source is post_inc, or absolute-set addressing, it can not feed
679  // into new value store
680  // r3 = memw(r2++#4)
681  // memw(r30 + #-1404) = r2.new -> can not be new value store
682  // arch spec section: 5.4.2.1.
683  return false;
684  }
685 
686  if (isLoadAbsSet(PacketMI) && getAbsSetOperand(PacketMI).getReg() == DepReg)
687  return false;
688 
689  // If the source that feeds the store is predicated, new value store must
690  // also be predicated.
691  if (HII->isPredicated(PacketMI)) {
692  if (!HII->isPredicated(MI))
693  return false;
694 
695  // Check to make sure that they both will have their predicates
696  // evaluate identically.
697  unsigned predRegNumSrc = 0;
698  unsigned predRegNumDst = 0;
699  const TargetRegisterClass* predRegClass = nullptr;
700 
701  // Get predicate register used in the source instruction.
702  for (auto &MO : PacketMI.operands()) {
703  if (!MO.isReg())
704  continue;
705  predRegNumSrc = MO.getReg();
706  predRegClass = HRI->getMinimalPhysRegClass(predRegNumSrc);
707  if (predRegClass == &Hexagon::PredRegsRegClass)
708  break;
709  }
710  assert((predRegClass == &Hexagon::PredRegsRegClass) &&
711  "predicate register not found in a predicated PacketMI instruction");
712 
713  // Get predicate register used in new-value store instruction.
714  for (auto &MO : MI.operands()) {
715  if (!MO.isReg())
716  continue;
717  predRegNumDst = MO.getReg();
718  predRegClass = HRI->getMinimalPhysRegClass(predRegNumDst);
719  if (predRegClass == &Hexagon::PredRegsRegClass)
720  break;
721  }
722  assert((predRegClass == &Hexagon::PredRegsRegClass) &&
723  "predicate register not found in a predicated MI instruction");
724 
725  // New-value register producer and user (store) need to satisfy these
726  // constraints:
727  // 1) Both instructions should be predicated on the same register.
728  // 2) If producer of the new-value register is .new predicated then store
729  // should also be .new predicated and if producer is not .new predicated
730  // then store should not be .new predicated.
731  // 3) Both new-value register producer and user should have same predicate
732  // sense, i.e, either both should be negated or both should be non-negated.
733  if (predRegNumDst != predRegNumSrc ||
734  HII->isDotNewInst(PacketMI) != HII->isDotNewInst(MI) ||
735  getPredicateSense(MI, HII) != getPredicateSense(PacketMI, HII))
736  return false;
737  }
738 
739  // Make sure that other than the new-value register no other store instruction
740  // register has been modified in the same packet. Predicate registers can be
741  // modified by they should not be modified between the producer and the store
742  // instruction as it will make them both conditional on different values.
743  // We already know this to be true for all the instructions before and
744  // including PacketMI. Howerver, we need to perform the check for the
745  // remaining instructions in the packet.
746 
747  unsigned StartCheck = 0;
748 
749  for (auto I : CurrentPacketMIs) {
750  SUnit *TempSU = MIToSUnit.find(I)->second;
751  MachineInstr &TempMI = *TempSU->getInstr();
752 
753  // Following condition is true for all the instructions until PacketMI is
754  // reached (StartCheck is set to 0 before the for loop).
755  // StartCheck flag is 1 for all the instructions after PacketMI.
756  if (&TempMI != &PacketMI && !StartCheck) // Start processing only after
757  continue; // encountering PacketMI.
758 
759  StartCheck = 1;
760  if (&TempMI == &PacketMI) // We don't want to check PacketMI for dependence.
761  continue;
762 
763  for (auto &MO : MI.operands())
764  if (MO.isReg() && TempSU->getInstr()->modifiesRegister(MO.getReg(), HRI))
765  return false;
766  }
767 
768  // Make sure that for non-POST_INC stores:
769  // 1. The only use of reg is DepReg and no other registers.
770  // This handles base+index registers.
771  // The following store can not be dot new.
772  // Eg. r0 = add(r0, #3)
773  // memw(r1+r0<<#2) = r0
774  if (!HII->isPostIncrement(MI)) {
775  for (unsigned opNum = 0; opNum < MI.getNumOperands()-1; opNum++) {
776  const MachineOperand &MO = MI.getOperand(opNum);
777  if (MO.isReg() && MO.getReg() == DepReg)
778  return false;
779  }
780  }
781 
782  // If data definition is because of implicit definition of the register,
783  // do not newify the store. Eg.
784  // %r9 = ZXTH %r12, implicit %d6, implicit-def %r12
785  // S2_storerh_io %r8, 2, killed %r12; mem:ST2[%scevgep343]
786  for (auto &MO : PacketMI.operands()) {
787  if (MO.isRegMask() && MO.clobbersPhysReg(DepReg))
788  return false;
789  if (!MO.isReg() || !MO.isDef() || !MO.isImplicit())
790  continue;
791  Register R = MO.getReg();
792  if (R == DepReg || HRI->isSuperRegister(DepReg, R))
793  return false;
794  }
795 
796  // Handle imp-use of super reg case. There is a target independent side
797  // change that should prevent this situation but I am handling it for
798  // just-in-case. For example, we cannot newify R2 in the following case:
799  // %r3 = A2_tfrsi 0;
800  // S2_storeri_io killed %r0, 0, killed %r2, implicit killed %d1;
801  for (auto &MO : MI.operands()) {
802  if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == DepReg)
803  return false;
804  }
805 
806  // Can be dot new store.
807  return true;
808 }
809 
810 // Can this MI to promoted to either new value store or new value jump.
812  const SUnit *PacketSU, unsigned DepReg,
814  if (!HII->mayBeNewStore(MI))
815  return false;
816 
817  // Check to see the store can be new value'ed.
818  MachineInstr &PacketMI = *PacketSU->getInstr();
819  if (canPromoteToNewValueStore(MI, PacketMI, DepReg))
820  return true;
821 
822  // Check to see the compare/jump can be new value'ed.
823  // This is done as a pass on its own. Don't need to check it here.
824  return false;
825 }
826 
827 static bool isImplicitDependency(const MachineInstr &I, bool CheckDef,
828  unsigned DepReg) {
829  for (auto &MO : I.operands()) {
830  if (CheckDef && MO.isRegMask() && MO.clobbersPhysReg(DepReg))
831  return true;
832  if (!MO.isReg() || MO.getReg() != DepReg || !MO.isImplicit())
833  continue;
834  if (CheckDef == MO.isDef())
835  return true;
836  }
837  return false;
838 }
839 
840 // Check to see if an instruction can be dot new.
842  const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII,
843  const TargetRegisterClass* RC) {
844  // Already a dot new instruction.
845  if (HII->isDotNewInst(MI) && !HII->mayBeNewStore(MI))
846  return false;
847 
848  if (!isNewifiable(MI, RC))
849  return false;
850 
851  const MachineInstr &PI = *PacketSU->getInstr();
852 
853  // The "new value" cannot come from inline asm.
854  if (PI.isInlineAsm())
855  return false;
856 
857  // IMPLICIT_DEFs won't materialize as real instructions, so .new makes no
858  // sense.
859  if (PI.isImplicitDef())
860  return false;
861 
862  // If dependency is trough an implicitly defined register, we should not
863  // newify the use.
864  if (isImplicitDependency(PI, true, DepReg) ||
865  isImplicitDependency(MI, false, DepReg))
866  return false;
867 
868  const MCInstrDesc& MCID = PI.getDesc();
869  const TargetRegisterClass *VecRC = HII->getRegClass(MCID, 0, HRI, MF);
870  if (DisableVecDblNVStores && VecRC == &Hexagon::HvxWRRegClass)
871  return false;
872 
873  // predicate .new
874  if (RC == &Hexagon::PredRegsRegClass)
875  return HII->predCanBeUsedAsDotNew(PI, DepReg);
876 
877  if (RC != &Hexagon::PredRegsRegClass && !HII->mayBeNewStore(MI))
878  return false;
879 
880  // Create a dot new machine instruction to see if resources can be
881  // allocated. If not, bail out now.
882  int NewOpcode = HII->getDotNewOp(MI);
883  const MCInstrDesc &D = HII->get(NewOpcode);
884  MachineInstr *NewMI = MF.CreateMachineInstr(D, DebugLoc());
885  bool ResourcesAvailable = ResourceTracker->canReserveResources(*NewMI);
886  MF.DeleteMachineInstr(NewMI);
887  if (!ResourcesAvailable)
888  return false;
889 
890  // New Value Store only. New Value Jump generated as a separate pass.
891  if (!canPromoteToNewValue(MI, PacketSU, DepReg, MII))
892  return false;
893 
894  return true;
895 }
896 
897 // Go through the packet instructions and search for an anti dependency between
898 // them and DepReg from MI. Consider this case:
899 // Trying to add
900 // a) %r1 = TFRI_cdNotPt %p3, 2
901 // to this packet:
902 // {
903 // b) %p0 = C2_or killed %p3, killed %p0
904 // c) %p3 = C2_tfrrp %r23
905 // d) %r1 = C2_cmovenewit %p3, 4
906 // }
907 // The P3 from a) and d) will be complements after
908 // a)'s P3 is converted to .new form
909 // Anti-dep between c) and b) is irrelevant for this case
911  unsigned DepReg) {
912  SUnit *PacketSUDep = MIToSUnit.find(&MI)->second;
913 
914  for (auto I : CurrentPacketMIs) {
915  // We only care for dependencies to predicated instructions
916  if (!HII->isPredicated(*I))
917  continue;
918 
919  // Scheduling Unit for current insn in the packet
920  SUnit *PacketSU = MIToSUnit.find(I)->second;
921 
922  // Look at dependencies between current members of the packet and
923  // predicate defining instruction MI. Make sure that dependency is
924  // on the exact register we care about.
925  if (PacketSU->isSucc(PacketSUDep)) {
926  for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
927  auto &Dep = PacketSU->Succs[i];
928  if (Dep.getSUnit() == PacketSUDep && Dep.getKind() == SDep::Anti &&
929  Dep.getReg() == DepReg)
930  return true;
931  }
932  }
933  }
934 
935  return false;
936 }
937 
938 /// Gets the predicate register of a predicated instruction.
940  const HexagonInstrInfo *QII) {
941  /// We use the following rule: The first predicate register that is a use is
942  /// the predicate register of a predicated instruction.
943  assert(QII->isPredicated(MI) && "Must be predicated instruction");
944 
945  for (auto &Op : MI.operands()) {
946  if (Op.isReg() && Op.getReg() && Op.isUse() &&
947  Hexagon::PredRegsRegClass.contains(Op.getReg()))
948  return Op.getReg();
949  }
950 
951  llvm_unreachable("Unknown instruction operand layout");
952  return 0;
953 }
954 
955 // Given two predicated instructions, this function detects whether
956 // the predicates are complements.
958  MachineInstr &MI2) {
959  // If we don't know the predicate sense of the instructions bail out early, we
960  // need it later.
961  if (getPredicateSense(MI1, HII) == PK_Unknown ||
962  getPredicateSense(MI2, HII) == PK_Unknown)
963  return false;
964 
965  // Scheduling unit for candidate.
966  SUnit *SU = MIToSUnit[&MI1];
967 
968  // One corner case deals with the following scenario:
969  // Trying to add
970  // a) %r24 = A2_tfrt %p0, %r25
971  // to this packet:
972  // {
973  // b) %r25 = A2_tfrf %p0, %r24
974  // c) %p0 = C2_cmpeqi %r26, 1
975  // }
976  //
977  // On general check a) and b) are complements, but presence of c) will
978  // convert a) to .new form, and then it is not a complement.
979  // We attempt to detect it by analyzing existing dependencies in the packet.
980 
981  // Analyze relationships between all existing members of the packet.
982  // Look for Anti dependecy on the same predicate reg as used in the
983  // candidate.
984  for (auto I : CurrentPacketMIs) {
985  // Scheduling Unit for current insn in the packet.
986  SUnit *PacketSU = MIToSUnit.find(I)->second;
987 
988  // If this instruction in the packet is succeeded by the candidate...
989  if (PacketSU->isSucc(SU)) {
990  for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
991  auto Dep = PacketSU->Succs[i];
992  // The corner case exist when there is true data dependency between
993  // candidate and one of current packet members, this dep is on
994  // predicate reg, and there already exist anti dep on the same pred in
995  // the packet.
996  if (Dep.getSUnit() == SU && Dep.getKind() == SDep::Data &&
997  Hexagon::PredRegsRegClass.contains(Dep.getReg())) {
998  // Here I know that I is predicate setting instruction with true
999  // data dep to candidate on the register we care about - c) in the
1000  // above example. Now I need to see if there is an anti dependency
1001  // from c) to any other instruction in the same packet on the pred
1002  // reg of interest.
1003  if (restrictingDepExistInPacket(*I, Dep.getReg()))
1004  return false;
1005  }
1006  }
1007  }
1008  }
1009 
1010  // If the above case does not apply, check regular complement condition.
1011  // Check that the predicate register is the same and that the predicate
1012  // sense is different We also need to differentiate .old vs. .new: !p0
1013  // is not complementary to p0.new.
1014  unsigned PReg1 = getPredicatedRegister(MI1, HII);
1015  unsigned PReg2 = getPredicatedRegister(MI2, HII);
1016  return PReg1 == PReg2 &&
1017  Hexagon::PredRegsRegClass.contains(PReg1) &&
1018  Hexagon::PredRegsRegClass.contains(PReg2) &&
1019  getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) &&
1020  HII->isDotNewInst(MI1) == HII->isDotNewInst(MI2);
1021 }
1022 
1023 // Initialize packetizer flags.
1025  Dependence = false;
1026  PromotedToDotNew = false;
1027  GlueToNewValueJump = false;
1028  GlueAllocframeStore = false;
1029  FoundSequentialDependence = false;
1030  ChangedOffset = INT64_MAX;
1031 }
1032 
1033 // Ignore bundling of pseudo instructions.
1035  const MachineBasicBlock *) {
1036  if (MI.isDebugInstr())
1037  return true;
1038 
1039  if (MI.isCFIInstruction())
1040  return false;
1041 
1042  // We must print out inline assembly.
1043  if (MI.isInlineAsm())
1044  return false;
1045 
1046  if (MI.isImplicitDef())
1047  return false;
1048 
1049  // We check if MI has any functional units mapped to it. If it doesn't,
1050  // we ignore the instruction.
1051  const MCInstrDesc& TID = MI.getDesc();
1052  auto *IS = ResourceTracker->getInstrItins()->beginStage(TID.getSchedClass());
1053  unsigned FuncUnits = IS->getUnits();
1054  return !FuncUnits;
1055 }
1056 
1058  // Ensure any bundles created by gather packetize remain seperate.
1059  if (MI.isBundle())
1060  return true;
1061 
1062  if (MI.isEHLabel() || MI.isCFIInstruction())
1063  return true;
1064 
1065  // Consider inline asm to not be a solo instruction by default.
1066  // Inline asm will be put in a packet temporarily, but then it will be
1067  // removed, and placed outside of the packet (before or after, depending
1068  // on dependencies). This is to reduce the impact of inline asm as a
1069  // "packet splitting" instruction.
1070  if (MI.isInlineAsm() && !ScheduleInlineAsm)
1071  return true;
1072 
1073  if (isSchedBarrier(MI))
1074  return true;
1075 
1076  if (HII->isSolo(MI))
1077  return true;
1078 
1079  if (MI.getOpcode() == Hexagon::A2_nop)
1080  return true;
1081 
1082  return false;
1083 }
1084 
1085 // Quick check if instructions MI and MJ cannot coexist in the same packet.
1086 // Limit the tests to be "one-way", e.g. "if MI->isBranch and MJ->isInlineAsm",
1087 // but not the symmetric case: "if MJ->isBranch and MI->isInlineAsm".
1088 // For full test call this function twice:
1089 // cannotCoexistAsymm(MI, MJ) || cannotCoexistAsymm(MJ, MI)
1090 // Doing the test only one way saves the amount of code in this function,
1091 // since every test would need to be repeated with the MI and MJ reversed.
1092 static bool cannotCoexistAsymm(const MachineInstr &MI, const MachineInstr &MJ,
1093  const HexagonInstrInfo &HII) {
1094  const MachineFunction *MF = MI.getParent()->getParent();
1096  HII.isHVXMemWithAIndirect(MI, MJ))
1097  return true;
1098 
1099  // An inline asm cannot be together with a branch, because we may not be
1100  // able to remove the asm out after packetizing (i.e. if the asm must be
1101  // moved past the bundle). Similarly, two asms cannot be together to avoid
1102  // complications when determining their relative order outside of a bundle.
1103  if (MI.isInlineAsm())
1104  return MJ.isInlineAsm() || MJ.isBranch() || MJ.isBarrier() ||
1105  MJ.isCall() || MJ.isTerminator();
1106 
1107  // New-value stores cannot coexist with any other stores.
1108  if (HII.isNewValueStore(MI) && MJ.mayStore())
1109  return true;
1110 
1111  switch (MI.getOpcode()) {
1112  case Hexagon::S2_storew_locked:
1113  case Hexagon::S4_stored_locked:
1114  case Hexagon::L2_loadw_locked:
1115  case Hexagon::L4_loadd_locked:
1116  case Hexagon::Y2_dccleana:
1117  case Hexagon::Y2_dccleaninva:
1118  case Hexagon::Y2_dcinva:
1119  case Hexagon::Y2_dczeroa:
1120  case Hexagon::Y4_l2fetch:
1121  case Hexagon::Y5_l2fetch: {
1122  // These instructions can only be grouped with ALU32 or non-floating-point
1123  // XTYPE instructions. Since there is no convenient way of identifying fp
1124  // XTYPE instructions, only allow grouping with ALU32 for now.
1125  unsigned TJ = HII.getType(MJ);
1126  if (TJ != HexagonII::TypeALU32_2op &&
1127  TJ != HexagonII::TypeALU32_3op &&
1129  return true;
1130  break;
1131  }
1132  default:
1133  break;
1134  }
1135 
1136  // "False" really means that the quick check failed to determine if
1137  // I and J cannot coexist.
1138  return false;
1139 }
1140 
1141 // Full, symmetric check.
1143  const MachineInstr &MJ) {
1144  return cannotCoexistAsymm(MI, MJ, *HII) || cannotCoexistAsymm(MJ, MI, *HII);
1145 }
1146 
1148  for (auto &B : MF) {
1149  MachineBasicBlock::iterator BundleIt;
1151  for (auto I = B.instr_begin(), E = B.instr_end(); I != E; I = NextI) {
1152  NextI = std::next(I);
1153  MachineInstr &MI = *I;
1154  if (MI.isBundle())
1155  BundleIt = I;
1156  if (!MI.isInsideBundle())
1157  continue;
1158 
1159  // Decide on where to insert the instruction that we are pulling out.
1160  // Debug instructions always go before the bundle, but the placement of
1161  // INLINE_ASM depends on potential dependencies. By default, try to
1162  // put it before the bundle, but if the asm writes to a register that
1163  // other instructions in the bundle read, then we need to place it
1164  // after the bundle (to preserve the bundle semantics).
1165  bool InsertBeforeBundle;
1166  if (MI.isInlineAsm())
1167  InsertBeforeBundle = !hasWriteToReadDep(MI, *BundleIt, HRI);
1168  else if (MI.isDebugValue())
1169  InsertBeforeBundle = true;
1170  else
1171  continue;
1172 
1173  BundleIt = moveInstrOut(MI, BundleIt, InsertBeforeBundle);
1174  }
1175  }
1176 }
1177 
1178 // Check if a given instruction is of class "system".
1179 static bool isSystemInstr(const MachineInstr &MI) {
1180  unsigned Opc = MI.getOpcode();
1181  switch (Opc) {
1182  case Hexagon::Y2_barrier:
1183  case Hexagon::Y2_dcfetchbo:
1184  case Hexagon::Y4_l2fetch:
1185  case Hexagon::Y5_l2fetch:
1186  return true;
1187  }
1188  return false;
1189 }
1190 
1192  const MachineInstr &J) {
1193  // The dependence graph may not include edges between dead definitions,
1194  // so without extra checks, we could end up packetizing two instruction
1195  // defining the same (dead) register.
1196  if (I.isCall() || J.isCall())
1197  return false;
1198  if (HII->isPredicated(I) || HII->isPredicated(J))
1199  return false;
1200 
1201  BitVector DeadDefs(Hexagon::NUM_TARGET_REGS);
1202  for (auto &MO : I.operands()) {
1203  if (!MO.isReg() || !MO.isDef() || !MO.isDead())
1204  continue;
1205  DeadDefs[MO.getReg()] = true;
1206  }
1207 
1208  for (auto &MO : J.operands()) {
1209  if (!MO.isReg() || !MO.isDef() || !MO.isDead())
1210  continue;
1211  Register R = MO.getReg();
1212  if (R != Hexagon::USR_OVF && DeadDefs[R])
1213  return true;
1214  }
1215  return false;
1216 }
1217 
1219  const MachineInstr &J) {
1220  // A save callee-save register function call can only be in a packet
1221  // with instructions that don't write to the callee-save registers.
1222  if ((HII->isSaveCalleeSavedRegsCall(I) &&
1223  doesModifyCalleeSavedReg(J, HRI)) ||
1224  (HII->isSaveCalleeSavedRegsCall(J) &&
1225  doesModifyCalleeSavedReg(I, HRI)))
1226  return true;
1227 
1228  // Two control flow instructions cannot go in the same packet.
1229  if (isControlFlow(I) && isControlFlow(J))
1230  return true;
1231 
1232  // \ref-manual (7.3.4) A loop setup packet in loopN or spNloop0 cannot
1233  // contain a speculative indirect jump,
1234  // a new-value compare jump or a dealloc_return.
1235  auto isBadForLoopN = [this] (const MachineInstr &MI) -> bool {
1236  if (MI.isCall() || HII->isDeallocRet(MI) || HII->isNewValueJump(MI))
1237  return true;
1238  if (HII->isPredicated(MI) && HII->isPredicatedNew(MI) && HII->isJumpR(MI))
1239  return true;
1240  return false;
1241  };
1242 
1243  if (HII->isLoopN(I) && isBadForLoopN(J))
1244  return true;
1245  if (HII->isLoopN(J) && isBadForLoopN(I))
1246  return true;
1247 
1248  // dealloc_return cannot appear in the same packet as a conditional or
1249  // unconditional jump.
1250  return HII->isDeallocRet(I) &&
1251  (J.isBranch() || J.isCall() || J.isBarrier());
1252 }
1253 
1255  const MachineInstr &J) {
1256  // Adding I to a packet that has J.
1257 
1258  // Regmasks are not reflected in the scheduling dependency graph, so
1259  // we need to check them manually. This code assumes that regmasks only
1260  // occur on calls, and the problematic case is when we add an instruction
1261  // defining a register R to a packet that has a call that clobbers R via
1262  // a regmask. Those cannot be packetized together, because the call will
1263  // be executed last. That's also a reson why it is ok to add a call
1264  // clobbering R to a packet that defines R.
1265 
1266  // Look for regmasks in J.
1267  for (const MachineOperand &OpJ : J.operands()) {
1268  if (!OpJ.isRegMask())
1269  continue;
1270  assert((J.isCall() || HII->isTailCall(J)) && "Regmask on a non-call");
1271  for (const MachineOperand &OpI : I.operands()) {
1272  if (OpI.isReg()) {
1273  if (OpJ.clobbersPhysReg(OpI.getReg()))
1274  return true;
1275  } else if (OpI.isRegMask()) {
1276  // Both are regmasks. Assume that they intersect.
1277  return true;
1278  }
1279  }
1280  }
1281  return false;
1282 }
1283 
1285  const MachineInstr &J) {
1286  bool SysI = isSystemInstr(I), SysJ = isSystemInstr(J);
1287  bool StoreI = I.mayStore(), StoreJ = J.mayStore();
1288  if ((SysI && StoreJ) || (SysJ && StoreI))
1289  return true;
1290 
1291  if (StoreI && StoreJ) {
1292  if (HII->isNewValueInst(J) || HII->isMemOp(J) || HII->isMemOp(I))
1293  return true;
1294  } else {
1295  // A memop cannot be in the same packet with another memop or a store.
1296  // Two stores can be together, but here I and J cannot both be stores.
1297  bool MopStI = HII->isMemOp(I) || StoreI;
1298  bool MopStJ = HII->isMemOp(J) || StoreJ;
1299  if (MopStI && MopStJ)
1300  return true;
1301  }
1302 
1303  return (StoreJ && HII->isDeallocRet(I)) || (StoreI && HII->isDeallocRet(J));
1304 }
1305 
1306 // SUI is the current instruction that is out side of the current packet.
1307 // SUJ is the current instruction inside the current packet against which that
1308 // SUI will be packetized.
1310  assert(SUI->getInstr() && SUJ->getInstr());
1311  MachineInstr &I = *SUI->getInstr();
1312  MachineInstr &J = *SUJ->getInstr();
1313 
1314  // Clear IgnoreDepMIs when Packet starts.
1315  if (CurrentPacketMIs.size() == 1)
1316  IgnoreDepMIs.clear();
1317 
1318  MachineBasicBlock::iterator II = I.getIterator();
1319 
1320  // Solo instructions cannot go in the packet.
1321  assert(!isSoloInstruction(I) && "Unexpected solo instr!");
1322 
1323  if (cannotCoexist(I, J))
1324  return false;
1325 
1326  Dependence = hasDeadDependence(I, J) || hasControlDependence(I, J);
1327  if (Dependence)
1328  return false;
1329 
1330  // Regmasks are not accounted for in the scheduling graph, so we need
1331  // to explicitly check for dependencies caused by them. They should only
1332  // appear on calls, so it's not too pessimistic to reject all regmask
1333  // dependencies.
1334  Dependence = hasRegMaskDependence(I, J);
1335  if (Dependence)
1336  return false;
1337 
1338  // Dual-store does not allow second store, if the first store is not
1339  // in SLOT0. New value store, new value jump, dealloc_return and memop
1340  // always take SLOT0. Arch spec 3.4.4.2.
1341  Dependence = hasDualStoreDependence(I, J);
1342  if (Dependence)
1343  return false;
1344 
1345  // If an instruction feeds new value jump, glue it.
1346  MachineBasicBlock::iterator NextMII = I.getIterator();
1347  ++NextMII;
1348  if (NextMII != I.getParent()->end() && HII->isNewValueJump(*NextMII)) {
1349  MachineInstr &NextMI = *NextMII;
1350 
1351  bool secondRegMatch = false;
1352  const MachineOperand &NOp0 = NextMI.getOperand(0);
1353  const MachineOperand &NOp1 = NextMI.getOperand(1);
1354 
1355  if (NOp1.isReg() && I.getOperand(0).getReg() == NOp1.getReg())
1356  secondRegMatch = true;
1357 
1358  for (MachineInstr *PI : CurrentPacketMIs) {
1359  // NVJ can not be part of the dual jump - Arch Spec: section 7.8.
1360  if (PI->isCall()) {
1361  Dependence = true;
1362  break;
1363  }
1364  // Validate:
1365  // 1. Packet does not have a store in it.
1366  // 2. If the first operand of the nvj is newified, and the second
1367  // operand is also a reg, it (second reg) is not defined in
1368  // the same packet.
1369  // 3. If the second operand of the nvj is newified, (which means
1370  // first operand is also a reg), first reg is not defined in
1371  // the same packet.
1372  if (PI->getOpcode() == Hexagon::S2_allocframe || PI->mayStore() ||
1373  HII->isLoopN(*PI)) {
1374  Dependence = true;
1375  break;
1376  }
1377  // Check #2/#3.
1378  const MachineOperand &OpR = secondRegMatch ? NOp0 : NOp1;
1379  if (OpR.isReg() && PI->modifiesRegister(OpR.getReg(), HRI)) {
1380  Dependence = true;
1381  break;
1382  }
1383  }
1384 
1385  GlueToNewValueJump = true;
1386  if (Dependence)
1387  return false;
1388  }
1389 
1390  // There no dependency between a prolog instruction and its successor.
1391  if (!SUJ->isSucc(SUI))
1392  return true;
1393 
1394  for (unsigned i = 0; i < SUJ->Succs.size(); ++i) {
1395  if (FoundSequentialDependence)
1396  break;
1397 
1398  if (SUJ->Succs[i].getSUnit() != SUI)
1399  continue;
1400 
1401  SDep::Kind DepType = SUJ->Succs[i].getKind();
1402  // For direct calls:
1403  // Ignore register dependences for call instructions for packetization
1404  // purposes except for those due to r31 and predicate registers.
1405  //
1406  // For indirect calls:
1407  // Same as direct calls + check for true dependences to the register
1408  // used in the indirect call.
1409  //
1410  // We completely ignore Order dependences for call instructions.
1411  //
1412  // For returns:
1413  // Ignore register dependences for return instructions like jumpr,
1414  // dealloc return unless we have dependencies on the explicit uses
1415  // of the registers used by jumpr (like r31) or dealloc return
1416  // (like r29 or r30).
1417  unsigned DepReg = 0;
1418  const TargetRegisterClass *RC = nullptr;
1419  if (DepType == SDep::Data) {
1420  DepReg = SUJ->Succs[i].getReg();
1421  RC = HRI->getMinimalPhysRegClass(DepReg);
1422  }
1423 
1424  if (I.isCall() || HII->isJumpR(I) || I.isReturn() || HII->isTailCall(I)) {
1425  if (!isRegDependence(DepType))
1426  continue;
1427  if (!isCallDependent(I, DepType, SUJ->Succs[i].getReg()))
1428  continue;
1429  }
1430 
1431  if (DepType == SDep::Data) {
1432  if (canPromoteToDotCur(J, SUJ, DepReg, II, RC))
1433  if (promoteToDotCur(J, DepType, II, RC))
1434  continue;
1435  }
1436 
1437  // Data dpendence ok if we have load.cur.
1438  if (DepType == SDep::Data && HII->isDotCurInst(J)) {
1439  if (HII->isHVXVec(I))
1440  continue;
1441  }
1442 
1443  // For instructions that can be promoted to dot-new, try to promote.
1444  if (DepType == SDep::Data) {
1445  if (canPromoteToDotNew(I, SUJ, DepReg, II, RC)) {
1446  if (promoteToDotNew(I, DepType, II, RC)) {
1447  PromotedToDotNew = true;
1448  if (cannotCoexist(I, J))
1449  FoundSequentialDependence = true;
1450  continue;
1451  }
1452  }
1453  if (HII->isNewValueJump(I))
1454  continue;
1455  }
1456 
1457  // For predicated instructions, if the predicates are complements then
1458  // there can be no dependence.
1459  if (HII->isPredicated(I) && HII->isPredicated(J) &&
1460  arePredicatesComplements(I, J)) {
1461  // Not always safe to do this translation.
1462  // DAG Builder attempts to reduce dependence edges using transitive
1463  // nature of dependencies. Here is an example:
1464  //
1465  // r0 = tfr_pt ... (1)
1466  // r0 = tfr_pf ... (2)
1467  // r0 = tfr_pt ... (3)
1468  //
1469  // There will be an output dependence between (1)->(2) and (2)->(3).
1470  // However, there is no dependence edge between (1)->(3). This results
1471  // in all 3 instructions going in the same packet. We ignore dependce
1472  // only once to avoid this situation.
1473  auto Itr = find(IgnoreDepMIs, &J);
1474  if (Itr != IgnoreDepMIs.end()) {
1475  Dependence = true;
1476  return false;
1477  }
1478  IgnoreDepMIs.push_back(&I);
1479  continue;
1480  }
1481 
1482  // Ignore Order dependences between unconditional direct branches
1483  // and non-control-flow instructions.
1484  if (isDirectJump(I) && !J.isBranch() && !J.isCall() &&
1485  DepType == SDep::Order)
1486  continue;
1487 
1488  // Ignore all dependences for jumps except for true and output
1489  // dependences.
1490  if (I.isConditionalBranch() && DepType != SDep::Data &&
1491  DepType != SDep::Output)
1492  continue;
1493 
1494  if (DepType == SDep::Output) {
1495  FoundSequentialDependence = true;
1496  break;
1497  }
1498 
1499  // For Order dependences:
1500  // 1. Volatile loads/stores can be packetized together, unless other
1501  // rules prevent is.
1502  // 2. Store followed by a load is not allowed.
1503  // 3. Store followed by a store is valid.
1504  // 4. Load followed by any memory operation is allowed.
1505  if (DepType == SDep::Order) {
1506  if (!PacketizeVolatiles) {
1507  bool OrdRefs = I.hasOrderedMemoryRef() || J.hasOrderedMemoryRef();
1508  if (OrdRefs) {
1509  FoundSequentialDependence = true;
1510  break;
1511  }
1512  }
1513  // J is first, I is second.
1514  bool LoadJ = J.mayLoad(), StoreJ = J.mayStore();
1515  bool LoadI = I.mayLoad(), StoreI = I.mayStore();
1516  bool NVStoreJ = HII->isNewValueStore(J);
1517  bool NVStoreI = HII->isNewValueStore(I);
1518  bool IsVecJ = HII->isHVXVec(J);
1519  bool IsVecI = HII->isHVXVec(I);
1520 
1522  ((LoadJ && StoreI && !NVStoreI) ||
1523  (StoreJ && LoadI && !NVStoreJ)) &&
1524  (J.getOpcode() != Hexagon::S2_allocframe &&
1525  I.getOpcode() != Hexagon::S2_allocframe) &&
1526  (J.getOpcode() != Hexagon::L2_deallocframe &&
1527  I.getOpcode() != Hexagon::L2_deallocframe) &&
1528  (!HII->isMemOp(J) && !HII->isMemOp(I)) && (!IsVecJ && !IsVecI))
1529  setmemShufDisabled(true);
1530  else
1531  if (StoreJ && LoadI && alias(J, I)) {
1532  FoundSequentialDependence = true;
1533  break;
1534  }
1535 
1536  if (!StoreJ)
1537  if (!LoadJ || (!LoadI && !StoreI)) {
1538  // If J is neither load nor store, assume a dependency.
1539  // If J is a load, but I is neither, also assume a dependency.
1540  FoundSequentialDependence = true;
1541  break;
1542  }
1543  // Store followed by store: not OK on V2.
1544  // Store followed by load: not OK on all.
1545  // Load followed by store: OK on all.
1546  // Load followed by load: OK on all.
1547  continue;
1548  }
1549 
1550  // Special case for ALLOCFRAME: even though there is dependency
1551  // between ALLOCFRAME and subsequent store, allow it to be packetized
1552  // in a same packet. This implies that the store is using the caller's
1553  // SP. Hence, offset needs to be updated accordingly.
1554  if (DepType == SDep::Data && J.getOpcode() == Hexagon::S2_allocframe) {
1555  unsigned Opc = I.getOpcode();
1556  switch (Opc) {
1557  case Hexagon::S2_storerd_io:
1558  case Hexagon::S2_storeri_io:
1559  case Hexagon::S2_storerh_io:
1560  case Hexagon::S2_storerb_io:
1561  if (I.getOperand(0).getReg() == HRI->getStackRegister()) {
1562  // Since this store is to be glued with allocframe in the same
1563  // packet, it will use SP of the previous stack frame, i.e.
1564  // caller's SP. Therefore, we need to recalculate offset
1565  // according to this change.
1566  GlueAllocframeStore = useCallersSP(I);
1567  if (GlueAllocframeStore)
1568  continue;
1569  }
1570  break;
1571  default:
1572  break;
1573  }
1574  }
1575 
1576  // There are certain anti-dependencies that cannot be ignored.
1577  // Specifically:
1578  // J2_call ... implicit-def %r0 ; SUJ
1579  // R0 = ... ; SUI
1580  // Those cannot be packetized together, since the call will observe
1581  // the effect of the assignment to R0.
1582  if ((DepType == SDep::Anti || DepType == SDep::Output) && J.isCall()) {
1583  // Check if I defines any volatile register. We should also check
1584  // registers that the call may read, but these happen to be a
1585  // subset of the volatile register set.
1586  for (const MachineOperand &Op : I.operands()) {
1587  if (Op.isReg() && Op.isDef()) {
1588  Register R = Op.getReg();
1589  if (!J.readsRegister(R, HRI) && !J.modifiesRegister(R, HRI))
1590  continue;
1591  } else if (!Op.isRegMask()) {
1592  // If I has a regmask assume dependency.
1593  continue;
1594  }
1595  FoundSequentialDependence = true;
1596  break;
1597  }
1598  }
1599 
1600  // Skip over remaining anti-dependences. Two instructions that are
1601  // anti-dependent can share a packet, since in most such cases all
1602  // operands are read before any modifications take place.
1603  // The exceptions are branch and call instructions, since they are
1604  // executed after all other instructions have completed (at least
1605  // conceptually).
1606  if (DepType != SDep::Anti) {
1607  FoundSequentialDependence = true;
1608  break;
1609  }
1610  }
1611 
1612  if (FoundSequentialDependence) {
1613  Dependence = true;
1614  return false;
1615  }
1616 
1617  return true;
1618 }
1619 
1621  assert(SUI->getInstr() && SUJ->getInstr());
1622  MachineInstr &I = *SUI->getInstr();
1623  MachineInstr &J = *SUJ->getInstr();
1624 
1625  bool Coexist = !cannotCoexist(I, J);
1626 
1627  if (Coexist && !Dependence)
1628  return true;
1629 
1630  // Check if the instruction was promoted to a dot-new. If so, demote it
1631  // back into a dot-old.
1632  if (PromotedToDotNew)
1633  demoteToDotOld(I);
1634 
1635  cleanUpDotCur();
1636  // Check if the instruction (must be a store) was glued with an allocframe
1637  // instruction. If so, restore its offset to its original value, i.e. use
1638  // current SP instead of caller's SP.
1639  if (GlueAllocframeStore) {
1640  useCalleesSP(I);
1641  GlueAllocframeStore = false;
1642  }
1643 
1644  if (ChangedOffset != INT64_MAX)
1645  undoChangedOffset(I);
1646 
1647  if (GlueToNewValueJump) {
1648  // Putting I and J together would prevent the new-value jump from being
1649  // packetized with the producer. In that case I and J must be separated.
1650  GlueToNewValueJump = false;
1651  return false;
1652  }
1653 
1654  if (!Coexist)
1655  return false;
1656 
1657  if (ChangedOffset == INT64_MAX && updateOffset(SUI, SUJ)) {
1658  FoundSequentialDependence = false;
1659  Dependence = false;
1660  return true;
1661  }
1662 
1663  return false;
1664 }
1665 
1666 
1668  bool FoundLoad = false;
1669  bool FoundStore = false;
1670 
1671  for (auto MJ : CurrentPacketMIs) {
1672  unsigned Opc = MJ->getOpcode();
1673  if (Opc == Hexagon::S2_allocframe || Opc == Hexagon::L2_deallocframe)
1674  continue;
1675  if (HII->isMemOp(*MJ))
1676  continue;
1677  if (MJ->mayLoad())
1678  FoundLoad = true;
1679  if (MJ->mayStore() && !HII->isNewValueStore(*MJ))
1680  FoundStore = true;
1681  }
1682  return FoundLoad && FoundStore;
1683 }
1684 
1685 
1689  MachineBasicBlock *MBB = MI.getParent();
1690 
1691  if (CurrentPacketMIs.empty())
1692  PacketStalls = false;
1693  PacketStalls |= producesStall(MI);
1694 
1695  if (MI.isImplicitDef()) {
1696  // Add to the packet to allow subsequent instructions to be checked
1697  // properly.
1698  CurrentPacketMIs.push_back(&MI);
1699  return MII;
1700  }
1701  assert(ResourceTracker->canReserveResources(MI));
1702 
1703  bool ExtMI = HII->isExtended(MI) || HII->isConstExtended(MI);
1704  bool Good = true;
1705 
1706  if (GlueToNewValueJump) {
1707  MachineInstr &NvjMI = *++MII;
1708  // We need to put both instructions in the same packet: MI and NvjMI.
1709  // Either of them can require a constant extender. Try to add both to
1710  // the current packet, and if that fails, end the packet and start a
1711  // new one.
1712  ResourceTracker->reserveResources(MI);
1713  if (ExtMI)
1714  Good = tryAllocateResourcesForConstExt(true);
1715 
1716  bool ExtNvjMI = HII->isExtended(NvjMI) || HII->isConstExtended(NvjMI);
1717  if (Good) {
1718  if (ResourceTracker->canReserveResources(NvjMI))
1719  ResourceTracker->reserveResources(NvjMI);
1720  else
1721  Good = false;
1722  }
1723  if (Good && ExtNvjMI)
1724  Good = tryAllocateResourcesForConstExt(true);
1725 
1726  if (!Good) {
1727  endPacket(MBB, MI);
1728  assert(ResourceTracker->canReserveResources(MI));
1729  ResourceTracker->reserveResources(MI);
1730  if (ExtMI) {
1731  assert(canReserveResourcesForConstExt());
1732  tryAllocateResourcesForConstExt(true);
1733  }
1734  assert(ResourceTracker->canReserveResources(NvjMI));
1735  ResourceTracker->reserveResources(NvjMI);
1736  if (ExtNvjMI) {
1737  assert(canReserveResourcesForConstExt());
1738  reserveResourcesForConstExt();
1739  }
1740  }
1741  CurrentPacketMIs.push_back(&MI);
1742  CurrentPacketMIs.push_back(&NvjMI);
1743  return MII;
1744  }
1745 
1746  ResourceTracker->reserveResources(MI);
1747  if (ExtMI && !tryAllocateResourcesForConstExt(true)) {
1748  endPacket(MBB, MI);
1749  if (PromotedToDotNew)
1750  demoteToDotOld(MI);
1751  if (GlueAllocframeStore) {
1752  useCalleesSP(MI);
1753  GlueAllocframeStore = false;
1754  }
1755  ResourceTracker->reserveResources(MI);
1756  reserveResourcesForConstExt();
1757  }
1758 
1759  CurrentPacketMIs.push_back(&MI);
1760  return MII;
1761 }
1762 
1765  // Replace VLIWPacketizerList::endPacket(MBB, EndMI).
1766 
1767  bool memShufDisabled = getmemShufDisabled();
1768  if (memShufDisabled && !foundLSInPacket()) {
1769  setmemShufDisabled(false);
1770  LLVM_DEBUG(dbgs() << " Not added to NoShufPacket\n");
1771  }
1772  memShufDisabled = getmemShufDisabled();
1773 
1774  OldPacketMIs.clear();
1775  for (MachineInstr *MI : CurrentPacketMIs) {
1776  MachineBasicBlock::instr_iterator NextMI = std::next(MI->getIterator());
1777  for (auto &I : make_range(HII->expandVGatherPseudo(*MI), NextMI))
1778  OldPacketMIs.push_back(&I);
1779  }
1780  CurrentPacketMIs.clear();
1781 
1782  if (OldPacketMIs.size() > 1) {
1783  MachineBasicBlock::instr_iterator FirstMI(OldPacketMIs.front());
1785  finalizeBundle(*MBB, FirstMI, LastMI);
1786  auto BundleMII = std::prev(FirstMI);
1787  if (memShufDisabled)
1788  HII->setBundleNoShuf(BundleMII);
1789 
1790  setmemShufDisabled(false);
1791  }
1792 
1793  ResourceTracker->clearResources();
1794  LLVM_DEBUG(dbgs() << "End packet\n");
1795 }
1796 
1798  if (Minimal)
1799  return false;
1800  return !producesStall(MI);
1801 }
1802 
1803 // V60 forward scheduling.
1805  // If the packet already stalls, then ignore the stall from a subsequent
1806  // instruction in the same packet.
1807  if (PacketStalls)
1808  return false;
1809 
1810  // Check whether the previous packet is in a different loop. If this is the
1811  // case, there is little point in trying to avoid a stall because that would
1812  // favor the rare case (loop entry) over the common case (loop iteration).
1813  //
1814  // TODO: We should really be able to check all the incoming edges if this is
1815  // the first packet in a basic block, so we can avoid stalls from the loop
1816  // backedge.
1817  if (!OldPacketMIs.empty()) {
1818  auto *OldBB = OldPacketMIs.front()->getParent();
1819  auto *ThisBB = I.getParent();
1820  if (MLI->getLoopFor(OldBB) != MLI->getLoopFor(ThisBB))
1821  return false;
1822  }
1823 
1824  SUnit *SUI = MIToSUnit[const_cast<MachineInstr *>(&I)];
1825 
1826  // If the latency is 0 and there is a data dependence between this
1827  // instruction and any instruction in the current packet, we disregard any
1828  // potential stalls due to the instructions in the previous packet. Most of
1829  // the instruction pairs that can go together in the same packet have 0
1830  // latency between them. The exceptions are
1831  // 1. NewValueJumps as they're generated much later and the latencies can't
1832  // be changed at that point.
1833  // 2. .cur instructions, if its consumer has a 0 latency successor (such as
1834  // .new). In this case, the latency between .cur and the consumer stays
1835  // non-zero even though we can have both .cur and .new in the same packet.
1836  // Changing the latency to 0 is not an option as it causes software pipeliner
1837  // to not pipeline in some cases.
1838 
1839  // For Example:
1840  // {
1841  // I1: v6.cur = vmem(r0++#1)
1842  // I2: v7 = valign(v6,v4,r2)
1843  // I3: vmem(r5++#1) = v7.new
1844  // }
1845  // Here I2 and I3 has 0 cycle latency, but I1 and I2 has 2.
1846 
1847  for (auto J : CurrentPacketMIs) {
1848  SUnit *SUJ = MIToSUnit[J];
1849  for (auto &Pred : SUI->Preds)
1850  if (Pred.getSUnit() == SUJ)
1851  if ((Pred.getLatency() == 0 && Pred.isAssignedRegDep()) ||
1852  HII->isNewValueJump(I) || HII->isToBeScheduledASAP(*J, I))
1853  return false;
1854  }
1855 
1856  // Check if the latency is greater than one between this instruction and any
1857  // instruction in the previous packet.
1858  for (auto J : OldPacketMIs) {
1859  SUnit *SUJ = MIToSUnit[J];
1860  for (auto &Pred : SUI->Preds)
1861  if (Pred.getSUnit() == SUJ && Pred.getLatency() > 1)
1862  return true;
1863  }
1864 
1865  return false;
1866 }
1867 
1868 //===----------------------------------------------------------------------===//
1869 // Public Constructor Functions
1870 //===----------------------------------------------------------------------===//
1871 
1873  return new HexagonPacketizer(Minimal);
1874 }
bool canPromoteToNewValueStore(const MachineInstr &MI, const MachineInstr &PacketMI, unsigned DepReg)
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
static bool hasWriteToReadDep(const MachineInstr &FirstI, const MachineInstr &SecondI, const TargetRegisterInfo *TRI)
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:635
instr_iterator instr_end()
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool canPromoteToDotNew(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
static bool cannotCoexistAsymm(const MachineInstr &MI, const MachineInstr &MJ, const HexagonInstrInfo &HII)
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
bool isCFIInstruction() const
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:364
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:178
static bool isImplicitDependency(const MachineInstr &I, bool CheckDef, unsigned DepReg)
unsigned Reg
bool isInlineAsm() const
bool demoteToDotOld(MachineInstr &MI)
static cl::opt< bool > PacketizeVolatiles("hexagon-packetize-volatiles", cl::ZeroOrMore, cl::Hidden, cl::init(true), cl::desc("Allow non-solo packetization of volatile memory references"))
void undoChangedOffset(MachineInstr &MI)
Undo the changed offset.
static cl::opt< bool > DisablePacketizer("disable-packetizer", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon packetizer pass"))
INITIALIZE_PASS_BEGIN(HexagonPacketizer, "hexagon-packetizer", "Hexagon Packetizer", false, false) INITIALIZE_PASS_END(HexagonPacketizer
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
Kind
These are the different kinds of scheduling dependencies.
Definition: ScheduleDAG.h:52
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:461
MachineInstr * CreateMachineInstr(const MCInstrDesc &MCID, const DebugLoc &DL, bool NoImp=false)
CreateMachineInstr - Allocate a new MachineInstr.
#define HEXAGON_LRFP_SIZE
SmallVector< SDep, 4 > Preds
All sunit predecessors.
Definition: ScheduleDAG.h:256
A register anti-dependence (aka WAR).
Definition: ScheduleDAG.h:54
bool restrictingDepExistInPacket(MachineInstr &, unsigned)
bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:50
static cl::opt< bool > EnableGenAllInsnClass("enable-gen-insn", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Generate all instruction with TC"))
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:414
cl::opt< bool > Slot1Store("slot1-store-slot0-load", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Allow slot1 store and slot0 load"))
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:368
bool shouldAddToPacket(const MachineInstr &MI) override
Regular data dependence (aka true-dependence).
Definition: ScheduleDAG.h:53
#define INT64_MAX
Definition: DataTypes.h:77
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:651
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
void endPacket(MachineBasicBlock *MBB, MachineBasicBlock::iterator MI) override
bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2)
static bool doesModifyCalleeSavedReg(const MachineInstr &MI, const TargetRegisterInfo *TRI)
Returns true if the instruction modifies a callee-saved register.
void unbundleFromPred()
Break bundle above this instruction.
A register output-dependence (aka WAW).
Definition: ScheduleDAG.h:55
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:408
static bool isControlFlow(const MachineInstr &MI)
bool isBundle() const
void initializeHexagonPacketizerPass(PassRegistry &)
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
Definition: MachineInstr.h:352
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
hexagon Hexagon Packetizer
bool hasDualStoreDependence(const MachineInstr &I, const MachineInstr &J)
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:659
static MachineBasicBlock::iterator moveInstrOut(MachineInstr &MI, MachineBasicBlock::iterator BundleIt, bool Before)
static unsigned getPredicatedRegister(MachineInstr &MI, const HexagonInstrInfo *QII)
Gets the predicate register of a predicated instruction.
static const MachineOperand & getAbsSetOperand(const MachineInstr &MI)
bool isSoloInstruction(const MachineInstr &MI) override
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:596
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:822
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
Definition: ScheduleDAG.h:373
static bool isSystemInstr(const MachineInstr &MI)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
std::pair< iterator, bool > insert(const ValueT &V)
Definition: DenseSet.h:187
Represent the analysis usage information of a pass.
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:313
bool isEHLabel() const
Definition: MachineInstr.h:992
void setImm(int64_t immVal)
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
self_iterator getIterator()
Definition: ilist_node.h:81
static bool isRegDependence(const SDep::Kind DepType)
bool tryAllocateResourcesForConstExt(bool Reserve)
void DeleteMachineInstr(MachineInstr *MI)
DeleteMachineInstr - Delete the given MachineInstr.
bool isImplicitDef() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Any other ordering dependency.
Definition: ScheduleDAG.h:56
auto find(R &&Range, const T &Val) -> decltype(adl_begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1198
bool isPostIncrement(const MachineInstr &MI) const override
Return true for post-incremented instructions.
bool isDebugInstr() const
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
static const MachineOperand & getPostIncrementOperand(const MachineInstr &MI, const HexagonInstrInfo *HII)
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Iterator for intrusive lists based on ilist_node.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
bool isNewValueStore(const MachineInstr &MI) const
bool isDebugValue() const
MachineOperand class - Representation of each machine instruction operand.
bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
uint64_t getType(const MachineInstr &MI) const
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
static cl::opt< bool > DisableVecDblNVStores("disable-vecdbl-nv-stores", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Disable vector double new-value-stores"))
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:301
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override
bool mayStore() const
Return true if this instruction could possibly modify memory.
Definition: MCInstrDesc.h:419
static const MachineOperand & getStoreValueOperand(const MachineInstr &MI)
static bool isLoadAbsSet(const MachineInstr &MI)
static PredicateKind getPredicateSense(const MachineInstr &MI, const HexagonInstrInfo *HII)
Returns true if an instruction is predicated on p0 and false if it&#39;s predicated on !p0...
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:256
MachineFunctionProperties & set(Property P)
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
static bool isSchedBarrier(const MachineInstr &MI)
bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType, unsigned DepReg)
bool ignorePseudoInstruction(const MachineInstr &MI, const MachineBasicBlock *MBB) override
bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC)
bool updateOffset(SUnit *SUI, SUnit *SUJ)
Return true if we can update the offset in MI so that MI and MJ can be packetized together...
cl::opt< bool > ScheduleInlineAsm
#define I(x, y, z)
Definition: MD5.cpp:58
bool isCall() const
Return true if the instruction is a call.
Definition: MCInstrDesc.h:272
bool isPredicatedTrue(const MachineInstr &MI) const
uint32_t Size
Definition: Profile.cpp:46
bool hasControlDependence(const MachineInstr &I, const MachineInstr &J)
bool useCallersSP(MachineInstr &MI)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
hexagon packetizer
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:809
bool promoteToDotNew(MachineInstr &MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool hasDeadDependence(const MachineInstr &I, const MachineInstr &J)
bool isHVXMemWithAIndirect(const MachineInstr &I, const MachineInstr &J) const
bool isTerminator() const
Returns true if this instruction part of the terminator for a basic block.
Definition: MCInstrDesc.h:285
aarch64 promote const
bool cannotCoexist(const MachineInstr &MI, const MachineInstr &MJ)
bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override
FunctionPass * createHexagonPacketizer(bool Minimal)
const HexagonInstrInfo * getInstrInfo() const override
SmallVector< SDep, 4 > Succs
All sunit successors.
Definition: ScheduleDAG.h:257
void useCalleesSP(MachineInstr &MI)
bool hasRegMaskDependence(const MachineInstr &I, const MachineInstr &J)
IRTranslator LLVM IR MI
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:642
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
Register getReg() const
getReg - Returns the register number.
void unpacketizeSoloInstrs(MachineFunction &MF)
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object...
Dependence - This class represents a dependence between two memory memory references in a function...
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
void finalizeBundle(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
finalizeBundle - Finalize a machine instruction bundle which includes a sequence of instructions star...
bool canPromoteToNewValue(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII)
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
bool isSucc(const SUnit *N) const
Tests if node N is a successor of this node.
Definition: ScheduleDAG.h:439
#define OP(n)
Definition: regex2.h:73
static bool isDirectJump(const MachineInstr &MI)
bool producesStall(const MachineInstr &MI)
Properties which a MachineFunction may have at a given point in time.
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
Wrapper class representing virtual and physical registers.
Definition: Register.h:19