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HexagonVLIWPacketizer.h
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1 //===- HexagonPacketizer.h - VLIW packetizer --------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H
10 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H
11 
15 #include <vector>
16 
17 namespace llvm {
18 
19 class HexagonInstrInfo;
20 class HexagonRegisterInfo;
21 class MachineBranchProbabilityInfo;
22 class MachineFunction;
23 class MachineInstr;
24 class MachineLoopInfo;
25 class TargetRegisterClass;
26 
28  // Vector of instructions assigned to the packet that has just been created.
29  std::vector<MachineInstr *> OldPacketMIs;
30 
31  // Has the instruction been promoted to a dot-new instruction.
32  bool PromotedToDotNew;
33 
34  // Has the instruction been glued to allocframe.
35  bool GlueAllocframeStore;
36 
37  // Has the feeder instruction been glued to new value jump.
38  bool GlueToNewValueJump;
39 
40  // This holds the offset value, when pruning the dependences.
41  int64_t ChangedOffset;
42 
43  // Check if there is a dependence between some instruction already in this
44  // packet and this instruction.
45  bool Dependence;
46 
47  // Only check for dependence if there are resources available to
48  // schedule this instruction.
49  bool FoundSequentialDependence;
50 
51  bool MemShufDisabled = false;
52 
53  // Track MIs with ignored dependence.
54  std::vector<MachineInstr*> IgnoreDepMIs;
55 
56  // Set to true if the packet contains an instruction that stalls with an
57  // instruction from the previous packet.
58  bool PacketStalls = false;
59 
60 protected:
61  /// A handle to the branch probability pass.
64 
65 private:
66  const HexagonInstrInfo *HII;
67  const HexagonRegisterInfo *HRI;
68  const bool Minimal;
69 
70 public:
73  const MachineBranchProbabilityInfo *MBPI,
74  bool Minimal);
75 
76  // initPacketizerState - initialize some internal flags.
77  void initPacketizerState() override;
78 
79  // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
81  const MachineBasicBlock *MBB) override;
82 
83  // isSoloInstruction - return true if instruction MI can not be packetized
84  // with any other instruction, which means that MI itself is a packet.
85  bool isSoloInstruction(const MachineInstr &MI) override;
86 
87  // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
88  // together.
89  bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override;
90 
91  // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
92  // and SUJ.
93  bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override;
94 
95  bool foundLSInPacket();
97  void endPacket(MachineBasicBlock *MBB,
99  bool shouldAddToPacket(const MachineInstr &MI) override;
100 
102 
103 protected:
105  return MemShufDisabled;
106  };
107  void setmemShufDisabled(bool val) {
108  MemShufDisabled = val;
109  };
110  bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType,
111  unsigned DepReg);
112  bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType,
114  const TargetRegisterClass *RC);
115  bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU,
116  unsigned DepReg, MachineBasicBlock::iterator &MII,
117  const TargetRegisterClass *RC);
118  void cleanUpDotCur();
119 
120  bool promoteToDotNew(MachineInstr &MI, SDep::Kind DepType,
122  const TargetRegisterClass *RC);
123  bool canPromoteToDotNew(const MachineInstr &MI, const SUnit *PacketSU,
124  unsigned DepReg, MachineBasicBlock::iterator &MII,
125  const TargetRegisterClass *RC);
126  bool canPromoteToNewValue(const MachineInstr &MI, const SUnit *PacketSU,
127  unsigned DepReg, MachineBasicBlock::iterator &MII);
129  const MachineInstr &PacketMI, unsigned DepReg);
130  bool demoteToDotOld(MachineInstr &MI);
131  bool useCallersSP(MachineInstr &MI);
132  void useCalleesSP(MachineInstr &MI);
133  bool updateOffset(SUnit *SUI, SUnit *SUJ);
136  bool restrictingDepExistInPacket(MachineInstr&, unsigned);
137  bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC);
138  bool isCurifiable(MachineInstr &MI);
139  bool cannotCoexist(const MachineInstr &MI, const MachineInstr &MJ);
140 
141  bool isPromotedToDotNew() const {
142  return PromotedToDotNew;
143  }
144 
145  bool tryAllocateResourcesForConstExt(bool Reserve);
148  bool hasDeadDependence(const MachineInstr &I, const MachineInstr &J);
149  bool hasControlDependence(const MachineInstr &I, const MachineInstr &J);
150  bool hasRegMaskDependence(const MachineInstr &I, const MachineInstr &J);
151  bool hasDualStoreDependence(const MachineInstr &I, const MachineInstr &J);
152  bool producesStall(const MachineInstr &MI);
153 };
154 
155 } // end namespace llvm
156 
157 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H
bool canPromoteToNewValueStore(const MachineInstr &MI, const MachineInstr &PacketMI, unsigned DepReg)
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool canPromoteToDotNew(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
const MachineLoopInfo * MLI
bool demoteToDotOld(MachineInstr &MI)
bool isCurifiable(MachineInstr &MI)
void undoChangedOffset(MachineInstr &MI)
Undo the changed offset.
Kind
These are the different kinds of scheduling dependencies.
Definition: ScheduleDAG.h:52
bool restrictingDepExistInPacket(MachineInstr &, unsigned)
bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
bool shouldAddToPacket(const MachineInstr &MI) override
MachineFunction & MF
void endPacket(MachineBasicBlock *MBB, MachineBasicBlock::iterator MI) override
bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2)
const MachineBranchProbabilityInfo * MBPI
A handle to the branch probability pass.
bool hasDualStoreDependence(const MachineInstr &I, const MachineInstr &J)
bool isSoloInstruction(const MachineInstr &MI) override
bool tryAllocateResourcesForConstExt(bool Reserve)
bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override
HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI, AliasAnalysis *AA, const MachineBranchProbabilityInfo *MBPI, bool Minimal)
MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override
Representation of each machine instruction.
Definition: MachineInstr.h:64
bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType, unsigned DepReg)
bool ignorePseudoInstruction(const MachineInstr &MI, const MachineBasicBlock *MBB) override
bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC)
bool updateOffset(SUnit *SUI, SUnit *SUJ)
Return true if we can update the offset in MI so that MI and MJ can be packetized together...
#define I(x, y, z)
Definition: MD5.cpp:58
bool hasControlDependence(const MachineInstr &I, const MachineInstr &J)
bool useCallersSP(MachineInstr &MI)
bool promoteToDotNew(MachineInstr &MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
bool hasDeadDependence(const MachineInstr &I, const MachineInstr &J)
bool cannotCoexist(const MachineInstr &MI, const MachineInstr &MJ)
bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override
void useCalleesSP(MachineInstr &MI)
bool hasRegMaskDependence(const MachineInstr &I, const MachineInstr &J)
IRTranslator LLVM IR MI
void unpacketizeSoloInstrs(MachineFunction &MF)
Dependence - This class represents a dependence between two memory memory references in a function...
bool canPromoteToNewValue(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII)
bool producesStall(const MachineInstr &MI)
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242