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HexagonInstrInfo.h
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1 //===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Hexagon implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
14 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
15 
17 #include "llvm/ADT/ArrayRef.h"
18 #include "llvm/ADT/SmallVector.h"
23 #include <cstdint>
24 #include <vector>
25 
26 #define GET_INSTRINFO_HEADER
27 #include "HexagonGenInstrInfo.inc"
28 
29 namespace llvm {
30 
31 class HexagonSubtarget;
32 class MachineBranchProbabilityInfo;
33 class MachineFunction;
34 class MachineInstr;
35 class MachineOperand;
36 class TargetRegisterInfo;
37 
39  const HexagonSubtarget &Subtarget;
40 
41  enum BundleAttribute {
42  memShufDisabledMask = 0x4
43  };
44 
45  virtual void anchor();
46 
47 public:
49 
50  /// TargetInstrInfo overrides.
51 
52  /// If the specified machine instruction is a direct
53  /// load from a stack slot, return the virtual or physical register number of
54  /// the destination along with the FrameIndex of the loaded stack slot. If
55  /// not, return 0. This predicate must return 0 if the instruction has
56  /// any side effects other than loading from the stack slot.
57  unsigned isLoadFromStackSlot(const MachineInstr &MI,
58  int &FrameIndex) const override;
59 
60  /// If the specified machine instruction is a direct
61  /// store to a stack slot, return the virtual or physical register number of
62  /// the source reg along with the FrameIndex of the loaded stack slot. If
63  /// not, return 0. This predicate must return 0 if the instruction has
64  /// any side effects other than storing to the stack slot.
65  unsigned isStoreToStackSlot(const MachineInstr &MI,
66  int &FrameIndex) const override;
67 
68  /// Check if the instruction or the bundle of instructions has
69  /// load from stack slots. Return the frameindex and machine memory operand
70  /// if true.
72  const MachineInstr &MI,
73  SmallVectorImpl<const MachineMemOperand *> &Accesses) const override;
74 
75  /// Check if the instruction or the bundle of instructions has
76  /// store to stack slots. Return the frameindex and machine memory operand
77  /// if true.
79  const MachineInstr &MI,
80  SmallVectorImpl<const MachineMemOperand *> &Accesses) const override;
81 
82  /// Analyze the branching code at the end of MBB, returning
83  /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
84  /// implemented for a target). Upon success, this returns false and returns
85  /// with the following information in various cases:
86  ///
87  /// 1. If this block ends with no branches (it just falls through to its succ)
88  /// just return false, leaving TBB/FBB null.
89  /// 2. If this block ends with only an unconditional branch, it sets TBB to be
90  /// the destination block.
91  /// 3. If this block ends with a conditional branch and it falls through to a
92  /// successor block, it sets TBB to be the branch destination block and a
93  /// list of operands that evaluate the condition. These operands can be
94  /// passed to other TargetInstrInfo methods to create new branches.
95  /// 4. If this block ends with a conditional branch followed by an
96  /// unconditional branch, it returns the 'true' destination in TBB, the
97  /// 'false' destination in FBB, and a list of operands that evaluate the
98  /// condition. These operands can be passed to other TargetInstrInfo
99  /// methods to create new branches.
100  ///
101  /// Note that removeBranch and insertBranch must be implemented to support
102  /// cases where this method returns success.
103  ///
104  /// If AllowModify is true, then this routine is allowed to modify the basic
105  /// block (e.g. delete instructions after the unconditional branch).
107  MachineBasicBlock *&FBB,
109  bool AllowModify) const override;
110 
111  /// Remove the branching code at the end of the specific MBB.
112  /// This is only invoked in cases where AnalyzeBranch returns success. It
113  /// returns the number of instructions that were removed.
114  unsigned removeBranch(MachineBasicBlock &MBB,
115  int *BytesRemoved = nullptr) const override;
116 
117  /// Insert branch code into the end of the specified MachineBasicBlock.
118  /// The operands to this method are the same as those
119  /// returned by AnalyzeBranch. This is only invoked in cases where
120  /// AnalyzeBranch returns success. It returns the number of instructions
121  /// inserted.
122  ///
123  /// It is also invoked by tail merging to add unconditional branches in
124  /// cases where AnalyzeBranch doesn't apply because there was no original
125  /// branch to analyze. At least this much must be implemented, else tail
126  /// merging needs to be disabled.
129  const DebugLoc &DL,
130  int *BytesAdded = nullptr) const override;
131 
132  /// Analyze the loop code, return true if it cannot be understood. Upon
133  /// success, this function returns false and returns information about the
134  /// induction variable and compare instruction used at the end.
135  bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
136  MachineInstr *&CmpInst) const override;
137 
138  /// Generate code to reduce the loop iteration by one and check if the loop
139  /// is finished. Return the value/register of the new loop count. We need
140  /// this function when peeling off one or more iterations of a loop. This
141  /// function assumes the nth iteration is peeled first.
142  unsigned reduceLoopCount(MachineBasicBlock &MBB,
143  MachineInstr *IndVar, MachineInstr &Cmp,
146  unsigned Iter, unsigned MaxIter) const override;
147 
148  /// Return true if it's profitable to predicate
149  /// instructions with accumulated instruction latency of "NumCycles"
150  /// of the specified basic block, where the probability of the instructions
151  /// being executed is given by Probability, and Confidence is a measure
152  /// of our confidence that it will be properly predicted.
153  bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
154  unsigned ExtraPredCycles,
155  BranchProbability Probability) const override;
156 
157  /// Second variant of isProfitableToIfCvt. This one
158  /// checks for the case where two basic blocks from true and false path
159  /// of a if-then-else (diamond) are predicated on mutally exclusive
160  /// predicates, where the probability of the true path being taken is given
161  /// by Probability, and Confidence is a measure of our confidence that it
162  /// will be properly predicted.
164  unsigned NumTCycles, unsigned ExtraTCycles,
165  MachineBasicBlock &FMBB,
166  unsigned NumFCycles, unsigned ExtraFCycles,
167  BranchProbability Probability) const override;
168 
169  /// Return true if it's profitable for if-converter to duplicate instructions
170  /// of specified accumulated instruction latencies in the specified MBB to
171  /// enable if-conversion.
172  /// The probability of the instructions being executed is given by
173  /// Probability, and Confidence is a measure of our confidence that it
174  /// will be properly predicted.
175  bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
176  BranchProbability Probability) const override;
177 
178  /// Emit instructions to copy a pair of physical registers.
179  ///
180  /// This function should support copies within any legal register class as
181  /// well as any cross-class copies created during instruction selection.
182  ///
183  /// The source and destination registers may overlap, which may require a
184  /// careful implementation when multiple copy instructions are required for
185  /// large registers. See for example the ARM target.
187  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
188  bool KillSrc) const override;
189 
190  /// Store the specified register of the given register class to the specified
191  /// stack frame index. The store instruction is to be added to the given
192  /// machine basic block before the specified machine instruction. If isKill
193  /// is true, the register operand is the last use and must be marked kill.
196  unsigned SrcReg, bool isKill, int FrameIndex,
197  const TargetRegisterClass *RC,
198  const TargetRegisterInfo *TRI) const override;
199 
200  /// Load the specified register of the given register class from the specified
201  /// stack frame index. The load instruction is to be added to the given
202  /// machine basic block before the specified machine instruction.
205  unsigned DestReg, int FrameIndex,
206  const TargetRegisterClass *RC,
207  const TargetRegisterInfo *TRI) const override;
208 
209  /// This function is called for all pseudo instructions
210  /// that remain after register allocation. Many pseudo instructions are
211  /// created to help register allocation. This is the place to convert them
212  /// into real instructions. The target can edit MI in place, or it can insert
213  /// new instructions and erase MI. The function should return true if
214  /// anything was changed.
215  bool expandPostRAPseudo(MachineInstr &MI) const override;
216 
217  /// Get the base register and byte offset of a load/store instr.
218  bool getMemOperandWithOffset(const MachineInstr &LdSt,
219  const MachineOperand *&BaseOp,
220  int64_t &Offset,
221  const TargetRegisterInfo *TRI) const override;
222 
223  /// Reverses the branch condition of the specified condition list,
224  /// returning false on success and true if it cannot be reversed.
226  const override;
227 
228  /// Insert a noop into the instruction stream at the specified point.
229  void insertNoop(MachineBasicBlock &MBB,
230  MachineBasicBlock::iterator MI) const override;
231 
232  /// Returns true if the instruction is already predicated.
233  bool isPredicated(const MachineInstr &MI) const override;
234 
235  /// Return true for post-incremented instructions.
236  bool isPostIncrement(const MachineInstr &MI) const override;
237 
238  /// Convert the instruction into a predicated instruction.
239  /// It returns true if the operation was successful.
241  ArrayRef<MachineOperand> Cond) const override;
242 
243  /// Returns true if the first specified predicate
244  /// subsumes the second, e.g. GE subsumes GT.
246  ArrayRef<MachineOperand> Pred2) const override;
247 
248  /// If the specified instruction defines any predicate
249  /// or condition code register(s) used for predication, returns true as well
250  /// as the definition predicate(s) by reference.
252  std::vector<MachineOperand> &Pred) const override;
253 
254  /// Return true if the specified instruction can be predicated.
255  /// By default, this returns true for every instruction with a
256  /// PredicateOperand.
257  bool isPredicable(const MachineInstr &MI) const override;
258 
259  /// Test if the given instruction should be considered a scheduling boundary.
260  /// This primarily includes labels and terminators.
261  bool isSchedulingBoundary(const MachineInstr &MI,
262  const MachineBasicBlock *MBB,
263  const MachineFunction &MF) const override;
264 
265  /// Measure the specified inline asm to determine an approximation of its
266  /// length.
267  unsigned getInlineAsmLength(const char *Str,
268  const MCAsmInfo &MAI) const override;
269 
270  /// Allocate and return a hazard recognizer to use for this target when
271  /// scheduling the machine instructions after register allocation.
274  const ScheduleDAG *DAG) const override;
275 
276  /// For a comparison instruction, return the source registers
277  /// in SrcReg and SrcReg2 if having two register operands, and the value it
278  /// compares against in CmpValue. Return true if the comparison instruction
279  /// can be analyzed.
280  bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
281  unsigned &SrcReg2, int &Mask, int &Value) const override;
282 
283  /// Compute the instruction latency of a given instruction.
284  /// If the instruction has higher cost when predicated, it's returned via
285  /// PredCost.
286  unsigned getInstrLatency(const InstrItineraryData *ItinData,
287  const MachineInstr &MI,
288  unsigned *PredCost = nullptr) const override;
289 
290  /// Create machine specific model for scheduling.
291  DFAPacketizer *
292  CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override;
293 
294  // Sometimes, it is possible for the target
295  // to tell, even without aliasing information, that two MIs access different
296  // memory addresses. This function returns true if two MIs access different
297  // memory addresses and false otherwise.
298  bool
300  const MachineInstr &MIb,
301  AliasAnalysis *AA = nullptr) const override;
302 
303  /// For instructions with a base and offset, return the position of the
304  /// base register and offset operands.
305  bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos,
306  unsigned &OffsetPos) const override;
307 
308  /// If the instruction is an increment of a constant value, return the amount.
309  bool getIncrementValue(const MachineInstr &MI, int &Value) const override;
310 
311  /// getOperandLatency - Compute and return the use operand latency of a given
312  /// pair of def and use.
313  /// In most cases, the static scheduling itinerary was enough to determine the
314  /// operand latency. But it may not be possible for instructions with variable
315  /// number of defs / uses.
316  ///
317  /// This is a raw interface to the itinerary that may be directly overriden by
318  /// a target. Use computeOperandLatency to get the best estimate of latency.
319  int getOperandLatency(const InstrItineraryData *ItinData,
320  const MachineInstr &DefMI, unsigned DefIdx,
321  const MachineInstr &UseMI,
322  unsigned UseIdx) const override;
323 
324  /// Decompose the machine operand's target flags into two values - the direct
325  /// target flag value and any of bit flags that are applied.
326  std::pair<unsigned, unsigned>
327  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
328 
329  /// Return an array that contains the direct target flag values and their
330  /// names.
331  ///
332  /// MIR Serialization is able to serialize only the target flags that are
333  /// defined by this method.
336 
337  /// Return an array that contains the bitmask target flag values and their
338  /// names.
339  ///
340  /// MIR Serialization is able to serialize only the target flags that are
341  /// defined by this method.
344 
345  bool isTailCall(const MachineInstr &MI) const override;
346 
347  /// HexagonInstrInfo specifics.
348 
349  unsigned createVR(MachineFunction *MF, MVT VT) const;
350  MachineInstr *findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp,
351  MachineBasicBlock *TargetBB,
352  SmallPtrSet<MachineBasicBlock *, 8> &Visited) const;
353 
354  bool isBaseImmOffset(const MachineInstr &MI) const;
355  bool isAbsoluteSet(const MachineInstr &MI) const;
356  bool isAccumulator(const MachineInstr &MI) const;
357  bool isAddrModeWithOffset(const MachineInstr &MI) const;
358  bool isComplex(const MachineInstr &MI) const;
359  bool isCompoundBranchInstr(const MachineInstr &MI) const;
360  bool isConstExtended(const MachineInstr &MI) const;
361  bool isDeallocRet(const MachineInstr &MI) const;
362  bool isDependent(const MachineInstr &ProdMI,
363  const MachineInstr &ConsMI) const;
364  bool isDotCurInst(const MachineInstr &MI) const;
365  bool isDotNewInst(const MachineInstr &MI) const;
366  bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const;
367  bool isEarlySourceInstr(const MachineInstr &MI) const;
368  bool isEndLoopN(unsigned Opcode) const;
369  bool isExpr(unsigned OpType) const;
370  bool isExtendable(const MachineInstr &MI) const;
371  bool isExtended(const MachineInstr &MI) const;
372  bool isFloat(const MachineInstr &MI) const;
373  bool isHVXMemWithAIndirect(const MachineInstr &I,
374  const MachineInstr &J) const;
375  bool isIndirectCall(const MachineInstr &MI) const;
376  bool isIndirectL4Return(const MachineInstr &MI) const;
377  bool isJumpR(const MachineInstr &MI) const;
378  bool isJumpWithinBranchRange(const MachineInstr &MI, unsigned offset) const;
379  bool isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI,
380  const MachineInstr &ESMI) const;
381  bool isLateResultInstr(const MachineInstr &MI) const;
382  bool isLateSourceInstr(const MachineInstr &MI) const;
383  bool isLoopN(const MachineInstr &MI) const;
384  bool isMemOp(const MachineInstr &MI) const;
385  bool isNewValue(const MachineInstr &MI) const;
386  bool isNewValue(unsigned Opcode) const;
387  bool isNewValueInst(const MachineInstr &MI) const;
388  bool isNewValueJump(const MachineInstr &MI) const;
389  bool isNewValueJump(unsigned Opcode) const;
390  bool isNewValueStore(const MachineInstr &MI) const;
391  bool isNewValueStore(unsigned Opcode) const;
392  bool isOperandExtended(const MachineInstr &MI, unsigned OperandNum) const;
393  bool isPredicatedNew(const MachineInstr &MI) const;
394  bool isPredicatedNew(unsigned Opcode) const;
395  bool isPredicatedTrue(const MachineInstr &MI) const;
396  bool isPredicatedTrue(unsigned Opcode) const;
397  bool isPredicated(unsigned Opcode) const;
398  bool isPredicateLate(unsigned Opcode) const;
399  bool isPredictedTaken(unsigned Opcode) const;
400  bool isSaveCalleeSavedRegsCall(const MachineInstr &MI) const;
401  bool isSignExtendingLoad(const MachineInstr &MI) const;
402  bool isSolo(const MachineInstr &MI) const;
403  bool isSpillPredRegOp(const MachineInstr &MI) const;
404  bool isTC1(const MachineInstr &MI) const;
405  bool isTC2(const MachineInstr &MI) const;
406  bool isTC2Early(const MachineInstr &MI) const;
407  bool isTC4x(const MachineInstr &MI) const;
408  bool isToBeScheduledASAP(const MachineInstr &MI1,
409  const MachineInstr &MI2) const;
410  bool isHVXVec(const MachineInstr &MI) const;
411  bool isValidAutoIncImm(const EVT VT, const int Offset) const;
412  bool isValidOffset(unsigned Opcode, int Offset,
413  const TargetRegisterInfo *TRI, bool Extend = true) const;
414  bool isVecAcc(const MachineInstr &MI) const;
415  bool isVecALU(const MachineInstr &MI) const;
416  bool isVecUsableNextPacket(const MachineInstr &ProdMI,
417  const MachineInstr &ConsMI) const;
418  bool isZeroExtendingLoad(const MachineInstr &MI) const;
419 
420  bool addLatencyToSchedule(const MachineInstr &MI1,
421  const MachineInstr &MI2) const;
422  bool canExecuteInBundle(const MachineInstr &First,
423  const MachineInstr &Second) const;
424  bool doesNotReturn(const MachineInstr &CallMI) const;
425  bool hasEHLabel(const MachineBasicBlock *B) const;
426  bool hasNonExtEquivalent(const MachineInstr &MI) const;
427  bool hasPseudoInstrPair(const MachineInstr &MI) const;
428  bool hasUncondBranch(const MachineBasicBlock *B) const;
429  bool mayBeCurLoad(const MachineInstr &MI) const;
430  bool mayBeNewStore(const MachineInstr &MI) const;
431  bool producesStall(const MachineInstr &ProdMI,
432  const MachineInstr &ConsMI) const;
433  bool producesStall(const MachineInstr &MI,
435  bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const;
436  bool PredOpcodeHasJMP_c(unsigned Opcode) const;
438 
439  unsigned getAddrMode(const MachineInstr &MI) const;
440  MachineOperand *getBaseAndOffset(const MachineInstr &MI, int64_t &Offset,
441  unsigned &AccessSize) const;
443  unsigned getCExtOpNum(const MachineInstr &MI) const;
445  getCompoundCandidateGroup(const MachineInstr &MI) const;
446  unsigned getCompoundOpcode(const MachineInstr &GA,
447  const MachineInstr &GB) const;
448  int getCondOpcode(int Opc, bool sense) const;
449  int getDotCurOp(const MachineInstr &MI) const;
450  int getNonDotCurOp(const MachineInstr &MI) const;
451  int getDotNewOp(const MachineInstr &MI) const;
452  int getDotNewPredJumpOp(const MachineInstr &MI,
453  const MachineBranchProbabilityInfo *MBPI) const;
454  int getDotNewPredOp(const MachineInstr &MI,
455  const MachineBranchProbabilityInfo *MBPI) const;
456  int getDotOldOp(const MachineInstr &MI) const;
458  const;
459  short getEquivalentHWInstr(const MachineInstr &MI) const;
460  unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData,
461  const MachineInstr &MI) const;
463  unsigned getInvertedPredicatedOpcode(const int Opc) const;
464  int getMaxValue(const MachineInstr &MI) const;
465  unsigned getMemAccessSize(const MachineInstr &MI) const;
466  int getMinValue(const MachineInstr &MI) const;
467  short getNonExtOpcode(const MachineInstr &MI) const;
468  bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg,
469  unsigned &PredRegPos, unsigned &PredRegFlags) const;
470  short getPseudoInstrPair(const MachineInstr &MI) const;
471  short getRegForm(const MachineInstr &MI) const;
472  unsigned getSize(const MachineInstr &MI) const;
473  uint64_t getType(const MachineInstr &MI) const;
474  unsigned getUnits(const MachineInstr &MI) const;
475 
477 
478  /// getInstrTimingClassLatency - Compute the instruction latency of a given
479  /// instruction using Timing Class information, if available.
480  unsigned nonDbgBBSize(const MachineBasicBlock *BB) const;
481  unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const;
482 
483  void immediateExtend(MachineInstr &MI) const;
485  MachineBasicBlock *NewTarget) const;
487  bool reversePredSense(MachineInstr &MI) const;
488  unsigned reversePrediction(unsigned Opcode) const;
489  bool validateBranchCond(const ArrayRef<MachineOperand> &Cond) const;
490 
492  bool getBundleNoShuf(const MachineInstr &MIB) const;
493  // Addressing mode relations.
494  short changeAddrMode_abs_io(short Opc) const;
495  short changeAddrMode_io_abs(short Opc) const;
496  short changeAddrMode_io_pi(short Opc) const;
497  short changeAddrMode_io_rr(short Opc) const;
498  short changeAddrMode_pi_io(short Opc) const;
499  short changeAddrMode_rr_io(short Opc) const;
500  short changeAddrMode_rr_ur(short Opc) const;
501  short changeAddrMode_ur_rr(short Opc) const;
502 
503  short changeAddrMode_abs_io(const MachineInstr &MI) const {
504  return changeAddrMode_abs_io(MI.getOpcode());
505  }
506  short changeAddrMode_io_abs(const MachineInstr &MI) const {
507  return changeAddrMode_io_abs(MI.getOpcode());
508  }
509  short changeAddrMode_io_rr(const MachineInstr &MI) const {
510  return changeAddrMode_io_rr(MI.getOpcode());
511  }
512  short changeAddrMode_rr_io(const MachineInstr &MI) const {
513  return changeAddrMode_rr_io(MI.getOpcode());
514  }
515  short changeAddrMode_rr_ur(const MachineInstr &MI) const {
516  return changeAddrMode_rr_ur(MI.getOpcode());
517  }
518  short changeAddrMode_ur_rr(const MachineInstr &MI) const {
519  return changeAddrMode_ur_rr(MI.getOpcode());
520  }
521 };
522 
523 } // end namespace llvm
524 
525 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
short getNonExtOpcode(const MachineInstr &MI) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Return an array that contains the direct target flag values and their names.
bool isVecALU(const MachineInstr &MI) const
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
If the specified instruction defines any predicate or condition code register(s) used for predication...
short changeAddrMode_io_rr(const MachineInstr &MI) const
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:699
short changeAddrMode_rr_io(short Opc) const
unsigned nonDbgBBSize(const MachineBasicBlock *BB) const
getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Clas...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
short changeAddrMode_io_abs(const MachineInstr &MI) const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index...
void setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const
short getEquivalentHWInstr(const MachineInstr &MI) const
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override
Create machine specific model for scheduling.
bool isAbsoluteSet(const MachineInstr &MI) const
bool isJumpR(const MachineInstr &MI) const
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
Returns true if the first specified predicate subsumes the second, e.g.
bool isConstExtended(const MachineInstr &MI) const
bool getInvertedPredSense(SmallVectorImpl< MachineOperand > &Cond) const
unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Reverses the branch condition of the specified condition list, returning false on success and true if...
int getMaxValue(const MachineInstr &MI) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
bool reversePredSense(MachineInstr &MI) const
int getDotNewPredOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
bool isExpr(unsigned OpType) const
bool isTailCall(const MachineInstr &MI) const override
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr *> &PrevInsts, unsigned Iter, unsigned MaxIter) const override
Generate code to reduce the loop iteration by one and check if the loop is finished.
bool producesStall(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
unsigned getMemAccessSize(const MachineInstr &MI) const
unsigned getSize(const MachineInstr &MI) const
int getDotCurOp(const MachineInstr &MI) const
bool isLateResultInstr(const MachineInstr &MI) const
void immediateExtend(MachineInstr &MI) const
immediateExtend - Changes the instruction in place to one using an immediate extender.
int getDotNewPredJumpOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
short changeAddrMode_ur_rr(short Opc) const
bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand *> &Accesses) const override
Check if the instruction or the bundle of instructions has load from stack slots. ...
bool isToBeScheduledASAP(const MachineInstr &MI1, const MachineInstr &MI2) const
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert a noop into the instruction stream at the specified point.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e...
bool isHVXVec(const MachineInstr &MI) const
bool isComplex(const MachineInstr &MI) const
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index...
unsigned getInvertedPredicatedOpcode(const int Opc) const
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
short changeAddrMode_abs_io(const MachineInstr &MI) const
unsigned getCompoundOpcode(const MachineInstr &GA, const MachineInstr &GB) const
bool isPredicatedNew(const MachineInstr &MI) const
bool canExecuteInBundle(const MachineInstr &First, const MachineInstr &Second) const
Can these instructions execute at the same time in a bundle.
bool predOpcodeHasNot(ArrayRef< MachineOperand > Cond) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
bool isVecUsableNextPacket(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
bool isDotNewInst(const MachineInstr &MI) const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
bool isDeallocRet(const MachineInstr &MI) const
bool isExtended(const MachineInstr &MI) const
bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand *> &Accesses) const override
Check if the instruction or the bundle of instructions has store to stack slots.
bool isSolo(const MachineInstr &MI) const
bool isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI, const MachineInstr &ESMI) const
MachineBasicBlock::instr_iterator expandVGatherPseudo(MachineInstr &MI) const
bool expandPostRAPseudo(MachineInstr &MI) const override
This function is called for all pseudo instructions that remain after register allocation.
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Cond) const override
Convert the instruction into a predicated instruction.
bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const
MachineInstr * findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp, MachineBasicBlock *TargetBB, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const
Find the hardware loop instruction used to set-up the specified loop.
SmallVector< MachineInstr *, 2 > getBranchingInstrs(MachineBasicBlock &MBB) const
bool doesNotReturn(const MachineInstr &CallMI) const
bool isEndLoopN(unsigned Opcode) const
bool isCompoundBranchInstr(const MachineInstr &MI) const
short changeAddrMode_io_rr(short Opc) const
bool isPredictedTaken(unsigned Opcode) const
int getMinValue(const MachineInstr &MI) const
bool getBundleNoShuf(const MachineInstr &MIB) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
Itinerary data supplied by a subtarget to be used by a target.
short changeAddrMode_io_pi(short Opc) const
bool isTC1(const MachineInstr &MI) const
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Compute the instruction latency of a given instruction.
short changeAddrMode_rr_ur(short Opc) const
bool getPredReg(ArrayRef< MachineOperand > Cond, unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const
unsigned getCExtOpNum(const MachineInstr &MI) const
MachineOperand * getBaseAndOffset(const MachineInstr &MI, int64_t &Offset, unsigned &AccessSize) const
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:55
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Return true if it&#39;s profitable for if-converter to duplicate instructions of specified accumulated in...
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Machine Value Type.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
bool getIncrementValue(const MachineInstr &MI, int &Value) const override
If the instruction is an increment of a constant value, return the amount.
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
bool validateBranchCond(const ArrayRef< MachineOperand > &Cond) const
MachineInstrBuilder & UseMI
bool isPredicable(const MachineInstr &MI) const override
Return true if the specified instruction can be predicated.
bool isAccumulator(const MachineInstr &MI) const
bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const override
For instructions with a base and offset, return the position of the base register and offset operands...
bool isZeroExtendingLoad(const MachineInstr &MI) const
short changeAddrMode_io_abs(short Opc) const
bool hasUncondBranch(const MachineBasicBlock *B) const
short changeAddrMode_abs_io(short Opc) const
unsigned getAddrMode(const MachineInstr &MI) const
int getNonDotCurOp(const MachineInstr &MI) const
bool invertAndChangeJumpTarget(MachineInstr &MI, MachineBasicBlock *NewTarget) const
bool isTC2Early(const MachineInstr &MI) const
bool isValidAutoIncImm(const EVT VT, const int Offset) const
bool isFloat(const MachineInstr &MI) const
HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI) const
void genAllInsnTimingClasses(MachineFunction &MF) const
Extended Value Type.
Definition: ValueTypes.h:33
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
short getPseudoInstrPair(const MachineInstr &MI) const
bool isEarlySourceInstr(const MachineInstr &MI) const
bool isPostIncrement(const MachineInstr &MI) const override
Return true for post-incremented instructions.
bool isExtendable(const MachineInstr &MI) const
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
bool hasPseudoInstrPair(const MachineInstr &MI) const
bool isIndirectCall(const MachineInstr &MI) const
bool isTC4x(const MachineInstr &MI) const
bool isDotCurInst(const MachineInstr &MI) const
Iterator for intrusive lists based on ilist_node.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Definition: SmallPtrSet.h:417
bool isNewValueStore(const MachineInstr &MI) const
HexagonInstrInfo(HexagonSubtarget &ST)
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Decompose the machine operand&#39;s target flags into two values - the direct target flag value and any o...
bool isNewValueInst(const MachineInstr &MI) const
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:841
bool isVecAcc(const MachineInstr &MI) const
short changeAddrMode_ur_rr(const MachineInstr &MI) const
MachineInstrBuilder MachineInstrBuilder & DefMI
bool hasEHLabel(const MachineBasicBlock *B) const
bool isJumpWithinBranchRange(const MachineInstr &MI, unsigned offset) const
unsigned getUnits(const MachineInstr &MI) const
short getRegForm(const MachineInstr &MI) const
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
uint64_t getType(const MachineInstr &MI) const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Insert branch code into the end of the specified MachineBasicBlock.
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Return true if it&#39;s profitable to predicate instructions with accumulated instruction latency of "Num...
bool isSignExtendingLoad(const MachineInstr &MI) const
bool isOperandExtended(const MachineInstr &MI, unsigned OperandNum) const
unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI) const override
Measure the specified inline asm to determine an approximation of its length.
bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const
Symmetrical. See if these two instructions are fit for duplex pair.
bool isLateSourceInstr(const MachineInstr &MI) const
bool isSpillPredRegOp(const MachineInstr &MI) const
unsigned createVR(MachineFunction *MF, MVT VT) const
HexagonInstrInfo specifics.
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Test if the given instruction should be considered a scheduling boundary.
unsigned reversePrediction(unsigned Opcode) const
bool isNewValue(const MachineInstr &MI) const
bool isSaveCalleeSavedRegsCall(const MachineInstr &MI) const
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Remove the branching code at the end of the specific MBB.
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
TargetInstrInfo overrides.
int getDotNewOp(const MachineInstr &MI) const
int getCondOpcode(int Opc, bool sense) const
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
Emit instructions to copy a pair of physical registers.
TargetSubtargetInfo - Generic base class for all target subtargets.
bool isPredicateLate(unsigned Opcode) const
Representation of each machine instruction.
Definition: MachineInstr.h:63
bool addLatencyToSchedule(const MachineInstr &MI1, const MachineInstr &MI2) const
bool isDependent(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
int getDotOldOp(const MachineInstr &MI) const
bool isValidOffset(unsigned Opcode, int Offset, const TargetRegisterInfo *TRI, bool Extend=true) const
bool mayBeNewStore(const MachineInstr &MI) const
#define I(x, y, z)
Definition: MD5.cpp:58
bool isPredicatedTrue(const MachineInstr &MI) const
bool isNewValueJump(const MachineInstr &MI) const
bool hasNonExtEquivalent(const MachineInstr &MI) const
unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData, const MachineInstr &MI) const
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
getOperandLatency - Compute and return the use operand latency of a given pair of def and use...
bool isTC2(const MachineInstr &MI) const
bool isLoopN(const MachineInstr &MI) const
bool isHVXMemWithAIndirect(const MachineInstr &I, const MachineInstr &J) const
LLVM Value Representation.
Definition: Value.h:72
bool PredOpcodeHasJMP_c(unsigned Opcode) const
bool getMemOperandWithOffset(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, const TargetRegisterInfo *TRI) const override
Get the base register and byte offset of a load/store instr.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
bool mayBeCurLoad(const MachineInstr &MI) const
bool isAddrModeWithOffset(const MachineInstr &MI) const
short changeAddrMode_pi_io(short Opc) const
IRTranslator LLVM IR MI
bool isMemOp(const MachineInstr &MI) const
short changeAddrMode_rr_io(const MachineInstr &MI) const
short changeAddrMode_rr_ur(const MachineInstr &MI) const
bool isBaseImmOffset(const MachineInstr &MI) const
bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst, MachineInstr *&CmpInst) const override
Analyze the loop code, return true if it cannot be understood.
bool isIndirectL4Return(const MachineInstr &MI) const
HexagonII::CompoundGroup getCompoundCandidateGroup(const MachineInstr &MI) const