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HexagonInstrInfo.h
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1 //===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
15 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
16 
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/SmallVector.h"
24 #include <cstdint>
25 #include <vector>
26 
27 #define GET_INSTRINFO_HEADER
28 #include "HexagonGenInstrInfo.inc"
29 
30 namespace llvm {
31 
32 class HexagonSubtarget;
33 class MachineBranchProbabilityInfo;
34 class MachineFunction;
35 class MachineInstr;
36 class MachineOperand;
37 class TargetRegisterInfo;
38 
40  const HexagonSubtarget &Subtarget;
41  virtual void anchor();
42 
43 public:
45 
46  /// TargetInstrInfo overrides.
47 
48  /// If the specified machine instruction is a direct
49  /// load from a stack slot, return the virtual or physical register number of
50  /// the destination along with the FrameIndex of the loaded stack slot. If
51  /// not, return 0. This predicate must return 0 if the instruction has
52  /// any side effects other than loading from the stack slot.
53  unsigned isLoadFromStackSlot(const MachineInstr &MI,
54  int &FrameIndex) const override;
55 
56  /// If the specified machine instruction is a direct
57  /// store to a stack slot, return the virtual or physical register number of
58  /// the source reg along with the FrameIndex of the loaded stack slot. If
59  /// not, return 0. This predicate must return 0 if the instruction has
60  /// any side effects other than storing to the stack slot.
61  unsigned isStoreToStackSlot(const MachineInstr &MI,
62  int &FrameIndex) const override;
63 
64  /// Analyze the branching code at the end of MBB, returning
65  /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
66  /// implemented for a target). Upon success, this returns false and returns
67  /// with the following information in various cases:
68  ///
69  /// 1. If this block ends with no branches (it just falls through to its succ)
70  /// just return false, leaving TBB/FBB null.
71  /// 2. If this block ends with only an unconditional branch, it sets TBB to be
72  /// the destination block.
73  /// 3. If this block ends with a conditional branch and it falls through to a
74  /// successor block, it sets TBB to be the branch destination block and a
75  /// list of operands that evaluate the condition. These operands can be
76  /// passed to other TargetInstrInfo methods to create new branches.
77  /// 4. If this block ends with a conditional branch followed by an
78  /// unconditional branch, it returns the 'true' destination in TBB, the
79  /// 'false' destination in FBB, and a list of operands that evaluate the
80  /// condition. These operands can be passed to other TargetInstrInfo
81  /// methods to create new branches.
82  ///
83  /// Note that removeBranch and insertBranch must be implemented to support
84  /// cases where this method returns success.
85  ///
86  /// If AllowModify is true, then this routine is allowed to modify the basic
87  /// block (e.g. delete instructions after the unconditional branch).
89  MachineBasicBlock *&FBB,
91  bool AllowModify) const override;
92 
93  /// Remove the branching code at the end of the specific MBB.
94  /// This is only invoked in cases where AnalyzeBranch returns success. It
95  /// returns the number of instructions that were removed.
96  unsigned removeBranch(MachineBasicBlock &MBB,
97  int *BytesRemoved = nullptr) const override;
98 
99  /// Insert branch code into the end of the specified MachineBasicBlock.
100  /// The operands to this method are the same as those
101  /// returned by AnalyzeBranch. This is only invoked in cases where
102  /// AnalyzeBranch returns success. It returns the number of instructions
103  /// inserted.
104  ///
105  /// It is also invoked by tail merging to add unconditional branches in
106  /// cases where AnalyzeBranch doesn't apply because there was no original
107  /// branch to analyze. At least this much must be implemented, else tail
108  /// merging needs to be disabled.
111  const DebugLoc &DL,
112  int *BytesAdded = nullptr) const override;
113 
114  /// Analyze the loop code, return true if it cannot be understood. Upon
115  /// success, this function returns false and returns information about the
116  /// induction variable and compare instruction used at the end.
117  bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
118  MachineInstr *&CmpInst) const override;
119 
120  /// Generate code to reduce the loop iteration by one and check if the loop is
121  /// finished. Return the value/register of the the new loop count. We need
122  /// this function when peeling off one or more iterations of a loop. This
123  /// function assumes the nth iteration is peeled first.
124  unsigned reduceLoopCount(MachineBasicBlock &MBB,
125  MachineInstr *IndVar, MachineInstr &Cmp,
128  unsigned Iter, unsigned MaxIter) const override;
129 
130  /// Return true if it's profitable to predicate
131  /// instructions with accumulated instruction latency of "NumCycles"
132  /// of the specified basic block, where the probability of the instructions
133  /// being executed is given by Probability, and Confidence is a measure
134  /// of our confidence that it will be properly predicted.
135  bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
136  unsigned ExtraPredCycles,
137  BranchProbability Probability) const override;
138 
139  /// Second variant of isProfitableToIfCvt. This one
140  /// checks for the case where two basic blocks from true and false path
141  /// of a if-then-else (diamond) are predicated on mutally exclusive
142  /// predicates, where the probability of the true path being taken is given
143  /// by Probability, and Confidence is a measure of our confidence that it
144  /// will be properly predicted.
146  unsigned NumTCycles, unsigned ExtraTCycles,
147  MachineBasicBlock &FMBB,
148  unsigned NumFCycles, unsigned ExtraFCycles,
149  BranchProbability Probability) const override;
150 
151  /// Return true if it's profitable for if-converter to duplicate instructions
152  /// of specified accumulated instruction latencies in the specified MBB to
153  /// enable if-conversion.
154  /// The probability of the instructions being executed is given by
155  /// Probability, and Confidence is a measure of our confidence that it
156  /// will be properly predicted.
157  bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
158  BranchProbability Probability) const override;
159 
160  /// Emit instructions to copy a pair of physical registers.
161  ///
162  /// This function should support copies within any legal register class as
163  /// well as any cross-class copies created during instruction selection.
164  ///
165  /// The source and destination registers may overlap, which may require a
166  /// careful implementation when multiple copy instructions are required for
167  /// large registers. See for example the ARM target.
169  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
170  bool KillSrc) const override;
171 
172  /// Store the specified register of the given register class to the specified
173  /// stack frame index. The store instruction is to be added to the given
174  /// machine basic block before the specified machine instruction. If isKill
175  /// is true, the register operand is the last use and must be marked kill.
178  unsigned SrcReg, bool isKill, int FrameIndex,
179  const TargetRegisterClass *RC,
180  const TargetRegisterInfo *TRI) const override;
181 
182  /// Load the specified register of the given register class from the specified
183  /// stack frame index. The load instruction is to be added to the given
184  /// machine basic block before the specified machine instruction.
187  unsigned DestReg, int FrameIndex,
188  const TargetRegisterClass *RC,
189  const TargetRegisterInfo *TRI) const override;
190 
191  /// This function is called for all pseudo instructions
192  /// that remain after register allocation. Many pseudo instructions are
193  /// created to help register allocation. This is the place to convert them
194  /// into real instructions. The target can edit MI in place, or it can insert
195  /// new instructions and erase MI. The function should return true if
196  /// anything was changed.
197  bool expandPostRAPseudo(MachineInstr &MI) const override;
198 
199  /// \brief Get the base register and byte offset of a load/store instr.
200  bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
201  int64_t &Offset,
202  const TargetRegisterInfo *TRI) const override;
203 
204  /// Reverses the branch condition of the specified condition list,
205  /// returning false on success and true if it cannot be reversed.
207  const override;
208 
209  /// Insert a noop into the instruction stream at the specified point.
210  void insertNoop(MachineBasicBlock &MBB,
211  MachineBasicBlock::iterator MI) const override;
212 
213  /// Returns true if the instruction is already predicated.
214  bool isPredicated(const MachineInstr &MI) const override;
215 
216  /// Return true for post-incremented instructions.
217  bool isPostIncrement(const MachineInstr &MI) const override;
218 
219  /// Convert the instruction into a predicated instruction.
220  /// It returns true if the operation was successful.
222  ArrayRef<MachineOperand> Cond) const override;
223 
224  /// Returns true if the first specified predicate
225  /// subsumes the second, e.g. GE subsumes GT.
227  ArrayRef<MachineOperand> Pred2) const override;
228 
229  /// If the specified instruction defines any predicate
230  /// or condition code register(s) used for predication, returns true as well
231  /// as the definition predicate(s) by reference.
233  std::vector<MachineOperand> &Pred) const override;
234 
235  /// Return true if the specified instruction can be predicated.
236  /// By default, this returns true for every instruction with a
237  /// PredicateOperand.
238  bool isPredicable(const MachineInstr &MI) const override;
239 
240  /// Test if the given instruction should be considered a scheduling boundary.
241  /// This primarily includes labels and terminators.
242  bool isSchedulingBoundary(const MachineInstr &MI,
243  const MachineBasicBlock *MBB,
244  const MachineFunction &MF) const override;
245 
246  /// Measure the specified inline asm to determine an approximation of its
247  /// length.
248  unsigned getInlineAsmLength(const char *Str,
249  const MCAsmInfo &MAI) const override;
250 
251  /// Allocate and return a hazard recognizer to use for this target when
252  /// scheduling the machine instructions after register allocation.
255  const ScheduleDAG *DAG) const override;
256 
257  /// For a comparison instruction, return the source registers
258  /// in SrcReg and SrcReg2 if having two register operands, and the value it
259  /// compares against in CmpValue. Return true if the comparison instruction
260  /// can be analyzed.
261  bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
262  unsigned &SrcReg2, int &Mask, int &Value) const override;
263 
264  /// Compute the instruction latency of a given instruction.
265  /// If the instruction has higher cost when predicated, it's returned via
266  /// PredCost.
267  unsigned getInstrLatency(const InstrItineraryData *ItinData,
268  const MachineInstr &MI,
269  unsigned *PredCost = nullptr) const override;
270 
271  /// Create machine specific model for scheduling.
272  DFAPacketizer *
273  CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override;
274 
275  // Sometimes, it is possible for the target
276  // to tell, even without aliasing information, that two MIs access different
277  // memory addresses. This function returns true if two MIs access different
278  // memory addresses and false otherwise.
279  bool
281  AliasAnalysis *AA = nullptr) const override;
282 
283  /// For instructions with a base and offset, return the position of the
284  /// base register and offset operands.
285  bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos,
286  unsigned &OffsetPos) const override;
287 
288  /// If the instruction is an increment of a constant value, return the amount.
289  bool getIncrementValue(const MachineInstr &MI, int &Value) const override;
290 
291  /// getOperandLatency - Compute and return the use operand latency of a given
292  /// pair of def and use.
293  /// In most cases, the static scheduling itinerary was enough to determine the
294  /// operand latency. But it may not be possible for instructions with variable
295  /// number of defs / uses.
296  ///
297  /// This is a raw interface to the itinerary that may be directly overriden by
298  /// a target. Use computeOperandLatency to get the best estimate of latency.
299  int getOperandLatency(const InstrItineraryData *ItinData,
300  const MachineInstr &DefMI, unsigned DefIdx,
301  const MachineInstr &UseMI,
302  unsigned UseIdx) const override;
303 
304  /// Decompose the machine operand's target flags into two values - the direct
305  /// target flag value and any of bit flags that are applied.
306  std::pair<unsigned, unsigned>
307  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
308 
309  /// Return an array that contains the direct target flag values and their
310  /// names.
311  ///
312  /// MIR Serialization is able to serialize only the target flags that are
313  /// defined by this method.
316 
317  /// Return an array that contains the bitmask target flag values and their
318  /// names.
319  ///
320  /// MIR Serialization is able to serialize only the target flags that are
321  /// defined by this method.
324 
325  bool isTailCall(const MachineInstr &MI) const override;
326 
327  /// HexagonInstrInfo specifics.
328 
329  unsigned createVR(MachineFunction* MF, MVT VT) const;
330 
331  bool isAbsoluteSet(const MachineInstr &MI) const;
332  bool isAccumulator(const MachineInstr &MI) const;
333  bool isComplex(const MachineInstr &MI) const;
334  bool isCompoundBranchInstr(const MachineInstr &MI) const;
335  bool isConstExtended(const MachineInstr &MI) const;
336  bool isDeallocRet(const MachineInstr &MI) const;
337  bool isDependent(const MachineInstr &ProdMI,
338  const MachineInstr &ConsMI) const;
339  bool isDotCurInst(const MachineInstr &MI) const;
340  bool isDotNewInst(const MachineInstr &MI) const;
341  bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const;
342  bool isEarlySourceInstr(const MachineInstr &MI) const;
343  bool isEndLoopN(unsigned Opcode) const;
344  bool isExpr(unsigned OpType) const;
345  bool isExtendable(const MachineInstr &MI) const;
346  bool isExtended(const MachineInstr &MI) const;
347  bool isFloat(const MachineInstr &MI) const;
348  bool isHVXMemWithAIndirect(const MachineInstr &I,
349  const MachineInstr &J) const;
350  bool isIndirectCall(const MachineInstr &MI) const;
351  bool isIndirectL4Return(const MachineInstr &MI) const;
352  bool isJumpR(const MachineInstr &MI) const;
353  bool isJumpWithinBranchRange(const MachineInstr &MI, unsigned offset) const;
354  bool isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI,
355  const MachineInstr &ESMI) const;
356  bool isLateResultInstr(const MachineInstr &MI) const;
357  bool isLateSourceInstr(const MachineInstr &MI) const;
358  bool isLoopN(const MachineInstr &MI) const;
359  bool isMemOp(const MachineInstr &MI) const;
360  bool isNewValue(const MachineInstr &MI) const;
361  bool isNewValue(unsigned Opcode) const;
362  bool isNewValueInst(const MachineInstr &MI) const;
363  bool isNewValueJump(const MachineInstr &MI) const;
364  bool isNewValueJump(unsigned Opcode) const;
365  bool isNewValueStore(const MachineInstr &MI) const;
366  bool isNewValueStore(unsigned Opcode) const;
367  bool isOperandExtended(const MachineInstr &MI, unsigned OperandNum) const;
368  bool isPredicatedNew(const MachineInstr &MI) const;
369  bool isPredicatedNew(unsigned Opcode) const;
370  bool isPredicatedTrue(const MachineInstr &MI) const;
371  bool isPredicatedTrue(unsigned Opcode) const;
372  bool isPredicated(unsigned Opcode) const;
373  bool isPredicateLate(unsigned Opcode) const;
374  bool isPredictedTaken(unsigned Opcode) const;
375  bool isSaveCalleeSavedRegsCall(const MachineInstr &MI) const;
376  bool isSignExtendingLoad(const MachineInstr &MI) const;
377  bool isSolo(const MachineInstr &MI) const;
378  bool isSpillPredRegOp(const MachineInstr &MI) const;
379  bool isTC1(const MachineInstr &MI) const;
380  bool isTC2(const MachineInstr &MI) const;
381  bool isTC2Early(const MachineInstr &MI) const;
382  bool isTC4x(const MachineInstr &MI) const;
383  bool isToBeScheduledASAP(const MachineInstr &MI1,
384  const MachineInstr &MI2) const;
385  bool isHVXVec(const MachineInstr &MI) const;
386  bool isValidAutoIncImm(const EVT VT, const int Offset) const;
387  bool isValidOffset(unsigned Opcode, int Offset,
388  const TargetRegisterInfo *TRI, bool Extend = true) const;
389  bool isVecAcc(const MachineInstr &MI) const;
390  bool isVecALU(const MachineInstr &MI) const;
391  bool isVecUsableNextPacket(const MachineInstr &ProdMI,
392  const MachineInstr &ConsMI) const;
393  bool isZeroExtendingLoad(const MachineInstr &MI) const;
394 
395  bool addLatencyToSchedule(const MachineInstr &MI1,
396  const MachineInstr &MI2) const;
397  bool canExecuteInBundle(const MachineInstr &First,
398  const MachineInstr &Second) const;
399  bool doesNotReturn(const MachineInstr &CallMI) const;
400  bool hasEHLabel(const MachineBasicBlock *B) const;
401  bool hasNonExtEquivalent(const MachineInstr &MI) const;
402  bool hasPseudoInstrPair(const MachineInstr &MI) const;
403  bool hasUncondBranch(const MachineBasicBlock *B) const;
404  bool mayBeCurLoad(const MachineInstr &MI) const;
405  bool mayBeNewStore(const MachineInstr &MI) const;
406  bool producesStall(const MachineInstr &ProdMI,
407  const MachineInstr &ConsMI) const;
408  bool producesStall(const MachineInstr &MI,
410  bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const;
411  bool PredOpcodeHasJMP_c(unsigned Opcode) const;
413 
414  unsigned getAddrMode(const MachineInstr &MI) const;
415  unsigned getBaseAndOffset(const MachineInstr &MI, int &Offset,
416  unsigned &AccessSize) const;
418  unsigned getCExtOpNum(const MachineInstr &MI) const;
420  getCompoundCandidateGroup(const MachineInstr &MI) const;
421  unsigned getCompoundOpcode(const MachineInstr &GA,
422  const MachineInstr &GB) const;
423  int getCondOpcode(int Opc, bool sense) const;
424  int getDotCurOp(const MachineInstr &MI) const;
425  int getNonDotCurOp(const MachineInstr &MI) const;
426  int getDotNewOp(const MachineInstr &MI) const;
427  int getDotNewPredJumpOp(const MachineInstr &MI,
428  const MachineBranchProbabilityInfo *MBPI) const;
429  int getDotNewPredOp(const MachineInstr &MI,
430  const MachineBranchProbabilityInfo *MBPI) const;
431  int getDotOldOp(const MachineInstr &MI) const;
433  const;
434  short getEquivalentHWInstr(const MachineInstr &MI) const;
436  unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData,
437  const MachineInstr &MI) const;
439  unsigned getInvertedPredicatedOpcode(const int Opc) const;
440  int getMaxValue(const MachineInstr &MI) const;
441  unsigned getMemAccessSize(const MachineInstr &MI) const;
442  int getMinValue(const MachineInstr &MI) const;
443  short getNonExtOpcode(const MachineInstr &MI) const;
444  bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg,
445  unsigned &PredRegPos, unsigned &PredRegFlags) const;
446  short getPseudoInstrPair(const MachineInstr &MI) const;
447  short getRegForm(const MachineInstr &MI) const;
448  unsigned getSize(const MachineInstr &MI) const;
449  uint64_t getType(const MachineInstr &MI) const;
450  unsigned getUnits(const MachineInstr &MI) const;
451 
452  /// getInstrTimingClassLatency - Compute the instruction latency of a given
453  /// instruction using Timing Class information, if available.
454  unsigned nonDbgBBSize(const MachineBasicBlock *BB) const;
455  unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const;
456 
457  void immediateExtend(MachineInstr &MI) const;
459  MachineBasicBlock* NewTarget) const;
461  bool reversePredSense(MachineInstr &MI) const;
462  unsigned reversePrediction(unsigned Opcode) const;
463  bool validateBranchCond(const ArrayRef<MachineOperand> &Cond) const;
464 
465  // Addressing mode relations.
466  short changeAddrMode_abs_io(short Opc) const;
467  short changeAddrMode_io_abs(short Opc) const;
468  short changeAddrMode_io_rr(short Opc) const;
469  short changeAddrMode_rr_io(short Opc) const;
470  short changeAddrMode_rr_ur(short Opc) const;
471  short changeAddrMode_ur_rr(short Opc) const;
472 
473  short changeAddrMode_abs_io(const MachineInstr &MI) const {
474  return changeAddrMode_abs_io(MI.getOpcode());
475  }
476  short changeAddrMode_io_abs(const MachineInstr &MI) const {
477  return changeAddrMode_io_abs(MI.getOpcode());
478  }
479  short changeAddrMode_io_rr(const MachineInstr &MI) const {
480  return changeAddrMode_io_rr(MI.getOpcode());
481  }
482  short changeAddrMode_rr_io(const MachineInstr &MI) const {
483  return changeAddrMode_rr_io(MI.getOpcode());
484  }
485  short changeAddrMode_rr_ur(const MachineInstr &MI) const {
486  return changeAddrMode_rr_ur(MI.getOpcode());
487  }
488  short changeAddrMode_ur_rr(const MachineInstr &MI) const {
489  return changeAddrMode_ur_rr(MI.getOpcode());
490  }
491 };
492 
493 } // end namespace llvm
494 
495 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
short getNonExtOpcode(const MachineInstr &MI) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Return an array that contains the direct target flag values and their names.
bool isVecALU(const MachineInstr &MI) const
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
If the specified instruction defines any predicate or condition code register(s) used for predication...
short changeAddrMode_io_rr(const MachineInstr &MI) const
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:843
short changeAddrMode_rr_io(short Opc) const
unsigned nonDbgBBSize(const MachineBasicBlock *BB) const
getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Clas...
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
short changeAddrMode_io_abs(const MachineInstr &MI) const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index...
short getEquivalentHWInstr(const MachineInstr &MI) const
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override
Create machine specific model for scheduling.
bool isAbsoluteSet(const MachineInstr &MI) const
bool isJumpR(const MachineInstr &MI) const
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
Returns true if the first specified predicate subsumes the second, e.g.
bool isConstExtended(const MachineInstr &MI) const
bool getInvertedPredSense(SmallVectorImpl< MachineOperand > &Cond) const
unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Reverses the branch condition of the specified condition list, returning false on success and true if...
int getMaxValue(const MachineInstr &MI) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
bool reversePredSense(MachineInstr &MI) const
int getDotNewPredOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
bool isExpr(unsigned OpType) const
bool isTailCall(const MachineInstr &MI) const override
A debug info location.
Definition: DebugLoc.h:34
unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr *> &PrevInsts, unsigned Iter, unsigned MaxIter) const override
Generate code to reduce the loop iteration by one and check if the loop is finished.
bool producesStall(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
unsigned getMemAccessSize(const MachineInstr &MI) const
unsigned getSize(const MachineInstr &MI) const
int getDotCurOp(const MachineInstr &MI) const
bool isLateResultInstr(const MachineInstr &MI) const
void immediateExtend(MachineInstr &MI) const
immediateExtend - Changes the instruction in place to one using an immediate extender.
int getDotNewPredJumpOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
short changeAddrMode_ur_rr(short Opc) const
bool isToBeScheduledASAP(const MachineInstr &MI1, const MachineInstr &MI2) const
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert a noop into the instruction stream at the specified point.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e...
bool isHVXVec(const MachineInstr &MI) const
bool isComplex(const MachineInstr &MI) const
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index...
unsigned getInvertedPredicatedOpcode(const int Opc) const
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
short changeAddrMode_abs_io(const MachineInstr &MI) const
unsigned getCompoundOpcode(const MachineInstr &GA, const MachineInstr &GB) const
bool isPredicatedNew(const MachineInstr &MI) const
bool canExecuteInBundle(const MachineInstr &First, const MachineInstr &Second) const
Can these instructions execute at the same time in a bundle.
bool predOpcodeHasNot(ArrayRef< MachineOperand > Cond) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
bool isVecUsableNextPacket(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
bool isDotNewInst(const MachineInstr &MI) const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
bool isDeallocRet(const MachineInstr &MI) const
bool isExtended(const MachineInstr &MI) const
bool isSolo(const MachineInstr &MI) const
bool isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI, const MachineInstr &ESMI) const
bool expandPostRAPseudo(MachineInstr &MI) const override
This function is called for all pseudo instructions that remain after register allocation.
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Cond) const override
Convert the instruction into a predicated instruction.
bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const
SmallVector< MachineInstr *, 2 > getBranchingInstrs(MachineBasicBlock &MBB) const
bool doesNotReturn(const MachineInstr &CallMI) const
bool isEndLoopN(unsigned Opcode) const
unsigned getBaseAndOffset(const MachineInstr &MI, int &Offset, unsigned &AccessSize) const
bool isCompoundBranchInstr(const MachineInstr &MI) const
short changeAddrMode_io_rr(short Opc) const
bool isPredictedTaken(unsigned Opcode) const
int getMinValue(const MachineInstr &MI) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
Itinerary data supplied by a subtarget to be used by a target.
bool isTC1(const MachineInstr &MI) const
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Compute the instruction latency of a given instruction.
short changeAddrMode_rr_ur(short Opc) const
bool getPredReg(ArrayRef< MachineOperand > Cond, unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const
unsigned getCExtOpNum(const MachineInstr &MI) const
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Return true if it&#39;s profitable for if-converter to duplicate instructions of specified accumulated in...
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Machine Value Type.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
bool getIncrementValue(const MachineInstr &MI, int &Value) const override
If the instruction is an increment of a constant value, return the amount.
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
bool validateBranchCond(const ArrayRef< MachineOperand > &Cond) const
MachineInstrBuilder & UseMI
bool isPredicable(const MachineInstr &MI) const override
Return true if the specified instruction can be predicated.
bool isAccumulator(const MachineInstr &MI) const
bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const override
For instructions with a base and offset, return the position of the base register and offset operands...
bool isZeroExtendingLoad(const MachineInstr &MI) const
short changeAddrMode_io_abs(short Opc) const
bool hasUncondBranch(const MachineBasicBlock *B) const
short changeAddrMode_abs_io(short Opc) const
unsigned getAddrMode(const MachineInstr &MI) const
int getNonDotCurOp(const MachineInstr &MI) const
bool invertAndChangeJumpTarget(MachineInstr &MI, MachineBasicBlock *NewTarget) const
bool isTC2Early(const MachineInstr &MI) const
bool isValidAutoIncImm(const EVT VT, const int Offset) const
bool isFloat(const MachineInstr &MI) const
HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI) const
void genAllInsnTimingClasses(MachineFunction &MF) const
Extended Value Type.
Definition: ValueTypes.h:34
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
short getPseudoInstrPair(const MachineInstr &MI) const
bool isEarlySourceInstr(const MachineInstr &MI) const
bool isPostIncrement(const MachineInstr &MI) const override
Return true for post-incremented instructions.
bool isExtendable(const MachineInstr &MI) const
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
bool hasPseudoInstrPair(const MachineInstr &MI) const
bool isIndirectCall(const MachineInstr &MI) const
bool isTC4x(const MachineInstr &MI) const
bool isDotCurInst(const MachineInstr &MI) const
Iterator for intrusive lists based on ilist_node.
bool isNewValueStore(const MachineInstr &MI) const
HexagonInstrInfo(HexagonSubtarget &ST)
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Decompose the machine operand&#39;s target flags into two values - the direct target flag value and any o...
bool isNewValueInst(const MachineInstr &MI) const
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:864
bool isVecAcc(const MachineInstr &MI) const
short changeAddrMode_ur_rr(const MachineInstr &MI) const
MachineInstrBuilder MachineInstrBuilder & DefMI
bool hasEHLabel(const MachineBasicBlock *B) const
bool isJumpWithinBranchRange(const MachineInstr &MI, unsigned offset) const
unsigned getUnits(const MachineInstr &MI) const
short getRegForm(const MachineInstr &MI) const
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
uint64_t getType(const MachineInstr &MI) const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Insert branch code into the end of the specified MachineBasicBlock.
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Return true if it&#39;s profitable to predicate instructions with accumulated instruction latency of "Num...
bool isSignExtendingLoad(const MachineInstr &MI) const
bool isOperandExtended(const MachineInstr &MI, unsigned OperandNum) const
unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI) const override
Measure the specified inline asm to determine an approximation of its length.
bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const
Symmetrical. See if these two instructions are fit for duplex pair.
bool isLateSourceInstr(const MachineInstr &MI) const
bool isSpillPredRegOp(const MachineInstr &MI) const
unsigned createVR(MachineFunction *MF, MVT VT) const
HexagonInstrInfo specifics.
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Test if the given instruction should be considered a scheduling boundary.
unsigned reversePrediction(unsigned Opcode) const
bool isNewValue(const MachineInstr &MI) const
bool isSaveCalleeSavedRegsCall(const MachineInstr &MI) const
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Remove the branching code at the end of the specific MBB.
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
TargetInstrInfo overrides.
int getDotNewOp(const MachineInstr &MI) const
int getCondOpcode(int Opc, bool sense) const
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
Emit instructions to copy a pair of physical registers.
TargetSubtargetInfo - Generic base class for all target subtargets.
bool isPredicateLate(unsigned Opcode) const
Representation of each machine instruction.
Definition: MachineInstr.h:59
bool addLatencyToSchedule(const MachineInstr &MI1, const MachineInstr &MI2) const
bool isDependent(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
int getDotOldOp(const MachineInstr &MI) const
MachineInstr * getFirstNonDbgInst(MachineBasicBlock *BB) const
bool isValidOffset(unsigned Opcode, int Offset, const TargetRegisterInfo *TRI, bool Extend=true) const
bool mayBeNewStore(const MachineInstr &MI) const
#define I(x, y, z)
Definition: MD5.cpp:58
bool isPredicatedTrue(const MachineInstr &MI) const
bool isNewValueJump(const MachineInstr &MI) const
bool hasNonExtEquivalent(const MachineInstr &MI) const
unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData, const MachineInstr &MI) const
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
getOperandLatency - Compute and return the use operand latency of a given pair of def and use...
bool isTC2(const MachineInstr &MI) const
bool isLoopN(const MachineInstr &MI) const
bool isHVXMemWithAIndirect(const MachineInstr &I, const MachineInstr &J) const
LLVM Value Representation.
Definition: Value.h:73
bool PredOpcodeHasJMP_c(unsigned Opcode) const
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
bool mayBeCurLoad(const MachineInstr &MI) const
IRTranslator LLVM IR MI
bool isMemOp(const MachineInstr &MI) const
short changeAddrMode_rr_io(const MachineInstr &MI) const
short changeAddrMode_rr_ur(const MachineInstr &MI) const
bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const override
Get the base register and byte offset of a load/store instr.
bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst, MachineInstr *&CmpInst) const override
Analyze the loop code, return true if it cannot be understood.
bool isIndirectL4Return(const MachineInstr &MI) const
bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
HexagonII::CompoundGroup getCompoundCandidateGroup(const MachineInstr &MI) const