LLVM  8.0.0svn
SystemZFrameLowering.cpp
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1 //===-- SystemZFrameLowering.cpp - Frame lowering for SystemZ -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "SystemZFrameLowering.h"
11 #include "SystemZCallingConv.h"
12 #include "SystemZInstrBuilder.h"
13 #include "SystemZInstrInfo.h"
15 #include "SystemZRegisterInfo.h"
16 #include "SystemZSubtarget.h"
20 #include "llvm/IR/Function.h"
21 
22 using namespace llvm;
23 
24 namespace {
25 // The ABI-defined register save slots, relative to the incoming stack
26 // pointer.
27 static const TargetFrameLowering::SpillSlot SpillOffsetTable[] = {
28  { SystemZ::R2D, 0x10 },
29  { SystemZ::R3D, 0x18 },
30  { SystemZ::R4D, 0x20 },
31  { SystemZ::R5D, 0x28 },
32  { SystemZ::R6D, 0x30 },
33  { SystemZ::R7D, 0x38 },
34  { SystemZ::R8D, 0x40 },
35  { SystemZ::R9D, 0x48 },
36  { SystemZ::R10D, 0x50 },
37  { SystemZ::R11D, 0x58 },
38  { SystemZ::R12D, 0x60 },
39  { SystemZ::R13D, 0x68 },
40  { SystemZ::R14D, 0x70 },
41  { SystemZ::R15D, 0x78 },
42  { SystemZ::F0D, 0x80 },
43  { SystemZ::F2D, 0x88 },
44  { SystemZ::F4D, 0x90 },
45  { SystemZ::F6D, 0x98 }
46 };
47 } // end anonymous namespace
48 
50  : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 8,
51  -SystemZMC::CallFrameSize, 8,
52  false /* StackRealignable */) {
53  // Create a mapping from register number to save slot offset.
54  RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS);
55  for (unsigned I = 0, E = array_lengthof(SpillOffsetTable); I != E; ++I)
56  RegSpillOffsets[SpillOffsetTable[I].Reg] = SpillOffsetTable[I].Offset;
57 }
58 
61  NumEntries = array_lengthof(SpillOffsetTable);
62  return SpillOffsetTable;
63 }
64 
66  BitVector &SavedRegs,
67  RegScavenger *RS) const {
69 
70  MachineFrameInfo &MFFrame = MF.getFrameInfo();
72  bool HasFP = hasFP(MF);
74  bool IsVarArg = MF.getFunction().isVarArg();
75 
76  // va_start stores incoming FPR varargs in the normal way, but delegates
77  // the saving of incoming GPR varargs to spillCalleeSavedRegisters().
78  // Record these pending uses, which typically include the call-saved
79  // argument register R6D.
80  if (IsVarArg)
81  for (unsigned I = MFI->getVarArgsFirstGPR(); I < SystemZ::NumArgGPRs; ++I)
82  SavedRegs.set(SystemZ::ArgGPRs[I]);
83 
84  // If there are any landing pads, entering them will modify r6/r7.
85  if (!MF.getLandingPads().empty()) {
86  SavedRegs.set(SystemZ::R6D);
87  SavedRegs.set(SystemZ::R7D);
88  }
89 
90  // If the function requires a frame pointer, record that the hard
91  // frame pointer will be clobbered.
92  if (HasFP)
93  SavedRegs.set(SystemZ::R11D);
94 
95  // If the function calls other functions, record that the return
96  // address register will be clobbered.
97  if (MFFrame.hasCalls())
98  SavedRegs.set(SystemZ::R14D);
99 
100  // If we are saving GPRs other than the stack pointer, we might as well
101  // save and restore the stack pointer at the same time, via STMG and LMG.
102  // This allows the deallocation to be done by the LMG, rather than needing
103  // a separate %r15 addition.
104  const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
105  for (unsigned I = 0; CSRegs[I]; ++I) {
106  unsigned Reg = CSRegs[I];
107  if (SystemZ::GR64BitRegClass.contains(Reg) && SavedRegs.test(Reg)) {
108  SavedRegs.set(SystemZ::R15D);
109  break;
110  }
111  }
112 }
113 
114 // Add GPR64 to the save instruction being built by MIB, which is in basic
115 // block MBB. IsImplicit says whether this is an explicit operand to the
116 // instruction, or an implicit one that comes between the explicit start
117 // and end registers.
119  unsigned GPR64, bool IsImplicit) {
120  const TargetRegisterInfo *RI =
122  unsigned GPR32 = RI->getSubReg(GPR64, SystemZ::subreg_l32);
123  bool IsLive = MBB.isLiveIn(GPR64) || MBB.isLiveIn(GPR32);
124  if (!IsLive || !IsImplicit) {
125  MIB.addReg(GPR64, getImplRegState(IsImplicit) | getKillRegState(!IsLive));
126  if (!IsLive)
127  MBB.addLiveIn(GPR64);
128  }
129 }
130 
134  const std::vector<CalleeSavedInfo> &CSI,
135  const TargetRegisterInfo *TRI) const {
136  if (CSI.empty())
137  return false;
138 
139  MachineFunction &MF = *MBB.getParent();
142  bool IsVarArg = MF.getFunction().isVarArg();
143  DebugLoc DL;
144 
145  // Scan the call-saved GPRs and find the bounds of the register spill area.
146  unsigned LowGPR = 0;
147  unsigned HighGPR = SystemZ::R15D;
148  unsigned StartOffset = -1U;
149  for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
150  unsigned Reg = CSI[I].getReg();
151  if (SystemZ::GR64BitRegClass.contains(Reg)) {
152  unsigned Offset = RegSpillOffsets[Reg];
153  assert(Offset && "Unexpected GPR save");
154  if (StartOffset > Offset) {
155  LowGPR = Reg;
156  StartOffset = Offset;
157  }
158  }
159  }
160 
161  // Save the range of call-saved registers, for use by the epilogue inserter.
162  ZFI->setLowSavedGPR(LowGPR);
163  ZFI->setHighSavedGPR(HighGPR);
164 
165  // Include the GPR varargs, if any. R6D is call-saved, so would
166  // be included by the loop above, but we also need to handle the
167  // call-clobbered argument registers.
168  if (IsVarArg) {
169  unsigned FirstGPR = ZFI->getVarArgsFirstGPR();
170  if (FirstGPR < SystemZ::NumArgGPRs) {
171  unsigned Reg = SystemZ::ArgGPRs[FirstGPR];
172  unsigned Offset = RegSpillOffsets[Reg];
173  if (StartOffset > Offset) {
174  LowGPR = Reg; StartOffset = Offset;
175  }
176  }
177  }
178 
179  // Save GPRs
180  if (LowGPR) {
181  assert(LowGPR != HighGPR && "Should be saving %r15 and something else");
182 
183  // Build an STMG instruction.
184  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG));
185 
186  // Add the explicit register operands.
187  addSavedGPR(MBB, MIB, LowGPR, false);
188  addSavedGPR(MBB, MIB, HighGPR, false);
189 
190  // Add the address.
191  MIB.addReg(SystemZ::R15D).addImm(StartOffset);
192 
193  // Make sure all call-saved GPRs are included as operands and are
194  // marked as live on entry.
195  for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
196  unsigned Reg = CSI[I].getReg();
197  if (SystemZ::GR64BitRegClass.contains(Reg))
198  addSavedGPR(MBB, MIB, Reg, true);
199  }
200 
201  // ...likewise GPR varargs.
202  if (IsVarArg)
203  for (unsigned I = ZFI->getVarArgsFirstGPR(); I < SystemZ::NumArgGPRs; ++I)
204  addSavedGPR(MBB, MIB, SystemZ::ArgGPRs[I], true);
205  }
206 
207  // Save FPRs/VRs in the normal TargetInstrInfo way.
208  for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
209  unsigned Reg = CSI[I].getReg();
210  if (SystemZ::FP64BitRegClass.contains(Reg)) {
211  MBB.addLiveIn(Reg);
212  TII->storeRegToStackSlot(MBB, MBBI, Reg, true, CSI[I].getFrameIdx(),
213  &SystemZ::FP64BitRegClass, TRI);
214  }
215  if (SystemZ::VR128BitRegClass.contains(Reg)) {
216  MBB.addLiveIn(Reg);
217  TII->storeRegToStackSlot(MBB, MBBI, Reg, true, CSI[I].getFrameIdx(),
218  &SystemZ::VR128BitRegClass, TRI);
219  }
220  }
221 
222  return true;
223 }
224 
228  std::vector<CalleeSavedInfo> &CSI,
229  const TargetRegisterInfo *TRI) const {
230  if (CSI.empty())
231  return false;
232 
233  MachineFunction &MF = *MBB.getParent();
236  bool HasFP = hasFP(MF);
237  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
238 
239  // Restore FPRs/VRs in the normal TargetInstrInfo way.
240  for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
241  unsigned Reg = CSI[I].getReg();
242  if (SystemZ::FP64BitRegClass.contains(Reg))
243  TII->loadRegFromStackSlot(MBB, MBBI, Reg, CSI[I].getFrameIdx(),
244  &SystemZ::FP64BitRegClass, TRI);
245  if (SystemZ::VR128BitRegClass.contains(Reg))
246  TII->loadRegFromStackSlot(MBB, MBBI, Reg, CSI[I].getFrameIdx(),
247  &SystemZ::VR128BitRegClass, TRI);
248  }
249 
250  // Restore call-saved GPRs (but not call-clobbered varargs, which at
251  // this point might hold return values).
252  unsigned LowGPR = ZFI->getLowSavedGPR();
253  unsigned HighGPR = ZFI->getHighSavedGPR();
254  unsigned StartOffset = RegSpillOffsets[LowGPR];
255  if (LowGPR) {
256  // If we saved any of %r2-%r5 as varargs, we should also be saving
257  // and restoring %r6. If we're saving %r6 or above, we should be
258  // restoring it too.
259  assert(LowGPR != HighGPR && "Should be loading %r15 and something else");
260 
261  // Build an LMG instruction.
262  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::LMG));
263 
264  // Add the explicit register operands.
265  MIB.addReg(LowGPR, RegState::Define);
266  MIB.addReg(HighGPR, RegState::Define);
267 
268  // Add the address.
269  MIB.addReg(HasFP ? SystemZ::R11D : SystemZ::R15D);
270  MIB.addImm(StartOffset);
271 
272  // Do a second scan adding regs as being defined by instruction
273  for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
274  unsigned Reg = CSI[I].getReg();
275  if (Reg != LowGPR && Reg != HighGPR &&
276  SystemZ::GR64BitRegClass.contains(Reg))
278  }
279  }
280 
281  return true;
282 }
283 
286  RegScavenger *RS) const {
287  MachineFrameInfo &MFFrame = MF.getFrameInfo();
288  // Get the size of our stack frame to be allocated ...
289  uint64_t StackSize = (MFFrame.estimateStackSize(MF) +
291  // ... and the maximum offset we may need to reach into the
292  // caller's frame to access the save area or stack arguments.
293  int64_t MaxArgOffset = SystemZMC::CallFrameSize;
294  for (int I = MFFrame.getObjectIndexBegin(); I != 0; ++I)
295  if (MFFrame.getObjectOffset(I) >= 0) {
296  int64_t ArgOffset = SystemZMC::CallFrameSize +
297  MFFrame.getObjectOffset(I) +
298  MFFrame.getObjectSize(I);
299  MaxArgOffset = std::max(MaxArgOffset, ArgOffset);
300  }
301 
302  uint64_t MaxReach = StackSize + MaxArgOffset;
303  if (!isUInt<12>(MaxReach)) {
304  // We may need register scavenging slots if some parts of the frame
305  // are outside the reach of an unsigned 12-bit displacement.
306  // Create 2 for the case where both addresses in an MVC are
307  // out of range.
308  RS->addScavengingFrameIndex(MFFrame.CreateStackObject(8, 8, false));
309  RS->addScavengingFrameIndex(MFFrame.CreateStackObject(8, 8, false));
310  }
311 }
312 
313 // Emit instructions before MBBI (in MBB) to add NumBytes to Reg.
316  const DebugLoc &DL,
317  unsigned Reg, int64_t NumBytes,
318  const TargetInstrInfo *TII) {
319  while (NumBytes) {
320  unsigned Opcode;
321  int64_t ThisVal = NumBytes;
322  if (isInt<16>(NumBytes))
323  Opcode = SystemZ::AGHI;
324  else {
325  Opcode = SystemZ::AGFI;
326  // Make sure we maintain 8-byte stack alignment.
327  int64_t MinVal = -uint64_t(1) << 31;
328  int64_t MaxVal = (int64_t(1) << 31) - 8;
329  if (ThisVal < MinVal)
330  ThisVal = MinVal;
331  else if (ThisVal > MaxVal)
332  ThisVal = MaxVal;
333  }
334  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII->get(Opcode), Reg)
335  .addReg(Reg).addImm(ThisVal);
336  // The CC implicit def is dead.
337  MI->getOperand(3).setIsDead();
338  NumBytes -= ThisVal;
339  }
340 }
341 
343  MachineBasicBlock &MBB) const {
344  assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
345  MachineFrameInfo &MFFrame = MF.getFrameInfo();
346  auto *ZII =
347  static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
349  MachineBasicBlock::iterator MBBI = MBB.begin();
350  MachineModuleInfo &MMI = MF.getMMI();
351  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
352  const std::vector<CalleeSavedInfo> &CSI = MFFrame.getCalleeSavedInfo();
353  bool HasFP = hasFP(MF);
354 
355  // Debug location must be unknown since the first debug location is used
356  // to determine the end of the prologue.
357  DebugLoc DL;
358 
359  // The current offset of the stack pointer from the CFA.
360  int64_t SPOffsetFromCFA = -SystemZMC::CFAOffsetFromInitialSP;
361 
362  if (ZFI->getLowSavedGPR()) {
363  // Skip over the GPR saves.
364  if (MBBI != MBB.end() && MBBI->getOpcode() == SystemZ::STMG)
365  ++MBBI;
366  else
367  llvm_unreachable("Couldn't skip over GPR saves");
368 
369  // Add CFI for the GPR saves.
370  for (auto &Save : CSI) {
371  unsigned Reg = Save.getReg();
372  if (SystemZ::GR64BitRegClass.contains(Reg)) {
373  int64_t Offset = SPOffsetFromCFA + RegSpillOffsets[Reg];
374  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
375  nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
376  BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
377  .addCFIIndex(CFIIndex);
378  }
379  }
380  }
381 
382  uint64_t StackSize = MFFrame.getStackSize();
383  // We need to allocate the ABI-defined 160-byte base area whenever
384  // we allocate stack space for our own use and whenever we call another
385  // function.
386  if (StackSize || MFFrame.hasVarSizedObjects() || MFFrame.hasCalls()) {
387  StackSize += SystemZMC::CallFrameSize;
388  MFFrame.setStackSize(StackSize);
389  }
390 
391  if (StackSize) {
392  // Determine if we want to store a backchain.
393  bool StoreBackchain = MF.getFunction().hasFnAttribute("backchain");
394 
395  // If we need backchain, save current stack pointer. R1 is free at this
396  // point.
397  if (StoreBackchain)
398  BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR))
399  .addReg(SystemZ::R1D, RegState::Define).addReg(SystemZ::R15D);
400 
401  // Allocate StackSize bytes.
402  int64_t Delta = -int64_t(StackSize);
403  emitIncrement(MBB, MBBI, DL, SystemZ::R15D, Delta, ZII);
404 
405  // Add CFI for the allocation.
406  unsigned CFIIndex = MF.addFrameInst(
407  MCCFIInstruction::createDefCfaOffset(nullptr, SPOffsetFromCFA + Delta));
408  BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
409  .addCFIIndex(CFIIndex);
410  SPOffsetFromCFA += Delta;
411 
412  if (StoreBackchain)
413  BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::STG))
414  .addReg(SystemZ::R1D, RegState::Kill).addReg(SystemZ::R15D).addImm(0).addReg(0);
415  }
416 
417  if (HasFP) {
418  // Copy the base of the frame to R11.
419  BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR), SystemZ::R11D)
420  .addReg(SystemZ::R15D);
421 
422  // Add CFI for the new frame location.
423  unsigned HardFP = MRI->getDwarfRegNum(SystemZ::R11D, true);
424  unsigned CFIIndex = MF.addFrameInst(
425  MCCFIInstruction::createDefCfaRegister(nullptr, HardFP));
426  BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
427  .addCFIIndex(CFIIndex);
428 
429  // Mark the FramePtr as live at the beginning of every block except
430  // the entry block. (We'll have marked R11 as live on entry when
431  // saving the GPRs.)
432  for (auto I = std::next(MF.begin()), E = MF.end(); I != E; ++I)
433  I->addLiveIn(SystemZ::R11D);
434  }
435 
436  // Skip over the FPR/VR saves.
437  SmallVector<unsigned, 8> CFIIndexes;
438  for (auto &Save : CSI) {
439  unsigned Reg = Save.getReg();
440  if (SystemZ::FP64BitRegClass.contains(Reg)) {
441  if (MBBI != MBB.end() &&
442  (MBBI->getOpcode() == SystemZ::STD ||
443  MBBI->getOpcode() == SystemZ::STDY))
444  ++MBBI;
445  else
446  llvm_unreachable("Couldn't skip over FPR save");
447  } else if (SystemZ::VR128BitRegClass.contains(Reg)) {
448  if (MBBI != MBB.end() &&
449  MBBI->getOpcode() == SystemZ::VST)
450  ++MBBI;
451  else
452  llvm_unreachable("Couldn't skip over VR save");
453  } else
454  continue;
455 
456  // Add CFI for the this save.
457  unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
458  unsigned IgnoredFrameReg;
459  int64_t Offset =
460  getFrameIndexReference(MF, Save.getFrameIdx(), IgnoredFrameReg);
461 
462  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
463  nullptr, DwarfReg, SPOffsetFromCFA + Offset));
464  CFIIndexes.push_back(CFIIndex);
465  }
466  // Complete the CFI for the FPR/VR saves, modelling them as taking effect
467  // after the last save.
468  for (auto CFIIndex : CFIIndexes) {
469  BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
470  .addCFIIndex(CFIIndex);
471  }
472 }
473 
475  MachineBasicBlock &MBB) const {
477  auto *ZII =
478  static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
480  MachineFrameInfo &MFFrame = MF.getFrameInfo();
481 
482  // Skip the return instruction.
483  assert(MBBI->isReturn() && "Can only insert epilogue into returning blocks");
484 
485  uint64_t StackSize = MFFrame.getStackSize();
486  if (ZFI->getLowSavedGPR()) {
487  --MBBI;
488  unsigned Opcode = MBBI->getOpcode();
489  if (Opcode != SystemZ::LMG)
490  llvm_unreachable("Expected to see callee-save register restore code");
491 
492  unsigned AddrOpNo = 2;
493  DebugLoc DL = MBBI->getDebugLoc();
494  uint64_t Offset = StackSize + MBBI->getOperand(AddrOpNo + 1).getImm();
495  unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
496 
497  // If the offset is too large, use the largest stack-aligned offset
498  // and add the rest to the base register (the stack or frame pointer).
499  if (!NewOpcode) {
500  uint64_t NumBytes = Offset - 0x7fff8;
501  emitIncrement(MBB, MBBI, DL, MBBI->getOperand(AddrOpNo).getReg(),
502  NumBytes, ZII);
503  Offset -= NumBytes;
504  NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
505  assert(NewOpcode && "No restore instruction available");
506  }
507 
508  MBBI->setDesc(ZII->get(NewOpcode));
509  MBBI->getOperand(AddrOpNo + 1).ChangeToImmediate(Offset);
510  } else if (StackSize) {
511  DebugLoc DL = MBBI->getDebugLoc();
512  emitIncrement(MBB, MBBI, DL, SystemZ::R15D, StackSize, ZII);
513  }
514 }
515 
517  return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
519  MF.getInfo<SystemZMachineFunctionInfo>()->getManipulatesSP());
520 }
521 
522 bool
524  // The ABI requires us to allocate 160 bytes of stack space for the callee,
525  // with any outgoing stack arguments being placed above that. It seems
526  // better to make that area a permanent feature of the frame even if
527  // we're using a frame pointer.
528  return true;
529 }
530 
533  MachineBasicBlock &MBB,
535  switch (MI->getOpcode()) {
536  case SystemZ::ADJCALLSTACKDOWN:
537  case SystemZ::ADJCALLSTACKUP:
539  "ADJSTACKDOWN and ADJSTACKUP should be no-ops");
540  return MBB.erase(MI);
541  break;
542 
543  default:
544  llvm_unreachable("Unexpected call frame instruction");
545  }
546 }
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:177
void push_back(const T &Elt)
Definition: SmallVector.h:218
BitVector & set()
Definition: BitVector.h:398
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
const int64_t CallFrameSize
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
virtual int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const
getFrameIndexReference - This method should return the base register and offset used to reference a f...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
static void emitIncrement(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &DL, unsigned Reg, int64_t NumBytes, const TargetInstrInfo *TII)
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:487
unsigned Reg
bool test(unsigned Idx) const
Definition: BitVector.h:502
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:321
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:306
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
void setIsDead(bool Val=true)
const unsigned NumArgGPRs
MachineModuleInfo & getMMI() const
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBII, std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
static MCCFIInstruction createDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:474
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
return AArch64::GPR64RegClass contains(Reg)
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
const HexagonInstrInfo * TII
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
const MCContext & getContext() const
int getObjectIndexBegin() const
Return the minimum frame object index.
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
virtual const TargetInstrInfo * getInstrInfo() const
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
unsigned getKillRegState(bool B)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
TargetInstrInfo - Interface to description of machine instruction set.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata *> MDs)
Definition: Metadata.h:1166
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
This file declares the machine register scavenger class.
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
Definition: MCDwarf.h:467
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
const int64_t CFAOffsetFromInitialSP
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MachineBasicBlock & front() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const std::vector< LandingPadInfo > & getLandingPads() const
Return a reference to the landing pad info for the current function.
static void addSavedGPR(MachineBasicBlock &MBB, MachineInstrBuilder &MIB, unsigned GPR64, bool IsImplicit)
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
unsigned estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:906
Information about stack frame layout on the target.
const Function & getFunction() const
Return the LLVM function that this machine code represents.
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Store the specified register of the given register class to the specified stack frame index...
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
TargetOptions Options
Definition: TargetMachine.h:97
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned getImplRegState(bool B)
const SpillSlot * getCalleeSavedSpillSlots(unsigned &NumEntries) const override
getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs, that contains an entry...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
void grow(IndexT n)
Definition: IndexedMap.h:68
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:295
const MCPhysReg ArgGPRs[NumArgGPRs]
IRTranslator LLVM IR MI
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Load the specified register of the given register class from the specified stack frame index...
This class contains meta information specific to a module.
bool hasCalls() const
Return true if the current function has any function calls.