LLVM  8.0.0svn
HexagonFrameLowering.cpp
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1 //===- HexagonFrameLowering.cpp - Define frame lowering -------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //
9 //===----------------------------------------------------------------------===//
10 
11 #include "HexagonFrameLowering.h"
12 #include "HexagonBlockRanges.h"
13 #include "HexagonInstrInfo.h"
15 #include "HexagonRegisterInfo.h"
16 #include "HexagonSubtarget.h"
17 #include "HexagonTargetMachine.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/ADT/None.h"
22 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/SetVector.h"
25 #include "llvm/ADT/SmallSet.h"
26 #include "llvm/ADT/SmallVector.h"
42 #include "llvm/IR/Attributes.h"
43 #include "llvm/IR/DebugLoc.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/MC/MCDwarf.h"
46 #include "llvm/MC/MCRegisterInfo.h"
47 #include "llvm/Pass.h"
48 #include "llvm/Support/CodeGen.h"
50 #include "llvm/Support/Compiler.h"
51 #include "llvm/Support/Debug.h"
57 #include <algorithm>
58 #include <cassert>
59 #include <cstdint>
60 #include <iterator>
61 #include <limits>
62 #include <map>
63 #include <utility>
64 #include <vector>
65 
66 #define DEBUG_TYPE "hexagon-pei"
67 
68 // Hexagon stack frame layout as defined by the ABI:
69 //
70 // Incoming arguments
71 // passed via stack
72 // |
73 // |
74 // SP during function's FP during function's |
75 // +-- runtime (top of stack) runtime (bottom) --+ |
76 // | | |
77 // --++---------------------+------------------+-----------------++-+-------
78 // | parameter area for | variable-size | fixed-size |LR| arg
79 // | called functions | local objects | local objects |FP|
80 // --+----------------------+------------------+-----------------+--+-------
81 // <- size known -> <- size unknown -> <- size known ->
82 //
83 // Low address High address
84 //
85 // <--- stack growth
86 //
87 //
88 // - In any circumstances, the outgoing function arguments are always accessi-
89 // ble using the SP, and the incoming arguments are accessible using the FP.
90 // - If the local objects are not aligned, they can always be accessed using
91 // the FP.
92 // - If there are no variable-sized objects, the local objects can always be
93 // accessed using the SP, regardless whether they are aligned or not. (The
94 // alignment padding will be at the bottom of the stack (highest address),
95 // and so the offset with respect to the SP will be known at the compile-
96 // -time.)
97 //
98 // The only complication occurs if there are both, local aligned objects, and
99 // dynamically allocated (variable-sized) objects. The alignment pad will be
100 // placed between the FP and the local objects, thus preventing the use of the
101 // FP to access the local objects. At the same time, the variable-sized objects
102 // will be between the SP and the local objects, thus introducing an unknown
103 // distance from the SP to the locals.
104 //
105 // To avoid this problem, a new register is created that holds the aligned
106 // address of the bottom of the stack, referred in the sources as AP (aligned
107 // pointer). The AP will be equal to "FP-p", where "p" is the smallest pad
108 // that aligns AP to the required boundary (a maximum of the alignments of
109 // all stack objects, fixed- and variable-sized). All local objects[1] will
110 // then use AP as the base pointer.
111 // [1] The exception is with "fixed" stack objects. "Fixed" stack objects get
112 // their name from being allocated at fixed locations on the stack, relative
113 // to the FP. In the presence of dynamic allocation and local alignment, such
114 // objects can only be accessed through the FP.
115 //
116 // Illustration of the AP:
117 // FP --+
118 // |
119 // ---------------+---------------------+-----+-----------------------++-+--
120 // Rest of the | Local stack objects | Pad | Fixed stack objects |LR|
121 // stack frame | (aligned) | | (CSR, spills, etc.) |FP|
122 // ---------------+---------------------+-----+-----------------+-----+--+--
123 // |<-- Multiple of the -->|
124 // stack alignment +-- AP
125 //
126 // The AP is set up at the beginning of the function. Since it is not a dedi-
127 // cated (reserved) register, it needs to be kept live throughout the function
128 // to be available as the base register for local object accesses.
129 // Normally, an address of a stack objects is obtained by a pseudo-instruction
130 // PS_fi. To access local objects with the AP register present, a different
131 // pseudo-instruction needs to be used: PS_fia. The PS_fia takes one extra
132 // argument compared to PS_fi: the first input register is the AP register.
133 // This keeps the register live between its definition and its uses.
134 
135 // The AP register is originally set up using pseudo-instruction PS_aligna:
136 // AP = PS_aligna A
137 // where
138 // A - required stack alignment
139 // The alignment value must be the maximum of all alignments required by
140 // any stack object.
141 
142 // The dynamic allocation uses a pseudo-instruction PS_alloca:
143 // Rd = PS_alloca Rs, A
144 // where
145 // Rd - address of the allocated space
146 // Rs - minimum size (the actual allocated can be larger to accommodate
147 // alignment)
148 // A - required alignment
149 
150 using namespace llvm;
151 
152 static cl::opt<bool> DisableDeallocRet("disable-hexagon-dealloc-ret",
153  cl::Hidden, cl::desc("Disable Dealloc Return for Hexagon target"));
154 
155 static cl::opt<unsigned> NumberScavengerSlots("number-scavenger-slots",
156  cl::Hidden, cl::desc("Set the number of scavenger slots"), cl::init(2),
158 
159 static cl::opt<int> SpillFuncThreshold("spill-func-threshold",
160  cl::Hidden, cl::desc("Specify O2(not Os) spill func threshold"),
162 
163 static cl::opt<int> SpillFuncThresholdOs("spill-func-threshold-Os",
164  cl::Hidden, cl::desc("Specify Os spill func threshold"),
166 
167 static cl::opt<bool> EnableStackOVFSanitizer("enable-stackovf-sanitizer",
168  cl::Hidden, cl::desc("Enable runtime checks for stack overflow."),
169  cl::init(false), cl::ZeroOrMore);
170 
171 static cl::opt<bool> EnableShrinkWrapping("hexagon-shrink-frame",
173  cl::desc("Enable stack frame shrink wrapping"));
174 
175 static cl::opt<unsigned> ShrinkLimit("shrink-frame-limit",
177  cl::desc("Max count of stack frame shrink-wraps"));
178 
179 static cl::opt<bool> EnableSaveRestoreLong("enable-save-restore-long",
180  cl::Hidden, cl::desc("Enable long calls for save-restore stubs."),
181  cl::init(false), cl::ZeroOrMore);
182 
183 static cl::opt<bool> EliminateFramePointer("hexagon-fp-elim", cl::init(true),
184  cl::Hidden, cl::desc("Refrain from using FP whenever possible"));
185 
186 static cl::opt<bool> OptimizeSpillSlots("hexagon-opt-spill", cl::Hidden,
187  cl::init(true), cl::desc("Optimize spill slots"));
188 
189 #ifndef NDEBUG
190 static cl::opt<unsigned> SpillOptMax("spill-opt-max", cl::Hidden,
192 static unsigned SpillOptCount = 0;
193 #endif
194 
195 namespace llvm {
196 
199 
200 } // end namespace llvm
201 
202 namespace {
203 
204  class HexagonCallFrameInformation : public MachineFunctionPass {
205  public:
206  static char ID;
207 
208  HexagonCallFrameInformation() : MachineFunctionPass(ID) {
211  }
212 
213  bool runOnMachineFunction(MachineFunction &MF) override;
214 
215  MachineFunctionProperties getRequiredProperties() const override {
218  }
219  };
220 
222 
223 } // end anonymous namespace
224 
225 bool HexagonCallFrameInformation::runOnMachineFunction(MachineFunction &MF) {
226  auto &HFI = *MF.getSubtarget<HexagonSubtarget>().getFrameLowering();
227  bool NeedCFI = MF.getMMI().hasDebugInfo() ||
229 
230  if (!NeedCFI)
231  return false;
232  HFI.insertCFIInstructions(MF);
233  return true;
234 }
235 
236 INITIALIZE_PASS(HexagonCallFrameInformation, "hexagon-cfi",
237  "Hexagon call frame information", false, false)
238 
240  return new HexagonCallFrameInformation();
241 }
242 
243 /// Map a register pair Reg to the subregister that has the greater "number",
244 /// i.e. D3 (aka R7:6) will be mapped to R7, etc.
245 static unsigned getMax32BitSubRegister(unsigned Reg,
246  const TargetRegisterInfo &TRI,
247  bool hireg = true) {
248  if (Reg < Hexagon::D0 || Reg > Hexagon::D15)
249  return Reg;
250 
251  unsigned RegNo = 0;
252  for (MCSubRegIterator SubRegs(Reg, &TRI); SubRegs.isValid(); ++SubRegs) {
253  if (hireg) {
254  if (*SubRegs > RegNo)
255  RegNo = *SubRegs;
256  } else {
257  if (!RegNo || *SubRegs < RegNo)
258  RegNo = *SubRegs;
259  }
260  }
261  return RegNo;
262 }
263 
264 /// Returns the callee saved register with the largest id in the vector.
265 static unsigned getMaxCalleeSavedReg(const std::vector<CalleeSavedInfo> &CSI,
266  const TargetRegisterInfo &TRI) {
267  static_assert(Hexagon::R1 > 0,
268  "Assume physical registers are encoded as positive integers");
269  if (CSI.empty())
270  return 0;
271 
272  unsigned Max = getMax32BitSubRegister(CSI[0].getReg(), TRI);
273  for (unsigned I = 1, E = CSI.size(); I < E; ++I) {
274  unsigned Reg = getMax32BitSubRegister(CSI[I].getReg(), TRI);
275  if (Reg > Max)
276  Max = Reg;
277  }
278  return Max;
279 }
280 
281 /// Checks if the basic block contains any instruction that needs a stack
282 /// frame to be already in place.
283 static bool needsStackFrame(const MachineBasicBlock &MBB, const BitVector &CSR,
284  const HexagonRegisterInfo &HRI) {
285  for (auto &I : MBB) {
286  const MachineInstr *MI = &I;
287  if (MI->isCall())
288  return true;
289  unsigned Opc = MI->getOpcode();
290  switch (Opc) {
291  case Hexagon::PS_alloca:
292  case Hexagon::PS_aligna:
293  return true;
294  default:
295  break;
296  }
297  // Check individual operands.
298  for (const MachineOperand &MO : MI->operands()) {
299  // While the presence of a frame index does not prove that a stack
300  // frame will be required, all frame indexes should be within alloc-
301  // frame/deallocframe. Otherwise, the code that translates a frame
302  // index into an offset would have to be aware of the placement of
303  // the frame creation/destruction instructions.
304  if (MO.isFI())
305  return true;
306  if (MO.isReg()) {
307  unsigned R = MO.getReg();
308  // Virtual registers will need scavenging, which then may require
309  // a stack slot.
311  return true;
312  for (MCSubRegIterator S(R, &HRI, true); S.isValid(); ++S)
313  if (CSR[*S])
314  return true;
315  continue;
316  }
317  if (MO.isRegMask()) {
318  // A regmask would normally have all callee-saved registers marked
319  // as preserved, so this check would not be needed, but in case of
320  // ever having other regmasks (for other calling conventions),
321  // make sure they would be processed correctly.
322  const uint32_t *BM = MO.getRegMask();
323  for (int x = CSR.find_first(); x >= 0; x = CSR.find_next(x)) {
324  unsigned R = x;
325  // If this regmask does not preserve a CSR, a frame will be needed.
326  if (!(BM[R/32] & (1u << (R%32))))
327  return true;
328  }
329  }
330  }
331  }
332  return false;
333 }
334 
335  /// Returns true if MBB has a machine instructions that indicates a tail call
336  /// in the block.
337 static bool hasTailCall(const MachineBasicBlock &MBB) {
339  if (I == MBB.end())
340  return false;
341  unsigned RetOpc = I->getOpcode();
342  return RetOpc == Hexagon::PS_tailcall_i || RetOpc == Hexagon::PS_tailcall_r;
343 }
344 
345 /// Returns true if MBB contains an instruction that returns.
346 static bool hasReturn(const MachineBasicBlock &MBB) {
347  for (auto I = MBB.getFirstTerminator(), E = MBB.end(); I != E; ++I)
348  if (I->isReturn())
349  return true;
350  return false;
351 }
352 
353 /// Returns the "return" instruction from this block, or nullptr if there
354 /// isn't any.
356  for (auto &I : MBB)
357  if (I.isReturn())
358  return &I;
359  return nullptr;
360 }
361 
362 static bool isRestoreCall(unsigned Opc) {
363  switch (Opc) {
364  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
365  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
366  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT:
367  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC:
368  case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT:
369  case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC:
370  case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4:
371  case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC:
372  return true;
373  }
374  return false;
375 }
376 
377 static inline bool isOptNone(const MachineFunction &MF) {
378  return MF.getFunction().hasFnAttribute(Attribute::OptimizeNone) ||
380 }
381 
382 static inline bool isOptSize(const MachineFunction &MF) {
383  const Function &F = MF.getFunction();
384  return F.optForSize() && !F.optForMinSize();
385 }
386 
387 static inline bool isMinSize(const MachineFunction &MF) {
388  return MF.getFunction().optForMinSize();
389 }
390 
391 /// Implements shrink-wrapping of the stack frame. By default, stack frame
392 /// is created in the function entry block, and is cleaned up in every block
393 /// that returns. This function finds alternate blocks: one for the frame
394 /// setup (prolog) and one for the cleanup (epilog).
395 void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF,
396  MachineBasicBlock *&PrologB, MachineBasicBlock *&EpilogB) const {
397  static unsigned ShrinkCounter = 0;
398 
399  if (ShrinkLimit.getPosition()) {
400  if (ShrinkCounter >= ShrinkLimit)
401  return;
402  ShrinkCounter++;
403  }
404 
405  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
406 
408  MDT.runOnMachineFunction(MF);
410  MPT.runOnMachineFunction(MF);
411 
412  using UnsignedMap = DenseMap<unsigned, unsigned>;
414 
415  UnsignedMap RPO;
416  RPOTType RPOT(&MF);
417  unsigned RPON = 0;
418  for (RPOTType::rpo_iterator I = RPOT.begin(), E = RPOT.end(); I != E; ++I)
419  RPO[(*I)->getNumber()] = RPON++;
420 
421  // Don't process functions that have loops, at least for now. Placement
422  // of prolog and epilog must take loop structure into account. For simpli-
423  // city don't do it right now.
424  for (auto &I : MF) {
425  unsigned BN = RPO[I.getNumber()];
426  for (auto SI = I.succ_begin(), SE = I.succ_end(); SI != SE; ++SI) {
427  // If found a back-edge, return.
428  if (RPO[(*SI)->getNumber()] <= BN)
429  return;
430  }
431  }
432 
433  // Collect the set of blocks that need a stack frame to execute. Scan
434  // each block for uses/defs of callee-saved registers, calls, etc.
436  BitVector CSR(Hexagon::NUM_TARGET_REGS);
437  for (const MCPhysReg *P = HRI.getCalleeSavedRegs(&MF); *P; ++P)
438  for (MCSubRegIterator S(*P, &HRI, true); S.isValid(); ++S)
439  CSR[*S] = true;
440 
441  for (auto &I : MF)
442  if (needsStackFrame(I, CSR, HRI))
443  SFBlocks.push_back(&I);
444 
445  LLVM_DEBUG({
446  dbgs() << "Blocks needing SF: {";
447  for (auto &B : SFBlocks)
448  dbgs() << " " << printMBBReference(*B);
449  dbgs() << " }\n";
450  });
451  // No frame needed?
452  if (SFBlocks.empty())
453  return;
454 
455  // Pick a common dominator and a common post-dominator.
456  MachineBasicBlock *DomB = SFBlocks[0];
457  for (unsigned i = 1, n = SFBlocks.size(); i < n; ++i) {
458  DomB = MDT.findNearestCommonDominator(DomB, SFBlocks[i]);
459  if (!DomB)
460  break;
461  }
462  MachineBasicBlock *PDomB = SFBlocks[0];
463  for (unsigned i = 1, n = SFBlocks.size(); i < n; ++i) {
464  PDomB = MPT.findNearestCommonDominator(PDomB, SFBlocks[i]);
465  if (!PDomB)
466  break;
467  }
468  LLVM_DEBUG({
469  dbgs() << "Computed dom block: ";
470  if (DomB)
471  dbgs() << printMBBReference(*DomB);
472  else
473  dbgs() << "<null>";
474  dbgs() << ", computed pdom block: ";
475  if (PDomB)
476  dbgs() << printMBBReference(*PDomB);
477  else
478  dbgs() << "<null>";
479  dbgs() << "\n";
480  });
481  if (!DomB || !PDomB)
482  return;
483 
484  // Make sure that DomB dominates PDomB and PDomB post-dominates DomB.
485  if (!MDT.dominates(DomB, PDomB)) {
486  LLVM_DEBUG(dbgs() << "Dom block does not dominate pdom block\n");
487  return;
488  }
489  if (!MPT.dominates(PDomB, DomB)) {
490  LLVM_DEBUG(dbgs() << "PDom block does not post-dominate dom block\n");
491  return;
492  }
493 
494  // Finally, everything seems right.
495  PrologB = DomB;
496  EpilogB = PDomB;
497 }
498 
499 /// Perform most of the PEI work here:
500 /// - saving/restoring of the callee-saved registers,
501 /// - stack frame creation and destruction.
502 /// Normally, this work is distributed among various functions, but doing it
503 /// in one place allows shrink-wrapping of the stack frame.
505  MachineBasicBlock &MBB) const {
506  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
507 
508  MachineFrameInfo &MFI = MF.getFrameInfo();
509  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
510 
511  MachineBasicBlock *PrologB = &MF.front(), *EpilogB = nullptr;
513  findShrunkPrologEpilog(MF, PrologB, EpilogB);
514 
515  bool PrologueStubs = false;
516  insertCSRSpillsInBlock(*PrologB, CSI, HRI, PrologueStubs);
517  insertPrologueInBlock(*PrologB, PrologueStubs);
518  updateEntryPaths(MF, *PrologB);
519 
520  if (EpilogB) {
521  insertCSRRestoresInBlock(*EpilogB, CSI, HRI);
522  insertEpilogueInBlock(*EpilogB);
523  } else {
524  for (auto &B : MF)
525  if (B.isReturnBlock())
526  insertCSRRestoresInBlock(B, CSI, HRI);
527 
528  for (auto &B : MF)
529  if (B.isReturnBlock())
530  insertEpilogueInBlock(B);
531 
532  for (auto &B : MF) {
533  if (B.empty())
534  continue;
535  MachineInstr *RetI = getReturn(B);
536  if (!RetI || isRestoreCall(RetI->getOpcode()))
537  continue;
538  for (auto &R : CSI)
539  RetI->addOperand(MachineOperand::CreateReg(R.getReg(), false, true));
540  }
541  }
542 
543  if (EpilogB) {
544  // If there is an epilog block, it may not have a return instruction.
545  // In such case, we need to add the callee-saved registers as live-ins
546  // in all blocks on all paths from the epilog to any return block.
547  unsigned MaxBN = MF.getNumBlockIDs();
548  BitVector DoneT(MaxBN+1), DoneF(MaxBN+1), Path(MaxBN+1);
549  updateExitPaths(*EpilogB, *EpilogB, DoneT, DoneF, Path);
550  }
551 }
552 
553 void HexagonFrameLowering::insertPrologueInBlock(MachineBasicBlock &MBB,
554  bool PrologueStubs) const {
555  MachineFunction &MF = *MBB.getParent();
556  MachineFrameInfo &MFI = MF.getFrameInfo();
557  auto &HST = MF.getSubtarget<HexagonSubtarget>();
558  auto &HII = *HST.getInstrInfo();
559  auto &HRI = *HST.getRegisterInfo();
560 
561  unsigned MaxAlign = std::max(MFI.getMaxAlignment(), getStackAlignment());
562 
563  // Calculate the total stack frame size.
564  // Get the number of bytes to allocate from the FrameInfo.
565  unsigned FrameSize = MFI.getStackSize();
566  // Round up the max call frame size to the max alignment on the stack.
567  unsigned MaxCFA = alignTo(MFI.getMaxCallFrameSize(), MaxAlign);
568  MFI.setMaxCallFrameSize(MaxCFA);
569 
570  FrameSize = MaxCFA + alignTo(FrameSize, MaxAlign);
571  MFI.setStackSize(FrameSize);
572 
573  bool AlignStack = (MaxAlign > getStackAlignment());
574 
575  // Get the number of bytes to allocate from the FrameInfo.
576  unsigned NumBytes = MFI.getStackSize();
577  unsigned SP = HRI.getStackRegister();
578  unsigned MaxCF = MFI.getMaxCallFrameSize();
579  MachineBasicBlock::iterator InsertPt = MBB.begin();
580 
582  for (auto &MBB : MF)
583  for (auto &MI : MBB)
584  if (MI.getOpcode() == Hexagon::PS_alloca)
585  AdjustRegs.push_back(&MI);
586 
587  for (auto MI : AdjustRegs) {
588  assert((MI->getOpcode() == Hexagon::PS_alloca) && "Expected alloca");
589  expandAlloca(MI, HII, SP, MaxCF);
590  MI->eraseFromParent();
591  }
592 
593  DebugLoc dl = MBB.findDebugLoc(InsertPt);
594 
595  if (hasFP(MF)) {
596  insertAllocframe(MBB, InsertPt, NumBytes);
597  if (AlignStack) {
598  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_andir), SP)
599  .addReg(SP)
600  .addImm(-int64_t(MaxAlign));
601  }
602  // If the stack-checking is enabled, and we spilled the callee-saved
603  // registers inline (i.e. did not use a spill function), then call
604  // the stack checker directly.
605  if (EnableStackOVFSanitizer && !PrologueStubs)
606  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::PS_call_stk))
607  .addExternalSymbol("__runtime_stack_check");
608  } else if (NumBytes > 0) {
609  assert(alignTo(NumBytes, 8) == NumBytes);
610  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
611  .addReg(SP)
612  .addImm(-int(NumBytes));
613  }
614 }
615 
616 void HexagonFrameLowering::insertEpilogueInBlock(MachineBasicBlock &MBB) const {
617  MachineFunction &MF = *MBB.getParent();
618  auto &HST = MF.getSubtarget<HexagonSubtarget>();
619  auto &HII = *HST.getInstrInfo();
620  auto &HRI = *HST.getRegisterInfo();
621  unsigned SP = HRI.getStackRegister();
622 
624  DebugLoc dl = MBB.findDebugLoc(InsertPt);
625 
626  if (!hasFP(MF)) {
627  MachineFrameInfo &MFI = MF.getFrameInfo();
628  if (unsigned NumBytes = MFI.getStackSize()) {
629  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
630  .addReg(SP)
631  .addImm(NumBytes);
632  }
633  return;
634  }
635 
636  MachineInstr *RetI = getReturn(MBB);
637  unsigned RetOpc = RetI ? RetI->getOpcode() : 0;
638 
639  // Handle EH_RETURN.
640  if (RetOpc == Hexagon::EH_RETURN_JMPR) {
641  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe))
642  .addDef(Hexagon::D15)
643  .addReg(Hexagon::R30);
644  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_add), SP)
645  .addReg(SP)
646  .addReg(Hexagon::R28);
647  return;
648  }
649 
650  // Check for RESTORE_DEALLOC_RET* tail call. Don't emit an extra dealloc-
651  // frame instruction if we encounter it.
652  if (RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4 ||
653  RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC ||
654  RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT ||
655  RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC) {
656  MachineBasicBlock::iterator It = RetI;
657  ++It;
658  // Delete all instructions after the RESTORE (except labels).
659  while (It != MBB.end()) {
660  if (!It->isLabel())
661  It = MBB.erase(It);
662  else
663  ++It;
664  }
665  return;
666  }
667 
668  // It is possible that the restoring code is a call to a library function.
669  // All of the restore* functions include "deallocframe", so we need to make
670  // sure that we don't add an extra one.
671  bool NeedsDeallocframe = true;
672  if (!MBB.empty() && InsertPt != MBB.begin()) {
673  MachineBasicBlock::iterator PrevIt = std::prev(InsertPt);
674  unsigned COpc = PrevIt->getOpcode();
675  if (COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4 ||
676  COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC ||
677  COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT ||
678  COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC ||
679  COpc == Hexagon::PS_call_nr || COpc == Hexagon::PS_callr_nr)
680  NeedsDeallocframe = false;
681  }
682 
683  if (!NeedsDeallocframe)
684  return;
685  // If the returning instruction is PS_jmpret, replace it with dealloc_return,
686  // otherwise just add deallocframe. The function could be returning via a
687  // tail call.
688  if (RetOpc != Hexagon::PS_jmpret || DisableDeallocRet) {
689  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe))
690  .addDef(Hexagon::D15)
691  .addReg(Hexagon::R30);
692  return;
693  }
694  unsigned NewOpc = Hexagon::L4_return;
695  MachineInstr *NewI = BuildMI(MBB, RetI, dl, HII.get(NewOpc))
696  .addDef(Hexagon::D15)
697  .addReg(Hexagon::R30);
698  // Transfer the function live-out registers.
699  NewI->copyImplicitOps(MF, *RetI);
700  MBB.erase(RetI);
701 }
702 
703 void HexagonFrameLowering::insertAllocframe(MachineBasicBlock &MBB,
704  MachineBasicBlock::iterator InsertPt, unsigned NumBytes) const {
705  MachineFunction &MF = *MBB.getParent();
706  auto &HST = MF.getSubtarget<HexagonSubtarget>();
707  auto &HII = *HST.getInstrInfo();
708  auto &HRI = *HST.getRegisterInfo();
709 
710  // Check for overflow.
711  // Hexagon_TODO: Ugh! hardcoding. Is there an API that can be used?
712  const unsigned int ALLOCFRAME_MAX = 16384;
713 
714  // Create a dummy memory operand to avoid allocframe from being treated as
715  // a volatile memory reference.
718 
719  DebugLoc dl = MBB.findDebugLoc(InsertPt);
720  unsigned SP = HRI.getStackRegister();
721 
722  if (NumBytes >= ALLOCFRAME_MAX) {
723  // Emit allocframe(#0).
724  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))
725  .addDef(SP)
726  .addReg(SP)
727  .addImm(0)
728  .addMemOperand(MMO);
729 
730  // Subtract the size from the stack pointer.
731  unsigned SP = HRI.getStackRegister();
732  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
733  .addReg(SP)
734  .addImm(-int(NumBytes));
735  } else {
736  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))
737  .addDef(SP)
738  .addReg(SP)
739  .addImm(NumBytes)
740  .addMemOperand(MMO);
741  }
742 }
743 
744 void HexagonFrameLowering::updateEntryPaths(MachineFunction &MF,
745  MachineBasicBlock &SaveB) const {
746  SetVector<unsigned> Worklist;
747 
748  MachineBasicBlock &EntryB = MF.front();
749  Worklist.insert(EntryB.getNumber());
750 
751  unsigned SaveN = SaveB.getNumber();
752  auto &CSI = MF.getFrameInfo().getCalleeSavedInfo();
753 
754  for (unsigned i = 0; i < Worklist.size(); ++i) {
755  unsigned BN = Worklist[i];
756  MachineBasicBlock &MBB = *MF.getBlockNumbered(BN);
757  for (auto &R : CSI)
758  if (!MBB.isLiveIn(R.getReg()))
759  MBB.addLiveIn(R.getReg());
760  if (BN != SaveN)
761  for (auto &SB : MBB.successors())
762  Worklist.insert(SB->getNumber());
763  }
764 }
765 
766 bool HexagonFrameLowering::updateExitPaths(MachineBasicBlock &MBB,
767  MachineBasicBlock &RestoreB, BitVector &DoneT, BitVector &DoneF,
768  BitVector &Path) const {
769  assert(MBB.getNumber() >= 0);
770  unsigned BN = MBB.getNumber();
771  if (Path[BN] || DoneF[BN])
772  return false;
773  if (DoneT[BN])
774  return true;
775 
776  auto &CSI = MBB.getParent()->getFrameInfo().getCalleeSavedInfo();
777 
778  Path[BN] = true;
779  bool ReachedExit = false;
780  for (auto &SB : MBB.successors())
781  ReachedExit |= updateExitPaths(*SB, RestoreB, DoneT, DoneF, Path);
782 
783  if (!MBB.empty() && MBB.back().isReturn()) {
784  // Add implicit uses of all callee-saved registers to the reached
785  // return instructions. This is to prevent the anti-dependency breaker
786  // from renaming these registers.
787  MachineInstr &RetI = MBB.back();
788  if (!isRestoreCall(RetI.getOpcode()))
789  for (auto &R : CSI)
790  RetI.addOperand(MachineOperand::CreateReg(R.getReg(), false, true));
791  ReachedExit = true;
792  }
793 
794  // We don't want to add unnecessary live-ins to the restore block: since
795  // the callee-saved registers are being defined in it, the entry of the
796  // restore block cannot be on the path from the definitions to any exit.
797  if (ReachedExit && &MBB != &RestoreB) {
798  for (auto &R : CSI)
799  if (!MBB.isLiveIn(R.getReg()))
800  MBB.addLiveIn(R.getReg());
801  DoneT[BN] = true;
802  }
803  if (!ReachedExit)
804  DoneF[BN] = true;
805 
806  Path[BN] = false;
807  return ReachedExit;
808 }
809 
812  // The CFI instructions need to be inserted right after allocframe.
813  // An exception to this is a situation where allocframe is bundled
814  // with a call: then the CFI instructions need to be inserted before
815  // the packet with the allocframe+call (in case the call throws an
816  // exception).
817  auto End = B.instr_end();
818 
819  for (MachineInstr &I : B) {
820  MachineBasicBlock::iterator It = I.getIterator();
821  if (!I.isBundle()) {
822  if (I.getOpcode() == Hexagon::S2_allocframe)
823  return std::next(It);
824  continue;
825  }
826  // I is a bundle.
827  bool HasCall = false, HasAllocFrame = false;
828  auto T = It.getInstrIterator();
829  while (++T != End && T->isBundled()) {
830  if (T->getOpcode() == Hexagon::S2_allocframe)
831  HasAllocFrame = true;
832  else if (T->isCall())
833  HasCall = true;
834  }
835  if (HasAllocFrame)
836  return HasCall ? It : std::next(It);
837  }
838  return None;
839 }
840 
842  for (auto &B : MF) {
843  auto At = findCFILocation(B);
844  if (At.hasValue())
845  insertCFIInstructionsAt(B, At.getValue());
846  }
847 }
848 
849 void HexagonFrameLowering::insertCFIInstructionsAt(MachineBasicBlock &MBB,
850  MachineBasicBlock::iterator At) const {
851  MachineFunction &MF = *MBB.getParent();
852  MachineFrameInfo &MFI = MF.getFrameInfo();
853  MachineModuleInfo &MMI = MF.getMMI();
854  auto &HST = MF.getSubtarget<HexagonSubtarget>();
855  auto &HII = *HST.getInstrInfo();
856  auto &HRI = *HST.getRegisterInfo();
857 
858  // If CFI instructions have debug information attached, something goes
859  // wrong with the final assembly generation: the prolog_end is placed
860  // in a wrong location.
861  DebugLoc DL;
862  const MCInstrDesc &CFID = HII.get(TargetOpcode::CFI_INSTRUCTION);
863 
864  MCSymbol *FrameLabel = MMI.getContext().createTempSymbol();
865  bool HasFP = hasFP(MF);
866 
867  if (HasFP) {
868  unsigned DwFPReg = HRI.getDwarfRegNum(HRI.getFrameRegister(), true);
869  unsigned DwRAReg = HRI.getDwarfRegNum(HRI.getRARegister(), true);
870 
871  // Define CFA via an offset from the value of FP.
872  //
873  // -8 -4 0 (SP)
874  // --+----+----+---------------------
875  // | FP | LR | increasing addresses -->
876  // --+----+----+---------------------
877  // | +-- Old SP (before allocframe)
878  // +-- New FP (after allocframe)
879  //
880  // MCCFIInstruction::createDefCfa subtracts the offset from the register.
881  // MCCFIInstruction::createOffset takes the offset without sign change.
882  auto DefCfa = MCCFIInstruction::createDefCfa(FrameLabel, DwFPReg, -8);
883  BuildMI(MBB, At, DL, CFID)
884  .addCFIIndex(MF.addFrameInst(DefCfa));
885  // R31 (return addr) = CFA - 4
886  auto OffR31 = MCCFIInstruction::createOffset(FrameLabel, DwRAReg, -4);
887  BuildMI(MBB, At, DL, CFID)
888  .addCFIIndex(MF.addFrameInst(OffR31));
889  // R30 (frame ptr) = CFA - 8
890  auto OffR30 = MCCFIInstruction::createOffset(FrameLabel, DwFPReg, -8);
891  BuildMI(MBB, At, DL, CFID)
892  .addCFIIndex(MF.addFrameInst(OffR30));
893  }
894 
895  static unsigned int RegsToMove[] = {
896  Hexagon::R1, Hexagon::R0, Hexagon::R3, Hexagon::R2,
897  Hexagon::R17, Hexagon::R16, Hexagon::R19, Hexagon::R18,
898  Hexagon::R21, Hexagon::R20, Hexagon::R23, Hexagon::R22,
899  Hexagon::R25, Hexagon::R24, Hexagon::R27, Hexagon::R26,
900  Hexagon::D0, Hexagon::D1, Hexagon::D8, Hexagon::D9,
901  Hexagon::D10, Hexagon::D11, Hexagon::D12, Hexagon::D13,
902  Hexagon::NoRegister
903  };
904 
905  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
906 
907  for (unsigned i = 0; RegsToMove[i] != Hexagon::NoRegister; ++i) {
908  unsigned Reg = RegsToMove[i];
909  auto IfR = [Reg] (const CalleeSavedInfo &C) -> bool {
910  return C.getReg() == Reg;
911  };
912  auto F = find_if(CSI, IfR);
913  if (F == CSI.end())
914  continue;
915 
916  int64_t Offset;
917  if (HasFP) {
918  // If the function has a frame pointer (i.e. has an allocframe),
919  // then the CFA has been defined in terms of FP. Any offsets in
920  // the following CFI instructions have to be defined relative
921  // to FP, which points to the bottom of the stack frame.
922  // The function getFrameIndexReference can still choose to use SP
923  // for the offset calculation, so we cannot simply call it here.
924  // Instead, get the offset (relative to the FP) directly.
925  Offset = MFI.getObjectOffset(F->getFrameIdx());
926  } else {
927  unsigned FrameReg;
928  Offset = getFrameIndexReference(MF, F->getFrameIdx(), FrameReg);
929  }
930  // Subtract 8 to make room for R30 and R31, which are added above.
931  Offset -= 8;
932 
933  if (Reg < Hexagon::D0 || Reg > Hexagon::D15) {
934  unsigned DwarfReg = HRI.getDwarfRegNum(Reg, true);
935  auto OffReg = MCCFIInstruction::createOffset(FrameLabel, DwarfReg,
936  Offset);
937  BuildMI(MBB, At, DL, CFID)
938  .addCFIIndex(MF.addFrameInst(OffReg));
939  } else {
940  // Split the double regs into subregs, and generate appropriate
941  // cfi_offsets.
942  // The only reason, we are split double regs is, llvm-mc does not
943  // understand paired registers for cfi_offset.
944  // Eg .cfi_offset r1:0, -64
945 
946  unsigned HiReg = HRI.getSubReg(Reg, Hexagon::isub_hi);
947  unsigned LoReg = HRI.getSubReg(Reg, Hexagon::isub_lo);
948  unsigned HiDwarfReg = HRI.getDwarfRegNum(HiReg, true);
949  unsigned LoDwarfReg = HRI.getDwarfRegNum(LoReg, true);
950  auto OffHi = MCCFIInstruction::createOffset(FrameLabel, HiDwarfReg,
951  Offset+4);
952  BuildMI(MBB, At, DL, CFID)
953  .addCFIIndex(MF.addFrameInst(OffHi));
954  auto OffLo = MCCFIInstruction::createOffset(FrameLabel, LoDwarfReg,
955  Offset);
956  BuildMI(MBB, At, DL, CFID)
957  .addCFIIndex(MF.addFrameInst(OffLo));
958  }
959  }
960 }
961 
963  if (MF.getFunction().hasFnAttribute(Attribute::Naked))
964  return false;
965 
966  auto &MFI = MF.getFrameInfo();
967  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
968  bool HasExtraAlign = HRI.needsStackRealignment(MF);
969  bool HasAlloca = MFI.hasVarSizedObjects();
970 
971  // Insert ALLOCFRAME if we need to or at -O0 for the debugger. Think
972  // that this shouldn't be required, but doing so now because gcc does and
973  // gdb can't break at the start of the function without it. Will remove if
974  // this turns out to be a gdb bug.
975  //
976  if (MF.getTarget().getOptLevel() == CodeGenOpt::None)
977  return true;
978 
979  // By default we want to use SP (since it's always there). FP requires
980  // some setup (i.e. ALLOCFRAME).
981  // Both, alloca and stack alignment modify the stack pointer by an
982  // undetermined value, so we need to save it at the entry to the function
983  // (i.e. use allocframe).
984  if (HasAlloca || HasExtraAlign)
985  return true;
986 
987  if (MFI.getStackSize() > 0) {
988  // If FP-elimination is disabled, we have to use FP at this point.
989  const TargetMachine &TM = MF.getTarget();
991  return true;
993  return true;
994  }
995 
996  const auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
997  if (MFI.hasCalls() || HMFI.hasClobberLR())
998  return true;
999 
1000  return false;
1001 }
1002 
1007 };
1008 
1009 static const char *getSpillFunctionFor(unsigned MaxReg, SpillKind SpillType,
1010  bool Stkchk = false) {
1011  const char * V4SpillToMemoryFunctions[] = {
1012  "__save_r16_through_r17",
1013  "__save_r16_through_r19",
1014  "__save_r16_through_r21",
1015  "__save_r16_through_r23",
1016  "__save_r16_through_r25",
1017  "__save_r16_through_r27" };
1018 
1019  const char * V4SpillToMemoryStkchkFunctions[] = {
1020  "__save_r16_through_r17_stkchk",
1021  "__save_r16_through_r19_stkchk",
1022  "__save_r16_through_r21_stkchk",
1023  "__save_r16_through_r23_stkchk",
1024  "__save_r16_through_r25_stkchk",
1025  "__save_r16_through_r27_stkchk" };
1026 
1027  const char * V4SpillFromMemoryFunctions[] = {
1028  "__restore_r16_through_r17_and_deallocframe",
1029  "__restore_r16_through_r19_and_deallocframe",
1030  "__restore_r16_through_r21_and_deallocframe",
1031  "__restore_r16_through_r23_and_deallocframe",
1032  "__restore_r16_through_r25_and_deallocframe",
1033  "__restore_r16_through_r27_and_deallocframe" };
1034 
1035  const char * V4SpillFromMemoryTailcallFunctions[] = {
1036  "__restore_r16_through_r17_and_deallocframe_before_tailcall",
1037  "__restore_r16_through_r19_and_deallocframe_before_tailcall",
1038  "__restore_r16_through_r21_and_deallocframe_before_tailcall",
1039  "__restore_r16_through_r23_and_deallocframe_before_tailcall",
1040  "__restore_r16_through_r25_and_deallocframe_before_tailcall",
1041  "__restore_r16_through_r27_and_deallocframe_before_tailcall"
1042  };
1043 
1044  const char **SpillFunc = nullptr;
1045 
1046  switch(SpillType) {
1047  case SK_ToMem:
1048  SpillFunc = Stkchk ? V4SpillToMemoryStkchkFunctions
1049  : V4SpillToMemoryFunctions;
1050  break;
1051  case SK_FromMem:
1052  SpillFunc = V4SpillFromMemoryFunctions;
1053  break;
1054  case SK_FromMemTailcall:
1055  SpillFunc = V4SpillFromMemoryTailcallFunctions;
1056  break;
1057  }
1058  assert(SpillFunc && "Unknown spill kind");
1059 
1060  // Spill all callee-saved registers up to the highest register used.
1061  switch (MaxReg) {
1062  case Hexagon::R17:
1063  return SpillFunc[0];
1064  case Hexagon::R19:
1065  return SpillFunc[1];
1066  case Hexagon::R21:
1067  return SpillFunc[2];
1068  case Hexagon::R23:
1069  return SpillFunc[3];
1070  case Hexagon::R25:
1071  return SpillFunc[4];
1072  case Hexagon::R27:
1073  return SpillFunc[5];
1074  default:
1075  llvm_unreachable("Unhandled maximum callee save register");
1076  }
1077  return nullptr;
1078 }
1079 
1081  int FI, unsigned &FrameReg) const {
1082  auto &MFI = MF.getFrameInfo();
1083  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1084 
1085  int Offset = MFI.getObjectOffset(FI);
1086  bool HasAlloca = MFI.hasVarSizedObjects();
1087  bool HasExtraAlign = HRI.needsStackRealignment(MF);
1088  bool NoOpt = MF.getTarget().getOptLevel() == CodeGenOpt::None;
1089 
1090  auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
1091  unsigned FrameSize = MFI.getStackSize();
1092  unsigned SP = HRI.getStackRegister();
1093  unsigned FP = HRI.getFrameRegister();
1094  unsigned AP = HMFI.getStackAlignBasePhysReg();
1095  // It may happen that AP will be absent even HasAlloca && HasExtraAlign
1096  // is true. HasExtraAlign may be set because of vector spills, without
1097  // aligned locals or aligned outgoing function arguments. Since vector
1098  // spills will ultimately be "unaligned", it is safe to use FP as the
1099  // base register.
1100  // In fact, in such a scenario the stack is actually not required to be
1101  // aligned, although it may end up being aligned anyway, since this
1102  // particular case is not easily detectable. The alignment will be
1103  // unnecessary, but not incorrect.
1104  // Unfortunately there is no quick way to verify that the above is
1105  // indeed the case (and that it's not a result of an error), so just
1106  // assume that missing AP will be replaced by FP.
1107  // (A better fix would be to rematerialize AP from FP and always align
1108  // vector spills.)
1109  if (AP == 0)
1110  AP = FP;
1111 
1112  bool UseFP = false, UseAP = false; // Default: use SP (except at -O0).
1113  // Use FP at -O0, except when there are objects with extra alignment.
1114  // That additional alignment requirement may cause a pad to be inserted,
1115  // which will make it impossible to use FP to access objects located
1116  // past the pad.
1117  if (NoOpt && !HasExtraAlign)
1118  UseFP = true;
1119  if (MFI.isFixedObjectIndex(FI) || MFI.isObjectPreAllocated(FI)) {
1120  // Fixed and preallocated objects will be located before any padding
1121  // so FP must be used to access them.
1122  UseFP |= (HasAlloca || HasExtraAlign);
1123  } else {
1124  if (HasAlloca) {
1125  if (HasExtraAlign)
1126  UseAP = true;
1127  else
1128  UseFP = true;
1129  }
1130  }
1131 
1132  // If FP was picked, then there had better be FP.
1133  bool HasFP = hasFP(MF);
1134  assert((HasFP || !UseFP) && "This function must have frame pointer");
1135 
1136  // Having FP implies allocframe. Allocframe will store extra 8 bytes:
1137  // FP/LR. If the base register is used to access an object across these
1138  // 8 bytes, then the offset will need to be adjusted by 8.
1139  //
1140  // After allocframe:
1141  // HexagonISelLowering adds 8 to ---+
1142  // the offsets of all stack-based |
1143  // arguments (*) |
1144  // |
1145  // getObjectOffset < 0 0 8 getObjectOffset >= 8
1146  // ------------------------+-----+------------------------> increasing
1147  // <local objects> |FP/LR| <input arguments> addresses
1148  // -----------------+------+-----+------------------------>
1149  // | |
1150  // SP/AP point --+ +-- FP points here (**)
1151  // somewhere on
1152  // this side of FP/LR
1153  //
1154  // (*) See LowerFormalArguments. The FP/LR is assumed to be present.
1155  // (**) *FP == old-FP. FP+0..7 are the bytes of FP/LR.
1156 
1157  // The lowering assumes that FP/LR is present, and so the offsets of
1158  // the formal arguments start at 8. If FP/LR is not there we need to
1159  // reduce the offset by 8.
1160  if (Offset > 0 && !HasFP)
1161  Offset -= 8;
1162 
1163  if (UseFP)
1164  FrameReg = FP;
1165  else if (UseAP)
1166  FrameReg = AP;
1167  else
1168  FrameReg = SP;
1169 
1170  // Calculate the actual offset in the instruction. If there is no FP
1171  // (in other words, no allocframe), then SP will not be adjusted (i.e.
1172  // there will be no SP -= FrameSize), so the frame size should not be
1173  // added to the calculated offset.
1174  int RealOffset = Offset;
1175  if (!UseFP && !UseAP)
1176  RealOffset = FrameSize+Offset;
1177  return RealOffset;
1178 }
1179 
1180 bool HexagonFrameLowering::insertCSRSpillsInBlock(MachineBasicBlock &MBB,
1181  const CSIVect &CSI, const HexagonRegisterInfo &HRI,
1182  bool &PrologueStubs) const {
1183  if (CSI.empty())
1184  return true;
1185 
1187  PrologueStubs = false;
1188  MachineFunction &MF = *MBB.getParent();
1189  auto &HST = MF.getSubtarget<HexagonSubtarget>();
1190  auto &HII = *HST.getInstrInfo();
1191 
1192  if (useSpillFunction(MF, CSI)) {
1193  PrologueStubs = true;
1194  unsigned MaxReg = getMaxCalleeSavedReg(CSI, HRI);
1195  bool StkOvrFlowEnabled = EnableStackOVFSanitizer;
1196  const char *SpillFun = getSpillFunctionFor(MaxReg, SK_ToMem,
1197  StkOvrFlowEnabled);
1198  auto &HTM = static_cast<const HexagonTargetMachine&>(MF.getTarget());
1199  bool IsPIC = HTM.isPositionIndependent();
1200  bool LongCalls = HST.useLongCalls() || EnableSaveRestoreLong;
1201 
1202  // Call spill function.
1203  DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
1204  unsigned SpillOpc;
1205  if (StkOvrFlowEnabled) {
1206  if (LongCalls)
1207  SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT_PIC
1208  : Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT;
1209  else
1210  SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4STK_PIC
1211  : Hexagon::SAVE_REGISTERS_CALL_V4STK;
1212  } else {
1213  if (LongCalls)
1214  SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC
1215  : Hexagon::SAVE_REGISTERS_CALL_V4_EXT;
1216  else
1217  SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4_PIC
1218  : Hexagon::SAVE_REGISTERS_CALL_V4;
1219  }
1220 
1221  MachineInstr *SaveRegsCall =
1222  BuildMI(MBB, MI, DL, HII.get(SpillOpc))
1223  .addExternalSymbol(SpillFun);
1224 
1225  // Add callee-saved registers as use.
1226  addCalleeSaveRegistersAsImpOperand(SaveRegsCall, CSI, false, true);
1227  // Add live in registers.
1228  for (unsigned I = 0; I < CSI.size(); ++I)
1229  MBB.addLiveIn(CSI[I].getReg());
1230  return true;
1231  }
1232 
1233  for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
1234  unsigned Reg = CSI[i].getReg();
1235  // Add live in registers. We treat eh_return callee saved register r0 - r3
1236  // specially. They are not really callee saved registers as they are not
1237  // supposed to be killed.
1238  bool IsKill = !HRI.isEHReturnCalleeSaveReg(Reg);
1239  int FI = CSI[i].getFrameIdx();
1240  const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);
1241  HII.storeRegToStackSlot(MBB, MI, Reg, IsKill, FI, RC, &HRI);
1242  if (IsKill)
1243  MBB.addLiveIn(Reg);
1244  }
1245  return true;
1246 }
1247 
1248 bool HexagonFrameLowering::insertCSRRestoresInBlock(MachineBasicBlock &MBB,
1249  const CSIVect &CSI, const HexagonRegisterInfo &HRI) const {
1250  if (CSI.empty())
1251  return false;
1252 
1254  MachineFunction &MF = *MBB.getParent();
1255  auto &HST = MF.getSubtarget<HexagonSubtarget>();
1256  auto &HII = *HST.getInstrInfo();
1257 
1258  if (useRestoreFunction(MF, CSI)) {
1259  bool HasTC = hasTailCall(MBB) || !hasReturn(MBB);
1260  unsigned MaxR = getMaxCalleeSavedReg(CSI, HRI);
1262  const char *RestoreFn = getSpillFunctionFor(MaxR, Kind);
1263  auto &HTM = static_cast<const HexagonTargetMachine&>(MF.getTarget());
1264  bool IsPIC = HTM.isPositionIndependent();
1265  bool LongCalls = HST.useLongCalls() || EnableSaveRestoreLong;
1266 
1267  // Call spill function.
1268  DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc()
1269  : MBB.getLastNonDebugInstr()->getDebugLoc();
1270  MachineInstr *DeallocCall = nullptr;
1271 
1272  if (HasTC) {
1273  unsigned RetOpc;
1274  if (LongCalls)
1275  RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC
1276  : Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT;
1277  else
1278  RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC
1279  : Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4;
1280  DeallocCall = BuildMI(MBB, MI, DL, HII.get(RetOpc))
1281  .addExternalSymbol(RestoreFn);
1282  } else {
1283  // The block has a return.
1285  assert(It->isReturn() && std::next(It) == MBB.end());
1286  unsigned RetOpc;
1287  if (LongCalls)
1288  RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC
1289  : Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT;
1290  else
1291  RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC
1292  : Hexagon::RESTORE_DEALLOC_RET_JMP_V4;
1293  DeallocCall = BuildMI(MBB, It, DL, HII.get(RetOpc))
1294  .addExternalSymbol(RestoreFn);
1295  // Transfer the function live-out registers.
1296  DeallocCall->copyImplicitOps(MF, *It);
1297  }
1298  addCalleeSaveRegistersAsImpOperand(DeallocCall, CSI, true, false);
1299  return true;
1300  }
1301 
1302  for (unsigned i = 0; i < CSI.size(); ++i) {
1303  unsigned Reg = CSI[i].getReg();
1304  const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);
1305  int FI = CSI[i].getFrameIdx();
1306  HII.loadRegFromStackSlot(MBB, MI, Reg, FI, RC, &HRI);
1307  }
1308 
1309  return true;
1310 }
1311 
1315  MachineInstr &MI = *I;
1316  unsigned Opc = MI.getOpcode();
1317  (void)Opc; // Silence compiler warning.
1318  assert((Opc == Hexagon::ADJCALLSTACKDOWN || Opc == Hexagon::ADJCALLSTACKUP) &&
1319  "Cannot handle this call frame pseudo instruction");
1320  return MBB.erase(I);
1321 }
1322 
1324  MachineFunction &MF, RegScavenger *RS) const {
1325  // If this function has uses aligned stack and also has variable sized stack
1326  // objects, then we need to map all spill slots to fixed positions, so that
1327  // they can be accessed through FP. Otherwise they would have to be accessed
1328  // via AP, which may not be available at the particular place in the program.
1329  MachineFrameInfo &MFI = MF.getFrameInfo();
1330  bool HasAlloca = MFI.hasVarSizedObjects();
1331  bool NeedsAlign = (MFI.getMaxAlignment() > getStackAlignment());
1332 
1333  if (!HasAlloca || !NeedsAlign)
1334  return;
1335 
1336  unsigned LFS = MFI.getLocalFrameSize();
1337  for (int i = 0, e = MFI.getObjectIndexEnd(); i != e; ++i) {
1338  if (!MFI.isSpillSlotObjectIndex(i) || MFI.isDeadObjectIndex(i))
1339  continue;
1340  unsigned S = MFI.getObjectSize(i);
1341  // Reduce the alignment to at most 8. This will require unaligned vector
1342  // stores if they happen here.
1343  unsigned A = std::max(MFI.getObjectAlignment(i), 8U);
1344  MFI.setObjectAlignment(i, 8);
1345  LFS = alignTo(LFS+S, A);
1346  MFI.mapLocalFrameObject(i, -LFS);
1347  }
1348 
1349  MFI.setLocalFrameSize(LFS);
1350  unsigned A = MFI.getLocalFrameMaxAlign();
1351  assert(A <= 8 && "Unexpected local frame alignment");
1352  if (A == 0)
1353  MFI.setLocalFrameMaxAlign(8);
1355 
1356  // Set the physical aligned-stack base address register.
1357  unsigned AP = 0;
1358  if (const MachineInstr *AI = getAlignaInstr(MF))
1359  AP = AI->getOperand(0).getReg();
1360  auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
1361  HMFI.setStackAlignBasePhysReg(AP);
1362 }
1363 
1364 /// Returns true if there are no caller-saved registers available in class RC.
1366  const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC) {
1368 
1369  auto IsUsed = [&HRI,&MRI] (unsigned Reg) -> bool {
1370  for (MCRegAliasIterator AI(Reg, &HRI, true); AI.isValid(); ++AI)
1371  if (MRI.isPhysRegUsed(*AI))
1372  return true;
1373  return false;
1374  };
1375 
1376  // Check for an unused caller-saved register. Callee-saved registers
1377  // have become pristine by now.
1378  for (const MCPhysReg *P = HRI.getCallerSavedRegs(&MF, RC); *P; ++P)
1379  if (!IsUsed(*P))
1380  return false;
1381 
1382  // All caller-saved registers are used.
1383  return true;
1384 }
1385 
1386 #ifndef NDEBUG
1388  dbgs() << '{';
1389  for (int x = Regs.find_first(); x >= 0; x = Regs.find_next(x)) {
1390  unsigned R = x;
1391  dbgs() << ' ' << printReg(R, &TRI);
1392  }
1393  dbgs() << " }";
1394 }
1395 #endif
1396 
1398  const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI) const {
1399  LLVM_DEBUG(dbgs() << __func__ << " on " << MF.getName() << '\n');
1400  MachineFrameInfo &MFI = MF.getFrameInfo();
1401  BitVector SRegs(Hexagon::NUM_TARGET_REGS);
1402 
1403  // Generate a set of unique, callee-saved registers (SRegs), where each
1404  // register in the set is maximal in terms of sub-/super-register relation,
1405  // i.e. for each R in SRegs, no proper super-register of R is also in SRegs.
1406 
1407  // (1) For each callee-saved register, add that register and all of its
1408  // sub-registers to SRegs.
1409  LLVM_DEBUG(dbgs() << "Initial CS registers: {");
1410  for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
1411  unsigned R = CSI[i].getReg();
1412  LLVM_DEBUG(dbgs() << ' ' << printReg(R, TRI));
1413  for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR)
1414  SRegs[*SR] = true;
1415  }
1416  LLVM_DEBUG(dbgs() << " }\n");
1417  LLVM_DEBUG(dbgs() << "SRegs.1: "; dump_registers(SRegs, *TRI);
1418  dbgs() << "\n");
1419 
1420  // (2) For each reserved register, remove that register and all of its
1421  // sub- and super-registers from SRegs.
1422  BitVector Reserved = TRI->getReservedRegs(MF);
1423  for (int x = Reserved.find_first(); x >= 0; x = Reserved.find_next(x)) {
1424  unsigned R = x;
1425  for (MCSuperRegIterator SR(R, TRI, true); SR.isValid(); ++SR)
1426  SRegs[*SR] = false;
1427  }
1428  LLVM_DEBUG(dbgs() << "Res: "; dump_registers(Reserved, *TRI);
1429  dbgs() << "\n");
1430  LLVM_DEBUG(dbgs() << "SRegs.2: "; dump_registers(SRegs, *TRI);
1431  dbgs() << "\n");
1432 
1433  // (3) Collect all registers that have at least one sub-register in SRegs,
1434  // and also have no sub-registers that are reserved. These will be the can-
1435  // didates for saving as a whole instead of their individual sub-registers.
1436  // (Saving R17:16 instead of R16 is fine, but only if R17 was not reserved.)
1437  BitVector TmpSup(Hexagon::NUM_TARGET_REGS);
1438  for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1439  unsigned R = x;
1440  for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR)
1441  TmpSup[*SR] = true;
1442  }
1443  for (int x = TmpSup.find_first(); x >= 0; x = TmpSup.find_next(x)) {
1444  unsigned R = x;
1445  for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR) {
1446  if (!Reserved[*SR])
1447  continue;
1448  TmpSup[R] = false;
1449  break;
1450  }
1451  }
1452  LLVM_DEBUG(dbgs() << "TmpSup: "; dump_registers(TmpSup, *TRI);
1453  dbgs() << "\n");
1454 
1455  // (4) Include all super-registers found in (3) into SRegs.
1456  SRegs |= TmpSup;
1457  LLVM_DEBUG(dbgs() << "SRegs.4: "; dump_registers(SRegs, *TRI);
1458  dbgs() << "\n");
1459 
1460  // (5) For each register R in SRegs, if any super-register of R is in SRegs,
1461  // remove R from SRegs.
1462  for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1463  unsigned R = x;
1464  for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR) {
1465  if (!SRegs[*SR])
1466  continue;
1467  SRegs[R] = false;
1468  break;
1469  }
1470  }
1471  LLVM_DEBUG(dbgs() << "SRegs.5: "; dump_registers(SRegs, *TRI);
1472  dbgs() << "\n");
1473 
1474  // Now, for each register that has a fixed stack slot, create the stack
1475  // object for it.
1476  CSI.clear();
1477 
1479 
1480  unsigned NumFixed;
1481  int MinOffset = 0; // CS offsets are negative.
1482  const SpillSlot *FixedSlots = getCalleeSavedSpillSlots(NumFixed);
1483  for (const SpillSlot *S = FixedSlots; S != FixedSlots+NumFixed; ++S) {
1484  if (!SRegs[S->Reg])
1485  continue;
1486  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(S->Reg);
1487  int FI = MFI.CreateFixedSpillStackObject(TRI->getSpillSize(*RC), S->Offset);
1488  MinOffset = std::min(MinOffset, S->Offset);
1489  CSI.push_back(CalleeSavedInfo(S->Reg, FI));
1490  SRegs[S->Reg] = false;
1491  }
1492 
1493  // There can be some registers that don't have fixed slots. For example,
1494  // we need to store R0-R3 in functions with exception handling. For each
1495  // such register, create a non-fixed stack object.
1496  for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1497  unsigned R = x;
1498  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(R);
1499  unsigned Size = TRI->getSpillSize(*RC);
1500  int Off = MinOffset - Size;
1501  unsigned Align = std::min(TRI->getSpillAlignment(*RC), getStackAlignment());
1502  assert(isPowerOf2_32(Align));
1503  Off &= -Align;
1504  int FI = MFI.CreateFixedSpillStackObject(Size, Off);
1505  MinOffset = std::min(MinOffset, Off);
1506  CSI.push_back(CalleeSavedInfo(R, FI));
1507  SRegs[R] = false;
1508  }
1509 
1510  LLVM_DEBUG({
1511  dbgs() << "CS information: {";
1512  for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
1513  int FI = CSI[i].getFrameIdx();
1514  int Off = MFI.getObjectOffset(FI);
1515  dbgs() << ' ' << printReg(CSI[i].getReg(), TRI) << ":fi#" << FI << ":sp";
1516  if (Off >= 0)
1517  dbgs() << '+';
1518  dbgs() << Off;
1519  }
1520  dbgs() << " }\n";
1521  });
1522 
1523 #ifndef NDEBUG
1524  // Verify that all registers were handled.
1525  bool MissedReg = false;
1526  for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1527  unsigned R = x;
1528  dbgs() << printReg(R, TRI) << ' ';
1529  MissedReg = true;
1530  }
1531  if (MissedReg)
1532  llvm_unreachable("...there are unhandled callee-saved registers!");
1533 #endif
1534 
1535  return true;
1536 }
1537 
1538 bool HexagonFrameLowering::expandCopy(MachineBasicBlock &B,
1540  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1541  MachineInstr *MI = &*It;
1542  DebugLoc DL = MI->getDebugLoc();
1543  unsigned DstR = MI->getOperand(0).getReg();
1544  unsigned SrcR = MI->getOperand(1).getReg();
1545  if (!Hexagon::ModRegsRegClass.contains(DstR) ||
1546  !Hexagon::ModRegsRegClass.contains(SrcR))
1547  return false;
1548 
1549  unsigned TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1550  BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), TmpR).add(MI->getOperand(1));
1551  BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), DstR)
1552  .addReg(TmpR, RegState::Kill);
1553 
1554  NewRegs.push_back(TmpR);
1555  B.erase(It);
1556  return true;
1557 }
1558 
1559 bool HexagonFrameLowering::expandStoreInt(MachineBasicBlock &B,
1561  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1562  MachineInstr *MI = &*It;
1563  if (!MI->getOperand(0).isFI())
1564  return false;
1565 
1566  DebugLoc DL = MI->getDebugLoc();
1567  unsigned Opc = MI->getOpcode();
1568  unsigned SrcR = MI->getOperand(2).getReg();
1569  bool IsKill = MI->getOperand(2).isKill();
1570  int FI = MI->getOperand(0).getIndex();
1571 
1572  // TmpR = C2_tfrpr SrcR if SrcR is a predicate register
1573  // TmpR = A2_tfrcrr SrcR if SrcR is a modifier register
1574  unsigned TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1575  unsigned TfrOpc = (Opc == Hexagon::STriw_pred) ? Hexagon::C2_tfrpr
1576  : Hexagon::A2_tfrcrr;
1577  BuildMI(B, It, DL, HII.get(TfrOpc), TmpR)
1578  .addReg(SrcR, getKillRegState(IsKill));
1579 
1580  // S2_storeri_io FI, 0, TmpR
1581  BuildMI(B, It, DL, HII.get(Hexagon::S2_storeri_io))
1582  .addFrameIndex(FI)
1583  .addImm(0)
1584  .addReg(TmpR, RegState::Kill)
1585  .cloneMemRefs(*MI);
1586 
1587  NewRegs.push_back(TmpR);
1588  B.erase(It);
1589  return true;
1590 }
1591 
1592 bool HexagonFrameLowering::expandLoadInt(MachineBasicBlock &B,
1594  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1595  MachineInstr *MI = &*It;
1596  if (!MI->getOperand(1).isFI())
1597  return false;
1598 
1599  DebugLoc DL = MI->getDebugLoc();
1600  unsigned Opc = MI->getOpcode();
1601  unsigned DstR = MI->getOperand(0).getReg();
1602  int FI = MI->getOperand(1).getIndex();
1603 
1604  // TmpR = L2_loadri_io FI, 0
1605  unsigned TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1606  BuildMI(B, It, DL, HII.get(Hexagon::L2_loadri_io), TmpR)
1607  .addFrameIndex(FI)
1608  .addImm(0)
1609  .cloneMemRefs(*MI);
1610 
1611  // DstR = C2_tfrrp TmpR if DstR is a predicate register
1612  // DstR = A2_tfrrcr TmpR if DstR is a modifier register
1613  unsigned TfrOpc = (Opc == Hexagon::LDriw_pred) ? Hexagon::C2_tfrrp
1614  : Hexagon::A2_tfrrcr;
1615  BuildMI(B, It, DL, HII.get(TfrOpc), DstR)
1616  .addReg(TmpR, RegState::Kill);
1617 
1618  NewRegs.push_back(TmpR);
1619  B.erase(It);
1620  return true;
1621 }
1622 
1623 bool HexagonFrameLowering::expandStoreVecPred(MachineBasicBlock &B,
1625  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1626  MachineInstr *MI = &*It;
1627  if (!MI->getOperand(0).isFI())
1628  return false;
1629 
1630  DebugLoc DL = MI->getDebugLoc();
1631  unsigned SrcR = MI->getOperand(2).getReg();
1632  bool IsKill = MI->getOperand(2).isKill();
1633  int FI = MI->getOperand(0).getIndex();
1634  auto *RC = &Hexagon::HvxVRRegClass;
1635 
1636  // Insert transfer to general vector register.
1637  // TmpR0 = A2_tfrsi 0x01010101
1638  // TmpR1 = V6_vandqrt Qx, TmpR0
1639  // store FI, 0, TmpR1
1640  unsigned TmpR0 = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1641  unsigned TmpR1 = MRI.createVirtualRegister(RC);
1642 
1643  BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0)
1644  .addImm(0x01010101);
1645 
1646  BuildMI(B, It, DL, HII.get(Hexagon::V6_vandqrt), TmpR1)
1647  .addReg(SrcR, getKillRegState(IsKill))
1648  .addReg(TmpR0, RegState::Kill);
1649 
1650  auto *HRI = B.getParent()->getSubtarget<HexagonSubtarget>().getRegisterInfo();
1651  HII.storeRegToStackSlot(B, It, TmpR1, true, FI, RC, HRI);
1652  expandStoreVec(B, std::prev(It), MRI, HII, NewRegs);
1653 
1654  NewRegs.push_back(TmpR0);
1655  NewRegs.push_back(TmpR1);
1656  B.erase(It);
1657  return true;
1658 }
1659 
1660 bool HexagonFrameLowering::expandLoadVecPred(MachineBasicBlock &B,
1662  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1663  MachineInstr *MI = &*It;
1664  if (!MI->getOperand(1).isFI())
1665  return false;
1666 
1667  DebugLoc DL = MI->getDebugLoc();
1668  unsigned DstR = MI->getOperand(0).getReg();
1669  int FI = MI->getOperand(1).getIndex();
1670  auto *RC = &Hexagon::HvxVRRegClass;
1671 
1672  // TmpR0 = A2_tfrsi 0x01010101
1673  // TmpR1 = load FI, 0
1674  // DstR = V6_vandvrt TmpR1, TmpR0
1675  unsigned TmpR0 = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1676  unsigned TmpR1 = MRI.createVirtualRegister(RC);
1677 
1678  BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0)
1679  .addImm(0x01010101);
1680  MachineFunction &MF = *B.getParent();
1681  auto *HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1682  HII.loadRegFromStackSlot(B, It, TmpR1, FI, RC, HRI);
1683  expandLoadVec(B, std::prev(It), MRI, HII, NewRegs);
1684 
1685  BuildMI(B, It, DL, HII.get(Hexagon::V6_vandvrt), DstR)
1686  .addReg(TmpR1, RegState::Kill)
1687  .addReg(TmpR0, RegState::Kill);
1688 
1689  NewRegs.push_back(TmpR0);
1690  NewRegs.push_back(TmpR1);
1691  B.erase(It);
1692  return true;
1693 }
1694 
1695 bool HexagonFrameLowering::expandStoreVec2(MachineBasicBlock &B,
1697  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1698  MachineFunction &MF = *B.getParent();
1699  auto &MFI = MF.getFrameInfo();
1700  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1701  MachineInstr *MI = &*It;
1702  if (!MI->getOperand(0).isFI())
1703  return false;
1704 
1705  // It is possible that the double vector being stored is only partially
1706  // defined. From the point of view of the liveness tracking, it is ok to
1707  // store it as a whole, but if we break it up we may end up storing a
1708  // register that is entirely undefined.
1709  LivePhysRegs LPR(HRI);
1710  LPR.addLiveIns(B);
1712  for (auto R = B.begin(); R != It; ++R) {
1713  Clobbers.clear();
1714  LPR.stepForward(*R, Clobbers);
1715  }
1716 
1717  DebugLoc DL = MI->getDebugLoc();
1718  unsigned SrcR = MI->getOperand(2).getReg();
1719  unsigned SrcLo = HRI.getSubReg(SrcR, Hexagon::vsub_lo);
1720  unsigned SrcHi = HRI.getSubReg(SrcR, Hexagon::vsub_hi);
1721  bool IsKill = MI->getOperand(2).isKill();
1722  int FI = MI->getOperand(0).getIndex();
1723 
1724  unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1725  unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
1726  unsigned HasAlign = MFI.getObjectAlignment(FI);
1727  unsigned StoreOpc;
1728 
1729  // Store low part.
1730  if (LPR.contains(SrcLo)) {
1731  StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai
1732  : Hexagon::V6_vS32Ub_ai;
1733  BuildMI(B, It, DL, HII.get(StoreOpc))
1734  .addFrameIndex(FI)
1735  .addImm(0)
1736  .addReg(SrcLo, getKillRegState(IsKill))
1737  .cloneMemRefs(*MI);
1738  }
1739 
1740  // Store high part.
1741  if (LPR.contains(SrcHi)) {
1742  StoreOpc = NeedAlign <= MinAlign(HasAlign, Size) ? Hexagon::V6_vS32b_ai
1743  : Hexagon::V6_vS32Ub_ai;
1744  BuildMI(B, It, DL, HII.get(StoreOpc))
1745  .addFrameIndex(FI)
1746  .addImm(Size)
1747  .addReg(SrcHi, getKillRegState(IsKill))
1748  .cloneMemRefs(*MI);
1749  }
1750 
1751  B.erase(It);
1752  return true;
1753 }
1754 
1755 bool HexagonFrameLowering::expandLoadVec2(MachineBasicBlock &B,
1757  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1758  MachineFunction &MF = *B.getParent();
1759  auto &MFI = MF.getFrameInfo();
1760  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1761  MachineInstr *MI = &*It;
1762  if (!MI->getOperand(1).isFI())
1763  return false;
1764 
1765  DebugLoc DL = MI->getDebugLoc();
1766  unsigned DstR = MI->getOperand(0).getReg();
1767  unsigned DstHi = HRI.getSubReg(DstR, Hexagon::vsub_hi);
1768  unsigned DstLo = HRI.getSubReg(DstR, Hexagon::vsub_lo);
1769  int FI = MI->getOperand(1).getIndex();
1770 
1771  unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1772  unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
1773  unsigned HasAlign = MFI.getObjectAlignment(FI);
1774  unsigned LoadOpc;
1775 
1776  // Load low part.
1777  LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai
1778  : Hexagon::V6_vL32Ub_ai;
1779  BuildMI(B, It, DL, HII.get(LoadOpc), DstLo)
1780  .addFrameIndex(FI)
1781  .addImm(0)
1782  .cloneMemRefs(*MI);
1783 
1784  // Load high part.
1785  LoadOpc = NeedAlign <= MinAlign(HasAlign, Size) ? Hexagon::V6_vL32b_ai
1786  : Hexagon::V6_vL32Ub_ai;
1787  BuildMI(B, It, DL, HII.get(LoadOpc), DstHi)
1788  .addFrameIndex(FI)
1789  .addImm(Size)
1790  .cloneMemRefs(*MI);
1791 
1792  B.erase(It);
1793  return true;
1794 }
1795 
1796 bool HexagonFrameLowering::expandStoreVec(MachineBasicBlock &B,
1798  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1799  MachineFunction &MF = *B.getParent();
1800  auto &MFI = MF.getFrameInfo();
1801  MachineInstr *MI = &*It;
1802  if (!MI->getOperand(0).isFI())
1803  return false;
1804 
1805  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1806  DebugLoc DL = MI->getDebugLoc();
1807  unsigned SrcR = MI->getOperand(2).getReg();
1808  bool IsKill = MI->getOperand(2).isKill();
1809  int FI = MI->getOperand(0).getIndex();
1810 
1811  unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
1812  unsigned HasAlign = MFI.getObjectAlignment(FI);
1813  unsigned StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai
1814  : Hexagon::V6_vS32Ub_ai;
1815  BuildMI(B, It, DL, HII.get(StoreOpc))
1816  .addFrameIndex(FI)
1817  .addImm(0)
1818  .addReg(SrcR, getKillRegState(IsKill))
1819  .cloneMemRefs(*MI);
1820 
1821  B.erase(It);
1822  return true;
1823 }
1824 
1825 bool HexagonFrameLowering::expandLoadVec(MachineBasicBlock &B,
1827  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1828  MachineFunction &MF = *B.getParent();
1829  auto &MFI = MF.getFrameInfo();
1830  MachineInstr *MI = &*It;
1831  if (!MI->getOperand(1).isFI())
1832  return false;
1833 
1834  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1835  DebugLoc DL = MI->getDebugLoc();
1836  unsigned DstR = MI->getOperand(0).getReg();
1837  int FI = MI->getOperand(1).getIndex();
1838 
1839  unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
1840  unsigned HasAlign = MFI.getObjectAlignment(FI);
1841  unsigned LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai
1842  : Hexagon::V6_vL32Ub_ai;
1843  BuildMI(B, It, DL, HII.get(LoadOpc), DstR)
1844  .addFrameIndex(FI)
1845  .addImm(0)
1846  .cloneMemRefs(*MI);
1847 
1848  B.erase(It);
1849  return true;
1850 }
1851 
1852 bool HexagonFrameLowering::expandSpillMacros(MachineFunction &MF,
1853  SmallVectorImpl<unsigned> &NewRegs) const {
1854  auto &HII = *MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
1855  MachineRegisterInfo &MRI = MF.getRegInfo();
1856  bool Changed = false;
1857 
1858  for (auto &B : MF) {
1859  // Traverse the basic block.
1861  for (auto I = B.begin(), E = B.end(); I != E; I = NextI) {
1862  MachineInstr *MI = &*I;
1863  NextI = std::next(I);
1864  unsigned Opc = MI->getOpcode();
1865 
1866  switch (Opc) {
1867  case TargetOpcode::COPY:
1868  Changed |= expandCopy(B, I, MRI, HII, NewRegs);
1869  break;
1870  case Hexagon::STriw_pred:
1871  case Hexagon::STriw_ctr:
1872  Changed |= expandStoreInt(B, I, MRI, HII, NewRegs);
1873  break;
1874  case Hexagon::LDriw_pred:
1875  case Hexagon::LDriw_ctr:
1876  Changed |= expandLoadInt(B, I, MRI, HII, NewRegs);
1877  break;
1878  case Hexagon::PS_vstorerq_ai:
1879  Changed |= expandStoreVecPred(B, I, MRI, HII, NewRegs);
1880  break;
1881  case Hexagon::PS_vloadrq_ai:
1882  Changed |= expandLoadVecPred(B, I, MRI, HII, NewRegs);
1883  break;
1884  case Hexagon::PS_vloadrw_ai:
1885  case Hexagon::PS_vloadrwu_ai:
1886  Changed |= expandLoadVec2(B, I, MRI, HII, NewRegs);
1887  break;
1888  case Hexagon::PS_vstorerw_ai:
1889  case Hexagon::PS_vstorerwu_ai:
1890  Changed |= expandStoreVec2(B, I, MRI, HII, NewRegs);
1891  break;
1892  }
1893  }
1894  }
1895 
1896  return Changed;
1897 }
1898 
1900  BitVector &SavedRegs,
1901  RegScavenger *RS) const {
1902  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1903 
1904  SavedRegs.resize(HRI.getNumRegs());
1905 
1906  // If we have a function containing __builtin_eh_return we want to spill and
1907  // restore all callee saved registers. Pretend that they are used.
1909  for (const MCPhysReg *R = HRI.getCalleeSavedRegs(&MF); *R; ++R)
1910  SavedRegs.set(*R);
1911 
1912  // Replace predicate register pseudo spill code.
1913  SmallVector<unsigned,8> NewRegs;
1914  expandSpillMacros(MF, NewRegs);
1915  if (OptimizeSpillSlots && !isOptNone(MF))
1916  optimizeSpillSlots(MF, NewRegs);
1917 
1918  // We need to reserve a spill slot if scavenging could potentially require
1919  // spilling a scavenged register.
1920  if (!NewRegs.empty() || mayOverflowFrameOffset(MF)) {
1921  MachineFrameInfo &MFI = MF.getFrameInfo();
1922  MachineRegisterInfo &MRI = MF.getRegInfo();
1924  // Reserve an int register in any case, because it could be used to hold
1925  // the stack offset in case it does not fit into a spill instruction.
1926  SpillRCs.insert(&Hexagon::IntRegsRegClass);
1927 
1928  for (unsigned VR : NewRegs)
1929  SpillRCs.insert(MRI.getRegClass(VR));
1930 
1931  for (auto *RC : SpillRCs) {
1932  if (!needToReserveScavengingSpillSlots(MF, HRI, RC))
1933  continue;
1934  unsigned Num = RC == &Hexagon::IntRegsRegClass ? NumberScavengerSlots : 1;
1935  unsigned S = HRI.getSpillSize(*RC), A = HRI.getSpillAlignment(*RC);
1936  for (unsigned i = 0; i < Num; i++) {
1937  int NewFI = MFI.CreateSpillStackObject(S, A);
1938  RS->addScavengingFrameIndex(NewFI);
1939  }
1940  }
1941  }
1942 
1943  TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1944 }
1945 
1946 unsigned HexagonFrameLowering::findPhysReg(MachineFunction &MF,
1950  const TargetRegisterClass *RC) const {
1951  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1952  auto &MRI = MF.getRegInfo();
1953 
1954  auto isDead = [&FIR,&DeadMap] (unsigned Reg) -> bool {
1955  auto F = DeadMap.find({Reg,0});
1956  if (F == DeadMap.end())
1957  return false;
1958  for (auto &DR : F->second)
1959  if (DR.contains(FIR))
1960  return true;
1961  return false;
1962  };
1963 
1964  for (unsigned Reg : RC->getRawAllocationOrder(MF)) {
1965  bool Dead = true;
1966  for (auto R : HexagonBlockRanges::expandToSubRegs({Reg,0}, MRI, HRI)) {
1967  if (isDead(R.Reg))
1968  continue;
1969  Dead = false;
1970  break;
1971  }
1972  if (Dead)
1973  return Reg;
1974  }
1975  return 0;
1976 }
1977 
1978 void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
1980  auto &HST = MF.getSubtarget<HexagonSubtarget>();
1981  auto &HII = *HST.getInstrInfo();
1982  auto &HRI = *HST.getRegisterInfo();
1983  auto &MRI = MF.getRegInfo();
1984  HexagonBlockRanges HBR(MF);
1985 
1986  using BlockIndexMap =
1987  std::map<MachineBasicBlock *, HexagonBlockRanges::InstrIndexMap>;
1988  using BlockRangeMap =
1989  std::map<MachineBasicBlock *, HexagonBlockRanges::RangeList>;
1990  using IndexType = HexagonBlockRanges::IndexType;
1991 
1992  struct SlotInfo {
1993  BlockRangeMap Map;
1994  unsigned Size = 0;
1995  const TargetRegisterClass *RC = nullptr;
1996 
1997  SlotInfo() = default;
1998  };
1999 
2000  BlockIndexMap BlockIndexes;
2001  SmallSet<int,4> BadFIs;
2002  std::map<int,SlotInfo> FIRangeMap;
2003 
2004  // Accumulate register classes: get a common class for a pre-existing
2005  // class HaveRC and a new class NewRC. Return nullptr if a common class
2006  // cannot be found, otherwise return the resulting class. If HaveRC is
2007  // nullptr, assume that it is still unset.
2008  auto getCommonRC =
2009  [](const TargetRegisterClass *HaveRC,
2010  const TargetRegisterClass *NewRC) -> const TargetRegisterClass * {
2011  if (HaveRC == nullptr || HaveRC == NewRC)
2012  return NewRC;
2013  // Different classes, both non-null. Pick the more general one.
2014  if (HaveRC->hasSubClassEq(NewRC))
2015  return HaveRC;
2016  if (NewRC->hasSubClassEq(HaveRC))
2017  return NewRC;
2018  return nullptr;
2019  };
2020 
2021  // Scan all blocks in the function. Check all occurrences of frame indexes,
2022  // and collect relevant information.
2023  for (auto &B : MF) {
2024  std::map<int,IndexType> LastStore, LastLoad;
2025  // Emplace appears not to be supported in gcc 4.7.2-4.
2026  //auto P = BlockIndexes.emplace(&B, HexagonBlockRanges::InstrIndexMap(B));
2027  auto P = BlockIndexes.insert(
2028  std::make_pair(&B, HexagonBlockRanges::InstrIndexMap(B)));
2029  auto &IndexMap = P.first->second;
2030  LLVM_DEBUG(dbgs() << "Index map for " << printMBBReference(B) << "\n"
2031  << IndexMap << '\n');
2032 
2033  for (auto &In : B) {
2034  int LFI, SFI;
2035  bool Load = HII.isLoadFromStackSlot(In, LFI) && !HII.isPredicated(In);
2036  bool Store = HII.isStoreToStackSlot(In, SFI) && !HII.isPredicated(In);
2037  if (Load && Store) {
2038  // If it's both a load and a store, then we won't handle it.
2039  BadFIs.insert(LFI);
2040  BadFIs.insert(SFI);
2041  continue;
2042  }
2043  // Check for register classes of the register used as the source for
2044  // the store, and the register used as the destination for the load.
2045  // Also, only accept base+imm_offset addressing modes. Other addressing
2046  // modes can have side-effects (post-increments, etc.). For stack
2047  // slots they are very unlikely, so there is not much loss due to
2048  // this restriction.
2049  if (Load || Store) {
2050  int TFI = Load ? LFI : SFI;
2051  unsigned AM = HII.getAddrMode(In);
2052  SlotInfo &SI = FIRangeMap[TFI];
2053  bool Bad = (AM != HexagonII::BaseImmOffset);
2054  if (!Bad) {
2055  // If the addressing mode is ok, check the register class.
2056  unsigned OpNum = Load ? 0 : 2;
2057  auto *RC = HII.getRegClass(In.getDesc(), OpNum, &HRI, MF);
2058  RC = getCommonRC(SI.RC, RC);
2059  if (RC == nullptr)
2060  Bad = true;
2061  else
2062  SI.RC = RC;
2063  }
2064  if (!Bad) {
2065  // Check sizes.
2066  unsigned S = HII.getMemAccessSize(In);
2067  if (SI.Size != 0 && SI.Size != S)
2068  Bad = true;
2069  else
2070  SI.Size = S;
2071  }
2072  if (!Bad) {
2073  for (auto *Mo : In.memoperands()) {
2074  if (!Mo->isVolatile())
2075  continue;
2076  Bad = true;
2077  break;
2078  }
2079  }
2080  if (Bad)
2081  BadFIs.insert(TFI);
2082  }
2083 
2084  // Locate uses of frame indices.
2085  for (unsigned i = 0, n = In.getNumOperands(); i < n; ++i) {
2086  const MachineOperand &Op = In.getOperand(i);
2087  if (!Op.isFI())
2088  continue;
2089  int FI = Op.getIndex();
2090  // Make sure that the following operand is an immediate and that
2091  // it is 0. This is the offset in the stack object.
2092  if (i+1 >= n || !In.getOperand(i+1).isImm() ||
2093  In.getOperand(i+1).getImm() != 0)
2094  BadFIs.insert(FI);
2095  if (BadFIs.count(FI))
2096  continue;
2097 
2098  IndexType Index = IndexMap.getIndex(&In);
2099  if (Load) {
2100  if (LastStore[FI] == IndexType::None)
2101  LastStore[FI] = IndexType::Entry;
2102  LastLoad[FI] = Index;
2103  } else if (Store) {
2104  HexagonBlockRanges::RangeList &RL = FIRangeMap[FI].Map[&B];
2105  if (LastStore[FI] != IndexType::None)
2106  RL.add(LastStore[FI], LastLoad[FI], false, false);
2107  else if (LastLoad[FI] != IndexType::None)
2108  RL.add(IndexType::Entry, LastLoad[FI], false, false);
2109  LastLoad[FI] = IndexType::None;
2110  LastStore[FI] = Index;
2111  } else {
2112  BadFIs.insert(FI);
2113  }
2114  }
2115  }
2116 
2117  for (auto &I : LastLoad) {
2118  IndexType LL = I.second;
2119  if (LL == IndexType::None)
2120  continue;
2121  auto &RL = FIRangeMap[I.first].Map[&B];
2122  IndexType &LS = LastStore[I.first];
2123  if (LS != IndexType::None)
2124  RL.add(LS, LL, false, false);
2125  else
2126  RL.add(IndexType::Entry, LL, false, false);
2127  LS = IndexType::None;
2128  }
2129  for (auto &I : LastStore) {
2130  IndexType LS = I.second;
2131  if (LS == IndexType::None)
2132  continue;
2133  auto &RL = FIRangeMap[I.first].Map[&B];
2134  RL.add(LS, IndexType::None, false, false);
2135  }
2136  }
2137 
2138  LLVM_DEBUG({
2139  for (auto &P : FIRangeMap) {
2140  dbgs() << "fi#" << P.first;
2141  if (BadFIs.count(P.first))
2142  dbgs() << " (bad)";
2143  dbgs() << " RC: ";
2144  if (P.second.RC != nullptr)
2145  dbgs() << HRI.getRegClassName(P.second.RC) << '\n';
2146  else
2147  dbgs() << "<null>\n";
2148  for (auto &R : P.second.Map)
2149  dbgs() << " " << printMBBReference(*R.first) << " { " << R.second
2150  << "}\n";
2151  }
2152  });
2153 
2154  // When a slot is loaded from in a block without being stored to in the
2155  // same block, it is live-on-entry to this block. To avoid CFG analysis,
2156  // consider this slot to be live-on-exit from all blocks.
2157  SmallSet<int,4> LoxFIs;
2158 
2159  std::map<MachineBasicBlock*,std::vector<int>> BlockFIMap;
2160 
2161  for (auto &P : FIRangeMap) {
2162  // P = pair(FI, map: BB->RangeList)
2163  if (BadFIs.count(P.first))
2164  continue;
2165  for (auto &B : MF) {
2166  auto F = P.second.Map.find(&B);
2167  // F = pair(BB, RangeList)
2168  if (F == P.second.Map.end() || F->second.empty())
2169  continue;
2170  HexagonBlockRanges::IndexRange &IR = F->second.front();
2171  if (IR.start() == IndexType::Entry)
2172  LoxFIs.insert(P.first);
2173  BlockFIMap[&B].push_back(P.first);
2174  }
2175  }
2176 
2177  LLVM_DEBUG({
2178  dbgs() << "Block-to-FI map (* -- live-on-exit):\n";
2179  for (auto &P : BlockFIMap) {
2180  auto &FIs = P.second;
2181  if (FIs.empty())
2182  continue;
2183  dbgs() << " " << printMBBReference(*P.first) << ": {";
2184  for (auto I : FIs) {
2185  dbgs() << " fi#" << I;
2186  if (LoxFIs.count(I))
2187  dbgs() << '*';
2188  }
2189  dbgs() << " }\n";
2190  }
2191  });
2192 
2193 #ifndef NDEBUG
2194  bool HasOptLimit = SpillOptMax.getPosition();
2195 #endif
2196 
2197  // eliminate loads, when all loads eliminated, eliminate all stores.
2198  for (auto &B : MF) {
2199  auto F = BlockIndexes.find(&B);
2200  assert(F != BlockIndexes.end());
2201  HexagonBlockRanges::InstrIndexMap &IM = F->second;
2204  LLVM_DEBUG(dbgs() << printMBBReference(B) << " dead map\n"
2205  << HexagonBlockRanges::PrintRangeMap(DM, HRI));
2206 
2207  for (auto FI : BlockFIMap[&B]) {
2208  if (BadFIs.count(FI))
2209  continue;
2210  LLVM_DEBUG(dbgs() << "Working on fi#" << FI << '\n');
2211  HexagonBlockRanges::RangeList &RL = FIRangeMap[FI].Map[&B];
2212  for (auto &Range : RL) {
2213  LLVM_DEBUG(dbgs() << "--Examining range:" << RL << '\n');
2214  if (!IndexType::isInstr(Range.start()) ||
2215  !IndexType::isInstr(Range.end()))
2216  continue;
2217  MachineInstr &SI = *IM.getInstr(Range.start());
2218  MachineInstr &EI = *IM.getInstr(Range.end());
2219  assert(SI.mayStore() && "Unexpected start instruction");
2220  assert(EI.mayLoad() && "Unexpected end instruction");
2221  MachineOperand &SrcOp = SI.getOperand(2);
2222 
2223  HexagonBlockRanges::RegisterRef SrcRR = { SrcOp.getReg(),
2224  SrcOp.getSubReg() };
2225  auto *RC = HII.getRegClass(SI.getDesc(), 2, &HRI, MF);
2226  // The this-> is needed to unconfuse MSVC.
2227  unsigned FoundR = this->findPhysReg(MF, Range, IM, DM, RC);
2228  LLVM_DEBUG(dbgs() << "Replacement reg:" << printReg(FoundR, &HRI)
2229  << '\n');
2230  if (FoundR == 0)
2231  continue;
2232 #ifndef NDEBUG
2233  if (HasOptLimit) {
2234  if (SpillOptCount >= SpillOptMax)
2235  return;
2236  SpillOptCount++;
2237  }
2238 #endif
2239 
2240  // Generate the copy-in: "FoundR = COPY SrcR" at the store location.
2241  MachineBasicBlock::iterator StartIt = SI.getIterator(), NextIt;
2242  MachineInstr *CopyIn = nullptr;
2243  if (SrcRR.Reg != FoundR || SrcRR.Sub != 0) {
2244  const DebugLoc &DL = SI.getDebugLoc();
2245  CopyIn = BuildMI(B, StartIt, DL, HII.get(TargetOpcode::COPY), FoundR)
2246  .add(SrcOp);
2247  }
2248 
2249  ++StartIt;
2250  // Check if this is a last store and the FI is live-on-exit.
2251  if (LoxFIs.count(FI) && (&Range == &RL.back())) {
2252  // Update store's source register.
2253  if (unsigned SR = SrcOp.getSubReg())
2254  SrcOp.setReg(HRI.getSubReg(FoundR, SR));
2255  else
2256  SrcOp.setReg(FoundR);
2257  SrcOp.setSubReg(0);
2258  // We are keeping this register live.
2259  SrcOp.setIsKill(false);
2260  } else {
2261  B.erase(&SI);
2262  IM.replaceInstr(&SI, CopyIn);
2263  }
2264 
2265  auto EndIt = std::next(EI.getIterator());
2266  for (auto It = StartIt; It != EndIt; It = NextIt) {
2267  MachineInstr &MI = *It;
2268  NextIt = std::next(It);
2269  int TFI;
2270  if (!HII.isLoadFromStackSlot(MI, TFI) || TFI != FI)
2271  continue;
2272  unsigned DstR = MI.getOperand(0).getReg();
2273  assert(MI.getOperand(0).getSubReg() == 0);
2274  MachineInstr *CopyOut = nullptr;
2275  if (DstR != FoundR) {
2276  DebugLoc DL = MI.getDebugLoc();
2277  unsigned MemSize = HII.getMemAccessSize(MI);
2278  assert(HII.getAddrMode(MI) == HexagonII::BaseImmOffset);
2279  unsigned CopyOpc = TargetOpcode::COPY;
2280  if (HII.isSignExtendingLoad(MI))
2281  CopyOpc = (MemSize == 1) ? Hexagon::A2_sxtb : Hexagon::A2_sxth;
2282  else if (HII.isZeroExtendingLoad(MI))
2283  CopyOpc = (MemSize == 1) ? Hexagon::A2_zxtb : Hexagon::A2_zxth;
2284  CopyOut = BuildMI(B, It, DL, HII.get(CopyOpc), DstR)
2285  .addReg(FoundR, getKillRegState(&MI == &EI));
2286  }
2287  IM.replaceInstr(&MI, CopyOut);
2288  B.erase(It);
2289  }
2290 
2291  // Update the dead map.
2292  HexagonBlockRanges::RegisterRef FoundRR = { FoundR, 0 };
2293  for (auto RR : HexagonBlockRanges::expandToSubRegs(FoundRR, MRI, HRI))
2294  DM[RR].subtract(Range);
2295  } // for Range in range list
2296  }
2297  }
2298 }
2299 
2300 void HexagonFrameLowering::expandAlloca(MachineInstr *AI,
2301  const HexagonInstrInfo &HII, unsigned SP, unsigned CF) const {
2302  MachineBasicBlock &MB = *AI->getParent();
2303  DebugLoc DL = AI->getDebugLoc();
2304  unsigned A = AI->getOperand(2).getImm();
2305 
2306  // Have
2307  // Rd = alloca Rs, #A
2308  //
2309  // If Rs and Rd are different registers, use this sequence:
2310  // Rd = sub(r29, Rs)
2311  // r29 = sub(r29, Rs)
2312  // Rd = and(Rd, #-A) ; if necessary
2313  // r29 = and(r29, #-A) ; if necessary
2314  // Rd = add(Rd, #CF) ; CF size aligned to at most A
2315  // otherwise, do
2316  // Rd = sub(r29, Rs)
2317  // Rd = and(Rd, #-A) ; if necessary
2318  // r29 = Rd
2319  // Rd = add(Rd, #CF) ; CF size aligned to at most A
2320 
2321  MachineOperand &RdOp = AI->getOperand(0);
2322  MachineOperand &RsOp = AI->getOperand(1);
2323  unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg();
2324 
2325  // Rd = sub(r29, Rs)
2326  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), Rd)
2327  .addReg(SP)
2328  .addReg(Rs);
2329  if (Rs != Rd) {
2330  // r29 = sub(r29, Rs)
2331  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), SP)
2332  .addReg(SP)
2333  .addReg(Rs);
2334  }
2335  if (A > 8) {
2336  // Rd = and(Rd, #-A)
2337  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), Rd)
2338  .addReg(Rd)
2339  .addImm(-int64_t(A));
2340  if (Rs != Rd)
2341  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), SP)
2342  .addReg(SP)
2343  .addImm(-int64_t(A));
2344  }
2345  if (Rs == Rd) {
2346  // r29 = Rd
2347  BuildMI(MB, AI, DL, HII.get(TargetOpcode::COPY), SP)
2348  .addReg(Rd);
2349  }
2350  if (CF > 0) {
2351  // Rd = add(Rd, #CF)
2352  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_addi), Rd)
2353  .addReg(Rd)
2354  .addImm(CF);
2355  }
2356 }
2357 
2359  const MachineFrameInfo &MFI = MF.getFrameInfo();
2360  if (!MFI.hasVarSizedObjects())
2361  return false;
2362  unsigned MaxA = MFI.getMaxAlignment();
2363  if (MaxA <= getStackAlignment())
2364  return false;
2365  return true;
2366 }
2367 
2369  const MachineFunction &MF) const {
2370  for (auto &B : MF)
2371  for (auto &I : B)
2372  if (I.getOpcode() == Hexagon::PS_aligna)
2373  return &I;
2374  return nullptr;
2375 }
2376 
2377 /// Adds all callee-saved registers as implicit uses or defs to the
2378 /// instruction.
2379 void HexagonFrameLowering::addCalleeSaveRegistersAsImpOperand(MachineInstr *MI,
2380  const CSIVect &CSI, bool IsDef, bool IsKill) const {
2381  // Add the callee-saved registers as implicit uses.
2382  for (auto &R : CSI)
2383  MI->addOperand(MachineOperand::CreateReg(R.getReg(), IsDef, true, IsKill));
2384 }
2385 
2386 /// Determine whether the callee-saved register saves and restores should
2387 /// be generated via inline code. If this function returns "true", inline
2388 /// code will be generated. If this function returns "false", additional
2389 /// checks are performed, which may still lead to the inline code.
2390 bool HexagonFrameLowering::shouldInlineCSR(const MachineFunction &MF,
2391  const CSIVect &CSI) const {
2393  return true;
2394  if (!hasFP(MF))
2395  return true;
2396  if (!isOptSize(MF) && !isMinSize(MF))
2398  return true;
2399 
2400  // Check if CSI only has double registers, and if the registers form
2401  // a contiguous block starting from D8.
2402  BitVector Regs(Hexagon::NUM_TARGET_REGS);
2403  for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
2404  unsigned R = CSI[i].getReg();
2405  if (!Hexagon::DoubleRegsRegClass.contains(R))
2406  return true;
2407  Regs[R] = true;
2408  }
2409  int F = Regs.find_first();
2410  if (F != Hexagon::D8)
2411  return true;
2412  while (F >= 0) {
2413  int N = Regs.find_next(F);
2414  if (N >= 0 && N != F+1)
2415  return true;
2416  F = N;
2417  }
2418 
2419  return false;
2420 }
2421 
2422 bool HexagonFrameLowering::useSpillFunction(const MachineFunction &MF,
2423  const CSIVect &CSI) const {
2424  if (shouldInlineCSR(MF, CSI))
2425  return false;
2426  unsigned NumCSI = CSI.size();
2427  if (NumCSI <= 1)
2428  return false;
2429 
2430  unsigned Threshold = isOptSize(MF) ? SpillFuncThresholdOs
2432  return Threshold < NumCSI;
2433 }
2434 
2435 bool HexagonFrameLowering::useRestoreFunction(const MachineFunction &MF,
2436  const CSIVect &CSI) const {
2437  if (shouldInlineCSR(MF, CSI))
2438  return false;
2439  // The restore functions do a bit more than just restoring registers.
2440  // The non-returning versions will go back directly to the caller's
2441  // caller, others will clean up the stack frame in preparation for
2442  // a tail call. Using them can still save code size even if only one
2443  // register is getting restores. Make the decision based on -Oz:
2444  // using -Os will use inline restore for a single register.
2445  if (isMinSize(MF))
2446  return true;
2447  unsigned NumCSI = CSI.size();
2448  if (NumCSI <= 1)
2449  return false;
2450 
2451  unsigned Threshold = isOptSize(MF) ? SpillFuncThresholdOs-1
2453  return Threshold < NumCSI;
2454 }
2455 
2456 bool HexagonFrameLowering::mayOverflowFrameOffset(MachineFunction &MF) const {
2457  unsigned StackSize = MF.getFrameInfo().estimateStackSize(MF);
2458  auto &HST = MF.getSubtarget<HexagonSubtarget>();
2459  // A fairly simplistic guess as to whether a potential load/store to a
2460  // stack location could require an extra register.
2461  if (HST.useHVXOps() && StackSize > 256)
2462  return true;
2463 
2464  // Check if the function has store-immediate instructions that access
2465  // the stack. Since the offset field is not extendable, if the stack
2466  // size exceeds the offset limit (6 bits, shifted), the stores will
2467  // require a new base register.
2468  bool HasImmStack = false;
2469  unsigned MinLS = ~0u; // Log_2 of the memory access size.
2470 
2471  for (const MachineBasicBlock &B : MF) {
2472  for (const MachineInstr &MI : B) {
2473  unsigned LS = 0;
2474  switch (MI.getOpcode()) {
2475  case Hexagon::S4_storeirit_io:
2476  case Hexagon::S4_storeirif_io:
2477  case Hexagon::S4_storeiri_io:
2478  ++LS;
2480  case Hexagon::S4_storeirht_io:
2481  case Hexagon::S4_storeirhf_io:
2482  case Hexagon::S4_storeirh_io:
2483  ++LS;
2485  case Hexagon::S4_storeirbt_io:
2486  case Hexagon::S4_storeirbf_io:
2487  case Hexagon::S4_storeirb_io:
2488  if (MI.getOperand(0).isFI())
2489  HasImmStack = true;
2490  MinLS = std::min(MinLS, LS);
2491  break;
2492  }
2493  }
2494  }
2495 
2496  if (HasImmStack)
2497  return !isUInt<6>(StackSize >> MinLS);
2498 
2499  return false;
2500 }
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:372
uint64_t CallInst * C
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
BitVector & set()
Definition: BitVector.h:398
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:619
instr_iterator instr_end()
bool hasDebugInfo() const
Returns true if valid debug info is present.
void mapLocalFrameObject(int ObjectIndex, int64_t Offset)
Map a frame index into the local object block.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
void stepForward(const MachineInstr &MI, SmallVectorImpl< std::pair< unsigned, const MachineOperand *>> &Clobbers)
Simulates liveness when stepping forward over an instruction(bundle).
static cl::opt< int > SpillFuncThresholdOs("spill-func-threshold-Os", cl::Hidden, cl::desc("Specify Os spill func threshold"), cl::init(1), cl::ZeroOrMore)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
size_type size() const
Determine the number of elements in the SetVector.
Definition: SetVector.h:78
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
INITIALIZE_PASS(HexagonCallFrameInformation, "hexagon-cfi", "Hexagon call frame information", false, false) FunctionPass *llvm
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID&#39;s allocated.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index...
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
MachineBasicBlock * findNearestCommonDominator(MachineBasicBlock *A, MachineBasicBlock *B)
bool isDeadObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a dead object.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:377
static Optional< MachineBasicBlock::iterator > findCFILocation(MachineBasicBlock &B)
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:162
unsigned getReg() const
getReg - Returns the register number.
int64_t getLocalFrameSize() const
Get the size of the local object blob.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:487
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned Reg
static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI)
unsigned getSubReg() const
static RegisterSet expandToSubRegs(RegisterRef R, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI)
static const MCPhysReg VRegs[32]
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:307
Hexagon target-specific information for each MachineFunction.
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
F(f)
MachineModuleInfo & getMMI() const
static const char * getSpillFunctionFor(unsigned MaxReg, SpillKind SpillType, bool Stkchk=false)
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:685
#define R2(n)
static unsigned SpillOptCount
static cl::opt< int > SpillFuncThreshold("spill-func-threshold", cl::Hidden, cl::desc("Specify O2(not Os) spill func threshold"), cl::init(6), cl::ZeroOrMore)
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:453
static cl::opt< unsigned > SpillOptMax("spill-opt-max", cl::Hidden, cl::init(std::numeric_limits< unsigned >::max()))
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
return AArch64::GPR64RegClass contains(Reg)
iterator_range< succ_iterator > successors()
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
std::map< RegisterRef, RangeList > RegToRangeMap
bool isEHReturnCalleeSaveReg(unsigned Reg) const
unsigned getSpillAlignment(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class...
void add(IndexType Start, IndexType End, bool Fixed, bool TiedEnd)
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index...
void setLocalFrameSize(int64_t sz)
Set the size of the local object blob.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
void setUseLocalStackAllocationBlock(bool v)
setUseLocalStackAllocationBlock - Set whether the local allocation blob should be allocated together ...
MCSuperRegIterator enumerates all super-registers of Reg.
bool contains(unsigned Reg) const
Returns true if register Reg is contained in the set.
Definition: LivePhysRegs.h:106
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Definition: BitVector.h:332
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
static cl::opt< bool > EnableStackOVFSanitizer("enable-stackovf-sanitizer", cl::Hidden, cl::desc("Enable runtime checks for stack overflow."), cl::init(false), cl::ZeroOrMore)
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
Definition: BitVector.h:340
static cl::opt< bool > EnableShrinkWrapping("hexagon-shrink-frame", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable stack frame shrink wrapping"))
This file contains the simple types necessary to represent the attributes associated with functions a...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:403
static unsigned getMax32BitSubRegister(unsigned Reg, const TargetRegisterInfo &TRI, bool hireg=true)
Map a register pair Reg to the subregister that has the greater "number", i.e.
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:400
const MachineInstr * getAlignaInstr(const MachineFunction &MF) const
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:142
static bool isMinSize(const MachineFunction &MF)
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
const MCContext & getContext() const
const RegList & Regs
static bool hasTailCall(const MachineBasicBlock &MBB)
Returns true if MBB has a machine instructions that indicates a tail call in the block.
void setLocalFrameMaxAlign(unsigned Align)
Required alignment of the local object blob, which is the strictest alignment of any object in it...
int getObjectIndexEnd() const
Return one past the maximum frame object index.
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they&#39;re not in a MachineFuncti...
MachineBasicBlock * findNearestCommonDominator(MachineBasicBlock *A, MachineBasicBlock *B)
findNearestCommonDominator - Find nearest common dominator basic block for basic block A and B...
const MCPhysReg * getCallerSavedRegs(const MachineFunction *MF, const TargetRegisterClass *RC) const
static bool needsStackFrame(const MachineBasicBlock &MBB, const BitVector &CSR, const HexagonRegisterInfo &HRI)
Checks if the basic block contains any instruction that needs a stack frame to be already in place...
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
Perform most of the PEI work here:
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
unsigned getKillRegState(bool B)
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
static cl::opt< bool > EliminateFramePointer("hexagon-fp-elim", cl::init(true), cl::Hidden, cl::desc("Refrain from using FP whenever possible"))
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:615
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
A and B are either alignments or offsets.
Definition: MathExtras.h:610
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:806
#define P(N)
static bool needToReserveScavengingSpillSlots(MachineFunction &MF, const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC)
Returns true if there are no caller-saved registers available in class RC.
static bool isOptSize(const MachineFunction &MF)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:410
static cl::opt< unsigned > NumberScavengerSlots("number-scavenger-slots", cl::Hidden, cl::desc("Set the number of scavenger slots"), cl::init(2), cl::ZeroOrMore)
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
This file declares the machine register scavenger class.
MachineBasicBlock * getBlockNumbered(unsigned N) const
getBlockNumbered - MachineBasicBlocks are automatically numbered when they are inserted into the mach...
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
Definition: MCContext.cpp:217
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
unsigned const MachineRegisterInfo * MRI
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
Definition: MCDwarf.h:460
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:429
static cl::opt< bool > DisableDeallocRet("disable-hexagon-dealloc-ret", cl::Hidden, cl::desc("Disable Dealloc Return for Hexagon target"))
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
void setStackSize(uint64_t Size)
Set the size of the stack.
void addLiveIns(const MachineBasicBlock &MBB)
Adds all live-in registers of basic block MBB.
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions...
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:135
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
MCRegAliasIterator enumerates all registers aliasing Reg.
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
bool optForSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Definition: Function.h:584
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
self_iterator getIterator()
Definition: ilist_node.h:82
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:181
auto find_if(R &&Range, UnaryPredicate P) -> decltype(adl_begin(Range))
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1046
int CreateSpillStackObject(uint64_t Size, unsigned Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MachineBasicBlock & front() const
MCSubRegIterator enumerates all sub-registers of Reg.
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
size_t size() const
Definition: SmallVector.h:53
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
IndexType getIndex(MachineInstr *MI) const
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
static MachineInstr * getReturn(MachineBasicBlock &MBB)
Returns the "return" instruction from this block, or nullptr if there isn&#39;t any.
static bool hasReturn(const MachineBasicBlock &MBB)
Returns true if MBB contains an instruction that returns.
The memory access writes data.
static cl::opt< unsigned > ShrinkLimit("shrink-frame-limit", cl::init(std::numeric_limits< unsigned >::max()), cl::Hidden, cl::ZeroOrMore, cl::desc("Max count of stack frame shrink-wraps"))
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
PostDominatorTree Class - Concrete subclass of DominatorTree that is used to compute the post-dominat...
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:847
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
unsigned estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI) const override
assignCalleeSavedSpillSlots - Allows target to override spill slot assignment logic.
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
bool needsUnwindTableEntry() const
True if this function needs an unwind table.
Definition: Function.h:559
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
bool isPhysRegUsed(unsigned PhysReg) const
Return true if the specified register is modified or read in this function.
static cl::opt< bool > EnableSaveRestoreLong("enable-save-restore-long", cl::Hidden, cl::desc("Enable long calls for save-restore stubs."), cl::init(false), cl::ZeroOrMore)
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
FunctionPass * createHexagonCallFrameInformation()
bool runOnMachineFunction(MachineFunction &F) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:248
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
MachineFunctionProperties & set(Property P)
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
RegToRangeMap computeLiveMap(InstrIndexMap &IndexMap)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
static bool isRestoreCall(unsigned Opc)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:49
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:56
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
bool isPositionIndependent() const
static cl::opt< bool > OptimizeSpillSlots("hexagon-opt-spill", cl::Hidden, cl::init(true), cl::desc("Optimize spill slots"))
TargetOptions Options
Definition: TargetMachine.h:98
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
void setMaxCallFrameSize(unsigned S)
void insertCFIInstructions(MachineFunction &MF) const
unsigned getLocalFrameMaxAlign() const
Return the required alignment of the local object blob.
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
bool optForMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:581
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
RegToRangeMap computeDeadMap(InstrIndexMap &IndexMap, RegToRangeMap &LiveMap)
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
static int const Threshold
TODO: Write a new FunctionPass AliasAnalysis so that it can keep a cache.
const unsigned Kind
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:793
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const HexagonInstrInfo * getInstrInfo() const override
rpo Deduce function attributes in RPO
A vector that has set insertion semantics.
Definition: SetVector.h:41
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
static bool isOptNone(const MachineFunction &MF)
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
IRTranslator LLVM IR MI
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:238
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:39
void initializeHexagonCallFrameInformationPass(PassRegistry &)
#define LLVM_DEBUG(X)
Definition: Debug.h:123
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:408
void setObjectAlignment(int ObjectIdx, unsigned Align)
setObjectAlignment - Change the alignment of the specified stack object.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
bool needsAligna(const MachineFunction &MF) const
static unsigned getMaxCalleeSavedReg(const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo &TRI)
Returns the callee saved register with the largest id in the vector.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Statically lint checks LLVM IR
Definition: Lint.cpp:193
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
Properties which a MachineFunction may have at a given point in time.
This class contains meta information specific to a module.
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:165