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HexagonFrameLowering.cpp
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1 //===- HexagonFrameLowering.cpp - Define frame lowering -------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //
9 //===----------------------------------------------------------------------===//
10 
11 #include "HexagonFrameLowering.h"
12 #include "HexagonBlockRanges.h"
13 #include "HexagonInstrInfo.h"
15 #include "HexagonRegisterInfo.h"
16 #include "HexagonSubtarget.h"
17 #include "HexagonTargetMachine.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/ADT/None.h"
22 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/SetVector.h"
25 #include "llvm/ADT/SmallSet.h"
26 #include "llvm/ADT/SmallVector.h"
42 #include "llvm/IR/Attributes.h"
43 #include "llvm/IR/DebugLoc.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/MC/MCDwarf.h"
46 #include "llvm/MC/MCRegisterInfo.h"
47 #include "llvm/Pass.h"
48 #include "llvm/Support/CodeGen.h"
50 #include "llvm/Support/Compiler.h"
51 #include "llvm/Support/Debug.h"
57 #include <algorithm>
58 #include <cassert>
59 #include <cstdint>
60 #include <iterator>
61 #include <limits>
62 #include <map>
63 #include <utility>
64 #include <vector>
65 
66 #define DEBUG_TYPE "hexagon-pei"
67 
68 // Hexagon stack frame layout as defined by the ABI:
69 //
70 // Incoming arguments
71 // passed via stack
72 // |
73 // |
74 // SP during function's FP during function's |
75 // +-- runtime (top of stack) runtime (bottom) --+ |
76 // | | |
77 // --++---------------------+------------------+-----------------++-+-------
78 // | parameter area for | variable-size | fixed-size |LR| arg
79 // | called functions | local objects | local objects |FP|
80 // --+----------------------+------------------+-----------------+--+-------
81 // <- size known -> <- size unknown -> <- size known ->
82 //
83 // Low address High address
84 //
85 // <--- stack growth
86 //
87 //
88 // - In any circumstances, the outgoing function arguments are always accessi-
89 // ble using the SP, and the incoming arguments are accessible using the FP.
90 // - If the local objects are not aligned, they can always be accessed using
91 // the FP.
92 // - If there are no variable-sized objects, the local objects can always be
93 // accessed using the SP, regardless whether they are aligned or not. (The
94 // alignment padding will be at the bottom of the stack (highest address),
95 // and so the offset with respect to the SP will be known at the compile-
96 // -time.)
97 //
98 // The only complication occurs if there are both, local aligned objects, and
99 // dynamically allocated (variable-sized) objects. The alignment pad will be
100 // placed between the FP and the local objects, thus preventing the use of the
101 // FP to access the local objects. At the same time, the variable-sized objects
102 // will be between the SP and the local objects, thus introducing an unknown
103 // distance from the SP to the locals.
104 //
105 // To avoid this problem, a new register is created that holds the aligned
106 // address of the bottom of the stack, referred in the sources as AP (aligned
107 // pointer). The AP will be equal to "FP-p", where "p" is the smallest pad
108 // that aligns AP to the required boundary (a maximum of the alignments of
109 // all stack objects, fixed- and variable-sized). All local objects[1] will
110 // then use AP as the base pointer.
111 // [1] The exception is with "fixed" stack objects. "Fixed" stack objects get
112 // their name from being allocated at fixed locations on the stack, relative
113 // to the FP. In the presence of dynamic allocation and local alignment, such
114 // objects can only be accessed through the FP.
115 //
116 // Illustration of the AP:
117 // FP --+
118 // |
119 // ---------------+---------------------+-----+-----------------------++-+--
120 // Rest of the | Local stack objects | Pad | Fixed stack objects |LR|
121 // stack frame | (aligned) | | (CSR, spills, etc.) |FP|
122 // ---------------+---------------------+-----+-----------------+-----+--+--
123 // |<-- Multiple of the -->|
124 // stack alignment +-- AP
125 //
126 // The AP is set up at the beginning of the function. Since it is not a dedi-
127 // cated (reserved) register, it needs to be kept live throughout the function
128 // to be available as the base register for local object accesses.
129 // Normally, an address of a stack objects is obtained by a pseudo-instruction
130 // PS_fi. To access local objects with the AP register present, a different
131 // pseudo-instruction needs to be used: PS_fia. The PS_fia takes one extra
132 // argument compared to PS_fi: the first input register is the AP register.
133 // This keeps the register live between its definition and its uses.
134 
135 // The AP register is originally set up using pseudo-instruction PS_aligna:
136 // AP = PS_aligna A
137 // where
138 // A - required stack alignment
139 // The alignment value must be the maximum of all alignments required by
140 // any stack object.
141 
142 // The dynamic allocation uses a pseudo-instruction PS_alloca:
143 // Rd = PS_alloca Rs, A
144 // where
145 // Rd - address of the allocated space
146 // Rs - minimum size (the actual allocated can be larger to accommodate
147 // alignment)
148 // A - required alignment
149 
150 using namespace llvm;
151 
152 static cl::opt<bool> DisableDeallocRet("disable-hexagon-dealloc-ret",
153  cl::Hidden, cl::desc("Disable Dealloc Return for Hexagon target"));
154 
155 static cl::opt<unsigned> NumberScavengerSlots("number-scavenger-slots",
156  cl::Hidden, cl::desc("Set the number of scavenger slots"), cl::init(2),
158 
159 static cl::opt<int> SpillFuncThreshold("spill-func-threshold",
160  cl::Hidden, cl::desc("Specify O2(not Os) spill func threshold"),
162 
163 static cl::opt<int> SpillFuncThresholdOs("spill-func-threshold-Os",
164  cl::Hidden, cl::desc("Specify Os spill func threshold"),
166 
167 static cl::opt<bool> EnableStackOVFSanitizer("enable-stackovf-sanitizer",
168  cl::Hidden, cl::desc("Enable runtime checks for stack overflow."),
169  cl::init(false), cl::ZeroOrMore);
170 
171 static cl::opt<bool> EnableShrinkWrapping("hexagon-shrink-frame",
173  cl::desc("Enable stack frame shrink wrapping"));
174 
175 static cl::opt<unsigned> ShrinkLimit("shrink-frame-limit",
177  cl::desc("Max count of stack frame shrink-wraps"));
178 
179 static cl::opt<bool> EnableSaveRestoreLong("enable-save-restore-long",
180  cl::Hidden, cl::desc("Enable long calls for save-restore stubs."),
181  cl::init(false), cl::ZeroOrMore);
182 
183 static cl::opt<bool> EliminateFramePointer("hexagon-fp-elim", cl::init(true),
184  cl::Hidden, cl::desc("Refrain from using FP whenever possible"));
185 
186 static cl::opt<bool> OptimizeSpillSlots("hexagon-opt-spill", cl::Hidden,
187  cl::init(true), cl::desc("Optimize spill slots"));
188 
189 #ifndef NDEBUG
190 static cl::opt<unsigned> SpillOptMax("spill-opt-max", cl::Hidden,
192 static unsigned SpillOptCount = 0;
193 #endif
194 
195 namespace llvm {
196 
199 
200 } // end namespace llvm
201 
202 namespace {
203 
204  class HexagonCallFrameInformation : public MachineFunctionPass {
205  public:
206  static char ID;
207 
208  HexagonCallFrameInformation() : MachineFunctionPass(ID) {
211  }
212 
213  bool runOnMachineFunction(MachineFunction &MF) override;
214 
215  MachineFunctionProperties getRequiredProperties() const override {
218  }
219  };
220 
222 
223 } // end anonymous namespace
224 
225 bool HexagonCallFrameInformation::runOnMachineFunction(MachineFunction &MF) {
226  auto &HFI = *MF.getSubtarget<HexagonSubtarget>().getFrameLowering();
227  bool NeedCFI = MF.getMMI().hasDebugInfo() ||
229 
230  if (!NeedCFI)
231  return false;
232  HFI.insertCFIInstructions(MF);
233  return true;
234 }
235 
236 INITIALIZE_PASS(HexagonCallFrameInformation, "hexagon-cfi",
237  "Hexagon call frame information", false, false)
238 
240  return new HexagonCallFrameInformation();
241 }
242 
243 /// Map a register pair Reg to the subregister that has the greater "number",
244 /// i.e. D3 (aka R7:6) will be mapped to R7, etc.
245 static unsigned getMax32BitSubRegister(unsigned Reg,
246  const TargetRegisterInfo &TRI,
247  bool hireg = true) {
248  if (Reg < Hexagon::D0 || Reg > Hexagon::D15)
249  return Reg;
250 
251  unsigned RegNo = 0;
252  for (MCSubRegIterator SubRegs(Reg, &TRI); SubRegs.isValid(); ++SubRegs) {
253  if (hireg) {
254  if (*SubRegs > RegNo)
255  RegNo = *SubRegs;
256  } else {
257  if (!RegNo || *SubRegs < RegNo)
258  RegNo = *SubRegs;
259  }
260  }
261  return RegNo;
262 }
263 
264 /// Returns the callee saved register with the largest id in the vector.
265 static unsigned getMaxCalleeSavedReg(const std::vector<CalleeSavedInfo> &CSI,
266  const TargetRegisterInfo &TRI) {
267  static_assert(Hexagon::R1 > 0,
268  "Assume physical registers are encoded as positive integers");
269  if (CSI.empty())
270  return 0;
271 
272  unsigned Max = getMax32BitSubRegister(CSI[0].getReg(), TRI);
273  for (unsigned I = 1, E = CSI.size(); I < E; ++I) {
274  unsigned Reg = getMax32BitSubRegister(CSI[I].getReg(), TRI);
275  if (Reg > Max)
276  Max = Reg;
277  }
278  return Max;
279 }
280 
281 /// Checks if the basic block contains any instruction that needs a stack
282 /// frame to be already in place.
283 static bool needsStackFrame(const MachineBasicBlock &MBB, const BitVector &CSR,
284  const HexagonRegisterInfo &HRI) {
285  for (auto &I : MBB) {
286  const MachineInstr *MI = &I;
287  if (MI->isCall())
288  return true;
289  unsigned Opc = MI->getOpcode();
290  switch (Opc) {
291  case Hexagon::PS_alloca:
292  case Hexagon::PS_aligna:
293  return true;
294  default:
295  break;
296  }
297  // Check individual operands.
298  for (const MachineOperand &MO : MI->operands()) {
299  // While the presence of a frame index does not prove that a stack
300  // frame will be required, all frame indexes should be within alloc-
301  // frame/deallocframe. Otherwise, the code that translates a frame
302  // index into an offset would have to be aware of the placement of
303  // the frame creation/destruction instructions.
304  if (MO.isFI())
305  return true;
306  if (MO.isReg()) {
307  unsigned R = MO.getReg();
308  // Virtual registers will need scavenging, which then may require
309  // a stack slot.
311  return true;
312  for (MCSubRegIterator S(R, &HRI, true); S.isValid(); ++S)
313  if (CSR[*S])
314  return true;
315  continue;
316  }
317  if (MO.isRegMask()) {
318  // A regmask would normally have all callee-saved registers marked
319  // as preserved, so this check would not be needed, but in case of
320  // ever having other regmasks (for other calling conventions),
321  // make sure they would be processed correctly.
322  const uint32_t *BM = MO.getRegMask();
323  for (int x = CSR.find_first(); x >= 0; x = CSR.find_next(x)) {
324  unsigned R = x;
325  // If this regmask does not preserve a CSR, a frame will be needed.
326  if (!(BM[R/32] & (1u << (R%32))))
327  return true;
328  }
329  }
330  }
331  }
332  return false;
333 }
334 
335  /// Returns true if MBB has a machine instructions that indicates a tail call
336  /// in the block.
337 static bool hasTailCall(const MachineBasicBlock &MBB) {
339  unsigned RetOpc = I->getOpcode();
340  return RetOpc == Hexagon::PS_tailcall_i || RetOpc == Hexagon::PS_tailcall_r;
341 }
342 
343 /// Returns true if MBB contains an instruction that returns.
344 static bool hasReturn(const MachineBasicBlock &MBB) {
345  for (auto I = MBB.getFirstTerminator(), E = MBB.end(); I != E; ++I)
346  if (I->isReturn())
347  return true;
348  return false;
349 }
350 
351 /// Returns the "return" instruction from this block, or nullptr if there
352 /// isn't any.
354  for (auto &I : MBB)
355  if (I.isReturn())
356  return &I;
357  return nullptr;
358 }
359 
360 static bool isRestoreCall(unsigned Opc) {
361  switch (Opc) {
362  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
363  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
364  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT:
365  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC:
366  case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT:
367  case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC:
368  case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4:
369  case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC:
370  return true;
371  }
372  return false;
373 }
374 
375 static inline bool isOptNone(const MachineFunction &MF) {
376  return MF.getFunction()->hasFnAttribute(Attribute::OptimizeNone) ||
378 }
379 
380 static inline bool isOptSize(const MachineFunction &MF) {
381  const Function &F = *MF.getFunction();
382  return F.optForSize() && !F.optForMinSize();
383 }
384 
385 static inline bool isMinSize(const MachineFunction &MF) {
386  return MF.getFunction()->optForMinSize();
387 }
388 
389 /// Implements shrink-wrapping of the stack frame. By default, stack frame
390 /// is created in the function entry block, and is cleaned up in every block
391 /// that returns. This function finds alternate blocks: one for the frame
392 /// setup (prolog) and one for the cleanup (epilog).
393 void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF,
394  MachineBasicBlock *&PrologB, MachineBasicBlock *&EpilogB) const {
395  static unsigned ShrinkCounter = 0;
396 
397  if (ShrinkLimit.getPosition()) {
398  if (ShrinkCounter >= ShrinkLimit)
399  return;
400  ShrinkCounter++;
401  }
402 
403  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
404 
406  MDT.runOnMachineFunction(MF);
408  MPT.runOnMachineFunction(MF);
409 
410  using UnsignedMap = DenseMap<unsigned, unsigned>;
412 
413  UnsignedMap RPO;
414  RPOTType RPOT(&MF);
415  unsigned RPON = 0;
416  for (RPOTType::rpo_iterator I = RPOT.begin(), E = RPOT.end(); I != E; ++I)
417  RPO[(*I)->getNumber()] = RPON++;
418 
419  // Don't process functions that have loops, at least for now. Placement
420  // of prolog and epilog must take loop structure into account. For simpli-
421  // city don't do it right now.
422  for (auto &I : MF) {
423  unsigned BN = RPO[I.getNumber()];
424  for (auto SI = I.succ_begin(), SE = I.succ_end(); SI != SE; ++SI) {
425  // If found a back-edge, return.
426  if (RPO[(*SI)->getNumber()] <= BN)
427  return;
428  }
429  }
430 
431  // Collect the set of blocks that need a stack frame to execute. Scan
432  // each block for uses/defs of callee-saved registers, calls, etc.
434  BitVector CSR(Hexagon::NUM_TARGET_REGS);
435  for (const MCPhysReg *P = HRI.getCalleeSavedRegs(&MF); *P; ++P)
436  for (MCSubRegIterator S(*P, &HRI, true); S.isValid(); ++S)
437  CSR[*S] = true;
438 
439  for (auto &I : MF)
440  if (needsStackFrame(I, CSR, HRI))
441  SFBlocks.push_back(&I);
442 
443  DEBUG({
444  dbgs() << "Blocks needing SF: {";
445  for (auto &B : SFBlocks)
446  dbgs() << " BB#" << B->getNumber();
447  dbgs() << " }\n";
448  });
449  // No frame needed?
450  if (SFBlocks.empty())
451  return;
452 
453  // Pick a common dominator and a common post-dominator.
454  MachineBasicBlock *DomB = SFBlocks[0];
455  for (unsigned i = 1, n = SFBlocks.size(); i < n; ++i) {
456  DomB = MDT.findNearestCommonDominator(DomB, SFBlocks[i]);
457  if (!DomB)
458  break;
459  }
460  MachineBasicBlock *PDomB = SFBlocks[0];
461  for (unsigned i = 1, n = SFBlocks.size(); i < n; ++i) {
462  PDomB = MPT.findNearestCommonDominator(PDomB, SFBlocks[i]);
463  if (!PDomB)
464  break;
465  }
466  DEBUG({
467  dbgs() << "Computed dom block: BB#";
468  if (DomB) dbgs() << DomB->getNumber();
469  else dbgs() << "<null>";
470  dbgs() << ", computed pdom block: BB#";
471  if (PDomB) dbgs() << PDomB->getNumber();
472  else dbgs() << "<null>";
473  dbgs() << "\n";
474  });
475  if (!DomB || !PDomB)
476  return;
477 
478  // Make sure that DomB dominates PDomB and PDomB post-dominates DomB.
479  if (!MDT.dominates(DomB, PDomB)) {
480  DEBUG(dbgs() << "Dom block does not dominate pdom block\n");
481  return;
482  }
483  if (!MPT.dominates(PDomB, DomB)) {
484  DEBUG(dbgs() << "PDom block does not post-dominate dom block\n");
485  return;
486  }
487 
488  // Finally, everything seems right.
489  PrologB = DomB;
490  EpilogB = PDomB;
491 }
492 
493 /// Perform most of the PEI work here:
494 /// - saving/restoring of the callee-saved registers,
495 /// - stack frame creation and destruction.
496 /// Normally, this work is distributed among various functions, but doing it
497 /// in one place allows shrink-wrapping of the stack frame.
499  MachineBasicBlock &MBB) const {
500  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
501 
502  MachineFrameInfo &MFI = MF.getFrameInfo();
503  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
504 
505  MachineBasicBlock *PrologB = &MF.front(), *EpilogB = nullptr;
507  findShrunkPrologEpilog(MF, PrologB, EpilogB);
508 
509  bool PrologueStubs = false;
510  insertCSRSpillsInBlock(*PrologB, CSI, HRI, PrologueStubs);
511  insertPrologueInBlock(*PrologB, PrologueStubs);
512  updateEntryPaths(MF, *PrologB);
513 
514  if (EpilogB) {
515  insertCSRRestoresInBlock(*EpilogB, CSI, HRI);
516  insertEpilogueInBlock(*EpilogB);
517  } else {
518  for (auto &B : MF)
519  if (B.isReturnBlock())
520  insertCSRRestoresInBlock(B, CSI, HRI);
521 
522  for (auto &B : MF)
523  if (B.isReturnBlock())
524  insertEpilogueInBlock(B);
525 
526  for (auto &B : MF) {
527  if (B.empty())
528  continue;
529  MachineInstr *RetI = getReturn(B);
530  if (!RetI || isRestoreCall(RetI->getOpcode()))
531  continue;
532  for (auto &R : CSI)
533  RetI->addOperand(MachineOperand::CreateReg(R.getReg(), false, true));
534  }
535  }
536 
537  if (EpilogB) {
538  // If there is an epilog block, it may not have a return instruction.
539  // In such case, we need to add the callee-saved registers as live-ins
540  // in all blocks on all paths from the epilog to any return block.
541  unsigned MaxBN = MF.getNumBlockIDs();
542  BitVector DoneT(MaxBN+1), DoneF(MaxBN+1), Path(MaxBN+1);
543  updateExitPaths(*EpilogB, *EpilogB, DoneT, DoneF, Path);
544  }
545 }
546 
547 void HexagonFrameLowering::insertPrologueInBlock(MachineBasicBlock &MBB,
548  bool PrologueStubs) const {
549  MachineFunction &MF = *MBB.getParent();
550  MachineFrameInfo &MFI = MF.getFrameInfo();
551  auto &HST = MF.getSubtarget<HexagonSubtarget>();
552  auto &HII = *HST.getInstrInfo();
553  auto &HRI = *HST.getRegisterInfo();
554 
555  unsigned MaxAlign = std::max(MFI.getMaxAlignment(), getStackAlignment());
556 
557  // Calculate the total stack frame size.
558  // Get the number of bytes to allocate from the FrameInfo.
559  unsigned FrameSize = MFI.getStackSize();
560  // Round up the max call frame size to the max alignment on the stack.
561  unsigned MaxCFA = alignTo(MFI.getMaxCallFrameSize(), MaxAlign);
562  MFI.setMaxCallFrameSize(MaxCFA);
563 
564  FrameSize = MaxCFA + alignTo(FrameSize, MaxAlign);
565  MFI.setStackSize(FrameSize);
566 
567  bool AlignStack = (MaxAlign > getStackAlignment());
568 
569  // Get the number of bytes to allocate from the FrameInfo.
570  unsigned NumBytes = MFI.getStackSize();
571  unsigned SP = HRI.getStackRegister();
572  unsigned MaxCF = MFI.getMaxCallFrameSize();
573  MachineBasicBlock::iterator InsertPt = MBB.begin();
574 
576  for (auto &MBB : MF)
577  for (auto &MI : MBB)
578  if (MI.getOpcode() == Hexagon::PS_alloca)
579  AdjustRegs.push_back(&MI);
580 
581  for (auto MI : AdjustRegs) {
582  assert((MI->getOpcode() == Hexagon::PS_alloca) && "Expected alloca");
583  expandAlloca(MI, HII, SP, MaxCF);
584  MI->eraseFromParent();
585  }
586 
587  DebugLoc dl = MBB.findDebugLoc(InsertPt);
588 
589  if (hasFP(MF)) {
590  insertAllocframe(MBB, InsertPt, NumBytes);
591  if (AlignStack) {
592  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_andir), SP)
593  .addReg(SP)
594  .addImm(-int64_t(MaxAlign));
595  }
596  // If the stack-checking is enabled, and we spilled the callee-saved
597  // registers inline (i.e. did not use a spill function), then call
598  // the stack checker directly.
599  if (EnableStackOVFSanitizer && !PrologueStubs)
600  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::PS_call_stk))
601  .addExternalSymbol("__runtime_stack_check");
602  } else if (NumBytes > 0) {
603  assert(alignTo(NumBytes, 8) == NumBytes);
604  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
605  .addReg(SP)
606  .addImm(-int(NumBytes));
607  }
608 }
609 
610 void HexagonFrameLowering::insertEpilogueInBlock(MachineBasicBlock &MBB) const {
611  MachineFunction &MF = *MBB.getParent();
612  auto &HST = MF.getSubtarget<HexagonSubtarget>();
613  auto &HII = *HST.getInstrInfo();
614  auto &HRI = *HST.getRegisterInfo();
615  unsigned SP = HRI.getStackRegister();
616 
618  DebugLoc dl = MBB.findDebugLoc(InsertPt);
619 
620  if (!hasFP(MF)) {
621  MachineFrameInfo &MFI = MF.getFrameInfo();
622  if (unsigned NumBytes = MFI.getStackSize()) {
623  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
624  .addReg(SP)
625  .addImm(NumBytes);
626  }
627  return;
628  }
629 
630  MachineInstr *RetI = getReturn(MBB);
631  unsigned RetOpc = RetI ? RetI->getOpcode() : 0;
632 
633  // Handle EH_RETURN.
634  if (RetOpc == Hexagon::EH_RETURN_JMPR) {
635  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe));
636  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_add), SP)
637  .addReg(SP)
638  .addReg(Hexagon::R28);
639  return;
640  }
641 
642  // Check for RESTORE_DEALLOC_RET* tail call. Don't emit an extra dealloc-
643  // frame instruction if we encounter it.
644  if (RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4 ||
645  RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC ||
646  RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT ||
647  RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC) {
648  MachineBasicBlock::iterator It = RetI;
649  ++It;
650  // Delete all instructions after the RESTORE (except labels).
651  while (It != MBB.end()) {
652  if (!It->isLabel())
653  It = MBB.erase(It);
654  else
655  ++It;
656  }
657  return;
658  }
659 
660  // It is possible that the restoring code is a call to a library function.
661  // All of the restore* functions include "deallocframe", so we need to make
662  // sure that we don't add an extra one.
663  bool NeedsDeallocframe = true;
664  if (!MBB.empty() && InsertPt != MBB.begin()) {
665  MachineBasicBlock::iterator PrevIt = std::prev(InsertPt);
666  unsigned COpc = PrevIt->getOpcode();
667  if (COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4 ||
668  COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC ||
669  COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT ||
670  COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC ||
671  COpc == Hexagon::PS_call_nr || COpc == Hexagon::PS_callr_nr)
672  NeedsDeallocframe = false;
673  }
674 
675  if (!NeedsDeallocframe)
676  return;
677  // If the returning instruction is PS_jmpret, replace it with dealloc_return,
678  // otherwise just add deallocframe. The function could be returning via a
679  // tail call.
680  if (RetOpc != Hexagon::PS_jmpret || DisableDeallocRet) {
681  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe));
682  return;
683  }
684  unsigned NewOpc = Hexagon::L4_return;
685  MachineInstr *NewI = BuildMI(MBB, RetI, dl, HII.get(NewOpc));
686  // Transfer the function live-out registers.
687  NewI->copyImplicitOps(MF, *RetI);
688  MBB.erase(RetI);
689 }
690 
691 void HexagonFrameLowering::insertAllocframe(MachineBasicBlock &MBB,
692  MachineBasicBlock::iterator InsertPt, unsigned NumBytes) const {
693  MachineFunction &MF = *MBB.getParent();
694  auto &HST = MF.getSubtarget<HexagonSubtarget>();
695  auto &HII = *HST.getInstrInfo();
696  auto &HRI = *HST.getRegisterInfo();
697 
698  // Check for overflow.
699  // Hexagon_TODO: Ugh! hardcoding. Is there an API that can be used?
700  const unsigned int ALLOCFRAME_MAX = 16384;
701 
702  // Create a dummy memory operand to avoid allocframe from being treated as
703  // a volatile memory reference.
706 
707  DebugLoc dl = MBB.findDebugLoc(InsertPt);
708 
709  if (NumBytes >= ALLOCFRAME_MAX) {
710  // Emit allocframe(#0).
711  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))
712  .addImm(0)
713  .addMemOperand(MMO);
714 
715  // Subtract the size from the stack pointer.
716  unsigned SP = HRI.getStackRegister();
717  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
718  .addReg(SP)
719  .addImm(-int(NumBytes));
720  } else {
721  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))
722  .addImm(NumBytes)
723  .addMemOperand(MMO);
724  }
725 }
726 
727 void HexagonFrameLowering::updateEntryPaths(MachineFunction &MF,
728  MachineBasicBlock &SaveB) const {
729  SetVector<unsigned> Worklist;
730 
731  MachineBasicBlock &EntryB = MF.front();
732  Worklist.insert(EntryB.getNumber());
733 
734  unsigned SaveN = SaveB.getNumber();
735  auto &CSI = MF.getFrameInfo().getCalleeSavedInfo();
736 
737  for (unsigned i = 0; i < Worklist.size(); ++i) {
738  unsigned BN = Worklist[i];
739  MachineBasicBlock &MBB = *MF.getBlockNumbered(BN);
740  for (auto &R : CSI)
741  if (!MBB.isLiveIn(R.getReg()))
742  MBB.addLiveIn(R.getReg());
743  if (BN != SaveN)
744  for (auto &SB : MBB.successors())
745  Worklist.insert(SB->getNumber());
746  }
747 }
748 
749 bool HexagonFrameLowering::updateExitPaths(MachineBasicBlock &MBB,
750  MachineBasicBlock &RestoreB, BitVector &DoneT, BitVector &DoneF,
751  BitVector &Path) const {
752  assert(MBB.getNumber() >= 0);
753  unsigned BN = MBB.getNumber();
754  if (Path[BN] || DoneF[BN])
755  return false;
756  if (DoneT[BN])
757  return true;
758 
759  auto &CSI = MBB.getParent()->getFrameInfo().getCalleeSavedInfo();
760 
761  Path[BN] = true;
762  bool ReachedExit = false;
763  for (auto &SB : MBB.successors())
764  ReachedExit |= updateExitPaths(*SB, RestoreB, DoneT, DoneF, Path);
765 
766  if (!MBB.empty() && MBB.back().isReturn()) {
767  // Add implicit uses of all callee-saved registers to the reached
768  // return instructions. This is to prevent the anti-dependency breaker
769  // from renaming these registers.
770  MachineInstr &RetI = MBB.back();
771  if (!isRestoreCall(RetI.getOpcode()))
772  for (auto &R : CSI)
773  RetI.addOperand(MachineOperand::CreateReg(R.getReg(), false, true));
774  ReachedExit = true;
775  }
776 
777  // We don't want to add unnecessary live-ins to the restore block: since
778  // the callee-saved registers are being defined in it, the entry of the
779  // restore block cannot be on the path from the definitions to any exit.
780  if (ReachedExit && &MBB != &RestoreB) {
781  for (auto &R : CSI)
782  if (!MBB.isLiveIn(R.getReg()))
783  MBB.addLiveIn(R.getReg());
784  DoneT[BN] = true;
785  }
786  if (!ReachedExit)
787  DoneF[BN] = true;
788 
789  Path[BN] = false;
790  return ReachedExit;
791 }
792 
795  // The CFI instructions need to be inserted right after allocframe.
796  // An exception to this is a situation where allocframe is bundled
797  // with a call: then the CFI instructions need to be inserted before
798  // the packet with the allocframe+call (in case the call throws an
799  // exception).
800  auto End = B.instr_end();
801 
802  for (MachineInstr &I : B) {
803  MachineBasicBlock::iterator It = I.getIterator();
804  if (!I.isBundle()) {
805  if (I.getOpcode() == Hexagon::S2_allocframe)
806  return std::next(It);
807  continue;
808  }
809  // I is a bundle.
810  bool HasCall = false, HasAllocFrame = false;
811  auto T = It.getInstrIterator();
812  while (++T != End && T->isBundled()) {
813  if (T->getOpcode() == Hexagon::S2_allocframe)
814  HasAllocFrame = true;
815  else if (T->isCall())
816  HasCall = true;
817  }
818  if (HasAllocFrame)
819  return HasCall ? It : std::next(It);
820  }
821  return None;
822 }
823 
825  for (auto &B : MF) {
826  auto At = findCFILocation(B);
827  if (At.hasValue())
828  insertCFIInstructionsAt(B, At.getValue());
829  }
830 }
831 
832 void HexagonFrameLowering::insertCFIInstructionsAt(MachineBasicBlock &MBB,
833  MachineBasicBlock::iterator At) const {
834  MachineFunction &MF = *MBB.getParent();
835  MachineFrameInfo &MFI = MF.getFrameInfo();
836  MachineModuleInfo &MMI = MF.getMMI();
837  auto &HST = MF.getSubtarget<HexagonSubtarget>();
838  auto &HII = *HST.getInstrInfo();
839  auto &HRI = *HST.getRegisterInfo();
840 
841  // If CFI instructions have debug information attached, something goes
842  // wrong with the final assembly generation: the prolog_end is placed
843  // in a wrong location.
844  DebugLoc DL;
845  const MCInstrDesc &CFID = HII.get(TargetOpcode::CFI_INSTRUCTION);
846 
847  MCSymbol *FrameLabel = MMI.getContext().createTempSymbol();
848  bool HasFP = hasFP(MF);
849 
850  if (HasFP) {
851  unsigned DwFPReg = HRI.getDwarfRegNum(HRI.getFrameRegister(), true);
852  unsigned DwRAReg = HRI.getDwarfRegNum(HRI.getRARegister(), true);
853 
854  // Define CFA via an offset from the value of FP.
855  //
856  // -8 -4 0 (SP)
857  // --+----+----+---------------------
858  // | FP | LR | increasing addresses -->
859  // --+----+----+---------------------
860  // | +-- Old SP (before allocframe)
861  // +-- New FP (after allocframe)
862  //
863  // MCCFIInstruction::createDefCfa subtracts the offset from the register.
864  // MCCFIInstruction::createOffset takes the offset without sign change.
865  auto DefCfa = MCCFIInstruction::createDefCfa(FrameLabel, DwFPReg, -8);
866  BuildMI(MBB, At, DL, CFID)
867  .addCFIIndex(MF.addFrameInst(DefCfa));
868  // R31 (return addr) = CFA - 4
869  auto OffR31 = MCCFIInstruction::createOffset(FrameLabel, DwRAReg, -4);
870  BuildMI(MBB, At, DL, CFID)
871  .addCFIIndex(MF.addFrameInst(OffR31));
872  // R30 (frame ptr) = CFA - 8
873  auto OffR30 = MCCFIInstruction::createOffset(FrameLabel, DwFPReg, -8);
874  BuildMI(MBB, At, DL, CFID)
875  .addCFIIndex(MF.addFrameInst(OffR30));
876  }
877 
878  static unsigned int RegsToMove[] = {
879  Hexagon::R1, Hexagon::R0, Hexagon::R3, Hexagon::R2,
880  Hexagon::R17, Hexagon::R16, Hexagon::R19, Hexagon::R18,
881  Hexagon::R21, Hexagon::R20, Hexagon::R23, Hexagon::R22,
882  Hexagon::R25, Hexagon::R24, Hexagon::R27, Hexagon::R26,
883  Hexagon::D0, Hexagon::D1, Hexagon::D8, Hexagon::D9,
884  Hexagon::D10, Hexagon::D11, Hexagon::D12, Hexagon::D13,
885  Hexagon::NoRegister
886  };
887 
888  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
889 
890  for (unsigned i = 0; RegsToMove[i] != Hexagon::NoRegister; ++i) {
891  unsigned Reg = RegsToMove[i];
892  auto IfR = [Reg] (const CalleeSavedInfo &C) -> bool {
893  return C.getReg() == Reg;
894  };
895  auto F = find_if(CSI, IfR);
896  if (F == CSI.end())
897  continue;
898 
899  int64_t Offset;
900  if (HasFP) {
901  // If the function has a frame pointer (i.e. has an allocframe),
902  // then the CFA has been defined in terms of FP. Any offsets in
903  // the following CFI instructions have to be defined relative
904  // to FP, which points to the bottom of the stack frame.
905  // The function getFrameIndexReference can still choose to use SP
906  // for the offset calculation, so we cannot simply call it here.
907  // Instead, get the offset (relative to the FP) directly.
908  Offset = MFI.getObjectOffset(F->getFrameIdx());
909  } else {
910  unsigned FrameReg;
911  Offset = getFrameIndexReference(MF, F->getFrameIdx(), FrameReg);
912  }
913  // Subtract 8 to make room for R30 and R31, which are added above.
914  Offset -= 8;
915 
916  if (Reg < Hexagon::D0 || Reg > Hexagon::D15) {
917  unsigned DwarfReg = HRI.getDwarfRegNum(Reg, true);
918  auto OffReg = MCCFIInstruction::createOffset(FrameLabel, DwarfReg,
919  Offset);
920  BuildMI(MBB, At, DL, CFID)
921  .addCFIIndex(MF.addFrameInst(OffReg));
922  } else {
923  // Split the double regs into subregs, and generate appropriate
924  // cfi_offsets.
925  // The only reason, we are split double regs is, llvm-mc does not
926  // understand paired registers for cfi_offset.
927  // Eg .cfi_offset r1:0, -64
928 
929  unsigned HiReg = HRI.getSubReg(Reg, Hexagon::isub_hi);
930  unsigned LoReg = HRI.getSubReg(Reg, Hexagon::isub_lo);
931  unsigned HiDwarfReg = HRI.getDwarfRegNum(HiReg, true);
932  unsigned LoDwarfReg = HRI.getDwarfRegNum(LoReg, true);
933  auto OffHi = MCCFIInstruction::createOffset(FrameLabel, HiDwarfReg,
934  Offset+4);
935  BuildMI(MBB, At, DL, CFID)
936  .addCFIIndex(MF.addFrameInst(OffHi));
937  auto OffLo = MCCFIInstruction::createOffset(FrameLabel, LoDwarfReg,
938  Offset);
939  BuildMI(MBB, At, DL, CFID)
940  .addCFIIndex(MF.addFrameInst(OffLo));
941  }
942  }
943 }
944 
946  if (MF.getFunction()->hasFnAttribute(Attribute::Naked))
947  return false;
948 
949  auto &MFI = MF.getFrameInfo();
950  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
951  bool HasExtraAlign = HRI.needsStackRealignment(MF);
952  bool HasAlloca = MFI.hasVarSizedObjects();
953 
954  // Insert ALLOCFRAME if we need to or at -O0 for the debugger. Think
955  // that this shouldn't be required, but doing so now because gcc does and
956  // gdb can't break at the start of the function without it. Will remove if
957  // this turns out to be a gdb bug.
958  //
959  if (MF.getTarget().getOptLevel() == CodeGenOpt::None)
960  return true;
961 
962  // By default we want to use SP (since it's always there). FP requires
963  // some setup (i.e. ALLOCFRAME).
964  // Both, alloca and stack alignment modify the stack pointer by an
965  // undetermined value, so we need to save it at the entry to the function
966  // (i.e. use allocframe).
967  if (HasAlloca || HasExtraAlign)
968  return true;
969 
970  if (MFI.getStackSize() > 0) {
971  // If FP-elimination is disabled, we have to use FP at this point.
972  const TargetMachine &TM = MF.getTarget();
974  return true;
976  return true;
977  }
978 
979  const auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
980  if (MFI.hasCalls() || HMFI.hasClobberLR())
981  return true;
982 
983  return false;
984 }
985 
986 enum SpillKind {
990 };
991 
992 static const char *getSpillFunctionFor(unsigned MaxReg, SpillKind SpillType,
993  bool Stkchk = false) {
994  const char * V4SpillToMemoryFunctions[] = {
995  "__save_r16_through_r17",
996  "__save_r16_through_r19",
997  "__save_r16_through_r21",
998  "__save_r16_through_r23",
999  "__save_r16_through_r25",
1000  "__save_r16_through_r27" };
1001 
1002  const char * V4SpillToMemoryStkchkFunctions[] = {
1003  "__save_r16_through_r17_stkchk",
1004  "__save_r16_through_r19_stkchk",
1005  "__save_r16_through_r21_stkchk",
1006  "__save_r16_through_r23_stkchk",
1007  "__save_r16_through_r25_stkchk",
1008  "__save_r16_through_r27_stkchk" };
1009 
1010  const char * V4SpillFromMemoryFunctions[] = {
1011  "__restore_r16_through_r17_and_deallocframe",
1012  "__restore_r16_through_r19_and_deallocframe",
1013  "__restore_r16_through_r21_and_deallocframe",
1014  "__restore_r16_through_r23_and_deallocframe",
1015  "__restore_r16_through_r25_and_deallocframe",
1016  "__restore_r16_through_r27_and_deallocframe" };
1017 
1018  const char * V4SpillFromMemoryTailcallFunctions[] = {
1019  "__restore_r16_through_r17_and_deallocframe_before_tailcall",
1020  "__restore_r16_through_r19_and_deallocframe_before_tailcall",
1021  "__restore_r16_through_r21_and_deallocframe_before_tailcall",
1022  "__restore_r16_through_r23_and_deallocframe_before_tailcall",
1023  "__restore_r16_through_r25_and_deallocframe_before_tailcall",
1024  "__restore_r16_through_r27_and_deallocframe_before_tailcall"
1025  };
1026 
1027  const char **SpillFunc = nullptr;
1028 
1029  switch(SpillType) {
1030  case SK_ToMem:
1031  SpillFunc = Stkchk ? V4SpillToMemoryStkchkFunctions
1032  : V4SpillToMemoryFunctions;
1033  break;
1034  case SK_FromMem:
1035  SpillFunc = V4SpillFromMemoryFunctions;
1036  break;
1037  case SK_FromMemTailcall:
1038  SpillFunc = V4SpillFromMemoryTailcallFunctions;
1039  break;
1040  }
1041  assert(SpillFunc && "Unknown spill kind");
1042 
1043  // Spill all callee-saved registers up to the highest register used.
1044  switch (MaxReg) {
1045  case Hexagon::R17:
1046  return SpillFunc[0];
1047  case Hexagon::R19:
1048  return SpillFunc[1];
1049  case Hexagon::R21:
1050  return SpillFunc[2];
1051  case Hexagon::R23:
1052  return SpillFunc[3];
1053  case Hexagon::R25:
1054  return SpillFunc[4];
1055  case Hexagon::R27:
1056  return SpillFunc[5];
1057  default:
1058  llvm_unreachable("Unhandled maximum callee save register");
1059  }
1060  return nullptr;
1061 }
1062 
1064  int FI, unsigned &FrameReg) const {
1065  auto &MFI = MF.getFrameInfo();
1066  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1067 
1068  int Offset = MFI.getObjectOffset(FI);
1069  bool HasAlloca = MFI.hasVarSizedObjects();
1070  bool HasExtraAlign = HRI.needsStackRealignment(MF);
1071  bool NoOpt = MF.getTarget().getOptLevel() == CodeGenOpt::None;
1072 
1073  auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
1074  unsigned FrameSize = MFI.getStackSize();
1075  unsigned SP = HRI.getStackRegister();
1076  unsigned FP = HRI.getFrameRegister();
1077  unsigned AP = HMFI.getStackAlignBasePhysReg();
1078  // It may happen that AP will be absent even HasAlloca && HasExtraAlign
1079  // is true. HasExtraAlign may be set because of vector spills, without
1080  // aligned locals or aligned outgoing function arguments. Since vector
1081  // spills will ultimately be "unaligned", it is safe to use FP as the
1082  // base register.
1083  // In fact, in such a scenario the stack is actually not required to be
1084  // aligned, although it may end up being aligned anyway, since this
1085  // particular case is not easily detectable. The alignment will be
1086  // unnecessary, but not incorrect.
1087  // Unfortunately there is no quick way to verify that the above is
1088  // indeed the case (and that it's not a result of an error), so just
1089  // assume that missing AP will be replaced by FP.
1090  // (A better fix would be to rematerialize AP from FP and always align
1091  // vector spills.)
1092  if (AP == 0)
1093  AP = FP;
1094 
1095  bool UseFP = false, UseAP = false; // Default: use SP (except at -O0).
1096  // Use FP at -O0, except when there are objects with extra alignment.
1097  // That additional alignment requirement may cause a pad to be inserted,
1098  // which will make it impossible to use FP to access objects located
1099  // past the pad.
1100  if (NoOpt && !HasExtraAlign)
1101  UseFP = true;
1102  if (MFI.isFixedObjectIndex(FI) || MFI.isObjectPreAllocated(FI)) {
1103  // Fixed and preallocated objects will be located before any padding
1104  // so FP must be used to access them.
1105  UseFP |= (HasAlloca || HasExtraAlign);
1106  } else {
1107  if (HasAlloca) {
1108  if (HasExtraAlign)
1109  UseAP = true;
1110  else
1111  UseFP = true;
1112  }
1113  }
1114 
1115  // If FP was picked, then there had better be FP.
1116  bool HasFP = hasFP(MF);
1117  assert((HasFP || !UseFP) && "This function must have frame pointer");
1118 
1119  // Having FP implies allocframe. Allocframe will store extra 8 bytes:
1120  // FP/LR. If the base register is used to access an object across these
1121  // 8 bytes, then the offset will need to be adjusted by 8.
1122  //
1123  // After allocframe:
1124  // HexagonISelLowering adds 8 to ---+
1125  // the offsets of all stack-based |
1126  // arguments (*) |
1127  // |
1128  // getObjectOffset < 0 0 8 getObjectOffset >= 8
1129  // ------------------------+-----+------------------------> increasing
1130  // <local objects> |FP/LR| <input arguments> addresses
1131  // -----------------+------+-----+------------------------>
1132  // | |
1133  // SP/AP point --+ +-- FP points here (**)
1134  // somewhere on
1135  // this side of FP/LR
1136  //
1137  // (*) See LowerFormalArguments. The FP/LR is assumed to be present.
1138  // (**) *FP == old-FP. FP+0..7 are the bytes of FP/LR.
1139 
1140  // The lowering assumes that FP/LR is present, and so the offsets of
1141  // the formal arguments start at 8. If FP/LR is not there we need to
1142  // reduce the offset by 8.
1143  if (Offset > 0 && !HasFP)
1144  Offset -= 8;
1145 
1146  if (UseFP)
1147  FrameReg = FP;
1148  else if (UseAP)
1149  FrameReg = AP;
1150  else
1151  FrameReg = SP;
1152 
1153  // Calculate the actual offset in the instruction. If there is no FP
1154  // (in other words, no allocframe), then SP will not be adjusted (i.e.
1155  // there will be no SP -= FrameSize), so the frame size should not be
1156  // added to the calculated offset.
1157  int RealOffset = Offset;
1158  if (!UseFP && !UseAP)
1159  RealOffset = FrameSize+Offset;
1160  return RealOffset;
1161 }
1162 
1163 bool HexagonFrameLowering::insertCSRSpillsInBlock(MachineBasicBlock &MBB,
1164  const CSIVect &CSI, const HexagonRegisterInfo &HRI,
1165  bool &PrologueStubs) const {
1166  if (CSI.empty())
1167  return true;
1168 
1170  PrologueStubs = false;
1171  MachineFunction &MF = *MBB.getParent();
1172  auto &HST = MF.getSubtarget<HexagonSubtarget>();
1173  auto &HII = *HST.getInstrInfo();
1174 
1175  if (useSpillFunction(MF, CSI)) {
1176  PrologueStubs = true;
1177  unsigned MaxReg = getMaxCalleeSavedReg(CSI, HRI);
1178  bool StkOvrFlowEnabled = EnableStackOVFSanitizer;
1179  const char *SpillFun = getSpillFunctionFor(MaxReg, SK_ToMem,
1180  StkOvrFlowEnabled);
1181  auto &HTM = static_cast<const HexagonTargetMachine&>(MF.getTarget());
1182  bool IsPIC = HTM.isPositionIndependent();
1183  bool LongCalls = HST.useLongCalls() || EnableSaveRestoreLong;
1184 
1185  // Call spill function.
1186  DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
1187  unsigned SpillOpc;
1188  if (StkOvrFlowEnabled) {
1189  if (LongCalls)
1190  SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT_PIC
1191  : Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT;
1192  else
1193  SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4STK_PIC
1194  : Hexagon::SAVE_REGISTERS_CALL_V4STK;
1195  } else {
1196  if (LongCalls)
1197  SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC
1198  : Hexagon::SAVE_REGISTERS_CALL_V4_EXT;
1199  else
1200  SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4_PIC
1201  : Hexagon::SAVE_REGISTERS_CALL_V4;
1202  }
1203 
1204  MachineInstr *SaveRegsCall =
1205  BuildMI(MBB, MI, DL, HII.get(SpillOpc))
1206  .addExternalSymbol(SpillFun);
1207 
1208  // Add callee-saved registers as use.
1209  addCalleeSaveRegistersAsImpOperand(SaveRegsCall, CSI, false, true);
1210  // Add live in registers.
1211  for (unsigned I = 0; I < CSI.size(); ++I)
1212  MBB.addLiveIn(CSI[I].getReg());
1213  return true;
1214  }
1215 
1216  for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
1217  unsigned Reg = CSI[i].getReg();
1218  // Add live in registers. We treat eh_return callee saved register r0 - r3
1219  // specially. They are not really callee saved registers as they are not
1220  // supposed to be killed.
1221  bool IsKill = !HRI.isEHReturnCalleeSaveReg(Reg);
1222  int FI = CSI[i].getFrameIdx();
1223  const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);
1224  HII.storeRegToStackSlot(MBB, MI, Reg, IsKill, FI, RC, &HRI);
1225  if (IsKill)
1226  MBB.addLiveIn(Reg);
1227  }
1228  return true;
1229 }
1230 
1231 bool HexagonFrameLowering::insertCSRRestoresInBlock(MachineBasicBlock &MBB,
1232  const CSIVect &CSI, const HexagonRegisterInfo &HRI) const {
1233  if (CSI.empty())
1234  return false;
1235 
1237  MachineFunction &MF = *MBB.getParent();
1238  auto &HST = MF.getSubtarget<HexagonSubtarget>();
1239  auto &HII = *HST.getInstrInfo();
1240 
1241  if (useRestoreFunction(MF, CSI)) {
1242  bool HasTC = hasTailCall(MBB) || !hasReturn(MBB);
1243  unsigned MaxR = getMaxCalleeSavedReg(CSI, HRI);
1245  const char *RestoreFn = getSpillFunctionFor(MaxR, Kind);
1246  auto &HTM = static_cast<const HexagonTargetMachine&>(MF.getTarget());
1247  bool IsPIC = HTM.isPositionIndependent();
1248  bool LongCalls = HST.useLongCalls() || EnableSaveRestoreLong;
1249 
1250  // Call spill function.
1251  DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc()
1252  : MBB.getLastNonDebugInstr()->getDebugLoc();
1253  MachineInstr *DeallocCall = nullptr;
1254 
1255  if (HasTC) {
1256  unsigned RetOpc;
1257  if (LongCalls)
1258  RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC
1259  : Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT;
1260  else
1261  RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC
1262  : Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4;
1263  DeallocCall = BuildMI(MBB, MI, DL, HII.get(RetOpc))
1264  .addExternalSymbol(RestoreFn);
1265  } else {
1266  // The block has a return.
1268  assert(It->isReturn() && std::next(It) == MBB.end());
1269  unsigned RetOpc;
1270  if (LongCalls)
1271  RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC
1272  : Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT;
1273  else
1274  RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC
1275  : Hexagon::RESTORE_DEALLOC_RET_JMP_V4;
1276  DeallocCall = BuildMI(MBB, It, DL, HII.get(RetOpc))
1277  .addExternalSymbol(RestoreFn);
1278  // Transfer the function live-out registers.
1279  DeallocCall->copyImplicitOps(MF, *It);
1280  }
1281  addCalleeSaveRegistersAsImpOperand(DeallocCall, CSI, true, false);
1282  return true;
1283  }
1284 
1285  for (unsigned i = 0; i < CSI.size(); ++i) {
1286  unsigned Reg = CSI[i].getReg();
1287  const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);
1288  int FI = CSI[i].getFrameIdx();
1289  HII.loadRegFromStackSlot(MBB, MI, Reg, FI, RC, &HRI);
1290  }
1291 
1292  return true;
1293 }
1294 
1298  MachineInstr &MI = *I;
1299  unsigned Opc = MI.getOpcode();
1300  (void)Opc; // Silence compiler warning.
1301  assert((Opc == Hexagon::ADJCALLSTACKDOWN || Opc == Hexagon::ADJCALLSTACKUP) &&
1302  "Cannot handle this call frame pseudo instruction");
1303  return MBB.erase(I);
1304 }
1305 
1307  MachineFunction &MF, RegScavenger *RS) const {
1308  // If this function has uses aligned stack and also has variable sized stack
1309  // objects, then we need to map all spill slots to fixed positions, so that
1310  // they can be accessed through FP. Otherwise they would have to be accessed
1311  // via AP, which may not be available at the particular place in the program.
1312  MachineFrameInfo &MFI = MF.getFrameInfo();
1313  bool HasAlloca = MFI.hasVarSizedObjects();
1314  bool NeedsAlign = (MFI.getMaxAlignment() > getStackAlignment());
1315 
1316  if (!HasAlloca || !NeedsAlign)
1317  return;
1318 
1319  unsigned LFS = MFI.getLocalFrameSize();
1320  for (int i = 0, e = MFI.getObjectIndexEnd(); i != e; ++i) {
1321  if (!MFI.isSpillSlotObjectIndex(i) || MFI.isDeadObjectIndex(i))
1322  continue;
1323  unsigned S = MFI.getObjectSize(i);
1324  // Reduce the alignment to at most 8. This will require unaligned vector
1325  // stores if they happen here.
1326  unsigned A = std::max(MFI.getObjectAlignment(i), 8U);
1327  MFI.setObjectAlignment(i, 8);
1328  LFS = alignTo(LFS+S, A);
1329  MFI.mapLocalFrameObject(i, -LFS);
1330  }
1331 
1332  MFI.setLocalFrameSize(LFS);
1333  unsigned A = MFI.getLocalFrameMaxAlign();
1334  assert(A <= 8 && "Unexpected local frame alignment");
1335  if (A == 0)
1336  MFI.setLocalFrameMaxAlign(8);
1338 
1339  // Set the physical aligned-stack base address register.
1340  unsigned AP = 0;
1341  if (const MachineInstr *AI = getAlignaInstr(MF))
1342  AP = AI->getOperand(0).getReg();
1343  auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
1344  HMFI.setStackAlignBasePhysReg(AP);
1345 }
1346 
1347 /// Returns true if there are no caller-saved registers available in class RC.
1349  const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC) {
1351 
1352  auto IsUsed = [&HRI,&MRI] (unsigned Reg) -> bool {
1353  for (MCRegAliasIterator AI(Reg, &HRI, true); AI.isValid(); ++AI)
1354  if (MRI.isPhysRegUsed(*AI))
1355  return true;
1356  return false;
1357  };
1358 
1359  // Check for an unused caller-saved register. Callee-saved registers
1360  // have become pristine by now.
1361  for (const MCPhysReg *P = HRI.getCallerSavedRegs(&MF, RC); *P; ++P)
1362  if (!IsUsed(*P))
1363  return false;
1364 
1365  // All caller-saved registers are used.
1366  return true;
1367 }
1368 
1369 #ifndef NDEBUG
1371  dbgs() << '{';
1372  for (int x = Regs.find_first(); x >= 0; x = Regs.find_next(x)) {
1373  unsigned R = x;
1374  dbgs() << ' ' << PrintReg(R, &TRI);
1375  }
1376  dbgs() << " }";
1377 }
1378 #endif
1379 
1381  const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI) const {
1382  DEBUG(dbgs() << __func__ << " on "
1383  << MF.getFunction()->getName() << '\n');
1384  MachineFrameInfo &MFI = MF.getFrameInfo();
1385  BitVector SRegs(Hexagon::NUM_TARGET_REGS);
1386 
1387  // Generate a set of unique, callee-saved registers (SRegs), where each
1388  // register in the set is maximal in terms of sub-/super-register relation,
1389  // i.e. for each R in SRegs, no proper super-register of R is also in SRegs.
1390 
1391  // (1) For each callee-saved register, add that register and all of its
1392  // sub-registers to SRegs.
1393  DEBUG(dbgs() << "Initial CS registers: {");
1394  for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
1395  unsigned R = CSI[i].getReg();
1396  DEBUG(dbgs() << ' ' << PrintReg(R, TRI));
1397  for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR)
1398  SRegs[*SR] = true;
1399  }
1400  DEBUG(dbgs() << " }\n");
1401  DEBUG(dbgs() << "SRegs.1: "; dump_registers(SRegs, *TRI); dbgs() << "\n");
1402 
1403  // (2) For each reserved register, remove that register and all of its
1404  // sub- and super-registers from SRegs.
1405  BitVector Reserved = TRI->getReservedRegs(MF);
1406  for (int x = Reserved.find_first(); x >= 0; x = Reserved.find_next(x)) {
1407  unsigned R = x;
1408  for (MCSuperRegIterator SR(R, TRI, true); SR.isValid(); ++SR)
1409  SRegs[*SR] = false;
1410  }
1411  DEBUG(dbgs() << "Res: "; dump_registers(Reserved, *TRI); dbgs() << "\n");
1412  DEBUG(dbgs() << "SRegs.2: "; dump_registers(SRegs, *TRI); dbgs() << "\n");
1413 
1414  // (3) Collect all registers that have at least one sub-register in SRegs,
1415  // and also have no sub-registers that are reserved. These will be the can-
1416  // didates for saving as a whole instead of their individual sub-registers.
1417  // (Saving R17:16 instead of R16 is fine, but only if R17 was not reserved.)
1418  BitVector TmpSup(Hexagon::NUM_TARGET_REGS);
1419  for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1420  unsigned R = x;
1421  for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR)
1422  TmpSup[*SR] = true;
1423  }
1424  for (int x = TmpSup.find_first(); x >= 0; x = TmpSup.find_next(x)) {
1425  unsigned R = x;
1426  for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR) {
1427  if (!Reserved[*SR])
1428  continue;
1429  TmpSup[R] = false;
1430  break;
1431  }
1432  }
1433  DEBUG(dbgs() << "TmpSup: "; dump_registers(TmpSup, *TRI); dbgs() << "\n");
1434 
1435  // (4) Include all super-registers found in (3) into SRegs.
1436  SRegs |= TmpSup;
1437  DEBUG(dbgs() << "SRegs.4: "; dump_registers(SRegs, *TRI); dbgs() << "\n");
1438 
1439  // (5) For each register R in SRegs, if any super-register of R is in SRegs,
1440  // remove R from SRegs.
1441  for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1442  unsigned R = x;
1443  for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR) {
1444  if (!SRegs[*SR])
1445  continue;
1446  SRegs[R] = false;
1447  break;
1448  }
1449  }
1450  DEBUG(dbgs() << "SRegs.5: "; dump_registers(SRegs, *TRI); dbgs() << "\n");
1451 
1452  // Now, for each register that has a fixed stack slot, create the stack
1453  // object for it.
1454  CSI.clear();
1455 
1457 
1458  unsigned NumFixed;
1459  int MinOffset = 0; // CS offsets are negative.
1460  const SpillSlot *FixedSlots = getCalleeSavedSpillSlots(NumFixed);
1461  for (const SpillSlot *S = FixedSlots; S != FixedSlots+NumFixed; ++S) {
1462  if (!SRegs[S->Reg])
1463  continue;
1464  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(S->Reg);
1465  int FI = MFI.CreateFixedSpillStackObject(TRI->getSpillSize(*RC), S->Offset);
1466  MinOffset = std::min(MinOffset, S->Offset);
1467  CSI.push_back(CalleeSavedInfo(S->Reg, FI));
1468  SRegs[S->Reg] = false;
1469  }
1470 
1471  // There can be some registers that don't have fixed slots. For example,
1472  // we need to store R0-R3 in functions with exception handling. For each
1473  // such register, create a non-fixed stack object.
1474  for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1475  unsigned R = x;
1476  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(R);
1477  unsigned Size = TRI->getSpillSize(*RC);
1478  int Off = MinOffset - Size;
1479  unsigned Align = std::min(TRI->getSpillAlignment(*RC), getStackAlignment());
1480  assert(isPowerOf2_32(Align));
1481  Off &= -Align;
1482  int FI = MFI.CreateFixedSpillStackObject(Size, Off);
1483  MinOffset = std::min(MinOffset, Off);
1484  CSI.push_back(CalleeSavedInfo(R, FI));
1485  SRegs[R] = false;
1486  }
1487 
1488  DEBUG({
1489  dbgs() << "CS information: {";
1490  for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
1491  int FI = CSI[i].getFrameIdx();
1492  int Off = MFI.getObjectOffset(FI);
1493  dbgs() << ' ' << PrintReg(CSI[i].getReg(), TRI) << ":fi#" << FI << ":sp";
1494  if (Off >= 0)
1495  dbgs() << '+';
1496  dbgs() << Off;
1497  }
1498  dbgs() << " }\n";
1499  });
1500 
1501 #ifndef NDEBUG
1502  // Verify that all registers were handled.
1503  bool MissedReg = false;
1504  for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1505  unsigned R = x;
1506  dbgs() << PrintReg(R, TRI) << ' ';
1507  MissedReg = true;
1508  }
1509  if (MissedReg)
1510  llvm_unreachable("...there are unhandled callee-saved registers!");
1511 #endif
1512 
1513  return true;
1514 }
1515 
1516 bool HexagonFrameLowering::expandCopy(MachineBasicBlock &B,
1518  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1519  MachineInstr *MI = &*It;
1520  DebugLoc DL = MI->getDebugLoc();
1521  unsigned DstR = MI->getOperand(0).getReg();
1522  unsigned SrcR = MI->getOperand(1).getReg();
1523  if (!Hexagon::ModRegsRegClass.contains(DstR) ||
1524  !Hexagon::ModRegsRegClass.contains(SrcR))
1525  return false;
1526 
1527  unsigned TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1528  BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), TmpR).add(MI->getOperand(1));
1529  BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), DstR)
1530  .addReg(TmpR, RegState::Kill);
1531 
1532  NewRegs.push_back(TmpR);
1533  B.erase(It);
1534  return true;
1535 }
1536 
1537 bool HexagonFrameLowering::expandStoreInt(MachineBasicBlock &B,
1539  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1540  MachineInstr *MI = &*It;
1541  if (!MI->getOperand(0).isFI())
1542  return false;
1543 
1544  DebugLoc DL = MI->getDebugLoc();
1545  unsigned Opc = MI->getOpcode();
1546  unsigned SrcR = MI->getOperand(2).getReg();
1547  bool IsKill = MI->getOperand(2).isKill();
1548  int FI = MI->getOperand(0).getIndex();
1549 
1550  // TmpR = C2_tfrpr SrcR if SrcR is a predicate register
1551  // TmpR = A2_tfrcrr SrcR if SrcR is a modifier register
1552  unsigned TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1553  unsigned TfrOpc = (Opc == Hexagon::STriw_pred) ? Hexagon::C2_tfrpr
1554  : Hexagon::A2_tfrcrr;
1555  BuildMI(B, It, DL, HII.get(TfrOpc), TmpR)
1556  .addReg(SrcR, getKillRegState(IsKill));
1557 
1558  // S2_storeri_io FI, 0, TmpR
1559  BuildMI(B, It, DL, HII.get(Hexagon::S2_storeri_io))
1560  .addFrameIndex(FI)
1561  .addImm(0)
1562  .addReg(TmpR, RegState::Kill)
1564 
1565  NewRegs.push_back(TmpR);
1566  B.erase(It);
1567  return true;
1568 }
1569 
1570 bool HexagonFrameLowering::expandLoadInt(MachineBasicBlock &B,
1572  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1573  MachineInstr *MI = &*It;
1574  if (!MI->getOperand(1).isFI())
1575  return false;
1576 
1577  DebugLoc DL = MI->getDebugLoc();
1578  unsigned Opc = MI->getOpcode();
1579  unsigned DstR = MI->getOperand(0).getReg();
1580  int FI = MI->getOperand(1).getIndex();
1581 
1582  // TmpR = L2_loadri_io FI, 0
1583  unsigned TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1584  BuildMI(B, It, DL, HII.get(Hexagon::L2_loadri_io), TmpR)
1585  .addFrameIndex(FI)
1586  .addImm(0)
1588 
1589  // DstR = C2_tfrrp TmpR if DstR is a predicate register
1590  // DstR = A2_tfrrcr TmpR if DstR is a modifier register
1591  unsigned TfrOpc = (Opc == Hexagon::LDriw_pred) ? Hexagon::C2_tfrrp
1592  : Hexagon::A2_tfrrcr;
1593  BuildMI(B, It, DL, HII.get(TfrOpc), DstR)
1594  .addReg(TmpR, RegState::Kill);
1595 
1596  NewRegs.push_back(TmpR);
1597  B.erase(It);
1598  return true;
1599 }
1600 
1601 bool HexagonFrameLowering::expandStoreVecPred(MachineBasicBlock &B,
1603  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1604  MachineInstr *MI = &*It;
1605  if (!MI->getOperand(0).isFI())
1606  return false;
1607 
1608  DebugLoc DL = MI->getDebugLoc();
1609  unsigned SrcR = MI->getOperand(2).getReg();
1610  bool IsKill = MI->getOperand(2).isKill();
1611  int FI = MI->getOperand(0).getIndex();
1612  auto *RC = &Hexagon::HvxVRRegClass;
1613 
1614  // Insert transfer to general vector register.
1615  // TmpR0 = A2_tfrsi 0x01010101
1616  // TmpR1 = V6_vandqrt Qx, TmpR0
1617  // store FI, 0, TmpR1
1618  unsigned TmpR0 = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1619  unsigned TmpR1 = MRI.createVirtualRegister(RC);
1620 
1621  BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0)
1622  .addImm(0x01010101);
1623 
1624  BuildMI(B, It, DL, HII.get(Hexagon::V6_vandqrt), TmpR1)
1625  .addReg(SrcR, getKillRegState(IsKill))
1626  .addReg(TmpR0, RegState::Kill);
1627 
1628  auto *HRI = B.getParent()->getSubtarget<HexagonSubtarget>().getRegisterInfo();
1629  HII.storeRegToStackSlot(B, It, TmpR1, true, FI, RC, HRI);
1630  expandStoreVec(B, std::prev(It), MRI, HII, NewRegs);
1631 
1632  NewRegs.push_back(TmpR0);
1633  NewRegs.push_back(TmpR1);
1634  B.erase(It);
1635  return true;
1636 }
1637 
1638 bool HexagonFrameLowering::expandLoadVecPred(MachineBasicBlock &B,
1640  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1641  MachineInstr *MI = &*It;
1642  if (!MI->getOperand(1).isFI())
1643  return false;
1644 
1645  DebugLoc DL = MI->getDebugLoc();
1646  unsigned DstR = MI->getOperand(0).getReg();
1647  int FI = MI->getOperand(1).getIndex();
1648  auto *RC = &Hexagon::HvxVRRegClass;
1649 
1650  // TmpR0 = A2_tfrsi 0x01010101
1651  // TmpR1 = load FI, 0
1652  // DstR = V6_vandvrt TmpR1, TmpR0
1653  unsigned TmpR0 = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1654  unsigned TmpR1 = MRI.createVirtualRegister(RC);
1655 
1656  BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0)
1657  .addImm(0x01010101);
1658  MachineFunction &MF = *B.getParent();
1659  auto *HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1660  HII.loadRegFromStackSlot(B, It, TmpR1, FI, RC, HRI);
1661  expandLoadVec(B, std::prev(It), MRI, HII, NewRegs);
1662 
1663  BuildMI(B, It, DL, HII.get(Hexagon::V6_vandvrt), DstR)
1664  .addReg(TmpR1, RegState::Kill)
1665  .addReg(TmpR0, RegState::Kill);
1666 
1667  NewRegs.push_back(TmpR0);
1668  NewRegs.push_back(TmpR1);
1669  B.erase(It);
1670  return true;
1671 }
1672 
1673 bool HexagonFrameLowering::expandStoreVec2(MachineBasicBlock &B,
1675  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1676  MachineFunction &MF = *B.getParent();
1677  auto &MFI = MF.getFrameInfo();
1678  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1679  MachineInstr *MI = &*It;
1680  if (!MI->getOperand(0).isFI())
1681  return false;
1682 
1683  // It is possible that the double vector being stored is only partially
1684  // defined. From the point of view of the liveness tracking, it is ok to
1685  // store it as a whole, but if we break it up we may end up storing a
1686  // register that is entirely undefined.
1687  LivePhysRegs LPR(HRI);
1688  LPR.addLiveIns(B);
1690  for (auto R = B.begin(); R != It; ++R) {
1691  Clobbers.clear();
1692  LPR.stepForward(*R, Clobbers);
1693  // Dead defs are recorded in Clobbers, but are not automatically removed
1694  // from the live set.
1695  for (auto &C : Clobbers)
1696  if (C.second->isReg() && C.second->isDead())
1697  LPR.removeReg(C.first);
1698  }
1699 
1700  DebugLoc DL = MI->getDebugLoc();
1701  unsigned SrcR = MI->getOperand(2).getReg();
1702  unsigned SrcLo = HRI.getSubReg(SrcR, Hexagon::vsub_lo);
1703  unsigned SrcHi = HRI.getSubReg(SrcR, Hexagon::vsub_hi);
1704  bool IsKill = MI->getOperand(2).isKill();
1705  int FI = MI->getOperand(0).getIndex();
1706 
1707  unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1708  unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
1709  unsigned HasAlign = MFI.getObjectAlignment(FI);
1710  unsigned StoreOpc;
1711 
1712  // Store low part.
1713  if (LPR.contains(SrcLo)) {
1714  StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai
1715  : Hexagon::V6_vS32Ub_ai;
1716  BuildMI(B, It, DL, HII.get(StoreOpc))
1717  .addFrameIndex(FI)
1718  .addImm(0)
1719  .addReg(SrcLo, getKillRegState(IsKill))
1721  }
1722 
1723  // Store high part.
1724  if (LPR.contains(SrcHi)) {
1725  StoreOpc = NeedAlign <= MinAlign(HasAlign, Size) ? Hexagon::V6_vS32b_ai
1726  : Hexagon::V6_vS32Ub_ai;
1727  BuildMI(B, It, DL, HII.get(StoreOpc))
1728  .addFrameIndex(FI)
1729  .addImm(Size)
1730  .addReg(SrcHi, getKillRegState(IsKill))
1732  }
1733 
1734  B.erase(It);
1735  return true;
1736 }
1737 
1738 bool HexagonFrameLowering::expandLoadVec2(MachineBasicBlock &B,
1740  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1741  MachineFunction &MF = *B.getParent();
1742  auto &MFI = MF.getFrameInfo();
1743  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1744  MachineInstr *MI = &*It;
1745  if (!MI->getOperand(1).isFI())
1746  return false;
1747 
1748  DebugLoc DL = MI->getDebugLoc();
1749  unsigned DstR = MI->getOperand(0).getReg();
1750  unsigned DstHi = HRI.getSubReg(DstR, Hexagon::vsub_hi);
1751  unsigned DstLo = HRI.getSubReg(DstR, Hexagon::vsub_lo);
1752  int FI = MI->getOperand(1).getIndex();
1753 
1754  unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1755  unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
1756  unsigned HasAlign = MFI.getObjectAlignment(FI);
1757  unsigned LoadOpc;
1758 
1759  // Load low part.
1760  LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai
1761  : Hexagon::V6_vL32Ub_ai;
1762  BuildMI(B, It, DL, HII.get(LoadOpc), DstLo)
1763  .addFrameIndex(FI)
1764  .addImm(0)
1766 
1767  // Load high part.
1768  LoadOpc = NeedAlign <= MinAlign(HasAlign, Size) ? Hexagon::V6_vL32b_ai
1769  : Hexagon::V6_vL32Ub_ai;
1770  BuildMI(B, It, DL, HII.get(LoadOpc), DstHi)
1771  .addFrameIndex(FI)
1772  .addImm(Size)
1774 
1775  B.erase(It);
1776  return true;
1777 }
1778 
1779 bool HexagonFrameLowering::expandStoreVec(MachineBasicBlock &B,
1781  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1782  MachineFunction &MF = *B.getParent();
1783  auto &MFI = MF.getFrameInfo();
1784  MachineInstr *MI = &*It;
1785  if (!MI->getOperand(0).isFI())
1786  return false;
1787 
1788  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1789  DebugLoc DL = MI->getDebugLoc();
1790  unsigned SrcR = MI->getOperand(2).getReg();
1791  bool IsKill = MI->getOperand(2).isKill();
1792  int FI = MI->getOperand(0).getIndex();
1793 
1794  unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
1795  unsigned HasAlign = MFI.getObjectAlignment(FI);
1796  unsigned StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai
1797  : Hexagon::V6_vS32Ub_ai;
1798  BuildMI(B, It, DL, HII.get(StoreOpc))
1799  .addFrameIndex(FI)
1800  .addImm(0)
1801  .addReg(SrcR, getKillRegState(IsKill))
1803 
1804  B.erase(It);
1805  return true;
1806 }
1807 
1808 bool HexagonFrameLowering::expandLoadVec(MachineBasicBlock &B,
1810  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1811  MachineFunction &MF = *B.getParent();
1812  auto &MFI = MF.getFrameInfo();
1813  MachineInstr *MI = &*It;
1814  if (!MI->getOperand(1).isFI())
1815  return false;
1816 
1817  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1818  DebugLoc DL = MI->getDebugLoc();
1819  unsigned DstR = MI->getOperand(0).getReg();
1820  int FI = MI->getOperand(1).getIndex();
1821 
1822  unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
1823  unsigned HasAlign = MFI.getObjectAlignment(FI);
1824  unsigned LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai
1825  : Hexagon::V6_vL32Ub_ai;
1826  BuildMI(B, It, DL, HII.get(LoadOpc), DstR)
1827  .addFrameIndex(FI)
1828  .addImm(0)
1830 
1831  B.erase(It);
1832  return true;
1833 }
1834 
1835 bool HexagonFrameLowering::expandSpillMacros(MachineFunction &MF,
1836  SmallVectorImpl<unsigned> &NewRegs) const {
1837  auto &HII = *MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
1838  MachineRegisterInfo &MRI = MF.getRegInfo();
1839  bool Changed = false;
1840 
1841  for (auto &B : MF) {
1842  // Traverse the basic block.
1844  for (auto I = B.begin(), E = B.end(); I != E; I = NextI) {
1845  MachineInstr *MI = &*I;
1846  NextI = std::next(I);
1847  unsigned Opc = MI->getOpcode();
1848 
1849  switch (Opc) {
1850  case TargetOpcode::COPY:
1851  Changed |= expandCopy(B, I, MRI, HII, NewRegs);
1852  break;
1853  case Hexagon::STriw_pred:
1854  case Hexagon::STriw_mod:
1855  Changed |= expandStoreInt(B, I, MRI, HII, NewRegs);
1856  break;
1857  case Hexagon::LDriw_pred:
1858  case Hexagon::LDriw_mod:
1859  Changed |= expandLoadInt(B, I, MRI, HII, NewRegs);
1860  break;
1861  case Hexagon::PS_vstorerq_ai:
1862  Changed |= expandStoreVecPred(B, I, MRI, HII, NewRegs);
1863  break;
1864  case Hexagon::PS_vloadrq_ai:
1865  Changed |= expandLoadVecPred(B, I, MRI, HII, NewRegs);
1866  break;
1867  case Hexagon::PS_vloadrw_ai:
1868  case Hexagon::PS_vloadrwu_ai:
1869  Changed |= expandLoadVec2(B, I, MRI, HII, NewRegs);
1870  break;
1871  case Hexagon::PS_vstorerw_ai:
1872  case Hexagon::PS_vstorerwu_ai:
1873  Changed |= expandStoreVec2(B, I, MRI, HII, NewRegs);
1874  break;
1875  }
1876  }
1877  }
1878 
1879  return Changed;
1880 }
1881 
1883  BitVector &SavedRegs,
1884  RegScavenger *RS) const {
1885  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1886 
1887  SavedRegs.resize(HRI.getNumRegs());
1888 
1889  // If we have a function containing __builtin_eh_return we want to spill and
1890  // restore all callee saved registers. Pretend that they are used.
1892  for (const MCPhysReg *R = HRI.getCalleeSavedRegs(&MF); *R; ++R)
1893  SavedRegs.set(*R);
1894 
1895  // Replace predicate register pseudo spill code.
1896  SmallVector<unsigned,8> NewRegs;
1897  expandSpillMacros(MF, NewRegs);
1898  if (OptimizeSpillSlots && !isOptNone(MF))
1899  optimizeSpillSlots(MF, NewRegs);
1900 
1901  // We need to reserve a a spill slot if scavenging could potentially require
1902  // spilling a scavenged register.
1903  if (!NewRegs.empty() || mayOverflowFrameOffset(MF)) {
1904  MachineFrameInfo &MFI = MF.getFrameInfo();
1905  MachineRegisterInfo &MRI = MF.getRegInfo();
1907  // Reserve an int register in any case, because it could be used to hold
1908  // the stack offset in case it does not fit into a spill instruction.
1909  SpillRCs.insert(&Hexagon::IntRegsRegClass);
1910 
1911  for (unsigned VR : NewRegs)
1912  SpillRCs.insert(MRI.getRegClass(VR));
1913 
1914  for (auto *RC : SpillRCs) {
1915  if (!needToReserveScavengingSpillSlots(MF, HRI, RC))
1916  continue;
1917  unsigned Num = RC == &Hexagon::IntRegsRegClass ? NumberScavengerSlots : 1;
1918  unsigned S = HRI.getSpillSize(*RC), A = HRI.getSpillAlignment(*RC);
1919  for (unsigned i = 0; i < Num; i++) {
1920  int NewFI = MFI.CreateSpillStackObject(S, A);
1921  RS->addScavengingFrameIndex(NewFI);
1922  }
1923  }
1924  }
1925 
1926  TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1927 }
1928 
1929 unsigned HexagonFrameLowering::findPhysReg(MachineFunction &MF,
1933  const TargetRegisterClass *RC) const {
1934  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1935  auto &MRI = MF.getRegInfo();
1936 
1937  auto isDead = [&FIR,&DeadMap] (unsigned Reg) -> bool {
1938  auto F = DeadMap.find({Reg,0});
1939  if (F == DeadMap.end())
1940  return false;
1941  for (auto &DR : F->second)
1942  if (DR.contains(FIR))
1943  return true;
1944  return false;
1945  };
1946 
1947  for (unsigned Reg : RC->getRawAllocationOrder(MF)) {
1948  bool Dead = true;
1949  for (auto R : HexagonBlockRanges::expandToSubRegs({Reg,0}, MRI, HRI)) {
1950  if (isDead(R.Reg))
1951  continue;
1952  Dead = false;
1953  break;
1954  }
1955  if (Dead)
1956  return Reg;
1957  }
1958  return 0;
1959 }
1960 
1961 void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
1963  auto &HST = MF.getSubtarget<HexagonSubtarget>();
1964  auto &HII = *HST.getInstrInfo();
1965  auto &HRI = *HST.getRegisterInfo();
1966  auto &MRI = MF.getRegInfo();
1967  HexagonBlockRanges HBR(MF);
1968 
1969  using BlockIndexMap =
1970  std::map<MachineBasicBlock *, HexagonBlockRanges::InstrIndexMap>;
1971  using BlockRangeMap =
1972  std::map<MachineBasicBlock *, HexagonBlockRanges::RangeList>;
1973  using IndexType = HexagonBlockRanges::IndexType;
1974 
1975  struct SlotInfo {
1976  BlockRangeMap Map;
1977  unsigned Size = 0;
1978  const TargetRegisterClass *RC = nullptr;
1979 
1980  SlotInfo() = default;
1981  };
1982 
1983  BlockIndexMap BlockIndexes;
1984  SmallSet<int,4> BadFIs;
1985  std::map<int,SlotInfo> FIRangeMap;
1986 
1987  // Accumulate register classes: get a common class for a pre-existing
1988  // class HaveRC and a new class NewRC. Return nullptr if a common class
1989  // cannot be found, otherwise return the resulting class. If HaveRC is
1990  // nullptr, assume that it is still unset.
1991  auto getCommonRC =
1992  [](const TargetRegisterClass *HaveRC,
1993  const TargetRegisterClass *NewRC) -> const TargetRegisterClass * {
1994  if (HaveRC == nullptr || HaveRC == NewRC)
1995  return NewRC;
1996  // Different classes, both non-null. Pick the more general one.
1997  if (HaveRC->hasSubClassEq(NewRC))
1998  return HaveRC;
1999  if (NewRC->hasSubClassEq(HaveRC))
2000  return NewRC;
2001  return nullptr;
2002  };
2003 
2004  // Scan all blocks in the function. Check all occurrences of frame indexes,
2005  // and collect relevant information.
2006  for (auto &B : MF) {
2007  std::map<int,IndexType> LastStore, LastLoad;
2008  // Emplace appears not to be supported in gcc 4.7.2-4.
2009  //auto P = BlockIndexes.emplace(&B, HexagonBlockRanges::InstrIndexMap(B));
2010  auto P = BlockIndexes.insert(
2011  std::make_pair(&B, HexagonBlockRanges::InstrIndexMap(B)));
2012  auto &IndexMap = P.first->second;
2013  DEBUG(dbgs() << "Index map for BB#" << B.getNumber() << "\n"
2014  << IndexMap << '\n');
2015 
2016  for (auto &In : B) {
2017  int LFI, SFI;
2018  bool Load = HII.isLoadFromStackSlot(In, LFI) && !HII.isPredicated(In);
2019  bool Store = HII.isStoreToStackSlot(In, SFI) && !HII.isPredicated(In);
2020  if (Load && Store) {
2021  // If it's both a load and a store, then we won't handle it.
2022  BadFIs.insert(LFI);
2023  BadFIs.insert(SFI);
2024  continue;
2025  }
2026  // Check for register classes of the register used as the source for
2027  // the store, and the register used as the destination for the load.
2028  // Also, only accept base+imm_offset addressing modes. Other addressing
2029  // modes can have side-effects (post-increments, etc.). For stack
2030  // slots they are very unlikely, so there is not much loss due to
2031  // this restriction.
2032  if (Load || Store) {
2033  int TFI = Load ? LFI : SFI;
2034  unsigned AM = HII.getAddrMode(In);
2035  SlotInfo &SI = FIRangeMap[TFI];
2036  bool Bad = (AM != HexagonII::BaseImmOffset);
2037  if (!Bad) {
2038  // If the addressing mode is ok, check the register class.
2039  unsigned OpNum = Load ? 0 : 2;
2040  auto *RC = HII.getRegClass(In.getDesc(), OpNum, &HRI, MF);
2041  RC = getCommonRC(SI.RC, RC);
2042  if (RC == nullptr)
2043  Bad = true;
2044  else
2045  SI.RC = RC;
2046  }
2047  if (!Bad) {
2048  // Check sizes.
2049  unsigned S = HII.getMemAccessSize(In);
2050  if (SI.Size != 0 && SI.Size != S)
2051  Bad = true;
2052  else
2053  SI.Size = S;
2054  }
2055  if (!Bad) {
2056  for (auto *Mo : In.memoperands()) {
2057  if (!Mo->isVolatile())
2058  continue;
2059  Bad = true;
2060  break;
2061  }
2062  }
2063  if (Bad)
2064  BadFIs.insert(TFI);
2065  }
2066 
2067  // Locate uses of frame indices.
2068  for (unsigned i = 0, n = In.getNumOperands(); i < n; ++i) {
2069  const MachineOperand &Op = In.getOperand(i);
2070  if (!Op.isFI())
2071  continue;
2072  int FI = Op.getIndex();
2073  // Make sure that the following operand is an immediate and that
2074  // it is 0. This is the offset in the stack object.
2075  if (i+1 >= n || !In.getOperand(i+1).isImm() ||
2076  In.getOperand(i+1).getImm() != 0)
2077  BadFIs.insert(FI);
2078  if (BadFIs.count(FI))
2079  continue;
2080 
2081  IndexType Index = IndexMap.getIndex(&In);
2082  if (Load) {
2083  if (LastStore[FI] == IndexType::None)
2084  LastStore[FI] = IndexType::Entry;
2085  LastLoad[FI] = Index;
2086  } else if (Store) {
2087  HexagonBlockRanges::RangeList &RL = FIRangeMap[FI].Map[&B];
2088  if (LastStore[FI] != IndexType::None)
2089  RL.add(LastStore[FI], LastLoad[FI], false, false);
2090  else if (LastLoad[FI] != IndexType::None)
2091  RL.add(IndexType::Entry, LastLoad[FI], false, false);
2092  LastLoad[FI] = IndexType::None;
2093  LastStore[FI] = Index;
2094  } else {
2095  BadFIs.insert(FI);
2096  }
2097  }
2098  }
2099 
2100  for (auto &I : LastLoad) {
2101  IndexType LL = I.second;
2102  if (LL == IndexType::None)
2103  continue;
2104  auto &RL = FIRangeMap[I.first].Map[&B];
2105  IndexType &LS = LastStore[I.first];
2106  if (LS != IndexType::None)
2107  RL.add(LS, LL, false, false);
2108  else
2109  RL.add(IndexType::Entry, LL, false, false);
2110  LS = IndexType::None;
2111  }
2112  for (auto &I : LastStore) {
2113  IndexType LS = I.second;
2114  if (LS == IndexType::None)
2115  continue;
2116  auto &RL = FIRangeMap[I.first].Map[&B];
2117  RL.add(LS, IndexType::None, false, false);
2118  }
2119  }
2120 
2121  DEBUG({
2122  for (auto &P : FIRangeMap) {
2123  dbgs() << "fi#" << P.first;
2124  if (BadFIs.count(P.first))
2125  dbgs() << " (bad)";
2126  dbgs() << " RC: ";
2127  if (P.second.RC != nullptr)
2128  dbgs() << HRI.getRegClassName(P.second.RC) << '\n';
2129  else
2130  dbgs() << "<null>\n";
2131  for (auto &R : P.second.Map)
2132  dbgs() << " BB#" << R.first->getNumber() << " { " << R.second << "}\n";
2133  }
2134  });
2135 
2136  // When a slot is loaded from in a block without being stored to in the
2137  // same block, it is live-on-entry to this block. To avoid CFG analysis,
2138  // consider this slot to be live-on-exit from all blocks.
2139  SmallSet<int,4> LoxFIs;
2140 
2141  std::map<MachineBasicBlock*,std::vector<int>> BlockFIMap;
2142 
2143  for (auto &P : FIRangeMap) {
2144  // P = pair(FI, map: BB->RangeList)
2145  if (BadFIs.count(P.first))
2146  continue;
2147  for (auto &B : MF) {
2148  auto F = P.second.Map.find(&B);
2149  // F = pair(BB, RangeList)
2150  if (F == P.second.Map.end() || F->second.empty())
2151  continue;
2152  HexagonBlockRanges::IndexRange &IR = F->second.front();
2153  if (IR.start() == IndexType::Entry)
2154  LoxFIs.insert(P.first);
2155  BlockFIMap[&B].push_back(P.first);
2156  }
2157  }
2158 
2159  DEBUG({
2160  dbgs() << "Block-to-FI map (* -- live-on-exit):\n";
2161  for (auto &P : BlockFIMap) {
2162  auto &FIs = P.second;
2163  if (FIs.empty())
2164  continue;
2165  dbgs() << " BB#" << P.first->getNumber() << ": {";
2166  for (auto I : FIs) {
2167  dbgs() << " fi#" << I;
2168  if (LoxFIs.count(I))
2169  dbgs() << '*';
2170  }
2171  dbgs() << " }\n";
2172  }
2173  });
2174 
2175 #ifndef NDEBUG
2176  bool HasOptLimit = SpillOptMax.getPosition();
2177 #endif
2178 
2179  // eliminate loads, when all loads eliminated, eliminate all stores.
2180  for (auto &B : MF) {
2181  auto F = BlockIndexes.find(&B);
2182  assert(F != BlockIndexes.end());
2183  HexagonBlockRanges::InstrIndexMap &IM = F->second;
2186  DEBUG(dbgs() << "BB#" << B.getNumber() << " dead map\n"
2187  << HexagonBlockRanges::PrintRangeMap(DM, HRI));
2188 
2189  for (auto FI : BlockFIMap[&B]) {
2190  if (BadFIs.count(FI))
2191  continue;
2192  DEBUG(dbgs() << "Working on fi#" << FI << '\n');
2193  HexagonBlockRanges::RangeList &RL = FIRangeMap[FI].Map[&B];
2194  for (auto &Range : RL) {
2195  DEBUG(dbgs() << "--Examining range:" << RL << '\n');
2196  if (!IndexType::isInstr(Range.start()) ||
2197  !IndexType::isInstr(Range.end()))
2198  continue;
2199  MachineInstr &SI = *IM.getInstr(Range.start());
2200  MachineInstr &EI = *IM.getInstr(Range.end());
2201  assert(SI.mayStore() && "Unexpected start instruction");
2202  assert(EI.mayLoad() && "Unexpected end instruction");
2203  MachineOperand &SrcOp = SI.getOperand(2);
2204 
2205  HexagonBlockRanges::RegisterRef SrcRR = { SrcOp.getReg(),
2206  SrcOp.getSubReg() };
2207  auto *RC = HII.getRegClass(SI.getDesc(), 2, &HRI, MF);
2208  // The this-> is needed to unconfuse MSVC.
2209  unsigned FoundR = this->findPhysReg(MF, Range, IM, DM, RC);
2210  DEBUG(dbgs() << "Replacement reg:" << PrintReg(FoundR, &HRI) << '\n');
2211  if (FoundR == 0)
2212  continue;
2213 #ifndef NDEBUG
2214  if (HasOptLimit) {
2215  if (SpillOptCount >= SpillOptMax)
2216  return;
2217  SpillOptCount++;
2218  }
2219 #endif
2220 
2221  // Generate the copy-in: "FoundR = COPY SrcR" at the store location.
2222  MachineBasicBlock::iterator StartIt = SI.getIterator(), NextIt;
2223  MachineInstr *CopyIn = nullptr;
2224  if (SrcRR.Reg != FoundR || SrcRR.Sub != 0) {
2225  const DebugLoc &DL = SI.getDebugLoc();
2226  CopyIn = BuildMI(B, StartIt, DL, HII.get(TargetOpcode::COPY), FoundR)
2227  .add(SrcOp);
2228  }
2229 
2230  ++StartIt;
2231  // Check if this is a last store and the FI is live-on-exit.
2232  if (LoxFIs.count(FI) && (&Range == &RL.back())) {
2233  // Update store's source register.
2234  if (unsigned SR = SrcOp.getSubReg())
2235  SrcOp.setReg(HRI.getSubReg(FoundR, SR));
2236  else
2237  SrcOp.setReg(FoundR);
2238  SrcOp.setSubReg(0);
2239  // We are keeping this register live.
2240  SrcOp.setIsKill(false);
2241  } else {
2242  B.erase(&SI);
2243  IM.replaceInstr(&SI, CopyIn);
2244  }
2245 
2246  auto EndIt = std::next(EI.getIterator());
2247  for (auto It = StartIt; It != EndIt; It = NextIt) {
2248  MachineInstr &MI = *It;
2249  NextIt = std::next(It);
2250  int TFI;
2251  if (!HII.isLoadFromStackSlot(MI, TFI) || TFI != FI)
2252  continue;
2253  unsigned DstR = MI.getOperand(0).getReg();
2254  assert(MI.getOperand(0).getSubReg() == 0);
2255  MachineInstr *CopyOut = nullptr;
2256  if (DstR != FoundR) {
2257  DebugLoc DL = MI.getDebugLoc();
2258  unsigned MemSize = HII.getMemAccessSize(MI);
2259  assert(HII.getAddrMode(MI) == HexagonII::BaseImmOffset);
2260  unsigned CopyOpc = TargetOpcode::COPY;
2261  if (HII.isSignExtendingLoad(MI))
2262  CopyOpc = (MemSize == 1) ? Hexagon::A2_sxtb : Hexagon::A2_sxth;
2263  else if (HII.isZeroExtendingLoad(MI))
2264  CopyOpc = (MemSize == 1) ? Hexagon::A2_zxtb : Hexagon::A2_zxth;
2265  CopyOut = BuildMI(B, It, DL, HII.get(CopyOpc), DstR)
2266  .addReg(FoundR, getKillRegState(&MI == &EI));
2267  }
2268  IM.replaceInstr(&MI, CopyOut);
2269  B.erase(It);
2270  }
2271 
2272  // Update the dead map.
2273  HexagonBlockRanges::RegisterRef FoundRR = { FoundR, 0 };
2274  for (auto RR : HexagonBlockRanges::expandToSubRegs(FoundRR, MRI, HRI))
2275  DM[RR].subtract(Range);
2276  } // for Range in range list
2277  }
2278  }
2279 }
2280 
2281 void HexagonFrameLowering::expandAlloca(MachineInstr *AI,
2282  const HexagonInstrInfo &HII, unsigned SP, unsigned CF) const {
2283  MachineBasicBlock &MB = *AI->getParent();
2284  DebugLoc DL = AI->getDebugLoc();
2285  unsigned A = AI->getOperand(2).getImm();
2286 
2287  // Have
2288  // Rd = alloca Rs, #A
2289  //
2290  // If Rs and Rd are different registers, use this sequence:
2291  // Rd = sub(r29, Rs)
2292  // r29 = sub(r29, Rs)
2293  // Rd = and(Rd, #-A) ; if necessary
2294  // r29 = and(r29, #-A) ; if necessary
2295  // Rd = add(Rd, #CF) ; CF size aligned to at most A
2296  // otherwise, do
2297  // Rd = sub(r29, Rs)
2298  // Rd = and(Rd, #-A) ; if necessary
2299  // r29 = Rd
2300  // Rd = add(Rd, #CF) ; CF size aligned to at most A
2301 
2302  MachineOperand &RdOp = AI->getOperand(0);
2303  MachineOperand &RsOp = AI->getOperand(1);
2304  unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg();
2305 
2306  // Rd = sub(r29, Rs)
2307  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), Rd)
2308  .addReg(SP)
2309  .addReg(Rs);
2310  if (Rs != Rd) {
2311  // r29 = sub(r29, Rs)
2312  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), SP)
2313  .addReg(SP)
2314  .addReg(Rs);
2315  }
2316  if (A > 8) {
2317  // Rd = and(Rd, #-A)
2318  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), Rd)
2319  .addReg(Rd)
2320  .addImm(-int64_t(A));
2321  if (Rs != Rd)
2322  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), SP)
2323  .addReg(SP)
2324  .addImm(-int64_t(A));
2325  }
2326  if (Rs == Rd) {
2327  // r29 = Rd
2328  BuildMI(MB, AI, DL, HII.get(TargetOpcode::COPY), SP)
2329  .addReg(Rd);
2330  }
2331  if (CF > 0) {
2332  // Rd = add(Rd, #CF)
2333  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_addi), Rd)
2334  .addReg(Rd)
2335  .addImm(CF);
2336  }
2337 }
2338 
2340  const MachineFrameInfo &MFI = MF.getFrameInfo();
2341  if (!MFI.hasVarSizedObjects())
2342  return false;
2343  unsigned MaxA = MFI.getMaxAlignment();
2344  if (MaxA <= getStackAlignment())
2345  return false;
2346  return true;
2347 }
2348 
2350  const MachineFunction &MF) const {
2351  for (auto &B : MF)
2352  for (auto &I : B)
2353  if (I.getOpcode() == Hexagon::PS_aligna)
2354  return &I;
2355  return nullptr;
2356 }
2357 
2358 /// Adds all callee-saved registers as implicit uses or defs to the
2359 /// instruction.
2360 void HexagonFrameLowering::addCalleeSaveRegistersAsImpOperand(MachineInstr *MI,
2361  const CSIVect &CSI, bool IsDef, bool IsKill) const {
2362  // Add the callee-saved registers as implicit uses.
2363  for (auto &R : CSI)
2364  MI->addOperand(MachineOperand::CreateReg(R.getReg(), IsDef, true, IsKill));
2365 }
2366 
2367 /// Determine whether the callee-saved register saves and restores should
2368 /// be generated via inline code. If this function returns "true", inline
2369 /// code will be generated. If this function returns "false", additional
2370 /// checks are performed, which may still lead to the inline code.
2371 bool HexagonFrameLowering::shouldInlineCSR(const MachineFunction &MF,
2372  const CSIVect &CSI) const {
2374  return true;
2375  if (!hasFP(MF))
2376  return true;
2377  if (!isOptSize(MF) && !isMinSize(MF))
2379  return true;
2380 
2381  // Check if CSI only has double registers, and if the registers form
2382  // a contiguous block starting from D8.
2383  BitVector Regs(Hexagon::NUM_TARGET_REGS);
2384  for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
2385  unsigned R = CSI[i].getReg();
2386  if (!Hexagon::DoubleRegsRegClass.contains(R))
2387  return true;
2388  Regs[R] = true;
2389  }
2390  int F = Regs.find_first();
2391  if (F != Hexagon::D8)
2392  return true;
2393  while (F >= 0) {
2394  int N = Regs.find_next(F);
2395  if (N >= 0 && N != F+1)
2396  return true;
2397  F = N;
2398  }
2399 
2400  return false;
2401 }
2402 
2403 bool HexagonFrameLowering::useSpillFunction(const MachineFunction &MF,
2404  const CSIVect &CSI) const {
2405  if (shouldInlineCSR(MF, CSI))
2406  return false;
2407  unsigned NumCSI = CSI.size();
2408  if (NumCSI <= 1)
2409  return false;
2410 
2411  unsigned Threshold = isOptSize(MF) ? SpillFuncThresholdOs
2413  return Threshold < NumCSI;
2414 }
2415 
2416 bool HexagonFrameLowering::useRestoreFunction(const MachineFunction &MF,
2417  const CSIVect &CSI) const {
2418  if (shouldInlineCSR(MF, CSI))
2419  return false;
2420  // The restore functions do a bit more than just restoring registers.
2421  // The non-returning versions will go back directly to the caller's
2422  // caller, others will clean up the stack frame in preparation for
2423  // a tail call. Using them can still save code size even if only one
2424  // register is getting restores. Make the decision based on -Oz:
2425  // using -Os will use inline restore for a single register.
2426  if (isMinSize(MF))
2427  return true;
2428  unsigned NumCSI = CSI.size();
2429  if (NumCSI <= 1)
2430  return false;
2431 
2432  unsigned Threshold = isOptSize(MF) ? SpillFuncThresholdOs-1
2434  return Threshold < NumCSI;
2435 }
2436 
2437 bool HexagonFrameLowering::mayOverflowFrameOffset(MachineFunction &MF) const {
2438  unsigned StackSize = MF.getFrameInfo().estimateStackSize(MF);
2439  auto &HST = MF.getSubtarget<HexagonSubtarget>();
2440  // A fairly simplistic guess as to whether a potential load/store to a
2441  // stack location could require an extra register.
2442  if (HST.useHVXOps() && StackSize > 256)
2443  return true;
2444 
2445  // Check if the function has store-immediate instructions that access
2446  // the stack. Since the offset field is not extendable, if the stack
2447  // size exceeds the offset limit (6 bits, shifted), the stores will
2448  // require a new base register.
2449  bool HasImmStack = false;
2450  unsigned MinLS = ~0u; // Log_2 of the memory access size.
2451 
2452  for (const MachineBasicBlock &B : MF) {
2453  for (const MachineInstr &MI : B) {
2454  unsigned LS = 0;
2455  switch (MI.getOpcode()) {
2456  case Hexagon::S4_storeirit_io:
2457  case Hexagon::S4_storeirif_io:
2458  case Hexagon::S4_storeiri_io:
2459  ++LS;
2461  case Hexagon::S4_storeirht_io:
2462  case Hexagon::S4_storeirhf_io:
2463  case Hexagon::S4_storeirh_io:
2464  ++LS;
2466  case Hexagon::S4_storeirbt_io:
2467  case Hexagon::S4_storeirbf_io:
2468  case Hexagon::S4_storeirb_io:
2469  if (MI.getOperand(0).isFI())
2470  HasImmStack = true;
2471  MinLS = std::min(MinLS, LS);
2472  break;
2473  }
2474  }
2475  }
2476 
2477  if (HasImmStack)
2478  return !isUInt<6>(StackSize >> MinLS);
2479 
2480  return false;
2481 }
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:372
uint64_t CallInst * C
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
BitVector & set()
Definition: BitVector.h:398
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:458
instr_iterator instr_end()
bool hasDebugInfo() const
Returns true if valid debug info is present.
void mapLocalFrameObject(int ObjectIndex, int64_t Offset)
Map a frame index into the local object block.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
void stepForward(const MachineInstr &MI, SmallVectorImpl< std::pair< unsigned, const MachineOperand *>> &Clobbers)
Simulates liveness when stepping forward over an instruction(bundle).
static cl::opt< int > SpillFuncThresholdOs("spill-func-threshold-Os", cl::Hidden, cl::desc("Specify Os spill func threshold"), cl::init(1), cl::ZeroOrMore)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
size_type size() const
Determine the number of elements in the SetVector.
Definition: SetVector.h:78
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
INITIALIZE_PASS(HexagonCallFrameInformation, "hexagon-cfi", "Hexagon call frame information", false, false) FunctionPass *llvm
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID&#39;s allocated.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
MachineBasicBlock * findNearestCommonDominator(MachineBasicBlock *A, MachineBasicBlock *B)
bool isDeadObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a dead object.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:268
static Optional< MachineBasicBlock::iterator > findCFILocation(MachineBasicBlock &B)
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
int64_t getLocalFrameSize() const
Get the size of the local object blob.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:404
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI)
unsigned getSubReg() const
static RegisterSet expandToSubRegs(RegisterRef R, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI)
static const MCPhysReg VRegs[32]
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:262
Hexagon target-specific information for each MachineFunction.
A debug info location.
Definition: DebugLoc.h:34
F(f)
MachineModuleInfo & getMMI() const
static const char * getSpillFunctionFor(unsigned MaxReg, SpillKind SpillType, bool Stkchk=false)
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:677
#define R2(n)
static unsigned SpillOptCount
static cl::opt< int > SpillFuncThreshold("spill-func-threshold", cl::Hidden, cl::desc("Specify O2(not Os) spill func threshold"), cl::init(6), cl::ZeroOrMore)
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:332
static cl::opt< unsigned > SpillOptMax("spill-opt-max", cl::Hidden, cl::init(std::numeric_limits< unsigned >::max()))
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
return AArch64::GPR64RegClass contains(Reg)
iterator_range< succ_iterator > successors()
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
std::map< RegisterRef, RangeList > RegToRangeMap
bool isEHReturnCalleeSaveReg(unsigned Reg) const
unsigned getSpillAlignment(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class...
void add(IndexType Start, IndexType End, bool Fixed, bool TiedEnd)
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index...
void setLocalFrameSize(int64_t sz)
Set the size of the local object blob.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
void setUseLocalStackAllocationBlock(bool v)
setUseLocalStackAllocationBlock - Set whether the local allocation blob should be allocated together ...
MCSuperRegIterator enumerates all super-registers of Reg.
bool contains(unsigned Reg) const
Returns true if register Reg is contained in the set.
Definition: LivePhysRegs.h:106
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Definition: BitVector.h:332
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
static cl::opt< bool > EnableStackOVFSanitizer("enable-stackovf-sanitizer", cl::Hidden, cl::desc("Enable runtime checks for stack overflow."), cl::init(false), cl::ZeroOrMore)
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
Definition: BitVector.h:340
Reg
All possible values of the reg field in the ModR/M byte.
static cl::opt< bool > EnableShrinkWrapping("hexagon-shrink-frame", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable stack frame shrink wrapping"))
This file contains the simple types necessary to represent the attributes associated with functions a...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
static unsigned getMax32BitSubRegister(unsigned Reg, const TargetRegisterInfo &TRI, bool hireg=true)
Map a register pair Reg to the subregister that has the greater "number", i.e.
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:287
const MachineInstr * getAlignaInstr(const MachineFunction &MF) const
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:142
static bool isMinSize(const MachineFunction &MF)
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
const MCContext & getContext() const
const RegList & Regs
static bool hasTailCall(const MachineBasicBlock &MBB)
Returns true if MBB has a machine instructions that indicates a tail call in the block.
void setLocalFrameMaxAlign(unsigned Align)
Required alignment of the local object blob, which is the strictest alignment of any object in it...
int getObjectIndexEnd() const
Return one past the maximum frame object index.
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they&#39;re not in a MachineFuncti...
MachineBasicBlock * findNearestCommonDominator(MachineBasicBlock *A, MachineBasicBlock *B)
findNearestCommonDominator - Find nearest common dominator basic block for basic block A and B...
const MCPhysReg * getCallerSavedRegs(const MachineFunction *MF, const TargetRegisterClass *RC) const
static bool needsStackFrame(const MachineBasicBlock &MBB, const BitVector &CSR, const HexagonRegisterInfo &HRI)
Checks if the basic block contains any instruction that needs a stack frame to be already in place...
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
Perform most of the PEI work here:
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
unsigned getKillRegState(bool B)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
static cl::opt< bool > EliminateFramePointer("hexagon-fp-elim", cl::init(true), cl::Hidden, cl::desc("Refrain from using FP whenever possible"))
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:454
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
A and B are either alignments or offsets.
Definition: MathExtras.h:602
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:639
#define P(N)
static bool needToReserveScavengingSpillSlots(MachineFunction &MF, const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC)
Returns true if there are no caller-saved registers available in class RC.
static bool isOptSize(const MachineFunction &MF)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:406
static cl::opt< unsigned > NumberScavengerSlots("number-scavenger-slots", cl::Hidden, cl::desc("Set the number of scavenger slots"), cl::init(2), cl::ZeroOrMore)
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
This file declares the machine register scavenger class.
MachineBasicBlock * getBlockNumbered(unsigned N) const
getBlockNumbered - MachineBasicBlocks are automatically numbered when they are inserted into the mach...
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
Definition: MCContext.cpp:215
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
unsigned const MachineRegisterInfo * MRI
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
Definition: MCDwarf.h:377
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:421
static cl::opt< bool > DisableDeallocRet("disable-hexagon-dealloc-ret", cl::Hidden, cl::desc("Disable Dealloc Return for Hexagon target"))
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
void setStackSize(uint64_t Size)
Set the size of the stack.
void addLiveIns(const MachineBasicBlock &MBB)
Adds all live-in registers of basic block MBB.
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE instructions.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:36
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
MCRegAliasIterator enumerates all registers aliasing Reg.
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
bool optForSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Definition: Function.h:530
static const unsigned End
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
self_iterator getIterator()
Definition: ilist_node.h:82
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:81
int CreateSpillStackObject(uint64_t Size, unsigned Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MachineBasicBlock & front() const
MCSubRegIterator enumerates all sub-registers of Reg.
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
IndexType getIndex(MachineInstr *MI) const
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
static MachineInstr * getReturn(MachineBasicBlock &MBB)
Returns the "return" instruction from this block, or nullptr if there isn&#39;t any.
static bool hasReturn(const MachineBasicBlock &MBB)
Returns true if MBB contains an instruction that returns.
The memory access writes data.
static cl::opt< unsigned > ShrinkLimit("shrink-frame-limit", cl::init(std::numeric_limits< unsigned >::max()), cl::Hidden, cl::ZeroOrMore, cl::desc("Max count of stack frame shrink-wraps"))
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:389
PostDominatorTree Class - Concrete subclass of DominatorTree that is used to compute the post-dominat...
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:864
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
unsigned estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI) const override
assignCalleeSavedSpillSlots - Allows target to override spill slot assignment logic.
int64_t getImm() const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
bool needsUnwindTableEntry() const
True if this function needs an unwind table.
Definition: Function.h:505
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
bool isPhysRegUsed(unsigned PhysReg) const
Return true if the specified register is modified or read in this function.
static cl::opt< bool > EnableSaveRestoreLong("enable-save-restore-long", cl::Hidden, cl::desc("Enable long calls for save-restore stubs."), cl::init(false), cl::ZeroOrMore)
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
FunctionPass * createHexagonCallFrameInformation()
bool runOnMachineFunction(MachineFunction &F) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
MachineFunctionProperties & set(Property P)
Representation of each machine instruction.
Definition: MachineInstr.h:59
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
RegToRangeMap computeLiveMap(InstrIndexMap &IndexMap)
void removeReg(unsigned Reg)
Removes a physical register, all its sub-registers, and all its super-registers from the set...
Definition: LivePhysRegs.h:89
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
static bool isRestoreCall(unsigned Opc)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:49
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:61
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
bool isPositionIndependent() const
StringRef getName() const
Return a constant reference to the value&#39;s name.
Definition: Value.cpp:220
static cl::opt< bool > OptimizeSpillSlots("hexagon-opt-spill", cl::Hidden, cl::init(true), cl::desc("Optimize spill slots"))
TargetOptions Options
Definition: TargetMachine.h:96
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
void setMaxCallFrameSize(unsigned S)
void insertCFIInstructions(MachineFunction &MF) const
unsigned getLocalFrameMaxAlign() const
Return the required alignment of the local object blob.
bool optForMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:527
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
RegToRangeMap computeDeadMap(InstrIndexMap &IndexMap, RegToRangeMap &LiveMap)
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
static int const Threshold
TODO: Write a new FunctionPass AliasAnalysis so that it can keep a cache.
const unsigned Kind
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:626
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const HexagonInstrInfo * getInstrInfo() const override
rpo Deduce function attributes in RPO
A vector that has set insertion semantics.
Definition: SetVector.h:41
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:235
#define DEBUG(X)
Definition: Debug.h:118
static bool isOptNone(const MachineFunction &MF)
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:57
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
IRTranslator LLVM IR MI
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:39
void initializeHexagonCallFrameInformationPass(PassRegistry &)
const MachineInstrBuilder & setMemRefs(MachineInstr::mmo_iterator b, MachineInstr::mmo_iterator e) const
auto find_if(R &&Range, UnaryPredicate P) -> decltype(std::begin(Range))
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:795
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
void setObjectAlignment(int ObjectIdx, unsigned Align)
setObjectAlignment - Change the alignment of the specified stack object.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
bool needsAligna(const MachineFunction &MF) const
static unsigned getMaxCalleeSavedReg(const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo &TRI)
Returns the callee saved register with the largest id in the vector.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Statically lint checks LLVM IR
Definition: Lint.cpp:193
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
Properties which a MachineFunction may have at a given point in time.
This class contains meta information specific to a module.
mmo_iterator memoperands_end() const
Definition: MachineInstr.h:390
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:65