24 #define GET_INSTRINFO_CTOR_DTOR 25 #include "NVPTXGenInstrInfo.inc" 28 void NVPTXInstrInfo::anchor() {}
34 const DebugLoc &DL,
unsigned DestReg,
35 unsigned SrcReg,
bool KillSrc)
const {
40 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC))
44 if (DestRC == &NVPTX::Int1RegsRegClass) {
46 }
else if (DestRC == &NVPTX::Int16RegsRegClass) {
48 }
else if (DestRC == &NVPTX::Int32RegsRegClass) {
49 Op = (SrcRC == &NVPTX::Int32RegsRegClass ? NVPTX::IMOV32rr
50 : NVPTX::BITCONVERT_32_F2I);
51 }
else if (DestRC == &NVPTX::Int64RegsRegClass) {
52 Op = (SrcRC == &NVPTX::Int64RegsRegClass ? NVPTX::IMOV64rr
53 : NVPTX::BITCONVERT_64_F2I);
54 }
else if (DestRC == &NVPTX::Float16RegsRegClass) {
55 Op = (SrcRC == &NVPTX::Float16RegsRegClass ? NVPTX::FMOV16rr
56 : NVPTX::BITCONVERT_16_I2F);
57 }
else if (DestRC == &NVPTX::Float16x2RegsRegClass) {
59 }
else if (DestRC == &NVPTX::Float32RegsRegClass) {
60 Op = (SrcRC == &NVPTX::Float32RegsRegClass ? NVPTX::FMOV32rr
61 : NVPTX::BITCONVERT_32_I2F);
62 }
else if (DestRC == &NVPTX::Float64RegsRegClass) {
63 Op = (SrcRC == &NVPTX::Float64RegsRegClass ? NVPTX::FMOV64rr
64 : NVPTX::BITCONVERT_64_I2F);
68 BuildMI(MBB, I, DL,
get(Op), DestReg)
99 bool AllowModify)
const {
102 if (I == MBB.
begin() || !isUnpredicatedTerminator(*--I))
109 if (I == MBB.
begin() || !isUnpredicatedTerminator(*--I)) {
110 if (LastInst.
getOpcode() == NVPTX::GOTO) {
113 }
else if (LastInst.
getOpcode() == NVPTX::CBranch) {
127 if (I != MBB.
begin() && isUnpredicatedTerminator(*--I))
131 if (SecondLastInst.
getOpcode() == NVPTX::CBranch &&
141 if (SecondLastInst.
getOpcode() == NVPTX::GOTO &&
146 I->eraseFromParent();
155 int *BytesRemoved)
const {
156 assert(!BytesRemoved &&
"code size not handled");
158 if (I == MBB.
begin())
161 if (I->getOpcode() != NVPTX::GOTO && I->getOpcode() != NVPTX::CBranch)
165 I->eraseFromParent();
169 if (I == MBB.
begin())
172 if (I->getOpcode() != NVPTX::CBranch)
176 I->eraseFromParent();
185 int *BytesAdded)
const {
186 assert(!BytesAdded &&
"code size not handled");
189 assert(TBB &&
"insertBranch must not be told to insert a fallthrough");
191 "NVPTX branch conditions have two components!");
196 BuildMI(&MBB, DL,
get(NVPTX::GOTO)).addMBB(TBB);
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
MachineBasicBlock * getMBB() const
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
This class represents lattice values for constants.
void push_back(const T &Elt)
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
unsigned getKillRegState(bool B)
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned const MachineRegisterInfo * MRI
size_t size() const
size - Get the array size.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
AnalyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understo...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MachineOperand & getOperand(unsigned i) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool empty() const
empty - Check if the array is empty.