LLVM  6.0.0svn
MipsInstrInfo.cpp
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1 //===- MipsInstrInfo.cpp - Mips Instruction Information -------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Mips implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsInstrInfo.h"
17 #include "MipsSubtarget.h"
18 #include "llvm/ADT/SmallVector.h"
27 #include "llvm/IR/DebugLoc.h"
28 #include "llvm/MC/MCInstrDesc.h"
30 #include <cassert>
31 
32 using namespace llvm;
33 
34 #define GET_INSTRINFO_CTOR_DTOR
35 #include "MipsGenInstrInfo.inc"
36 
37 // Pin the vtable to this file.
38 void MipsInstrInfo::anchor() {}
39 
40 MipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBr)
41  : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
42  Subtarget(STI), UncondBrOpc(UncondBr) {}
43 
45  if (STI.inMips16Mode())
46  return createMips16InstrInfo(STI);
47 
48  return createMipsSEInstrInfo(STI);
49 }
50 
52  return op.isImm() && op.getImm() == 0;
53 }
54 
55 /// insertNoop - If data hazard condition is found insert the target nop
56 /// instruction.
57 // FIXME: This appears to be dead code.
58 void MipsInstrInfo::
60 {
61  DebugLoc DL;
62  BuildMI(MBB, MI, DL, get(Mips::NOP));
63 }
64 
67  MachineMemOperand::Flags Flags) const {
68  MachineFunction &MF = *MBB.getParent();
69  MachineFrameInfo &MFI = MF.getFrameInfo();
70  unsigned Align = MFI.getObjectAlignment(FI);
71 
73  Flags, MFI.getObjectSize(FI), Align);
74 }
75 
76 //===----------------------------------------------------------------------===//
77 // Branch Analysis
78 //===----------------------------------------------------------------------===//
79 
80 void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
81  MachineBasicBlock *&BB,
82  SmallVectorImpl<MachineOperand> &Cond) const {
83  assert(getAnalyzableBrOpc(Opc) && "Not an analyzable branch");
84  int NumOp = Inst->getNumExplicitOperands();
85 
86  // for both int and fp branches, the last explicit operand is the
87  // MBB.
88  BB = Inst->getOperand(NumOp-1).getMBB();
90 
91  for (int i = 0; i < NumOp-1; i++)
92  Cond.push_back(Inst->getOperand(i));
93 }
94 
96  MachineBasicBlock *&TBB,
97  MachineBasicBlock *&FBB,
99  bool AllowModify) const {
100  SmallVector<MachineInstr*, 2> BranchInstrs;
101  BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
102 
103  return (BT == BT_None) || (BT == BT_Indirect);
104 }
105 
106 void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
107  const DebugLoc &DL,
108  ArrayRef<MachineOperand> Cond) const {
109  unsigned Opc = Cond[0].getImm();
110  const MCInstrDesc &MCID = get(Opc);
111  MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
112 
113  for (unsigned i = 1; i < Cond.size(); ++i) {
114  assert((Cond[i].isImm() || Cond[i].isReg()) &&
115  "Cannot copy operand for conditional branch!");
116  MIB.add(Cond[i]);
117  }
118  MIB.addMBB(TBB);
119 }
120 
122  MachineBasicBlock *TBB,
123  MachineBasicBlock *FBB,
125  const DebugLoc &DL,
126  int *BytesAdded) const {
127  // Shouldn't be a fall through.
128  assert(TBB && "insertBranch must not be told to insert a fallthrough");
129  assert(!BytesAdded && "code size not handled");
130 
131  // # of condition operands:
132  // Unconditional branches: 0
133  // Floating point branches: 1 (opc)
134  // Int BranchZero: 2 (opc, reg)
135  // Int Branch: 3 (opc, reg0, reg1)
136  assert((Cond.size() <= 3) &&
137  "# of Mips branch conditions must be <= 3!");
138 
139  // Two-way Conditional branch.
140  if (FBB) {
141  BuildCondBr(MBB, TBB, DL, Cond);
142  BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
143  return 2;
144  }
145 
146  // One way branch.
147  // Unconditional branch.
148  if (Cond.empty())
149  BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
150  else // Conditional branch.
151  BuildCondBr(MBB, TBB, DL, Cond);
152  return 1;
153 }
154 
156  int *BytesRemoved) const {
157  assert(!BytesRemoved && "code size not handled");
158 
159  MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
160  unsigned removed = 0;
161 
162  // Up to 2 branches are removed.
163  // Note that indirect branches are not removed.
164  while (I != REnd && removed < 2) {
165  // Skip past debug instructions.
166  if (I->isDebugValue()) {
167  ++I;
168  continue;
169  }
170  if (!getAnalyzableBrOpc(I->getOpcode()))
171  break;
172  // Remove the branch.
173  I->eraseFromParent();
174  I = MBB.rbegin();
175  ++removed;
176  }
177 
178  return removed;
179 }
180 
181 /// reverseBranchCondition - Return the inverse opcode of the
182 /// specified Branch instruction.
184  SmallVectorImpl<MachineOperand> &Cond) const {
185  assert( (Cond.size() && Cond.size() <= 3) &&
186  "Invalid Mips branch condition!");
187  Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
188  return false;
189 }
190 
193  SmallVectorImpl<MachineOperand> &Cond, bool AllowModify,
194  SmallVectorImpl<MachineInstr *> &BranchInstrs) const {
195  MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
196 
197  // Skip all the debug instructions.
198  while (I != REnd && I->isDebugValue())
199  ++I;
200 
201  if (I == REnd || !isUnpredicatedTerminator(*I)) {
202  // This block ends with no branches (it just falls through to its succ).
203  // Leave TBB/FBB null.
204  TBB = FBB = nullptr;
205  return BT_NoBranch;
206  }
207 
208  MachineInstr *LastInst = &*I;
209  unsigned LastOpc = LastInst->getOpcode();
210  BranchInstrs.push_back(LastInst);
211 
212  // Not an analyzable branch (e.g., indirect jump).
213  if (!getAnalyzableBrOpc(LastOpc))
214  return LastInst->isIndirectBranch() ? BT_Indirect : BT_None;
215 
216  // Get the second to last instruction in the block.
217  unsigned SecondLastOpc = 0;
218  MachineInstr *SecondLastInst = nullptr;
219 
220  // Skip past any debug instruction to see if the second last actual
221  // is a branch.
222  ++I;
223  while (I != REnd && I->isDebugValue())
224  ++I;
225 
226  if (I != REnd) {
227  SecondLastInst = &*I;
228  SecondLastOpc = getAnalyzableBrOpc(SecondLastInst->getOpcode());
229 
230  // Not an analyzable branch (must be an indirect jump).
231  if (isUnpredicatedTerminator(*SecondLastInst) && !SecondLastOpc)
232  return BT_None;
233  }
234 
235  // If there is only one terminator instruction, process it.
236  if (!SecondLastOpc) {
237  // Unconditional branch.
238  if (LastInst->isUnconditionalBranch()) {
239  TBB = LastInst->getOperand(0).getMBB();
240  return BT_Uncond;
241  }
242 
243  // Conditional branch
244  AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
245  return BT_Cond;
246  }
247 
248  // If we reached here, there are two branches.
249  // If there are three terminators, we don't know what sort of block this is.
250  if (++I != REnd && isUnpredicatedTerminator(*I))
251  return BT_None;
252 
253  BranchInstrs.insert(BranchInstrs.begin(), SecondLastInst);
254 
255  // If second to last instruction is an unconditional branch,
256  // analyze it and remove the last instruction.
257  if (SecondLastInst->isUnconditionalBranch()) {
258  // Return if the last instruction cannot be removed.
259  if (!AllowModify)
260  return BT_None;
261 
262  TBB = SecondLastInst->getOperand(0).getMBB();
263  LastInst->eraseFromParent();
264  BranchInstrs.pop_back();
265  return BT_Uncond;
266  }
267 
268  // Conditional branch followed by an unconditional branch.
269  // The last one must be unconditional.
270  if (!LastInst->isUnconditionalBranch())
271  return BT_None;
272 
273  AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
274  FBB = LastInst->getOperand(0).getMBB();
275 
276  return BT_CondUncond;
277 }
278 
279 /// Return the corresponding compact (no delay slot) form of a branch.
281  const MachineBasicBlock::iterator I) const {
282  unsigned Opcode = I->getOpcode();
283  bool canUseShortMicroMipsCTI = false;
284 
285  if (Subtarget.inMicroMipsMode()) {
286  switch (Opcode) {
287  case Mips::BNE:
288  case Mips::BNE_MM:
289  case Mips::BEQ:
290  case Mips::BEQ_MM:
291  // microMIPS has NE,EQ branches that do not have delay slots provided one
292  // of the operands is zero.
293  if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg())
294  canUseShortMicroMipsCTI = true;
295  break;
296  // For microMIPS the PseudoReturn and PseudoIndirectBranch are always
297  // expanded to JR_MM, so they can be replaced with JRC16_MM.
298  case Mips::JR:
299  case Mips::PseudoReturn:
300  case Mips::PseudoIndirectBranch:
301  case Mips::TAILCALLREG:
302  canUseShortMicroMipsCTI = true;
303  break;
304  }
305  }
306 
307  // MIPSR6 forbids both operands being the zero register.
308  if (Subtarget.hasMips32r6() && (I->getNumOperands() > 1) &&
309  (I->getOperand(0).isReg() &&
310  (I->getOperand(0).getReg() == Mips::ZERO ||
311  I->getOperand(0).getReg() == Mips::ZERO_64)) &&
312  (I->getOperand(1).isReg() &&
313  (I->getOperand(1).getReg() == Mips::ZERO ||
314  I->getOperand(1).getReg() == Mips::ZERO_64)))
315  return 0;
316 
317  if (Subtarget.hasMips32r6() || canUseShortMicroMipsCTI) {
318  switch (Opcode) {
319  case Mips::B:
320  return Mips::BC;
321  case Mips::BAL:
322  return Mips::BALC;
323  case Mips::BEQ:
324  case Mips::BEQ_MM:
325  if (canUseShortMicroMipsCTI)
326  return Mips::BEQZC_MM;
327  else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
328  return 0;
329  return Mips::BEQC;
330  case Mips::BNE:
331  case Mips::BNE_MM:
332  if (canUseShortMicroMipsCTI)
333  return Mips::BNEZC_MM;
334  else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
335  return 0;
336  return Mips::BNEC;
337  case Mips::BGE:
338  if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
339  return 0;
340  return Mips::BGEC;
341  case Mips::BGEU:
342  if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
343  return 0;
344  return Mips::BGEUC;
345  case Mips::BGEZ:
346  return Mips::BGEZC;
347  case Mips::BGTZ:
348  return Mips::BGTZC;
349  case Mips::BLEZ:
350  return Mips::BLEZC;
351  case Mips::BLT:
352  if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
353  return 0;
354  return Mips::BLTC;
355  case Mips::BLTU:
356  if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
357  return 0;
358  return Mips::BLTUC;
359  case Mips::BLTZ:
360  return Mips::BLTZC;
361  case Mips::BEQ64:
362  if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
363  return 0;
364  return Mips::BEQC64;
365  case Mips::BNE64:
366  if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
367  return 0;
368  return Mips::BNEC64;
369  case Mips::BGTZ64:
370  return Mips::BGTZC64;
371  case Mips::BGEZ64:
372  return Mips::BGEZC64;
373  case Mips::BLTZ64:
374  return Mips::BLTZC64;
375  case Mips::BLEZ64:
376  return Mips::BLEZC64;
377  // For MIPSR6, the instruction 'jic' can be used for these cases. Some
378  // tools will accept 'jrc reg' as an alias for 'jic 0, $reg'.
379  case Mips::JR:
380  case Mips::PseudoReturn:
381  case Mips::PseudoIndirectBranch:
382  case Mips::TAILCALLREG:
383  if (canUseShortMicroMipsCTI)
384  return Mips::JRC16_MM;
385  return Mips::JIC;
386  case Mips::JALRPseudo:
387  return Mips::JIALC;
388  case Mips::JR64:
389  case Mips::PseudoReturn64:
390  case Mips::PseudoIndirectBranch64:
391  case Mips::TAILCALLREG64:
392  return Mips::JIC64;
393  case Mips::JALR64Pseudo:
394  return Mips::JIALC64;
395  default:
396  return 0;
397  }
398  }
399 
400  return 0;
401 }
402 
403 /// Predicate for distingushing between control transfer instructions and all
404 /// other instructions for handling forbidden slots. Consider inline assembly
405 /// as unsafe as well.
407  if (MI.isInlineAsm())
408  return false;
409 
410  return (MI.getDesc().TSFlags & MipsII::IsCTI) == 0;
411 }
412 
413 /// Predicate for distingushing instructions that have forbidden slots.
415  return (MI.getDesc().TSFlags & MipsII::HasForbiddenSlot) != 0;
416 }
417 
418 /// Return the number of bytes of code the specified instruction may be.
420  switch (MI.getOpcode()) {
421  default:
422  return MI.getDesc().getSize();
423  case TargetOpcode::INLINEASM: { // Inline Asm: Variable size.
424  const MachineFunction *MF = MI.getParent()->getParent();
425  const char *AsmStr = MI.getOperand(0).getSymbolName();
426  return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
427  }
428  case Mips::CONSTPOOL_ENTRY:
429  // If this machine instr is a constant pool entry, its size is recorded as
430  // operand #2.
431  return MI.getOperand(2).getImm();
432  }
433 }
434 
439 
440  // Certain branches have two forms: e.g beq $1, $zero, dest vs beqz $1, dest
441  // Pick the zero form of the branch for readable assembly and for greater
442  // branch distance in non-microMIPS mode.
443  // Additional MIPSR6 does not permit the use of register $zero for compact
444  // branches.
445  // FIXME: Certain atomic sequences on mips64 generate 32bit references to
446  // Mips::ZERO, which is incorrect. This test should be updated to use
447  // Subtarget.getABI().GetZeroReg() when those atomic sequences and others
448  // are fixed.
449  int ZeroOperandPosition = -1;
450  bool BranchWithZeroOperand = false;
451  if (I->isBranch() && !I->isPseudo()) {
452  auto TRI = I->getParent()->getParent()->getSubtarget().getRegisterInfo();
453  ZeroOperandPosition = I->findRegisterUseOperandIdx(Mips::ZERO, false, TRI);
454  BranchWithZeroOperand = ZeroOperandPosition != -1;
455  }
456 
457  if (BranchWithZeroOperand) {
458  switch (NewOpc) {
459  case Mips::BEQC:
460  NewOpc = Mips::BEQZC;
461  break;
462  case Mips::BNEC:
463  NewOpc = Mips::BNEZC;
464  break;
465  case Mips::BGEC:
466  NewOpc = Mips::BGEZC;
467  break;
468  case Mips::BLTC:
469  NewOpc = Mips::BLTZC;
470  break;
471  case Mips::BEQC64:
472  NewOpc = Mips::BEQZC64;
473  break;
474  case Mips::BNEC64:
475  NewOpc = Mips::BNEZC64;
476  break;
477  }
478  }
479 
480  MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
481 
482  // For MIPSR6 JI*C requires an immediate 0 as an operand, JIALC(64) an
483  // immediate 0 as an operand and requires the removal of it's %RA<imp-def>
484  // implicit operand as copying the implicit operations of the instructio we're
485  // looking at will give us the correct flags.
486  if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 ||
487  NewOpc == Mips::JIALC64) {
488 
489  if (NewOpc == Mips::JIALC || NewOpc == Mips::JIALC64)
490  MIB->RemoveOperand(0);
491 
492  for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
493  MIB.add(I->getOperand(J));
494  }
495 
496  MIB.addImm(0);
497 
498  } else {
499  for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
500  if (BranchWithZeroOperand && (unsigned)ZeroOperandPosition == J)
501  continue;
502 
503  MIB.add(I->getOperand(J));
504  }
505  }
506 
507  MIB.copyImplicitOps(*I);
508 
509  MIB.setMemRefs(I->memoperands_begin(), I->memoperands_end());
510  return MIB;
511 }
512 
514  unsigned &SrcOpIdx2) const {
515  assert(!MI.isBundle() &&
516  "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
517 
518  const MCInstrDesc &MCID = MI.getDesc();
519  if (!MCID.isCommutable())
520  return false;
521 
522  switch (MI.getOpcode()) {
523  case Mips::DPADD_U_H:
524  case Mips::DPADD_U_W:
525  case Mips::DPADD_U_D:
526  case Mips::DPADD_S_H:
527  case Mips::DPADD_S_W:
528  case Mips::DPADD_S_D:
529  // The first operand is both input and output, so it should not commute
530  if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3))
531  return false;
532 
533  if (!MI.getOperand(SrcOpIdx1).isReg() || !MI.getOperand(SrcOpIdx2).isReg())
534  return false;
535  return true;
536  }
537  return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
538 }
539 
540 // ins, ext, dext*, dins have the following constraints:
541 // 0 <= pos < X
542 // 0 < size <= X
543 // 0 < pos+size <= x
544 //
545 // dinsm and dinsm have the following contraints:
546 // 0 <= pos < X
547 // 0 <= size <= X
548 // 0 < pos+size <= x
549 
550 static bool verifyInsExtInstruction(const MachineInstr &MI, StringRef &ErrInfo,
551  const int64_t PosLow, const int64_t PosHigh,
552  const int64_t SizeLow,
553  const int64_t SizeHigh,
554  const int64_t BothLow,
555  const int64_t BothHigh) {
556  MachineOperand MOPos = MI.getOperand(2);
557  if (!MOPos.isImm()) {
558  ErrInfo = "Position is not an immediate!";
559  return false;
560  }
561  int64_t Pos = MOPos.getImm();
562  if (!((PosLow <= Pos) && (Pos < PosHigh))) {
563  ErrInfo = "Position operand is out of range!";
564  return false;
565  }
566 
567  MachineOperand MOSize = MI.getOperand(3);
568  if (!MOSize.isImm()) {
569  ErrInfo = "Size operand is not an immediate!";
570  return false;
571  }
572  int64_t Size = MOSize.getImm();
573  if (!((SizeLow < Size) && (Size <= SizeHigh))) {
574  ErrInfo = "Size operand is out of range!";
575  return false;
576  }
577 
578  if (!((BothLow < (Pos + Size)) && ((Pos + Size) <= BothHigh))) {
579  ErrInfo = "Position + Size is out of range!";
580  return false;
581  }
582 
583  return true;
584 }
585 
586 // Perform target specific instruction verification.
588  StringRef &ErrInfo) const {
589  // Verify that ins and ext instructions are well formed.
590  switch (MI.getOpcode()) {
591  case Mips::EXT:
592  case Mips::EXT_MM:
593  case Mips::INS:
594  case Mips::INS_MM:
595  case Mips::DINS:
596  case Mips::DINS_MM64R6:
597  return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 32);
598  case Mips::DINSM:
599  case Mips::DINSM_MM64R6:
600  // The ISA spec has a subtle difference here in that it says:
601  // 2 <= size <= 64 for 'dinsm', so we change the bounds so that it
602  // is in line with the rest of instructions.
603  return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 1, 64, 32, 64);
604  case Mips::DINSU:
605  case Mips::DINSU_MM64R6:
606  // The ISA spec has a subtle difference here in that it says:
607  // 2 <= size <= 64 for 'dinsm', so we change the bounds so that it
608  // is in line with the rest of instructions.
609  return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 1, 32, 32, 64);
610  case Mips::DEXT:
611  case Mips::DEXT_MM64R6:
612  return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 63);
613  case Mips::DEXTM:
614  case Mips::DEXTM_MM64R6:
615  return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 32, 64, 32, 64);
616  case Mips::DEXTU:
617  case Mips::DEXTU_MM64R6:
618  return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64);
619  default:
620  return true;
621  }
622 
623  return true;
624 }
625 
626 std::pair<unsigned, unsigned>
628  return std::make_pair(TF, 0u);
629 }
630 
633  using namespace MipsII;
634 
635  static const std::pair<unsigned, const char*> Flags[] = {
636  {MO_GOT, "mips-got"},
637  {MO_GOT_CALL, "mips-got-call"},
638  {MO_GPREL, "mips-gprel"},
639  {MO_ABS_HI, "mips-abs-hi"},
640  {MO_ABS_LO, "mips-abs-lo"},
641  {MO_TLSGD, "mips-tlsgd"},
642  {MO_TLSLDM, "mips-tlsldm"},
643  {MO_DTPREL_HI, "mips-dtprel-hi"},
644  {MO_DTPREL_LO, "mips-dtprel-lo"},
645  {MO_GOTTPREL, "mips-gottprel"},
646  {MO_TPREL_HI, "mips-tprel-hi"},
647  {MO_TPREL_LO, "mips-tprel-lo"},
648  {MO_GPOFF_HI, "mips-gpoff-hi"},
649  {MO_GPOFF_LO, "mips-gpoff-lo"},
650  {MO_GOT_DISP, "mips-got-disp"},
651  {MO_GOT_PAGE, "mips-got-page"},
652  {MO_GOT_OFST, "mips-got-ofst"},
653  {MO_HIGHER, "mips-higher"},
654  {MO_HIGHEST, "mips-highest"},
655  {MO_GOT_HI16, "mips-got-hi16"},
656  {MO_GOT_LO16, "mips-got-lo16"},
657  {MO_CALL_HI16, "mips-call-hi16"},
658  {MO_CALL_LO16, "mips-call-lo16"}
659  };
660  return makeArrayRef(Flags);
661 }
static bool isReg(const MCInst &MI, unsigned OpNo)
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
Return the number of bytes of code the specified instruction may be.
const MachineInstrBuilder & add(const MachineOperand &MO) const
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
MachineBasicBlock * getMBB() const
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Branch Analysis.
MO_TLSLDM - Represents the offset into the global offset table at which.
Definition: MipsBaseInfo.h:63
bool inMips16Mode() const
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
MO_HIGHER/HIGHEST - Represents the highest or higher half word of a 64-bit symbol address...
Definition: MipsBaseInfo.h:85
MO_GOT_HI16/LO16, MO_CALL_HI16/LO16 - Relocations used for large GOTs.
Definition: MipsBaseInfo.h:89
MO_TLSGD - Represents the offset into the global offset table at which.
Definition: MipsBaseInfo.h:58
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
bool isInlineAsm() const
Definition: MachineInstr.h:832
bool SafeInForbiddenSlot(const MachineInstr &MI) const
Predicate to determine if an instruction can go in a forbidden slot.
MachineMemOperand * GetMemOperand(MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const
A debug info location.
Definition: DebugLoc.h:34
virtual unsigned getOppositeBranchOpc(unsigned Opc) const =0
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
reverseBranchCondition - Return the inverse opcode of the specified Branch instruction.
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
Perform target specific instruction verification.
bool HasForbiddenSlot(const MachineInstr &MI) const
Predicate to determine if an instruction has a forbidden slot.
#define op(i)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert nop instruction when hazard condition is found.
static bool verifyInsExtInstruction(const MachineInstr &MI, StringRef &ErrInfo, const int64_t PosLow, const int64_t PosHigh, const int64_t SizeLow, const int64_t SizeHigh, const int64_t BothLow, const int64_t BothHigh)
A description of a memory reference used in the backend.
MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc)
IsCTI - Instruction is a Control Transfer Instruction.
Definition: MipsBaseInfo.h:121
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:451
bool inMicroMipsMode() const
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
const MipsSubtarget & Subtarget
Definition: MipsInstrInfo.h:46
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool hasMips32r6() const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
const char * getSymbolName() const
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:634
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:287
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MachineInstr.h:488
bool isBundle() const
Definition: MachineInstr.h:853
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
reverse_iterator rend()
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
reverse_iterator rbegin()
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
MO_GOT_CALL - Represents the offset into the global offset table at which the address of a call site ...
Definition: MipsBaseInfo.h:44
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
const MipsInstrInfo * createMips16InstrInfo(const MipsSubtarget &STI)
Create MipsInstrInfo objects.
MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc, MachineBasicBlock::iterator I) const
Create an instruction which has the same operands and memory operands as MI but has a new opcode...
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:116
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const
Determine the opcode of a non-delay slot form for a branch if one exists.
bool isZeroImm(const MachineOperand &op) const
const MipsABIInfo & getABI() const
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
MO_GOTTPREL - Represents the offset from the thread pointer (Initial.
Definition: MipsBaseInfo.h:69
bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:864
int64_t getImm() const
virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction...
HasForbiddenSlot - Instruction has a forbidden slot.
Definition: MipsBaseInfo.h:123
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
bool isUnconditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which always transfers control flow to some other block...
Definition: MachineInstr.h:504
const MachineInstrBuilder & copyImplicitOps(const MachineInstr &OtherMI) const
Copy all the implicit operands from OtherMI onto this one.
iterator insert(iterator I, T &&Elt)
Definition: SmallVector.h:482
Flags
Flags values. These may be or&#39;d together.
MO_TPREL_HI/LO - Represents the hi and low part of the offset from.
Definition: MipsBaseInfo.h:73
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Representation of each machine instruction.
Definition: MachineInstr.h:59
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:58
const MipsInstrInfo * createMipsSEInstrInfo(const MipsSubtarget &STI)
unsigned GetZeroReg() const
Definition: MipsABIInfo.cpp:85
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
const MachineInstrBuilder & setMemRefs(MachineInstr::mmo_iterator b, MachineInstr::mmo_iterator e) const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
static const MipsInstrInfo * create(MipsSubtarget &STI)
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:144
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:569