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Mips16InstrInfo.cpp
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1 //===- Mips16InstrInfo.cpp - Mips16 Instruction Information ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Mips16 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "Mips16InstrInfo.h"
14 #include "llvm/ADT/BitVector.h"
24 #include "llvm/IR/DebugLoc.h"
25 #include "llvm/MC/MCAsmInfo.h"
26 #include "llvm/Support/Debug.h"
30 #include <cassert>
31 #include <cctype>
32 #include <cstdint>
33 #include <cstdlib>
34 #include <cstring>
35 #include <iterator>
36 #include <vector>
37 
38 using namespace llvm;
39 
40 #define DEBUG_TYPE "mips16-instrinfo"
41 
43  : MipsInstrInfo(STI, Mips::Bimm16) {}
44 
46  return RI;
47 }
48 
49 /// isLoadFromStackSlot - If the specified machine instruction is a direct
50 /// load from a stack slot, return the virtual or physical register number of
51 /// the destination along with the FrameIndex of the loaded stack slot. If
52 /// not, return 0. This predicate must return 0 if the instruction has
53 /// any side effects other than loading from the stack slot.
55  int &FrameIndex) const {
56  return 0;
57 }
58 
59 /// isStoreToStackSlot - If the specified machine instruction is a direct
60 /// store to a stack slot, return the virtual or physical register number of
61 /// the source reg along with the FrameIndex of the loaded stack slot. If
62 /// not, return 0. This predicate must return 0 if the instruction has
63 /// any side effects other than storing to the stack slot.
65  int &FrameIndex) const {
66  return 0;
67 }
68 
71  const DebugLoc &DL, unsigned DestReg,
72  unsigned SrcReg, bool KillSrc) const {
73  unsigned Opc = 0;
74 
75  if (Mips::CPU16RegsRegClass.contains(DestReg) &&
76  Mips::GPR32RegClass.contains(SrcReg))
77  Opc = Mips::MoveR3216;
78  else if (Mips::GPR32RegClass.contains(DestReg) &&
79  Mips::CPU16RegsRegClass.contains(SrcReg))
80  Opc = Mips::Move32R16;
81  else if ((SrcReg == Mips::HI0) &&
82  (Mips::CPU16RegsRegClass.contains(DestReg)))
83  Opc = Mips::Mfhi16, SrcReg = 0;
84  else if ((SrcReg == Mips::LO0) &&
85  (Mips::CPU16RegsRegClass.contains(DestReg)))
86  Opc = Mips::Mflo16, SrcReg = 0;
87 
88  assert(Opc && "Cannot copy registers");
89 
90  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
91 
92  if (DestReg)
93  MIB.addReg(DestReg, RegState::Define);
94 
95  if (SrcReg)
96  MIB.addReg(SrcReg, getKillRegState(KillSrc));
97 }
98 
100  const MachineOperand *&Src,
101  const MachineOperand *&Dest) const {
102  if (MI.isMoveReg()) {
103  Dest = &MI.getOperand(0);
104  Src = &MI.getOperand(1);
105  return true;
106  }
107  return false;
108 }
109 
112  unsigned SrcReg, bool isKill, int FI,
113  const TargetRegisterClass *RC,
114  const TargetRegisterInfo *TRI,
115  int64_t Offset) const {
116  DebugLoc DL;
117  if (I != MBB.end()) DL = I->getDebugLoc();
119  unsigned Opc = 0;
120  if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
121  Opc = Mips::SwRxSpImmX16;
122  assert(Opc && "Register class not handled!");
123  BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)).
124  addFrameIndex(FI).addImm(Offset)
125  .addMemOperand(MMO);
126 }
127 
130  unsigned DestReg, int FI,
131  const TargetRegisterClass *RC,
132  const TargetRegisterInfo *TRI,
133  int64_t Offset) const {
134  DebugLoc DL;
135  if (I != MBB.end()) DL = I->getDebugLoc();
137  unsigned Opc = 0;
138 
139  if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
140  Opc = Mips::LwRxSpImmX16;
141  assert(Opc && "Register class not handled!");
142  BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
143  .addMemOperand(MMO);
144 }
145 
147  MachineBasicBlock &MBB = *MI.getParent();
148  switch (MI.getDesc().getOpcode()) {
149  default:
150  return false;
151  case Mips::RetRA16:
152  ExpandRetRA16(MBB, MI, Mips::JrcRa16);
153  break;
154  }
155 
156  MBB.erase(MI.getIterator());
157  return true;
158 }
159 
160 /// GetOppositeBranchOpc - Return the inverse of the specified
161 /// opcode, e.g. turning BEQ to BNE.
162 unsigned Mips16InstrInfo::getOppositeBranchOpc(unsigned Opc) const {
163  switch (Opc) {
164  case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16;
165  case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16;
166  case Mips::BeqzRxImm16: return Mips::BnezRxImm16;
167  case Mips::BnezRxImm16: return Mips::BeqzRxImm16;
168  case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16;
169  case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16;
170  case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16;
171  case Mips::Btnez16: return Mips::Bteqz16;
172  case Mips::BtnezX16: return Mips::BteqzX16;
173  case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16;
174  case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16;
175  case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16;
176  case Mips::Bteqz16: return Mips::Btnez16;
177  case Mips::BteqzX16: return Mips::BtnezX16;
178  case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16;
179  case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16;
180  case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX16;
181  case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX16;
182  case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16;
183  case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16;
184  }
185  llvm_unreachable("Illegal opcode!");
186 }
187 
189  const std::vector<CalleeSavedInfo> &CSI,
190  unsigned Flags = 0) {
191  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
192  // Add the callee-saved register as live-in. Do not add if the register is
193  // RA and return address is taken, because it has already been added in
194  // method MipsTargetLowering::lowerRETURNADDR.
195  // It's killed at the spill, unless the register is RA and return address
196  // is taken.
197  unsigned Reg = CSI[e-i-1].getReg();
198  switch (Reg) {
199  case Mips::RA:
200  case Mips::S0:
201  case Mips::S1:
202  MIB.addReg(Reg, Flags);
203  break;
204  case Mips::S2:
205  break;
206  default:
207  llvm_unreachable("unexpected mips16 callee saved register");
208 
209  }
210  }
211 }
212 
213 // Adjust SP by FrameSize bytes. Save RA, S0, S1
214 void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
215  MachineBasicBlock &MBB,
217  DebugLoc DL;
218  MachineFunction &MF = *MBB.getParent();
219  MachineFrameInfo &MFI = MF.getFrameInfo();
220  const BitVector Reserved = RI.getReservedRegs(MF);
221  bool SaveS2 = Reserved[Mips::S2];
223  unsigned Opc = ((FrameSize <= 128) && !SaveS2)? Mips::Save16:Mips::SaveX16;
224  MIB = BuildMI(MBB, I, DL, get(Opc));
225  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
226  addSaveRestoreRegs(MIB, CSI);
227  if (SaveS2)
228  MIB.addReg(Mips::S2);
229  if (isUInt<11>(FrameSize))
230  MIB.addImm(FrameSize);
231  else {
232  int Base = 2040; // should create template function like isUInt that
233  // returns largest possible n bit unsigned integer
234  int64_t Remainder = FrameSize - Base;
235  MIB.addImm(Base);
236  if (isInt<16>(-Remainder))
237  BuildAddiuSpImm(MBB, I, -Remainder);
238  else
239  adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);
240  }
241 }
242 
243 // Adjust SP by FrameSize bytes. Restore RA, S0, S1
244 void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
245  MachineBasicBlock &MBB,
247  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
248  MachineFunction *MF = MBB.getParent();
249  MachineFrameInfo &MFI = MF->getFrameInfo();
250  const BitVector Reserved = RI.getReservedRegs(*MF);
251  bool SaveS2 = Reserved[Mips::S2];
253  unsigned Opc = ((FrameSize <= 128) && !SaveS2)?
254  Mips::Restore16:Mips::RestoreX16;
255 
256  if (!isUInt<11>(FrameSize)) {
257  unsigned Base = 2040;
258  int64_t Remainder = FrameSize - Base;
259  FrameSize = Base; // should create template function like isUInt that
260  // returns largest possible n bit unsigned integer
261 
262  if (isInt<16>(Remainder))
263  BuildAddiuSpImm(MBB, I, Remainder);
264  else
265  adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);
266  }
267  MIB = BuildMI(MBB, I, DL, get(Opc));
268  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
270  if (SaveS2)
271  MIB.addReg(Mips::S2, RegState::Define);
272  MIB.addImm(FrameSize);
273 }
274 
275 // Adjust SP by Amount bytes where bytes can be up to 32bit number.
276 // This can only be called at times that we know that there is at least one free
277 // register.
278 // This is clearly safe at prologue and epilogue.
279 void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
280  MachineBasicBlock &MBB,
282  unsigned Reg1, unsigned Reg2) const {
283  DebugLoc DL;
284  //
285  // li reg1, constant
286  // move reg2, sp
287  // add reg1, reg1, reg2
288  // move sp, reg1
289  //
290  //
291  MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
292  MIB1.addImm(Amount).addImm(-1);
293  MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
294  MIB2.addReg(Mips::SP, RegState::Kill);
295  MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
296  MIB3.addReg(Reg1);
297  MIB3.addReg(Reg2, RegState::Kill);
298  MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
299  Mips::SP);
300  MIB4.addReg(Reg1, RegState::Kill);
301 }
302 
303 void Mips16InstrInfo::adjustStackPtrBigUnrestricted(
304  unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
305  MachineBasicBlock::iterator I) const {
306  llvm_unreachable("adjust stack pointer amount exceeded");
307 }
308 
309 /// Adjust SP by Amount bytes.
310 void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
311  MachineBasicBlock &MBB,
312  MachineBasicBlock::iterator I) const {
313  if (Amount == 0)
314  return;
315 
316  if (isInt<16>(Amount)) // need to change to addiu sp, ....and isInt<16>
317  BuildAddiuSpImm(MBB, I, Amount);
318  else
319  adjustStackPtrBigUnrestricted(SP, Amount, MBB, I);
320 }
321 
322 /// This function generates the sequence of instructions needed to get the
323 /// result of adding register REG and immediate IMM.
324 unsigned Mips16InstrInfo::loadImmediate(unsigned FrameReg, int64_t Imm,
325  MachineBasicBlock &MBB,
327  const DebugLoc &DL,
328  unsigned &NewImm) const {
329  //
330  // given original instruction is:
331  // Instr rx, T[offset] where offset is too big.
332  //
333  // lo = offset & 0xFFFF
334  // hi = ((offset >> 16) + (lo >> 15)) & 0xFFFF;
335  //
336  // let T = temporary register
337  // li T, hi
338  // shl T, 16
339  // add T, Rx, T
340  //
341  RegScavenger rs;
342  int32_t lo = Imm & 0xFFFF;
343  NewImm = lo;
344  int Reg =0;
345  int SpReg = 0;
346 
347  rs.enterBasicBlock(MBB);
348  rs.forward(II);
349  //
350  // We need to know which registers can be used, in the case where there
351  // are not enough free registers. We exclude all registers that
352  // are used in the instruction that we are helping.
353  // // Consider all allocatable registers in the register class initially
354  BitVector Candidates =
355  RI.getAllocatableSet
356  (*II->getParent()->getParent(), &Mips::CPU16RegsRegClass);
357  // Exclude all the registers being used by the instruction.
358  for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
359  MachineOperand &MO = II->getOperand(i);
360  if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
362  Candidates.reset(MO.getReg());
363  }
364 
365  // If the same register was used and defined in an instruction, then
366  // it will not be in the list of candidates.
367  //
368  // we need to analyze the instruction that we are helping.
369  // we need to know if it defines register x but register x is not
370  // present as an operand of the instruction. this tells
371  // whether the register is live before the instruction. if it's not
372  // then we don't need to save it in case there are no free registers.
373  int DefReg = 0;
374  for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
375  MachineOperand &MO = II->getOperand(i);
376  if (MO.isReg() && MO.isDef()) {
377  DefReg = MO.getReg();
378  break;
379  }
380  }
381 
382  BitVector Available = rs.getRegsAvailable(&Mips::CPU16RegsRegClass);
383  Available &= Candidates;
384  //
385  // we use T0 for the first register, if we need to save something away.
386  // we use T1 for the second register, if we need to save something away.
387  //
388  unsigned FirstRegSaved =0, SecondRegSaved=0;
389  unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0;
390 
391  Reg = Available.find_first();
392 
393  if (Reg == -1) {
394  Reg = Candidates.find_first();
395  Candidates.reset(Reg);
396  if (DefReg != Reg) {
397  FirstRegSaved = Reg;
398  FirstRegSavedTo = Mips::T0;
399  copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved, true);
400  }
401  }
402  else
403  Available.reset(Reg);
404  BuildMI(MBB, II, DL, get(Mips::LwConstant32), Reg).addImm(Imm).addImm(-1);
405  NewImm = 0;
406  if (FrameReg == Mips::SP) {
407  SpReg = Available.find_first();
408  if (SpReg == -1) {
409  SpReg = Candidates.find_first();
410  // Candidates.reset(SpReg); // not really needed
411  if (DefReg!= SpReg) {
412  SecondRegSaved = SpReg;
413  SecondRegSavedTo = Mips::T1;
414  }
415  if (SecondRegSaved)
416  copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true);
417  }
418  else
419  Available.reset(SpReg);
420  copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);
421  BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(SpReg, RegState::Kill)
422  .addReg(Reg);
423  }
424  else
425  BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(FrameReg)
426  .addReg(Reg, RegState::Kill);
427  if (FirstRegSaved || SecondRegSaved) {
428  II = std::next(II);
429  if (FirstRegSaved)
430  copyPhysReg(MBB, II, DL, FirstRegSaved, FirstRegSavedTo, true);
431  if (SecondRegSaved)
432  copyPhysReg(MBB, II, DL, SecondRegSaved, SecondRegSavedTo, true);
433  }
434  return Reg;
435 }
436 
437 unsigned Mips16InstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
438  return (Opc == Mips::BeqzRxImmX16 || Opc == Mips::BimmX16 ||
439  Opc == Mips::Bimm16 ||
440  Opc == Mips::Bteqz16 || Opc == Mips::Btnez16 ||
441  Opc == Mips::BeqzRxImm16 || Opc == Mips::BnezRxImm16 ||
442  Opc == Mips::BnezRxImmX16 || Opc == Mips::BteqzX16 ||
443  Opc == Mips::BteqzT8CmpX16 || Opc == Mips::BteqzT8CmpiX16 ||
444  Opc == Mips::BteqzT8SltX16 || Opc == Mips::BteqzT8SltuX16 ||
445  Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 ||
446  Opc == Mips::BtnezX16 || Opc == Mips::BtnezT8CmpX16 ||
447  Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 ||
448  Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 ||
449  Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0;
450 }
451 
452 void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
454  unsigned Opc) const {
455  BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
456 }
457 
458 const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {
459  if (validSpImm8(Imm))
460  return get(Mips::AddiuSpImm16);
461  else
462  return get(Mips::AddiuSpImmX16);
463 }
464 
466  (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const {
467  DebugLoc DL;
468  BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm);
469 }
470 
472  return new Mips16InstrInfo(STI);
473 }
474 
475 bool Mips16InstrInfo::validImmediate(unsigned Opcode, unsigned Reg,
476  int64_t Amount) {
477  switch (Opcode) {
478  case Mips::LbRxRyOffMemX16:
479  case Mips::LbuRxRyOffMemX16:
480  case Mips::LhRxRyOffMemX16:
481  case Mips::LhuRxRyOffMemX16:
482  case Mips::SbRxRyOffMemX16:
483  case Mips::ShRxRyOffMemX16:
484  case Mips::LwRxRyOffMemX16:
485  case Mips::SwRxRyOffMemX16:
486  case Mips::SwRxSpImmX16:
487  case Mips::LwRxSpImmX16:
488  return isInt<16>(Amount);
489  case Mips::AddiuRxRyOffMemX16:
490  if ((Reg == Mips::PC) || (Reg == Mips::SP))
491  return isInt<16>(Amount);
492  return isInt<15>(Amount);
493  }
494  llvm_unreachable("unexpected Opcode in validImmediate");
495 }
const MCInstrDesc & AddiuSpImm(int64_t Imm) const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:179
unsigned Reg
MachineMemOperand * GetMemOperand(MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:342
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
return AArch64::GPR64RegClass contains(Reg)
static void addSaveRestoreRegs(MachineInstrBuilder &MIB, const std::vector< CalleeSavedInfo > &CSI, unsigned Flags=0)
SI optimize exec mask operations pre RA
A description of a memory reference used in the backend.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Definition: BitVector.h:331
unsigned loadImmediate(unsigned FrameReg, int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, unsigned &NewImm) const
Emit a series of instructions to load an immediate.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
static bool validImmediate(unsigned Opcode, unsigned Reg, int64_t Amount)
void restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
void forward()
Move the internal MBB iterator and update register states.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:408
BitVector getRegsAvailable(const TargetRegisterClass *RC)
Return all available registers in the register class in Mask.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot...
BitVector getReservedRegs(const MachineFunction &MF) const override
void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
Adjust SP by Amount bytes.
unsigned getKillRegState(bool B)
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
This file declares the machine register scavenger class.
const MipsInstrInfo * createMips16InstrInfo(const MipsSubtarget &STI)
Create MipsInstrInfo objects.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
BitVector & reset()
Definition: BitVector.h:438
void BuildAddiuSpImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const
constexpr double e
Definition: MathExtras.h:57
self_iterator getIterator()
Definition: ilist_node.h:81
const MachineInstrBuilder & addFrameIndex(int Idx) const
bool expandPostRAPseudo(MachineInstr &MI) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source, const MachineOperand *&Destination) const override
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static bool validSpImm8(int offset)
const MipsRegisterInfo & getRegisterInfo() const override
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
The memory access writes data.
MachineOperand class - Representation of each machine instruction operand.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:256
The memory access reads data.
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool isMoveReg(QueryType Type=IgnoreBundle) const
Return true if this instruction is a register move.
Definition: MachineInstr.h:730
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Mips16InstrInfo(const MipsSubtarget &STI)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:69
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:219
IRTranslator LLVM IR MI
Register getReg() const
getReg - Returns the register number.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
unsigned getOppositeBranchOpc(unsigned Opc) const override
GetOppositeBranchOpc - Return the inverse of the specified opcode, e.g.
#define T1