LLVM  8.0.0svn
MipsInstrInfo.h
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1 //===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Mips implementation of the TargetInstrInfo class.
11 //
12 // FIXME: We need to override TargetInstrInfo::getInlineAsmLength method in
13 // order for MipsLongBranch pass to work correctly when the code has inline
14 // assembly. The returned value doesn't have to be the asm instruction's exact
15 // size in bytes; MipsLongBranch only expects it to be the correct upper bound.
16 //===----------------------------------------------------------------------===//
17 
18 #ifndef LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
19 #define LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
20 
22 #include "Mips.h"
23 #include "MipsRegisterInfo.h"
24 #include "llvm/ADT/ArrayRef.h"
29 #include <cstdint>
30 
31 #define GET_INSTRINFO_HEADER
32 #include "MipsGenInstrInfo.inc"
33 
34 namespace llvm {
35 
36 class MachineInstr;
37 class MachineOperand;
38 class MipsSubtarget;
39 class TargetRegisterClass;
40 class TargetRegisterInfo;
41 
43  virtual void anchor();
44 
45 protected:
47  unsigned UncondBrOpc;
48 
49 public:
50  enum BranchType {
51  BT_None, // Couldn't analyze branch.
52  BT_NoBranch, // No branches found.
53  BT_Uncond, // One unconditional branch.
54  BT_Cond, // One conditional branch.
55  BT_CondUncond, // A conditional branch followed by an unconditional branch.
56  BT_Indirect // One indirct branch.
57  };
58 
59  explicit MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc);
60 
61  static const MipsInstrInfo *create(MipsSubtarget &STI);
62 
63  /// Branch Analysis
65  MachineBasicBlock *&FBB,
67  bool AllowModify) const override;
68 
69  unsigned removeBranch(MachineBasicBlock &MBB,
70  int *BytesRemoved = nullptr) const override;
71 
74  const DebugLoc &DL,
75  int *BytesAdded = nullptr) const override;
76 
77  bool
79 
81  MachineBasicBlock *&FBB,
83  bool AllowModify,
84  SmallVectorImpl<MachineInstr *> &BranchInstrs) const;
85 
86  /// Determine the opcode of a non-delay slot form for a branch if one exists.
88 
89  /// Determine if the branch target is in range.
90  bool isBranchOffsetInRange(unsigned BranchOpc,
91  int64_t BrOffset) const override;
92 
93  /// Predicate to determine if an instruction can go in a forbidden slot.
94  bool SafeInForbiddenSlot(const MachineInstr &MI) const;
95 
96  /// Predicate to determine if an instruction has a forbidden slot.
97  bool HasForbiddenSlot(const MachineInstr &MI) const;
98 
99  /// Insert nop instruction when hazard condition is found
100  void insertNoop(MachineBasicBlock &MBB,
101  MachineBasicBlock::iterator MI) const override;
102 
103  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
104  /// such, whenever a client has an instance of instruction info, it should
105  /// always be able to get register info as well (through this method).
106  virtual const MipsRegisterInfo &getRegisterInfo() const = 0;
107 
108  virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0;
109 
110  /// Return the number of bytes of code the specified instruction may be.
111  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
112 
115  unsigned SrcReg, bool isKill, int FrameIndex,
116  const TargetRegisterClass *RC,
117  const TargetRegisterInfo *TRI) const override {
118  storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0);
119  }
120 
123  unsigned DestReg, int FrameIndex,
124  const TargetRegisterClass *RC,
125  const TargetRegisterInfo *TRI) const override {
126  loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0);
127  }
128 
129  virtual void storeRegToStack(MachineBasicBlock &MBB,
131  unsigned SrcReg, bool isKill, int FrameIndex,
132  const TargetRegisterClass *RC,
133  const TargetRegisterInfo *TRI,
134  int64_t Offset) const = 0;
135 
136  virtual void loadRegFromStack(MachineBasicBlock &MBB,
138  unsigned DestReg, int FrameIndex,
139  const TargetRegisterClass *RC,
140  const TargetRegisterInfo *TRI,
141  int64_t Offset) const = 0;
142 
143  virtual void adjustStackPtr(unsigned SP, int64_t Amount,
144  MachineBasicBlock &MBB,
145  MachineBasicBlock::iterator I) const = 0;
146 
147  /// Create an instruction which has the same operands and memory operands
148  /// as MI but has a new opcode.
149  MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc,
151 
152  bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
153  unsigned &SrcOpIdx2) const override;
154 
155  /// Perform target specific instruction verification.
156  bool verifyInstruction(const MachineInstr &MI,
157  StringRef &ErrInfo) const override;
158 
159  std::pair<unsigned, unsigned>
160  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
161 
164 
165 protected:
166  bool isZeroImm(const MachineOperand &op) const;
167 
169  MachineMemOperand::Flags Flags) const;
170 
171 private:
172  virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0;
173 
174  void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
175  MachineBasicBlock *&BB,
176  SmallVectorImpl<MachineOperand> &Cond) const;
177 
178  void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
179  const DebugLoc &DL, ArrayRef<MachineOperand> Cond) const;
180 };
181 
182 /// Create MipsInstrInfo objects.
185 
186 } // end namespace llvm
187 
188 #endif // LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
Return the number of bytes of code the specified instruction may be.
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
Determine if the branch target is in range.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Branch Analysis.
virtual void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const =0
bool SafeInForbiddenSlot(const MachineInstr &MI) const
Predicate to determine if an instruction can go in a forbidden slot.
MachineMemOperand * GetMemOperand(MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
virtual unsigned getOppositeBranchOpc(unsigned Opc) const =0
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
reverseBranchCondition - Return the inverse opcode of the specified Branch instruction.
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
Perform target specific instruction verification.
bool HasForbiddenSlot(const MachineInstr &MI) const
Predicate to determine if an instruction has a forbidden slot.
#define op(i)
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert nop instruction when hazard condition is found.
virtual const MipsRegisterInfo & getRegisterInfo() const =0
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
A description of a memory reference used in the backend.
MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc)
virtual void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const =0
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
const MipsSubtarget & Subtarget
Definition: MipsInstrInfo.h:46
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
const MipsInstrInfo * createMips16InstrInfo(const MipsSubtarget &STI)
Create MipsInstrInfo objects.
MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc, MachineBasicBlock::iterator I) const
Create an instruction which has the same operands and memory operands as MI but has a new opcode...
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const
Determine the opcode of a non-delay slot form for a branch if one exists.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isZeroImm(const MachineOperand &op) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
MachineOperand class - Representation of each machine instruction operand.
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Flags
Flags values. These may be or&#39;d together.
Representation of each machine instruction.
Definition: MachineInstr.h:64
#define I(x, y, z)
Definition: MD5.cpp:58
const MipsInstrInfo * createMipsSEInstrInfo(const MipsSubtarget &STI)
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
static const MipsInstrInfo * create(MipsSubtarget &STI)
virtual void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const =0
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override