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MipsInstrInfo.h
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1 //===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Mips implementation of the TargetInstrInfo class.
10 //
11 // FIXME: We need to override TargetInstrInfo::getInlineAsmLength method in
12 // order for MipsLongBranch pass to work correctly when the code has inline
13 // assembly. The returned value doesn't have to be the asm instruction's exact
14 // size in bytes; MipsLongBranch only expects it to be the correct upper bound.
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
18 #define LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
19 
21 #include "Mips.h"
22 #include "MipsRegisterInfo.h"
23 #include "llvm/ADT/ArrayRef.h"
28 #include <cstdint>
29 
30 #define GET_INSTRINFO_HEADER
31 #include "MipsGenInstrInfo.inc"
32 
33 namespace llvm {
34 
35 class MachineInstr;
36 class MachineOperand;
37 class MipsSubtarget;
38 class TargetRegisterClass;
39 class TargetRegisterInfo;
40 
42  virtual void anchor();
43 
44 protected:
46  unsigned UncondBrOpc;
47 
48 public:
49  enum BranchType {
50  BT_None, // Couldn't analyze branch.
51  BT_NoBranch, // No branches found.
52  BT_Uncond, // One unconditional branch.
53  BT_Cond, // One conditional branch.
54  BT_CondUncond, // A conditional branch followed by an unconditional branch.
55  BT_Indirect // One indirct branch.
56  };
57 
58  explicit MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc);
59 
60  static const MipsInstrInfo *create(MipsSubtarget &STI);
61 
62  /// Branch Analysis
64  MachineBasicBlock *&FBB,
66  bool AllowModify) const override;
67 
68  unsigned removeBranch(MachineBasicBlock &MBB,
69  int *BytesRemoved = nullptr) const override;
70 
73  const DebugLoc &DL,
74  int *BytesAdded = nullptr) const override;
75 
76  bool
78 
80  MachineBasicBlock *&FBB,
82  bool AllowModify,
83  SmallVectorImpl<MachineInstr *> &BranchInstrs) const;
84 
85  /// Determine the opcode of a non-delay slot form for a branch if one exists.
87 
88  /// Determine if the branch target is in range.
89  bool isBranchOffsetInRange(unsigned BranchOpc,
90  int64_t BrOffset) const override;
91 
92  /// Predicate to determine if an instruction can go in a forbidden slot.
93  bool SafeInForbiddenSlot(const MachineInstr &MI) const;
94 
95  /// Predicate to determine if an instruction has a forbidden slot.
96  bool HasForbiddenSlot(const MachineInstr &MI) const;
97 
98  /// Insert nop instruction when hazard condition is found
99  void insertNoop(MachineBasicBlock &MBB,
100  MachineBasicBlock::iterator MI) const override;
101 
102  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
103  /// such, whenever a client has an instance of instruction info, it should
104  /// always be able to get register info as well (through this method).
105  virtual const MipsRegisterInfo &getRegisterInfo() const = 0;
106 
107  virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0;
108 
109  /// Return the number of bytes of code the specified instruction may be.
110  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
111 
114  unsigned SrcReg, bool isKill, int FrameIndex,
115  const TargetRegisterClass *RC,
116  const TargetRegisterInfo *TRI) const override {
117  storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0);
118  }
119 
122  unsigned DestReg, int FrameIndex,
123  const TargetRegisterClass *RC,
124  const TargetRegisterInfo *TRI) const override {
125  loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0);
126  }
127 
128  virtual void storeRegToStack(MachineBasicBlock &MBB,
130  unsigned SrcReg, bool isKill, int FrameIndex,
131  const TargetRegisterClass *RC,
132  const TargetRegisterInfo *TRI,
133  int64_t Offset) const = 0;
134 
135  virtual void loadRegFromStack(MachineBasicBlock &MBB,
137  unsigned DestReg, int FrameIndex,
138  const TargetRegisterClass *RC,
139  const TargetRegisterInfo *TRI,
140  int64_t Offset) const = 0;
141 
142  virtual void adjustStackPtr(unsigned SP, int64_t Amount,
143  MachineBasicBlock &MBB,
144  MachineBasicBlock::iterator I) const = 0;
145 
146  /// Create an instruction which has the same operands and memory operands
147  /// as MI but has a new opcode.
148  MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc,
150 
151  bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
152  unsigned &SrcOpIdx2) const override;
153 
154  /// Perform target specific instruction verification.
155  bool verifyInstruction(const MachineInstr &MI,
156  StringRef &ErrInfo) const override;
157 
158  std::pair<unsigned, unsigned>
159  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
160 
163 
164 protected:
165  bool isZeroImm(const MachineOperand &op) const;
166 
168  MachineMemOperand::Flags Flags) const;
169 
170 private:
171  virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0;
172 
173  void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
174  MachineBasicBlock *&BB,
175  SmallVectorImpl<MachineOperand> &Cond) const;
176 
177  void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
178  const DebugLoc &DL, ArrayRef<MachineOperand> Cond) const;
179 };
180 
181 /// Create MipsInstrInfo objects.
184 
185 } // end namespace llvm
186 
187 #endif // LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
Return the number of bytes of code the specified instruction may be.
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
Determine if the branch target is in range.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Branch Analysis.
virtual void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const =0
bool SafeInForbiddenSlot(const MachineInstr &MI) const
Predicate to determine if an instruction can go in a forbidden slot.
MachineMemOperand * GetMemOperand(MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
virtual unsigned getOppositeBranchOpc(unsigned Opc) const =0
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
reverseBranchCondition - Return the inverse opcode of the specified Branch instruction.
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
Perform target specific instruction verification.
bool HasForbiddenSlot(const MachineInstr &MI) const
Predicate to determine if an instruction has a forbidden slot.
#define op(i)
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert nop instruction when hazard condition is found.
virtual const MipsRegisterInfo & getRegisterInfo() const =0
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
A description of a memory reference used in the backend.
MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc)
virtual void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const =0
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
const MipsSubtarget & Subtarget
Definition: MipsInstrInfo.h:45
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
const MipsInstrInfo * createMips16InstrInfo(const MipsSubtarget &STI)
Create MipsInstrInfo objects.
MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc, MachineBasicBlock::iterator I) const
Create an instruction which has the same operands and memory operands as MI but has a new opcode...
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const
Determine the opcode of a non-delay slot form for a branch if one exists.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isZeroImm(const MachineOperand &op) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
MachineOperand class - Representation of each machine instruction operand.
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Flags
Flags values. These may be or&#39;d together.
Representation of each machine instruction.
Definition: MachineInstr.h:64
#define I(x, y, z)
Definition: MD5.cpp:58
const MipsInstrInfo * createMipsSEInstrInfo(const MipsSubtarget &STI)
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
static const MipsInstrInfo * create(MipsSubtarget &STI)
virtual void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const =0
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override