LLVM  6.0.0svn
MipsSubtarget.h
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1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the Mips specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
15 #define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
16 
18 #include "MipsFrameLowering.h"
19 #include "MipsISelLowering.h"
20 #include "MipsInstrInfo.h"
22 #include "llvm/IR/DataLayout.h"
26 #include <string>
27 
28 #define GET_SUBTARGETINFO_HEADER
29 #include "MipsGenSubtargetInfo.inc"
30 
31 namespace llvm {
32 class StringRef;
33 
34 class MipsTargetMachine;
35 
37  virtual void anchor();
38 
39  enum MipsArchEnum {
40  MipsDefault,
41  Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,
42  Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
43  };
44 
45  enum class CPU { P5600 };
46 
47  // Mips architecture version
48  MipsArchEnum MipsArchVersion;
49 
50  // Processor implementation (unused but required to exist by
51  // tablegen-erated code).
52  CPU ProcImpl;
53 
54  // IsLittle - The target is Little Endian
55  bool IsLittle;
56 
57  // IsSoftFloat - The target does not support any floating point instructions.
58  bool IsSoftFloat;
59 
60  // IsSingleFloat - The target only supports single precision float
61  // point operations. This enable the target to use all 32 32-bit
62  // floating point registers instead of only using even ones.
63  bool IsSingleFloat;
64 
65  // IsFPXX - MIPS O32 modeless ABI.
66  bool IsFPXX;
67 
68  // NoABICalls - Disable SVR4-style position-independent code.
69  bool NoABICalls;
70 
71  // IsFP64bit - The target processor has 64-bit floating point registers.
72  bool IsFP64bit;
73 
74  /// Are odd single-precision registers permitted?
75  /// This corresponds to -modd-spreg and -mno-odd-spreg
76  bool UseOddSPReg;
77 
78  // IsNan2008 - IEEE 754-2008 NaN encoding.
79  bool IsNaN2008bit;
80 
81  // IsGP64bit - General-purpose registers are 64 bits wide
82  bool IsGP64bit;
83 
84  // IsPTR64bit - Pointers are 64 bit wide
85  bool IsPTR64bit;
86 
87  // HasVFPU - Processor has a vector floating point unit.
88  bool HasVFPU;
89 
90  // CPU supports cnMIPS (Cavium Networks Octeon CPU).
91  bool HasCnMips;
92 
93  // isLinux - Target system is Linux. Is false we consider ELFOS for now.
94  bool IsLinux;
95 
96  // UseSmallSection - Small section is used.
97  bool UseSmallSection;
98 
99  /// Features related to the presence of specific instructions.
100 
101  // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
102  bool HasMips3_32;
103 
104  // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
105  bool HasMips3_32r2;
106 
107  // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
108  bool HasMips4_32;
109 
110  // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
111  bool HasMips4_32r2;
112 
113  // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
114  bool HasMips5_32r2;
115 
116  // InMips16 -- can process Mips16 instructions
117  bool InMips16Mode;
118 
119  // Mips16 hard float
120  bool InMips16HardFloat;
121 
122  // InMicroMips -- can process MicroMips instructions
123  bool InMicroMipsMode;
124 
125  // HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE.
126  bool HasDSP, HasDSPR2, HasDSPR3;
127 
128  // Allow mixed Mips16 and Mips32 in one source file
129  bool AllowMixed16_32;
130 
131  // Optimize for space by compiling all functions as Mips 16 unless
132  // it needs floating point. Functions needing floating point are
133  // compiled as Mips32
134  bool Os16;
135 
136  // HasMSA -- supports MSA ASE.
137  bool HasMSA;
138 
139  // UseTCCInDIV -- Enables the use of trapping in the assembler.
140  bool UseTCCInDIV;
141 
142  // Sym32 -- On Mips64 symbols are 32 bits.
143  bool HasSym32;
144 
145  // HasEVA -- supports EVA ASE.
146  bool HasEVA;
147 
148  // nomadd4 - disables generation of 4-operand madd.s, madd.d and
149  // related instructions.
150  bool DisableMadd4;
151 
152  // HasMT -- support MT ASE.
153  bool HasMT;
154 
155  // Disable use of the `jal` instruction.
156  bool UseLongCalls = false;
157 
158  InstrItineraryData InstrItins;
159 
160  // We can override the determination of whether we are in mips16 mode
161  // as from the command line
162  enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
163 
164  const MipsTargetMachine &TM;
165 
166  Triple TargetTriple;
167 
168  const SelectionDAGTargetInfo TSInfo;
169  std::unique_ptr<const MipsInstrInfo> InstrInfo;
170  std::unique_ptr<const MipsFrameLowering> FrameLowering;
171  std::unique_ptr<const MipsTargetLowering> TLInfo;
172 
173 public:
174  bool isPositionIndependent() const;
175  /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
176  bool enablePostRAScheduler() const override;
177  void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
179 
180  bool isABI_N64() const;
181  bool isABI_N32() const;
182  bool isABI_O32() const;
183  const MipsABIInfo &getABI() const;
184  bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
185 
186  /// This constructor initializes the data members to match that
187  /// of the specified triple.
188  MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little,
189  const MipsTargetMachine &TM);
190 
191  /// ParseSubtargetFeatures - Parses features string setting specified
192  /// subtarget options. Definition of function is auto generated by tblgen.
194 
195  bool hasMips1() const { return MipsArchVersion >= Mips1; }
196  bool hasMips2() const { return MipsArchVersion >= Mips2; }
197  bool hasMips3() const { return MipsArchVersion >= Mips3; }
198  bool hasMips4() const { return MipsArchVersion >= Mips4; }
199  bool hasMips5() const { return MipsArchVersion >= Mips5; }
200  bool hasMips4_32() const { return HasMips4_32; }
201  bool hasMips4_32r2() const { return HasMips4_32r2; }
202  bool hasMips32() const {
203  return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) ||
204  hasMips64();
205  }
206  bool hasMips32r2() const {
207  return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) ||
208  hasMips64r2();
209  }
210  bool hasMips32r3() const {
211  return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) ||
212  hasMips64r2();
213  }
214  bool hasMips32r5() const {
215  return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
216  hasMips64r5();
217  }
218  bool hasMips32r6() const {
219  return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||
220  hasMips64r6();
221  }
222  bool hasMips64() const { return MipsArchVersion >= Mips64; }
223  bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; }
224  bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; }
225  bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; }
226  bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; }
227 
228  bool hasCnMips() const { return HasCnMips; }
229 
230  bool isLittle() const { return IsLittle; }
231  bool isABICalls() const { return !NoABICalls; }
232  bool isFPXX() const { return IsFPXX; }
233  bool isFP64bit() const { return IsFP64bit; }
234  bool useOddSPReg() const { return UseOddSPReg; }
235  bool noOddSPReg() const { return !UseOddSPReg; }
236  bool isNaN2008() const { return IsNaN2008bit; }
237  bool isGP64bit() const { return IsGP64bit; }
238  bool isGP32bit() const { return !IsGP64bit; }
239  unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
240  bool isPTR64bit() const { return IsPTR64bit; }
241  bool isPTR32bit() const { return !IsPTR64bit; }
242  bool hasSym32() const {
243  return (HasSym32 && isABI_N64()) || isABI_N32() || isABI_O32();
244  }
245  bool isSingleFloat() const { return IsSingleFloat; }
246  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
247  bool hasVFPU() const { return HasVFPU; }
248  bool inMips16Mode() const { return InMips16Mode; }
249  bool inMips16ModeDefault() const {
250  return InMips16Mode;
251  }
252  // Hard float for mips16 means essentially to compile as soft float
253  // but to use a runtime library for soft float that is written with
254  // native mips32 floating point instructions (those runtime routines
255  // run in mips32 hard float mode).
256  bool inMips16HardFloat() const {
257  return inMips16Mode() && InMips16HardFloat;
258  }
259  bool inMicroMipsMode() const { return InMicroMipsMode; }
260  bool inMicroMips32r6Mode() const { return InMicroMipsMode && hasMips32r6(); }
261  bool inMicroMips64r6Mode() const { return InMicroMipsMode && hasMips64r6(); }
262  bool hasDSP() const { return HasDSP; }
263  bool hasDSPR2() const { return HasDSPR2; }
264  bool hasDSPR3() const { return HasDSPR3; }
265  bool hasMSA() const { return HasMSA; }
266  bool disableMadd4() const { return DisableMadd4; }
267  bool hasEVA() const { return HasEVA; }
268  bool hasMT() const { return HasMT; }
269  bool useSmallSection() const { return UseSmallSection; }
270 
271  bool hasStandardEncoding() const { return !inMips16Mode(); }
272 
273  bool useSoftFloat() const { return IsSoftFloat; }
274 
275  bool useLongCalls() const { return UseLongCalls; }
276 
277  bool enableLongBranchPass() const {
278  return hasStandardEncoding() || allowMixed16_32();
279  }
280 
281  /// Features related to the presence of specific instructions.
282  bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
283  bool hasMTHC1() const { return hasMips32r2(); }
284 
285  bool allowMixed16_32() const { return inMips16ModeDefault() |
286  AllowMixed16_32; }
287 
288  bool os16() const { return Os16; }
289 
290  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
291 
292  bool isXRaySupported() const override { return true; }
293 
294  // for now constant islands are on for the whole compilation unit but we only
295  // really use them if in addition we are in mips16 mode
296  static bool useConstantIslands();
297 
298  unsigned stackAlignment() const { return hasMips64() ? 16 : 8; }
299 
300  // Grab relocation model
302 
304  const TargetMachine &TM);
305 
306  /// Does the system support unaligned memory access.
307  ///
308  /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
309  /// specify which component of the system provides it. Hardware, software, and
310  /// hybrid implementations are all valid.
311  bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
312 
313  // Set helper classes
314  void setHelperClassesMips16();
315  void setHelperClassesMipsSE();
316 
317  const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
318  return &TSInfo;
319  }
320  const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
321  const TargetFrameLowering *getFrameLowering() const override {
322  return FrameLowering.get();
323  }
324  const MipsRegisterInfo *getRegisterInfo() const override {
325  return &InstrInfo->getRegisterInfo();
326  }
327  const MipsTargetLowering *getTargetLowering() const override {
328  return TLInfo.get();
329  }
330  const InstrItineraryData *getInstrItineraryData() const override {
331  return &InstrItins;
332  }
333 };
334 } // End llvm namespace
335 
336 #endif
bool isABI_FPXX() const
bool isABICalls() const
bool inMips16HardFloat() const
bool isPTR64bit() const
bool hasVFPU() const
bool inMips16ModeDefault() const
bool hasMTHC1() const
bool hasMips3() const
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool inMips16Mode() const
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:572
bool hasMips2() const
void setHelperClassesMips16()
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:551
const MipsInstrInfo * getInstrInfo() const override
const InstrItineraryData * getInstrItineraryData() const override
bool isABI_O32() const
bool hasMips4_32() const
bool hasExtractInsert() const
Features related to the presence of specific instructions.
bool enableLongBranchPass() const
bool isFPXX() const
bool hasMips64() const
bool hasDSPR3() const
bool hasDSPR2() const
bool hasSym32() const
bool inMicroMipsMode() const
bool isXRaySupported() const override
bool hasStandardEncoding() const
bool hasMips4_32r2() const
bool isGP64bit() const
bool hasMips32r6() const
bool hasMips1() const
bool hasMips64r3() const
Itinerary data supplied by a subtarget to be used by a target.
bool useSmallSection() const
bool isPTR32bit() const
bool hasMips32r5() const
bool isTargetNaCl() const
const TargetFrameLowering * getFrameLowering() const override
unsigned getGPRSizeInBytes() const
bool useLongCalls() const
bool hasMips64r2() const
bool hasMips32r3() const
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
bool isSingleFloat() const
bool hasMips64r6() const
const MipsABIInfo & getABI() const
bool isABI_N32() const
bool isNaN2008() const
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool hasMips64r5() const
bool hasMT() const
static bool useConstantIslands()
MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little, const MipsTargetMachine &TM)
This constructor initializes the data members to match that of the specified triple.
unsigned stackAlignment() const
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
bool hasEVA() const
bool isLittle() const
const MipsRegisterInfo * getRegisterInfo() const override
bool isPositionIndependent() const
bool enablePostRAScheduler() const override
This overrides the PostRAScheduler bit in the SchedModel for each CPU.
bool hasCnMips() const
void setHelperClassesMipsSE()
Information about stack frame layout on the target.
bool hasMips5() const
bool hasDSP() const
const MipsTargetLowering * getTargetLowering() const override
bool isTargetELF() const
bool hasMips4() const
bool inMicroMips64r6Mode() const
bool noOddSPReg() const
bool hasMips32() const
bool useOddSPReg() const
bool hasMips32r2() const
bool isABI_N64() const
bool allowMixed16_32() const
CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override
Reloc::Model getRelocationModel() const
bool isGP32bit() const
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
MipsSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS, const TargetMachine &TM)
bool useSoftFloat() const
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:56
bool inMicroMips32r6Mode() const
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
bool systemSupportsUnalignedAccess() const
Does the system support unaligned memory access.
bool isFP64bit() const
bool disableMadd4() const
bool hasMSA() const