LLVM  9.0.0svn
MipsSubtarget.h
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1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the Mips specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
14 #define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
15 
17 #include "MipsFrameLowering.h"
18 #include "MipsISelLowering.h"
19 #include "MipsInstrInfo.h"
26 #include "llvm/IR/DataLayout.h"
29 #include <string>
30 
31 #define GET_SUBTARGETINFO_HEADER
32 #include "MipsGenSubtargetInfo.inc"
33 
34 namespace llvm {
35 class StringRef;
36 
37 class MipsTargetMachine;
38 
40  virtual void anchor();
41 
42  enum MipsArchEnum {
43  MipsDefault,
44  Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,
45  Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
46  };
47 
48  enum class CPU { P5600 };
49 
50  // Used to avoid printing dsp warnings multiple times.
51  static bool DspWarningPrinted;
52 
53  // Used to avoid printing msa warnings multiple times.
54  static bool MSAWarningPrinted;
55 
56  // Used to avoid printing crc warnings multiple times.
57  static bool CRCWarningPrinted;
58 
59  // Used to avoid printing ginv warnings multiple times.
60  static bool GINVWarningPrinted;
61 
62  // Used to avoid printing virt warnings multiple times.
63  static bool VirtWarningPrinted;
64 
65  // Mips architecture version
66  MipsArchEnum MipsArchVersion;
67 
68  // Processor implementation (unused but required to exist by
69  // tablegen-erated code).
70  CPU ProcImpl;
71 
72  // IsLittle - The target is Little Endian
73  bool IsLittle;
74 
75  // IsSoftFloat - The target does not support any floating point instructions.
76  bool IsSoftFloat;
77 
78  // IsSingleFloat - The target only supports single precision float
79  // point operations. This enable the target to use all 32 32-bit
80  // floating point registers instead of only using even ones.
81  bool IsSingleFloat;
82 
83  // IsFPXX - MIPS O32 modeless ABI.
84  bool IsFPXX;
85 
86  // NoABICalls - Disable SVR4-style position-independent code.
87  bool NoABICalls;
88 
89  // IsFP64bit - The target processor has 64-bit floating point registers.
90  bool IsFP64bit;
91 
92  /// Are odd single-precision registers permitted?
93  /// This corresponds to -modd-spreg and -mno-odd-spreg
94  bool UseOddSPReg;
95 
96  // IsNan2008 - IEEE 754-2008 NaN encoding.
97  bool IsNaN2008bit;
98 
99  // IsGP64bit - General-purpose registers are 64 bits wide
100  bool IsGP64bit;
101 
102  // IsPTR64bit - Pointers are 64 bit wide
103  bool IsPTR64bit;
104 
105  // HasVFPU - Processor has a vector floating point unit.
106  bool HasVFPU;
107 
108  // CPU supports cnMIPS (Cavium Networks Octeon CPU).
109  bool HasCnMips;
110 
111  // isLinux - Target system is Linux. Is false we consider ELFOS for now.
112  bool IsLinux;
113 
114  // UseSmallSection - Small section is used.
115  bool UseSmallSection;
116 
117  /// Features related to the presence of specific instructions.
118 
119  // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
120  bool HasMips3_32;
121 
122  // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
123  bool HasMips3_32r2;
124 
125  // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
126  bool HasMips4_32;
127 
128  // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
129  bool HasMips4_32r2;
130 
131  // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
132  bool HasMips5_32r2;
133 
134  // InMips16 -- can process Mips16 instructions
135  bool InMips16Mode;
136 
137  // Mips16 hard float
138  bool InMips16HardFloat;
139 
140  // InMicroMips -- can process MicroMips instructions
141  bool InMicroMipsMode;
142 
143  // HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE.
144  bool HasDSP, HasDSPR2, HasDSPR3;
145 
146  // Allow mixed Mips16 and Mips32 in one source file
147  bool AllowMixed16_32;
148 
149  // Optimize for space by compiling all functions as Mips 16 unless
150  // it needs floating point. Functions needing floating point are
151  // compiled as Mips32
152  bool Os16;
153 
154  // HasMSA -- supports MSA ASE.
155  bool HasMSA;
156 
157  // UseTCCInDIV -- Enables the use of trapping in the assembler.
158  bool UseTCCInDIV;
159 
160  // Sym32 -- On Mips64 symbols are 32 bits.
161  bool HasSym32;
162 
163  // HasEVA -- supports EVA ASE.
164  bool HasEVA;
165 
166  // nomadd4 - disables generation of 4-operand madd.s, madd.d and
167  // related instructions.
168  bool DisableMadd4;
169 
170  // HasMT -- support MT ASE.
171  bool HasMT;
172 
173  // HasCRC -- supports R6 CRC ASE
174  bool HasCRC;
175 
176  // HasVirt -- supports Virtualization ASE
177  bool HasVirt;
178 
179  // HasGINV -- supports R6 Global INValidate ASE
180  bool HasGINV;
181 
182  // Use hazard variants of the jump register instructions for indirect
183  // function calls and jump tables.
184  bool UseIndirectJumpsHazard;
185 
186  // Disable use of the `jal` instruction.
187  bool UseLongCalls = false;
188 
189  /// The minimum alignment known to hold of the stack frame on
190  /// entry to the function and which must be maintained by every function.
191  unsigned stackAlignment;
192 
193  /// The overridden stack alignment.
194  unsigned StackAlignOverride;
195 
196  InstrItineraryData InstrItins;
197 
198  // We can override the determination of whether we are in mips16 mode
199  // as from the command line
200  enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
201 
202  const MipsTargetMachine &TM;
203 
204  Triple TargetTriple;
205 
206  const SelectionDAGTargetInfo TSInfo;
207  std::unique_ptr<const MipsInstrInfo> InstrInfo;
208  std::unique_ptr<const MipsFrameLowering> FrameLowering;
209  std::unique_ptr<const MipsTargetLowering> TLInfo;
210 
211 public:
212  bool isPositionIndependent() const;
213  /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
214  bool enablePostRAScheduler() const override;
215  void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
217 
218  bool isABI_N64() const;
219  bool isABI_N32() const;
220  bool isABI_O32() const;
221  const MipsABIInfo &getABI() const;
222  bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
223 
224  /// This constructor initializes the data members to match that
225  /// of the specified triple.
226  MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little,
227  const MipsTargetMachine &TM, unsigned StackAlignOverride);
228 
229  /// ParseSubtargetFeatures - Parses features string setting specified
230  /// subtarget options. Definition of function is auto generated by tblgen.
232 
233  bool hasMips1() const { return MipsArchVersion >= Mips1; }
234  bool hasMips2() const { return MipsArchVersion >= Mips2; }
235  bool hasMips3() const { return MipsArchVersion >= Mips3; }
236  bool hasMips4() const { return MipsArchVersion >= Mips4; }
237  bool hasMips5() const { return MipsArchVersion >= Mips5; }
238  bool hasMips4_32() const { return HasMips4_32; }
239  bool hasMips4_32r2() const { return HasMips4_32r2; }
240  bool hasMips32() const {
241  return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) ||
242  hasMips64();
243  }
244  bool hasMips32r2() const {
245  return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) ||
246  hasMips64r2();
247  }
248  bool hasMips32r3() const {
249  return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) ||
250  hasMips64r2();
251  }
252  bool hasMips32r5() const {
253  return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
254  hasMips64r5();
255  }
256  bool hasMips32r6() const {
257  return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||
258  hasMips64r6();
259  }
260  bool hasMips64() const { return MipsArchVersion >= Mips64; }
261  bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; }
262  bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; }
263  bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; }
264  bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; }
265 
266  bool hasCnMips() const { return HasCnMips; }
267 
268  bool isLittle() const { return IsLittle; }
269  bool isABICalls() const { return !NoABICalls; }
270  bool isFPXX() const { return IsFPXX; }
271  bool isFP64bit() const { return IsFP64bit; }
272  bool useOddSPReg() const { return UseOddSPReg; }
273  bool noOddSPReg() const { return !UseOddSPReg; }
274  bool isNaN2008() const { return IsNaN2008bit; }
275  bool isGP64bit() const { return IsGP64bit; }
276  bool isGP32bit() const { return !IsGP64bit; }
277  unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
278  bool isPTR64bit() const { return IsPTR64bit; }
279  bool isPTR32bit() const { return !IsPTR64bit; }
280  bool hasSym32() const {
281  return (HasSym32 && isABI_N64()) || isABI_N32() || isABI_O32();
282  }
283  bool isSingleFloat() const { return IsSingleFloat; }
284  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
285  bool hasVFPU() const { return HasVFPU; }
286  bool inMips16Mode() const { return InMips16Mode; }
287  bool inMips16ModeDefault() const {
288  return InMips16Mode;
289  }
290  // Hard float for mips16 means essentially to compile as soft float
291  // but to use a runtime library for soft float that is written with
292  // native mips32 floating point instructions (those runtime routines
293  // run in mips32 hard float mode).
294  bool inMips16HardFloat() const {
295  return inMips16Mode() && InMips16HardFloat;
296  }
297  bool inMicroMipsMode() const { return InMicroMipsMode && !InMips16Mode; }
298  bool inMicroMips32r6Mode() const {
299  return inMicroMipsMode() && hasMips32r6();
300  }
301  bool hasDSP() const { return HasDSP; }
302  bool hasDSPR2() const { return HasDSPR2; }
303  bool hasDSPR3() const { return HasDSPR3; }
304  bool hasMSA() const { return HasMSA; }
305  bool disableMadd4() const { return DisableMadd4; }
306  bool hasEVA() const { return HasEVA; }
307  bool hasMT() const { return HasMT; }
308  bool hasCRC() const { return HasCRC; }
309  bool hasVirt() const { return HasVirt; }
310  bool hasGINV() const { return HasGINV; }
311  bool useIndirectJumpsHazard() const {
312  return UseIndirectJumpsHazard && hasMips32r2();
313  }
314  bool useSmallSection() const { return UseSmallSection; }
315 
316  bool hasStandardEncoding() const { return !InMips16Mode && !InMicroMipsMode; }
317 
318  bool useSoftFloat() const { return IsSoftFloat; }
319 
320  bool useLongCalls() const { return UseLongCalls; }
321 
322  bool enableLongBranchPass() const {
324  }
325 
326  /// Features related to the presence of specific instructions.
327  bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
328  bool hasMTHC1() const { return hasMips32r2(); }
329 
330  bool allowMixed16_32() const { return inMips16ModeDefault() |
331  AllowMixed16_32; }
332 
333  bool os16() const { return Os16; }
334 
335  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
336 
337  bool isXRaySupported() const override { return true; }
338 
339  // for now constant islands are on for the whole compilation unit but we only
340  // really use them if in addition we are in mips16 mode
341  static bool useConstantIslands();
342 
343  unsigned getStackAlignment() const { return stackAlignment; }
344 
345  // Grab relocation model
347 
349  const TargetMachine &TM);
350 
351  /// Does the system support unaligned memory access.
352  ///
353  /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
354  /// specify which component of the system provides it. Hardware, software, and
355  /// hybrid implementations are all valid.
356  bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
357 
358  // Set helper classes
359  void setHelperClassesMips16();
360  void setHelperClassesMipsSE();
361 
362  const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
363  return &TSInfo;
364  }
365  const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
366  const TargetFrameLowering *getFrameLowering() const override {
367  return FrameLowering.get();
368  }
369  const MipsRegisterInfo *getRegisterInfo() const override {
370  return &InstrInfo->getRegisterInfo();
371  }
372  const MipsTargetLowering *getTargetLowering() const override {
373  return TLInfo.get();
374  }
375  const InstrItineraryData *getInstrItineraryData() const override {
376  return &InstrItins;
377  }
378 
379 protected:
380  // GlobalISel related APIs.
381  std::unique_ptr<CallLowering> CallLoweringInfo;
382  std::unique_ptr<LegalizerInfo> Legalizer;
383  std::unique_ptr<RegisterBankInfo> RegBankInfo;
384  std::unique_ptr<InstructionSelector> InstSelector;
385 
386 public:
387  const CallLowering *getCallLowering() const override;
388  const LegalizerInfo *getLegalizerInfo() const override;
389  const RegisterBankInfo *getRegBankInfo() const override;
390  const InstructionSelector *getInstructionSelector() const override;
391 };
392 } // End llvm namespace
393 
394 #endif
const RegisterBankInfo * getRegBankInfo() const override
bool isABI_FPXX() const
bool isABICalls() const
bool inMips16HardFloat() const
bool isPTR64bit() const
bool hasVFPU() const
bool inMips16ModeDefault() const
std::unique_ptr< InstructionSelector > InstSelector
bool hasMTHC1() const
bool hasMips3() const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool inMips16Mode() const
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:603
MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little, const MipsTargetMachine &TM, unsigned StackAlignOverride)
This constructor initializes the data members to match that of the specified triple.
bool hasMips2() const
void setHelperClassesMips16()
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:571
const MipsInstrInfo * getInstrInfo() const override
const InstrItineraryData * getInstrItineraryData() const override
bool isABI_O32() const
bool hasMips4_32() const
bool hasExtractInsert() const
Features related to the presence of specific instructions.
bool enableLongBranchPass() const
const InstructionSelector * getInstructionSelector() const override
bool isFPXX() const
bool hasMips64() const
bool hasDSPR3() const
bool hasDSPR2() const
Holds all the information related to register banks.
bool hasSym32() const
bool inMicroMipsMode() const
bool isXRaySupported() const override
bool hasStandardEncoding() const
bool useIndirectJumpsHazard() const
bool hasMips4_32r2() const
bool isGP64bit() const
bool hasMips32r6() const
bool hasMips1() const
bool hasMips64r3() const
Itinerary data supplied by a subtarget to be used by a target.
bool useSmallSection() const
bool isPTR32bit() const
bool hasMips32r5() const
bool isTargetNaCl() const
const TargetFrameLowering * getFrameLowering() const override
unsigned getGPRSizeInBytes() const
unsigned getStackAlignment() const
bool hasCRC() const
const LegalizerInfo * getLegalizerInfo() const override
bool useLongCalls() const
std::unique_ptr< RegisterBankInfo > RegBankInfo
bool hasMips64r2() const
bool hasMips32r3() const
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
bool isSingleFloat() const
bool hasMips64r6() const
const MipsABIInfo & getABI() const
bool isABI_N32() const
bool isNaN2008() const
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
std::unique_ptr< CallLowering > CallLoweringInfo
bool hasMips64r5() const
bool hasMT() const
static bool useConstantIslands()
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
bool hasEVA() const
bool isLittle() const
const MipsRegisterInfo * getRegisterInfo() const override
bool isPositionIndependent() const
bool enablePostRAScheduler() const override
This overrides the PostRAScheduler bit in the SchedModel for each CPU.
bool hasCnMips() const
void setHelperClassesMipsSE()
Information about stack frame layout on the target.
bool hasMips5() const
bool hasDSP() const
const CallLowering * getCallLowering() const override
const MipsTargetLowering * getTargetLowering() const override
bool hasVirt() const
bool isTargetELF() const
bool hasMips4() const
Provides the logic to select generic machine instructions.
bool hasGINV() const
bool noOddSPReg() const
bool hasMips32() const
bool useOddSPReg() const
bool hasMips32r2() const
bool isABI_N64() const
bool allowMixed16_32() const
CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override
Reloc::Model getRelocationModel() const
bool isGP32bit() const
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
This file describes how to lower LLVM calls to machine code calls.
MipsSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS, const TargetMachine &TM)
bool useSoftFloat() const
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:58
bool inMicroMips32r6Mode() const
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
bool systemSupportsUnalignedAccess() const
Does the system support unaligned memory access.
bool isFP64bit() const
bool disableMadd4() const
bool hasMSA() const
std::unique_ptr< LegalizerInfo > Legalizer