LLVM  7.0.0svn
MipsSubtarget.h
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1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the Mips specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
15 #define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
16 
18 #include "MipsFrameLowering.h"
19 #include "MipsISelLowering.h"
20 #include "MipsInstrInfo.h"
23 #include "llvm/IR/DataLayout.h"
26 #include <string>
27 
28 #define GET_SUBTARGETINFO_HEADER
29 #include "MipsGenSubtargetInfo.inc"
30 
31 namespace llvm {
32 class StringRef;
33 
34 class MipsTargetMachine;
35 
37  virtual void anchor();
38 
39  enum MipsArchEnum {
40  MipsDefault,
41  Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,
42  Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
43  };
44 
45  enum class CPU { P5600 };
46 
47  // Used to avoid printing dsp warnings multiple times.
48  static bool DspWarningPrinted;
49 
50  // Used to avoid printing msa warnings multiple times.
51  static bool MSAWarningPrinted;
52 
53  // Mips architecture version
54  MipsArchEnum MipsArchVersion;
55 
56  // Processor implementation (unused but required to exist by
57  // tablegen-erated code).
58  CPU ProcImpl;
59 
60  // IsLittle - The target is Little Endian
61  bool IsLittle;
62 
63  // IsSoftFloat - The target does not support any floating point instructions.
64  bool IsSoftFloat;
65 
66  // IsSingleFloat - The target only supports single precision float
67  // point operations. This enable the target to use all 32 32-bit
68  // floating point registers instead of only using even ones.
69  bool IsSingleFloat;
70 
71  // IsFPXX - MIPS O32 modeless ABI.
72  bool IsFPXX;
73 
74  // NoABICalls - Disable SVR4-style position-independent code.
75  bool NoABICalls;
76 
77  // IsFP64bit - The target processor has 64-bit floating point registers.
78  bool IsFP64bit;
79 
80  /// Are odd single-precision registers permitted?
81  /// This corresponds to -modd-spreg and -mno-odd-spreg
82  bool UseOddSPReg;
83 
84  // IsNan2008 - IEEE 754-2008 NaN encoding.
85  bool IsNaN2008bit;
86 
87  // IsGP64bit - General-purpose registers are 64 bits wide
88  bool IsGP64bit;
89 
90  // IsPTR64bit - Pointers are 64 bit wide
91  bool IsPTR64bit;
92 
93  // HasVFPU - Processor has a vector floating point unit.
94  bool HasVFPU;
95 
96  // CPU supports cnMIPS (Cavium Networks Octeon CPU).
97  bool HasCnMips;
98 
99  // isLinux - Target system is Linux. Is false we consider ELFOS for now.
100  bool IsLinux;
101 
102  // UseSmallSection - Small section is used.
103  bool UseSmallSection;
104 
105  /// Features related to the presence of specific instructions.
106 
107  // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
108  bool HasMips3_32;
109 
110  // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
111  bool HasMips3_32r2;
112 
113  // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
114  bool HasMips4_32;
115 
116  // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
117  bool HasMips4_32r2;
118 
119  // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
120  bool HasMips5_32r2;
121 
122  // InMips16 -- can process Mips16 instructions
123  bool InMips16Mode;
124 
125  // Mips16 hard float
126  bool InMips16HardFloat;
127 
128  // InMicroMips -- can process MicroMips instructions
129  bool InMicroMipsMode;
130 
131  // HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE.
132  bool HasDSP, HasDSPR2, HasDSPR3;
133 
134  // Allow mixed Mips16 and Mips32 in one source file
135  bool AllowMixed16_32;
136 
137  // Optimize for space by compiling all functions as Mips 16 unless
138  // it needs floating point. Functions needing floating point are
139  // compiled as Mips32
140  bool Os16;
141 
142  // HasMSA -- supports MSA ASE.
143  bool HasMSA;
144 
145  // UseTCCInDIV -- Enables the use of trapping in the assembler.
146  bool UseTCCInDIV;
147 
148  // Sym32 -- On Mips64 symbols are 32 bits.
149  bool HasSym32;
150 
151  // HasEVA -- supports EVA ASE.
152  bool HasEVA;
153 
154  // nomadd4 - disables generation of 4-operand madd.s, madd.d and
155  // related instructions.
156  bool DisableMadd4;
157 
158  // HasMT -- support MT ASE.
159  bool HasMT;
160 
161  // Disable use of the `jal` instruction.
162  bool UseLongCalls = false;
163 
164  /// The minimum alignment known to hold of the stack frame on
165  /// entry to the function and which must be maintained by every function.
166  unsigned stackAlignment;
167 
168  /// The overridden stack alignment.
169  unsigned StackAlignOverride;
170 
171  InstrItineraryData InstrItins;
172 
173  // We can override the determination of whether we are in mips16 mode
174  // as from the command line
175  enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
176 
177  const MipsTargetMachine &TM;
178 
179  Triple TargetTriple;
180 
181  const SelectionDAGTargetInfo TSInfo;
182  std::unique_ptr<const MipsInstrInfo> InstrInfo;
183  std::unique_ptr<const MipsFrameLowering> FrameLowering;
184  std::unique_ptr<const MipsTargetLowering> TLInfo;
185 
186 public:
187  bool isPositionIndependent() const;
188  /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
189  bool enablePostRAScheduler() const override;
190  void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
192 
193  bool isABI_N64() const;
194  bool isABI_N32() const;
195  bool isABI_O32() const;
196  const MipsABIInfo &getABI() const;
197  bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
198 
199  /// This constructor initializes the data members to match that
200  /// of the specified triple.
201  MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little,
202  const MipsTargetMachine &TM, unsigned StackAlignOverride);
203 
204  /// ParseSubtargetFeatures - Parses features string setting specified
205  /// subtarget options. Definition of function is auto generated by tblgen.
207 
208  bool hasMips1() const { return MipsArchVersion >= Mips1; }
209  bool hasMips2() const { return MipsArchVersion >= Mips2; }
210  bool hasMips3() const { return MipsArchVersion >= Mips3; }
211  bool hasMips4() const { return MipsArchVersion >= Mips4; }
212  bool hasMips5() const { return MipsArchVersion >= Mips5; }
213  bool hasMips4_32() const { return HasMips4_32; }
214  bool hasMips4_32r2() const { return HasMips4_32r2; }
215  bool hasMips32() const {
216  return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) ||
217  hasMips64();
218  }
219  bool hasMips32r2() const {
220  return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) ||
221  hasMips64r2();
222  }
223  bool hasMips32r3() const {
224  return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) ||
225  hasMips64r2();
226  }
227  bool hasMips32r5() const {
228  return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
229  hasMips64r5();
230  }
231  bool hasMips32r6() const {
232  return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||
233  hasMips64r6();
234  }
235  bool hasMips64() const { return MipsArchVersion >= Mips64; }
236  bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; }
237  bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; }
238  bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; }
239  bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; }
240 
241  bool hasCnMips() const { return HasCnMips; }
242 
243  bool isLittle() const { return IsLittle; }
244  bool isABICalls() const { return !NoABICalls; }
245  bool isFPXX() const { return IsFPXX; }
246  bool isFP64bit() const { return IsFP64bit; }
247  bool useOddSPReg() const { return UseOddSPReg; }
248  bool noOddSPReg() const { return !UseOddSPReg; }
249  bool isNaN2008() const { return IsNaN2008bit; }
250  bool isGP64bit() const { return IsGP64bit; }
251  bool isGP32bit() const { return !IsGP64bit; }
252  unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
253  bool isPTR64bit() const { return IsPTR64bit; }
254  bool isPTR32bit() const { return !IsPTR64bit; }
255  bool hasSym32() const {
256  return (HasSym32 && isABI_N64()) || isABI_N32() || isABI_O32();
257  }
258  bool isSingleFloat() const { return IsSingleFloat; }
259  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
260  bool hasVFPU() const { return HasVFPU; }
261  bool inMips16Mode() const { return InMips16Mode; }
262  bool inMips16ModeDefault() const {
263  return InMips16Mode;
264  }
265  // Hard float for mips16 means essentially to compile as soft float
266  // but to use a runtime library for soft float that is written with
267  // native mips32 floating point instructions (those runtime routines
268  // run in mips32 hard float mode).
269  bool inMips16HardFloat() const {
270  return inMips16Mode() && InMips16HardFloat;
271  }
272  bool inMicroMipsMode() const { return InMicroMipsMode; }
273  bool inMicroMips32r6Mode() const { return InMicroMipsMode && hasMips32r6(); }
274  bool hasDSP() const { return HasDSP; }
275  bool hasDSPR2() const { return HasDSPR2; }
276  bool hasDSPR3() const { return HasDSPR3; }
277  bool hasMSA() const { return HasMSA; }
278  bool disableMadd4() const { return DisableMadd4; }
279  bool hasEVA() const { return HasEVA; }
280  bool hasMT() const { return HasMT; }
281  bool useSmallSection() const { return UseSmallSection; }
282 
283  bool hasStandardEncoding() const { return !inMips16Mode(); }
284 
285  bool useSoftFloat() const { return IsSoftFloat; }
286 
287  bool useLongCalls() const { return UseLongCalls; }
288 
289  bool enableLongBranchPass() const {
290  return hasStandardEncoding() || allowMixed16_32();
291  }
292 
293  /// Features related to the presence of specific instructions.
294  bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
295  bool hasMTHC1() const { return hasMips32r2(); }
296 
297  bool allowMixed16_32() const { return inMips16ModeDefault() |
298  AllowMixed16_32; }
299 
300  bool os16() const { return Os16; }
301 
302  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
303 
304  bool isXRaySupported() const override { return true; }
305 
306  // for now constant islands are on for the whole compilation unit but we only
307  // really use them if in addition we are in mips16 mode
308  static bool useConstantIslands();
309 
310  unsigned getStackAlignment() const { return stackAlignment; }
311 
312  // Grab relocation model
314 
316  const TargetMachine &TM);
317 
318  /// Does the system support unaligned memory access.
319  ///
320  /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
321  /// specify which component of the system provides it. Hardware, software, and
322  /// hybrid implementations are all valid.
323  bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
324 
325  // Set helper classes
326  void setHelperClassesMips16();
327  void setHelperClassesMipsSE();
328 
329  const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
330  return &TSInfo;
331  }
332  const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
333  const TargetFrameLowering *getFrameLowering() const override {
334  return FrameLowering.get();
335  }
336  const MipsRegisterInfo *getRegisterInfo() const override {
337  return &InstrInfo->getRegisterInfo();
338  }
339  const MipsTargetLowering *getTargetLowering() const override {
340  return TLInfo.get();
341  }
342  const InstrItineraryData *getInstrItineraryData() const override {
343  return &InstrItins;
344  }
345 };
346 } // End llvm namespace
347 
348 #endif
bool isABI_FPXX() const
bool isABICalls() const
bool inMips16HardFloat() const
bool isPTR64bit() const
bool hasVFPU() const
bool inMips16ModeDefault() const
bool hasMTHC1() const
bool hasMips3() const
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool inMips16Mode() const
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:588
MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little, const MipsTargetMachine &TM, unsigned StackAlignOverride)
This constructor initializes the data members to match that of the specified triple.
bool hasMips2() const
void setHelperClassesMips16()
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:567
const MipsInstrInfo * getInstrInfo() const override
const InstrItineraryData * getInstrItineraryData() const override
bool isABI_O32() const
bool hasMips4_32() const
bool hasExtractInsert() const
Features related to the presence of specific instructions.
bool enableLongBranchPass() const
bool isFPXX() const
bool hasMips64() const
bool hasDSPR3() const
bool hasDSPR2() const
bool hasSym32() const
bool inMicroMipsMode() const
bool isXRaySupported() const override
bool hasStandardEncoding() const
bool hasMips4_32r2() const
bool isGP64bit() const
bool hasMips32r6() const
bool hasMips1() const
bool hasMips64r3() const
Itinerary data supplied by a subtarget to be used by a target.
bool useSmallSection() const
bool isPTR32bit() const
bool hasMips32r5() const
bool isTargetNaCl() const
const TargetFrameLowering * getFrameLowering() const override
unsigned getGPRSizeInBytes() const
unsigned getStackAlignment() const
bool useLongCalls() const
bool hasMips64r2() const
bool hasMips32r3() const
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
bool isSingleFloat() const
bool hasMips64r6() const
const MipsABIInfo & getABI() const
bool isABI_N32() const
bool isNaN2008() const
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool hasMips64r5() const
bool hasMT() const
static bool useConstantIslands()
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
bool hasEVA() const
bool isLittle() const
const MipsRegisterInfo * getRegisterInfo() const override
bool isPositionIndependent() const
bool enablePostRAScheduler() const override
This overrides the PostRAScheduler bit in the SchedModel for each CPU.
bool hasCnMips() const
void setHelperClassesMipsSE()
Information about stack frame layout on the target.
bool hasMips5() const
bool hasDSP() const
const MipsTargetLowering * getTargetLowering() const override
bool isTargetELF() const
bool hasMips4() const
bool noOddSPReg() const
bool hasMips32() const
bool useOddSPReg() const
bool hasMips32r2() const
bool isABI_N64() const
bool allowMixed16_32() const
CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override
Reloc::Model getRelocationModel() const
bool isGP32bit() const
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
MipsSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS, const TargetMachine &TM)
bool useSoftFloat() const
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
bool inMicroMips32r6Mode() const
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
bool systemSupportsUnalignedAccess() const
Does the system support unaligned memory access.
bool isFP64bit() const
bool disableMadd4() const
bool hasMSA() const