LLVM  6.0.0svn
MipsSubtarget.h
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1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the Mips specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
15 #define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
16 
18 #include "MipsFrameLowering.h"
19 #include "MipsISelLowering.h"
20 #include "MipsInstrInfo.h"
22 #include "llvm/IR/DataLayout.h"
26 #include <string>
27 
28 #define GET_SUBTARGETINFO_HEADER
29 #include "MipsGenSubtargetInfo.inc"
30 
31 namespace llvm {
32 class StringRef;
33 
34 class MipsTargetMachine;
35 
37  virtual void anchor();
38 
39  enum MipsArchEnum {
40  MipsDefault,
41  Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,
42  Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
43  };
44 
45  enum class CPU { P5600 };
46 
47  // Mips architecture version
48  MipsArchEnum MipsArchVersion;
49 
50  // Processor implementation (unused but required to exist by
51  // tablegen-erated code).
52  CPU ProcImpl;
53 
54  // IsLittle - The target is Little Endian
55  bool IsLittle;
56 
57  // IsSoftFloat - The target does not support any floating point instructions.
58  bool IsSoftFloat;
59 
60  // IsSingleFloat - The target only supports single precision float
61  // point operations. This enable the target to use all 32 32-bit
62  // floating point registers instead of only using even ones.
63  bool IsSingleFloat;
64 
65  // IsFPXX - MIPS O32 modeless ABI.
66  bool IsFPXX;
67 
68  // NoABICalls - Disable SVR4-style position-independent code.
69  bool NoABICalls;
70 
71  // IsFP64bit - The target processor has 64-bit floating point registers.
72  bool IsFP64bit;
73 
74  /// Are odd single-precision registers permitted?
75  /// This corresponds to -modd-spreg and -mno-odd-spreg
76  bool UseOddSPReg;
77 
78  // IsNan2008 - IEEE 754-2008 NaN encoding.
79  bool IsNaN2008bit;
80 
81  // IsGP64bit - General-purpose registers are 64 bits wide
82  bool IsGP64bit;
83 
84  // IsPTR64bit - Pointers are 64 bit wide
85  bool IsPTR64bit;
86 
87  // HasVFPU - Processor has a vector floating point unit.
88  bool HasVFPU;
89 
90  // CPU supports cnMIPS (Cavium Networks Octeon CPU).
91  bool HasCnMips;
92 
93  // isLinux - Target system is Linux. Is false we consider ELFOS for now.
94  bool IsLinux;
95 
96  // UseSmallSection - Small section is used.
97  bool UseSmallSection;
98 
99  /// Features related to the presence of specific instructions.
100 
101  // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
102  bool HasMips3_32;
103 
104  // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
105  bool HasMips3_32r2;
106 
107  // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
108  bool HasMips4_32;
109 
110  // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
111  bool HasMips4_32r2;
112 
113  // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
114  bool HasMips5_32r2;
115 
116  // InMips16 -- can process Mips16 instructions
117  bool InMips16Mode;
118 
119  // Mips16 hard float
120  bool InMips16HardFloat;
121 
122  // InMicroMips -- can process MicroMips instructions
123  bool InMicroMipsMode;
124 
125  // HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE.
126  bool HasDSP, HasDSPR2, HasDSPR3;
127 
128  // Allow mixed Mips16 and Mips32 in one source file
129  bool AllowMixed16_32;
130 
131  // Optimize for space by compiling all functions as Mips 16 unless
132  // it needs floating point. Functions needing floating point are
133  // compiled as Mips32
134  bool Os16;
135 
136  // HasMSA -- supports MSA ASE.
137  bool HasMSA;
138 
139  // UseTCCInDIV -- Enables the use of trapping in the assembler.
140  bool UseTCCInDIV;
141 
142  // Sym32 -- On Mips64 symbols are 32 bits.
143  bool HasSym32;
144 
145  // HasEVA -- supports EVA ASE.
146  bool HasEVA;
147 
148  // nomadd4 - disables generation of 4-operand madd.s, madd.d and
149  // related instructions.
150  bool DisableMadd4;
151 
152  // HasMT -- support MT ASE.
153  bool HasMT;
154 
155  // Disable use of the `jal` instruction.
156  bool UseLongCalls = false;
157 
158  /// The minimum alignment known to hold of the stack frame on
159  /// entry to the function and which must be maintained by every function.
160  unsigned stackAlignment;
161 
162  /// The overridden stack alignment.
163  unsigned StackAlignOverride;
164 
165  InstrItineraryData InstrItins;
166 
167  // We can override the determination of whether we are in mips16 mode
168  // as from the command line
169  enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
170 
171  const MipsTargetMachine &TM;
172 
173  Triple TargetTriple;
174 
175  const SelectionDAGTargetInfo TSInfo;
176  std::unique_ptr<const MipsInstrInfo> InstrInfo;
177  std::unique_ptr<const MipsFrameLowering> FrameLowering;
178  std::unique_ptr<const MipsTargetLowering> TLInfo;
179 
180 public:
181  bool isPositionIndependent() const;
182  /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
183  bool enablePostRAScheduler() const override;
184  void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
186 
187  bool isABI_N64() const;
188  bool isABI_N32() const;
189  bool isABI_O32() const;
190  const MipsABIInfo &getABI() const;
191  bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
192 
193  /// This constructor initializes the data members to match that
194  /// of the specified triple.
195  MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little,
196  const MipsTargetMachine &TM, unsigned StackAlignOverride);
197 
198  /// ParseSubtargetFeatures - Parses features string setting specified
199  /// subtarget options. Definition of function is auto generated by tblgen.
201 
202  bool hasMips1() const { return MipsArchVersion >= Mips1; }
203  bool hasMips2() const { return MipsArchVersion >= Mips2; }
204  bool hasMips3() const { return MipsArchVersion >= Mips3; }
205  bool hasMips4() const { return MipsArchVersion >= Mips4; }
206  bool hasMips5() const { return MipsArchVersion >= Mips5; }
207  bool hasMips4_32() const { return HasMips4_32; }
208  bool hasMips4_32r2() const { return HasMips4_32r2; }
209  bool hasMips32() const {
210  return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) ||
211  hasMips64();
212  }
213  bool hasMips32r2() const {
214  return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) ||
215  hasMips64r2();
216  }
217  bool hasMips32r3() const {
218  return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) ||
219  hasMips64r2();
220  }
221  bool hasMips32r5() const {
222  return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
223  hasMips64r5();
224  }
225  bool hasMips32r6() const {
226  return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||
227  hasMips64r6();
228  }
229  bool hasMips64() const { return MipsArchVersion >= Mips64; }
230  bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; }
231  bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; }
232  bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; }
233  bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; }
234 
235  bool hasCnMips() const { return HasCnMips; }
236 
237  bool isLittle() const { return IsLittle; }
238  bool isABICalls() const { return !NoABICalls; }
239  bool isFPXX() const { return IsFPXX; }
240  bool isFP64bit() const { return IsFP64bit; }
241  bool useOddSPReg() const { return UseOddSPReg; }
242  bool noOddSPReg() const { return !UseOddSPReg; }
243  bool isNaN2008() const { return IsNaN2008bit; }
244  bool isGP64bit() const { return IsGP64bit; }
245  bool isGP32bit() const { return !IsGP64bit; }
246  unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
247  bool isPTR64bit() const { return IsPTR64bit; }
248  bool isPTR32bit() const { return !IsPTR64bit; }
249  bool hasSym32() const {
250  return (HasSym32 && isABI_N64()) || isABI_N32() || isABI_O32();
251  }
252  bool isSingleFloat() const { return IsSingleFloat; }
253  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
254  bool hasVFPU() const { return HasVFPU; }
255  bool inMips16Mode() const { return InMips16Mode; }
256  bool inMips16ModeDefault() const {
257  return InMips16Mode;
258  }
259  // Hard float for mips16 means essentially to compile as soft float
260  // but to use a runtime library for soft float that is written with
261  // native mips32 floating point instructions (those runtime routines
262  // run in mips32 hard float mode).
263  bool inMips16HardFloat() const {
264  return inMips16Mode() && InMips16HardFloat;
265  }
266  bool inMicroMipsMode() const { return InMicroMipsMode; }
267  bool inMicroMips32r6Mode() const { return InMicroMipsMode && hasMips32r6(); }
268  bool inMicroMips64r6Mode() const { return InMicroMipsMode && hasMips64r6(); }
269  bool hasDSP() const { return HasDSP; }
270  bool hasDSPR2() const { return HasDSPR2; }
271  bool hasDSPR3() const { return HasDSPR3; }
272  bool hasMSA() const { return HasMSA; }
273  bool disableMadd4() const { return DisableMadd4; }
274  bool hasEVA() const { return HasEVA; }
275  bool hasMT() const { return HasMT; }
276  bool useSmallSection() const { return UseSmallSection; }
277 
278  bool hasStandardEncoding() const { return !inMips16Mode(); }
279 
280  bool useSoftFloat() const { return IsSoftFloat; }
281 
282  bool useLongCalls() const { return UseLongCalls; }
283 
284  bool enableLongBranchPass() const {
285  return hasStandardEncoding() || allowMixed16_32();
286  }
287 
288  /// Features related to the presence of specific instructions.
289  bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
290  bool hasMTHC1() const { return hasMips32r2(); }
291 
292  bool allowMixed16_32() const { return inMips16ModeDefault() |
293  AllowMixed16_32; }
294 
295  bool os16() const { return Os16; }
296 
297  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
298 
299  bool isXRaySupported() const override { return true; }
300 
301  // for now constant islands are on for the whole compilation unit but we only
302  // really use them if in addition we are in mips16 mode
303  static bool useConstantIslands();
304 
305  unsigned getStackAlignment() const { return stackAlignment; }
306 
307  // Grab relocation model
309 
311  const TargetMachine &TM);
312 
313  /// Does the system support unaligned memory access.
314  ///
315  /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
316  /// specify which component of the system provides it. Hardware, software, and
317  /// hybrid implementations are all valid.
318  bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
319 
320  // Set helper classes
321  void setHelperClassesMips16();
322  void setHelperClassesMipsSE();
323 
324  const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
325  return &TSInfo;
326  }
327  const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
328  const TargetFrameLowering *getFrameLowering() const override {
329  return FrameLowering.get();
330  }
331  const MipsRegisterInfo *getRegisterInfo() const override {
332  return &InstrInfo->getRegisterInfo();
333  }
334  const MipsTargetLowering *getTargetLowering() const override {
335  return TLInfo.get();
336  }
337  const InstrItineraryData *getInstrItineraryData() const override {
338  return &InstrItins;
339  }
340 };
341 } // End llvm namespace
342 
343 #endif
bool isABI_FPXX() const
bool isABICalls() const
bool inMips16HardFloat() const
bool isPTR64bit() const
bool hasVFPU() const
bool inMips16ModeDefault() const
bool hasMTHC1() const
bool hasMips3() const
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool inMips16Mode() const
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:581
MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little, const MipsTargetMachine &TM, unsigned StackAlignOverride)
This constructor initializes the data members to match that of the specified triple.
bool hasMips2() const
void setHelperClassesMips16()
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:560
const MipsInstrInfo * getInstrInfo() const override
const InstrItineraryData * getInstrItineraryData() const override
bool isABI_O32() const
bool hasMips4_32() const
bool hasExtractInsert() const
Features related to the presence of specific instructions.
bool enableLongBranchPass() const
bool isFPXX() const
bool hasMips64() const
bool hasDSPR3() const
bool hasDSPR2() const
bool hasSym32() const
bool inMicroMipsMode() const
bool isXRaySupported() const override
bool hasStandardEncoding() const
bool hasMips4_32r2() const
bool isGP64bit() const
bool hasMips32r6() const
bool hasMips1() const
bool hasMips64r3() const
Itinerary data supplied by a subtarget to be used by a target.
bool useSmallSection() const
bool isPTR32bit() const
bool hasMips32r5() const
bool isTargetNaCl() const
const TargetFrameLowering * getFrameLowering() const override
unsigned getGPRSizeInBytes() const
unsigned getStackAlignment() const
bool useLongCalls() const
bool hasMips64r2() const
bool hasMips32r3() const
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
bool isSingleFloat() const
bool hasMips64r6() const
const MipsABIInfo & getABI() const
bool isABI_N32() const
bool isNaN2008() const
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool hasMips64r5() const
bool hasMT() const
static bool useConstantIslands()
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
bool hasEVA() const
bool isLittle() const
const MipsRegisterInfo * getRegisterInfo() const override
bool isPositionIndependent() const
bool enablePostRAScheduler() const override
This overrides the PostRAScheduler bit in the SchedModel for each CPU.
bool hasCnMips() const
void setHelperClassesMipsSE()
Information about stack frame layout on the target.
bool hasMips5() const
bool hasDSP() const
const MipsTargetLowering * getTargetLowering() const override
bool isTargetELF() const
bool hasMips4() const
bool inMicroMips64r6Mode() const
bool noOddSPReg() const
bool hasMips32() const
bool useOddSPReg() const
bool hasMips32r2() const
bool isABI_N64() const
bool allowMixed16_32() const
CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override
Reloc::Model getRelocationModel() const
bool isGP32bit() const
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
MipsSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS, const TargetMachine &TM)
bool useSoftFloat() const
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:57
bool inMicroMips32r6Mode() const
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
bool systemSupportsUnalignedAccess() const
Does the system support unaligned memory access.
bool isFP64bit() const
bool disableMadd4() const
bool hasMSA() const