LLVM  7.0.0svn
MipsSubtarget.h
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1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the Mips specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
15 #define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
16 
18 #include "MipsFrameLowering.h"
19 #include "MipsISelLowering.h"
20 #include "MipsInstrInfo.h"
27 #include "llvm/IR/DataLayout.h"
30 #include <string>
31 
32 #define GET_SUBTARGETINFO_HEADER
33 #include "MipsGenSubtargetInfo.inc"
34 
35 namespace llvm {
36 class StringRef;
37 
38 class MipsTargetMachine;
39 
41  virtual void anchor();
42 
43  enum MipsArchEnum {
44  MipsDefault,
45  Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,
46  Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
47  };
48 
49  enum class CPU { P5600 };
50 
51  // Used to avoid printing dsp warnings multiple times.
52  static bool DspWarningPrinted;
53 
54  // Used to avoid printing msa warnings multiple times.
55  static bool MSAWarningPrinted;
56 
57  // Mips architecture version
58  MipsArchEnum MipsArchVersion;
59 
60  // Processor implementation (unused but required to exist by
61  // tablegen-erated code).
62  CPU ProcImpl;
63 
64  // IsLittle - The target is Little Endian
65  bool IsLittle;
66 
67  // IsSoftFloat - The target does not support any floating point instructions.
68  bool IsSoftFloat;
69 
70  // IsSingleFloat - The target only supports single precision float
71  // point operations. This enable the target to use all 32 32-bit
72  // floating point registers instead of only using even ones.
73  bool IsSingleFloat;
74 
75  // IsFPXX - MIPS O32 modeless ABI.
76  bool IsFPXX;
77 
78  // NoABICalls - Disable SVR4-style position-independent code.
79  bool NoABICalls;
80 
81  // IsFP64bit - The target processor has 64-bit floating point registers.
82  bool IsFP64bit;
83 
84  /// Are odd single-precision registers permitted?
85  /// This corresponds to -modd-spreg and -mno-odd-spreg
86  bool UseOddSPReg;
87 
88  // IsNan2008 - IEEE 754-2008 NaN encoding.
89  bool IsNaN2008bit;
90 
91  // IsGP64bit - General-purpose registers are 64 bits wide
92  bool IsGP64bit;
93 
94  // IsPTR64bit - Pointers are 64 bit wide
95  bool IsPTR64bit;
96 
97  // HasVFPU - Processor has a vector floating point unit.
98  bool HasVFPU;
99 
100  // CPU supports cnMIPS (Cavium Networks Octeon CPU).
101  bool HasCnMips;
102 
103  // isLinux - Target system is Linux. Is false we consider ELFOS for now.
104  bool IsLinux;
105 
106  // UseSmallSection - Small section is used.
107  bool UseSmallSection;
108 
109  /// Features related to the presence of specific instructions.
110 
111  // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
112  bool HasMips3_32;
113 
114  // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
115  bool HasMips3_32r2;
116 
117  // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
118  bool HasMips4_32;
119 
120  // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
121  bool HasMips4_32r2;
122 
123  // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
124  bool HasMips5_32r2;
125 
126  // InMips16 -- can process Mips16 instructions
127  bool InMips16Mode;
128 
129  // Mips16 hard float
130  bool InMips16HardFloat;
131 
132  // InMicroMips -- can process MicroMips instructions
133  bool InMicroMipsMode;
134 
135  // HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE.
136  bool HasDSP, HasDSPR2, HasDSPR3;
137 
138  // Allow mixed Mips16 and Mips32 in one source file
139  bool AllowMixed16_32;
140 
141  // Optimize for space by compiling all functions as Mips 16 unless
142  // it needs floating point. Functions needing floating point are
143  // compiled as Mips32
144  bool Os16;
145 
146  // HasMSA -- supports MSA ASE.
147  bool HasMSA;
148 
149  // UseTCCInDIV -- Enables the use of trapping in the assembler.
150  bool UseTCCInDIV;
151 
152  // Sym32 -- On Mips64 symbols are 32 bits.
153  bool HasSym32;
154 
155  // HasEVA -- supports EVA ASE.
156  bool HasEVA;
157 
158  // nomadd4 - disables generation of 4-operand madd.s, madd.d and
159  // related instructions.
160  bool DisableMadd4;
161 
162  // HasMT -- support MT ASE.
163  bool HasMT;
164 
165  // HasCRC -- supports R6 CRC ASE
166  bool HasCRC;
167 
168  // Use hazard variants of the jump register instructions for indirect
169  // function calls and jump tables.
170  bool UseIndirectJumpsHazard;
171 
172  // Disable use of the `jal` instruction.
173  bool UseLongCalls = false;
174 
175  /// The minimum alignment known to hold of the stack frame on
176  /// entry to the function and which must be maintained by every function.
177  unsigned stackAlignment;
178 
179  /// The overridden stack alignment.
180  unsigned StackAlignOverride;
181 
182  InstrItineraryData InstrItins;
183 
184  // We can override the determination of whether we are in mips16 mode
185  // as from the command line
186  enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
187 
188  const MipsTargetMachine &TM;
189 
190  Triple TargetTriple;
191 
192  const SelectionDAGTargetInfo TSInfo;
193  std::unique_ptr<const MipsInstrInfo> InstrInfo;
194  std::unique_ptr<const MipsFrameLowering> FrameLowering;
195  std::unique_ptr<const MipsTargetLowering> TLInfo;
196 
197 public:
198  bool isPositionIndependent() const;
199  /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
200  bool enablePostRAScheduler() const override;
201  void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
203 
204  bool isABI_N64() const;
205  bool isABI_N32() const;
206  bool isABI_O32() const;
207  const MipsABIInfo &getABI() const;
208  bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
209 
210  /// This constructor initializes the data members to match that
211  /// of the specified triple.
212  MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little,
213  const MipsTargetMachine &TM, unsigned StackAlignOverride);
214 
215  /// ParseSubtargetFeatures - Parses features string setting specified
216  /// subtarget options. Definition of function is auto generated by tblgen.
218 
219  bool hasMips1() const { return MipsArchVersion >= Mips1; }
220  bool hasMips2() const { return MipsArchVersion >= Mips2; }
221  bool hasMips3() const { return MipsArchVersion >= Mips3; }
222  bool hasMips4() const { return MipsArchVersion >= Mips4; }
223  bool hasMips5() const { return MipsArchVersion >= Mips5; }
224  bool hasMips4_32() const { return HasMips4_32; }
225  bool hasMips4_32r2() const { return HasMips4_32r2; }
226  bool hasMips32() const {
227  return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) ||
228  hasMips64();
229  }
230  bool hasMips32r2() const {
231  return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) ||
232  hasMips64r2();
233  }
234  bool hasMips32r3() const {
235  return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) ||
236  hasMips64r2();
237  }
238  bool hasMips32r5() const {
239  return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
240  hasMips64r5();
241  }
242  bool hasMips32r6() const {
243  return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||
244  hasMips64r6();
245  }
246  bool hasMips64() const { return MipsArchVersion >= Mips64; }
247  bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; }
248  bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; }
249  bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; }
250  bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; }
251 
252  bool hasCnMips() const { return HasCnMips; }
253 
254  bool isLittle() const { return IsLittle; }
255  bool isABICalls() const { return !NoABICalls; }
256  bool isFPXX() const { return IsFPXX; }
257  bool isFP64bit() const { return IsFP64bit; }
258  bool useOddSPReg() const { return UseOddSPReg; }
259  bool noOddSPReg() const { return !UseOddSPReg; }
260  bool isNaN2008() const { return IsNaN2008bit; }
261  bool isGP64bit() const { return IsGP64bit; }
262  bool isGP32bit() const { return !IsGP64bit; }
263  unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
264  bool isPTR64bit() const { return IsPTR64bit; }
265  bool isPTR32bit() const { return !IsPTR64bit; }
266  bool hasSym32() const {
267  return (HasSym32 && isABI_N64()) || isABI_N32() || isABI_O32();
268  }
269  bool isSingleFloat() const { return IsSingleFloat; }
270  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
271  bool hasVFPU() const { return HasVFPU; }
272  bool inMips16Mode() const { return InMips16Mode; }
273  bool inMips16ModeDefault() const {
274  return InMips16Mode;
275  }
276  // Hard float for mips16 means essentially to compile as soft float
277  // but to use a runtime library for soft float that is written with
278  // native mips32 floating point instructions (those runtime routines
279  // run in mips32 hard float mode).
280  bool inMips16HardFloat() const {
281  return inMips16Mode() && InMips16HardFloat;
282  }
283  bool inMicroMipsMode() const { return InMicroMipsMode; }
284  bool inMicroMips32r6Mode() const { return InMicroMipsMode && hasMips32r6(); }
285  bool hasDSP() const { return HasDSP; }
286  bool hasDSPR2() const { return HasDSPR2; }
287  bool hasDSPR3() const { return HasDSPR3; }
288  bool hasMSA() const { return HasMSA; }
289  bool disableMadd4() const { return DisableMadd4; }
290  bool hasEVA() const { return HasEVA; }
291  bool hasMT() const { return HasMT; }
292  bool hasCRC() const { return HasCRC; }
293  bool useIndirectJumpsHazard() const {
294  return UseIndirectJumpsHazard && hasMips32r2();
295  }
296  bool useSmallSection() const { return UseSmallSection; }
297 
298  bool hasStandardEncoding() const { return !inMips16Mode(); }
299 
300  bool useSoftFloat() const { return IsSoftFloat; }
301 
302  bool useLongCalls() const { return UseLongCalls; }
303 
304  bool enableLongBranchPass() const {
305  return hasStandardEncoding() || allowMixed16_32();
306  }
307 
308  /// Features related to the presence of specific instructions.
309  bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
310  bool hasMTHC1() const { return hasMips32r2(); }
311 
312  bool allowMixed16_32() const { return inMips16ModeDefault() |
313  AllowMixed16_32; }
314 
315  bool os16() const { return Os16; }
316 
317  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
318 
319  bool isXRaySupported() const override { return true; }
320 
321  // for now constant islands are on for the whole compilation unit but we only
322  // really use them if in addition we are in mips16 mode
323  static bool useConstantIslands();
324 
325  unsigned getStackAlignment() const { return stackAlignment; }
326 
327  // Grab relocation model
329 
331  const TargetMachine &TM);
332 
333  /// Does the system support unaligned memory access.
334  ///
335  /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
336  /// specify which component of the system provides it. Hardware, software, and
337  /// hybrid implementations are all valid.
338  bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
339 
340  // Set helper classes
341  void setHelperClassesMips16();
342  void setHelperClassesMipsSE();
343 
344  const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
345  return &TSInfo;
346  }
347  const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
348  const TargetFrameLowering *getFrameLowering() const override {
349  return FrameLowering.get();
350  }
351  const MipsRegisterInfo *getRegisterInfo() const override {
352  return &InstrInfo->getRegisterInfo();
353  }
354  const MipsTargetLowering *getTargetLowering() const override {
355  return TLInfo.get();
356  }
357  const InstrItineraryData *getInstrItineraryData() const override {
358  return &InstrItins;
359  }
360 
361 protected:
362  // GlobalISel related APIs.
363  std::unique_ptr<CallLowering> CallLoweringInfo;
364  std::unique_ptr<LegalizerInfo> Legalizer;
365  std::unique_ptr<RegisterBankInfo> RegBankInfo;
366  std::unique_ptr<InstructionSelector> InstSelector;
367 
368 public:
369  const CallLowering *getCallLowering() const override;
370  const LegalizerInfo *getLegalizerInfo() const override;
371  const RegisterBankInfo *getRegBankInfo() const override;
372  const InstructionSelector *getInstructionSelector() const override;
373 };
374 } // End llvm namespace
375 
376 #endif
const RegisterBankInfo * getRegBankInfo() const override
bool isABI_FPXX() const
bool isABICalls() const
bool inMips16HardFloat() const
bool isPTR64bit() const
bool hasVFPU() const
bool inMips16ModeDefault() const
std::unique_ptr< InstructionSelector > InstSelector
bool hasMTHC1() const
bool hasMips3() const
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool inMips16Mode() const
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:586
MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little, const MipsTargetMachine &TM, unsigned StackAlignOverride)
This constructor initializes the data members to match that of the specified triple.
bool hasMips2() const
void setHelperClassesMips16()
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:565
const MipsInstrInfo * getInstrInfo() const override
const InstrItineraryData * getInstrItineraryData() const override
bool isABI_O32() const
bool hasMips4_32() const
bool hasExtractInsert() const
Features related to the presence of specific instructions.
bool enableLongBranchPass() const
const InstructionSelector * getInstructionSelector() const override
bool isFPXX() const
bool hasMips64() const
bool hasDSPR3() const
bool hasDSPR2() const
Holds all the information related to register banks.
bool hasSym32() const
bool inMicroMipsMode() const
bool isXRaySupported() const override
bool hasStandardEncoding() const
bool useIndirectJumpsHazard() const
bool hasMips4_32r2() const
bool isGP64bit() const
bool hasMips32r6() const
bool hasMips1() const
bool hasMips64r3() const
Itinerary data supplied by a subtarget to be used by a target.
bool useSmallSection() const
bool isPTR32bit() const
bool hasMips32r5() const
bool isTargetNaCl() const
const TargetFrameLowering * getFrameLowering() const override
unsigned getGPRSizeInBytes() const
unsigned getStackAlignment() const
bool hasCRC() const
const LegalizerInfo * getLegalizerInfo() const override
bool useLongCalls() const
std::unique_ptr< RegisterBankInfo > RegBankInfo
bool hasMips64r2() const
bool hasMips32r3() const
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
bool isSingleFloat() const
bool hasMips64r6() const
const MipsABIInfo & getABI() const
bool isABI_N32() const
bool isNaN2008() const
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
std::unique_ptr< CallLowering > CallLoweringInfo
bool hasMips64r5() const
bool hasMT() const
static bool useConstantIslands()
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
bool hasEVA() const
bool isLittle() const
const MipsRegisterInfo * getRegisterInfo() const override
bool isPositionIndependent() const
bool enablePostRAScheduler() const override
This overrides the PostRAScheduler bit in the SchedModel for each CPU.
bool hasCnMips() const
void setHelperClassesMipsSE()
Information about stack frame layout on the target.
bool hasMips5() const
bool hasDSP() const
const CallLowering * getCallLowering() const override
const MipsTargetLowering * getTargetLowering() const override
bool isTargetELF() const
bool hasMips4() const
Provides the logic to select generic machine instructions.
bool noOddSPReg() const
bool hasMips32() const
bool useOddSPReg() const
bool hasMips32r2() const
bool isABI_N64() const
bool allowMixed16_32() const
CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override
Reloc::Model getRelocationModel() const
bool isGP32bit() const
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
This file describes how to lower LLVM calls to machine code calls.
MipsSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS, const TargetMachine &TM)
bool useSoftFloat() const
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
bool inMicroMips32r6Mode() const
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
bool systemSupportsUnalignedAccess() const
Does the system support unaligned memory access.
bool isFP64bit() const
bool disableMadd4() const
bool hasMSA() const
std::unique_ptr< LegalizerInfo > Legalizer