LLVM  6.0.0svn
SparcInstrInfo.cpp
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1 //===-- SparcInstrInfo.cpp - Sparc Instruction Information ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Sparc implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "SparcInstrInfo.h"
15 #include "Sparc.h"
17 #include "SparcSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
26 
27 using namespace llvm;
28 
29 #define GET_INSTRINFO_CTOR_DTOR
30 #include "SparcGenInstrInfo.inc"
31 
32 // Pin the vtable to this file.
33 void SparcInstrInfo::anchor() {}
34 
36  : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), RI(),
37  Subtarget(ST) {}
38 
39 /// isLoadFromStackSlot - If the specified machine instruction is a direct
40 /// load from a stack slot, return the virtual or physical register number of
41 /// the destination along with the FrameIndex of the loaded stack slot. If
42 /// not, return 0. This predicate must return 0 if the instruction has
43 /// any side effects other than loading from the stack slot.
45  int &FrameIndex) const {
46  if (MI.getOpcode() == SP::LDri || MI.getOpcode() == SP::LDXri ||
47  MI.getOpcode() == SP::LDFri || MI.getOpcode() == SP::LDDFri ||
48  MI.getOpcode() == SP::LDQFri) {
49  if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
50  MI.getOperand(2).getImm() == 0) {
51  FrameIndex = MI.getOperand(1).getIndex();
52  return MI.getOperand(0).getReg();
53  }
54  }
55  return 0;
56 }
57 
58 /// isStoreToStackSlot - If the specified machine instruction is a direct
59 /// store to a stack slot, return the virtual or physical register number of
60 /// the source reg along with the FrameIndex of the loaded stack slot. If
61 /// not, return 0. This predicate must return 0 if the instruction has
62 /// any side effects other than storing to the stack slot.
64  int &FrameIndex) const {
65  if (MI.getOpcode() == SP::STri || MI.getOpcode() == SP::STXri ||
66  MI.getOpcode() == SP::STFri || MI.getOpcode() == SP::STDFri ||
67  MI.getOpcode() == SP::STQFri) {
68  if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
69  MI.getOperand(1).getImm() == 0) {
70  FrameIndex = MI.getOperand(0).getIndex();
71  return MI.getOperand(2).getReg();
72  }
73  }
74  return 0;
75 }
76 
77 static bool IsIntegerCC(unsigned CC)
78 {
79  return (CC <= SPCC::ICC_VC);
80 }
81 
83 {
84  switch(CC) {
85  case SPCC::ICC_A: return SPCC::ICC_N;
86  case SPCC::ICC_N: return SPCC::ICC_A;
87  case SPCC::ICC_NE: return SPCC::ICC_E;
88  case SPCC::ICC_E: return SPCC::ICC_NE;
89  case SPCC::ICC_G: return SPCC::ICC_LE;
90  case SPCC::ICC_LE: return SPCC::ICC_G;
91  case SPCC::ICC_GE: return SPCC::ICC_L;
92  case SPCC::ICC_L: return SPCC::ICC_GE;
93  case SPCC::ICC_GU: return SPCC::ICC_LEU;
94  case SPCC::ICC_LEU: return SPCC::ICC_GU;
95  case SPCC::ICC_CC: return SPCC::ICC_CS;
96  case SPCC::ICC_CS: return SPCC::ICC_CC;
97  case SPCC::ICC_POS: return SPCC::ICC_NEG;
98  case SPCC::ICC_NEG: return SPCC::ICC_POS;
99  case SPCC::ICC_VC: return SPCC::ICC_VS;
100  case SPCC::ICC_VS: return SPCC::ICC_VC;
101 
102  case SPCC::FCC_A: return SPCC::FCC_N;
103  case SPCC::FCC_N: return SPCC::FCC_A;
104  case SPCC::FCC_U: return SPCC::FCC_O;
105  case SPCC::FCC_O: return SPCC::FCC_U;
106  case SPCC::FCC_G: return SPCC::FCC_ULE;
107  case SPCC::FCC_LE: return SPCC::FCC_UG;
108  case SPCC::FCC_UG: return SPCC::FCC_LE;
109  case SPCC::FCC_ULE: return SPCC::FCC_G;
110  case SPCC::FCC_L: return SPCC::FCC_UGE;
111  case SPCC::FCC_GE: return SPCC::FCC_UL;
112  case SPCC::FCC_UL: return SPCC::FCC_GE;
113  case SPCC::FCC_UGE: return SPCC::FCC_L;
114  case SPCC::FCC_LG: return SPCC::FCC_UE;
115  case SPCC::FCC_UE: return SPCC::FCC_LG;
116  case SPCC::FCC_NE: return SPCC::FCC_E;
117  case SPCC::FCC_E: return SPCC::FCC_NE;
118 
119  case SPCC::CPCC_A: return SPCC::CPCC_N;
120  case SPCC::CPCC_N: return SPCC::CPCC_A;
134  case SPCC::CPCC_012:
135  // "Opposite" code is not meaningful, as we don't know
136  // what the CoProc condition means here. The cond-code will
137  // only be used in inline assembler, so this code should
138  // not be reached in a normal compilation pass.
139  llvm_unreachable("Meaningless inversion of co-processor cond code");
140  }
141  llvm_unreachable("Invalid cond code");
142 }
143 
144 static bool isUncondBranchOpcode(int Opc) { return Opc == SP::BA; }
145 
146 static bool isCondBranchOpcode(int Opc) {
147  return Opc == SP::FBCOND || Opc == SP::BCOND;
148 }
149 
150 static bool isIndirectBranchOpcode(int Opc) {
151  return Opc == SP::BINDrr || Opc == SP::BINDri;
152 }
153 
157  Target = LastInst->getOperand(0).getMBB();
158 }
159 
161  MachineBasicBlock *&TBB,
162  MachineBasicBlock *&FBB,
164  bool AllowModify) const {
166  if (I == MBB.end())
167  return false;
168 
169  if (!isUnpredicatedTerminator(*I))
170  return false;
171 
172  // Get the last instruction in the block.
173  MachineInstr *LastInst = &*I;
174  unsigned LastOpc = LastInst->getOpcode();
175 
176  // If there is only one terminator instruction, process it.
177  if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
178  if (isUncondBranchOpcode(LastOpc)) {
179  TBB = LastInst->getOperand(0).getMBB();
180  return false;
181  }
182  if (isCondBranchOpcode(LastOpc)) {
183  // Block ends with fall-through condbranch.
184  parseCondBranch(LastInst, TBB, Cond);
185  return false;
186  }
187  return true; // Can't handle indirect branch.
188  }
189 
190  // Get the instruction before it if it is a terminator.
191  MachineInstr *SecondLastInst = &*I;
192  unsigned SecondLastOpc = SecondLastInst->getOpcode();
193 
194  // If AllowModify is true and the block ends with two or more unconditional
195  // branches, delete all but the first unconditional branch.
196  if (AllowModify && isUncondBranchOpcode(LastOpc)) {
197  while (isUncondBranchOpcode(SecondLastOpc)) {
198  LastInst->eraseFromParent();
199  LastInst = SecondLastInst;
200  LastOpc = LastInst->getOpcode();
201  if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
202  // Return now the only terminator is an unconditional branch.
203  TBB = LastInst->getOperand(0).getMBB();
204  return false;
205  } else {
206  SecondLastInst = &*I;
207  SecondLastOpc = SecondLastInst->getOpcode();
208  }
209  }
210  }
211 
212  // If there are three terminators, we don't know what sort of block this is.
213  if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I))
214  return true;
215 
216  // If the block ends with a B and a Bcc, handle it.
217  if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
218  parseCondBranch(SecondLastInst, TBB, Cond);
219  FBB = LastInst->getOperand(0).getMBB();
220  return false;
221  }
222 
223  // If the block ends with two unconditional branches, handle it. The second
224  // one is not executed.
225  if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
226  TBB = SecondLastInst->getOperand(0).getMBB();
227  return false;
228  }
229 
230  // ...likewise if it ends with an indirect branch followed by an unconditional
231  // branch.
232  if (isIndirectBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
233  I = LastInst;
234  if (AllowModify)
235  I->eraseFromParent();
236  return true;
237  }
238 
239  // Otherwise, can't handle this.
240  return true;
241 }
242 
244  MachineBasicBlock *TBB,
245  MachineBasicBlock *FBB,
247  const DebugLoc &DL,
248  int *BytesAdded) const {
249  assert(TBB && "insertBranch must not be told to insert a fallthrough");
250  assert((Cond.size() == 1 || Cond.size() == 0) &&
251  "Sparc branch conditions should have one component!");
252  assert(!BytesAdded && "code size not handled");
253 
254  if (Cond.empty()) {
255  assert(!FBB && "Unconditional branch with multiple successors!");
256  BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
257  return 1;
258  }
259 
260  // Conditional branch
261  unsigned CC = Cond[0].getImm();
262 
263  if (IsIntegerCC(CC))
264  BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
265  else
266  BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
267  if (!FBB)
268  return 1;
269 
270  BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
271  return 2;
272 }
273 
275  int *BytesRemoved) const {
276  assert(!BytesRemoved && "code size not handled");
277 
279  unsigned Count = 0;
280  while (I != MBB.begin()) {
281  --I;
282 
283  if (I->isDebugValue())
284  continue;
285 
286  if (I->getOpcode() != SP::BA
287  && I->getOpcode() != SP::BCOND
288  && I->getOpcode() != SP::FBCOND)
289  break; // Not a branch
290 
291  I->eraseFromParent();
292  I = MBB.end();
293  ++Count;
294  }
295  return Count;
296 }
297 
299  SmallVectorImpl<MachineOperand> &Cond) const {
300  assert(Cond.size() == 1);
301  SPCC::CondCodes CC = static_cast<SPCC::CondCodes>(Cond[0].getImm());
302  Cond[0].setImm(GetOppositeBranchCondition(CC));
303  return false;
304 }
305 
308  const DebugLoc &DL, unsigned DestReg,
309  unsigned SrcReg, bool KillSrc) const {
310  unsigned numSubRegs = 0;
311  unsigned movOpc = 0;
312  const unsigned *subRegIdx = nullptr;
313  bool ExtraG0 = false;
314 
315  const unsigned DW_SubRegsIdx[] = { SP::sub_even, SP::sub_odd };
316  const unsigned DFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd };
317  const unsigned QFP_DFP_SubRegsIdx[] = { SP::sub_even64, SP::sub_odd64 };
318  const unsigned QFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd,
319  SP::sub_odd64_then_sub_even,
320  SP::sub_odd64_then_sub_odd };
321 
322  if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
323  BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
324  .addReg(SrcReg, getKillRegState(KillSrc));
325  else if (SP::IntPairRegClass.contains(DestReg, SrcReg)) {
326  subRegIdx = DW_SubRegsIdx;
327  numSubRegs = 2;
328  movOpc = SP::ORrr;
329  ExtraG0 = true;
330  } else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
331  BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
332  .addReg(SrcReg, getKillRegState(KillSrc));
333  else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) {
334  if (Subtarget.isV9()) {
335  BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg)
336  .addReg(SrcReg, getKillRegState(KillSrc));
337  } else {
338  // Use two FMOVS instructions.
339  subRegIdx = DFP_FP_SubRegsIdx;
340  numSubRegs = 2;
341  movOpc = SP::FMOVS;
342  }
343  } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) {
344  if (Subtarget.isV9()) {
345  if (Subtarget.hasHardQuad()) {
346  BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg)
347  .addReg(SrcReg, getKillRegState(KillSrc));
348  } else {
349  // Use two FMOVD instructions.
350  subRegIdx = QFP_DFP_SubRegsIdx;
351  numSubRegs = 2;
352  movOpc = SP::FMOVD;
353  }
354  } else {
355  // Use four FMOVS instructions.
356  subRegIdx = QFP_FP_SubRegsIdx;
357  numSubRegs = 4;
358  movOpc = SP::FMOVS;
359  }
360  } else if (SP::ASRRegsRegClass.contains(DestReg) &&
361  SP::IntRegsRegClass.contains(SrcReg)) {
362  BuildMI(MBB, I, DL, get(SP::WRASRrr), DestReg)
363  .addReg(SP::G0)
364  .addReg(SrcReg, getKillRegState(KillSrc));
365  } else if (SP::IntRegsRegClass.contains(DestReg) &&
366  SP::ASRRegsRegClass.contains(SrcReg)) {
367  BuildMI(MBB, I, DL, get(SP::RDASR), DestReg)
368  .addReg(SrcReg, getKillRegState(KillSrc));
369  } else
370  llvm_unreachable("Impossible reg-to-reg copy");
371 
372  if (numSubRegs == 0 || subRegIdx == nullptr || movOpc == 0)
373  return;
374 
375  const TargetRegisterInfo *TRI = &getRegisterInfo();
376  MachineInstr *MovMI = nullptr;
377 
378  for (unsigned i = 0; i != numSubRegs; ++i) {
379  unsigned Dst = TRI->getSubReg(DestReg, subRegIdx[i]);
380  unsigned Src = TRI->getSubReg(SrcReg, subRegIdx[i]);
381  assert(Dst && Src && "Bad sub-register");
382 
383  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(movOpc), Dst);
384  if (ExtraG0)
385  MIB.addReg(SP::G0);
386  MIB.addReg(Src);
387  MovMI = MIB.getInstr();
388  }
389  // Add implicit super-register defs and kills to the last MovMI.
390  MovMI->addRegisterDefined(DestReg, TRI);
391  if (KillSrc)
392  MovMI->addRegisterKilled(SrcReg, TRI);
393 }
394 
395 void SparcInstrInfo::
397  unsigned SrcReg, bool isKill, int FI,
398  const TargetRegisterClass *RC,
399  const TargetRegisterInfo *TRI) const {
400  DebugLoc DL;
401  if (I != MBB.end()) DL = I->getDebugLoc();
402 
403  MachineFunction *MF = MBB.getParent();
404  const MachineFrameInfo &MFI = MF->getFrameInfo();
407  MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
408 
409  // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
410  if (RC == &SP::I64RegsRegClass)
411  BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0)
412  .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
413  else if (RC == &SP::IntRegsRegClass)
414  BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
415  .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
416  else if (RC == &SP::IntPairRegClass)
417  BuildMI(MBB, I, DL, get(SP::STDri)).addFrameIndex(FI).addImm(0)
418  .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
419  else if (RC == &SP::FPRegsRegClass)
420  BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
421  .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
422  else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
423  BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
424  .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
425  else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
426  // Use STQFri irrespective of its legality. If STQ is not legal, it will be
427  // lowered into two STDs in eliminateFrameIndex.
428  BuildMI(MBB, I, DL, get(SP::STQFri)).addFrameIndex(FI).addImm(0)
429  .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
430  else
431  llvm_unreachable("Can't store this register to stack slot");
432 }
433 
434 void SparcInstrInfo::
436  unsigned DestReg, int FI,
437  const TargetRegisterClass *RC,
438  const TargetRegisterInfo *TRI) const {
439  DebugLoc DL;
440  if (I != MBB.end()) DL = I->getDebugLoc();
441 
442  MachineFunction *MF = MBB.getParent();
443  const MachineFrameInfo &MFI = MF->getFrameInfo();
446  MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
447 
448  if (RC == &SP::I64RegsRegClass)
449  BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0)
450  .addMemOperand(MMO);
451  else if (RC == &SP::IntRegsRegClass)
452  BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0)
453  .addMemOperand(MMO);
454  else if (RC == &SP::IntPairRegClass)
455  BuildMI(MBB, I, DL, get(SP::LDDri), DestReg).addFrameIndex(FI).addImm(0)
456  .addMemOperand(MMO);
457  else if (RC == &SP::FPRegsRegClass)
458  BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0)
459  .addMemOperand(MMO);
460  else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
461  BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0)
462  .addMemOperand(MMO);
463  else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
464  // Use LDQFri irrespective of its legality. If LDQ is not legal, it will be
465  // lowered into two LDDs in eliminateFrameIndex.
466  BuildMI(MBB, I, DL, get(SP::LDQFri), DestReg).addFrameIndex(FI).addImm(0)
467  .addMemOperand(MMO);
468  else
469  llvm_unreachable("Can't load this register from stack slot");
470 }
471 
473 {
475  unsigned GlobalBaseReg = SparcFI->getGlobalBaseReg();
476  if (GlobalBaseReg != 0)
477  return GlobalBaseReg;
478 
479  // Insert the set of GlobalBaseReg into the first MBB of the function
480  MachineBasicBlock &FirstMBB = MF->front();
481  MachineBasicBlock::iterator MBBI = FirstMBB.begin();
482  MachineRegisterInfo &RegInfo = MF->getRegInfo();
483 
484  const TargetRegisterClass *PtrRC =
485  Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
486  GlobalBaseReg = RegInfo.createVirtualRegister(PtrRC);
487 
488  DebugLoc dl;
489 
490  BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);
491  SparcFI->setGlobalBaseReg(GlobalBaseReg);
492  return GlobalBaseReg;
493 }
494 
496  switch (MI.getOpcode()) {
497  case TargetOpcode::LOAD_STACK_GUARD: {
498  assert(Subtarget.isTargetLinux() &&
499  "Only Linux target is expected to contain LOAD_STACK_GUARD");
500  // offsetof(tcbhead_t, stack_guard) from sysdeps/sparc/nptl/tls.h in glibc.
501  const int64_t Offset = Subtarget.is64Bit() ? 0x28 : 0x14;
502  MI.setDesc(get(Subtarget.is64Bit() ? SP::LDXri : SP::LDri));
504  .addReg(SP::G7)
505  .addImm(Offset);
506  return true;
507  }
508  }
509  return false;
510 }
MachineBasicBlock * getMBB() const
bool expandPostRAPseudo(MachineInstr &MI) const override
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
unsigned getReg() const
getReg - Returns the register number.
bool hasHardQuad() const
A debug info location.
Definition: DebugLoc.h:34
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
return AArch64::GPR64RegClass contains(Reg)
GlobalBaseReg - On Darwin, this node represents the result of the mflr at function entry...
bool isTargetLinux() const
A description of a memory reference used in the backend.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
static bool IsIntegerCC(unsigned CC)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
unsigned getKillRegState(bool B)
static bool isCondBranchOpcode(int Opc)
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
unsigned getGlobalBaseReg(MachineFunction *MF) const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target, SmallVectorImpl< MachineOperand > &Cond)
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const SparcRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
const MachineInstrBuilder & addFrameIndex(int Idx) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MachineBasicBlock & front() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
The memory access writes data.
static bool isIndirectBranchOpcode(int Opc)
static bool isUncondBranchOpcode(int Opc)
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot...
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly. ...
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
int64_t getImm() const
void addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
Target - Wrapper for Target specific information.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Representation of each machine instruction.
Definition: MachineInstr.h:59
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
CondCodes
Definition: Sparc.h:42
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
SparcInstrInfo(SparcSubtarget &ST)
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:58
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:235
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
IRTranslator LLVM IR MI
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot...
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:144