LLVM  6.0.0svn
RegBankSelect.cpp
Go to the documentation of this file.
1 //==- llvm/CodeGen/GlobalISel/RegBankSelect.cpp - RegBankSelect --*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the RegBankSelect class.
11 //===----------------------------------------------------------------------===//
12 
15 #include "llvm/ADT/STLExtras.h"
16 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/IR/Attributes.h"
34 #include "llvm/IR/Function.h"
35 #include "llvm/Pass.h"
38 #include "llvm/Support/Compiler.h"
39 #include "llvm/Support/Debug.h"
42 #include <algorithm>
43 #include <cassert>
44 #include <cstdint>
45 #include <limits>
46 #include <memory>
47 #include <utility>
48 
49 #define DEBUG_TYPE "regbankselect"
50 
51 using namespace llvm;
52 
54  cl::desc("Mode of the RegBankSelect pass"), cl::Hidden, cl::Optional,
55  cl::values(clEnumValN(RegBankSelect::Mode::Fast, "regbankselect-fast",
56  "Run the Fast mode (default mapping)"),
57  clEnumValN(RegBankSelect::Mode::Greedy, "regbankselect-greedy",
58  "Use the Greedy mode (best local mapping)")));
59 
60 char RegBankSelect::ID = 0;
61 
63  "Assign register bank of generic virtual registers",
64  false, false);
69  "Assign register bank of generic virtual registers", false,
70  false)
71 
72 RegBankSelect::RegBankSelect(Mode RunningMode)
73  : MachineFunctionPass(ID), OptMode(RunningMode) {
75  if (RegBankSelectMode.getNumOccurrences() != 0) {
76  OptMode = RegBankSelectMode;
77  if (RegBankSelectMode != RunningMode)
78  DEBUG(dbgs() << "RegBankSelect mode overrided by command line\n");
79  }
80 }
81 
82 void RegBankSelect::init(MachineFunction &MF) {
83  RBI = MF.getSubtarget().getRegBankInfo();
84  assert(RBI && "Cannot work without RegisterBankInfo");
85  MRI = &MF.getRegInfo();
86  TRI = MF.getSubtarget().getRegisterInfo();
87  TPC = &getAnalysis<TargetPassConfig>();
88  if (OptMode != Mode::Fast) {
89  MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
90  MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
91  } else {
92  MBFI = nullptr;
93  MBPI = nullptr;
94  }
95  MIRBuilder.setMF(MF);
96  MORE = llvm::make_unique<MachineOptimizationRemarkEmitter>(MF, MBFI);
97 }
98 
100  if (OptMode != Mode::Fast) {
101  // We could preserve the information from these two analysis but
102  // the APIs do not allow to do so yet.
105  }
108 }
109 
110 bool RegBankSelect::assignmentMatch(
111  unsigned Reg, const RegisterBankInfo::ValueMapping &ValMapping,
112  bool &OnlyAssign) const {
113  // By default we assume we will have to repair something.
114  OnlyAssign = false;
115  // Each part of a break down needs to end up in a different register.
116  // In other word, Reg assignement does not match.
117  if (ValMapping.NumBreakDowns > 1)
118  return false;
119 
120  const RegisterBank *CurRegBank = RBI->getRegBank(Reg, *MRI, *TRI);
121  const RegisterBank *DesiredRegBrank = ValMapping.BreakDown[0].RegBank;
122  // Reg is free of assignment, a simple assignment will make the
123  // register bank to match.
124  OnlyAssign = CurRegBank == nullptr;
125  DEBUG(dbgs() << "Does assignment already match: ";
126  if (CurRegBank) dbgs() << *CurRegBank; else dbgs() << "none";
127  dbgs() << " against ";
128  assert(DesiredRegBrank && "The mapping must be valid");
129  dbgs() << *DesiredRegBrank << '\n';);
130  return CurRegBank == DesiredRegBrank;
131 }
132 
133 bool RegBankSelect::repairReg(
134  MachineOperand &MO, const RegisterBankInfo::ValueMapping &ValMapping,
137  if (ValMapping.NumBreakDowns != 1 && !TPC->isGlobalISelAbortEnabled())
138  return false;
139  assert(ValMapping.NumBreakDowns == 1 && "Not yet implemented");
140  // An empty range of new register means no repairing.
141  assert(NewVRegs.begin() != NewVRegs.end() && "We should not have to repair");
142 
143  // Assume we are repairing a use and thus, the original reg will be
144  // the source of the repairing.
145  unsigned Src = MO.getReg();
146  unsigned Dst = *NewVRegs.begin();
147 
148  // If we repair a definition, swap the source and destination for
149  // the repairing.
150  if (MO.isDef())
151  std::swap(Src, Dst);
152 
153  assert((RepairPt.getNumInsertPoints() == 1 ||
155  "We are about to create several defs for Dst");
156 
157  // Build the instruction used to repair, then clone it at the right
158  // places. Avoiding buildCopy bypasses the check that Src and Dst have the
159  // same types because the type is a placeholder when this function is called.
160  MachineInstr *MI =
161  MIRBuilder.buildInstrNoInsert(TargetOpcode::COPY).addDef(Dst).addUse(Src);
162  DEBUG(dbgs() << "Copy: " << PrintReg(Src) << " to: " << PrintReg(Dst)
163  << '\n');
164  // TODO:
165  // Check if MI is legal. if not, we need to legalize all the
166  // instructions we are going to insert.
167  std::unique_ptr<MachineInstr *[]> NewInstrs(
168  new MachineInstr *[RepairPt.getNumInsertPoints()]);
169  bool IsFirst = true;
170  unsigned Idx = 0;
171  for (const std::unique_ptr<InsertPoint> &InsertPt : RepairPt) {
172  MachineInstr *CurMI;
173  if (IsFirst)
174  CurMI = MI;
175  else
176  CurMI = MIRBuilder.getMF().CloneMachineInstr(MI);
177  InsertPt->insert(*CurMI);
178  NewInstrs[Idx++] = CurMI;
179  IsFirst = false;
180  }
181  // TODO:
182  // Legalize NewInstrs if need be.
183  return true;
184 }
185 
186 uint64_t RegBankSelect::getRepairCost(
187  const MachineOperand &MO,
188  const RegisterBankInfo::ValueMapping &ValMapping) const {
189  assert(MO.isReg() && "We should only repair register operand");
190  assert(ValMapping.NumBreakDowns && "Nothing to map??");
191 
192  bool IsSameNumOfValues = ValMapping.NumBreakDowns == 1;
193  const RegisterBank *CurRegBank = RBI->getRegBank(MO.getReg(), *MRI, *TRI);
194  // If MO does not have a register bank, we should have just been
195  // able to set one unless we have to break the value down.
196  assert((!IsSameNumOfValues || CurRegBank) && "We should not have to repair");
197  // Def: Val <- NewDefs
198  // Same number of values: copy
199  // Different number: Val = build_sequence Defs1, Defs2, ...
200  // Use: NewSources <- Val.
201  // Same number of values: copy.
202  // Different number: Src1, Src2, ... =
203  // extract_value Val, Src1Begin, Src1Len, Src2Begin, Src2Len, ...
204  // We should remember that this value is available somewhere else to
205  // coalesce the value.
206 
207  if (IsSameNumOfValues) {
208  const RegisterBank *DesiredRegBrank = ValMapping.BreakDown[0].RegBank;
209  // If we repair a definition, swap the source and destination for
210  // the repairing.
211  if (MO.isDef())
212  std::swap(CurRegBank, DesiredRegBrank);
213  // TODO: It may be possible to actually avoid the copy.
214  // If we repair something where the source is defined by a copy
215  // and the source of that copy is on the right bank, we can reuse
216  // it for free.
217  // E.g.,
218  // RegToRepair<BankA> = copy AlternativeSrc<BankB>
219  // = op RegToRepair<BankA>
220  // We can simply propagate AlternativeSrc instead of copying RegToRepair
221  // into a new virtual register.
222  // We would also need to propagate this information in the
223  // repairing placement.
224  unsigned Cost = RBI->copyCost(*DesiredRegBrank, *CurRegBank,
225  RBI->getSizeInBits(MO.getReg(), *MRI, *TRI));
226  // TODO: use a dedicated constant for ImpossibleCost.
228  return Cost;
229  // Return the legalization cost of that repairing.
230  }
232 }
233 
234 const RegisterBankInfo::InstructionMapping &RegBankSelect::findBestMapping(
237  assert(!PossibleMappings.empty() &&
238  "Do not know how to map this instruction");
239 
240  const RegisterBankInfo::InstructionMapping *BestMapping = nullptr;
241  MappingCost Cost = MappingCost::ImpossibleCost();
242  SmallVector<RepairingPlacement, 4> LocalRepairPts;
243  for (const RegisterBankInfo::InstructionMapping *CurMapping :
244  PossibleMappings) {
245  MappingCost CurCost =
246  computeMapping(MI, *CurMapping, LocalRepairPts, &Cost);
247  if (CurCost < Cost) {
248  DEBUG(dbgs() << "New best: " << CurCost << '\n');
249  Cost = CurCost;
250  BestMapping = CurMapping;
251  RepairPts.clear();
252  for (RepairingPlacement &RepairPt : LocalRepairPts)
253  RepairPts.emplace_back(std::move(RepairPt));
254  }
255  }
256  if (!BestMapping && !TPC->isGlobalISelAbortEnabled()) {
257  // If none of the mapping worked that means they are all impossible.
258  // Thus, pick the first one and set an impossible repairing point.
259  // It will trigger the failed isel mode.
260  BestMapping = *PossibleMappings.begin();
261  RepairPts.emplace_back(
263  } else
264  assert(BestMapping && "No suitable mapping for instruction");
265  return *BestMapping;
266 }
267 
268 void RegBankSelect::tryAvoidingSplit(
270  const RegisterBankInfo::ValueMapping &ValMapping) const {
271  const MachineInstr &MI = *MO.getParent();
272  assert(RepairPt.hasSplit() && "We should not have to adjust for split");
273  // Splitting should only occur for PHIs or between terminators,
274  // because we only do local repairing.
275  assert((MI.isPHI() || MI.isTerminator()) && "Why do we split?");
276 
277  assert(&MI.getOperand(RepairPt.getOpIdx()) == &MO &&
278  "Repairing placement does not match operand");
279 
280  // If we need splitting for phis, that means it is because we
281  // could not find an insertion point before the terminators of
282  // the predecessor block for this argument. In other words,
283  // the input value is defined by one of the terminators.
284  assert((!MI.isPHI() || !MO.isDef()) && "Need split for phi def?");
285 
286  // We split to repair the use of a phi or a terminator.
287  if (!MO.isDef()) {
288  if (MI.isTerminator()) {
289  assert(&MI != &(*MI.getParent()->getFirstTerminator()) &&
290  "Need to split for the first terminator?!");
291  } else {
292  // For the PHI case, the split may not be actually required.
293  // In the copy case, a phi is already a copy on the incoming edge,
294  // therefore there is no need to split.
295  if (ValMapping.NumBreakDowns == 1)
296  // This is a already a copy, there is nothing to do.
297  RepairPt.switchTo(RepairingPlacement::RepairingKind::Reassign);
298  }
299  return;
300  }
301 
302  // At this point, we need to repair a defintion of a terminator.
303 
304  // Technically we need to fix the def of MI on all outgoing
305  // edges of MI to keep the repairing local. In other words, we
306  // will create several definitions of the same register. This
307  // does not work for SSA unless that definition is a physical
308  // register.
309  // However, there are other cases where we can get away with
310  // that while still keeping the repairing local.
311  assert(MI.isTerminator() && MO.isDef() &&
312  "This code is for the def of a terminator");
313 
314  // Since we use RPO traversal, if we need to repair a definition
315  // this means this definition could be:
316  // 1. Used by PHIs (i.e., this VReg has been visited as part of the
317  // uses of a phi.), or
318  // 2. Part of a target specific instruction (i.e., the target applied
319  // some register class constraints when creating the instruction.)
320  // If the constraints come for #2, the target said that another mapping
321  // is supported so we may just drop them. Indeed, if we do not change
322  // the number of registers holding that value, the uses will get fixed
323  // when we get to them.
324  // Uses in PHIs may have already been proceeded though.
325  // If the constraints come for #1, then, those are weak constraints and
326  // no actual uses may rely on them. However, the problem remains mainly
327  // the same as for #2. If the value stays in one register, we could
328  // just switch the register bank of the definition, but we would need to
329  // account for a repairing cost for each phi we silently change.
330  //
331  // In any case, if the value needs to be broken down into several
332  // registers, the repairing is not local anymore as we need to patch
333  // every uses to rebuild the value in just one register.
334  //
335  // To summarize:
336  // - If the value is in a physical register, we can do the split and
337  // fix locally.
338  // Otherwise if the value is in a virtual register:
339  // - If the value remains in one register, we do not have to split
340  // just switching the register bank would do, but we need to account
341  // in the repairing cost all the phi we changed.
342  // - If the value spans several registers, then we cannot do a local
343  // repairing.
344 
345  // Check if this is a physical or virtual register.
346  unsigned Reg = MO.getReg();
348  // We are going to split every outgoing edges.
349  // Check that this is possible.
350  // FIXME: The machine representation is currently broken
351  // since it also several terminators in one basic block.
352  // Because of that we would technically need a way to get
353  // the targets of just one terminator to know which edges
354  // we have to split.
355  // Assert that we do not hit the ill-formed representation.
356 
357  // If there are other terminators before that one, some of
358  // the outgoing edges may not be dominated by this definition.
359  assert(&MI == &(*MI.getParent()->getFirstTerminator()) &&
360  "Do not know which outgoing edges are relevant");
361  const MachineInstr *Next = MI.getNextNode();
362  assert((!Next || Next->isUnconditionalBranch()) &&
363  "Do not know where each terminator ends up");
364  if (Next)
365  // If the next terminator uses Reg, this means we have
366  // to split right after MI and thus we need a way to ask
367  // which outgoing edges are affected.
368  assert(!Next->readsRegister(Reg) && "Need to split between terminators");
369  // We will split all the edges and repair there.
370  } else {
371  // This is a virtual register defined by a terminator.
372  if (ValMapping.NumBreakDowns == 1) {
373  // There is nothing to repair, but we may actually lie on
374  // the repairing cost because of the PHIs already proceeded
375  // as already stated.
376  // Though the code will be correct.
377  assert(false && "Repairing cost may not be accurate");
378  } else {
379  // We need to do non-local repairing. Basically, patch all
380  // the uses (i.e., phis) that we already proceeded.
381  // For now, just say this mapping is not possible.
382  RepairPt.switchTo(RepairingPlacement::RepairingKind::Impossible);
383  }
384  }
385 }
386 
387 RegBankSelect::MappingCost RegBankSelect::computeMapping(
388  MachineInstr &MI, const RegisterBankInfo::InstructionMapping &InstrMapping,
390  const RegBankSelect::MappingCost *BestCost) {
391  assert((MBFI || !BestCost) && "Costs comparison require MBFI");
392 
393  if (!InstrMapping.isValid())
394  return MappingCost::ImpossibleCost();
395 
396  // If mapped with InstrMapping, MI will have the recorded cost.
397  MappingCost Cost(MBFI ? MBFI->getBlockFreq(MI.getParent()) : 1);
398  bool Saturated = Cost.addLocalCost(InstrMapping.getCost());
399  assert(!Saturated && "Possible mapping saturated the cost");
400  DEBUG(dbgs() << "Evaluating mapping cost for: " << MI);
401  DEBUG(dbgs() << "With: " << InstrMapping << '\n');
402  RepairPts.clear();
403  if (BestCost && Cost > *BestCost) {
404  DEBUG(dbgs() << "Mapping is too expensive from the start\n");
405  return Cost;
406  }
407 
408  // Moreover, to realize this mapping, the register bank of each operand must
409  // match this mapping. In other words, we may need to locally reassign the
410  // register banks. Account for that repairing cost as well.
411  // In this context, local means in the surrounding of MI.
412  for (unsigned OpIdx = 0, EndOpIdx = InstrMapping.getNumOperands();
413  OpIdx != EndOpIdx; ++OpIdx) {
414  const MachineOperand &MO = MI.getOperand(OpIdx);
415  if (!MO.isReg())
416  continue;
417  unsigned Reg = MO.getReg();
418  if (!Reg)
419  continue;
420  DEBUG(dbgs() << "Opd" << OpIdx << '\n');
421  const RegisterBankInfo::ValueMapping &ValMapping =
422  InstrMapping.getOperandMapping(OpIdx);
423  // If Reg is already properly mapped, this is free.
424  bool Assign;
425  if (assignmentMatch(Reg, ValMapping, Assign)) {
426  DEBUG(dbgs() << "=> is free (match).\n");
427  continue;
428  }
429  if (Assign) {
430  DEBUG(dbgs() << "=> is free (simple assignment).\n");
431  RepairPts.emplace_back(RepairingPlacement(MI, OpIdx, *TRI, *this,
433  continue;
434  }
435 
436  // Find the insertion point for the repairing code.
437  RepairPts.emplace_back(
438  RepairingPlacement(MI, OpIdx, *TRI, *this, RepairingPlacement::Insert));
439  RepairingPlacement &RepairPt = RepairPts.back();
440 
441  // If we need to split a basic block to materialize this insertion point,
442  // we may give a higher cost to this mapping.
443  // Nevertheless, we may get away with the split, so try that first.
444  if (RepairPt.hasSplit())
445  tryAvoidingSplit(RepairPt, MO, ValMapping);
446 
447  // Check that the materialization of the repairing is possible.
448  if (!RepairPt.canMaterialize()) {
449  DEBUG(dbgs() << "Mapping involves impossible repairing\n");
450  return MappingCost::ImpossibleCost();
451  }
452 
453  // Account for the split cost and repair cost.
454  // Unless the cost is already saturated or we do not care about the cost.
455  if (!BestCost || Saturated)
456  continue;
457 
458  // To get accurate information we need MBFI and MBPI.
459  // Thus, if we end up here this information should be here.
460  assert(MBFI && MBPI && "Cost computation requires MBFI and MBPI");
461 
462  // FIXME: We will have to rework the repairing cost model.
463  // The repairing cost depends on the register bank that MO has.
464  // However, when we break down the value into different values,
465  // MO may not have a register bank while still needing repairing.
466  // For the fast mode, we don't compute the cost so that is fine,
467  // but still for the repairing code, we will have to make a choice.
468  // For the greedy mode, we should choose greedily what is the best
469  // choice based on the next use of MO.
470 
471  // Sums up the repairing cost of MO at each insertion point.
472  uint64_t RepairCost = getRepairCost(MO, ValMapping);
473 
474  // This is an impossible to repair cost.
475  if (RepairCost == std::numeric_limits<unsigned>::max())
476  continue;
477 
478  // Bias used for splitting: 5%.
479  const uint64_t PercentageForBias = 5;
480  uint64_t Bias = (RepairCost * PercentageForBias + 99) / 100;
481  // We should not need more than a couple of instructions to repair
482  // an assignment. In other words, the computation should not
483  // overflow because the repairing cost is free of basic block
484  // frequency.
485  assert(((RepairCost < RepairCost * PercentageForBias) &&
486  (RepairCost * PercentageForBias <
487  RepairCost * PercentageForBias + 99)) &&
488  "Repairing involves more than a billion of instructions?!");
489  for (const std::unique_ptr<InsertPoint> &InsertPt : RepairPt) {
490  assert(InsertPt->canMaterialize() && "We should not have made it here");
491  // We will applied some basic block frequency and those uses uint64_t.
492  if (!InsertPt->isSplit())
493  Saturated = Cost.addLocalCost(RepairCost);
494  else {
495  uint64_t CostForInsertPt = RepairCost;
496  // Again we shouldn't overflow here givent that
497  // CostForInsertPt is frequency free at this point.
498  assert(CostForInsertPt + Bias > CostForInsertPt &&
499  "Repairing + split bias overflows");
500  CostForInsertPt += Bias;
501  uint64_t PtCost = InsertPt->frequency(*this) * CostForInsertPt;
502  // Check if we just overflowed.
503  if ((Saturated = PtCost < CostForInsertPt))
504  Cost.saturate();
505  else
506  Saturated = Cost.addNonLocalCost(PtCost);
507  }
508 
509  // Stop looking into what it takes to repair, this is already
510  // too expensive.
511  if (BestCost && Cost > *BestCost) {
512  DEBUG(dbgs() << "Mapping is too expensive, stop processing\n");
513  return Cost;
514  }
515 
516  // No need to accumulate more cost information.
517  // We need to still gather the repairing information though.
518  if (Saturated)
519  break;
520  }
521  }
522  DEBUG(dbgs() << "Total cost is: " << Cost << "\n");
523  return Cost;
524 }
525 
526 bool RegBankSelect::applyMapping(
527  MachineInstr &MI, const RegisterBankInfo::InstructionMapping &InstrMapping,
529  // OpdMapper will hold all the information needed for the rewritting.
530  RegisterBankInfo::OperandsMapper OpdMapper(MI, InstrMapping, *MRI);
531 
532  // First, place the repairing code.
533  for (RepairingPlacement &RepairPt : RepairPts) {
534  if (!RepairPt.canMaterialize() ||
536  return false;
537  assert(RepairPt.getKind() != RepairingPlacement::None &&
538  "This should not make its way in the list");
539  unsigned OpIdx = RepairPt.getOpIdx();
540  MachineOperand &MO = MI.getOperand(OpIdx);
541  const RegisterBankInfo::ValueMapping &ValMapping =
542  InstrMapping.getOperandMapping(OpIdx);
543  unsigned Reg = MO.getReg();
544 
545  switch (RepairPt.getKind()) {
547  assert(ValMapping.NumBreakDowns == 1 &&
548  "Reassignment should only be for simple mapping");
549  MRI->setRegBank(Reg, *ValMapping.BreakDown[0].RegBank);
550  break;
552  OpdMapper.createVRegs(OpIdx);
553  if (!repairReg(MO, ValMapping, RepairPt, OpdMapper.getVRegs(OpIdx)))
554  return false;
555  break;
556  default:
557  llvm_unreachable("Other kind should not happen");
558  }
559  }
560 
561  // Second, rewrite the instruction.
562  DEBUG(dbgs() << "Actual mapping of the operands: " << OpdMapper << '\n');
563  RBI->applyMapping(OpdMapper);
564 
565  return true;
566 }
567 
568 bool RegBankSelect::assignInstr(MachineInstr &MI) {
569  DEBUG(dbgs() << "Assign: " << MI);
570  // Remember the repairing placement for all the operands.
572 
573  const RegisterBankInfo::InstructionMapping *BestMapping;
574  if (OptMode == RegBankSelect::Mode::Fast) {
575  BestMapping = &RBI->getInstrMapping(MI);
576  MappingCost DefaultCost = computeMapping(MI, *BestMapping, RepairPts);
577  (void)DefaultCost;
578  if (DefaultCost == MappingCost::ImpossibleCost())
579  return false;
580  } else {
581  RegisterBankInfo::InstructionMappings PossibleMappings =
582  RBI->getInstrPossibleMappings(MI);
583  if (PossibleMappings.empty())
584  return false;
585  BestMapping = &findBestMapping(MI, PossibleMappings, RepairPts);
586  }
587  // Make sure the mapping is valid for MI.
588  assert(BestMapping->verify(MI) && "Invalid instruction mapping");
589 
590  DEBUG(dbgs() << "Best Mapping: " << *BestMapping << '\n');
591 
592  // After this call, MI may not be valid anymore.
593  // Do not use it.
594  return applyMapping(MI, *BestMapping, RepairPts);
595 }
596 
598  // If the ISel pipeline failed, do not bother running that pass.
599  if (MF.getProperties().hasProperty(
601  return false;
602 
603  DEBUG(dbgs() << "Assign register banks for: " << MF.getName() << '\n');
604  const Function *F = MF.getFunction();
605  Mode SaveOptMode = OptMode;
606  if (F->hasFnAttribute(Attribute::OptimizeNone))
607  OptMode = Mode::Fast;
608  init(MF);
609 
610 #ifndef NDEBUG
611  // Check that our input is fully legal: we require the function to have the
612  // Legalized property, so it should be.
613  // FIXME: This should be in the MachineVerifier, but it can't use the
614  // LegalizerInfo as it's currently in the separate GlobalISel library.
615  const MachineRegisterInfo &MRI = MF.getRegInfo();
616  if (const LegalizerInfo *MLI = MF.getSubtarget().getLegalizerInfo()) {
617  for (MachineBasicBlock &MBB : MF) {
618  for (MachineInstr &MI : MBB) {
619  if (isPreISelGenericOpcode(MI.getOpcode()) && !MLI->isLegal(MI, MRI)) {
620  reportGISelFailure(MF, *TPC, *MORE, "gisel-regbankselect",
621  "instruction is not legal", MI);
622  return false;
623  }
624  }
625  }
626  }
627 #endif
628 
629  // Walk the function and assign register banks to all operands.
630  // Use a RPOT to make sure all registers are assigned before we choose
631  // the best mapping of the current instruction.
633  for (MachineBasicBlock *MBB : RPOT) {
634  // Set a sensible insertion point so that subsequent calls to
635  // MIRBuilder.
636  MIRBuilder.setMBB(*MBB);
637  for (MachineBasicBlock::iterator MII = MBB->begin(), End = MBB->end();
638  MII != End;) {
639  // MI might be invalidated by the assignment, so move the
640  // iterator before hand.
641  MachineInstr &MI = *MII++;
642 
643  // Ignore target-specific instructions: they should use proper regclasses.
645  continue;
646 
647  if (!assignInstr(MI)) {
648  reportGISelFailure(MF, *TPC, *MORE, "gisel-regbankselect",
649  "unable to map instruction", MI);
650  return false;
651  }
652  }
653  }
654  OptMode = SaveOptMode;
655  return false;
656 }
657 
658 //------------------------------------------------------------------------------
659 // Helper Classes Implementation
660 //------------------------------------------------------------------------------
662  MachineInstr &MI, unsigned OpIdx, const TargetRegisterInfo &TRI, Pass &P,
664  // Default is, we are going to insert code to repair OpIdx.
665  : Kind(Kind), OpIdx(OpIdx),
666  CanMaterialize(Kind != RepairingKind::Impossible), P(P) {
667  const MachineOperand &MO = MI.getOperand(OpIdx);
668  assert(MO.isReg() && "Trying to repair a non-reg operand");
669 
670  if (Kind != RepairingKind::Insert)
671  return;
672 
673  // Repairings for definitions happen after MI, uses happen before.
674  bool Before = !MO.isDef();
675 
676  // Check if we are done with MI.
677  if (!MI.isPHI() && !MI.isTerminator()) {
678  addInsertPoint(MI, Before);
679  // We are done with the initialization.
680  return;
681  }
682 
683  // Now, look for the special cases.
684  if (MI.isPHI()) {
685  // - PHI must be the first instructions:
686  // * Before, we have to split the related incoming edge.
687  // * After, move the insertion point past the last phi.
688  if (!Before) {
690  if (It != MI.getParent()->end())
691  addInsertPoint(*It, /*Before*/ true);
692  else
693  addInsertPoint(*(--It), /*Before*/ false);
694  return;
695  }
696  // We repair a use of a phi, we may need to split the related edge.
697  MachineBasicBlock &Pred = *MI.getOperand(OpIdx + 1).getMBB();
698  // Check if we can move the insertion point prior to the
699  // terminators of the predecessor.
700  unsigned Reg = MO.getReg();
702  for (auto Begin = Pred.begin(); It != Begin && It->isTerminator(); --It)
703  if (It->modifiesRegister(Reg, &TRI)) {
704  // We cannot hoist the repairing code in the predecessor.
705  // Split the edge.
706  addInsertPoint(Pred, *MI.getParent());
707  return;
708  }
709  // At this point, we can insert in Pred.
710 
711  // - If It is invalid, Pred is empty and we can insert in Pred
712  // wherever we want.
713  // - If It is valid, It is the first non-terminator, insert after It.
714  if (It == Pred.end())
715  addInsertPoint(Pred, /*Beginning*/ false);
716  else
717  addInsertPoint(*It, /*Before*/ false);
718  } else {
719  // - Terminators must be the last instructions:
720  // * Before, move the insert point before the first terminator.
721  // * After, we have to split the outcoming edges.
722  unsigned Reg = MO.getReg();
723  if (Before) {
724  // Check whether Reg is defined by any terminator.
726  for (auto Begin = MI.getParent()->begin();
727  --It != Begin && It->isTerminator();)
728  if (It->modifiesRegister(Reg, &TRI)) {
729  // Insert the repairing code right after the definition.
730  addInsertPoint(*It, /*Before*/ false);
731  return;
732  }
733  addInsertPoint(*It, /*Before*/ true);
734  return;
735  }
736  // Make sure Reg is not redefined by other terminators, otherwise
737  // we do not know how to split.
738  for (MachineBasicBlock::iterator It = MI, End = MI.getParent()->end();
739  ++It != End;)
740  // The machine verifier should reject this kind of code.
741  assert(It->modifiesRegister(Reg, &TRI) && "Do not know where to split");
742  // Split each outcoming edges.
743  MachineBasicBlock &Src = *MI.getParent();
744  for (auto &Succ : Src.successors())
745  addInsertPoint(Src, Succ);
746  }
747 }
748 
750  bool Before) {
751  addInsertPoint(*new InstrInsertPoint(MI, Before));
752 }
753 
755  bool Beginning) {
756  addInsertPoint(*new MBBInsertPoint(MBB, Beginning));
757 }
758 
760  MachineBasicBlock &Dst) {
761  addInsertPoint(*new EdgeInsertPoint(Src, Dst, P));
762 }
763 
766  CanMaterialize &= Point.canMaterialize();
767  HasSplit |= Point.isSplit();
768  InsertPoints.emplace_back(&Point);
769 }
770 
772  bool Before)
773  : InsertPoint(), Instr(Instr), Before(Before) {
774  // Since we do not support splitting, we do not need to update
775  // liveness and such, so do not do anything with P.
776  assert((!Before || !Instr.isPHI()) &&
777  "Splitting before phis requires more points");
778  assert((!Before || !Instr.getNextNode() || !Instr.getNextNode()->isPHI()) &&
779  "Splitting between phis does not make sense");
780 }
781 
782 void RegBankSelect::InstrInsertPoint::materialize() {
783  if (isSplit()) {
784  // Slice and return the beginning of the new block.
785  // If we need to split between the terminators, we theoritically
786  // need to know where the first and second set of terminators end
787  // to update the successors properly.
788  // Now, in pratice, we should have a maximum of 2 branch
789  // instructions; one conditional and one unconditional. Therefore
790  // we know how to update the successor by looking at the target of
791  // the unconditional branch.
792  // If we end up splitting at some point, then, we should update
793  // the liveness information and such. I.e., we would need to
794  // access P here.
795  // The machine verifier should actually make sure such cases
796  // cannot happen.
797  llvm_unreachable("Not yet implemented");
798  }
799  // Otherwise the insertion point is just the current or next
800  // instruction depending on Before. I.e., there is nothing to do
801  // here.
802 }
803 
805  // If the insertion point is after a terminator, we need to split.
806  if (!Before)
807  return Instr.isTerminator();
808  // If we insert before an instruction that is after a terminator,
809  // we are still after a terminator.
810  return Instr.getPrevNode() && Instr.getPrevNode()->isTerminator();
811 }
812 
814  // Even if we need to split, because we insert between terminators,
815  // this split has actually the same frequency as the instruction.
816  const MachineBlockFrequencyInfo *MBFI =
818  if (!MBFI)
819  return 1;
820  return MBFI->getBlockFreq(Instr.getParent()).getFrequency();
821 }
822 
824  const MachineBlockFrequencyInfo *MBFI =
826  if (!MBFI)
827  return 1;
828  return MBFI->getBlockFreq(&MBB).getFrequency();
829 }
830 
831 void RegBankSelect::EdgeInsertPoint::materialize() {
832  // If we end up repairing twice at the same place before materializing the
833  // insertion point, we may think we have to split an edge twice.
834  // We should have a factory for the insert point such that identical points
835  // are the same instance.
836  assert(Src.isSuccessor(DstOrSplit) && DstOrSplit->isPredecessor(&Src) &&
837  "This point has already been split");
838  MachineBasicBlock *NewBB = Src.SplitCriticalEdge(DstOrSplit, P);
839  assert(NewBB && "Invalid call to materialize");
840  // We reuse the destination block to hold the information of the new block.
841  DstOrSplit = NewBB;
842 }
843 
845  const MachineBlockFrequencyInfo *MBFI =
847  if (!MBFI)
848  return 1;
849  if (WasMaterialized)
850  return MBFI->getBlockFreq(DstOrSplit).getFrequency();
851 
852  const MachineBranchProbabilityInfo *MBPI =
854  if (!MBPI)
855  return 1;
856  // The basic block will be on the edge.
857  return (MBFI->getBlockFreq(&Src) * MBPI->getEdgeProbability(&Src, DstOrSplit))
858  .getFrequency();
859 }
860 
862  // If this is not a critical edge, we should not have used this insert
863  // point. Indeed, either the successor or the predecessor should
864  // have do.
865  assert(Src.succ_size() > 1 && DstOrSplit->pred_size() > 1 &&
866  "Edge is not critical");
867  return Src.canSplitCriticalEdge(DstOrSplit);
868 }
869 
870 RegBankSelect::MappingCost::MappingCost(const BlockFrequency &LocalFreq)
871  : LocalFreq(LocalFreq.getFrequency()) {}
872 
873 bool RegBankSelect::MappingCost::addLocalCost(uint64_t Cost) {
874  // Check if this overflows.
875  if (LocalCost + Cost < LocalCost) {
876  saturate();
877  return true;
878  }
879  LocalCost += Cost;
880  return isSaturated();
881 }
882 
883 bool RegBankSelect::MappingCost::addNonLocalCost(uint64_t Cost) {
884  // Check if this overflows.
885  if (NonLocalCost + Cost < NonLocalCost) {
886  saturate();
887  return true;
888  }
889  NonLocalCost += Cost;
890  return isSaturated();
891 }
892 
893 bool RegBankSelect::MappingCost::isSaturated() const {
894  return LocalCost == UINT64_MAX - 1 && NonLocalCost == UINT64_MAX &&
895  LocalFreq == UINT64_MAX;
896 }
897 
898 void RegBankSelect::MappingCost::saturate() {
899  *this = ImpossibleCost();
900  --LocalCost;
901 }
902 
903 RegBankSelect::MappingCost RegBankSelect::MappingCost::ImpossibleCost() {
904  return MappingCost(UINT64_MAX, UINT64_MAX, UINT64_MAX);
905 }
906 
907 bool RegBankSelect::MappingCost::operator<(const MappingCost &Cost) const {
908  // Sort out the easy cases.
909  if (*this == Cost)
910  return false;
911  // If one is impossible to realize the other is cheaper unless it is
912  // impossible as well.
913  if ((*this == ImpossibleCost()) || (Cost == ImpossibleCost()))
914  return (*this == ImpossibleCost()) < (Cost == ImpossibleCost());
915  // If one is saturated the other is cheaper, unless it is saturated
916  // as well.
917  if (isSaturated() || Cost.isSaturated())
918  return isSaturated() < Cost.isSaturated();
919  // At this point we know both costs hold sensible values.
920 
921  // If both values have a different base frequency, there is no much
922  // we can do but to scale everything.
923  // However, if they have the same base frequency we can avoid making
924  // complicated computation.
925  uint64_t ThisLocalAdjust;
926  uint64_t OtherLocalAdjust;
927  if (LLVM_LIKELY(LocalFreq == Cost.LocalFreq)) {
928 
929  // At this point, we know the local costs are comparable.
930  // Do the case that do not involve potential overflow first.
931  if (NonLocalCost == Cost.NonLocalCost)
932  // Since the non-local costs do not discriminate on the result,
933  // just compare the local costs.
934  return LocalCost < Cost.LocalCost;
935 
936  // The base costs are comparable so we may only keep the relative
937  // value to increase our chances of avoiding overflows.
938  ThisLocalAdjust = 0;
939  OtherLocalAdjust = 0;
940  if (LocalCost < Cost.LocalCost)
941  OtherLocalAdjust = Cost.LocalCost - LocalCost;
942  else
943  ThisLocalAdjust = LocalCost - Cost.LocalCost;
944  } else {
945  ThisLocalAdjust = LocalCost;
946  OtherLocalAdjust = Cost.LocalCost;
947  }
948 
949  // The non-local costs are comparable, just keep the relative value.
950  uint64_t ThisNonLocalAdjust = 0;
951  uint64_t OtherNonLocalAdjust = 0;
952  if (NonLocalCost < Cost.NonLocalCost)
953  OtherNonLocalAdjust = Cost.NonLocalCost - NonLocalCost;
954  else
955  ThisNonLocalAdjust = NonLocalCost - Cost.NonLocalCost;
956  // Scale everything to make them comparable.
957  uint64_t ThisScaledCost = ThisLocalAdjust * LocalFreq;
958  // Check for overflow on that operation.
959  bool ThisOverflows = ThisLocalAdjust && (ThisScaledCost < ThisLocalAdjust ||
960  ThisScaledCost < LocalFreq);
961  uint64_t OtherScaledCost = OtherLocalAdjust * Cost.LocalFreq;
962  // Check for overflow on the last operation.
963  bool OtherOverflows =
964  OtherLocalAdjust &&
965  (OtherScaledCost < OtherLocalAdjust || OtherScaledCost < Cost.LocalFreq);
966  // Add the non-local costs.
967  ThisOverflows |= ThisNonLocalAdjust &&
968  ThisScaledCost + ThisNonLocalAdjust < ThisNonLocalAdjust;
969  ThisScaledCost += ThisNonLocalAdjust;
970  OtherOverflows |= OtherNonLocalAdjust &&
971  OtherScaledCost + OtherNonLocalAdjust < OtherNonLocalAdjust;
972  OtherScaledCost += OtherNonLocalAdjust;
973  // If both overflows, we cannot compare without additional
974  // precision, e.g., APInt. Just give up on that case.
975  if (ThisOverflows && OtherOverflows)
976  return false;
977  // If one overflows but not the other, we can still compare.
978  if (ThisOverflows || OtherOverflows)
979  return ThisOverflows < OtherOverflows;
980  // Otherwise, just compare the values.
981  return ThisScaledCost < OtherScaledCost;
982 }
983 
984 bool RegBankSelect::MappingCost::operator==(const MappingCost &Cost) const {
985  return LocalCost == Cost.LocalCost && NonLocalCost == Cost.NonLocalCost &&
986  LocalFreq == Cost.LocalFreq;
987 }
988 
989 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
991  print(dbgs());
992  dbgs() << '\n';
993 }
994 #endif
995 
997  if (*this == ImpossibleCost()) {
998  OS << "impossible";
999  return;
1000  }
1001  if (isSaturated()) {
1002  OS << "saturated";
1003  return;
1004  }
1005  OS << LocalFreq << " * " << LocalCost << " + " << NonLocalCost;
1006 }
Pass interface - Implemented by all &#39;passes&#39;.
Definition: Pass.h:81
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
bool canMaterialize() const override
Check whether this insertion point can be materialized.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
MachineBasicBlock * getMBB() const
SI Whole Quad Mode
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
Definition: ilist_node.h:289
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:449
#define LLVM_LIKELY(EXPR)
Definition: Compiler.h:175
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
INITIALIZE_PASS_BEGIN(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false)
const MachineFunctionProperties & getProperties() const
Get the function properties.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
unsigned getCost() const
Get the cost.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
unsigned getReg() const
getReg - Returns the register number.
Reparing code needs to happen before InsertPoints.
uint64_t getFrequency() const
Returns the frequency as a fixpoint number scaled by the entry frequency.
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
static void dump(StringRef Title, SpillInfo const &Spills)
Definition: CoroFrame.cpp:283
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
F(f)
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
void setRegBank(unsigned Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
bool isPHI() const
Definition: MachineInstr.h:826
Mode
List of the modes supported by the RegBankSelect pass.
Definition: RegBankSelect.h:96
void switchTo(RepairingKind NewKind)
Change the type of this repairing placement to NewKind.
iterator_range< succ_iterator > successors()
const PartialMapping * BreakDown
How the value is broken down between the different register banks.
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:51
Mark this repairing placement as impossible.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Abstract class used to represent an insertion point in a CFG.
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
Reg
All possible values of the reg field in the ModR/M byte.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:474
RepairingKind
Define the kind of action this repairing needs.
This file contains the simple types necessary to represent the attributes associated with functions a...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
iterator_range< SmallVectorImpl< unsigned >::const_iterator > getVRegs(unsigned OpIdx, bool ForDebug=false) const
Get all the virtual registers required to map the OpIdx-th operand of the instruction.
Target-Independent Code Generator Pass Configuration Options.
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don&#39;t insert <empty> = Opcode <empty>.
MachineFunction & getMF()
Getter for the function we currently build.
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
#define DEBUG_TYPE
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
RepairingPlacement(MachineInstr &MI, unsigned OpIdx, const TargetRegisterInfo &TRI, Pass &P, RepairingKind Kind=RepairingKind::Insert)
Create a repairing placement for the OpIdx-th operand of MI.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
const RegisterBank * RegBank
Register bank where the partial value lives.
uint64_t frequency(const Pass &P) const override
Frequency of the insertion point.
===- MachineOptimizationRemarkEmitter.h - Opt Diagnostics -*- C++ -*-—===//
#define P(N)
virtual const LegalizerInfo * getLegalizerInfo() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
Insertion point on an edge.
virtual const InstructionMapping & getInstrMapping(const MachineInstr &MI) const
Get the mapping of the different operands of MI on the register bank.
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:626
BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const
getblockFreq - Return block frequency.
Represent the analysis usage information of a pass.
static const unsigned End
bool isTargetSpecificOpcode(unsigned Opcode)
Check whether the given Opcode is a target-specific opcode.
Definition: TargetOpcodes.h:37
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
void initializeRegBankSelectPass(PassRegistry &)
void setMF(MachineFunction &)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isValid() const
Check whether this object is valid.
bool verify(const MachineInstr &MI) const
Verifiy that this mapping makes sense for MI.
virtual bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
Struct used to represent the placement of a repairing point for a given operand.
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
Create a new MachineInstr which is a copy of Orig, identical in all ways except the instruction has n...
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:864
This class implements the register bank concept.
Definition: RegisterBank.h:29
Helper struct that represents how a value is mapped through different register banks.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:923
A range adaptor for a pair of iterators.
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:927
virtual bool canMaterialize() const
Check whether this insertion point can be materialized.
bool isUnconditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which always transfers control flow to some other block...
Definition: MachineInstr.h:504
void createVRegs(unsigned OpIdx)
Create as many new virtual registers as needed for the mapping of the OpIdx-th operand.
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:601
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
BranchProbability getEdgeProbability(const MachineBasicBlock *Src, const MachineBasicBlock *Dst) const
Representation of each machine instruction.
Definition: MachineInstr.h:59
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Insertion point before or after an instruction.
void emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:656
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:61
virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
InstrInsertPoint(MachineInstr &Instr, bool Before=true)
Create an insertion point before (Before=true) or after Instr.
uint64_t frequency(const Pass &P) const override
Frequency of the insertion point.
bool WasMaterialized
Tell if the insert point has already been materialized.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:123
void addInsertPoint(MachineBasicBlock &MBB, bool Beginning)
iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
static cl::opt< RegBankSelect::Mode > RegBankSelectMode(cl::desc("Mode of the RegBankSelect pass"), cl::Hidden, cl::Optional, cl::values(clEnumValN(RegBankSelect::Mode::Fast, "regbankselect-fast", "Run the Fast mode (default mapping)"), clEnumValN(RegBankSelect::Mode::Greedy, "regbankselect-greedy", "Use the Greedy mode (best local mapping)")))
bool runOnMachineFunction(MachineFunction &MF) override
Walk through MF and assign a register bank to every virtual register that are still mapped to nothing...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool hasProperty(Property P) const
MachineBasicBlock * SplitCriticalEdge(MachineBasicBlock *Succ, Pass &P)
Split the critical edge from this block to the given successor block, and return the newly created bl...
bool operator<(int64_t V1, const APSInt &V2)
Definition: APSInt.h:326
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel...
Definition: TargetOpcodes.h:31
unsigned NumBreakDowns
Number of partial mapping to break down this value.
AnalysisType * getAnalysisIfAvailable() const
getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information tha...
(Re)assign the register bank of the operand.
virtual bool isSplit() const
Does this point involve splitting an edge or block? As soon as ::getPoint is called and thus...
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
#define DEBUG(X)
Definition: Debug.h:118
IRTranslator LLVM IR MI
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
bool operator==(uint64_t V1, const APInt &V2)
Definition: APInt.h:1946
uint64_t frequency(const Pass &P) const override
Frequency of the insertion point.
unsigned getNumOperands() const
Get the number of operands.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext&#39;s diagnostic stream...
Definition: Utils.cpp:80
Insertion point at the beginning or end of a basic block.
Nothing to repair, just drop this action.
bool isSplit() const override
Does this point involve splitting an edge or block? As soon as ::getPoint is called and thus...