LLVM  9.0.0svn
RegBankSelect.cpp
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1 //==- llvm/CodeGen/GlobalISel/RegBankSelect.cpp - RegBankSelect --*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the RegBankSelect class.
10 //===----------------------------------------------------------------------===//
11 
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/SmallVector.h"
32 #include "llvm/Config/llvm-config.h"
33 #include "llvm/IR/Attributes.h"
34 #include "llvm/IR/Function.h"
35 #include "llvm/Pass.h"
38 #include "llvm/Support/Compiler.h"
39 #include "llvm/Support/Debug.h"
42 #include <algorithm>
43 #include <cassert>
44 #include <cstdint>
45 #include <limits>
46 #include <memory>
47 #include <utility>
48 
49 #define DEBUG_TYPE "regbankselect"
50 
51 using namespace llvm;
52 
54  cl::desc("Mode of the RegBankSelect pass"), cl::Hidden, cl::Optional,
55  cl::values(clEnumValN(RegBankSelect::Mode::Fast, "regbankselect-fast",
56  "Run the Fast mode (default mapping)"),
57  clEnumValN(RegBankSelect::Mode::Greedy, "regbankselect-greedy",
58  "Use the Greedy mode (best local mapping)")));
59 
60 char RegBankSelect::ID = 0;
61 
63  "Assign register bank of generic virtual registers",
64  false, false);
69  "Assign register bank of generic virtual registers", false,
70  false)
71 
72 RegBankSelect::RegBankSelect(Mode RunningMode)
73  : MachineFunctionPass(ID), OptMode(RunningMode) {
75  if (RegBankSelectMode.getNumOccurrences() != 0) {
76  OptMode = RegBankSelectMode;
77  if (RegBankSelectMode != RunningMode)
78  LLVM_DEBUG(dbgs() << "RegBankSelect mode overrided by command line\n");
79  }
80 }
81 
82 void RegBankSelect::init(MachineFunction &MF) {
83  RBI = MF.getSubtarget().getRegBankInfo();
84  assert(RBI && "Cannot work without RegisterBankInfo");
85  MRI = &MF.getRegInfo();
86  TRI = MF.getSubtarget().getRegisterInfo();
87  TPC = &getAnalysis<TargetPassConfig>();
88  if (OptMode != Mode::Fast) {
89  MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
90  MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
91  } else {
92  MBFI = nullptr;
93  MBPI = nullptr;
94  }
95  MIRBuilder.setMF(MF);
96  MORE = llvm::make_unique<MachineOptimizationRemarkEmitter>(MF, MBFI);
97 }
98 
100  if (OptMode != Mode::Fast) {
101  // We could preserve the information from these two analysis but
102  // the APIs do not allow to do so yet.
105  }
109 }
110 
111 bool RegBankSelect::assignmentMatch(
112  unsigned Reg, const RegisterBankInfo::ValueMapping &ValMapping,
113  bool &OnlyAssign) const {
114  // By default we assume we will have to repair something.
115  OnlyAssign = false;
116  // Each part of a break down needs to end up in a different register.
117  // In other word, Reg assignment does not match.
118  if (ValMapping.NumBreakDowns != 1)
119  return false;
120 
121  const RegisterBank *CurRegBank = RBI->getRegBank(Reg, *MRI, *TRI);
122  const RegisterBank *DesiredRegBrank = ValMapping.BreakDown[0].RegBank;
123  // Reg is free of assignment, a simple assignment will make the
124  // register bank to match.
125  OnlyAssign = CurRegBank == nullptr;
126  LLVM_DEBUG(dbgs() << "Does assignment already match: ";
127  if (CurRegBank) dbgs() << *CurRegBank; else dbgs() << "none";
128  dbgs() << " against ";
129  assert(DesiredRegBrank && "The mapping must be valid");
130  dbgs() << *DesiredRegBrank << '\n';);
131  return CurRegBank == DesiredRegBrank;
132 }
133 
134 bool RegBankSelect::repairReg(
135  MachineOperand &MO, const RegisterBankInfo::ValueMapping &ValMapping,
138 
139  assert(ValMapping.NumBreakDowns == size(NewVRegs) && "need new vreg for each breakdown");
140 
141  // An empty range of new register means no repairing.
142  assert(!empty(NewVRegs) && "We should not have to repair");
143 
144  MachineInstr *MI;
145  if (ValMapping.NumBreakDowns == 1) {
146  // Assume we are repairing a use and thus, the original reg will be
147  // the source of the repairing.
148  unsigned Src = MO.getReg();
149  unsigned Dst = *NewVRegs.begin();
150 
151  // If we repair a definition, swap the source and destination for
152  // the repairing.
153  if (MO.isDef())
154  std::swap(Src, Dst);
155 
156  assert((RepairPt.getNumInsertPoints() == 1 ||
158  "We are about to create several defs for Dst");
159 
160  // Build the instruction used to repair, then clone it at the right
161  // places. Avoiding buildCopy bypasses the check that Src and Dst have the
162  // same types because the type is a placeholder when this function is called.
163  MI = MIRBuilder.buildInstrNoInsert(TargetOpcode::COPY)
164  .addDef(Dst)
165  .addUse(Src);
166  LLVM_DEBUG(dbgs() << "Copy: " << printReg(Src) << " to: " << printReg(Dst)
167  << '\n');
168  } else {
169  // TODO: Support with G_IMPLICIT_DEF + G_INSERT sequence or G_EXTRACT
170  // sequence.
171  assert(ValMapping.partsAllUniform() && "irregular breakdowns not supported");
172 
173  LLT RegTy = MRI->getType(MO.getReg());
174  assert(!RegTy.isPointer() && "not implemented");
175 
176  // FIXME: We could handle split vectors with concat_vectors easily, but this
177  // would require an agreement on the type of registers with the
178  // target. Currently createVRegs just uses scalar types, and expects the
179  // target code to replace this type (which we won't know about here)
180  assert((RegTy.isScalar() ||
181  RegTy.getNumElements() == ValMapping.NumBreakDowns) &&
182  "only basic vector breakdowns currently supported");
183 
184  if (MO.isDef()) {
185  unsigned MergeOp = RegTy.isScalar() ?
186  TargetOpcode::G_MERGE_VALUES : TargetOpcode::G_BUILD_VECTOR;
187 
188  auto MergeBuilder =
189  MIRBuilder.buildInstrNoInsert(MergeOp)
190  .addDef(MO.getReg());
191 
192  for (unsigned SrcReg : NewVRegs)
193  MergeBuilder.addUse(SrcReg);
194 
195  MI = MergeBuilder;
196  } else {
197  MachineInstrBuilder UnMergeBuilder =
198  MIRBuilder.buildInstrNoInsert(TargetOpcode::G_UNMERGE_VALUES);
199  for (unsigned DefReg : NewVRegs)
200  UnMergeBuilder.addDef(DefReg);
201 
202  UnMergeBuilder.addUse(MO.getReg());
203  MI = UnMergeBuilder;
204  }
205  }
206 
207  if (RepairPt.getNumInsertPoints() != 1)
208  report_fatal_error("need testcase to support multiple insertion points");
209 
210  // TODO:
211  // Check if MI is legal. if not, we need to legalize all the
212  // instructions we are going to insert.
213  std::unique_ptr<MachineInstr *[]> NewInstrs(
214  new MachineInstr *[RepairPt.getNumInsertPoints()]);
215  bool IsFirst = true;
216  unsigned Idx = 0;
217  for (const std::unique_ptr<InsertPoint> &InsertPt : RepairPt) {
218  MachineInstr *CurMI;
219  if (IsFirst)
220  CurMI = MI;
221  else
222  CurMI = MIRBuilder.getMF().CloneMachineInstr(MI);
223  InsertPt->insert(*CurMI);
224  NewInstrs[Idx++] = CurMI;
225  IsFirst = false;
226  }
227  // TODO:
228  // Legalize NewInstrs if need be.
229  return true;
230 }
231 
232 uint64_t RegBankSelect::getRepairCost(
233  const MachineOperand &MO,
234  const RegisterBankInfo::ValueMapping &ValMapping) const {
235  assert(MO.isReg() && "We should only repair register operand");
236  assert(ValMapping.NumBreakDowns && "Nothing to map??");
237 
238  bool IsSameNumOfValues = ValMapping.NumBreakDowns == 1;
239  const RegisterBank *CurRegBank = RBI->getRegBank(MO.getReg(), *MRI, *TRI);
240  // If MO does not have a register bank, we should have just been
241  // able to set one unless we have to break the value down.
242  assert(CurRegBank || MO.isDef());
243 
244  // Def: Val <- NewDefs
245  // Same number of values: copy
246  // Different number: Val = build_sequence Defs1, Defs2, ...
247  // Use: NewSources <- Val.
248  // Same number of values: copy.
249  // Different number: Src1, Src2, ... =
250  // extract_value Val, Src1Begin, Src1Len, Src2Begin, Src2Len, ...
251  // We should remember that this value is available somewhere else to
252  // coalesce the value.
253 
254  if (ValMapping.NumBreakDowns != 1)
255  return RBI->getBreakDownCost(ValMapping, CurRegBank);
256 
257  if (IsSameNumOfValues) {
258  const RegisterBank *DesiredRegBrank = ValMapping.BreakDown[0].RegBank;
259  // If we repair a definition, swap the source and destination for
260  // the repairing.
261  if (MO.isDef())
262  std::swap(CurRegBank, DesiredRegBrank);
263  // TODO: It may be possible to actually avoid the copy.
264  // If we repair something where the source is defined by a copy
265  // and the source of that copy is on the right bank, we can reuse
266  // it for free.
267  // E.g.,
268  // RegToRepair<BankA> = copy AlternativeSrc<BankB>
269  // = op RegToRepair<BankA>
270  // We can simply propagate AlternativeSrc instead of copying RegToRepair
271  // into a new virtual register.
272  // We would also need to propagate this information in the
273  // repairing placement.
274  unsigned Cost = RBI->copyCost(*DesiredRegBrank, *CurRegBank,
275  RBI->getSizeInBits(MO.getReg(), *MRI, *TRI));
276  // TODO: use a dedicated constant for ImpossibleCost.
278  return Cost;
279  // Return the legalization cost of that repairing.
280  }
282 }
283 
284 const RegisterBankInfo::InstructionMapping &RegBankSelect::findBestMapping(
287  assert(!PossibleMappings.empty() &&
288  "Do not know how to map this instruction");
289 
290  const RegisterBankInfo::InstructionMapping *BestMapping = nullptr;
291  MappingCost Cost = MappingCost::ImpossibleCost();
292  SmallVector<RepairingPlacement, 4> LocalRepairPts;
293  for (const RegisterBankInfo::InstructionMapping *CurMapping :
294  PossibleMappings) {
295  MappingCost CurCost =
296  computeMapping(MI, *CurMapping, LocalRepairPts, &Cost);
297  if (CurCost < Cost) {
298  LLVM_DEBUG(dbgs() << "New best: " << CurCost << '\n');
299  Cost = CurCost;
300  BestMapping = CurMapping;
301  RepairPts.clear();
302  for (RepairingPlacement &RepairPt : LocalRepairPts)
303  RepairPts.emplace_back(std::move(RepairPt));
304  }
305  }
306  if (!BestMapping && !TPC->isGlobalISelAbortEnabled()) {
307  // If none of the mapping worked that means they are all impossible.
308  // Thus, pick the first one and set an impossible repairing point.
309  // It will trigger the failed isel mode.
310  BestMapping = *PossibleMappings.begin();
311  RepairPts.emplace_back(
313  } else
314  assert(BestMapping && "No suitable mapping for instruction");
315  return *BestMapping;
316 }
317 
318 void RegBankSelect::tryAvoidingSplit(
320  const RegisterBankInfo::ValueMapping &ValMapping) const {
321  const MachineInstr &MI = *MO.getParent();
322  assert(RepairPt.hasSplit() && "We should not have to adjust for split");
323  // Splitting should only occur for PHIs or between terminators,
324  // because we only do local repairing.
325  assert((MI.isPHI() || MI.isTerminator()) && "Why do we split?");
326 
327  assert(&MI.getOperand(RepairPt.getOpIdx()) == &MO &&
328  "Repairing placement does not match operand");
329 
330  // If we need splitting for phis, that means it is because we
331  // could not find an insertion point before the terminators of
332  // the predecessor block for this argument. In other words,
333  // the input value is defined by one of the terminators.
334  assert((!MI.isPHI() || !MO.isDef()) && "Need split for phi def?");
335 
336  // We split to repair the use of a phi or a terminator.
337  if (!MO.isDef()) {
338  if (MI.isTerminator()) {
339  assert(&MI != &(*MI.getParent()->getFirstTerminator()) &&
340  "Need to split for the first terminator?!");
341  } else {
342  // For the PHI case, the split may not be actually required.
343  // In the copy case, a phi is already a copy on the incoming edge,
344  // therefore there is no need to split.
345  if (ValMapping.NumBreakDowns == 1)
346  // This is a already a copy, there is nothing to do.
347  RepairPt.switchTo(RepairingPlacement::RepairingKind::Reassign);
348  }
349  return;
350  }
351 
352  // At this point, we need to repair a defintion of a terminator.
353 
354  // Technically we need to fix the def of MI on all outgoing
355  // edges of MI to keep the repairing local. In other words, we
356  // will create several definitions of the same register. This
357  // does not work for SSA unless that definition is a physical
358  // register.
359  // However, there are other cases where we can get away with
360  // that while still keeping the repairing local.
361  assert(MI.isTerminator() && MO.isDef() &&
362  "This code is for the def of a terminator");
363 
364  // Since we use RPO traversal, if we need to repair a definition
365  // this means this definition could be:
366  // 1. Used by PHIs (i.e., this VReg has been visited as part of the
367  // uses of a phi.), or
368  // 2. Part of a target specific instruction (i.e., the target applied
369  // some register class constraints when creating the instruction.)
370  // If the constraints come for #2, the target said that another mapping
371  // is supported so we may just drop them. Indeed, if we do not change
372  // the number of registers holding that value, the uses will get fixed
373  // when we get to them.
374  // Uses in PHIs may have already been proceeded though.
375  // If the constraints come for #1, then, those are weak constraints and
376  // no actual uses may rely on them. However, the problem remains mainly
377  // the same as for #2. If the value stays in one register, we could
378  // just switch the register bank of the definition, but we would need to
379  // account for a repairing cost for each phi we silently change.
380  //
381  // In any case, if the value needs to be broken down into several
382  // registers, the repairing is not local anymore as we need to patch
383  // every uses to rebuild the value in just one register.
384  //
385  // To summarize:
386  // - If the value is in a physical register, we can do the split and
387  // fix locally.
388  // Otherwise if the value is in a virtual register:
389  // - If the value remains in one register, we do not have to split
390  // just switching the register bank would do, but we need to account
391  // in the repairing cost all the phi we changed.
392  // - If the value spans several registers, then we cannot do a local
393  // repairing.
394 
395  // Check if this is a physical or virtual register.
396  unsigned Reg = MO.getReg();
398  // We are going to split every outgoing edges.
399  // Check that this is possible.
400  // FIXME: The machine representation is currently broken
401  // since it also several terminators in one basic block.
402  // Because of that we would technically need a way to get
403  // the targets of just one terminator to know which edges
404  // we have to split.
405  // Assert that we do not hit the ill-formed representation.
406 
407  // If there are other terminators before that one, some of
408  // the outgoing edges may not be dominated by this definition.
409  assert(&MI == &(*MI.getParent()->getFirstTerminator()) &&
410  "Do not know which outgoing edges are relevant");
411  const MachineInstr *Next = MI.getNextNode();
412  assert((!Next || Next->isUnconditionalBranch()) &&
413  "Do not know where each terminator ends up");
414  if (Next)
415  // If the next terminator uses Reg, this means we have
416  // to split right after MI and thus we need a way to ask
417  // which outgoing edges are affected.
418  assert(!Next->readsRegister(Reg) && "Need to split between terminators");
419  // We will split all the edges and repair there.
420  } else {
421  // This is a virtual register defined by a terminator.
422  if (ValMapping.NumBreakDowns == 1) {
423  // There is nothing to repair, but we may actually lie on
424  // the repairing cost because of the PHIs already proceeded
425  // as already stated.
426  // Though the code will be correct.
427  assert(false && "Repairing cost may not be accurate");
428  } else {
429  // We need to do non-local repairing. Basically, patch all
430  // the uses (i.e., phis) that we already proceeded.
431  // For now, just say this mapping is not possible.
432  RepairPt.switchTo(RepairingPlacement::RepairingKind::Impossible);
433  }
434  }
435 }
436 
437 RegBankSelect::MappingCost RegBankSelect::computeMapping(
438  MachineInstr &MI, const RegisterBankInfo::InstructionMapping &InstrMapping,
440  const RegBankSelect::MappingCost *BestCost) {
441  assert((MBFI || !BestCost) && "Costs comparison require MBFI");
442 
443  if (!InstrMapping.isValid())
444  return MappingCost::ImpossibleCost();
445 
446  // If mapped with InstrMapping, MI will have the recorded cost.
447  MappingCost Cost(MBFI ? MBFI->getBlockFreq(MI.getParent()) : 1);
448  bool Saturated = Cost.addLocalCost(InstrMapping.getCost());
449  assert(!Saturated && "Possible mapping saturated the cost");
450  LLVM_DEBUG(dbgs() << "Evaluating mapping cost for: " << MI);
451  LLVM_DEBUG(dbgs() << "With: " << InstrMapping << '\n');
452  RepairPts.clear();
453  if (BestCost && Cost > *BestCost) {
454  LLVM_DEBUG(dbgs() << "Mapping is too expensive from the start\n");
455  return Cost;
456  }
457 
458  // Moreover, to realize this mapping, the register bank of each operand must
459  // match this mapping. In other words, we may need to locally reassign the
460  // register banks. Account for that repairing cost as well.
461  // In this context, local means in the surrounding of MI.
462  for (unsigned OpIdx = 0, EndOpIdx = InstrMapping.getNumOperands();
463  OpIdx != EndOpIdx; ++OpIdx) {
464  const MachineOperand &MO = MI.getOperand(OpIdx);
465  if (!MO.isReg())
466  continue;
467  unsigned Reg = MO.getReg();
468  if (!Reg)
469  continue;
470  LLVM_DEBUG(dbgs() << "Opd" << OpIdx << '\n');
471  const RegisterBankInfo::ValueMapping &ValMapping =
472  InstrMapping.getOperandMapping(OpIdx);
473  // If Reg is already properly mapped, this is free.
474  bool Assign;
475  if (assignmentMatch(Reg, ValMapping, Assign)) {
476  LLVM_DEBUG(dbgs() << "=> is free (match).\n");
477  continue;
478  }
479  if (Assign) {
480  LLVM_DEBUG(dbgs() << "=> is free (simple assignment).\n");
481  RepairPts.emplace_back(RepairingPlacement(MI, OpIdx, *TRI, *this,
483  continue;
484  }
485 
486  // Find the insertion point for the repairing code.
487  RepairPts.emplace_back(
488  RepairingPlacement(MI, OpIdx, *TRI, *this, RepairingPlacement::Insert));
489  RepairingPlacement &RepairPt = RepairPts.back();
490 
491  // If we need to split a basic block to materialize this insertion point,
492  // we may give a higher cost to this mapping.
493  // Nevertheless, we may get away with the split, so try that first.
494  if (RepairPt.hasSplit())
495  tryAvoidingSplit(RepairPt, MO, ValMapping);
496 
497  // Check that the materialization of the repairing is possible.
498  if (!RepairPt.canMaterialize()) {
499  LLVM_DEBUG(dbgs() << "Mapping involves impossible repairing\n");
500  return MappingCost::ImpossibleCost();
501  }
502 
503  // Account for the split cost and repair cost.
504  // Unless the cost is already saturated or we do not care about the cost.
505  if (!BestCost || Saturated)
506  continue;
507 
508  // To get accurate information we need MBFI and MBPI.
509  // Thus, if we end up here this information should be here.
510  assert(MBFI && MBPI && "Cost computation requires MBFI and MBPI");
511 
512  // FIXME: We will have to rework the repairing cost model.
513  // The repairing cost depends on the register bank that MO has.
514  // However, when we break down the value into different values,
515  // MO may not have a register bank while still needing repairing.
516  // For the fast mode, we don't compute the cost so that is fine,
517  // but still for the repairing code, we will have to make a choice.
518  // For the greedy mode, we should choose greedily what is the best
519  // choice based on the next use of MO.
520 
521  // Sums up the repairing cost of MO at each insertion point.
522  uint64_t RepairCost = getRepairCost(MO, ValMapping);
523 
524  // This is an impossible to repair cost.
525  if (RepairCost == std::numeric_limits<unsigned>::max())
526  return MappingCost::ImpossibleCost();
527 
528  // Bias used for splitting: 5%.
529  const uint64_t PercentageForBias = 5;
530  uint64_t Bias = (RepairCost * PercentageForBias + 99) / 100;
531  // We should not need more than a couple of instructions to repair
532  // an assignment. In other words, the computation should not
533  // overflow because the repairing cost is free of basic block
534  // frequency.
535  assert(((RepairCost < RepairCost * PercentageForBias) &&
536  (RepairCost * PercentageForBias <
537  RepairCost * PercentageForBias + 99)) &&
538  "Repairing involves more than a billion of instructions?!");
539  for (const std::unique_ptr<InsertPoint> &InsertPt : RepairPt) {
540  assert(InsertPt->canMaterialize() && "We should not have made it here");
541  // We will applied some basic block frequency and those uses uint64_t.
542  if (!InsertPt->isSplit())
543  Saturated = Cost.addLocalCost(RepairCost);
544  else {
545  uint64_t CostForInsertPt = RepairCost;
546  // Again we shouldn't overflow here givent that
547  // CostForInsertPt is frequency free at this point.
548  assert(CostForInsertPt + Bias > CostForInsertPt &&
549  "Repairing + split bias overflows");
550  CostForInsertPt += Bias;
551  uint64_t PtCost = InsertPt->frequency(*this) * CostForInsertPt;
552  // Check if we just overflowed.
553  if ((Saturated = PtCost < CostForInsertPt))
554  Cost.saturate();
555  else
556  Saturated = Cost.addNonLocalCost(PtCost);
557  }
558 
559  // Stop looking into what it takes to repair, this is already
560  // too expensive.
561  if (BestCost && Cost > *BestCost) {
562  LLVM_DEBUG(dbgs() << "Mapping is too expensive, stop processing\n");
563  return Cost;
564  }
565 
566  // No need to accumulate more cost information.
567  // We need to still gather the repairing information though.
568  if (Saturated)
569  break;
570  }
571  }
572  LLVM_DEBUG(dbgs() << "Total cost is: " << Cost << "\n");
573  return Cost;
574 }
575 
576 bool RegBankSelect::applyMapping(
577  MachineInstr &MI, const RegisterBankInfo::InstructionMapping &InstrMapping,
579  // OpdMapper will hold all the information needed for the rewriting.
580  RegisterBankInfo::OperandsMapper OpdMapper(MI, InstrMapping, *MRI);
581 
582  // First, place the repairing code.
583  for (RepairingPlacement &RepairPt : RepairPts) {
584  if (!RepairPt.canMaterialize() ||
586  return false;
587  assert(RepairPt.getKind() != RepairingPlacement::None &&
588  "This should not make its way in the list");
589  unsigned OpIdx = RepairPt.getOpIdx();
590  MachineOperand &MO = MI.getOperand(OpIdx);
591  const RegisterBankInfo::ValueMapping &ValMapping =
592  InstrMapping.getOperandMapping(OpIdx);
593  unsigned Reg = MO.getReg();
594 
595  switch (RepairPt.getKind()) {
597  assert(ValMapping.NumBreakDowns == 1 &&
598  "Reassignment should only be for simple mapping");
599  MRI->setRegBank(Reg, *ValMapping.BreakDown[0].RegBank);
600  break;
602  OpdMapper.createVRegs(OpIdx);
603  if (!repairReg(MO, ValMapping, RepairPt, OpdMapper.getVRegs(OpIdx)))
604  return false;
605  break;
606  default:
607  llvm_unreachable("Other kind should not happen");
608  }
609  }
610 
611  // Second, rewrite the instruction.
612  LLVM_DEBUG(dbgs() << "Actual mapping of the operands: " << OpdMapper << '\n');
613  RBI->applyMapping(OpdMapper);
614 
615  return true;
616 }
617 
618 bool RegBankSelect::assignInstr(MachineInstr &MI) {
619  LLVM_DEBUG(dbgs() << "Assign: " << MI);
620  // Remember the repairing placement for all the operands.
622 
623  const RegisterBankInfo::InstructionMapping *BestMapping;
624  if (OptMode == RegBankSelect::Mode::Fast) {
625  BestMapping = &RBI->getInstrMapping(MI);
626  MappingCost DefaultCost = computeMapping(MI, *BestMapping, RepairPts);
627  (void)DefaultCost;
628  if (DefaultCost == MappingCost::ImpossibleCost())
629  return false;
630  } else {
631  RegisterBankInfo::InstructionMappings PossibleMappings =
632  RBI->getInstrPossibleMappings(MI);
633  if (PossibleMappings.empty())
634  return false;
635  BestMapping = &findBestMapping(MI, PossibleMappings, RepairPts);
636  }
637  // Make sure the mapping is valid for MI.
638  assert(BestMapping->verify(MI) && "Invalid instruction mapping");
639 
640  LLVM_DEBUG(dbgs() << "Best Mapping: " << *BestMapping << '\n');
641 
642  // After this call, MI may not be valid anymore.
643  // Do not use it.
644  return applyMapping(MI, *BestMapping, RepairPts);
645 }
646 
648  // If the ISel pipeline failed, do not bother running that pass.
649  if (MF.getProperties().hasProperty(
651  return false;
652 
653  LLVM_DEBUG(dbgs() << "Assign register banks for: " << MF.getName() << '\n');
654  const Function &F = MF.getFunction();
655  Mode SaveOptMode = OptMode;
656  if (F.hasFnAttribute(Attribute::OptimizeNone))
657  OptMode = Mode::Fast;
658  init(MF);
659 
660 #ifndef NDEBUG
661  // Check that our input is fully legal: we require the function to have the
662  // Legalized property, so it should be.
663  // FIXME: This should be in the MachineVerifier.
665  if (const MachineInstr *MI = machineFunctionIsIllegal(MF)) {
666  reportGISelFailure(MF, *TPC, *MORE, "gisel-regbankselect",
667  "instruction is not legal", *MI);
668  return false;
669  }
670 #endif
671 
672  // Walk the function and assign register banks to all operands.
673  // Use a RPOT to make sure all registers are assigned before we choose
674  // the best mapping of the current instruction.
676  for (MachineBasicBlock *MBB : RPOT) {
677  // Set a sensible insertion point so that subsequent calls to
678  // MIRBuilder.
679  MIRBuilder.setMBB(*MBB);
680  for (MachineBasicBlock::iterator MII = MBB->begin(), End = MBB->end();
681  MII != End;) {
682  // MI might be invalidated by the assignment, so move the
683  // iterator before hand.
684  MachineInstr &MI = *MII++;
685 
686  // Ignore target-specific instructions: they should use proper regclasses.
688  continue;
689 
690  if (!assignInstr(MI)) {
691  reportGISelFailure(MF, *TPC, *MORE, "gisel-regbankselect",
692  "unable to map instruction", MI);
693  return false;
694  }
695 
696  // It's possible the mapping changed control flow, and moved the following
697  // instruction to a new block, so figure out the new parent.
698  if (MII != End) {
699  MachineBasicBlock *NextInstBB = MII->getParent();
700  if (NextInstBB != MBB) {
701  LLVM_DEBUG(dbgs() << "Instruction mapping changed control flow\n");
702  MBB = NextInstBB;
703  MIRBuilder.setMBB(*MBB);
704  End = MBB->end();
705  }
706  }
707  }
708  }
709 
710  OptMode = SaveOptMode;
711  return false;
712 }
713 
714 //------------------------------------------------------------------------------
715 // Helper Classes Implementation
716 //------------------------------------------------------------------------------
718  MachineInstr &MI, unsigned OpIdx, const TargetRegisterInfo &TRI, Pass &P,
720  // Default is, we are going to insert code to repair OpIdx.
721  : Kind(Kind), OpIdx(OpIdx),
722  CanMaterialize(Kind != RepairingKind::Impossible), P(P) {
723  const MachineOperand &MO = MI.getOperand(OpIdx);
724  assert(MO.isReg() && "Trying to repair a non-reg operand");
725 
726  if (Kind != RepairingKind::Insert)
727  return;
728 
729  // Repairings for definitions happen after MI, uses happen before.
730  bool Before = !MO.isDef();
731 
732  // Check if we are done with MI.
733  if (!MI.isPHI() && !MI.isTerminator()) {
734  addInsertPoint(MI, Before);
735  // We are done with the initialization.
736  return;
737  }
738 
739  // Now, look for the special cases.
740  if (MI.isPHI()) {
741  // - PHI must be the first instructions:
742  // * Before, we have to split the related incoming edge.
743  // * After, move the insertion point past the last phi.
744  if (!Before) {
746  if (It != MI.getParent()->end())
747  addInsertPoint(*It, /*Before*/ true);
748  else
749  addInsertPoint(*(--It), /*Before*/ false);
750  return;
751  }
752  // We repair a use of a phi, we may need to split the related edge.
753  MachineBasicBlock &Pred = *MI.getOperand(OpIdx + 1).getMBB();
754  // Check if we can move the insertion point prior to the
755  // terminators of the predecessor.
756  unsigned Reg = MO.getReg();
758  for (auto Begin = Pred.begin(); It != Begin && It->isTerminator(); --It)
759  if (It->modifiesRegister(Reg, &TRI)) {
760  // We cannot hoist the repairing code in the predecessor.
761  // Split the edge.
762  addInsertPoint(Pred, *MI.getParent());
763  return;
764  }
765  // At this point, we can insert in Pred.
766 
767  // - If It is invalid, Pred is empty and we can insert in Pred
768  // wherever we want.
769  // - If It is valid, It is the first non-terminator, insert after It.
770  if (It == Pred.end())
771  addInsertPoint(Pred, /*Beginning*/ false);
772  else
773  addInsertPoint(*It, /*Before*/ false);
774  } else {
775  // - Terminators must be the last instructions:
776  // * Before, move the insert point before the first terminator.
777  // * After, we have to split the outcoming edges.
778  if (Before) {
779  // Check whether Reg is defined by any terminator.
781  auto REnd = MI.getParent()->rend();
782 
783  for (; It != REnd && It->isTerminator(); ++It) {
784  assert(!It->modifiesRegister(MO.getReg(), &TRI) &&
785  "copy insertion in middle of terminators not handled");
786  }
787 
788  if (It == REnd) {
789  addInsertPoint(*MI.getParent()->begin(), true);
790  return;
791  }
792 
793  // We are sure to be right before the first terminator.
794  addInsertPoint(*It, /*Before*/ false);
795  return;
796  }
797  // Make sure Reg is not redefined by other terminators, otherwise
798  // we do not know how to split.
799  for (MachineBasicBlock::iterator It = MI, End = MI.getParent()->end();
800  ++It != End;)
801  // The machine verifier should reject this kind of code.
802  assert(It->modifiesRegister(MO.getReg(), &TRI) &&
803  "Do not know where to split");
804  // Split each outcoming edges.
805  MachineBasicBlock &Src = *MI.getParent();
806  for (auto &Succ : Src.successors())
807  addInsertPoint(Src, Succ);
808  }
809 }
810 
812  bool Before) {
813  addInsertPoint(*new InstrInsertPoint(MI, Before));
814 }
815 
817  bool Beginning) {
818  addInsertPoint(*new MBBInsertPoint(MBB, Beginning));
819 }
820 
822  MachineBasicBlock &Dst) {
823  addInsertPoint(*new EdgeInsertPoint(Src, Dst, P));
824 }
825 
828  CanMaterialize &= Point.canMaterialize();
829  HasSplit |= Point.isSplit();
830  InsertPoints.emplace_back(&Point);
831 }
832 
834  bool Before)
835  : InsertPoint(), Instr(Instr), Before(Before) {
836  // Since we do not support splitting, we do not need to update
837  // liveness and such, so do not do anything with P.
838  assert((!Before || !Instr.isPHI()) &&
839  "Splitting before phis requires more points");
840  assert((!Before || !Instr.getNextNode() || !Instr.getNextNode()->isPHI()) &&
841  "Splitting between phis does not make sense");
842 }
843 
844 void RegBankSelect::InstrInsertPoint::materialize() {
845  if (isSplit()) {
846  // Slice and return the beginning of the new block.
847  // If we need to split between the terminators, we theoritically
848  // need to know where the first and second set of terminators end
849  // to update the successors properly.
850  // Now, in pratice, we should have a maximum of 2 branch
851  // instructions; one conditional and one unconditional. Therefore
852  // we know how to update the successor by looking at the target of
853  // the unconditional branch.
854  // If we end up splitting at some point, then, we should update
855  // the liveness information and such. I.e., we would need to
856  // access P here.
857  // The machine verifier should actually make sure such cases
858  // cannot happen.
859  llvm_unreachable("Not yet implemented");
860  }
861  // Otherwise the insertion point is just the current or next
862  // instruction depending on Before. I.e., there is nothing to do
863  // here.
864 }
865 
867  // If the insertion point is after a terminator, we need to split.
868  if (!Before)
869  return Instr.isTerminator();
870  // If we insert before an instruction that is after a terminator,
871  // we are still after a terminator.
872  return Instr.getPrevNode() && Instr.getPrevNode()->isTerminator();
873 }
874 
876  // Even if we need to split, because we insert between terminators,
877  // this split has actually the same frequency as the instruction.
878  const MachineBlockFrequencyInfo *MBFI =
880  if (!MBFI)
881  return 1;
882  return MBFI->getBlockFreq(Instr.getParent()).getFrequency();
883 }
884 
886  const MachineBlockFrequencyInfo *MBFI =
888  if (!MBFI)
889  return 1;
890  return MBFI->getBlockFreq(&MBB).getFrequency();
891 }
892 
893 void RegBankSelect::EdgeInsertPoint::materialize() {
894  // If we end up repairing twice at the same place before materializing the
895  // insertion point, we may think we have to split an edge twice.
896  // We should have a factory for the insert point such that identical points
897  // are the same instance.
898  assert(Src.isSuccessor(DstOrSplit) && DstOrSplit->isPredecessor(&Src) &&
899  "This point has already been split");
900  MachineBasicBlock *NewBB = Src.SplitCriticalEdge(DstOrSplit, P);
901  assert(NewBB && "Invalid call to materialize");
902  // We reuse the destination block to hold the information of the new block.
903  DstOrSplit = NewBB;
904 }
905 
907  const MachineBlockFrequencyInfo *MBFI =
909  if (!MBFI)
910  return 1;
911  if (WasMaterialized)
912  return MBFI->getBlockFreq(DstOrSplit).getFrequency();
913 
914  const MachineBranchProbabilityInfo *MBPI =
916  if (!MBPI)
917  return 1;
918  // The basic block will be on the edge.
919  return (MBFI->getBlockFreq(&Src) * MBPI->getEdgeProbability(&Src, DstOrSplit))
920  .getFrequency();
921 }
922 
924  // If this is not a critical edge, we should not have used this insert
925  // point. Indeed, either the successor or the predecessor should
926  // have do.
927  assert(Src.succ_size() > 1 && DstOrSplit->pred_size() > 1 &&
928  "Edge is not critical");
929  return Src.canSplitCriticalEdge(DstOrSplit);
930 }
931 
932 RegBankSelect::MappingCost::MappingCost(const BlockFrequency &LocalFreq)
933  : LocalFreq(LocalFreq.getFrequency()) {}
934 
935 bool RegBankSelect::MappingCost::addLocalCost(uint64_t Cost) {
936  // Check if this overflows.
937  if (LocalCost + Cost < LocalCost) {
938  saturate();
939  return true;
940  }
941  LocalCost += Cost;
942  return isSaturated();
943 }
944 
945 bool RegBankSelect::MappingCost::addNonLocalCost(uint64_t Cost) {
946  // Check if this overflows.
947  if (NonLocalCost + Cost < NonLocalCost) {
948  saturate();
949  return true;
950  }
951  NonLocalCost += Cost;
952  return isSaturated();
953 }
954 
955 bool RegBankSelect::MappingCost::isSaturated() const {
956  return LocalCost == UINT64_MAX - 1 && NonLocalCost == UINT64_MAX &&
957  LocalFreq == UINT64_MAX;
958 }
959 
960 void RegBankSelect::MappingCost::saturate() {
961  *this = ImpossibleCost();
962  --LocalCost;
963 }
964 
965 RegBankSelect::MappingCost RegBankSelect::MappingCost::ImpossibleCost() {
966  return MappingCost(UINT64_MAX, UINT64_MAX, UINT64_MAX);
967 }
968 
969 bool RegBankSelect::MappingCost::operator<(const MappingCost &Cost) const {
970  // Sort out the easy cases.
971  if (*this == Cost)
972  return false;
973  // If one is impossible to realize the other is cheaper unless it is
974  // impossible as well.
975  if ((*this == ImpossibleCost()) || (Cost == ImpossibleCost()))
976  return (*this == ImpossibleCost()) < (Cost == ImpossibleCost());
977  // If one is saturated the other is cheaper, unless it is saturated
978  // as well.
979  if (isSaturated() || Cost.isSaturated())
980  return isSaturated() < Cost.isSaturated();
981  // At this point we know both costs hold sensible values.
982 
983  // If both values have a different base frequency, there is no much
984  // we can do but to scale everything.
985  // However, if they have the same base frequency we can avoid making
986  // complicated computation.
987  uint64_t ThisLocalAdjust;
988  uint64_t OtherLocalAdjust;
989  if (LLVM_LIKELY(LocalFreq == Cost.LocalFreq)) {
990 
991  // At this point, we know the local costs are comparable.
992  // Do the case that do not involve potential overflow first.
993  if (NonLocalCost == Cost.NonLocalCost)
994  // Since the non-local costs do not discriminate on the result,
995  // just compare the local costs.
996  return LocalCost < Cost.LocalCost;
997 
998  // The base costs are comparable so we may only keep the relative
999  // value to increase our chances of avoiding overflows.
1000  ThisLocalAdjust = 0;
1001  OtherLocalAdjust = 0;
1002  if (LocalCost < Cost.LocalCost)
1003  OtherLocalAdjust = Cost.LocalCost - LocalCost;
1004  else
1005  ThisLocalAdjust = LocalCost - Cost.LocalCost;
1006  } else {
1007  ThisLocalAdjust = LocalCost;
1008  OtherLocalAdjust = Cost.LocalCost;
1009  }
1010 
1011  // The non-local costs are comparable, just keep the relative value.
1012  uint64_t ThisNonLocalAdjust = 0;
1013  uint64_t OtherNonLocalAdjust = 0;
1014  if (NonLocalCost < Cost.NonLocalCost)
1015  OtherNonLocalAdjust = Cost.NonLocalCost - NonLocalCost;
1016  else
1017  ThisNonLocalAdjust = NonLocalCost - Cost.NonLocalCost;
1018  // Scale everything to make them comparable.
1019  uint64_t ThisScaledCost = ThisLocalAdjust * LocalFreq;
1020  // Check for overflow on that operation.
1021  bool ThisOverflows = ThisLocalAdjust && (ThisScaledCost < ThisLocalAdjust ||
1022  ThisScaledCost < LocalFreq);
1023  uint64_t OtherScaledCost = OtherLocalAdjust * Cost.LocalFreq;
1024  // Check for overflow on the last operation.
1025  bool OtherOverflows =
1026  OtherLocalAdjust &&
1027  (OtherScaledCost < OtherLocalAdjust || OtherScaledCost < Cost.LocalFreq);
1028  // Add the non-local costs.
1029  ThisOverflows |= ThisNonLocalAdjust &&
1030  ThisScaledCost + ThisNonLocalAdjust < ThisNonLocalAdjust;
1031  ThisScaledCost += ThisNonLocalAdjust;
1032  OtherOverflows |= OtherNonLocalAdjust &&
1033  OtherScaledCost + OtherNonLocalAdjust < OtherNonLocalAdjust;
1034  OtherScaledCost += OtherNonLocalAdjust;
1035  // If both overflows, we cannot compare without additional
1036  // precision, e.g., APInt. Just give up on that case.
1037  if (ThisOverflows && OtherOverflows)
1038  return false;
1039  // If one overflows but not the other, we can still compare.
1040  if (ThisOverflows || OtherOverflows)
1041  return ThisOverflows < OtherOverflows;
1042  // Otherwise, just compare the values.
1043  return ThisScaledCost < OtherScaledCost;
1044 }
1045 
1046 bool RegBankSelect::MappingCost::operator==(const MappingCost &Cost) const {
1047  return LocalCost == Cost.LocalCost && NonLocalCost == Cost.NonLocalCost &&
1048  LocalFreq == Cost.LocalFreq;
1049 }
1050 
1051 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1053  print(dbgs());
1054  dbgs() << '\n';
1055 }
1056 #endif
1057 
1059  if (*this == ImpossibleCost()) {
1060  OS << "impossible";
1061  return;
1062  }
1063  if (isSaturated()) {
1064  OS << "saturated";
1065  return;
1066  }
1067  OS << LocalFreq << " * " << LocalCost << " + " << NonLocalCost;
1068 }
Pass interface - Implemented by all &#39;passes&#39;.
Definition: Pass.h:80
bool canMaterialize() const override
Check whether this insertion point can be materialized.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
MachineBasicBlock * getMBB() const
SI Whole Quad Mode
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
Definition: ilist_node.h:288
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:464
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition: Utils.cpp:288
#define LLVM_LIKELY(EXPR)
Definition: Compiler.h:190
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
INITIALIZE_PASS_BEGIN(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false)
const MachineFunctionProperties & getProperties() const
Get the function properties.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
unsigned getCost() const
Get the cost.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
unsigned getReg() const
getReg - Returns the register number.
Reparing code needs to happen before InsertPoints.
unsigned Reg
uint64_t getFrequency() const
Returns the frequency as a fixpoint number scaled by the entry frequency.
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
static void dump(StringRef Title, SpillInfo const &Spills)
Definition: CoroFrame.cpp:298
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
F(f)
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
void setRegBank(unsigned Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
bool isPHI() const
Mode
List of the modes supported by the RegBankSelect pass.
Definition: RegBankSelect.h:95
void switchTo(RepairingKind NewKind)
Change the type of this repairing placement to NewKind.
iterator_range< succ_iterator > successors()
const PartialMapping * BreakDown
How the value is broken down between the different register banks.
void setMF(MachineFunction &MF)
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:50
Mark this repairing placement as impossible.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Abstract class used to represent an insertion point in a CFG.
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
virtual unsigned getBreakDownCost(const ValueMapping &ValMapping, const RegisterBank *CurBank=nullptr) const
Get the cost of using ValMapping to decompose a register.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:648
RepairingKind
Define the kind of action this repairing needs.
This file contains the simple types necessary to represent the attributes associated with functions a...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
iterator_range< SmallVectorImpl< unsigned >::const_iterator > getVRegs(unsigned OpIdx, bool ForDebug=false) const
Get all the virtual registers required to map the OpIdx-th operand of the instruction.
Target-Independent Code Generator Pass Configuration Options.
#define UINT64_MAX
Definition: DataTypes.h:83
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don&#39;t insert <empty> = Opcode <empty>.
MachineFunction & getMF()
Getter for the function we currently build.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
#define DEBUG_TYPE
reverse_iterator rend()
RepairingPlacement(MachineInstr &MI, unsigned OpIdx, const TargetRegisterInfo &TRI, Pass &P, RepairingKind Kind=RepairingKind::Insert)
Create a repairing placement for the OpIdx-th operand of MI.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
const RegisterBank * RegBank
Register bank where the partial value lives.
uint64_t frequency(const Pass &P) const override
Frequency of the insertion point.
===- MachineOptimizationRemarkEmitter.h - Opt Diagnostics -*- C++ -*-—===//
#define P(N)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:90
Insertion point on an edge.
virtual const InstructionMapping & getInstrMapping(const MachineInstr &MI) const
Get the mapping of the different operands of MI on the register bank.
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:642
BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const
getblockFreq - Return block frequency.
Represent the analysis usage information of a pass.
bool isTargetSpecificOpcode(unsigned Opcode)
Check whether the given Opcode is a target-specific opcode.
Definition: TargetOpcodes.h:36
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
void initializeRegBankSelectPass(PassRegistry &)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
cl::opt< bool > DisableGISelLegalityCheck
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr bool empty(const T &RangeOrContainer)
Test whether RangeOrContainer is empty. Similar to C++17 std::empty.
Definition: STLExtras.h:209
bool isValid() const
Check whether this object is valid.
bool verify(const MachineInstr &MI) const
Verifiy that this mapping makes sense for MI.
const MachineInstr * machineFunctionIsIllegal(const MachineFunction &MF)
Checks that MIR is fully legal, returns an illegal instruction if it&#39;s not, nullptr otherwise...
auto size(R &&Range, typename std::enable_if< std::is_same< typename std::iterator_traits< decltype(Range.begin())>::iterator_category, std::random_access_iterator_tag >::value, void >::type *=nullptr) -> decltype(std::distance(Range.begin(), Range.end()))
Get the size of a range.
Definition: STLExtras.h:1166
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
Struct used to represent the placement of a repairing point for a given operand.
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
Create a new MachineInstr which is a copy of Orig, identical in all ways except the instruction has n...
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:839
This class implements the register bank concept.
Definition: RegisterBank.h:28
Helper struct that represents how a value is mapped through different register banks.
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:940
A range adaptor for a pair of iterators.
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
virtual bool canMaterialize() const
Check whether this insertion point can be materialized.
bool isUnconditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which always transfers control flow to some other block...
Definition: MachineInstr.h:678
void createVRegs(unsigned OpIdx)
Create as many new virtual registers as needed for the mapping of the OpIdx-th operand.
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:617
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:253
bool operator==(const StringView &LHS, const StringView &RHS)
Definition: StringView.h:119
BranchProbability getEdgeProbability(const MachineBasicBlock *Src, const MachineBasicBlock *Dst) const
Representation of each machine instruction.
Definition: MachineInstr.h:63
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Insertion point before or after an instruction.
void emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:644
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
InstrInsertPoint(MachineInstr &Instr, bool Before=true)
Create an insertion point before (Before=true) or after Instr.
uint64_t frequency(const Pass &P) const override
Frequency of the insertion point.
bool WasMaterialized
Tell if the insert point has already been materialized.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:123
void addInsertPoint(MachineBasicBlock &MBB, bool Beginning)
iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
static cl::opt< RegBankSelect::Mode > RegBankSelectMode(cl::desc("Mode of the RegBankSelect pass"), cl::Hidden, cl::Optional, cl::values(clEnumValN(RegBankSelect::Mode::Fast, "regbankselect-fast", "Run the Fast mode (default mapping)"), clEnumValN(RegBankSelect::Mode::Greedy, "regbankselect-greedy", "Use the Greedy mode (best local mapping)")))
bool runOnMachineFunction(MachineFunction &MF) override
Walk through MF and assign a register bank to every virtual register that are still mapped to nothing...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool hasProperty(Property P) const
MachineBasicBlock * SplitCriticalEdge(MachineBasicBlock *Succ, Pass &P)
Split the critical edge from this block to the given successor block, and return the newly created bl...
bool operator<(int64_t V1, const APSInt &V2)
Definition: APSInt.h:325
unsigned NumBreakDowns
Number of partial mapping to break down this value.
AnalysisType * getAnalysisIfAvailable() const
getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information tha...
(Re)assign the register bank of the operand.
virtual bool isSplit() const
Does this point involve splitting an edge or block? As soon as ::getPoint is called and thus...
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
IRTranslator LLVM IR MI
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
uint64_t frequency(const Pass &P) const override
Frequency of the insertion point.
unsigned getNumOperands() const
Get the number of operands.
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext&#39;s diagnostic stream...
Definition: Utils.cpp:155
Insertion point at the beginning or end of a basic block.
Nothing to repair, just drop this action.
bool isSplit() const override
Does this point involve splitting an edge or block? As soon as ::getPoint is called and thus...