LLVM  10.0.0svn
WebAssemblyInstrInfo.cpp
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1 //===-- WebAssemblyInstrInfo.cpp - WebAssembly Instruction Information ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file contains the WebAssembly implementation of the
11 /// TargetInstrInfo class.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "WebAssemblyInstrInfo.h"
18 #include "WebAssemblySubtarget.h"
23 using namespace llvm;
24 
25 #define DEBUG_TYPE "wasm-instr-info"
26 
27 #define GET_INSTRINFO_CTOR_DTOR
28 #include "WebAssemblyGenInstrInfo.inc"
29 
30 // defines WebAssembly::getNamedOperandIdx
31 #define GET_INSTRINFO_NAMED_OPS
32 #include "WebAssemblyGenInstrInfo.inc"
33 
35  : WebAssemblyGenInstrInfo(WebAssembly::ADJCALLSTACKDOWN,
36  WebAssembly::ADJCALLSTACKUP,
37  WebAssembly::CATCHRET),
38  RI(STI.getTargetTriple()) {}
39 
41  const MachineInstr &MI, AAResults *AA) const {
42  switch (MI.getOpcode()) {
43  case WebAssembly::CONST_I32:
44  case WebAssembly::CONST_I64:
45  case WebAssembly::CONST_F32:
46  case WebAssembly::CONST_F64:
47  // isReallyTriviallyReMaterializableGeneric misses these because of the
48  // ARGUMENTS implicit def, so we manualy override it here.
49  return true;
50  default:
51  return false;
52  }
53 }
54 
57  const DebugLoc &DL, unsigned DestReg,
58  unsigned SrcReg, bool KillSrc) const {
59  // This method is called by post-RA expansion, which expects only pregs to
60  // exist. However we need to handle both here.
61  auto &MRI = MBB.getParent()->getRegInfo();
62  const TargetRegisterClass *RC =
64  ? MRI.getRegClass(DestReg)
65  : MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg);
66 
67  unsigned CopyOpcode;
68  if (RC == &WebAssembly::I32RegClass)
69  CopyOpcode = WebAssembly::COPY_I32;
70  else if (RC == &WebAssembly::I64RegClass)
71  CopyOpcode = WebAssembly::COPY_I64;
72  else if (RC == &WebAssembly::F32RegClass)
73  CopyOpcode = WebAssembly::COPY_F32;
74  else if (RC == &WebAssembly::F64RegClass)
75  CopyOpcode = WebAssembly::COPY_F64;
76  else if (RC == &WebAssembly::V128RegClass)
77  CopyOpcode = WebAssembly::COPY_V128;
78  else if (RC == &WebAssembly::EXNREFRegClass)
79  CopyOpcode = WebAssembly::COPY_EXNREF;
80  else
81  llvm_unreachable("Unexpected register class");
82 
83  BuildMI(MBB, I, DL, get(CopyOpcode), DestReg)
84  .addReg(SrcReg, KillSrc ? RegState::Kill : 0);
85 }
86 
88  MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const {
89  // If the operands are stackified, we can't reorder them.
92  if (MFI.isVRegStackified(MI.getOperand(OpIdx1).getReg()) ||
93  MFI.isVRegStackified(MI.getOperand(OpIdx2).getReg()))
94  return nullptr;
95 
96  // Otherwise use the default implementation.
97  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
98 }
99 
100 // Branch analysis.
102  MachineBasicBlock *&TBB,
103  MachineBasicBlock *&FBB,
105  bool /*AllowModify*/) const {
106  const auto &MFI = *MBB.getParent()->getInfo<WebAssemblyFunctionInfo>();
107  // WebAssembly has control flow that doesn't have explicit branches or direct
108  // fallthrough (e.g. try/catch), which can't be modeled by analyzeBranch. It
109  // is created after CFGStackify.
110  if (MFI.isCFGStackified())
111  return true;
112 
113  bool HaveCond = false;
114  for (MachineInstr &MI : MBB.terminators()) {
115  switch (MI.getOpcode()) {
116  default:
117  // Unhandled instruction; bail out.
118  return true;
119  case WebAssembly::BR_IF:
120  if (HaveCond)
121  return true;
123  Cond.push_back(MI.getOperand(1));
124  TBB = MI.getOperand(0).getMBB();
125  HaveCond = true;
126  break;
127  case WebAssembly::BR_UNLESS:
128  if (HaveCond)
129  return true;
131  Cond.push_back(MI.getOperand(1));
132  TBB = MI.getOperand(0).getMBB();
133  HaveCond = true;
134  break;
135  case WebAssembly::BR:
136  if (!HaveCond)
137  TBB = MI.getOperand(0).getMBB();
138  else
139  FBB = MI.getOperand(0).getMBB();
140  break;
141  case WebAssembly::BR_ON_EXN:
142  if (HaveCond)
143  return true;
145  Cond.push_back(MI.getOperand(2));
146  TBB = MI.getOperand(0).getMBB();
147  HaveCond = true;
148  break;
149  }
150  if (MI.isBarrier())
151  break;
152  }
153 
154  return false;
155 }
156 
158  int *BytesRemoved) const {
159  assert(!BytesRemoved && "code size not handled");
160 
162  unsigned Count = 0;
163 
164  while (I != MBB.instr_begin()) {
165  --I;
166  if (I->isDebugInstr())
167  continue;
168  if (!I->isTerminator())
169  break;
170  // Remove the branch.
171  I->eraseFromParent();
172  I = MBB.instr_end();
173  ++Count;
174  }
175 
176  return Count;
177 }
178 
181  ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
182  assert(!BytesAdded && "code size not handled");
183 
184  if (Cond.empty()) {
185  if (!TBB)
186  return 0;
187 
188  BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(TBB);
189  return 1;
190  }
191 
192  assert(Cond.size() == 2 && "Expected a flag and a successor block");
193 
194  MachineFunction &MF = *MBB.getParent();
195  auto &MRI = MF.getRegInfo();
196  bool IsBrOnExn = Cond[1].isReg() && MRI.getRegClass(Cond[1].getReg()) ==
197  &WebAssembly::EXNREFRegClass;
198 
199  if (Cond[0].getImm()) {
200  if (IsBrOnExn) {
201  const char *CPPExnSymbol = MF.createExternalSymbolName("__cpp_exception");
202  BuildMI(&MBB, DL, get(WebAssembly::BR_ON_EXN))
203  .addMBB(TBB)
204  .addExternalSymbol(CPPExnSymbol)
205  .add(Cond[1]);
206  } else
207  BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]);
208  } else {
209  assert(!IsBrOnExn && "br_on_exn does not have a reversed condition");
210  BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS)).addMBB(TBB).add(Cond[1]);
211  }
212  if (!FBB)
213  return 1;
214 
215  BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(FBB);
216  return 2;
217 }
218 
220  SmallVectorImpl<MachineOperand> &Cond) const {
221  assert(Cond.size() == 2 && "Expected a flag and a condition expression");
222 
223  // br_on_exn's condition cannot be reversed
224  MachineFunction &MF = *Cond[1].getParent()->getParent()->getParent();
225  auto &MRI = MF.getRegInfo();
226  if (Cond[1].isReg() &&
227  MRI.getRegClass(Cond[1].getReg()) == &WebAssembly::EXNREFRegClass)
228  return true;
229 
230  Cond.front() = MachineOperand::CreateImm(!Cond.front().getImm());
231  return false;
232 }
static bool isReg(const MCInst &MI, unsigned OpNo)
const MachineInstrBuilder & add(const MachineOperand &MO) const
instr_iterator instr_begin()
instr_iterator instr_end()
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
A debug info location.
Definition: DebugLoc.h:33
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
iterator_range< iterator > terminators()
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:410
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:665
unsigned const MachineRegisterInfo * MRI
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
This file provides WebAssembly-specific target descriptions.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
size_t size() const
Definition: SmallVector.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This file declares the WebAssembly-specific subclass of TargetSubtarget.
Iterator for intrusive lists based on ilist_node.
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AAResults *AA) const override
This file contains the WebAssembly implementation of the TargetInstrInfo class.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
CATCHRET - Represents a return from a catch block funclet.
Definition: ISDOpcodes.h:725
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:255
Representation of each machine instruction.
Definition: MachineInstr.h:63
This class is derived from MachineFunctionInfo and contains private WebAssembly-specific information ...
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
WebAssemblyInstrInfo(const WebAssemblySubtarget &STI)
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:58
This file declares WebAssembly-specific per-machine-function information.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:69
IRTranslator LLVM IR MI
Register getReg() const
getReg - Returns the register number.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:415
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:143