LLVM  8.0.0svn
WebAssemblyInstrInfo.cpp
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1 //===-- WebAssemblyInstrInfo.cpp - WebAssembly Instruction Information ----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// This file contains the WebAssembly implementation of the
12 /// TargetInstrInfo class.
13 ///
14 //===----------------------------------------------------------------------===//
15 
16 #include "WebAssemblyInstrInfo.h"
19 #include "WebAssemblySubtarget.h"
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "wasm-instr-info"
27 
28 #define GET_INSTRINFO_CTOR_DTOR
29 #include "WebAssemblyGenInstrInfo.inc"
30 
32  : WebAssemblyGenInstrInfo(WebAssembly::ADJCALLSTACKDOWN,
33  WebAssembly::ADJCALLSTACKUP,
34  WebAssembly::CATCHRET),
35  RI(STI.getTargetTriple()) {}
36 
38  const MachineInstr &MI, AliasAnalysis *AA) const {
39  switch (MI.getOpcode()) {
40  case WebAssembly::CONST_I32:
41  case WebAssembly::CONST_I64:
42  case WebAssembly::CONST_F32:
43  case WebAssembly::CONST_F64:
44  // isReallyTriviallyReMaterializableGeneric misses these because of the
45  // ARGUMENTS implicit def, so we manualy override it here.
46  return true;
47  default:
48  return false;
49  }
50 }
51 
54  const DebugLoc &DL, unsigned DestReg,
55  unsigned SrcReg, bool KillSrc) const {
56  // This method is called by post-RA expansion, which expects only pregs to
57  // exist. However we need to handle both here.
58  auto &MRI = MBB.getParent()->getRegInfo();
59  const TargetRegisterClass *RC =
61  ? MRI.getRegClass(DestReg)
62  : MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg);
63 
64  unsigned CopyOpcode;
65  if (RC == &WebAssembly::I32RegClass)
66  CopyOpcode = WebAssembly::COPY_I32;
67  else if (RC == &WebAssembly::I64RegClass)
68  CopyOpcode = WebAssembly::COPY_I64;
69  else if (RC == &WebAssembly::F32RegClass)
70  CopyOpcode = WebAssembly::COPY_F32;
71  else if (RC == &WebAssembly::F64RegClass)
72  CopyOpcode = WebAssembly::COPY_F64;
73  else
74  llvm_unreachable("Unexpected register class");
75 
76  BuildMI(MBB, I, DL, get(CopyOpcode), DestReg)
77  .addReg(SrcReg, KillSrc ? RegState::Kill : 0);
78 }
79 
81  MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const {
82  // If the operands are stackified, we can't reorder them.
85  if (MFI.isVRegStackified(MI.getOperand(OpIdx1).getReg()) ||
86  MFI.isVRegStackified(MI.getOperand(OpIdx2).getReg()))
87  return nullptr;
88 
89  // Otherwise use the default implementation.
90  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
91 }
92 
93 // Branch analysis.
95  MachineBasicBlock *&TBB,
96  MachineBasicBlock *&FBB,
98  bool /*AllowModify*/) const {
99  bool HaveCond = false;
100  for (MachineInstr &MI : MBB.terminators()) {
101  switch (MI.getOpcode()) {
102  default:
103  // Unhandled instruction; bail out.
104  return true;
105  case WebAssembly::BR_IF:
106  if (HaveCond)
107  return true;
108  // If we're running after CFGStackify, we can't optimize further.
109  if (!MI.getOperand(0).isMBB())
110  return true;
112  Cond.push_back(MI.getOperand(1));
113  TBB = MI.getOperand(0).getMBB();
114  HaveCond = true;
115  break;
116  case WebAssembly::BR_UNLESS:
117  if (HaveCond)
118  return true;
119  // If we're running after CFGStackify, we can't optimize further.
120  if (!MI.getOperand(0).isMBB())
121  return true;
123  Cond.push_back(MI.getOperand(1));
124  TBB = MI.getOperand(0).getMBB();
125  HaveCond = true;
126  break;
127  case WebAssembly::BR:
128  // If we're running after CFGStackify, we can't optimize further.
129  if (!MI.getOperand(0).isMBB())
130  return true;
131  if (!HaveCond)
132  TBB = MI.getOperand(0).getMBB();
133  else
134  FBB = MI.getOperand(0).getMBB();
135  break;
136  }
137  if (MI.isBarrier())
138  break;
139  }
140 
141  return false;
142 }
143 
145  int *BytesRemoved) const {
146  assert(!BytesRemoved && "code size not handled");
147 
149  unsigned Count = 0;
150 
151  while (I != MBB.instr_begin()) {
152  --I;
153  if (I->isDebugInstr())
154  continue;
155  if (!I->isTerminator())
156  break;
157  // Remove the branch.
158  I->eraseFromParent();
159  I = MBB.instr_end();
160  ++Count;
161  }
162 
163  return Count;
164 }
165 
168  ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
169  assert(!BytesAdded && "code size not handled");
170 
171  if (Cond.empty()) {
172  if (!TBB)
173  return 0;
174 
175  BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(TBB);
176  return 1;
177  }
178 
179  assert(Cond.size() == 2 && "Expected a flag and a successor block");
180 
181  if (Cond[0].getImm()) {
182  BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]);
183  } else {
184  BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS)).addMBB(TBB).add(Cond[1]);
185  }
186  if (!FBB)
187  return 1;
188 
189  BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(FBB);
190  return 2;
191 }
192 
194  SmallVectorImpl<MachineOperand> &Cond) const {
195  assert(Cond.size() == 2 && "Expected a flag and a successor block");
196  Cond.front() = MachineOperand::CreateImm(!Cond.front().getImm());
197  return false;
198 }
const MachineInstrBuilder & add(const MachineOperand &MO) const
instr_iterator instr_begin()
instr_iterator instr_end()
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const override
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
A debug info location.
Definition: DebugLoc.h:34
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
iterator_range< iterator > terminators()
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:409
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:598
unsigned const MachineRegisterInfo * MRI
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
This file provides WebAssembly-specific target descriptions.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
size_t size() const
Definition: SmallVector.h:53
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This file declares the WebAssembly-specific subclass of TargetSubtarget.
Iterator for intrusive lists based on ilist_node.
This file contains the WebAssembly implementation of the TargetInstrInfo class.
int64_t getImm() const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
CATCHRET - Represents a return from a catch block funclet.
Definition: ISDOpcodes.h:655
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:254
Representation of each machine instruction.
Definition: MachineInstr.h:64
This class is derived from MachineFunctionInfo and contains private WebAssembly-specific information ...
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
WebAssemblyInstrInfo(const WebAssemblySubtarget &STI)
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:58
This file declares WebAssembly-specific per-machine-function information.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
IRTranslator LLVM IR MI
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:144