LLVM  6.0.0svn
WebAssemblyInstrInfo.cpp
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1 //===-- WebAssemblyInstrInfo.cpp - WebAssembly Instruction Information ----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// \brief This file contains the WebAssembly implementation of the
12 /// TargetInstrInfo class.
13 ///
14 //===----------------------------------------------------------------------===//
15 
16 #include "WebAssemblyInstrInfo.h"
19 #include "WebAssemblySubtarget.h"
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "wasm-instr-info"
27 
28 #define GET_INSTRINFO_CTOR_DTOR
29 #include "WebAssemblyGenInstrInfo.inc"
30 
32  : WebAssemblyGenInstrInfo(WebAssembly::ADJCALLSTACKDOWN,
33  WebAssembly::ADJCALLSTACKUP),
34  RI(STI.getTargetTriple()) {}
35 
37  const MachineInstr &MI, AliasAnalysis *AA) const {
38  switch (MI.getOpcode()) {
39  case WebAssembly::CONST_I32:
40  case WebAssembly::CONST_I64:
41  case WebAssembly::CONST_F32:
42  case WebAssembly::CONST_F64:
43  // isReallyTriviallyReMaterializableGeneric misses these because of the
44  // ARGUMENTS implicit def, so we manualy override it here.
45  return true;
46  default:
47  return false;
48  }
49 }
50 
53  const DebugLoc &DL, unsigned DestReg,
54  unsigned SrcReg, bool KillSrc) const {
55  // This method is called by post-RA expansion, which expects only pregs to
56  // exist. However we need to handle both here.
57  auto &MRI = MBB.getParent()->getRegInfo();
58  const TargetRegisterClass *RC =
60  ? MRI.getRegClass(DestReg)
61  : MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg);
62 
63  unsigned CopyOpcode;
64  if (RC == &WebAssembly::I32RegClass)
65  CopyOpcode = WebAssembly::COPY_I32;
66  else if (RC == &WebAssembly::I64RegClass)
67  CopyOpcode = WebAssembly::COPY_I64;
68  else if (RC == &WebAssembly::F32RegClass)
69  CopyOpcode = WebAssembly::COPY_F32;
70  else if (RC == &WebAssembly::F64RegClass)
71  CopyOpcode = WebAssembly::COPY_F64;
72  else
73  llvm_unreachable("Unexpected register class");
74 
75  BuildMI(MBB, I, DL, get(CopyOpcode), DestReg)
76  .addReg(SrcReg, KillSrc ? RegState::Kill : 0);
77 }
78 
81  unsigned OpIdx1,
82  unsigned OpIdx2) const {
83  // If the operands are stackified, we can't reorder them.
86  if (MFI.isVRegStackified(MI.getOperand(OpIdx1).getReg()) ||
87  MFI.isVRegStackified(MI.getOperand(OpIdx2).getReg()))
88  return nullptr;
89 
90  // Otherwise use the default implementation.
91  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
92 }
93 
94 // Branch analysis.
96  MachineBasicBlock *&TBB,
97  MachineBasicBlock *&FBB,
99  bool /*AllowModify*/) const {
100  bool HaveCond = false;
101  for (MachineInstr &MI : MBB.terminators()) {
102  switch (MI.getOpcode()) {
103  default:
104  // Unhandled instruction; bail out.
105  return true;
106  case WebAssembly::BR_IF:
107  if (HaveCond)
108  return true;
109  // If we're running after CFGStackify, we can't optimize further.
110  if (!MI.getOperand(0).isMBB())
111  return true;
113  Cond.push_back(MI.getOperand(1));
114  TBB = MI.getOperand(0).getMBB();
115  HaveCond = true;
116  break;
117  case WebAssembly::BR_UNLESS:
118  if (HaveCond)
119  return true;
120  // If we're running after CFGStackify, we can't optimize further.
121  if (!MI.getOperand(0).isMBB())
122  return true;
124  Cond.push_back(MI.getOperand(1));
125  TBB = MI.getOperand(0).getMBB();
126  HaveCond = true;
127  break;
128  case WebAssembly::BR:
129  // If we're running after CFGStackify, we can't optimize further.
130  if (!MI.getOperand(0).isMBB())
131  return true;
132  if (!HaveCond)
133  TBB = MI.getOperand(0).getMBB();
134  else
135  FBB = MI.getOperand(0).getMBB();
136  break;
137  }
138  if (MI.isBarrier())
139  break;
140  }
141 
142  return false;
143 }
144 
146  int *BytesRemoved) const {
147  assert(!BytesRemoved && "code size not handled");
148 
150  unsigned Count = 0;
151 
152  while (I != MBB.instr_begin()) {
153  --I;
154  if (I->isDebugValue())
155  continue;
156  if (!I->isTerminator())
157  break;
158  // Remove the branch.
159  I->eraseFromParent();
160  I = MBB.instr_end();
161  ++Count;
162  }
163 
164  return Count;
165 }
166 
168  MachineBasicBlock *TBB,
169  MachineBasicBlock *FBB,
171  const DebugLoc &DL,
172  int *BytesAdded) const {
173  assert(!BytesAdded && "code size not handled");
174 
175  if (Cond.empty()) {
176  if (!TBB)
177  return 0;
178 
179  BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(TBB);
180  return 1;
181  }
182 
183  assert(Cond.size() == 2 && "Expected a flag and a successor block");
184 
185  if (Cond[0].getImm()) {
186  BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]);
187  } else {
188  BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS)).addMBB(TBB).add(Cond[1]);
189  }
190  if (!FBB)
191  return 1;
192 
193  BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(FBB);
194  return 2;
195 }
196 
198  SmallVectorImpl<MachineOperand> &Cond) const {
199  assert(Cond.size() == 2 && "Expected a flag and a successor block");
200  Cond.front() = MachineOperand::CreateImm(!Cond.front().getImm());
201  return false;
202 }
const MachineInstrBuilder & add(const MachineOperand &MO) const
instr_iterator instr_begin()
instr_iterator instr_end()
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const override
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
A debug info location.
Definition: DebugLoc.h:34
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
iterator_range< iterator > terminators()
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:596
unsigned const MachineRegisterInfo * MRI
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
This file provides WebAssembly-specific target descriptions.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This file declares the WebAssembly-specific subclass of TargetSubtarget.
Iterator for intrusive lists based on ilist_node.
This file contains the WebAssembly implementation of the TargetInstrInfo class.
int64_t getImm() const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
Representation of each machine instruction.
Definition: MachineInstr.h:59
This class is derived from MachineFunctionInfo and contains private WebAssembly-specific information ...
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
WebAssemblyInstrInfo(const WebAssemblySubtarget &STI)
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:58
This file declares WebAssembly-specific per-machine-function information.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
IRTranslator LLVM IR MI
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:144