LLVM  9.0.0svn
WebAssemblyInstrInfo.cpp
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1 //===-- WebAssemblyInstrInfo.cpp - WebAssembly Instruction Information ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file contains the WebAssembly implementation of the
11 /// TargetInstrInfo class.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "WebAssemblyInstrInfo.h"
18 #include "WebAssemblySubtarget.h"
23 using namespace llvm;
24 
25 #define DEBUG_TYPE "wasm-instr-info"
26 
27 #define GET_INSTRINFO_CTOR_DTOR
28 #include "WebAssemblyGenInstrInfo.inc"
29 
30 // defines WebAssembly::getNamedOperandIdx
31 #define GET_INSTRINFO_NAMED_OPS
32 #include "WebAssemblyGenInstrInfo.inc"
33 
35  : WebAssemblyGenInstrInfo(WebAssembly::ADJCALLSTACKDOWN,
36  WebAssembly::ADJCALLSTACKUP,
37  WebAssembly::CATCHRET),
38  RI(STI.getTargetTriple()) {}
39 
41  const MachineInstr &MI, AliasAnalysis *AA) const {
42  switch (MI.getOpcode()) {
43  case WebAssembly::CONST_I32:
44  case WebAssembly::CONST_I64:
45  case WebAssembly::CONST_F32:
46  case WebAssembly::CONST_F64:
47  // isReallyTriviallyReMaterializableGeneric misses these because of the
48  // ARGUMENTS implicit def, so we manualy override it here.
49  return true;
50  default:
51  return false;
52  }
53 }
54 
57  const DebugLoc &DL, unsigned DestReg,
58  unsigned SrcReg, bool KillSrc) const {
59  // This method is called by post-RA expansion, which expects only pregs to
60  // exist. However we need to handle both here.
61  auto &MRI = MBB.getParent()->getRegInfo();
62  const TargetRegisterClass *RC =
64  ? MRI.getRegClass(DestReg)
65  : MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg);
66 
67  unsigned CopyOpcode;
68  if (RC == &WebAssembly::I32RegClass)
69  CopyOpcode = WebAssembly::COPY_I32;
70  else if (RC == &WebAssembly::I64RegClass)
71  CopyOpcode = WebAssembly::COPY_I64;
72  else if (RC == &WebAssembly::F32RegClass)
73  CopyOpcode = WebAssembly::COPY_F32;
74  else if (RC == &WebAssembly::F64RegClass)
75  CopyOpcode = WebAssembly::COPY_F64;
76  else if (RC == &WebAssembly::V128RegClass)
77  CopyOpcode = WebAssembly::COPY_V128;
78  else
79  llvm_unreachable("Unexpected register class");
80 
81  BuildMI(MBB, I, DL, get(CopyOpcode), DestReg)
82  .addReg(SrcReg, KillSrc ? RegState::Kill : 0);
83 }
84 
86  MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const {
87  // If the operands are stackified, we can't reorder them.
90  if (MFI.isVRegStackified(MI.getOperand(OpIdx1).getReg()) ||
91  MFI.isVRegStackified(MI.getOperand(OpIdx2).getReg()))
92  return nullptr;
93 
94  // Otherwise use the default implementation.
95  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
96 }
97 
98 // Branch analysis.
100  MachineBasicBlock *&TBB,
101  MachineBasicBlock *&FBB,
103  bool /*AllowModify*/) const {
104  const auto &MFI = *MBB.getParent()->getInfo<WebAssemblyFunctionInfo>();
105  // WebAssembly has control flow that doesn't have explicit branches or direct
106  // fallthrough (e.g. try/catch), which can't be modeled by analyzeBranch. It
107  // is created after CFGStackify.
108  if (MFI.isCFGStackified())
109  return true;
110 
111  bool HaveCond = false;
112  for (MachineInstr &MI : MBB.terminators()) {
113  switch (MI.getOpcode()) {
114  default:
115  // Unhandled instruction; bail out.
116  return true;
117  case WebAssembly::BR_IF:
118  if (HaveCond)
119  return true;
121  Cond.push_back(MI.getOperand(1));
122  TBB = MI.getOperand(0).getMBB();
123  HaveCond = true;
124  break;
125  case WebAssembly::BR_UNLESS:
126  if (HaveCond)
127  return true;
129  Cond.push_back(MI.getOperand(1));
130  TBB = MI.getOperand(0).getMBB();
131  HaveCond = true;
132  break;
133  case WebAssembly::BR:
134  if (!HaveCond)
135  TBB = MI.getOperand(0).getMBB();
136  else
137  FBB = MI.getOperand(0).getMBB();
138  break;
139  case WebAssembly::BR_ON_EXN:
140  if (HaveCond)
141  return true;
143  Cond.push_back(MI.getOperand(2));
144  TBB = MI.getOperand(0).getMBB();
145  HaveCond = true;
146  break;
147  }
148  if (MI.isBarrier())
149  break;
150  }
151 
152  return false;
153 }
154 
156  int *BytesRemoved) const {
157  assert(!BytesRemoved && "code size not handled");
158 
160  unsigned Count = 0;
161 
162  while (I != MBB.instr_begin()) {
163  --I;
164  if (I->isDebugInstr())
165  continue;
166  if (!I->isTerminator())
167  break;
168  // Remove the branch.
169  I->eraseFromParent();
170  I = MBB.instr_end();
171  ++Count;
172  }
173 
174  return Count;
175 }
176 
179  ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
180  assert(!BytesAdded && "code size not handled");
181 
182  if (Cond.empty()) {
183  if (!TBB)
184  return 0;
185 
186  BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(TBB);
187  return 1;
188  }
189 
190  assert(Cond.size() == 2 && "Expected a flag and a successor block");
191 
192  MachineFunction &MF = *MBB.getParent();
193  auto &MRI = MF.getRegInfo();
194  bool IsBrOnExn = Cond[1].isReg() && MRI.getRegClass(Cond[1].getReg()) ==
195  &WebAssembly::EXCEPT_REFRegClass;
196 
197  if (Cond[0].getImm()) {
198  if (IsBrOnExn) {
199  const char *CPPExnSymbol = MF.createExternalSymbolName("__cpp_exception");
200  BuildMI(&MBB, DL, get(WebAssembly::BR_ON_EXN))
201  .addMBB(TBB)
202  .addExternalSymbol(CPPExnSymbol)
203  .add(Cond[1]);
204  } else
205  BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]);
206  } else {
207  assert(!IsBrOnExn && "br_on_exn does not have a reversed condition");
208  BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS)).addMBB(TBB).add(Cond[1]);
209  }
210  if (!FBB)
211  return 1;
212 
213  BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(FBB);
214  return 2;
215 }
216 
218  SmallVectorImpl<MachineOperand> &Cond) const {
219  assert(Cond.size() == 2 && "Expected a flag and a condition expression");
220 
221  // br_on_exn's condition cannot be reversed
222  MachineFunction &MF = *Cond[1].getParent()->getParent()->getParent();
223  auto &MRI = MF.getRegInfo();
224  if (Cond[1].isReg() &&
225  MRI.getRegClass(Cond[1].getReg()) == &WebAssembly::EXCEPT_REFRegClass)
226  return true;
227 
228  Cond.front() = MachineOperand::CreateImm(!Cond.front().getImm());
229  return false;
230 }
static bool isReg(const MCInst &MI, unsigned OpNo)
const MachineInstrBuilder & add(const MachineOperand &MO) const
instr_iterator instr_begin()
instr_iterator instr_end()
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const override
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
A debug info location.
Definition: DebugLoc.h:33
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
iterator_range< iterator > terminators()
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:630
unsigned const MachineRegisterInfo * MRI
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
This file provides WebAssembly-specific target descriptions.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
size_t size() const
Definition: SmallVector.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This file declares the WebAssembly-specific subclass of TargetSubtarget.
Iterator for intrusive lists based on ilist_node.
This file contains the WebAssembly implementation of the TargetInstrInfo class.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
CATCHRET - Represents a return from a catch block funclet.
Definition: ISDOpcodes.h:690
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:253
Representation of each machine instruction.
Definition: MachineInstr.h:63
This class is derived from MachineFunctionInfo and contains private WebAssembly-specific information ...
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
WebAssemblyInstrInfo(const WebAssemblySubtarget &STI)
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned char TargetFlags=0) const
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:58
This file declares WebAssembly-specific per-machine-function information.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
IRTranslator LLVM IR MI
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:143