LLVM  11.0.0git
WebAssemblyInstrInfo.cpp
Go to the documentation of this file.
1 //===-- WebAssemblyInstrInfo.cpp - WebAssembly Instruction Information ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file contains the WebAssembly implementation of the
11 /// TargetInstrInfo class.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "WebAssemblyInstrInfo.h"
17 #include "WebAssembly.h"
19 #include "WebAssemblySubtarget.h"
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "wasm-instr-info"
27 
28 #define GET_INSTRINFO_CTOR_DTOR
29 #include "WebAssemblyGenInstrInfo.inc"
30 
31 // defines WebAssembly::getNamedOperandIdx
32 #define GET_INSTRINFO_NAMED_OPS
33 #include "WebAssemblyGenInstrInfo.inc"
34 
36  : WebAssemblyGenInstrInfo(WebAssembly::ADJCALLSTACKDOWN,
37  WebAssembly::ADJCALLSTACKUP,
38  WebAssembly::CATCHRET),
39  RI(STI.getTargetTriple()) {}
40 
42  const MachineInstr &MI, AAResults *AA) const {
43  switch (MI.getOpcode()) {
44  case WebAssembly::CONST_I32:
45  case WebAssembly::CONST_I64:
46  case WebAssembly::CONST_F32:
47  case WebAssembly::CONST_F64:
48  // isReallyTriviallyReMaterializableGeneric misses these because of the
49  // ARGUMENTS implicit def, so we manualy override it here.
50  return true;
51  default:
52  return false;
53  }
54 }
55 
58  const DebugLoc &DL, MCRegister DestReg,
59  MCRegister SrcReg, bool KillSrc) const {
60  // This method is called by post-RA expansion, which expects only pregs to
61  // exist. However we need to handle both here.
62  auto &MRI = MBB.getParent()->getRegInfo();
63  const TargetRegisterClass *RC =
65  ? MRI.getRegClass(DestReg)
66  : MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg);
67 
68  unsigned CopyOpcode;
69  if (RC == &WebAssembly::I32RegClass)
70  CopyOpcode = WebAssembly::COPY_I32;
71  else if (RC == &WebAssembly::I64RegClass)
72  CopyOpcode = WebAssembly::COPY_I64;
73  else if (RC == &WebAssembly::F32RegClass)
74  CopyOpcode = WebAssembly::COPY_F32;
75  else if (RC == &WebAssembly::F64RegClass)
76  CopyOpcode = WebAssembly::COPY_F64;
77  else if (RC == &WebAssembly::V128RegClass)
78  CopyOpcode = WebAssembly::COPY_V128;
79  else if (RC == &WebAssembly::EXNREFRegClass)
80  CopyOpcode = WebAssembly::COPY_EXNREF;
81  else
82  llvm_unreachable("Unexpected register class");
83 
84  BuildMI(MBB, I, DL, get(CopyOpcode), DestReg)
85  .addReg(SrcReg, KillSrc ? RegState::Kill : 0);
86 }
87 
89  MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const {
90  // If the operands are stackified, we can't reorder them.
93  if (MFI.isVRegStackified(MI.getOperand(OpIdx1).getReg()) ||
94  MFI.isVRegStackified(MI.getOperand(OpIdx2).getReg()))
95  return nullptr;
96 
97  // Otherwise use the default implementation.
98  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
99 }
100 
101 // Branch analysis.
103  MachineBasicBlock *&TBB,
104  MachineBasicBlock *&FBB,
106  bool /*AllowModify*/) const {
107  const auto &MFI = *MBB.getParent()->getInfo<WebAssemblyFunctionInfo>();
108  // WebAssembly has control flow that doesn't have explicit branches or direct
109  // fallthrough (e.g. try/catch), which can't be modeled by analyzeBranch. It
110  // is created after CFGStackify.
111  if (MFI.isCFGStackified())
112  return true;
113 
114  bool HaveCond = false;
115  for (MachineInstr &MI : MBB.terminators()) {
116  switch (MI.getOpcode()) {
117  default:
118  // Unhandled instruction; bail out.
119  return true;
120  case WebAssembly::BR_IF:
121  if (HaveCond)
122  return true;
124  Cond.push_back(MI.getOperand(1));
125  TBB = MI.getOperand(0).getMBB();
126  HaveCond = true;
127  break;
128  case WebAssembly::BR_UNLESS:
129  if (HaveCond)
130  return true;
132  Cond.push_back(MI.getOperand(1));
133  TBB = MI.getOperand(0).getMBB();
134  HaveCond = true;
135  break;
136  case WebAssembly::BR:
137  if (!HaveCond)
138  TBB = MI.getOperand(0).getMBB();
139  else
140  FBB = MI.getOperand(0).getMBB();
141  break;
142  case WebAssembly::BR_ON_EXN:
143  if (HaveCond)
144  return true;
146  Cond.push_back(MI.getOperand(2));
147  TBB = MI.getOperand(0).getMBB();
148  HaveCond = true;
149  break;
150  }
151  if (MI.isBarrier())
152  break;
153  }
154 
155  return false;
156 }
157 
159  int *BytesRemoved) const {
160  assert(!BytesRemoved && "code size not handled");
161 
163  unsigned Count = 0;
164 
165  while (I != MBB.instr_begin()) {
166  --I;
167  if (I->isDebugInstr())
168  continue;
169  if (!I->isTerminator())
170  break;
171  // Remove the branch.
172  I->eraseFromParent();
173  I = MBB.instr_end();
174  ++Count;
175  }
176 
177  return Count;
178 }
179 
182  ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
183  assert(!BytesAdded && "code size not handled");
184 
185  if (Cond.empty()) {
186  if (!TBB)
187  return 0;
188 
189  BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(TBB);
190  return 1;
191  }
192 
193  assert(Cond.size() == 2 && "Expected a flag and a successor block");
194 
195  MachineFunction &MF = *MBB.getParent();
196  auto &MRI = MF.getRegInfo();
197  bool IsBrOnExn = Cond[1].isReg() && MRI.getRegClass(Cond[1].getReg()) ==
198  &WebAssembly::EXNREFRegClass;
199 
200  if (Cond[0].getImm()) {
201  if (IsBrOnExn) {
202  const char *CPPExnSymbol = MF.createExternalSymbolName("__cpp_exception");
203  BuildMI(&MBB, DL, get(WebAssembly::BR_ON_EXN))
204  .addMBB(TBB)
205  .addExternalSymbol(CPPExnSymbol)
206  .add(Cond[1]);
207  } else
208  BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]);
209  } else {
210  assert(!IsBrOnExn && "br_on_exn does not have a reversed condition");
211  BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS)).addMBB(TBB).add(Cond[1]);
212  }
213  if (!FBB)
214  return 1;
215 
216  BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(FBB);
217  return 2;
218 }
219 
222  assert(Cond.size() == 2 && "Expected a flag and a condition expression");
223 
224  // br_on_exn's condition cannot be reversed
225  MachineFunction &MF = *Cond[1].getParent()->getParent()->getParent();
226  auto &MRI = MF.getRegInfo();
227  if (Cond[1].isReg() &&
228  MRI.getRegClass(Cond[1].getReg()) == &WebAssembly::EXNREFRegClass)
229  return true;
230 
231  Cond.front() = MachineOperand::CreateImm(!Cond.front().getImm());
232  return false;
233 }
234 
237  static const std::pair<int, const char *> TargetIndices[] = {
238  {WebAssembly::TI_LOCAL, "wasm-local"},
239  {WebAssembly::TI_GLOBAL_FIXED, "wasm-global-fixed"},
240  {WebAssembly::TI_OPERAND_STACK, "wasm-operand-stack"},
241  {WebAssembly::TI_GLOBAL_RELOC, "wasm-global-reloc"}};
242  return makeArrayRef(TargetIndices);
243 }
static bool isReg(const MCInst &MI, unsigned OpNo)
const MachineInstrBuilder & add(const MachineOperand &MO) const
instr_iterator instr_begin()
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22
instr_iterator instr_end()
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
A debug info location.
Definition: DebugLoc.h:33
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
This file contains the entry points for global functions defined in the LLVM WebAssembly back-end...
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
MachineBasicBlock & MBB
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:458
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
iterator_range< iterator > terminators()
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:456
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
SmallVector< MachineOperand, 4 > Cond
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:833
unsigned const MachineRegisterInfo * MRI
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:156
This file provides WebAssembly-specific target descriptions.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This file declares the WebAssembly-specific subclass of TargetSubtarget.
Iterator for intrusive lists based on ilist_node.
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AAResults *AA) const override
This file contains the WebAssembly implementation of the TargetInstrInfo class.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
CATCHRET - Represents a return from a catch block funclet.
Definition: ISDOpcodes.h:890
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:280
Representation of each machine instruction.
Definition: MachineInstr.h:62
This class is derived from MachineFunctionInfo and contains private WebAssembly-specific information ...
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const override
WebAssemblyInstrInfo(const WebAssemblySubtarget &STI)
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:59
This file declares WebAssembly-specific per-machine-function information.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
IRTranslator LLVM IR MI
Register getReg() const
getReg - Returns the register number.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:466
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:151
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL