LLVM 19.0.0git
WebAssemblyMCTargetDesc.h
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1//==- WebAssemblyMCTargetDesc.h - WebAssembly Target Descriptions -*- C++ -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file provides WebAssembly-specific target descriptions.
11///
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
15#define LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
16
18#include "llvm/MC/MCContext.h"
19#include "llvm/MC/MCInstrDesc.h"
22#include <memory>
23
24namespace llvm {
25
26class MCAsmBackend;
27class MCCodeEmitter;
28class MCInstrInfo;
29class MCObjectTargetWriter;
30class Triple;
31
32MCCodeEmitter *createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII,
33 MCContext &Ctx);
34
35MCAsmBackend *createWebAssemblyAsmBackend(const Triple &TT);
36
37std::unique_ptr<MCObjectTargetWriter>
38createWebAssemblyWasmObjectWriter(bool Is64Bit, bool IsEmscripten);
39
40namespace WebAssembly {
41
42// Exception handling / setjmp-longjmp handling command-line options
43extern cl::opt<bool> WasmEnableEmEH; // asm.js-style EH
44extern cl::opt<bool> WasmEnableEmSjLj; // asm.js-style SjLJ
45extern cl::opt<bool> WasmEnableEH; // EH using Wasm EH instructions
46extern cl::opt<bool> WasmEnableSjLj; // SjLj using Wasm EH instructions
47
49 /// Basic block label in a branch construct.
51 /// Local index.
53 /// Global index.
55 /// 32-bit integer immediates.
57 /// 64-bit integer immediates.
59 /// 32-bit floating-point immediates.
61 /// 64-bit floating-point immediates.
63 /// 8-bit vector lane immediate
65 /// 16-bit vector lane immediate
67 /// 32-bit vector lane immediate
69 /// 64-bit vector lane immediate
71 /// 32-bit unsigned function indices.
73 /// 32-bit unsigned memory offsets.
75 /// 64-bit unsigned memory offsets.
77 /// p2align immediate for load and store address alignment.
79 /// signature immediate for block/loop.
81 /// type signature immediate for call_indirect.
83 /// Tag index.
85 /// A list of branch targets for br_list.
87 /// 32-bit unsigned table number.
89};
90} // end namespace WebAssembly
91
92namespace WebAssemblyII {
93
94/// Target Operand Flag enum.
95enum TOF {
97
98 // On a symbol operand this indicates that the immediate is a wasm global
99 // index. The value of the wasm global will be set to the symbol address at
100 // runtime. This adds a level of indirection similar to the GOT on native
101 // platforms.
103
104 // Same as MO_GOT but the address stored in the global is a TLS address.
106
107 // On a symbol operand this indicates that the immediate is the symbol
108 // address relative the __memory_base wasm global.
109 // Only applicable to data symbols.
111
112 // On a symbol operand this indicates that the immediate is the symbol
113 // address relative the __tls_base wasm global.
114 // Only applicable to data symbols.
116
117 // On a symbol operand this indicates that the immediate is the symbol
118 // address relative the __table_base wasm global.
119 // Only applicable to function symbols.
121};
122
123} // end namespace WebAssemblyII
124
125} // end namespace llvm
126
127// Defines symbolic names for WebAssembly registers. This defines a mapping from
128// register name to register number.
129//
130#define GET_REGINFO_ENUM
131#include "WebAssemblyGenRegisterInfo.inc"
132
133// Defines symbolic names for the WebAssembly instructions.
134//
135#define GET_INSTRINFO_ENUM
136#define GET_INSTRINFO_MC_HELPER_DECLS
137#include "WebAssemblyGenInstrInfo.inc"
138
139namespace llvm {
140namespace WebAssembly {
141
142/// Instruction opcodes emitted via means other than CodeGen.
143static const unsigned Nop = 0x01;
144static const unsigned End = 0x0b;
145
146/// Return the default p2align value for a load or store with the given opcode.
147inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
148 switch (Opc) {
149#define WASM_LOAD_STORE(NAME) \
150 case WebAssembly::NAME##_A32: \
151 case WebAssembly::NAME##_A64: \
152 case WebAssembly::NAME##_A32_S: \
153 case WebAssembly::NAME##_A64_S:
154 WASM_LOAD_STORE(LOAD8_S_I32)
155 WASM_LOAD_STORE(LOAD8_U_I32)
156 WASM_LOAD_STORE(LOAD8_S_I64)
157 WASM_LOAD_STORE(LOAD8_U_I64)
158 WASM_LOAD_STORE(ATOMIC_LOAD8_U_I32)
159 WASM_LOAD_STORE(ATOMIC_LOAD8_U_I64)
160 WASM_LOAD_STORE(STORE8_I32)
161 WASM_LOAD_STORE(STORE8_I64)
162 WASM_LOAD_STORE(ATOMIC_STORE8_I32)
163 WASM_LOAD_STORE(ATOMIC_STORE8_I64)
164 WASM_LOAD_STORE(ATOMIC_RMW8_U_ADD_I32)
165 WASM_LOAD_STORE(ATOMIC_RMW8_U_ADD_I64)
166 WASM_LOAD_STORE(ATOMIC_RMW8_U_SUB_I32)
167 WASM_LOAD_STORE(ATOMIC_RMW8_U_SUB_I64)
168 WASM_LOAD_STORE(ATOMIC_RMW8_U_AND_I32)
169 WASM_LOAD_STORE(ATOMIC_RMW8_U_AND_I64)
170 WASM_LOAD_STORE(ATOMIC_RMW8_U_OR_I32)
171 WASM_LOAD_STORE(ATOMIC_RMW8_U_OR_I64)
172 WASM_LOAD_STORE(ATOMIC_RMW8_U_XOR_I32)
173 WASM_LOAD_STORE(ATOMIC_RMW8_U_XOR_I64)
174 WASM_LOAD_STORE(ATOMIC_RMW8_U_XCHG_I32)
175 WASM_LOAD_STORE(ATOMIC_RMW8_U_XCHG_I64)
176 WASM_LOAD_STORE(ATOMIC_RMW8_U_CMPXCHG_I32)
177 WASM_LOAD_STORE(ATOMIC_RMW8_U_CMPXCHG_I64)
178 WASM_LOAD_STORE(LOAD8_SPLAT)
179 WASM_LOAD_STORE(LOAD_LANE_I8x16)
180 WASM_LOAD_STORE(STORE_LANE_I8x16)
181 return 0;
182 WASM_LOAD_STORE(LOAD16_S_I32)
183 WASM_LOAD_STORE(LOAD16_U_I32)
184 WASM_LOAD_STORE(LOAD16_S_I64)
185 WASM_LOAD_STORE(LOAD16_U_I64)
186 WASM_LOAD_STORE(ATOMIC_LOAD16_U_I32)
187 WASM_LOAD_STORE(ATOMIC_LOAD16_U_I64)
188 WASM_LOAD_STORE(STORE16_I32)
189 WASM_LOAD_STORE(STORE16_I64)
190 WASM_LOAD_STORE(ATOMIC_STORE16_I32)
191 WASM_LOAD_STORE(ATOMIC_STORE16_I64)
192 WASM_LOAD_STORE(ATOMIC_RMW16_U_ADD_I32)
193 WASM_LOAD_STORE(ATOMIC_RMW16_U_ADD_I64)
194 WASM_LOAD_STORE(ATOMIC_RMW16_U_SUB_I32)
195 WASM_LOAD_STORE(ATOMIC_RMW16_U_SUB_I64)
196 WASM_LOAD_STORE(ATOMIC_RMW16_U_AND_I32)
197 WASM_LOAD_STORE(ATOMIC_RMW16_U_AND_I64)
198 WASM_LOAD_STORE(ATOMIC_RMW16_U_OR_I32)
199 WASM_LOAD_STORE(ATOMIC_RMW16_U_OR_I64)
200 WASM_LOAD_STORE(ATOMIC_RMW16_U_XOR_I32)
201 WASM_LOAD_STORE(ATOMIC_RMW16_U_XOR_I64)
202 WASM_LOAD_STORE(ATOMIC_RMW16_U_XCHG_I32)
203 WASM_LOAD_STORE(ATOMIC_RMW16_U_XCHG_I64)
204 WASM_LOAD_STORE(ATOMIC_RMW16_U_CMPXCHG_I32)
205 WASM_LOAD_STORE(ATOMIC_RMW16_U_CMPXCHG_I64)
206 WASM_LOAD_STORE(LOAD16_SPLAT)
207 WASM_LOAD_STORE(LOAD_LANE_I16x8)
208 WASM_LOAD_STORE(STORE_LANE_I16x8)
209 return 1;
210 WASM_LOAD_STORE(LOAD_I32)
211 WASM_LOAD_STORE(LOAD_F32)
212 WASM_LOAD_STORE(STORE_I32)
213 WASM_LOAD_STORE(STORE_F32)
214 WASM_LOAD_STORE(LOAD32_S_I64)
215 WASM_LOAD_STORE(LOAD32_U_I64)
216 WASM_LOAD_STORE(STORE32_I64)
217 WASM_LOAD_STORE(ATOMIC_LOAD_I32)
218 WASM_LOAD_STORE(ATOMIC_LOAD32_U_I64)
219 WASM_LOAD_STORE(ATOMIC_STORE_I32)
220 WASM_LOAD_STORE(ATOMIC_STORE32_I64)
221 WASM_LOAD_STORE(ATOMIC_RMW_ADD_I32)
222 WASM_LOAD_STORE(ATOMIC_RMW32_U_ADD_I64)
223 WASM_LOAD_STORE(ATOMIC_RMW_SUB_I32)
224 WASM_LOAD_STORE(ATOMIC_RMW32_U_SUB_I64)
225 WASM_LOAD_STORE(ATOMIC_RMW_AND_I32)
226 WASM_LOAD_STORE(ATOMIC_RMW32_U_AND_I64)
227 WASM_LOAD_STORE(ATOMIC_RMW_OR_I32)
228 WASM_LOAD_STORE(ATOMIC_RMW32_U_OR_I64)
229 WASM_LOAD_STORE(ATOMIC_RMW_XOR_I32)
230 WASM_LOAD_STORE(ATOMIC_RMW32_U_XOR_I64)
231 WASM_LOAD_STORE(ATOMIC_RMW_XCHG_I32)
232 WASM_LOAD_STORE(ATOMIC_RMW32_U_XCHG_I64)
233 WASM_LOAD_STORE(ATOMIC_RMW_CMPXCHG_I32)
234 WASM_LOAD_STORE(ATOMIC_RMW32_U_CMPXCHG_I64)
235 WASM_LOAD_STORE(MEMORY_ATOMIC_NOTIFY)
236 WASM_LOAD_STORE(MEMORY_ATOMIC_WAIT32)
237 WASM_LOAD_STORE(LOAD32_SPLAT)
238 WASM_LOAD_STORE(LOAD_ZERO_I32x4)
239 WASM_LOAD_STORE(LOAD_LANE_I32x4)
240 WASM_LOAD_STORE(STORE_LANE_I32x4)
241 return 2;
242 WASM_LOAD_STORE(LOAD_I64)
243 WASM_LOAD_STORE(LOAD_F64)
244 WASM_LOAD_STORE(STORE_I64)
245 WASM_LOAD_STORE(STORE_F64)
246 WASM_LOAD_STORE(ATOMIC_LOAD_I64)
247 WASM_LOAD_STORE(ATOMIC_STORE_I64)
248 WASM_LOAD_STORE(ATOMIC_RMW_ADD_I64)
249 WASM_LOAD_STORE(ATOMIC_RMW_SUB_I64)
250 WASM_LOAD_STORE(ATOMIC_RMW_AND_I64)
251 WASM_LOAD_STORE(ATOMIC_RMW_OR_I64)
252 WASM_LOAD_STORE(ATOMIC_RMW_XOR_I64)
253 WASM_LOAD_STORE(ATOMIC_RMW_XCHG_I64)
254 WASM_LOAD_STORE(ATOMIC_RMW_CMPXCHG_I64)
255 WASM_LOAD_STORE(MEMORY_ATOMIC_WAIT64)
256 WASM_LOAD_STORE(LOAD64_SPLAT)
257 WASM_LOAD_STORE(LOAD_EXTEND_S_I16x8)
258 WASM_LOAD_STORE(LOAD_EXTEND_U_I16x8)
259 WASM_LOAD_STORE(LOAD_EXTEND_S_I32x4)
260 WASM_LOAD_STORE(LOAD_EXTEND_U_I32x4)
261 WASM_LOAD_STORE(LOAD_EXTEND_S_I64x2)
262 WASM_LOAD_STORE(LOAD_EXTEND_U_I64x2)
263 WASM_LOAD_STORE(LOAD_ZERO_I64x2)
264 WASM_LOAD_STORE(LOAD_LANE_I64x2)
265 WASM_LOAD_STORE(STORE_LANE_I64x2)
266 return 3;
267 WASM_LOAD_STORE(LOAD_V128)
268 WASM_LOAD_STORE(STORE_V128)
269 return 4;
270 default:
271 return -1;
272 }
273#undef WASM_LOAD_STORE
274}
275
276inline unsigned GetDefaultP2Align(unsigned Opc) {
277 auto Align = GetDefaultP2AlignAny(Opc);
278 if (Align == -1U) {
279 llvm_unreachable("Only loads and stores have p2align values");
280 }
281 return Align;
282}
283
284inline bool isConst(unsigned Opc) {
285 switch (Opc) {
286 case WebAssembly::CONST_I32:
287 case WebAssembly::CONST_I32_S:
288 case WebAssembly::CONST_I64:
289 case WebAssembly::CONST_I64_S:
290 case WebAssembly::CONST_F32:
291 case WebAssembly::CONST_F32_S:
292 case WebAssembly::CONST_F64:
293 case WebAssembly::CONST_F64_S:
294 case WebAssembly::CONST_V128_I8x16:
295 case WebAssembly::CONST_V128_I8x16_S:
296 case WebAssembly::CONST_V128_I16x8:
297 case WebAssembly::CONST_V128_I16x8_S:
298 case WebAssembly::CONST_V128_I32x4:
299 case WebAssembly::CONST_V128_I32x4_S:
300 case WebAssembly::CONST_V128_I64x2:
301 case WebAssembly::CONST_V128_I64x2_S:
302 case WebAssembly::CONST_V128_F32x4:
303 case WebAssembly::CONST_V128_F32x4_S:
304 case WebAssembly::CONST_V128_F64x2:
305 case WebAssembly::CONST_V128_F64x2_S:
306 return true;
307 default:
308 return false;
309 }
310}
311
312inline bool isScalarConst(unsigned Opc) {
313 switch (Opc) {
314 case WebAssembly::CONST_I32:
315 case WebAssembly::CONST_I32_S:
316 case WebAssembly::CONST_I64:
317 case WebAssembly::CONST_I64_S:
318 case WebAssembly::CONST_F32:
319 case WebAssembly::CONST_F32_S:
320 case WebAssembly::CONST_F64:
321 case WebAssembly::CONST_F64_S:
322 return true;
323 default:
324 return false;
325 }
326}
327
328inline bool isArgument(unsigned Opc) {
329 switch (Opc) {
330 case WebAssembly::ARGUMENT_i32:
331 case WebAssembly::ARGUMENT_i32_S:
332 case WebAssembly::ARGUMENT_i64:
333 case WebAssembly::ARGUMENT_i64_S:
334 case WebAssembly::ARGUMENT_f32:
335 case WebAssembly::ARGUMENT_f32_S:
336 case WebAssembly::ARGUMENT_f64:
337 case WebAssembly::ARGUMENT_f64_S:
338 case WebAssembly::ARGUMENT_v16i8:
339 case WebAssembly::ARGUMENT_v16i8_S:
340 case WebAssembly::ARGUMENT_v8i16:
341 case WebAssembly::ARGUMENT_v8i16_S:
342 case WebAssembly::ARGUMENT_v4i32:
343 case WebAssembly::ARGUMENT_v4i32_S:
344 case WebAssembly::ARGUMENT_v2i64:
345 case WebAssembly::ARGUMENT_v2i64_S:
346 case WebAssembly::ARGUMENT_v4f32:
347 case WebAssembly::ARGUMENT_v4f32_S:
348 case WebAssembly::ARGUMENT_v2f64:
349 case WebAssembly::ARGUMENT_v2f64_S:
350 case WebAssembly::ARGUMENT_funcref:
351 case WebAssembly::ARGUMENT_funcref_S:
352 case WebAssembly::ARGUMENT_externref:
353 case WebAssembly::ARGUMENT_externref_S:
354 return true;
355 default:
356 return false;
357 }
358}
359
360inline bool isCopy(unsigned Opc) {
361 switch (Opc) {
362 case WebAssembly::COPY_I32:
363 case WebAssembly::COPY_I32_S:
364 case WebAssembly::COPY_I64:
365 case WebAssembly::COPY_I64_S:
366 case WebAssembly::COPY_F32:
367 case WebAssembly::COPY_F32_S:
368 case WebAssembly::COPY_F64:
369 case WebAssembly::COPY_F64_S:
370 case WebAssembly::COPY_V128:
371 case WebAssembly::COPY_V128_S:
372 case WebAssembly::COPY_FUNCREF:
373 case WebAssembly::COPY_FUNCREF_S:
374 case WebAssembly::COPY_EXTERNREF:
375 case WebAssembly::COPY_EXTERNREF_S:
376 return true;
377 default:
378 return false;
379 }
380}
381
382inline bool isTee(unsigned Opc) {
383 switch (Opc) {
384 case WebAssembly::TEE_I32:
385 case WebAssembly::TEE_I32_S:
386 case WebAssembly::TEE_I64:
387 case WebAssembly::TEE_I64_S:
388 case WebAssembly::TEE_F32:
389 case WebAssembly::TEE_F32_S:
390 case WebAssembly::TEE_F64:
391 case WebAssembly::TEE_F64_S:
392 case WebAssembly::TEE_V128:
393 case WebAssembly::TEE_V128_S:
394 case WebAssembly::TEE_FUNCREF:
395 case WebAssembly::TEE_FUNCREF_S:
396 case WebAssembly::TEE_EXTERNREF:
397 case WebAssembly::TEE_EXTERNREF_S:
398 return true;
399 default:
400 return false;
401 }
402}
403
404inline bool isCallDirect(unsigned Opc) {
405 switch (Opc) {
406 case WebAssembly::CALL:
407 case WebAssembly::CALL_S:
408 case WebAssembly::RET_CALL:
409 case WebAssembly::RET_CALL_S:
410 return true;
411 default:
412 return false;
413 }
414}
415
416inline bool isCallIndirect(unsigned Opc) {
417 switch (Opc) {
418 case WebAssembly::CALL_INDIRECT:
419 case WebAssembly::CALL_INDIRECT_S:
420 case WebAssembly::RET_CALL_INDIRECT:
421 case WebAssembly::RET_CALL_INDIRECT_S:
422 return true;
423 default:
424 return false;
425 }
426}
427
428inline bool isBrTable(unsigned Opc) {
429 switch (Opc) {
430 case WebAssembly::BR_TABLE_I32:
431 case WebAssembly::BR_TABLE_I32_S:
432 case WebAssembly::BR_TABLE_I64:
433 case WebAssembly::BR_TABLE_I64_S:
434 return true;
435 default:
436 return false;
437 }
438}
439
440inline bool isMarker(unsigned Opc) {
441 switch (Opc) {
442 case WebAssembly::BLOCK:
443 case WebAssembly::BLOCK_S:
444 case WebAssembly::END_BLOCK:
445 case WebAssembly::END_BLOCK_S:
446 case WebAssembly::LOOP:
447 case WebAssembly::LOOP_S:
448 case WebAssembly::END_LOOP:
449 case WebAssembly::END_LOOP_S:
450 case WebAssembly::TRY:
451 case WebAssembly::TRY_S:
452 case WebAssembly::END_TRY:
453 case WebAssembly::END_TRY_S:
454 return true;
455 default:
456 return false;
457 }
458}
459
460inline bool isCatch(unsigned Opc) {
461 switch (Opc) {
462 case WebAssembly::CATCH:
463 case WebAssembly::CATCH_S:
464 case WebAssembly::CATCH_ALL:
465 case WebAssembly::CATCH_ALL_S:
466 return true;
467 default:
468 return false;
469 }
470}
471
472inline bool isLocalGet(unsigned Opc) {
473 switch (Opc) {
474 case WebAssembly::LOCAL_GET_I32:
475 case WebAssembly::LOCAL_GET_I32_S:
476 case WebAssembly::LOCAL_GET_I64:
477 case WebAssembly::LOCAL_GET_I64_S:
478 case WebAssembly::LOCAL_GET_F32:
479 case WebAssembly::LOCAL_GET_F32_S:
480 case WebAssembly::LOCAL_GET_F64:
481 case WebAssembly::LOCAL_GET_F64_S:
482 case WebAssembly::LOCAL_GET_V128:
483 case WebAssembly::LOCAL_GET_V128_S:
484 case WebAssembly::LOCAL_GET_FUNCREF:
485 case WebAssembly::LOCAL_GET_FUNCREF_S:
486 case WebAssembly::LOCAL_GET_EXTERNREF:
487 case WebAssembly::LOCAL_GET_EXTERNREF_S:
488 return true;
489 default:
490 return false;
491 }
492}
493
494inline bool isLocalSet(unsigned Opc) {
495 switch (Opc) {
496 case WebAssembly::LOCAL_SET_I32:
497 case WebAssembly::LOCAL_SET_I32_S:
498 case WebAssembly::LOCAL_SET_I64:
499 case WebAssembly::LOCAL_SET_I64_S:
500 case WebAssembly::LOCAL_SET_F32:
501 case WebAssembly::LOCAL_SET_F32_S:
502 case WebAssembly::LOCAL_SET_F64:
503 case WebAssembly::LOCAL_SET_F64_S:
504 case WebAssembly::LOCAL_SET_V128:
505 case WebAssembly::LOCAL_SET_V128_S:
506 case WebAssembly::LOCAL_SET_FUNCREF:
507 case WebAssembly::LOCAL_SET_FUNCREF_S:
508 case WebAssembly::LOCAL_SET_EXTERNREF:
509 case WebAssembly::LOCAL_SET_EXTERNREF_S:
510 return true;
511 default:
512 return false;
513 }
514}
515
516inline bool isLocalTee(unsigned Opc) {
517 switch (Opc) {
518 case WebAssembly::LOCAL_TEE_I32:
519 case WebAssembly::LOCAL_TEE_I32_S:
520 case WebAssembly::LOCAL_TEE_I64:
521 case WebAssembly::LOCAL_TEE_I64_S:
522 case WebAssembly::LOCAL_TEE_F32:
523 case WebAssembly::LOCAL_TEE_F32_S:
524 case WebAssembly::LOCAL_TEE_F64:
525 case WebAssembly::LOCAL_TEE_F64_S:
526 case WebAssembly::LOCAL_TEE_V128:
527 case WebAssembly::LOCAL_TEE_V128_S:
528 case WebAssembly::LOCAL_TEE_FUNCREF:
529 case WebAssembly::LOCAL_TEE_FUNCREF_S:
530 case WebAssembly::LOCAL_TEE_EXTERNREF:
531 case WebAssembly::LOCAL_TEE_EXTERNREF_S:
532 return true;
533 default:
534 return false;
535 }
536}
537
538static const unsigned UnusedReg = -1u;
539
540// For a given stackified WAReg, return the id number to print with push/pop.
541unsigned inline getWARegStackId(unsigned Reg) {
542 assert(Reg & INT32_MIN);
543 return Reg & INT32_MAX;
544}
545
546} // end namespace WebAssembly
547} // end namespace llvm
548
549#define GET_SUBTARGETINFO_ENUM
550#include "WebAssemblyGenSubtargetInfo.inc"
551
552#endif
unsigned Reg
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
#define WASM_LOAD_STORE(NAME)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:78
TOF
Target Operand Flag enum.
bool isLocalTee(unsigned Opc)
bool isArgument(unsigned Opc)
bool isCallIndirect(unsigned Opc)
unsigned GetDefaultP2Align(unsigned Opc)
bool isMarker(unsigned Opc)
bool isBrTable(unsigned Opc)
bool isCatch(unsigned Opc)
static const unsigned UnusedReg
static const unsigned Nop
Instruction opcodes emitted via means other than CodeGen.
cl::opt< bool > WasmEnableEH
bool isCopy(unsigned Opc)
cl::opt< bool > WasmEnableSjLj
bool isTee(unsigned Opc)
static const unsigned End
bool isConst(unsigned Opc)
cl::opt< bool > WasmEnableEmEH
@ OPERAND_GLOBAL
Global index.
@ OPERAND_OFFSET64
64-bit unsigned memory offsets.
@ OPERAND_I32IMM
32-bit integer immediates.
@ OPERAND_P2ALIGN
p2align immediate for load and store address alignment.
@ OPERAND_TABLE
32-bit unsigned table number.
@ OPERAND_VEC_I64IMM
64-bit vector lane immediate
@ OPERAND_VEC_I16IMM
16-bit vector lane immediate
@ OPERAND_TYPEINDEX
type signature immediate for call_indirect.
@ OPERAND_FUNCTION32
32-bit unsigned function indices.
@ OPERAND_F32IMM
32-bit floating-point immediates.
@ OPERAND_BASIC_BLOCK
Basic block label in a branch construct.
@ OPERAND_VEC_I32IMM
32-bit vector lane immediate
@ OPERAND_BRLIST
A list of branch targets for br_list.
@ OPERAND_F64IMM
64-bit floating-point immediates.
@ OPERAND_VEC_I8IMM
8-bit vector lane immediate
@ OPERAND_SIGNATURE
signature immediate for block/loop.
@ OPERAND_I64IMM
64-bit integer immediates.
@ OPERAND_OFFSET32
32-bit unsigned memory offsets.
unsigned GetDefaultP2AlignAny(unsigned Opc)
Return the default p2align value for a load or store with the given opcode.
cl::opt< bool > WasmEnableEmSjLj
bool isCallDirect(unsigned Opc)
bool isScalarConst(unsigned Opc)
unsigned getWARegStackId(unsigned Reg)
bool isLocalSet(unsigned Opc)
bool isLocalGet(unsigned Opc)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MCCodeEmitter * createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
MCAsmBackend * createWebAssemblyAsmBackend(const Triple &TT)
std::unique_ptr< MCObjectTargetWriter > createWebAssemblyWasmObjectWriter(bool Is64Bit, bool IsEmscripten)
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39