LLVM  8.0.0svn
WebAssemblyMCTargetDesc.h
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1 //==- WebAssemblyMCTargetDesc.h - WebAssembly Target Descriptions -*- C++ -*-=//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// This file provides WebAssembly-specific target descriptions.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
16 #define LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
17 
18 #include "llvm/BinaryFormat/Wasm.h"
19 #include "llvm/MC/MCInstrDesc.h"
20 #include "llvm/Support/DataTypes.h"
21 #include <memory>
22 
23 namespace llvm {
24 
25 class MCAsmBackend;
26 class MCCodeEmitter;
27 class MCContext;
28 class MCInstrInfo;
29 class MCObjectTargetWriter;
30 class MCSubtargetInfo;
31 class MVT;
32 class Target;
33 class Triple;
34 class raw_pwrite_stream;
35 
38 
39 MCCodeEmitter *createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII);
40 
41 MCAsmBackend *createWebAssemblyAsmBackend(const Triple &TT);
42 
43 std::unique_ptr<MCObjectTargetWriter>
45 
46 namespace WebAssembly {
48  /// Basic block label in a branch construct.
50  /// Local index.
52  /// Global index.
54  /// 32-bit integer immediates.
56  /// 64-bit integer immediates.
58  /// 32-bit floating-point immediates.
60  /// 64-bit floating-point immediates.
62  /// 32-bit unsigned function indices.
64  /// 32-bit unsigned memory offsets.
66  /// p2align immediate for load and store address alignment.
68  /// signature immediate for block/loop.
70  /// type signature immediate for call_indirect.
72 };
73 } // end namespace WebAssembly
74 
75 namespace WebAssemblyII {
76 enum {
77  // For variadic instructions, this flag indicates whether an operand
78  // in the variable_ops range is an immediate value.
80  // For immediate values in the variable_ops range, this flag indicates
81  // whether the value represents a control-flow label.
83 };
84 
85 /// Target Operand Flag enum.
86 enum TOF {
88 
89  // Flags to indicate the type of the symbol being referenced
93 };
94 } // end namespace WebAssemblyII
95 
96 } // end namespace llvm
97 
98 // Defines symbolic names for WebAssembly registers. This defines a mapping from
99 // register name to register number.
100 //
101 #define GET_REGINFO_ENUM
102 #include "WebAssemblyGenRegisterInfo.inc"
103 
104 // Defines symbolic names for the WebAssembly instructions.
105 //
106 #define GET_INSTRINFO_ENUM
107 #include "WebAssemblyGenInstrInfo.inc"
108 
109 #define GET_SUBTARGETINFO_ENUM
110 #include "WebAssemblyGenSubtargetInfo.inc"
111 
112 namespace llvm {
113 namespace WebAssembly {
114 
115 /// Return the default p2align value for a load or store with the given opcode.
116 inline unsigned GetDefaultP2Align(unsigned Opcode) {
117  switch (Opcode) {
118  case WebAssembly::LOAD8_S_I32:
119  case WebAssembly::LOAD8_S_I32_S:
120  case WebAssembly::LOAD8_U_I32:
121  case WebAssembly::LOAD8_U_I32_S:
122  case WebAssembly::LOAD8_S_I64:
123  case WebAssembly::LOAD8_S_I64_S:
124  case WebAssembly::LOAD8_U_I64:
125  case WebAssembly::LOAD8_U_I64_S:
126  case WebAssembly::ATOMIC_LOAD8_U_I32:
127  case WebAssembly::ATOMIC_LOAD8_U_I32_S:
128  case WebAssembly::ATOMIC_LOAD8_U_I64:
129  case WebAssembly::ATOMIC_LOAD8_U_I64_S:
130  case WebAssembly::STORE8_I32:
131  case WebAssembly::STORE8_I32_S:
132  case WebAssembly::STORE8_I64:
133  case WebAssembly::STORE8_I64_S:
134  case WebAssembly::ATOMIC_STORE8_I32:
135  case WebAssembly::ATOMIC_STORE8_I32_S:
136  case WebAssembly::ATOMIC_STORE8_I64:
137  case WebAssembly::ATOMIC_STORE8_I64_S:
138  case WebAssembly::ATOMIC_RMW8_U_ADD_I32:
139  case WebAssembly::ATOMIC_RMW8_U_ADD_I32_S:
140  case WebAssembly::ATOMIC_RMW8_U_ADD_I64:
141  case WebAssembly::ATOMIC_RMW8_U_ADD_I64_S:
142  case WebAssembly::ATOMIC_RMW8_U_SUB_I32:
143  case WebAssembly::ATOMIC_RMW8_U_SUB_I32_S:
144  case WebAssembly::ATOMIC_RMW8_U_SUB_I64:
145  case WebAssembly::ATOMIC_RMW8_U_SUB_I64_S:
146  case WebAssembly::ATOMIC_RMW8_U_AND_I32:
147  case WebAssembly::ATOMIC_RMW8_U_AND_I32_S:
148  case WebAssembly::ATOMIC_RMW8_U_AND_I64:
149  case WebAssembly::ATOMIC_RMW8_U_AND_I64_S:
150  case WebAssembly::ATOMIC_RMW8_U_OR_I32:
151  case WebAssembly::ATOMIC_RMW8_U_OR_I32_S:
152  case WebAssembly::ATOMIC_RMW8_U_OR_I64:
153  case WebAssembly::ATOMIC_RMW8_U_OR_I64_S:
154  case WebAssembly::ATOMIC_RMW8_U_XOR_I32:
155  case WebAssembly::ATOMIC_RMW8_U_XOR_I32_S:
156  case WebAssembly::ATOMIC_RMW8_U_XOR_I64:
157  case WebAssembly::ATOMIC_RMW8_U_XOR_I64_S:
158  case WebAssembly::ATOMIC_RMW8_U_XCHG_I32:
159  case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_S:
160  case WebAssembly::ATOMIC_RMW8_U_XCHG_I64:
161  case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_S:
162  case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32:
163  case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_S:
164  case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64:
165  case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_S:
166  return 0;
167  case WebAssembly::LOAD16_S_I32:
168  case WebAssembly::LOAD16_S_I32_S:
169  case WebAssembly::LOAD16_U_I32:
170  case WebAssembly::LOAD16_U_I32_S:
171  case WebAssembly::LOAD16_S_I64:
172  case WebAssembly::LOAD16_S_I64_S:
173  case WebAssembly::LOAD16_U_I64:
174  case WebAssembly::LOAD16_U_I64_S:
175  case WebAssembly::ATOMIC_LOAD16_U_I32:
176  case WebAssembly::ATOMIC_LOAD16_U_I32_S:
177  case WebAssembly::ATOMIC_LOAD16_U_I64:
178  case WebAssembly::ATOMIC_LOAD16_U_I64_S:
179  case WebAssembly::STORE16_I32:
180  case WebAssembly::STORE16_I32_S:
181  case WebAssembly::STORE16_I64:
182  case WebAssembly::STORE16_I64_S:
183  case WebAssembly::ATOMIC_STORE16_I32:
184  case WebAssembly::ATOMIC_STORE16_I32_S:
185  case WebAssembly::ATOMIC_STORE16_I64:
186  case WebAssembly::ATOMIC_STORE16_I64_S:
187  case WebAssembly::ATOMIC_RMW16_U_ADD_I32:
188  case WebAssembly::ATOMIC_RMW16_U_ADD_I32_S:
189  case WebAssembly::ATOMIC_RMW16_U_ADD_I64:
190  case WebAssembly::ATOMIC_RMW16_U_ADD_I64_S:
191  case WebAssembly::ATOMIC_RMW16_U_SUB_I32:
192  case WebAssembly::ATOMIC_RMW16_U_SUB_I32_S:
193  case WebAssembly::ATOMIC_RMW16_U_SUB_I64:
194  case WebAssembly::ATOMIC_RMW16_U_SUB_I64_S:
195  case WebAssembly::ATOMIC_RMW16_U_AND_I32:
196  case WebAssembly::ATOMIC_RMW16_U_AND_I32_S:
197  case WebAssembly::ATOMIC_RMW16_U_AND_I64:
198  case WebAssembly::ATOMIC_RMW16_U_AND_I64_S:
199  case WebAssembly::ATOMIC_RMW16_U_OR_I32:
200  case WebAssembly::ATOMIC_RMW16_U_OR_I32_S:
201  case WebAssembly::ATOMIC_RMW16_U_OR_I64:
202  case WebAssembly::ATOMIC_RMW16_U_OR_I64_S:
203  case WebAssembly::ATOMIC_RMW16_U_XOR_I32:
204  case WebAssembly::ATOMIC_RMW16_U_XOR_I32_S:
205  case WebAssembly::ATOMIC_RMW16_U_XOR_I64:
206  case WebAssembly::ATOMIC_RMW16_U_XOR_I64_S:
207  case WebAssembly::ATOMIC_RMW16_U_XCHG_I32:
208  case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_S:
209  case WebAssembly::ATOMIC_RMW16_U_XCHG_I64:
210  case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_S:
211  case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32:
212  case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_S:
213  case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64:
214  case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_S:
215  return 1;
216  case WebAssembly::LOAD_I32:
217  case WebAssembly::LOAD_I32_S:
218  case WebAssembly::LOAD_F32:
219  case WebAssembly::LOAD_F32_S:
220  case WebAssembly::STORE_I32:
221  case WebAssembly::STORE_I32_S:
222  case WebAssembly::STORE_F32:
223  case WebAssembly::STORE_F32_S:
224  case WebAssembly::LOAD32_S_I64:
225  case WebAssembly::LOAD32_S_I64_S:
226  case WebAssembly::LOAD32_U_I64:
227  case WebAssembly::LOAD32_U_I64_S:
228  case WebAssembly::STORE32_I64:
229  case WebAssembly::STORE32_I64_S:
230  case WebAssembly::ATOMIC_LOAD_I32:
231  case WebAssembly::ATOMIC_LOAD_I32_S:
232  case WebAssembly::ATOMIC_LOAD32_U_I64:
233  case WebAssembly::ATOMIC_LOAD32_U_I64_S:
234  case WebAssembly::ATOMIC_STORE_I32:
235  case WebAssembly::ATOMIC_STORE_I32_S:
236  case WebAssembly::ATOMIC_STORE32_I64:
237  case WebAssembly::ATOMIC_STORE32_I64_S:
238  case WebAssembly::ATOMIC_RMW_ADD_I32:
239  case WebAssembly::ATOMIC_RMW_ADD_I32_S:
240  case WebAssembly::ATOMIC_RMW32_U_ADD_I64:
241  case WebAssembly::ATOMIC_RMW32_U_ADD_I64_S:
242  case WebAssembly::ATOMIC_RMW_SUB_I32:
243  case WebAssembly::ATOMIC_RMW_SUB_I32_S:
244  case WebAssembly::ATOMIC_RMW32_U_SUB_I64:
245  case WebAssembly::ATOMIC_RMW32_U_SUB_I64_S:
246  case WebAssembly::ATOMIC_RMW_AND_I32:
247  case WebAssembly::ATOMIC_RMW_AND_I32_S:
248  case WebAssembly::ATOMIC_RMW32_U_AND_I64:
249  case WebAssembly::ATOMIC_RMW32_U_AND_I64_S:
250  case WebAssembly::ATOMIC_RMW_OR_I32:
251  case WebAssembly::ATOMIC_RMW_OR_I32_S:
252  case WebAssembly::ATOMIC_RMW32_U_OR_I64:
253  case WebAssembly::ATOMIC_RMW32_U_OR_I64_S:
254  case WebAssembly::ATOMIC_RMW_XOR_I32:
255  case WebAssembly::ATOMIC_RMW_XOR_I32_S:
256  case WebAssembly::ATOMIC_RMW32_U_XOR_I64:
257  case WebAssembly::ATOMIC_RMW32_U_XOR_I64_S:
258  case WebAssembly::ATOMIC_RMW_XCHG_I32:
259  case WebAssembly::ATOMIC_RMW_XCHG_I32_S:
260  case WebAssembly::ATOMIC_RMW32_U_XCHG_I64:
261  case WebAssembly::ATOMIC_RMW32_U_XCHG_I64_S:
262  case WebAssembly::ATOMIC_RMW_CMPXCHG_I32:
263  case WebAssembly::ATOMIC_RMW_CMPXCHG_I32_S:
264  case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64:
265  case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_S:
266  case WebAssembly::ATOMIC_NOTIFY:
267  case WebAssembly::ATOMIC_NOTIFY_S:
268  case WebAssembly::ATOMIC_WAIT_I32:
269  case WebAssembly::ATOMIC_WAIT_I32_S:
270  return 2;
271  case WebAssembly::LOAD_I64:
272  case WebAssembly::LOAD_I64_S:
273  case WebAssembly::LOAD_F64:
274  case WebAssembly::LOAD_F64_S:
275  case WebAssembly::STORE_I64:
276  case WebAssembly::STORE_I64_S:
277  case WebAssembly::STORE_F64:
278  case WebAssembly::STORE_F64_S:
279  case WebAssembly::ATOMIC_LOAD_I64:
280  case WebAssembly::ATOMIC_LOAD_I64_S:
281  case WebAssembly::ATOMIC_STORE_I64:
282  case WebAssembly::ATOMIC_STORE_I64_S:
283  case WebAssembly::ATOMIC_RMW_ADD_I64:
284  case WebAssembly::ATOMIC_RMW_ADD_I64_S:
285  case WebAssembly::ATOMIC_RMW_SUB_I64:
286  case WebAssembly::ATOMIC_RMW_SUB_I64_S:
287  case WebAssembly::ATOMIC_RMW_AND_I64:
288  case WebAssembly::ATOMIC_RMW_AND_I64_S:
289  case WebAssembly::ATOMIC_RMW_OR_I64:
290  case WebAssembly::ATOMIC_RMW_OR_I64_S:
291  case WebAssembly::ATOMIC_RMW_XOR_I64:
292  case WebAssembly::ATOMIC_RMW_XOR_I64_S:
293  case WebAssembly::ATOMIC_RMW_XCHG_I64:
294  case WebAssembly::ATOMIC_RMW_XCHG_I64_S:
295  case WebAssembly::ATOMIC_RMW_CMPXCHG_I64:
296  case WebAssembly::ATOMIC_RMW_CMPXCHG_I64_S:
297  case WebAssembly::ATOMIC_WAIT_I64:
298  case WebAssembly::ATOMIC_WAIT_I64_S:
299  return 3;
300  default:
301  llvm_unreachable("Only loads and stores have p2align values");
302  }
303 }
304 
305 /// The operand number of the load or store address in load/store instructions.
306 static const unsigned LoadAddressOperandNo = 3;
307 static const unsigned StoreAddressOperandNo = 2;
308 
309 /// The operand number of the load or store p2align in load/store instructions.
310 static const unsigned LoadP2AlignOperandNo = 1;
311 static const unsigned StoreP2AlignOperandNo = 0;
312 
313 /// This is used to indicate block signatures.
314 enum class ExprType : unsigned {
315  Void = 0x40,
316  I32 = 0x7F,
317  I64 = 0x7E,
318  F32 = 0x7D,
319  F64 = 0x7C,
320  V128 = 0x7B,
321  ExceptRef = 0x68
322 };
323 
324 /// Instruction opcodes emitted via means other than CodeGen.
325 static const unsigned Nop = 0x01;
326 static const unsigned End = 0x0b;
327 
328 wasm::ValType toValType(const MVT &Ty);
329 
330 } // end namespace WebAssembly
331 } // end namespace llvm
332 
333 #endif
static const unsigned LoadP2AlignOperandNo
The operand number of the load or store p2align in load/store instructions.
32-bit floating-point immediates.
static const unsigned LoadAddressOperandNo
The operand number of the load or store address in load/store instructions.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
std::unique_ptr< MCObjectTargetWriter > createWebAssemblyWasmObjectWriter(bool Is64Bit)
32-bit unsigned memory offsets.
Basic block label in a branch construct.
static const unsigned StoreP2AlignOperandNo
signature immediate for block/loop.
wasm::ValType toValType(const MVT &Ty)
Machine Value Type.
MCCodeEmitter * createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII)
TOF
Target Operand Flag enum.
static const unsigned End
unsigned GetDefaultP2Align(unsigned Opcode)
Return the default p2align value for a load or store with the given opcode.
type signature immediate for call_indirect.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
ExprType
This is used to indicate block signatures.
MCAsmBackend * createWebAssemblyAsmBackend(const Triple &TT)
static const unsigned StoreAddressOperandNo
64-bit floating-point immediates.
32-bit unsigned function indices.
p2align immediate for load and store address alignment.
static const unsigned Nop
Instruction opcodes emitted via means other than CodeGen.
Target & getTheWebAssemblyTarget32()
Target & getTheWebAssemblyTarget64()