LLVM  8.0.0svn
WebAssemblyMCTargetDesc.h
Go to the documentation of this file.
1 //==- WebAssemblyMCTargetDesc.h - WebAssembly Target Descriptions -*- C++ -*-=//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// This file provides WebAssembly-specific target descriptions.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
16 #define LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
17 
18 #include "llvm/BinaryFormat/Wasm.h"
19 #include "llvm/MC/MCInstrDesc.h"
20 #include "llvm/Support/DataTypes.h"
21 #include <memory>
22 
23 namespace llvm {
24 
25 class MCAsmBackend;
26 class MCCodeEmitter;
27 class MCContext;
28 class MCInstrInfo;
29 class MCObjectTargetWriter;
30 class MCSubtargetInfo;
31 class MVT;
32 class Target;
33 class Triple;
34 class raw_pwrite_stream;
35 
38 
39 MCCodeEmitter *createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII);
40 
41 MCAsmBackend *createWebAssemblyAsmBackend(const Triple &TT);
42 
43 std::unique_ptr<MCObjectTargetWriter>
45 
46 namespace WebAssembly {
48  /// Basic block label in a branch construct.
50  /// Local index.
52  /// Global index.
54  /// 32-bit integer immediates.
56  /// 64-bit integer immediates.
58  /// 32-bit floating-point immediates.
60  /// 64-bit floating-point immediates.
62  /// 8-bit vector lane immediate
64  /// 16-bit vector lane immediate
66  /// 32-bit vector lane immediate
68  /// 64-bit vector lane immediate
70  /// 32-bit unsigned function indices.
72  /// 32-bit unsigned memory offsets.
74  /// p2align immediate for load and store address alignment.
76  /// signature immediate for block/loop.
78  /// type signature immediate for call_indirect.
80  /// Event index.
82 };
83 } // end namespace WebAssembly
84 
85 namespace WebAssemblyII {
86 
87 /// Target Operand Flag enum.
88 enum TOF {
90 
91  // Flags to indicate the type of the symbol being referenced
96 };
97 } // end namespace WebAssemblyII
98 
99 } // end namespace llvm
100 
101 // Defines symbolic names for WebAssembly registers. This defines a mapping from
102 // register name to register number.
103 //
104 #define GET_REGINFO_ENUM
105 #include "WebAssemblyGenRegisterInfo.inc"
106 
107 // Defines symbolic names for the WebAssembly instructions.
108 //
109 #define GET_INSTRINFO_ENUM
110 #include "WebAssemblyGenInstrInfo.inc"
111 
112 #define GET_SUBTARGETINFO_ENUM
113 #include "WebAssemblyGenSubtargetInfo.inc"
114 
115 namespace llvm {
116 namespace WebAssembly {
117 
118 /// Return the default p2align value for a load or store with the given opcode.
119 inline unsigned GetDefaultP2Align(unsigned Opcode) {
120  switch (Opcode) {
121  case WebAssembly::LOAD8_S_I32:
122  case WebAssembly::LOAD8_S_I32_S:
123  case WebAssembly::LOAD8_U_I32:
124  case WebAssembly::LOAD8_U_I32_S:
125  case WebAssembly::LOAD8_S_I64:
126  case WebAssembly::LOAD8_S_I64_S:
127  case WebAssembly::LOAD8_U_I64:
128  case WebAssembly::LOAD8_U_I64_S:
129  case WebAssembly::ATOMIC_LOAD8_U_I32:
130  case WebAssembly::ATOMIC_LOAD8_U_I32_S:
131  case WebAssembly::ATOMIC_LOAD8_U_I64:
132  case WebAssembly::ATOMIC_LOAD8_U_I64_S:
133  case WebAssembly::STORE8_I32:
134  case WebAssembly::STORE8_I32_S:
135  case WebAssembly::STORE8_I64:
136  case WebAssembly::STORE8_I64_S:
137  case WebAssembly::ATOMIC_STORE8_I32:
138  case WebAssembly::ATOMIC_STORE8_I32_S:
139  case WebAssembly::ATOMIC_STORE8_I64:
140  case WebAssembly::ATOMIC_STORE8_I64_S:
141  case WebAssembly::ATOMIC_RMW8_U_ADD_I32:
142  case WebAssembly::ATOMIC_RMW8_U_ADD_I32_S:
143  case WebAssembly::ATOMIC_RMW8_U_ADD_I64:
144  case WebAssembly::ATOMIC_RMW8_U_ADD_I64_S:
145  case WebAssembly::ATOMIC_RMW8_U_SUB_I32:
146  case WebAssembly::ATOMIC_RMW8_U_SUB_I32_S:
147  case WebAssembly::ATOMIC_RMW8_U_SUB_I64:
148  case WebAssembly::ATOMIC_RMW8_U_SUB_I64_S:
149  case WebAssembly::ATOMIC_RMW8_U_AND_I32:
150  case WebAssembly::ATOMIC_RMW8_U_AND_I32_S:
151  case WebAssembly::ATOMIC_RMW8_U_AND_I64:
152  case WebAssembly::ATOMIC_RMW8_U_AND_I64_S:
153  case WebAssembly::ATOMIC_RMW8_U_OR_I32:
154  case WebAssembly::ATOMIC_RMW8_U_OR_I32_S:
155  case WebAssembly::ATOMIC_RMW8_U_OR_I64:
156  case WebAssembly::ATOMIC_RMW8_U_OR_I64_S:
157  case WebAssembly::ATOMIC_RMW8_U_XOR_I32:
158  case WebAssembly::ATOMIC_RMW8_U_XOR_I32_S:
159  case WebAssembly::ATOMIC_RMW8_U_XOR_I64:
160  case WebAssembly::ATOMIC_RMW8_U_XOR_I64_S:
161  case WebAssembly::ATOMIC_RMW8_U_XCHG_I32:
162  case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_S:
163  case WebAssembly::ATOMIC_RMW8_U_XCHG_I64:
164  case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_S:
165  case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32:
166  case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_S:
167  case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64:
168  case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_S:
169  return 0;
170  case WebAssembly::LOAD16_S_I32:
171  case WebAssembly::LOAD16_S_I32_S:
172  case WebAssembly::LOAD16_U_I32:
173  case WebAssembly::LOAD16_U_I32_S:
174  case WebAssembly::LOAD16_S_I64:
175  case WebAssembly::LOAD16_S_I64_S:
176  case WebAssembly::LOAD16_U_I64:
177  case WebAssembly::LOAD16_U_I64_S:
178  case WebAssembly::ATOMIC_LOAD16_U_I32:
179  case WebAssembly::ATOMIC_LOAD16_U_I32_S:
180  case WebAssembly::ATOMIC_LOAD16_U_I64:
181  case WebAssembly::ATOMIC_LOAD16_U_I64_S:
182  case WebAssembly::STORE16_I32:
183  case WebAssembly::STORE16_I32_S:
184  case WebAssembly::STORE16_I64:
185  case WebAssembly::STORE16_I64_S:
186  case WebAssembly::ATOMIC_STORE16_I32:
187  case WebAssembly::ATOMIC_STORE16_I32_S:
188  case WebAssembly::ATOMIC_STORE16_I64:
189  case WebAssembly::ATOMIC_STORE16_I64_S:
190  case WebAssembly::ATOMIC_RMW16_U_ADD_I32:
191  case WebAssembly::ATOMIC_RMW16_U_ADD_I32_S:
192  case WebAssembly::ATOMIC_RMW16_U_ADD_I64:
193  case WebAssembly::ATOMIC_RMW16_U_ADD_I64_S:
194  case WebAssembly::ATOMIC_RMW16_U_SUB_I32:
195  case WebAssembly::ATOMIC_RMW16_U_SUB_I32_S:
196  case WebAssembly::ATOMIC_RMW16_U_SUB_I64:
197  case WebAssembly::ATOMIC_RMW16_U_SUB_I64_S:
198  case WebAssembly::ATOMIC_RMW16_U_AND_I32:
199  case WebAssembly::ATOMIC_RMW16_U_AND_I32_S:
200  case WebAssembly::ATOMIC_RMW16_U_AND_I64:
201  case WebAssembly::ATOMIC_RMW16_U_AND_I64_S:
202  case WebAssembly::ATOMIC_RMW16_U_OR_I32:
203  case WebAssembly::ATOMIC_RMW16_U_OR_I32_S:
204  case WebAssembly::ATOMIC_RMW16_U_OR_I64:
205  case WebAssembly::ATOMIC_RMW16_U_OR_I64_S:
206  case WebAssembly::ATOMIC_RMW16_U_XOR_I32:
207  case WebAssembly::ATOMIC_RMW16_U_XOR_I32_S:
208  case WebAssembly::ATOMIC_RMW16_U_XOR_I64:
209  case WebAssembly::ATOMIC_RMW16_U_XOR_I64_S:
210  case WebAssembly::ATOMIC_RMW16_U_XCHG_I32:
211  case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_S:
212  case WebAssembly::ATOMIC_RMW16_U_XCHG_I64:
213  case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_S:
214  case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32:
215  case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_S:
216  case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64:
217  case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_S:
218  return 1;
219  case WebAssembly::LOAD_I32:
220  case WebAssembly::LOAD_I32_S:
221  case WebAssembly::LOAD_F32:
222  case WebAssembly::LOAD_F32_S:
223  case WebAssembly::STORE_I32:
224  case WebAssembly::STORE_I32_S:
225  case WebAssembly::STORE_F32:
226  case WebAssembly::STORE_F32_S:
227  case WebAssembly::LOAD32_S_I64:
228  case WebAssembly::LOAD32_S_I64_S:
229  case WebAssembly::LOAD32_U_I64:
230  case WebAssembly::LOAD32_U_I64_S:
231  case WebAssembly::STORE32_I64:
232  case WebAssembly::STORE32_I64_S:
233  case WebAssembly::ATOMIC_LOAD_I32:
234  case WebAssembly::ATOMIC_LOAD_I32_S:
235  case WebAssembly::ATOMIC_LOAD32_U_I64:
236  case WebAssembly::ATOMIC_LOAD32_U_I64_S:
237  case WebAssembly::ATOMIC_STORE_I32:
238  case WebAssembly::ATOMIC_STORE_I32_S:
239  case WebAssembly::ATOMIC_STORE32_I64:
240  case WebAssembly::ATOMIC_STORE32_I64_S:
241  case WebAssembly::ATOMIC_RMW_ADD_I32:
242  case WebAssembly::ATOMIC_RMW_ADD_I32_S:
243  case WebAssembly::ATOMIC_RMW32_U_ADD_I64:
244  case WebAssembly::ATOMIC_RMW32_U_ADD_I64_S:
245  case WebAssembly::ATOMIC_RMW_SUB_I32:
246  case WebAssembly::ATOMIC_RMW_SUB_I32_S:
247  case WebAssembly::ATOMIC_RMW32_U_SUB_I64:
248  case WebAssembly::ATOMIC_RMW32_U_SUB_I64_S:
249  case WebAssembly::ATOMIC_RMW_AND_I32:
250  case WebAssembly::ATOMIC_RMW_AND_I32_S:
251  case WebAssembly::ATOMIC_RMW32_U_AND_I64:
252  case WebAssembly::ATOMIC_RMW32_U_AND_I64_S:
253  case WebAssembly::ATOMIC_RMW_OR_I32:
254  case WebAssembly::ATOMIC_RMW_OR_I32_S:
255  case WebAssembly::ATOMIC_RMW32_U_OR_I64:
256  case WebAssembly::ATOMIC_RMW32_U_OR_I64_S:
257  case WebAssembly::ATOMIC_RMW_XOR_I32:
258  case WebAssembly::ATOMIC_RMW_XOR_I32_S:
259  case WebAssembly::ATOMIC_RMW32_U_XOR_I64:
260  case WebAssembly::ATOMIC_RMW32_U_XOR_I64_S:
261  case WebAssembly::ATOMIC_RMW_XCHG_I32:
262  case WebAssembly::ATOMIC_RMW_XCHG_I32_S:
263  case WebAssembly::ATOMIC_RMW32_U_XCHG_I64:
264  case WebAssembly::ATOMIC_RMW32_U_XCHG_I64_S:
265  case WebAssembly::ATOMIC_RMW_CMPXCHG_I32:
266  case WebAssembly::ATOMIC_RMW_CMPXCHG_I32_S:
267  case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64:
268  case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_S:
269  case WebAssembly::ATOMIC_NOTIFY:
270  case WebAssembly::ATOMIC_NOTIFY_S:
271  case WebAssembly::ATOMIC_WAIT_I32:
272  case WebAssembly::ATOMIC_WAIT_I32_S:
273  return 2;
274  case WebAssembly::LOAD_I64:
275  case WebAssembly::LOAD_I64_S:
276  case WebAssembly::LOAD_F64:
277  case WebAssembly::LOAD_F64_S:
278  case WebAssembly::STORE_I64:
279  case WebAssembly::STORE_I64_S:
280  case WebAssembly::STORE_F64:
281  case WebAssembly::STORE_F64_S:
282  case WebAssembly::ATOMIC_LOAD_I64:
283  case WebAssembly::ATOMIC_LOAD_I64_S:
284  case WebAssembly::ATOMIC_STORE_I64:
285  case WebAssembly::ATOMIC_STORE_I64_S:
286  case WebAssembly::ATOMIC_RMW_ADD_I64:
287  case WebAssembly::ATOMIC_RMW_ADD_I64_S:
288  case WebAssembly::ATOMIC_RMW_SUB_I64:
289  case WebAssembly::ATOMIC_RMW_SUB_I64_S:
290  case WebAssembly::ATOMIC_RMW_AND_I64:
291  case WebAssembly::ATOMIC_RMW_AND_I64_S:
292  case WebAssembly::ATOMIC_RMW_OR_I64:
293  case WebAssembly::ATOMIC_RMW_OR_I64_S:
294  case WebAssembly::ATOMIC_RMW_XOR_I64:
295  case WebAssembly::ATOMIC_RMW_XOR_I64_S:
296  case WebAssembly::ATOMIC_RMW_XCHG_I64:
297  case WebAssembly::ATOMIC_RMW_XCHG_I64_S:
298  case WebAssembly::ATOMIC_RMW_CMPXCHG_I64:
299  case WebAssembly::ATOMIC_RMW_CMPXCHG_I64_S:
300  case WebAssembly::ATOMIC_WAIT_I64:
301  case WebAssembly::ATOMIC_WAIT_I64_S:
302  return 3;
303  case WebAssembly::LOAD_v16i8:
304  case WebAssembly::LOAD_v16i8_S:
305  case WebAssembly::LOAD_v8i16:
306  case WebAssembly::LOAD_v8i16_S:
307  case WebAssembly::LOAD_v4i32:
308  case WebAssembly::LOAD_v4i32_S:
309  case WebAssembly::LOAD_v2i64:
310  case WebAssembly::LOAD_v2i64_S:
311  case WebAssembly::LOAD_v4f32:
312  case WebAssembly::LOAD_v4f32_S:
313  case WebAssembly::LOAD_v2f64:
314  case WebAssembly::LOAD_v2f64_S:
315  case WebAssembly::STORE_v16i8:
316  case WebAssembly::STORE_v16i8_S:
317  case WebAssembly::STORE_v8i16:
318  case WebAssembly::STORE_v8i16_S:
319  case WebAssembly::STORE_v4i32:
320  case WebAssembly::STORE_v4i32_S:
321  case WebAssembly::STORE_v2i64:
322  case WebAssembly::STORE_v2i64_S:
323  case WebAssembly::STORE_v4f32:
324  case WebAssembly::STORE_v4f32_S:
325  case WebAssembly::STORE_v2f64:
326  case WebAssembly::STORE_v2f64_S:
327  return 4;
328  default:
329  llvm_unreachable("Only loads and stores have p2align values");
330  }
331 }
332 
333 /// The operand number of the load or store address in load/store instructions.
334 static const unsigned LoadAddressOperandNo = 3;
335 static const unsigned StoreAddressOperandNo = 2;
336 
337 /// The operand number of the load or store p2align in load/store instructions.
338 static const unsigned LoadP2AlignOperandNo = 1;
339 static const unsigned StoreP2AlignOperandNo = 0;
340 
341 /// This is used to indicate block signatures.
342 enum class ExprType : unsigned {
343  Void = 0x40,
344  I32 = 0x7F,
345  I64 = 0x7E,
346  F32 = 0x7D,
347  F64 = 0x7C,
348  V128 = 0x7B,
349  ExceptRef = 0x68
350 };
351 
352 /// Instruction opcodes emitted via means other than CodeGen.
353 static const unsigned Nop = 0x01;
354 static const unsigned End = 0x0b;
355 
356 wasm::ValType toValType(const MVT &Ty);
357 
358 } // end namespace WebAssembly
359 } // end namespace llvm
360 
361 #endif
static const unsigned LoadP2AlignOperandNo
The operand number of the load or store p2align in load/store instructions.
32-bit floating-point immediates.
static const unsigned LoadAddressOperandNo
The operand number of the load or store address in load/store instructions.
This class represents lattice values for constants.
Definition: AllocatorList.h:24
std::unique_ptr< MCObjectTargetWriter > createWebAssemblyWasmObjectWriter(bool Is64Bit)
32-bit unsigned memory offsets.
Basic block label in a branch construct.
static const unsigned StoreP2AlignOperandNo
signature immediate for block/loop.
wasm::ValType toValType(const MVT &Ty)
Machine Value Type.
MCCodeEmitter * createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII)
TOF
Target Operand Flag enum.
static const unsigned End
unsigned GetDefaultP2Align(unsigned Opcode)
Return the default p2align value for a load or store with the given opcode.
type signature immediate for call_indirect.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
ExprType
This is used to indicate block signatures.
MCAsmBackend * createWebAssemblyAsmBackend(const Triple &TT)
static const unsigned StoreAddressOperandNo
64-bit floating-point immediates.
32-bit unsigned function indices.
p2align immediate for load and store address alignment.
static const unsigned Nop
Instruction opcodes emitted via means other than CodeGen.
Target & getTheWebAssemblyTarget32()
Target & getTheWebAssemblyTarget64()