LLVM  6.0.0svn
MipsAsmPrinter.cpp
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1 //===- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer --------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "MipsAsmPrinter.h"
21 #include "Mips.h"
22 #include "MipsMCInstLower.h"
23 #include "MipsMachineFunction.h"
24 #include "MipsSubtarget.h"
25 #include "MipsTargetMachine.h"
26 #include "MipsTargetStreamer.h"
27 #include "llvm/ADT/SmallString.h"
28 #include "llvm/ADT/StringRef.h"
29 #include "llvm/ADT/Triple.h"
30 #include "llvm/ADT/Twine.h"
31 #include "llvm/BinaryFormat/ELF.h"
41 #include "llvm/IR/Attributes.h"
42 #include "llvm/IR/BasicBlock.h"
43 #include "llvm/IR/DataLayout.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/InlineAsm.h"
46 #include "llvm/IR/Instructions.h"
47 #include "llvm/MC/MCContext.h"
48 #include "llvm/MC/MCExpr.h"
49 #include "llvm/MC/MCInst.h"
50 #include "llvm/MC/MCInstBuilder.h"
52 #include "llvm/MC/MCSectionELF.h"
53 #include "llvm/MC/MCSymbol.h"
54 #include "llvm/MC/MCSymbolELF.h"
55 #include "llvm/Support/Casting.h"
60 #include <cassert>
61 #include <cstdint>
62 #include <map>
63 #include <memory>
64 #include <string>
65 #include <vector>
66 
67 using namespace llvm;
68 
69 #define DEBUG_TYPE "mips-asm-printer"
70 
71 MipsTargetStreamer &MipsAsmPrinter::getTargetStreamer() const {
72  return static_cast<MipsTargetStreamer &>(*OutStreamer->getTargetStreamer());
73 }
74 
77 
79  if (Subtarget->inMips16Mode())
80  for (std::map<
81  const char *,
82  const Mips16HardFloatInfo::FuncSignature *>::const_iterator
83  it = MipsFI->StubsNeeded.begin();
84  it != MipsFI->StubsNeeded.end(); ++it) {
85  const char *Symbol = it->first;
86  const Mips16HardFloatInfo::FuncSignature *Signature = it->second;
87  if (StubsNeeded.find(Symbol) == StubsNeeded.end())
88  StubsNeeded[Symbol] = Signature;
89  }
90  MCP = MF.getConstantPool();
91 
92  // In NaCl, all indirect jump targets must be aligned to bundle size.
93  if (Subtarget->isTargetNaCl())
94  NaClAlignIndirectJumpTargets(MF);
95 
97 
98  emitXRayTable();
99 
100  return true;
101 }
102 
103 bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {
104  MCOp = MCInstLowering.LowerOperand(MO);
105  return MCOp.isValid();
106 }
107 
108 #include "MipsGenMCPseudoLowering.inc"
109 
110 // Lower PseudoReturn/PseudoIndirectBranch/PseudoIndirectBranch64 to JR, JR_MM,
111 // JALR, or JALR64 as appropriate for the target.
112 void MipsAsmPrinter::emitPseudoIndirectBranch(MCStreamer &OutStreamer,
113  const MachineInstr *MI) {
114  bool HasLinkReg = false;
115  bool InMicroMipsMode = Subtarget->inMicroMipsMode();
116  MCInst TmpInst0;
117 
118  if (Subtarget->hasMips64r6()) {
119  // MIPS64r6 should use (JALR64 ZERO_64, $rs)
120  TmpInst0.setOpcode(Mips::JALR64);
121  HasLinkReg = true;
122  } else if (Subtarget->hasMips32r6()) {
123  // MIPS32r6 should use (JALR ZERO, $rs)
124  if (InMicroMipsMode)
125  TmpInst0.setOpcode(Mips::JRC16_MMR6);
126  else {
127  TmpInst0.setOpcode(Mips::JALR);
128  HasLinkReg = true;
129  }
130  } else if (Subtarget->inMicroMipsMode())
131  // microMIPS should use (JR_MM $rs)
132  TmpInst0.setOpcode(Mips::JR_MM);
133  else {
134  // Everything else should use (JR $rs)
135  TmpInst0.setOpcode(Mips::JR);
136  }
137 
138  MCOperand MCOp;
139 
140  if (HasLinkReg) {
141  unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
142  TmpInst0.addOperand(MCOperand::createReg(ZeroReg));
143  }
144 
145  lowerOperand(MI->getOperand(0), MCOp);
146  TmpInst0.addOperand(MCOp);
147 
148  EmitToStreamer(OutStreamer, TmpInst0);
149 }
150 
152  MipsTargetStreamer &TS = getTargetStreamer();
153  unsigned Opc = MI->getOpcode();
155 
156  if (MI->isDebugValue()) {
157  SmallString<128> Str;
158  raw_svector_ostream OS(Str);
159 
160  PrintDebugValueComment(MI, OS);
161  return;
162  }
163 
164  // If we just ended a constant pool, mark it as such.
165  if (InConstantPool && Opc != Mips::CONSTPOOL_ENTRY) {
166  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
167  InConstantPool = false;
168  }
169  if (Opc == Mips::CONSTPOOL_ENTRY) {
170  // CONSTPOOL_ENTRY - This instruction represents a floating
171  // constant pool in the function. The first operand is the ID#
172  // for this instruction, the second is the index into the
173  // MachineConstantPool that this is, the third is the size in
174  // bytes of this constant pool entry.
175  // The required alignment is specified on the basic block holding this MI.
176  //
177  unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
178  unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
179 
180  // If this is the first entry of the pool, mark it.
181  if (!InConstantPool) {
182  OutStreamer->EmitDataRegion(MCDR_DataRegion);
183  InConstantPool = true;
184  }
185 
186  OutStreamer->EmitLabel(GetCPISymbol(LabelId));
187 
188  const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
189  if (MCPE.isMachineConstantPoolEntry())
191  else
193  return;
194  }
195 
196  switch (Opc) {
197  case Mips::PATCHABLE_FUNCTION_ENTER:
199  return;
200  case Mips::PATCHABLE_FUNCTION_EXIT:
202  return;
203  case Mips::PATCHABLE_TAIL_CALL:
205  return;
206  }
207 
210 
211  do {
212  // Do any auto-generated pseudo lowerings.
213  if (emitPseudoExpansionLowering(*OutStreamer, &*I))
214  continue;
215 
216  if (I->getOpcode() == Mips::PseudoReturn ||
217  I->getOpcode() == Mips::PseudoReturn64 ||
218  I->getOpcode() == Mips::PseudoIndirectBranch ||
219  I->getOpcode() == Mips::PseudoIndirectBranch64 ||
220  I->getOpcode() == Mips::TAILCALLREG ||
221  I->getOpcode() == Mips::TAILCALLREG64) {
222  emitPseudoIndirectBranch(*OutStreamer, &*I);
223  continue;
224  }
225 
226  // The inMips16Mode() test is not permanent.
227  // Some instructions are marked as pseudo right now which
228  // would make the test fail for the wrong reason but
229  // that will be fixed soon. We need this here because we are
230  // removing another test for this situation downstream in the
231  // callchain.
232  //
233  if (I->isPseudo() && !Subtarget->inMips16Mode()
234  && !isLongBranchPseudo(I->getOpcode()))
235  llvm_unreachable("Pseudo opcode found in EmitInstruction()");
236 
237  MCInst TmpInst0;
238  MCInstLowering.Lower(&*I, TmpInst0);
239  EmitToStreamer(*OutStreamer, TmpInst0);
240  } while ((++I != E) && I->isInsideBundle()); // Delay slot check
241 }
242 
243 //===----------------------------------------------------------------------===//
244 //
245 // Mips Asm Directives
246 //
247 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
248 // Describe the stack frame.
249 //
250 // -- Mask directives "(f)mask bitmask, offset"
251 // Tells the assembler which registers are saved and where.
252 // bitmask - contain a little endian bitset indicating which registers are
253 // saved on function prologue (e.g. with a 0x80000000 mask, the
254 // assembler knows the register 31 (RA) is saved at prologue.
255 // offset - the position before stack pointer subtraction indicating where
256 // the first saved register on prologue is located. (e.g. with a
257 //
258 // Consider the following function prologue:
259 //
260 // .frame $fp,48,$ra
261 // .mask 0xc0000000,-8
262 // addiu $sp, $sp, -48
263 // sw $ra, 40($sp)
264 // sw $fp, 36($sp)
265 //
266 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
267 // 30 (FP) are saved at prologue. As the save order on prologue is from
268 // left to right, RA is saved first. A -8 offset means that after the
269 // stack pointer subtration, the first register in the mask (RA) will be
270 // saved at address 48-8=40.
271 //
272 //===----------------------------------------------------------------------===//
273 
274 //===----------------------------------------------------------------------===//
275 // Mask directives
276 //===----------------------------------------------------------------------===//
277 
278 // Create a bitmask with all callee saved registers for CPU or Floating Point
279 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
281  // CPU and FPU Saved Registers Bitmasks
282  unsigned CPUBitmask = 0, FPUBitmask = 0;
283  int CPUTopSavedRegOff, FPUTopSavedRegOff;
284 
285  // Set the CPU and FPU Bitmasks
286  const MachineFrameInfo &MFI = MF->getFrameInfo();
288  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
289  // size of stack area to which FP callee-saved regs are saved.
290  unsigned CPURegSize = TRI->getRegSizeInBits(Mips::GPR32RegClass) / 8;
291  unsigned FGR32RegSize = TRI->getRegSizeInBits(Mips::FGR32RegClass) / 8;
292  unsigned AFGR64RegSize = TRI->getRegSizeInBits(Mips::AFGR64RegClass) / 8;
293  bool HasAFGR64Reg = false;
294  unsigned CSFPRegsSize = 0;
295 
296  for (const auto &I : CSI) {
297  unsigned Reg = I.getReg();
298  unsigned RegNum = TRI->getEncodingValue(Reg);
299 
300  // If it's a floating point register, set the FPU Bitmask.
301  // If it's a general purpose register, set the CPU Bitmask.
302  if (Mips::FGR32RegClass.contains(Reg)) {
303  FPUBitmask |= (1 << RegNum);
304  CSFPRegsSize += FGR32RegSize;
305  } else if (Mips::AFGR64RegClass.contains(Reg)) {
306  FPUBitmask |= (3 << RegNum);
307  CSFPRegsSize += AFGR64RegSize;
308  HasAFGR64Reg = true;
309  } else if (Mips::GPR32RegClass.contains(Reg))
310  CPUBitmask |= (1 << RegNum);
311  }
312 
313  // FP Regs are saved right below where the virtual frame pointer points to.
314  FPUTopSavedRegOff = FPUBitmask ?
315  (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
316 
317  // CPU Regs are saved below FP Regs.
318  CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
319 
320  MipsTargetStreamer &TS = getTargetStreamer();
321  // Print CPUBitmask
322  TS.emitMask(CPUBitmask, CPUTopSavedRegOff);
323 
324  // Print FPUBitmask
325  TS.emitFMask(FPUBitmask, FPUTopSavedRegOff);
326 }
327 
328 //===----------------------------------------------------------------------===//
329 // Frame and Set directives
330 //===----------------------------------------------------------------------===//
331 
332 /// Frame Directive
335 
336  unsigned stackReg = RI.getFrameRegister(*MF);
337  unsigned returnReg = RI.getRARegister();
338  unsigned stackSize = MF->getFrameInfo().getStackSize();
339 
340  getTargetStreamer().emitFrame(stackReg, stackSize, returnReg);
341 }
342 
343 /// Emit Set directives.
345  switch (static_cast<MipsTargetMachine &>(TM).getABI().GetEnumValue()) {
346  case MipsABIInfo::ABI::O32: return "abi32";
347  case MipsABIInfo::ABI::N32: return "abiN32";
348  case MipsABIInfo::ABI::N64: return "abi64";
349  default: llvm_unreachable("Unknown Mips ABI");
350  }
351 }
352 
354  MipsTargetStreamer &TS = getTargetStreamer();
355 
356  // NaCl sandboxing requires that indirect call instructions are masked.
357  // This means that function entry points should be bundle-aligned.
358  if (Subtarget->isTargetNaCl())
360 
361  if (Subtarget->inMicroMipsMode()) {
363  TS.setUsesMicroMips();
364  } else
366 
367  if (Subtarget->inMips16Mode())
369  else
371 
373  OutStreamer->EmitLabel(CurrentFnSym);
374 }
375 
376 /// EmitFunctionBodyStart - Targets can override this to emit stuff before
377 /// the first basic block in the function.
379  MipsTargetStreamer &TS = getTargetStreamer();
380 
382 
383  bool IsNakedFunction = MF->getFunction()->hasFnAttribute(Attribute::Naked);
384  if (!IsNakedFunction)
386 
387  if (!IsNakedFunction)
389 
390  if (!Subtarget->inMips16Mode()) {
394  }
395 }
396 
397 /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
398 /// the last basic block in the function.
400  MipsTargetStreamer &TS = getTargetStreamer();
401 
402  // There are instruction for this macros, but they must
403  // always be at the function end, and we can't emit and
404  // break with BB logic.
405  if (!Subtarget->inMips16Mode()) {
406  TS.emitDirectiveSetAt();
409  }
411  // Make sure to terminate any constant pools that were at the end
412  // of the function.
413  if (!InConstantPool)
414  return;
415  InConstantPool = false;
416  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
417 }
418 
421  MipsTargetStreamer &TS = getTargetStreamer();
422  if (MBB.empty())
423  TS.emitDirectiveInsn();
424 }
425 
426 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
427 /// exactly one predecessor and the control transfer mechanism between
428 /// the predecessor and this block is a fall-through.
430  MBB) const {
431  // The predecessor has to be immediately before this block.
432  const MachineBasicBlock *Pred = *MBB->pred_begin();
433 
434  // If the predecessor is a switch statement, assume a jump table
435  // implementation, so it is not a fall through.
436  if (const BasicBlock *bb = Pred->getBasicBlock())
437  if (isa<SwitchInst>(bb->getTerminator()))
438  return false;
439 
440  // If this is a landing pad, it isn't a fall through. If it has no preds,
441  // then nothing falls through to it.
442  if (MBB->isEHPad() || MBB->pred_empty())
443  return false;
444 
445  // If there isn't exactly one predecessor, it can't be a fall through.
447  ++PI2;
448 
449  if (PI2 != MBB->pred_end())
450  return false;
451 
452  // The predecessor has to be immediately before this block.
453  if (!Pred->isLayoutSuccessor(MBB))
454  return false;
455 
456  // If the block is completely empty, then it definitely does fall through.
457  if (Pred->empty())
458  return true;
459 
460  // Otherwise, check the last instruction.
461  // Check if the last terminator is an unconditional branch.
463  while (I != Pred->begin() && !(--I)->isTerminator()) ;
464 
465  return !I->isBarrier();
466 }
467 
468 // Print out an operand for an inline asm expression.
469 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
470  unsigned AsmVariant, const char *ExtraCode,
471  raw_ostream &O) {
472  // Does this asm operand have a single letter operand modifier?
473  if (ExtraCode && ExtraCode[0]) {
474  if (ExtraCode[1] != 0) return true; // Unknown modifier.
475 
476  const MachineOperand &MO = MI->getOperand(OpNum);
477  switch (ExtraCode[0]) {
478  default:
479  // See if this is a generic print operand
480  return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O);
481  case 'X': // hex const int
483  return true;
484  O << "0x" << Twine::utohexstr(MO.getImm());
485  return false;
486  case 'x': // hex const int (low 16 bits)
488  return true;
489  O << "0x" << Twine::utohexstr(MO.getImm() & 0xffff);
490  return false;
491  case 'd': // decimal const int
493  return true;
494  O << MO.getImm();
495  return false;
496  case 'm': // decimal const int minus 1
498  return true;
499  O << MO.getImm() - 1;
500  return false;
501  case 'z':
502  // $0 if zero, regular printing otherwise
503  if (MO.getType() == MachineOperand::MO_Immediate && MO.getImm() == 0) {
504  O << "$0";
505  return false;
506  }
507  // If not, call printOperand as normal.
508  break;
509  case 'D': // Second part of a double word register operand
510  case 'L': // Low order register of a double word register operand
511  case 'M': // High order register of a double word register operand
512  {
513  if (OpNum == 0)
514  return true;
515  const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
516  if (!FlagsOP.isImm())
517  return true;
518  unsigned Flags = FlagsOP.getImm();
519  unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
520  // Number of registers represented by this operand. We are looking
521  // for 2 for 32 bit mode and 1 for 64 bit mode.
522  if (NumVals != 2) {
523  if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
524  unsigned Reg = MO.getReg();
525  O << '$' << MipsInstPrinter::getRegisterName(Reg);
526  return false;
527  }
528  return true;
529  }
530 
531  unsigned RegOp = OpNum;
532  if (!Subtarget->isGP64bit()){
533  // Endianness reverses which register holds the high or low value
534  // between M and L.
535  switch(ExtraCode[0]) {
536  case 'M':
537  RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
538  break;
539  case 'L':
540  RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
541  break;
542  case 'D': // Always the second part
543  RegOp = OpNum + 1;
544  }
545  if (RegOp >= MI->getNumOperands())
546  return true;
547  const MachineOperand &MO = MI->getOperand(RegOp);
548  if (!MO.isReg())
549  return true;
550  unsigned Reg = MO.getReg();
551  O << '$' << MipsInstPrinter::getRegisterName(Reg);
552  return false;
553  }
554  }
555  case 'w':
556  // Print MSA registers for the 'f' constraint
557  // In LLVM, the 'w' modifier doesn't need to do anything.
558  // We can just call printOperand as normal.
559  break;
560  }
561  }
562 
563  printOperand(MI, OpNum, O);
564  return false;
565 }
566 
568  unsigned OpNum, unsigned AsmVariant,
569  const char *ExtraCode,
570  raw_ostream &O) {
571  assert(OpNum + 1 < MI->getNumOperands() && "Insufficient operands");
572  const MachineOperand &BaseMO = MI->getOperand(OpNum);
573  const MachineOperand &OffsetMO = MI->getOperand(OpNum + 1);
574  assert(BaseMO.isReg() && "Unexpected base pointer for inline asm memory operand.");
575  assert(OffsetMO.isImm() && "Unexpected offset for inline asm memory operand.");
576  int Offset = OffsetMO.getImm();
577 
578  // Currently we are expecting either no ExtraCode or 'D'
579  if (ExtraCode) {
580  if (ExtraCode[0] == 'D')
581  Offset += 4;
582  else
583  return true; // Unknown modifier.
584  // FIXME: M = high order bits
585  // FIXME: L = low order bits
586  }
587 
588  O << Offset << "($" << MipsInstPrinter::getRegisterName(BaseMO.getReg()) << ")";
589 
590  return false;
591 }
592 
593 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
594  raw_ostream &O) {
595  const MachineOperand &MO = MI->getOperand(opNum);
596  bool closeP = false;
597 
598  if (MO.getTargetFlags())
599  closeP = true;
600 
601  switch(MO.getTargetFlags()) {
602  case MipsII::MO_GPREL: O << "%gp_rel("; break;
603  case MipsII::MO_GOT_CALL: O << "%call16("; break;
604  case MipsII::MO_GOT: O << "%got("; break;
605  case MipsII::MO_ABS_HI: O << "%hi("; break;
606  case MipsII::MO_ABS_LO: O << "%lo("; break;
607  case MipsII::MO_HIGHER: O << "%higher("; break;
608  case MipsII::MO_HIGHEST: O << "%highest(("; break;
609  case MipsII::MO_TLSGD: O << "%tlsgd("; break;
610  case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
611  case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
612  case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
613  case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
614  case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
615  case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
616  case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
617  case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
618  }
619 
620  switch (MO.getType()) {
622  O << '$'
624  break;
625 
627  O << MO.getImm();
628  break;
629 
631  MO.getMBB()->getSymbol()->print(O, MAI);
632  return;
633 
635  getSymbol(MO.getGlobal())->print(O, MAI);
636  break;
637 
640  O << BA->getName();
641  break;
642  }
643 
645  O << getDataLayout().getPrivateGlobalPrefix() << "CPI"
646  << getFunctionNumber() << "_" << MO.getIndex();
647  if (MO.getOffset())
648  O << "+" << MO.getOffset();
649  break;
650 
651  default:
652  llvm_unreachable("<unknown operand type>");
653  }
654 
655  if (closeP) O << ")";
656 }
657 
658 void MipsAsmPrinter::
659 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
660  // Load/Store memory operands -- imm($reg)
661  // If PIC target the target is loaded as the
662  // pattern lw $25,%call16($28)
663 
664  // opNum can be invalid if instruction has reglist as operand.
665  // MemOperand is always last operand of instruction (base + offset).
666  switch (MI->getOpcode()) {
667  default:
668  break;
669  case Mips::SWM32_MM:
670  case Mips::LWM32_MM:
671  opNum = MI->getNumOperands() - 2;
672  break;
673  }
674 
675  printOperand(MI, opNum+1, O);
676  O << "(";
677  printOperand(MI, opNum, O);
678  O << ")";
679 }
680 
681 void MipsAsmPrinter::
682 printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
683  // when using stack locations for not load/store instructions
684  // print the same way as all normal 3 operand instructions.
685  printOperand(MI, opNum, O);
686  O << ", ";
687  printOperand(MI, opNum+1, O);
688 }
689 
690 void MipsAsmPrinter::
691 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
692  const char *Modifier) {
693  const MachineOperand &MO = MI->getOperand(opNum);
695 }
696 
697 void MipsAsmPrinter::
698 printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O) {
699  for (int i = opNum, e = MI->getNumOperands(); i != e; ++i) {
700  if (i != opNum) O << ", ";
701  printOperand(MI, i, O);
702  }
703 }
704 
706  MipsTargetStreamer &TS = getTargetStreamer();
707 
708  // MipsTargetStreamer has an initialization order problem when emitting an
709  // object file directly (see MipsTargetELFStreamer for full details). Work
710  // around it by re-initializing the PIC state here.
712 
713  // Compute MIPS architecture attributes based on the default subtarget
714  // that we'd have constructed. Module level directives aren't LTO
715  // clean anyhow.
716  // FIXME: For ifunc related functions we could iterate over and look
717  // for a feature string that doesn't match the default one.
718  const Triple &TT = TM.getTargetTriple();
721  const MipsTargetMachine &MTM = static_cast<const MipsTargetMachine &>(TM);
722  const MipsSubtarget STI(TT, CPU, FS, MTM.isLittleEndian(), MTM, 0);
723 
724  bool IsABICalls = STI.isABICalls();
725  const MipsABIInfo &ABI = MTM.getABI();
726  if (IsABICalls) {
728  // FIXME: This condition should be a lot more complicated that it is here.
729  // Ideally it should test for properties of the ABI and not the ABI
730  // itself.
731  // For the moment, I'm only correcting enough to make MIPS-IV work.
732  if (!isPositionIndependent() && STI.hasSym32())
734  }
735 
736  // Tell the assembler which ABI we are using
737  std::string SectionName = std::string(".mdebug.") + getCurrentABIString();
738  OutStreamer->SwitchSection(
739  OutContext.getELFSection(SectionName, ELF::SHT_PROGBITS, 0));
740 
741  // NaN: At the moment we only support:
742  // 1. .nan legacy (default)
743  // 2. .nan 2008
744  STI.isNaN2008() ? TS.emitDirectiveNaN2008()
745  : TS.emitDirectiveNaNLegacy();
746 
747  // TODO: handle O64 ABI
748 
749  TS.updateABIInfo(STI);
750 
751  // We should always emit a '.module fp=...' but binutils 2.24 does not accept
752  // it. We therefore emit it when it contradicts the ABI defaults (-mfpxx or
753  // -mfp64) and omit it otherwise.
754  if (ABI.IsO32() && (STI.isABI_FPXX() || STI.isFP64bit()))
756 
757  // We should always emit a '.module [no]oddspreg' but binutils 2.24 does not
758  // accept it. We therefore emit it when it contradicts the default or an
759  // option has changed the default (i.e. FPXX) and omit it otherwise.
760  if (ABI.IsO32() && (!STI.useOddSPReg() || STI.isABI_FPXX()))
762 }
763 
764 void MipsAsmPrinter::emitInlineAsmStart() const {
765  MipsTargetStreamer &TS = getTargetStreamer();
766 
767  // GCC's choice of assembler options for inline assembly code ('at', 'macro'
768  // and 'reorder') is different from LLVM's choice for generated code ('noat',
769  // 'nomacro' and 'noreorder').
770  // In order to maintain compatibility with inline assembly code which depends
771  // on GCC's assembler options being used, we have to switch to those options
772  // for the duration of the inline assembly block and then switch back.
774  TS.emitDirectiveSetAt();
777  OutStreamer->AddBlankLine();
778 }
779 
780 void MipsAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
781  const MCSubtargetInfo *EndInfo) const {
782  OutStreamer->AddBlankLine();
783  getTargetStreamer().emitDirectiveSetPop();
784 }
785 
786 void MipsAsmPrinter::EmitJal(const MCSubtargetInfo &STI, MCSymbol *Symbol) {
787  MCInst I;
788  I.setOpcode(Mips::JAL);
789  I.addOperand(
791  OutStreamer->EmitInstruction(I, STI);
792 }
793 
794 void MipsAsmPrinter::EmitInstrReg(const MCSubtargetInfo &STI, unsigned Opcode,
795  unsigned Reg) {
796  MCInst I;
797  I.setOpcode(Opcode);
799  OutStreamer->EmitInstruction(I, STI);
800 }
801 
802 void MipsAsmPrinter::EmitInstrRegReg(const MCSubtargetInfo &STI,
803  unsigned Opcode, unsigned Reg1,
804  unsigned Reg2) {
805  MCInst I;
806  //
807  // Because of the current td files for Mips32, the operands for MTC1
808  // appear backwards from their normal assembly order. It's not a trivial
809  // change to fix this in the td file so we adjust for it here.
810  //
811  if (Opcode == Mips::MTC1) {
812  unsigned Temp = Reg1;
813  Reg1 = Reg2;
814  Reg2 = Temp;
815  }
816  I.setOpcode(Opcode);
819  OutStreamer->EmitInstruction(I, STI);
820 }
821 
822 void MipsAsmPrinter::EmitInstrRegRegReg(const MCSubtargetInfo &STI,
823  unsigned Opcode, unsigned Reg1,
824  unsigned Reg2, unsigned Reg3) {
825  MCInst I;
826  I.setOpcode(Opcode);
830  OutStreamer->EmitInstruction(I, STI);
831 }
832 
833 void MipsAsmPrinter::EmitMovFPIntPair(const MCSubtargetInfo &STI,
834  unsigned MovOpc, unsigned Reg1,
835  unsigned Reg2, unsigned FPReg1,
836  unsigned FPReg2, bool LE) {
837  if (!LE) {
838  unsigned temp = Reg1;
839  Reg1 = Reg2;
840  Reg2 = temp;
841  }
842  EmitInstrRegReg(STI, MovOpc, Reg1, FPReg1);
843  EmitInstrRegReg(STI, MovOpc, Reg2, FPReg2);
844 }
845 
846 void MipsAsmPrinter::EmitSwapFPIntParams(const MCSubtargetInfo &STI,
848  bool LE, bool ToFP) {
849  using namespace Mips16HardFloatInfo;
850 
851  unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1;
852  switch (PV) {
853  case FSig:
854  EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);
855  break;
856  case FFSig:
857  EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F14, LE);
858  break;
859  case FDSig:
860  EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);
861  EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
862  break;
863  case DSig:
864  EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
865  break;
866  case DDSig:
867  EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
868  EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
869  break;
870  case DFSig:
871  EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
872  EmitInstrRegReg(STI, MovOpc, Mips::A2, Mips::F14);
873  break;
874  case NoSig:
875  return;
876  }
877 }
878 
879 void MipsAsmPrinter::EmitSwapFPIntRetval(
881  bool LE) {
882  using namespace Mips16HardFloatInfo;
883 
884  unsigned MovOpc = Mips::MFC1;
885  switch (RV) {
886  case FRet:
887  EmitInstrRegReg(STI, MovOpc, Mips::V0, Mips::F0);
888  break;
889  case DRet:
890  EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
891  break;
892  case CFRet:
893  EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
894  break;
895  case CDRet:
896  EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
897  EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F2, Mips::F3, LE);
898  break;
899  case NoFPRet:
900  break;
901  }
902 }
903 
904 void MipsAsmPrinter::EmitFPCallStub(
905  const char *Symbol, const Mips16HardFloatInfo::FuncSignature *Signature) {
906  using namespace Mips16HardFloatInfo;
907 
908  MCSymbol *MSymbol = OutContext.getOrCreateSymbol(StringRef(Symbol));
909  bool LE = getDataLayout().isLittleEndian();
910  // Construct a local MCSubtargetInfo here.
911  // This is because the MachineFunction won't exist (but have not yet been
912  // freed) and since we're at the global level we can use the default
913  // constructed subtarget.
914  std::unique_ptr<MCSubtargetInfo> STI(TM.getTarget().createMCSubtargetInfo(
917 
918  //
919  // .global xxxx
920  //
921  OutStreamer->EmitSymbolAttribute(MSymbol, MCSA_Global);
922  const char *RetType;
923  //
924  // make the comment field identifying the return and parameter
925  // types of the floating point stub
926  // # Stub function to call rettype xxxx (params)
927  //
928  switch (Signature->RetSig) {
929  case FRet:
930  RetType = "float";
931  break;
932  case DRet:
933  RetType = "double";
934  break;
935  case CFRet:
936  RetType = "complex";
937  break;
938  case CDRet:
939  RetType = "double complex";
940  break;
941  case NoFPRet:
942  RetType = "";
943  break;
944  }
945  const char *Parms;
946  switch (Signature->ParamSig) {
947  case FSig:
948  Parms = "float";
949  break;
950  case FFSig:
951  Parms = "float, float";
952  break;
953  case FDSig:
954  Parms = "float, double";
955  break;
956  case DSig:
957  Parms = "double";
958  break;
959  case DDSig:
960  Parms = "double, double";
961  break;
962  case DFSig:
963  Parms = "double, float";
964  break;
965  case NoSig:
966  Parms = "";
967  break;
968  }
969  OutStreamer->AddComment("\t# Stub function to call " + Twine(RetType) + " " +
970  Twine(Symbol) + " (" + Twine(Parms) + ")");
971  //
972  // probably not necessary but we save and restore the current section state
973  //
974  OutStreamer->PushSection();
975  //
976  // .section mips16.call.fpxxxx,"ax",@progbits
977  //
979  ".mips16.call.fp." + std::string(Symbol), ELF::SHT_PROGBITS,
981  OutStreamer->SwitchSection(M, nullptr);
982  //
983  // .align 2
984  //
985  OutStreamer->EmitValueToAlignment(4);
986  MipsTargetStreamer &TS = getTargetStreamer();
987  //
988  // .set nomips16
989  // .set nomicromips
990  //
993  //
994  // .ent __call_stub_fp_xxxx
995  // .type __call_stub_fp_xxxx,@function
996  // __call_stub_fp_xxxx:
997  //
998  std::string x = "__call_stub_fp_" + std::string(Symbol);
999  MCSymbolELF *Stub =
1000  cast<MCSymbolELF>(OutContext.getOrCreateSymbol(StringRef(x)));
1001  TS.emitDirectiveEnt(*Stub);
1002  MCSymbol *MType =
1003  OutContext.getOrCreateSymbol("__call_stub_fp_" + Twine(Symbol));
1004  OutStreamer->EmitSymbolAttribute(MType, MCSA_ELF_TypeFunction);
1005  OutStreamer->EmitLabel(Stub);
1006 
1007  // Only handle non-pic for now.
1009  "should not be here if we are compiling pic");
1011  //
1012  // We need to add a MipsMCExpr class to MCTargetDesc to fully implement
1013  // stubs without raw text but this current patch is for compiler generated
1014  // functions and they all return some value.
1015  // The calling sequence for non pic is different in that case and we need
1016  // to implement %lo and %hi in order to handle the case of no return value
1017  // See the corresponding method in Mips16HardFloat for details.
1018  //
1019  // mov the return address to S2.
1020  // we have no stack space to store it and we are about to make another call.
1021  // We need to make sure that the enclosing function knows to save S2
1022  // This should have already been handled.
1023  //
1024  // Mov $18, $31
1025 
1026  EmitInstrRegRegReg(*STI, Mips::OR, Mips::S2, Mips::RA, Mips::ZERO);
1027 
1028  EmitSwapFPIntParams(*STI, Signature->ParamSig, LE, true);
1029 
1030  // Jal xxxx
1031  //
1032  EmitJal(*STI, MSymbol);
1033 
1034  // fix return values
1035  EmitSwapFPIntRetval(*STI, Signature->RetSig, LE);
1036  //
1037  // do the return
1038  // if (Signature->RetSig == NoFPRet)
1039  // llvm_unreachable("should not be any stubs here with no return value");
1040  // else
1041  EmitInstrReg(*STI, Mips::JR, Mips::S2);
1042 
1044  OutStreamer->EmitLabel(Tmp);
1047  const MCExpr *T_min_E = MCBinaryExpr::createSub(T, E, OutContext);
1048  OutStreamer->emitELFSize(Stub, T_min_E);
1049  TS.emitDirectiveEnd(x);
1050  OutStreamer->PopSection();
1051 }
1052 
1054  // Emit needed stubs
1055  //
1056  for (std::map<
1057  const char *,
1058  const Mips16HardFloatInfo::FuncSignature *>::const_iterator
1059  it = StubsNeeded.begin();
1060  it != StubsNeeded.end(); ++it) {
1061  const char *Symbol = it->first;
1062  const Mips16HardFloatInfo::FuncSignature *Signature = it->second;
1063  EmitFPCallStub(Symbol, Signature);
1064  }
1065  // return to the text section
1067 }
1068 
1069 void MipsAsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind) {
1070  const uint8_t NoopsInSledCount = Subtarget->isGP64bit() ? 15 : 11;
1071  // For mips32 we want to emit the following pattern:
1072  //
1073  // .Lxray_sled_N:
1074  // ALIGN
1075  // B .tmpN
1076  // 11 NOP instructions (44 bytes)
1077  // ADDIU T9, T9, 52
1078  // .tmpN
1079  //
1080  // We need the 44 bytes (11 instructions) because at runtime, we'd
1081  // be patching over the full 48 bytes (12 instructions) with the following
1082  // pattern:
1083  //
1084  // ADDIU SP, SP, -8
1085  // NOP
1086  // SW RA, 4(SP)
1087  // SW T9, 0(SP)
1088  // LUI T9, %hi(__xray_FunctionEntry/Exit)
1089  // ORI T9, T9, %lo(__xray_FunctionEntry/Exit)
1090  // LUI T0, %hi(function_id)
1091  // JALR T9
1092  // ORI T0, T0, %lo(function_id)
1093  // LW T9, 0(SP)
1094  // LW RA, 4(SP)
1095  // ADDIU SP, SP, 8
1096  //
1097  // We add 52 bytes to t9 because we want to adjust the function pointer to
1098  // the actual start of function i.e. the address just after the noop sled.
1099  // We do this because gp displacement relocation is emitted at the start of
1100  // of the function i.e after the nop sled and to correctly calculate the
1101  // global offset table address, t9 must hold the address of the instruction
1102  // containing the gp displacement relocation.
1103  // FIXME: Is this correct for the static relocation model?
1104  //
1105  // For mips64 we want to emit the following pattern:
1106  //
1107  // .Lxray_sled_N:
1108  // ALIGN
1109  // B .tmpN
1110  // 15 NOP instructions (60 bytes)
1111  // .tmpN
1112  //
1113  // We need the 60 bytes (15 instructions) because at runtime, we'd
1114  // be patching over the full 64 bytes (16 instructions) with the following
1115  // pattern:
1116  //
1117  // DADDIU SP, SP, -16
1118  // NOP
1119  // SD RA, 8(SP)
1120  // SD T9, 0(SP)
1121  // LUI T9, %highest(__xray_FunctionEntry/Exit)
1122  // ORI T9, T9, %higher(__xray_FunctionEntry/Exit)
1123  // DSLL T9, T9, 16
1124  // ORI T9, T9, %hi(__xray_FunctionEntry/Exit)
1125  // DSLL T9, T9, 16
1126  // ORI T9, T9, %lo(__xray_FunctionEntry/Exit)
1127  // LUI T0, %hi(function_id)
1128  // JALR T9
1129  // ADDIU T0, T0, %lo(function_id)
1130  // LD T9, 0(SP)
1131  // LD RA, 8(SP)
1132  // DADDIU SP, SP, 16
1133  //
1134  OutStreamer->EmitCodeAlignment(4);
1135  auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1136  OutStreamer->EmitLabel(CurSled);
1138 
1139  // Emit "B .tmpN" instruction, which jumps over the nop sled to the actual
1140  // start of function
1141  const MCExpr *TargetExpr = MCSymbolRefExpr::create(
1142  Target, MCSymbolRefExpr::VariantKind::VK_None, OutContext);
1143  EmitToStreamer(*OutStreamer, MCInstBuilder(Mips::BEQ)
1144  .addReg(Mips::ZERO)
1145  .addReg(Mips::ZERO)
1146  .addExpr(TargetExpr));
1147 
1148  for (int8_t I = 0; I < NoopsInSledCount; I++)
1149  EmitToStreamer(*OutStreamer, MCInstBuilder(Mips::SLL)
1150  .addReg(Mips::ZERO)
1151  .addReg(Mips::ZERO)
1152  .addImm(0));
1153 
1154  OutStreamer->EmitLabel(Target);
1155 
1156  if (!Subtarget->isGP64bit()) {
1157  EmitToStreamer(*OutStreamer,
1158  MCInstBuilder(Mips::ADDiu)
1159  .addReg(Mips::T9)
1160  .addReg(Mips::T9)
1161  .addImm(0x34));
1162  }
1163 
1164  recordSled(CurSled, MI, Kind);
1165 }
1166 
1168  EmitSled(MI, SledKind::FUNCTION_ENTER);
1169 }
1170 
1172  EmitSled(MI, SledKind::FUNCTION_EXIT);
1173 }
1174 
1176  EmitSled(MI, SledKind::TAIL_CALL);
1177 }
1178 
1180  raw_ostream &OS) {
1181  // TODO: implement
1182 }
1183 
1184 // Emit .dtprelword or .dtpreldword directive
1185 // and value for debug thread local expression.
1187  unsigned Size) const {
1188  switch (Size) {
1189  case 4:
1190  OutStreamer->EmitDTPRel32Value(Value);
1191  break;
1192  case 8:
1193  OutStreamer->EmitDTPRel64Value(Value);
1194  break;
1195  default:
1196  llvm_unreachable("Unexpected size of expression value.");
1197  }
1198 }
1199 
1200 // Align all targets of indirect branches on bundle size. Used only if target
1201 // is NaCl.
1202 void MipsAsmPrinter::NaClAlignIndirectJumpTargets(MachineFunction &MF) {
1203  // Align all blocks that are jumped to through jump table.
1204  if (MachineJumpTableInfo *JtInfo = MF.getJumpTableInfo()) {
1205  const std::vector<MachineJumpTableEntry> &JT = JtInfo->getJumpTables();
1206  for (unsigned I = 0; I < JT.size(); ++I) {
1207  const std::vector<MachineBasicBlock*> &MBBs = JT[I].MBBs;
1208 
1209  for (unsigned J = 0; J < MBBs.size(); ++J)
1210  MBBs[J]->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
1211  }
1212  }
1213 
1214  // If basic block address is taken, block can be target of indirect branch.
1215  for (auto &MBB : MF) {
1216  if (MBB.hasAddressTaken())
1217  MBB.setAlignment(MIPS_NACL_BUNDLE_ALIGN);
1218  }
1219 }
1220 
1221 bool MipsAsmPrinter::isLongBranchPseudo(int Opcode) const {
1222  return (Opcode == Mips::LONG_BRANCH_LUi
1223  || Opcode == Mips::LONG_BRANCH_ADDiu
1224  || Opcode == Mips::LONG_BRANCH_DADDiu);
1225 }
1226 
1227 // Force static initialization.
1228 extern "C" void LLVMInitializeMipsAsmPrinter() {
1233 }
unsigned getTargetFlags() const
MachineConstantPoolValue * MachineCPVal
virtual void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff)
bool isABICalls() const
StringRef getTargetFeatureString() const
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
instr_iterator instr_end()
MachineBasicBlock * getMBB() const
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:92
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:305
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
StringRef getPrivateGlobalPrefix() const
Definition: DataLayout.h:281
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
bool inMips16Mode() const
virtual void AddBlankLine()
AddBlankLine - Emit a blank line to a .s file to pretty it up.
Definition: MCStreamer.h:303
MO_HIGHER/HIGHEST - Represents the highest or higher half word of a 64-bit symbol address...
Definition: MipsBaseInfo.h:85
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:87
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:137
void EmitFunctionBodyEnd() override
EmitFunctionBodyEnd - Targets can override this to emit stuff after the last basic block in the funct...
MO_TLSGD - Represents the offset into the global offset table at which.
Definition: MipsBaseInfo.h:58
unsigned getReg() const
getReg - Returns the register number.
const MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:95
Target & getTheMipselTarget()
virtual void EmitDTPRel64Value(const MCExpr *Value)
Emit the expression Value into the output as a dtprel (64-bit DTP relative) value.
Definition: MCStreamer.cpp:138
virtual void emitDirectiveSetNoReorder()
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:262
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:489
bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const override
isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the...
void PushSection()
Save the current and previous section on the section stack.
Definition: MCStreamer.h:338
MachineBasicBlock reference.
void Initialize(MCContext *C)
std::vector< MachineBasicBlock * >::const_iterator const_pred_iterator
void EmitFunctionBodyStart() override
EmitFunctionBodyStart - Targets can override this to emit stuff before the first basic block in the f...
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
union llvm::MachineConstantPoolEntry::@140 Val
The constant itself.
void EmitFunctionEntryLabel() override
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, bool PrintSchedInfo=false)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:863
return AArch64::GPR64RegClass contains(Reg)
SI optimize exec mask operations pre RA
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
virtual void emitDirectiveSetMicroMips()
void recordSled(MCSymbol *Sled, const MachineInstr &MI, SledKind Kind, uint8_t Version=0)
bool isMachineConstantPoolEntry() const
isMachineConstantPoolEntry - Return true if the MachineConstantPoolEntry is indeed a target specific ...
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:116
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
virtual void emitFrame(unsigned StackReg, unsigned StackSize, unsigned ReturnReg)
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:293
bool inMicroMipsMode() const
void LLVMInitializeMipsAsmPrinter()
virtual void emitDirectiveSetNoMacro()
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
virtual void emitDirectiveEnd(StringRef Name)
bool isGP64bit() const
Reg
All possible values of the reg field in the ModR/M byte.
This file contains the simple types necessary to represent the attributes associated with functions a...
unsigned getAlignment() const
getAlignment - Return the alignment (log2, not bytes) of the function.
bool hasMips32r6() const
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:165
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
virtual unsigned getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
void EmitAlignment(unsigned NumBits, const GlobalObject *GO=nullptr) const
Emit an alignment directive to the specified power of two boundary.
MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol address.
Definition: MipsBaseInfo.h:52
const MipsABIInfo & getABI() const
void emitXRayTable()
Emit a table with all XRay instrumentation points.
virtual void emitDirectiveModuleOddSPReg()
virtual void AddComment(const Twine &T, bool EOL=true)
Add a textual comment.
Definition: MCStreamer.h:282
bool runOnMachineFunction(MachineFunction &MF) override
Emit the specified function out to the OutStreamer.
Definition: AsmPrinter.h:277
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:528
bool isPositionIndependent() const
Definition: AsmPrinter.cpp:196
virtual void EmitBasicBlockEnd(const MachineBasicBlock &MBB)
Targets can override this to emit stuff at the end of a basic block.
Target & getTheMips64Target()
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant...
void printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O)
bool isLittleEndian() const
Layout endianness...
Definition: DataLayout.h:216
RegisterAsmPrinter - Helper template for registering a target specific assembly printer, for use in the target machine initialization function.
This class is a data container for one entry in a MachineConstantPool.
StringRef getTargetCPU() const
void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS)
void EmitEndOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the end of their file...
const std::string & str() const
Definition: Triple.h:354
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:159
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
bool isTargetNaCl() const
MO_GPREL - Represents the offset from the current gp value to be used for the relocatable object file...
Definition: MipsBaseInfo.h:48
MCContext & getContext() const
Address of a global value.
Streaming machine code generation interface.
Definition: MCStreamer.h:169
MO_GOT_CALL - Represents the offset into the global offset table at which the address of a call site ...
Definition: MipsBaseInfo.h:44
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
Definition: MCContext.cpp:215
Target & getTheMips64elTarget()
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
MCSymbol * CurrentFnSym
The symbol for the current function.
Definition: AsmPrinter.h:105
LLVM Basic Block Representation.
Definition: BasicBlock.h:59
const MCAsmInfo * MAI
Target Asm Printer information.
Definition: AsmPrinter.h:83
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
virtual void emitDirectiveSetNoMicroMips()
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
virtual void emitDirectiveSetMips16()
virtual void SwitchSection(MCSection *Section, const MCExpr *Subsection=nullptr)
Set the current section where code is being emitted to Section.
Definition: MCStreamer.cpp:937
const GlobalValue * getGlobal() const
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant...
void EmitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:31
virtual void emitDirectiveSetMacro()
TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:80
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:336
void Lower(const MachineInstr *MI, MCInst &OutMI) const
virtual void EmitValueToAlignment(unsigned ByteAlignment, int64_t Value=0, unsigned ValueSize=1, unsigned MaxBytesToEmit=0)
Emit some number of copies of Value until the byte alignment ByteAlignment is reached.
Definition: MCStreamer.cpp:925
virtual bool EmitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute)=0
Add the given Attribute to Symbol.
Address of a basic block.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MCObjectFileInfo * getObjectFileInfo() const
Definition: MCContext.h:287
const Triple & getTargetTriple() const
StringRef selectMipsCPU(const Triple &TT, StringRef CPU)
Select the Mips CPU for the given triple and cpu name.
bool IsO32() const
Definition: MipsABIInfo.h:42
self_iterator getIterator()
Definition: ilist_node.h:82
virtual void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff)
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
bool runOnMachineFunction(MachineFunction &MF) override
Emit the specified function out to the OutStreamer.
const Target & getTarget() const
MipsMCInstLower MCInstLowering
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual MCSymbol * GetCPISymbol(unsigned CPID) const
Return the symbol for the specified constant pool entry.
bool hasMips64r6() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MO_GOTTPREL - Represents the offset from the thread pointer (Initial.
Definition: MipsBaseInfo.h:69
virtual void EmitDataRegion(MCDataRegionType Kind)
Note in the output the specified region Kind.
Definition: MCStreamer.h:422
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
const std::vector< MachineConstantPoolEntry > & getConstants() const
unsigned getFunctionNumber() const
Return a unique ID for the current function.
Definition: AsmPrinter.cpp:201
virtual void emitDirectiveAbiCalls()
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
Definition: MipsBaseInfo.h:38
Iterator for intrusive lists based on ilist_node.
void setOpcode(unsigned Op)
Definition: MCInst.h:171
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
bool isLittle() const
virtual void emitDirectiveOptionPic0()
MCSymbol * getSymbol(const GlobalValue *GV) const
Definition: AsmPrinter.cpp:433
bool isDebugValue() const
Definition: MachineInstr.h:816
MachineOperand class - Representation of each machine instruction operand.
virtual void EmitCodeAlignment(unsigned ByteAlignment, unsigned MaxBytesToEmit=0)
Emit nops until the byte alignment ByteAlignment is reached.
Definition: MCStreamer.cpp:928
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
Definition: AsmPrinter.cpp:222
static Twine utohexstr(const uint64_t &Val)
Definition: Twine.h:385
virtual void emitDirectiveSetNoMips16()
int64_t getImm() const
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O, const char *Modifier=nullptr)
void EmitStartOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the start of their fi...
const char * MipsFCCToString(Mips::CondCode CC)
Target - Wrapper for Target specific information.
Target & getTheMipsTarget()
MCSubtargetInfo * createMCSubtargetInfo(StringRef TheTriple, StringRef CPU, StringRef Features) const
createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
MO_TPREL_HI/LO - Represents the hi and low part of the offset from.
Definition: MipsBaseInfo.h:73
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
static const unsigned MIPS_NACL_BUNDLE_ALIGN
Definition: MipsMCNaCl.h:18
virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV)
const char * getCurrentABIString() const
Emit Set directives.
virtual void setPic(bool Value)
void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O)
Representation of each machine instruction.
Definition: MachineInstr.h:59
void updateABIInfo(const PredicateLibrary &P)
virtual void emitDirectiveEnt(const MCSymbol &Symbol)
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
const MipsSubtarget * Subtarget
.type _foo,
Definition: MCDirectives.h:30
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:121
bool isEHPad() const
Returns true if the block is a landing pad.
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
void EmitDebugThreadLocal(const MCExpr *Value, unsigned Size) const override
Emit the directive and value for debug thread local expression.
.type _foo, STT_FUNC # aka
Definition: MCDirectives.h:23
int64_t getOffset() const
Return the offset from the symbol in this operand.
const BlockAddress * getBlockAddress() const
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
#define I(x, y, z)
Definition: MD5.cpp:58
virtual void EmitDTPRel32Value(const MCExpr *Value)
Emit the expression Value into the output as a dtprel (32-bit DTP relative) value.
Definition: MCStreamer.cpp:142
MCSubtargetInfo - Generic base class for all target subtargets.
void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O)
virtual void emitELFSize(MCSymbol *Symbol, const MCExpr *Value)
Emit an ELF .size directive.
Definition: MCStreamer.cpp:906
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI)
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:123
This represents a section on linux, lots of unix variants and some bare metal systems.
Definition: MCSectionELF.h:28
MCOperand LowerOperand(const MachineOperand &MO, unsigned offset=0) const
unsigned getRARegister() const
This method should return the register where the return address can be found.
void printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:203
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
LLVM_NODISCARD std::string lower() const
Definition: StringRef.cpp:123
MCSection * getTextSection() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool PopSection()
Restore the current and previous section from the section stack.
Definition: MCStreamer.h:347
MCSectionELF * getELFSection(const Twine &Section, unsigned Type, unsigned Flags)
Definition: MCContext.h:379
virtual void emitDirectiveSetReorder()
static const char * getRegisterName(unsigned RegNo)
void EmitGlobalConstant(const DataLayout &DL, const Constant *CV)
Print a general LLVM constant to the .s file.
LLVM Value Representation.
Definition: Value.h:73
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
virtual void emitDirectiveNaNLegacy()
virtual void EmitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:300
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
const DataLayout & getDataLayout() const
Return information about data layout.
Definition: AsmPrinter.cpp:209
const MipsFunctionInfo * MipsFI
IRTranslator LLVM IR MI
void emitFrameDirective()
Frame Directive.
void addOperand(const MCOperand &Op)
Definition: MCInst.h:184
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
bool isValid() const
Definition: MCInst.h:57
void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI)
Address of indexed Constant in Constant Pool.
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...
bool isPositionIndependent() const
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
void EmitBasicBlockEnd(const MachineBasicBlock &MBB) override
Targets can override this to emit stuff at the end of a basic block.
void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
const MachineJumpTableInfo * getJumpTableInfo() const
getJumpTableInfo - Return the jump table info object for the current function.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
.end_data_region
Definition: MCDirectives.h:61
void print(raw_ostream &OS, const MCAsmInfo *MAI) const
print - Print the value to the stream OS.
Definition: MCSymbol.cpp:59