LLVM  6.0.0svn
MipsAsmPrinter.cpp
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1 //===-- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer -------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "MipsAsmPrinter.h"
19 #include "Mips.h"
20 #include "MipsInstrInfo.h"
21 #include "MipsMCInstLower.h"
22 #include "MipsTargetMachine.h"
23 #include "MipsTargetStreamer.h"
24 #include "llvm/ADT/SmallString.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/BinaryFormat/ELF.h"
33 #include "llvm/IR/BasicBlock.h"
34 #include "llvm/IR/DataLayout.h"
35 #include "llvm/IR/InlineAsm.h"
36 #include "llvm/IR/Instructions.h"
37 #include "llvm/IR/Mangler.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCELFStreamer.h"
41 #include "llvm/MC/MCExpr.h"
42 #include "llvm/MC/MCInst.h"
43 #include "llvm/MC/MCInstBuilder.h"
44 #include "llvm/MC/MCSection.h"
45 #include "llvm/MC/MCSectionELF.h"
46 #include "llvm/MC/MCSymbolELF.h"
51 #include <string>
52 
53 using namespace llvm;
54 
55 #define DEBUG_TYPE "mips-asm-printer"
56 
57 MipsTargetStreamer &MipsAsmPrinter::getTargetStreamer() const {
58  return static_cast<MipsTargetStreamer &>(*OutStreamer->getTargetStreamer());
59 }
60 
63 
65  if (Subtarget->inMips16Mode())
66  for (std::map<
67  const char *,
68  const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
69  it = MipsFI->StubsNeeded.begin();
70  it != MipsFI->StubsNeeded.end(); ++it) {
71  const char *Symbol = it->first;
72  const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
73  if (StubsNeeded.find(Symbol) == StubsNeeded.end())
74  StubsNeeded[Symbol] = Signature;
75  }
76  MCP = MF.getConstantPool();
77 
78  // In NaCl, all indirect jump targets must be aligned to bundle size.
79  if (Subtarget->isTargetNaCl())
80  NaClAlignIndirectJumpTargets(MF);
81 
83 
84  emitXRayTable();
85 
86  return true;
87 }
88 
89 bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {
90  MCOp = MCInstLowering.LowerOperand(MO);
91  return MCOp.isValid();
92 }
93 
94 #include "MipsGenMCPseudoLowering.inc"
95 
96 // Lower PseudoReturn/PseudoIndirectBranch/PseudoIndirectBranch64 to JR, JR_MM,
97 // JALR, or JALR64 as appropriate for the target
98 void MipsAsmPrinter::emitPseudoIndirectBranch(MCStreamer &OutStreamer,
99  const MachineInstr *MI) {
100  bool HasLinkReg = false;
101  bool InMicroMipsMode = Subtarget->inMicroMipsMode();
102  MCInst TmpInst0;
103 
104  if (Subtarget->hasMips64r6()) {
105  // MIPS64r6 should use (JALR64 ZERO_64, $rs)
106  TmpInst0.setOpcode(Mips::JALR64);
107  HasLinkReg = true;
108  } else if (Subtarget->hasMips32r6()) {
109  // MIPS32r6 should use (JALR ZERO, $rs)
110  if (InMicroMipsMode)
111  TmpInst0.setOpcode(Mips::JRC16_MMR6);
112  else {
113  TmpInst0.setOpcode(Mips::JALR);
114  HasLinkReg = true;
115  }
116  } else if (Subtarget->inMicroMipsMode())
117  // microMIPS should use (JR_MM $rs)
118  TmpInst0.setOpcode(Mips::JR_MM);
119  else {
120  // Everything else should use (JR $rs)
121  TmpInst0.setOpcode(Mips::JR);
122  }
123 
124  MCOperand MCOp;
125 
126  if (HasLinkReg) {
127  unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
128  TmpInst0.addOperand(MCOperand::createReg(ZeroReg));
129  }
130 
131  lowerOperand(MI->getOperand(0), MCOp);
132  TmpInst0.addOperand(MCOp);
133 
134  EmitToStreamer(OutStreamer, TmpInst0);
135 }
136 
138  MipsTargetStreamer &TS = getTargetStreamer();
139  unsigned Opc = MI->getOpcode();
141 
142  if (MI->isDebugValue()) {
143  SmallString<128> Str;
144  raw_svector_ostream OS(Str);
145 
146  PrintDebugValueComment(MI, OS);
147  return;
148  }
149 
150  // If we just ended a constant pool, mark it as such.
151  if (InConstantPool && Opc != Mips::CONSTPOOL_ENTRY) {
152  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
153  InConstantPool = false;
154  }
155  if (Opc == Mips::CONSTPOOL_ENTRY) {
156  // CONSTPOOL_ENTRY - This instruction represents a floating
157  // constant pool in the function. The first operand is the ID#
158  // for this instruction, the second is the index into the
159  // MachineConstantPool that this is, the third is the size in
160  // bytes of this constant pool entry.
161  // The required alignment is specified on the basic block holding this MI.
162  //
163  unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
164  unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
165 
166  // If this is the first entry of the pool, mark it.
167  if (!InConstantPool) {
168  OutStreamer->EmitDataRegion(MCDR_DataRegion);
169  InConstantPool = true;
170  }
171 
172  OutStreamer->EmitLabel(GetCPISymbol(LabelId));
173 
174  const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
175  if (MCPE.isMachineConstantPoolEntry())
177  else
179  return;
180  }
181 
182  switch (Opc) {
183  case Mips::PATCHABLE_FUNCTION_ENTER:
185  return;
186  case Mips::PATCHABLE_FUNCTION_EXIT:
188  return;
189  case Mips::PATCHABLE_TAIL_CALL:
191  return;
192  }
193 
196 
197  do {
198  // Do any auto-generated pseudo lowerings.
199  if (emitPseudoExpansionLowering(*OutStreamer, &*I))
200  continue;
201 
202  if (I->getOpcode() == Mips::PseudoReturn ||
203  I->getOpcode() == Mips::PseudoReturn64 ||
204  I->getOpcode() == Mips::PseudoIndirectBranch ||
205  I->getOpcode() == Mips::PseudoIndirectBranch64 ||
206  I->getOpcode() == Mips::TAILCALLREG ||
207  I->getOpcode() == Mips::TAILCALLREG64) {
208  emitPseudoIndirectBranch(*OutStreamer, &*I);
209  continue;
210  }
211 
212  // The inMips16Mode() test is not permanent.
213  // Some instructions are marked as pseudo right now which
214  // would make the test fail for the wrong reason but
215  // that will be fixed soon. We need this here because we are
216  // removing another test for this situation downstream in the
217  // callchain.
218  //
219  if (I->isPseudo() && !Subtarget->inMips16Mode()
220  && !isLongBranchPseudo(I->getOpcode()))
221  llvm_unreachable("Pseudo opcode found in EmitInstruction()");
222 
223  MCInst TmpInst0;
224  MCInstLowering.Lower(&*I, TmpInst0);
225  EmitToStreamer(*OutStreamer, TmpInst0);
226  } while ((++I != E) && I->isInsideBundle()); // Delay slot check
227 }
228 
229 //===----------------------------------------------------------------------===//
230 //
231 // Mips Asm Directives
232 //
233 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
234 // Describe the stack frame.
235 //
236 // -- Mask directives "(f)mask bitmask, offset"
237 // Tells the assembler which registers are saved and where.
238 // bitmask - contain a little endian bitset indicating which registers are
239 // saved on function prologue (e.g. with a 0x80000000 mask, the
240 // assembler knows the register 31 (RA) is saved at prologue.
241 // offset - the position before stack pointer subtraction indicating where
242 // the first saved register on prologue is located. (e.g. with a
243 //
244 // Consider the following function prologue:
245 //
246 // .frame $fp,48,$ra
247 // .mask 0xc0000000,-8
248 // addiu $sp, $sp, -48
249 // sw $ra, 40($sp)
250 // sw $fp, 36($sp)
251 //
252 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
253 // 30 (FP) are saved at prologue. As the save order on prologue is from
254 // left to right, RA is saved first. A -8 offset means that after the
255 // stack pointer subtration, the first register in the mask (RA) will be
256 // saved at address 48-8=40.
257 //
258 //===----------------------------------------------------------------------===//
259 
260 //===----------------------------------------------------------------------===//
261 // Mask directives
262 //===----------------------------------------------------------------------===//
263 
264 // Create a bitmask with all callee saved registers for CPU or Floating Point
265 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
267  // CPU and FPU Saved Registers Bitmasks
268  unsigned CPUBitmask = 0, FPUBitmask = 0;
269  int CPUTopSavedRegOff, FPUTopSavedRegOff;
270 
271  // Set the CPU and FPU Bitmasks
272  const MachineFrameInfo &MFI = MF->getFrameInfo();
274  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
275  // size of stack area to which FP callee-saved regs are saved.
276  unsigned CPURegSize = TRI->getRegSizeInBits(Mips::GPR32RegClass) / 8;
277  unsigned FGR32RegSize = TRI->getRegSizeInBits(Mips::FGR32RegClass) / 8;
278  unsigned AFGR64RegSize = TRI->getRegSizeInBits(Mips::AFGR64RegClass) / 8;
279  bool HasAFGR64Reg = false;
280  unsigned CSFPRegsSize = 0;
281 
282  for (const auto &I : CSI) {
283  unsigned Reg = I.getReg();
284  unsigned RegNum = TRI->getEncodingValue(Reg);
285 
286  // If it's a floating point register, set the FPU Bitmask.
287  // If it's a general purpose register, set the CPU Bitmask.
288  if (Mips::FGR32RegClass.contains(Reg)) {
289  FPUBitmask |= (1 << RegNum);
290  CSFPRegsSize += FGR32RegSize;
291  } else if (Mips::AFGR64RegClass.contains(Reg)) {
292  FPUBitmask |= (3 << RegNum);
293  CSFPRegsSize += AFGR64RegSize;
294  HasAFGR64Reg = true;
295  } else if (Mips::GPR32RegClass.contains(Reg))
296  CPUBitmask |= (1 << RegNum);
297  }
298 
299  // FP Regs are saved right below where the virtual frame pointer points to.
300  FPUTopSavedRegOff = FPUBitmask ?
301  (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
302 
303  // CPU Regs are saved below FP Regs.
304  CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
305 
306  MipsTargetStreamer &TS = getTargetStreamer();
307  // Print CPUBitmask
308  TS.emitMask(CPUBitmask, CPUTopSavedRegOff);
309 
310  // Print FPUBitmask
311  TS.emitFMask(FPUBitmask, FPUTopSavedRegOff);
312 }
313 
314 //===----------------------------------------------------------------------===//
315 // Frame and Set directives
316 //===----------------------------------------------------------------------===//
317 
318 /// Frame Directive
321 
322  unsigned stackReg = RI.getFrameRegister(*MF);
323  unsigned returnReg = RI.getRARegister();
324  unsigned stackSize = MF->getFrameInfo().getStackSize();
325 
326  getTargetStreamer().emitFrame(stackReg, stackSize, returnReg);
327 }
328 
329 /// Emit Set directives.
331  switch (static_cast<MipsTargetMachine &>(TM).getABI().GetEnumValue()) {
332  case MipsABIInfo::ABI::O32: return "abi32";
333  case MipsABIInfo::ABI::N32: return "abiN32";
334  case MipsABIInfo::ABI::N64: return "abi64";
335  default: llvm_unreachable("Unknown Mips ABI");
336  }
337 }
338 
340  MipsTargetStreamer &TS = getTargetStreamer();
341 
342  // NaCl sandboxing requires that indirect call instructions are masked.
343  // This means that function entry points should be bundle-aligned.
344  if (Subtarget->isTargetNaCl())
346 
347  if (Subtarget->inMicroMipsMode()) {
349  TS.setUsesMicroMips();
350  } else
352 
353  if (Subtarget->inMips16Mode())
355  else
357 
359  OutStreamer->EmitLabel(CurrentFnSym);
360 }
361 
362 /// EmitFunctionBodyStart - Targets can override this to emit stuff before
363 /// the first basic block in the function.
365  MipsTargetStreamer &TS = getTargetStreamer();
366 
368 
369  bool IsNakedFunction = MF->getFunction()->hasFnAttribute(Attribute::Naked);
370  if (!IsNakedFunction)
372 
373  if (!IsNakedFunction)
375 
376  if (!Subtarget->inMips16Mode()) {
380  }
381 }
382 
383 /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
384 /// the last basic block in the function.
386  MipsTargetStreamer &TS = getTargetStreamer();
387 
388  // There are instruction for this macros, but they must
389  // always be at the function end, and we can't emit and
390  // break with BB logic.
391  if (!Subtarget->inMips16Mode()) {
392  TS.emitDirectiveSetAt();
395  }
397  // Make sure to terminate any constant pools that were at the end
398  // of the function.
399  if (!InConstantPool)
400  return;
401  InConstantPool = false;
402  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
403 }
404 
406  MipsTargetStreamer &TS = getTargetStreamer();
407  if (MBB.size() == 0)
408  TS.emitDirectiveInsn();
409 }
410 
411 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
412 /// exactly one predecessor and the control transfer mechanism between
413 /// the predecessor and this block is a fall-through.
415  MBB) const {
416  // The predecessor has to be immediately before this block.
417  const MachineBasicBlock *Pred = *MBB->pred_begin();
418 
419  // If the predecessor is a switch statement, assume a jump table
420  // implementation, so it is not a fall through.
421  if (const BasicBlock *bb = Pred->getBasicBlock())
422  if (isa<SwitchInst>(bb->getTerminator()))
423  return false;
424 
425  // If this is a landing pad, it isn't a fall through. If it has no preds,
426  // then nothing falls through to it.
427  if (MBB->isEHPad() || MBB->pred_empty())
428  return false;
429 
430  // If there isn't exactly one predecessor, it can't be a fall through.
432  ++PI2;
433 
434  if (PI2 != MBB->pred_end())
435  return false;
436 
437  // The predecessor has to be immediately before this block.
438  if (!Pred->isLayoutSuccessor(MBB))
439  return false;
440 
441  // If the block is completely empty, then it definitely does fall through.
442  if (Pred->empty())
443  return true;
444 
445  // Otherwise, check the last instruction.
446  // Check if the last terminator is an unconditional branch.
448  while (I != Pred->begin() && !(--I)->isTerminator()) ;
449 
450  return !I->isBarrier();
451 }
452 
453 // Print out an operand for an inline asm expression.
454 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
455  unsigned AsmVariant, const char *ExtraCode,
456  raw_ostream &O) {
457  // Does this asm operand have a single letter operand modifier?
458  if (ExtraCode && ExtraCode[0]) {
459  if (ExtraCode[1] != 0) return true; // Unknown modifier.
460 
461  const MachineOperand &MO = MI->getOperand(OpNum);
462  switch (ExtraCode[0]) {
463  default:
464  // See if this is a generic print operand
465  return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O);
466  case 'X': // hex const int
468  return true;
469  O << "0x" << Twine::utohexstr(MO.getImm());
470  return false;
471  case 'x': // hex const int (low 16 bits)
473  return true;
474  O << "0x" << Twine::utohexstr(MO.getImm() & 0xffff);
475  return false;
476  case 'd': // decimal const int
478  return true;
479  O << MO.getImm();
480  return false;
481  case 'm': // decimal const int minus 1
483  return true;
484  O << MO.getImm() - 1;
485  return false;
486  case 'z': {
487  // $0 if zero, regular printing otherwise
488  if (MO.getType() == MachineOperand::MO_Immediate && MO.getImm() == 0) {
489  O << "$0";
490  return false;
491  }
492  // If not, call printOperand as normal.
493  break;
494  }
495  case 'D': // Second part of a double word register operand
496  case 'L': // Low order register of a double word register operand
497  case 'M': // High order register of a double word register operand
498  {
499  if (OpNum == 0)
500  return true;
501  const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
502  if (!FlagsOP.isImm())
503  return true;
504  unsigned Flags = FlagsOP.getImm();
505  unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
506  // Number of registers represented by this operand. We are looking
507  // for 2 for 32 bit mode and 1 for 64 bit mode.
508  if (NumVals != 2) {
509  if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
510  unsigned Reg = MO.getReg();
511  O << '$' << MipsInstPrinter::getRegisterName(Reg);
512  return false;
513  }
514  return true;
515  }
516 
517  unsigned RegOp = OpNum;
518  if (!Subtarget->isGP64bit()){
519  // Endianness reverses which register holds the high or low value
520  // between M and L.
521  switch(ExtraCode[0]) {
522  case 'M':
523  RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
524  break;
525  case 'L':
526  RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
527  break;
528  case 'D': // Always the second part
529  RegOp = OpNum + 1;
530  }
531  if (RegOp >= MI->getNumOperands())
532  return true;
533  const MachineOperand &MO = MI->getOperand(RegOp);
534  if (!MO.isReg())
535  return true;
536  unsigned Reg = MO.getReg();
537  O << '$' << MipsInstPrinter::getRegisterName(Reg);
538  return false;
539  }
540  }
541  case 'w':
542  // Print MSA registers for the 'f' constraint
543  // In LLVM, the 'w' modifier doesn't need to do anything.
544  // We can just call printOperand as normal.
545  break;
546  }
547  }
548 
549  printOperand(MI, OpNum, O);
550  return false;
551 }
552 
554  unsigned OpNum, unsigned AsmVariant,
555  const char *ExtraCode,
556  raw_ostream &O) {
557  assert(OpNum + 1 < MI->getNumOperands() && "Insufficient operands");
558  const MachineOperand &BaseMO = MI->getOperand(OpNum);
559  const MachineOperand &OffsetMO = MI->getOperand(OpNum + 1);
560  assert(BaseMO.isReg() && "Unexpected base pointer for inline asm memory operand.");
561  assert(OffsetMO.isImm() && "Unexpected offset for inline asm memory operand.");
562  int Offset = OffsetMO.getImm();
563 
564  // Currently we are expecting either no ExtraCode or 'D'
565  if (ExtraCode) {
566  if (ExtraCode[0] == 'D')
567  Offset += 4;
568  else
569  return true; // Unknown modifier.
570  // FIXME: M = high order bits
571  // FIXME: L = low order bits
572  }
573 
574  O << Offset << "($" << MipsInstPrinter::getRegisterName(BaseMO.getReg()) << ")";
575 
576  return false;
577 }
578 
579 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
580  raw_ostream &O) {
581  const MachineOperand &MO = MI->getOperand(opNum);
582  bool closeP = false;
583 
584  if (MO.getTargetFlags())
585  closeP = true;
586 
587  switch(MO.getTargetFlags()) {
588  case MipsII::MO_GPREL: O << "%gp_rel("; break;
589  case MipsII::MO_GOT_CALL: O << "%call16("; break;
590  case MipsII::MO_GOT: O << "%got("; break;
591  case MipsII::MO_ABS_HI: O << "%hi("; break;
592  case MipsII::MO_ABS_LO: O << "%lo("; break;
593  case MipsII::MO_HIGHER: O << "%higher("; break;
594  case MipsII::MO_HIGHEST: O << "%highest(("; break;
595  case MipsII::MO_TLSGD: O << "%tlsgd("; break;
596  case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
597  case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
598  case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
599  case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
600  case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
601  case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
602  case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
603  case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
604  }
605 
606  switch (MO.getType()) {
608  O << '$'
610  break;
611 
613  O << MO.getImm();
614  break;
615 
617  MO.getMBB()->getSymbol()->print(O, MAI);
618  return;
619 
621  getSymbol(MO.getGlobal())->print(O, MAI);
622  break;
623 
626  O << BA->getName();
627  break;
628  }
629 
631  O << getDataLayout().getPrivateGlobalPrefix() << "CPI"
632  << getFunctionNumber() << "_" << MO.getIndex();
633  if (MO.getOffset())
634  O << "+" << MO.getOffset();
635  break;
636 
637  default:
638  llvm_unreachable("<unknown operand type>");
639  }
640 
641  if (closeP) O << ")";
642 }
643 
644 void MipsAsmPrinter::
645 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
646  // Load/Store memory operands -- imm($reg)
647  // If PIC target the target is loaded as the
648  // pattern lw $25,%call16($28)
649 
650  // opNum can be invalid if instruction has reglist as operand.
651  // MemOperand is always last operand of instruction (base + offset).
652  switch (MI->getOpcode()) {
653  default:
654  break;
655  case Mips::SWM32_MM:
656  case Mips::LWM32_MM:
657  opNum = MI->getNumOperands() - 2;
658  break;
659  }
660 
661  printOperand(MI, opNum+1, O);
662  O << "(";
663  printOperand(MI, opNum, O);
664  O << ")";
665 }
666 
667 void MipsAsmPrinter::
668 printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
669  // when using stack locations for not load/store instructions
670  // print the same way as all normal 3 operand instructions.
671  printOperand(MI, opNum, O);
672  O << ", ";
673  printOperand(MI, opNum+1, O);
674  return;
675 }
676 
677 void MipsAsmPrinter::
678 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
679  const char *Modifier) {
680  const MachineOperand &MO = MI->getOperand(opNum);
682 }
683 
684 void MipsAsmPrinter::
685 printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O) {
686  for (int i = opNum, e = MI->getNumOperands(); i != e; ++i) {
687  if (i != opNum) O << ", ";
688  printOperand(MI, i, O);
689  }
690 }
691 
693  MipsTargetStreamer &TS = getTargetStreamer();
694 
695  // MipsTargetStreamer has an initialization order problem when emitting an
696  // object file directly (see MipsTargetELFStreamer for full details). Work
697  // around it by re-initializing the PIC state here.
699 
700  // Compute MIPS architecture attributes based on the default subtarget
701  // that we'd have constructed. Module level directives aren't LTO
702  // clean anyhow.
703  // FIXME: For ifunc related functions we could iterate over and look
704  // for a feature string that doesn't match the default one.
705  const Triple &TT = TM.getTargetTriple();
708  const MipsTargetMachine &MTM = static_cast<const MipsTargetMachine &>(TM);
709  const MipsSubtarget STI(TT, CPU, FS, MTM.isLittleEndian(), MTM);
710 
711  bool IsABICalls = STI.isABICalls();
712  const MipsABIInfo &ABI = MTM.getABI();
713  if (IsABICalls) {
715  // FIXME: This condition should be a lot more complicated that it is here.
716  // Ideally it should test for properties of the ABI and not the ABI
717  // itself.
718  // For the moment, I'm only correcting enough to make MIPS-IV work.
719  if (!isPositionIndependent() && STI.hasSym32())
721  }
722 
723  // Tell the assembler which ABI we are using
724  std::string SectionName = std::string(".mdebug.") + getCurrentABIString();
725  OutStreamer->SwitchSection(
726  OutContext.getELFSection(SectionName, ELF::SHT_PROGBITS, 0));
727 
728  // NaN: At the moment we only support:
729  // 1. .nan legacy (default)
730  // 2. .nan 2008
731  STI.isNaN2008() ? TS.emitDirectiveNaN2008()
732  : TS.emitDirectiveNaNLegacy();
733 
734  // TODO: handle O64 ABI
735 
736  TS.updateABIInfo(STI);
737 
738  // We should always emit a '.module fp=...' but binutils 2.24 does not accept
739  // it. We therefore emit it when it contradicts the ABI defaults (-mfpxx or
740  // -mfp64) and omit it otherwise.
741  if (ABI.IsO32() && (STI.isABI_FPXX() || STI.isFP64bit()))
743 
744  // We should always emit a '.module [no]oddspreg' but binutils 2.24 does not
745  // accept it. We therefore emit it when it contradicts the default or an
746  // option has changed the default (i.e. FPXX) and omit it otherwise.
747  if (ABI.IsO32() && (!STI.useOddSPReg() || STI.isABI_FPXX()))
749 }
750 
751 void MipsAsmPrinter::emitInlineAsmStart() const {
752  MipsTargetStreamer &TS = getTargetStreamer();
753 
754  // GCC's choice of assembler options for inline assembly code ('at', 'macro'
755  // and 'reorder') is different from LLVM's choice for generated code ('noat',
756  // 'nomacro' and 'noreorder').
757  // In order to maintain compatibility with inline assembly code which depends
758  // on GCC's assembler options being used, we have to switch to those options
759  // for the duration of the inline assembly block and then switch back.
761  TS.emitDirectiveSetAt();
764  OutStreamer->AddBlankLine();
765 }
766 
767 void MipsAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
768  const MCSubtargetInfo *EndInfo) const {
769  OutStreamer->AddBlankLine();
770  getTargetStreamer().emitDirectiveSetPop();
771 }
772 
773 void MipsAsmPrinter::EmitJal(const MCSubtargetInfo &STI, MCSymbol *Symbol) {
774  MCInst I;
775  I.setOpcode(Mips::JAL);
776  I.addOperand(
778  OutStreamer->EmitInstruction(I, STI);
779 }
780 
781 void MipsAsmPrinter::EmitInstrReg(const MCSubtargetInfo &STI, unsigned Opcode,
782  unsigned Reg) {
783  MCInst I;
784  I.setOpcode(Opcode);
786  OutStreamer->EmitInstruction(I, STI);
787 }
788 
789 void MipsAsmPrinter::EmitInstrRegReg(const MCSubtargetInfo &STI,
790  unsigned Opcode, unsigned Reg1,
791  unsigned Reg2) {
792  MCInst I;
793  //
794  // Because of the current td files for Mips32, the operands for MTC1
795  // appear backwards from their normal assembly order. It's not a trivial
796  // change to fix this in the td file so we adjust for it here.
797  //
798  if (Opcode == Mips::MTC1) {
799  unsigned Temp = Reg1;
800  Reg1 = Reg2;
801  Reg2 = Temp;
802  }
803  I.setOpcode(Opcode);
806  OutStreamer->EmitInstruction(I, STI);
807 }
808 
809 void MipsAsmPrinter::EmitInstrRegRegReg(const MCSubtargetInfo &STI,
810  unsigned Opcode, unsigned Reg1,
811  unsigned Reg2, unsigned Reg3) {
812  MCInst I;
813  I.setOpcode(Opcode);
817  OutStreamer->EmitInstruction(I, STI);
818 }
819 
820 void MipsAsmPrinter::EmitMovFPIntPair(const MCSubtargetInfo &STI,
821  unsigned MovOpc, unsigned Reg1,
822  unsigned Reg2, unsigned FPReg1,
823  unsigned FPReg2, bool LE) {
824  if (!LE) {
825  unsigned temp = Reg1;
826  Reg1 = Reg2;
827  Reg2 = temp;
828  }
829  EmitInstrRegReg(STI, MovOpc, Reg1, FPReg1);
830  EmitInstrRegReg(STI, MovOpc, Reg2, FPReg2);
831 }
832 
833 void MipsAsmPrinter::EmitSwapFPIntParams(const MCSubtargetInfo &STI,
835  bool LE, bool ToFP) {
836  using namespace Mips16HardFloatInfo;
837  unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1;
838  switch (PV) {
839  case FSig:
840  EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);
841  break;
842  case FFSig:
843  EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F14, LE);
844  break;
845  case FDSig:
846  EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);
847  EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
848  break;
849  case DSig:
850  EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
851  break;
852  case DDSig:
853  EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
854  EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
855  break;
856  case DFSig:
857  EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
858  EmitInstrRegReg(STI, MovOpc, Mips::A2, Mips::F14);
859  break;
860  case NoSig:
861  return;
862  }
863 }
864 
865 void MipsAsmPrinter::EmitSwapFPIntRetval(
867  bool LE) {
868  using namespace Mips16HardFloatInfo;
869  unsigned MovOpc = Mips::MFC1;
870  switch (RV) {
871  case FRet:
872  EmitInstrRegReg(STI, MovOpc, Mips::V0, Mips::F0);
873  break;
874  case DRet:
875  EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
876  break;
877  case CFRet:
878  EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
879  break;
880  case CDRet:
881  EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
882  EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F2, Mips::F3, LE);
883  break;
884  case NoFPRet:
885  break;
886  }
887 }
888 
889 void MipsAsmPrinter::EmitFPCallStub(
890  const char *Symbol, const Mips16HardFloatInfo::FuncSignature *Signature) {
891  MCSymbol *MSymbol = OutContext.getOrCreateSymbol(StringRef(Symbol));
892  using namespace Mips16HardFloatInfo;
893  bool LE = getDataLayout().isLittleEndian();
894  // Construct a local MCSubtargetInfo here.
895  // This is because the MachineFunction won't exist (but have not yet been
896  // freed) and since we're at the global level we can use the default
897  // constructed subtarget.
898  std::unique_ptr<MCSubtargetInfo> STI(TM.getTarget().createMCSubtargetInfo(
901 
902  //
903  // .global xxxx
904  //
905  OutStreamer->EmitSymbolAttribute(MSymbol, MCSA_Global);
906  const char *RetType;
907  //
908  // make the comment field identifying the return and parameter
909  // types of the floating point stub
910  // # Stub function to call rettype xxxx (params)
911  //
912  switch (Signature->RetSig) {
913  case FRet:
914  RetType = "float";
915  break;
916  case DRet:
917  RetType = "double";
918  break;
919  case CFRet:
920  RetType = "complex";
921  break;
922  case CDRet:
923  RetType = "double complex";
924  break;
925  case NoFPRet:
926  RetType = "";
927  break;
928  }
929  const char *Parms;
930  switch (Signature->ParamSig) {
931  case FSig:
932  Parms = "float";
933  break;
934  case FFSig:
935  Parms = "float, float";
936  break;
937  case FDSig:
938  Parms = "float, double";
939  break;
940  case DSig:
941  Parms = "double";
942  break;
943  case DDSig:
944  Parms = "double, double";
945  break;
946  case DFSig:
947  Parms = "double, float";
948  break;
949  case NoSig:
950  Parms = "";
951  break;
952  }
953  OutStreamer->AddComment("\t# Stub function to call " + Twine(RetType) + " " +
954  Twine(Symbol) + " (" + Twine(Parms) + ")");
955  //
956  // probably not necessary but we save and restore the current section state
957  //
958  OutStreamer->PushSection();
959  //
960  // .section mips16.call.fpxxxx,"ax",@progbits
961  //
963  ".mips16.call.fp." + std::string(Symbol), ELF::SHT_PROGBITS,
965  OutStreamer->SwitchSection(M, nullptr);
966  //
967  // .align 2
968  //
969  OutStreamer->EmitValueToAlignment(4);
970  MipsTargetStreamer &TS = getTargetStreamer();
971  //
972  // .set nomips16
973  // .set nomicromips
974  //
977  //
978  // .ent __call_stub_fp_xxxx
979  // .type __call_stub_fp_xxxx,@function
980  // __call_stub_fp_xxxx:
981  //
982  std::string x = "__call_stub_fp_" + std::string(Symbol);
983  MCSymbolELF *Stub =
984  cast<MCSymbolELF>(OutContext.getOrCreateSymbol(StringRef(x)));
985  TS.emitDirectiveEnt(*Stub);
986  MCSymbol *MType =
987  OutContext.getOrCreateSymbol("__call_stub_fp_" + Twine(Symbol));
988  OutStreamer->EmitSymbolAttribute(MType, MCSA_ELF_TypeFunction);
989  OutStreamer->EmitLabel(Stub);
990 
991  // Only handle non-pic for now.
993  "should not be here if we are compiling pic");
995  //
996  // We need to add a MipsMCExpr class to MCTargetDesc to fully implement
997  // stubs without raw text but this current patch is for compiler generated
998  // functions and they all return some value.
999  // The calling sequence for non pic is different in that case and we need
1000  // to implement %lo and %hi in order to handle the case of no return value
1001  // See the corresponding method in Mips16HardFloat for details.
1002  //
1003  // mov the return address to S2.
1004  // we have no stack space to store it and we are about to make another call.
1005  // We need to make sure that the enclosing function knows to save S2
1006  // This should have already been handled.
1007  //
1008  // Mov $18, $31
1009 
1010  EmitInstrRegRegReg(*STI, Mips::OR, Mips::S2, Mips::RA, Mips::ZERO);
1011 
1012  EmitSwapFPIntParams(*STI, Signature->ParamSig, LE, true);
1013 
1014  // Jal xxxx
1015  //
1016  EmitJal(*STI, MSymbol);
1017 
1018  // fix return values
1019  EmitSwapFPIntRetval(*STI, Signature->RetSig, LE);
1020  //
1021  // do the return
1022  // if (Signature->RetSig == NoFPRet)
1023  // llvm_unreachable("should not be any stubs here with no return value");
1024  // else
1025  EmitInstrReg(*STI, Mips::JR, Mips::S2);
1026 
1028  OutStreamer->EmitLabel(Tmp);
1031  const MCExpr *T_min_E = MCBinaryExpr::createSub(T, E, OutContext);
1032  OutStreamer->emitELFSize(Stub, T_min_E);
1033  TS.emitDirectiveEnd(x);
1034  OutStreamer->PopSection();
1035 }
1036 
1038  // Emit needed stubs
1039  //
1040  for (std::map<
1041  const char *,
1042  const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
1043  it = StubsNeeded.begin();
1044  it != StubsNeeded.end(); ++it) {
1045  const char *Symbol = it->first;
1046  const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
1047  EmitFPCallStub(Symbol, Signature);
1048  }
1049  // return to the text section
1051 }
1052 
1053 void MipsAsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind) {
1054  const uint8_t NoopsInSledCount = Subtarget->isGP64bit() ? 15 : 11;
1055  // For mips32 we want to emit the following pattern:
1056  //
1057  // .Lxray_sled_N:
1058  // ALIGN
1059  // B .tmpN
1060  // 11 NOP instructions (44 bytes)
1061  // ADDIU T9, T9, 52
1062  // .tmpN
1063  //
1064  // We need the 44 bytes (11 instructions) because at runtime, we'd
1065  // be patching over the full 48 bytes (12 instructions) with the following
1066  // pattern:
1067  //
1068  // ADDIU SP, SP, -8
1069  // NOP
1070  // SW RA, 4(SP)
1071  // SW T9, 0(SP)
1072  // LUI T9, %hi(__xray_FunctionEntry/Exit)
1073  // ORI T9, T9, %lo(__xray_FunctionEntry/Exit)
1074  // LUI T0, %hi(function_id)
1075  // JALR T9
1076  // ORI T0, T0, %lo(function_id)
1077  // LW T9, 0(SP)
1078  // LW RA, 4(SP)
1079  // ADDIU SP, SP, 8
1080  //
1081  // We add 52 bytes to t9 because we want to adjust the function pointer to
1082  // the actual start of function i.e. the address just after the noop sled.
1083  // We do this because gp displacement relocation is emitted at the start of
1084  // of the function i.e after the nop sled and to correctly calculate the
1085  // global offset table address, t9 must hold the address of the instruction
1086  // containing the gp displacement relocation.
1087  // FIXME: Is this correct for the static relocation model?
1088  //
1089  // For mips64 we want to emit the following pattern:
1090  //
1091  // .Lxray_sled_N:
1092  // ALIGN
1093  // B .tmpN
1094  // 15 NOP instructions (60 bytes)
1095  // .tmpN
1096  //
1097  // We need the 60 bytes (15 instructions) because at runtime, we'd
1098  // be patching over the full 64 bytes (16 instructions) with the following
1099  // pattern:
1100  //
1101  // DADDIU SP, SP, -16
1102  // NOP
1103  // SD RA, 8(SP)
1104  // SD T9, 0(SP)
1105  // LUI T9, %highest(__xray_FunctionEntry/Exit)
1106  // ORI T9, T9, %higher(__xray_FunctionEntry/Exit)
1107  // DSLL T9, T9, 16
1108  // ORI T9, T9, %hi(__xray_FunctionEntry/Exit)
1109  // DSLL T9, T9, 16
1110  // ORI T9, T9, %lo(__xray_FunctionEntry/Exit)
1111  // LUI T0, %hi(function_id)
1112  // JALR T9
1113  // ADDIU T0, T0, %lo(function_id)
1114  // LD T9, 0(SP)
1115  // LD RA, 8(SP)
1116  // DADDIU SP, SP, 16
1117  //
1118  OutStreamer->EmitCodeAlignment(4);
1119  auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1120  OutStreamer->EmitLabel(CurSled);
1122 
1123  // Emit "B .tmpN" instruction, which jumps over the nop sled to the actual
1124  // start of function
1125  const MCExpr *TargetExpr = MCSymbolRefExpr::create(
1126  Target, MCSymbolRefExpr::VariantKind::VK_None, OutContext);
1127  EmitToStreamer(*OutStreamer, MCInstBuilder(Mips::BEQ)
1128  .addReg(Mips::ZERO)
1129  .addReg(Mips::ZERO)
1130  .addExpr(TargetExpr));
1131 
1132  for (int8_t I = 0; I < NoopsInSledCount; I++)
1133  EmitToStreamer(*OutStreamer, MCInstBuilder(Mips::SLL)
1134  .addReg(Mips::ZERO)
1135  .addReg(Mips::ZERO)
1136  .addImm(0));
1137 
1138  OutStreamer->EmitLabel(Target);
1139 
1140  if (!Subtarget->isGP64bit()) {
1141  EmitToStreamer(*OutStreamer,
1142  MCInstBuilder(Mips::ADDiu)
1143  .addReg(Mips::T9)
1144  .addReg(Mips::T9)
1145  .addImm(0x34));
1146  }
1147 
1148  recordSled(CurSled, MI, Kind);
1149 }
1150 
1152  EmitSled(MI, SledKind::FUNCTION_ENTER);
1153 }
1154 
1156  EmitSled(MI, SledKind::FUNCTION_EXIT);
1157 }
1158 
1160  EmitSled(MI, SledKind::TAIL_CALL);
1161 }
1162 
1164  raw_ostream &OS) {
1165  // TODO: implement
1166 }
1167 
1168 // Emit .dtprelword or .dtpreldword directive
1169 // and value for debug thread local expression.
1171  unsigned Size) const {
1172  switch (Size) {
1173  case 4:
1174  OutStreamer->EmitDTPRel32Value(Value);
1175  break;
1176  case 8:
1177  OutStreamer->EmitDTPRel64Value(Value);
1178  break;
1179  default:
1180  llvm_unreachable("Unexpected size of expression value.");
1181  }
1182 }
1183 
1184 // Align all targets of indirect branches on bundle size. Used only if target
1185 // is NaCl.
1186 void MipsAsmPrinter::NaClAlignIndirectJumpTargets(MachineFunction &MF) {
1187  // Align all blocks that are jumped to through jump table.
1188  if (MachineJumpTableInfo *JtInfo = MF.getJumpTableInfo()) {
1189  const std::vector<MachineJumpTableEntry> &JT = JtInfo->getJumpTables();
1190  for (unsigned I = 0; I < JT.size(); ++I) {
1191  const std::vector<MachineBasicBlock*> &MBBs = JT[I].MBBs;
1192 
1193  for (unsigned J = 0; J < MBBs.size(); ++J)
1194  MBBs[J]->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
1195  }
1196  }
1197 
1198  // If basic block address is taken, block can be target of indirect branch.
1199  for (auto &MBB : MF) {
1200  if (MBB.hasAddressTaken())
1201  MBB.setAlignment(MIPS_NACL_BUNDLE_ALIGN);
1202  }
1203 }
1204 
1205 bool MipsAsmPrinter::isLongBranchPseudo(int Opcode) const {
1206  return (Opcode == Mips::LONG_BRANCH_LUi
1207  || Opcode == Mips::LONG_BRANCH_ADDiu
1208  || Opcode == Mips::LONG_BRANCH_DADDiu);
1209 }
1210 
1211 // Force static initialization.
1212 extern "C" void LLVMInitializeMipsAsmPrinter() {
1217 }
unsigned getTargetFlags() const
MachineConstantPoolValue * MachineCPVal
virtual void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff)
bool isABICalls() const
StringRef getTargetFeatureString() const
union llvm::MachineConstantPoolEntry::@132 Val
The constant itself.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
instr_iterator instr_end()
MachineBasicBlock * getMBB() const
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:93
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:305
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
StringRef getPrivateGlobalPrefix() const
Definition: DataLayout.h:281
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
bool inMips16Mode() const
virtual void AddBlankLine()
AddBlankLine - Emit a blank line to a .s file to pretty it up.
Definition: MCStreamer.h:295
MO_HIGHER/HIGHEST - Represents the highest or higher half word of a 64-bit symbol address...
Definition: MipsBaseInfo.h:85
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:88
virtual void print(raw_ostream &O, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:117
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:137
void EmitFunctionBodyEnd() override
EmitFunctionBodyEnd - Targets can override this to emit stuff after the last basic block in the funct...
MO_TLSGD - Represents the offset into the global offset table at which.
Definition: MipsBaseInfo.h:58
unsigned getReg() const
getReg - Returns the register number.
const MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:96
Target & getTheMipselTarget()
virtual void EmitDTPRel64Value(const MCExpr *Value)
Emit the expression Value into the output as a dtprel (64-bit DTP relative) value.
Definition: MCStreamer.cpp:139
virtual void emitDirectiveSetNoReorder()
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:254
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:490
bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const override
isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the...
void PushSection()
Save the current and previous section on the section stack.
Definition: MCStreamer.h:330
MachineBasicBlock reference.
void Initialize(MCContext *C)
std::vector< MachineBasicBlock * >::const_iterator const_pred_iterator
void EmitFunctionBodyStart() override
EmitFunctionBodyStart - Targets can override this to emit stuff before the first basic block in the f...
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void EmitFunctionEntryLabel() override
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, bool PrintSchedInfo=false)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:780
return AArch64::GPR64RegClass contains(Reg)
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
virtual void emitDirectiveSetMicroMips()
bool isMachineConstantPoolEntry() const
isMachineConstantPoolEntry - Return true if the MachineConstantPoolEntry is indeed a target specific ...
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:116
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
virtual void emitFrame(unsigned StackReg, unsigned StackSize, unsigned ReturnReg)
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:282
bool inMicroMipsMode() const
void LLVMInitializeMipsAsmPrinter()
virtual void emitDirectiveSetNoMacro()
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
virtual void emitDirectiveEnd(StringRef Name)
bool isGP64bit() const
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getAlignment() const
getAlignment - Return the alignment (log2, not bytes) of the function.
bool hasMips32r6() const
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:165
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:279
virtual unsigned getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
void EmitAlignment(unsigned NumBits, const GlobalObject *GO=nullptr) const
Emit an alignment directive to the specified power of two boundary.
MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol address.
Definition: MipsBaseInfo.h:52
const MipsABIInfo & getABI() const
void emitXRayTable()
Emit a table with all XRay instrumentation points.
virtual void emitDirectiveModuleOddSPReg()
virtual void AddComment(const Twine &T, bool EOL=true)
Add a textual comment.
Definition: MCStreamer.h:274
bool runOnMachineFunction(MachineFunction &MF) override
Emit the specified function out to the OutStreamer.
Definition: AsmPrinter.h:275
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:528
bool isPositionIndependent() const
Definition: AsmPrinter.cpp:182
Target & getTheMips64Target()
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant...
void printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O)
bool isLittleEndian() const
Layout endianness...
Definition: DataLayout.h:216
This class is a data container for one entry in a MachineConstantPool.
StringRef getTargetCPU() const
void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS)
void EmitEndOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the end of their file...
const std::string & str() const
Definition: Triple.h:349
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:159
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
bool isTargetNaCl() const
MO_GPREL - Represents the offset from the current gp value to be used for the relocatable object file...
Definition: MipsBaseInfo.h:48
MCContext & getContext() const
Address of a global value.
Streaming machine code generation interface.
Definition: MCStreamer.h:167
MO_GOT_CALL - Represents the offset into the global offset table at which the address of a call site ...
Definition: MipsBaseInfo.h:44
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
Definition: MCContext.cpp:215
Target & getTheMips64elTarget()
MCSymbol * CurrentFnSym
The symbol for the current function.
Definition: AsmPrinter.h:107
LLVM Basic Block Representation.
Definition: BasicBlock.h:59
const MCAsmInfo * MAI
Target Asm Printer information.
Definition: AsmPrinter.h:84
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
virtual void emitDirectiveSetNoMicroMips()
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
virtual void emitDirectiveSetMips16()
virtual void SwitchSection(MCSection *Section, const MCExpr *Subsection=nullptr)
Set the current section where code is being emitted to Section.
Definition: MCStreamer.cpp:854
void recordSled(MCSymbol *Sled, const MachineInstr &MI, SledKind Kind)
const GlobalValue * getGlobal() const
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant...
void EmitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:31
virtual void emitDirectiveSetMacro()
#define A
Definition: LargeTest.cpp:12
TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:80
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:336
void Lower(const MachineInstr *MI, MCInst &OutMI) const
virtual void EmitValueToAlignment(unsigned ByteAlignment, int64_t Value=0, unsigned ValueSize=1, unsigned MaxBytesToEmit=0)
Emit some number of copies of Value until the byte alignment ByteAlignment is reached.
Definition: MCStreamer.cpp:842
virtual bool EmitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute)=0
Add the given Attribute to Symbol.
Address of a basic block.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MCObjectFileInfo * getObjectFileInfo() const
Definition: MCContext.h:287
const Triple & getTargetTriple() const
StringRef selectMipsCPU(const Triple &TT, StringRef CPU)
Select the Mips CPU for the given triple and cpu name.
bool IsO32() const
Definition: MipsABIInfo.h:42
self_iterator getIterator()
Definition: ilist_node.h:82
virtual void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff)
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
bool runOnMachineFunction(MachineFunction &MF) override
Emit the specified function out to the OutStreamer.
const Target & getTarget() const
MipsMCInstLower MCInstLowering
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual MCSymbol * GetCPISymbol(unsigned CPID) const
Return the symbol for the specified constant pool entry.
bool hasMips64r6() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MO_GOTTPREL - Represents the offset from the thread pointer (Initial.
Definition: MipsBaseInfo.h:69
virtual void EmitDataRegion(MCDataRegionType Kind)
Note in the output the specified region Kind.
Definition: MCStreamer.h:414
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
const std::vector< MachineConstantPoolEntry > & getConstants() const
unsigned getFunctionNumber() const
Return a unique ID for the current function.
Definition: AsmPrinter.cpp:188
virtual void emitDirectiveAbiCalls()
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
Definition: MipsBaseInfo.h:38
Iterator for intrusive lists based on ilist_node.
void setOpcode(unsigned Op)
Definition: MCInst.h:167
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
#define E
Definition: LargeTest.cpp:27
#define B
Definition: LargeTest.cpp:24
bool isLittle() const
virtual void emitDirectiveOptionPic0()
MCSymbol * getSymbol(const GlobalValue *GV) const
Definition: AsmPrinter.cpp:420
bool isDebugValue() const
Definition: MachineInstr.h:782
MachineOperand class - Representation of each machine instruction operand.
virtual void EmitCodeAlignment(unsigned ByteAlignment, unsigned MaxBytesToEmit=0)
Emit nops until the byte alignment ByteAlignment is reached.
Definition: MCStreamer.cpp:845
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
Definition: AsmPrinter.cpp:209
static Twine utohexstr(const uint64_t &Val)
Definition: Twine.h:395
virtual void emitDirectiveSetNoMips16()
int64_t getImm() const
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O, const char *Modifier=nullptr)
void EmitStartOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the start of their fi...
const char * MipsFCCToString(Mips::CondCode CC)
Target - Wrapper for Target specific information.
Target & getTheMipsTarget()
MCSubtargetInfo * createMCSubtargetInfo(StringRef TheTriple, StringRef CPU, StringRef Features) const
createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
MO_TPREL_HI/LO - Represents the hi and low part of the offset from.
Definition: MipsBaseInfo.h:73
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
static const unsigned MIPS_NACL_BUNDLE_ALIGN
Definition: MipsMCNaCl.h:18
virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV)
const char * getCurrentABIString() const
Emit Set directives.
virtual void setPic(bool Value)
void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O)
static std::vector< std::string > Flags
Definition: FlagsTest.cpp:8
Representation of each machine instruction.
Definition: MachineInstr.h:59
void updateABIInfo(const PredicateLibrary &P)
virtual void emitDirectiveEnt(const MCSymbol &Symbol)
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
const MipsSubtarget * Subtarget
.type _foo,
Definition: MCDirectives.h:30
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:121
bool isEHPad() const
Returns true if the block is a landing pad.
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
void EmitDebugThreadLocal(const MCExpr *Value, unsigned Size) const override
Emit the directive and value for debug thread local expression.
.type _foo, STT_FUNC # aka
Definition: MCDirectives.h:23
int64_t getOffset() const
Return the offset from the symbol in this operand.
const BlockAddress * getBlockAddress() const
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
#define I(x, y, z)
Definition: MD5.cpp:58
virtual void EmitDTPRel32Value(const MCExpr *Value)
Emit the expression Value into the output as a dtprel (32-bit DTP relative) value.
Definition: MCStreamer.cpp:143
MCSubtargetInfo - Generic base class for all target subtargets.
void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O)
virtual void emitELFSize(MCSymbol *Symbol, const MCExpr *Value)
Emit an ELF .size directive.
Definition: MCStreamer.cpp:823
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI)
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
This represents a section on linux, lots of unix variants and some bare metal systems.
Definition: MCSectionELF.h:28
MCOperand LowerOperand(const MachineOperand &MO, unsigned offset=0) const
unsigned getRARegister() const
This method should return the register where the return address can be found.
void printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:203
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
LLVM_NODISCARD std::string lower() const
Definition: StringRef.cpp:123
MCSection * getTextSection() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool PopSection()
Restore the current and previous section from the section stack.
Definition: MCStreamer.h:339
MCSectionELF * getELFSection(const Twine &Section, unsigned Type, unsigned Flags)
Definition: MCContext.h:379
virtual void emitDirectiveSetReorder()
static const char * getRegisterName(unsigned RegNo)
void EmitGlobalConstant(const DataLayout &DL, const Constant *CV)
Print a general LLVM constant to the .s file.
LLVM Value Representation.
Definition: Value.h:73
RegisterAsmPrinter - Helper template for registering a target specific assembly printer, for use in the target machine initialization function.
virtual void emitDirectiveNaNLegacy()
virtual void EmitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:301
const char SectionName[]
Definition: AMDGPUPTNote.h:24
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
const DataLayout & getDataLayout() const
Return information about data layout.
Definition: AsmPrinter.cpp:196
const MipsFunctionInfo * MipsFI
IRTranslator LLVM IR MI
void emitFrameDirective()
Frame Directive.
void addOperand(const MCOperand &Op)
Definition: MCInst.h:177
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
bool isValid() const
Definition: MCInst.h:57
void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI)
Address of indexed Constant in Constant Pool.
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...
bool isPositionIndependent() const
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
void EmitBasicBlockEnd(const MachineBasicBlock &MBB) override
Targets can override this to emit stuff at the end of a basic block.
void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
const MachineJumpTableInfo * getJumpTableInfo() const
getJumpTableInfo - Return the jump table info object for the current function.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:284
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
.end_data_region
Definition: MCDirectives.h:61
void print(raw_ostream &OS, const MCAsmInfo *MAI) const
print - Print the value to the stream OS.
Definition: MCSymbol.cpp:59