LLVM  7.0.0svn
MipsAsmPrinter.cpp
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1 //===- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer --------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "MipsAsmPrinter.h"
21 #include "Mips.h"
22 #include "MipsMCInstLower.h"
23 #include "MipsMachineFunction.h"
24 #include "MipsSubtarget.h"
25 #include "MipsTargetMachine.h"
26 #include "MipsTargetStreamer.h"
27 #include "llvm/ADT/SmallString.h"
28 #include "llvm/ADT/StringRef.h"
29 #include "llvm/ADT/Triple.h"
30 #include "llvm/ADT/Twine.h"
31 #include "llvm/BinaryFormat/ELF.h"
41 #include "llvm/IR/Attributes.h"
42 #include "llvm/IR/BasicBlock.h"
43 #include "llvm/IR/DataLayout.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/InlineAsm.h"
46 #include "llvm/IR/Instructions.h"
47 #include "llvm/MC/MCContext.h"
48 #include "llvm/MC/MCExpr.h"
49 #include "llvm/MC/MCInst.h"
50 #include "llvm/MC/MCInstBuilder.h"
52 #include "llvm/MC/MCSectionELF.h"
53 #include "llvm/MC/MCSymbol.h"
54 #include "llvm/MC/MCSymbolELF.h"
55 #include "llvm/Support/Casting.h"
60 #include <cassert>
61 #include <cstdint>
62 #include <map>
63 #include <memory>
64 #include <string>
65 #include <vector>
66 
67 using namespace llvm;
68 
69 #define DEBUG_TYPE "mips-asm-printer"
70 
71 MipsTargetStreamer &MipsAsmPrinter::getTargetStreamer() const {
72  return static_cast<MipsTargetStreamer &>(*OutStreamer->getTargetStreamer());
73 }
74 
77 
79  if (Subtarget->inMips16Mode())
80  for (std::map<
81  const char *,
82  const Mips16HardFloatInfo::FuncSignature *>::const_iterator
83  it = MipsFI->StubsNeeded.begin();
84  it != MipsFI->StubsNeeded.end(); ++it) {
85  const char *Symbol = it->first;
86  const Mips16HardFloatInfo::FuncSignature *Signature = it->second;
87  if (StubsNeeded.find(Symbol) == StubsNeeded.end())
88  StubsNeeded[Symbol] = Signature;
89  }
90  MCP = MF.getConstantPool();
91 
92  // In NaCl, all indirect jump targets must be aligned to bundle size.
93  if (Subtarget->isTargetNaCl())
94  NaClAlignIndirectJumpTargets(MF);
95 
97 
98  emitXRayTable();
99 
100  return true;
101 }
102 
103 bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {
104  MCOp = MCInstLowering.LowerOperand(MO);
105  return MCOp.isValid();
106 }
107 
108 #include "MipsGenMCPseudoLowering.inc"
109 
110 // Lower PseudoReturn/PseudoIndirectBranch/PseudoIndirectBranch64 to JR, JR_MM,
111 // JALR, or JALR64 as appropriate for the target.
112 void MipsAsmPrinter::emitPseudoIndirectBranch(MCStreamer &OutStreamer,
113  const MachineInstr *MI) {
114  bool HasLinkReg = false;
115  bool InMicroMipsMode = Subtarget->inMicroMipsMode();
116  MCInst TmpInst0;
117 
118  if (Subtarget->hasMips64r6()) {
119  // MIPS64r6 should use (JALR64 ZERO_64, $rs)
120  TmpInst0.setOpcode(Mips::JALR64);
121  HasLinkReg = true;
122  } else if (Subtarget->hasMips32r6()) {
123  // MIPS32r6 should use (JALR ZERO, $rs)
124  if (InMicroMipsMode)
125  TmpInst0.setOpcode(Mips::JRC16_MMR6);
126  else {
127  TmpInst0.setOpcode(Mips::JALR);
128  HasLinkReg = true;
129  }
130  } else if (Subtarget->inMicroMipsMode())
131  // microMIPS should use (JR_MM $rs)
132  TmpInst0.setOpcode(Mips::JR_MM);
133  else {
134  // Everything else should use (JR $rs)
135  TmpInst0.setOpcode(Mips::JR);
136  }
137 
138  MCOperand MCOp;
139 
140  if (HasLinkReg) {
141  unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
142  TmpInst0.addOperand(MCOperand::createReg(ZeroReg));
143  }
144 
145  lowerOperand(MI->getOperand(0), MCOp);
146  TmpInst0.addOperand(MCOp);
147 
148  EmitToStreamer(OutStreamer, TmpInst0);
149 }
150 
152  MipsTargetStreamer &TS = getTargetStreamer();
153  unsigned Opc = MI->getOpcode();
155 
156  if (MI->isDebugValue()) {
157  SmallString<128> Str;
158  raw_svector_ostream OS(Str);
159 
160  PrintDebugValueComment(MI, OS);
161  return;
162  }
163  if (MI->isDebugLabel())
164  return;
165 
166  // If we just ended a constant pool, mark it as such.
167  if (InConstantPool && Opc != Mips::CONSTPOOL_ENTRY) {
168  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
169  InConstantPool = false;
170  }
171  if (Opc == Mips::CONSTPOOL_ENTRY) {
172  // CONSTPOOL_ENTRY - This instruction represents a floating
173  // constant pool in the function. The first operand is the ID#
174  // for this instruction, the second is the index into the
175  // MachineConstantPool that this is, the third is the size in
176  // bytes of this constant pool entry.
177  // The required alignment is specified on the basic block holding this MI.
178  //
179  unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
180  unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
181 
182  // If this is the first entry of the pool, mark it.
183  if (!InConstantPool) {
184  OutStreamer->EmitDataRegion(MCDR_DataRegion);
185  InConstantPool = true;
186  }
187 
188  OutStreamer->EmitLabel(GetCPISymbol(LabelId));
189 
190  const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
191  if (MCPE.isMachineConstantPoolEntry())
193  else
195  return;
196  }
197 
198  switch (Opc) {
199  case Mips::PATCHABLE_FUNCTION_ENTER:
201  return;
202  case Mips::PATCHABLE_FUNCTION_EXIT:
204  return;
205  case Mips::PATCHABLE_TAIL_CALL:
207  return;
208  }
209 
212 
213  do {
214  // Do any auto-generated pseudo lowerings.
215  if (emitPseudoExpansionLowering(*OutStreamer, &*I))
216  continue;
217 
218  if (I->getOpcode() == Mips::PseudoReturn ||
219  I->getOpcode() == Mips::PseudoReturn64 ||
220  I->getOpcode() == Mips::PseudoIndirectBranch ||
221  I->getOpcode() == Mips::PseudoIndirectBranch64 ||
222  I->getOpcode() == Mips::TAILCALLREG ||
223  I->getOpcode() == Mips::TAILCALLREG64) {
224  emitPseudoIndirectBranch(*OutStreamer, &*I);
225  continue;
226  }
227 
228  // The inMips16Mode() test is not permanent.
229  // Some instructions are marked as pseudo right now which
230  // would make the test fail for the wrong reason but
231  // that will be fixed soon. We need this here because we are
232  // removing another test for this situation downstream in the
233  // callchain.
234  //
235  if (I->isPseudo() && !Subtarget->inMips16Mode()
236  && !isLongBranchPseudo(I->getOpcode()))
237  llvm_unreachable("Pseudo opcode found in EmitInstruction()");
238 
239  MCInst TmpInst0;
240  MCInstLowering.Lower(&*I, TmpInst0);
241  EmitToStreamer(*OutStreamer, TmpInst0);
242  } while ((++I != E) && I->isInsideBundle()); // Delay slot check
243 }
244 
245 //===----------------------------------------------------------------------===//
246 //
247 // Mips Asm Directives
248 //
249 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
250 // Describe the stack frame.
251 //
252 // -- Mask directives "(f)mask bitmask, offset"
253 // Tells the assembler which registers are saved and where.
254 // bitmask - contain a little endian bitset indicating which registers are
255 // saved on function prologue (e.g. with a 0x80000000 mask, the
256 // assembler knows the register 31 (RA) is saved at prologue.
257 // offset - the position before stack pointer subtraction indicating where
258 // the first saved register on prologue is located. (e.g. with a
259 //
260 // Consider the following function prologue:
261 //
262 // .frame $fp,48,$ra
263 // .mask 0xc0000000,-8
264 // addiu $sp, $sp, -48
265 // sw $ra, 40($sp)
266 // sw $fp, 36($sp)
267 //
268 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
269 // 30 (FP) are saved at prologue. As the save order on prologue is from
270 // left to right, RA is saved first. A -8 offset means that after the
271 // stack pointer subtration, the first register in the mask (RA) will be
272 // saved at address 48-8=40.
273 //
274 //===----------------------------------------------------------------------===//
275 
276 //===----------------------------------------------------------------------===//
277 // Mask directives
278 //===----------------------------------------------------------------------===//
279 
280 // Create a bitmask with all callee saved registers for CPU or Floating Point
281 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
283  // CPU and FPU Saved Registers Bitmasks
284  unsigned CPUBitmask = 0, FPUBitmask = 0;
285  int CPUTopSavedRegOff, FPUTopSavedRegOff;
286 
287  // Set the CPU and FPU Bitmasks
288  const MachineFrameInfo &MFI = MF->getFrameInfo();
290  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
291  // size of stack area to which FP callee-saved regs are saved.
292  unsigned CPURegSize = TRI->getRegSizeInBits(Mips::GPR32RegClass) / 8;
293  unsigned FGR32RegSize = TRI->getRegSizeInBits(Mips::FGR32RegClass) / 8;
294  unsigned AFGR64RegSize = TRI->getRegSizeInBits(Mips::AFGR64RegClass) / 8;
295  bool HasAFGR64Reg = false;
296  unsigned CSFPRegsSize = 0;
297 
298  for (const auto &I : CSI) {
299  unsigned Reg = I.getReg();
300  unsigned RegNum = TRI->getEncodingValue(Reg);
301 
302  // If it's a floating point register, set the FPU Bitmask.
303  // If it's a general purpose register, set the CPU Bitmask.
304  if (Mips::FGR32RegClass.contains(Reg)) {
305  FPUBitmask |= (1 << RegNum);
306  CSFPRegsSize += FGR32RegSize;
307  } else if (Mips::AFGR64RegClass.contains(Reg)) {
308  FPUBitmask |= (3 << RegNum);
309  CSFPRegsSize += AFGR64RegSize;
310  HasAFGR64Reg = true;
311  } else if (Mips::GPR32RegClass.contains(Reg))
312  CPUBitmask |= (1 << RegNum);
313  }
314 
315  // FP Regs are saved right below where the virtual frame pointer points to.
316  FPUTopSavedRegOff = FPUBitmask ?
317  (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
318 
319  // CPU Regs are saved below FP Regs.
320  CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
321 
322  MipsTargetStreamer &TS = getTargetStreamer();
323  // Print CPUBitmask
324  TS.emitMask(CPUBitmask, CPUTopSavedRegOff);
325 
326  // Print FPUBitmask
327  TS.emitFMask(FPUBitmask, FPUTopSavedRegOff);
328 }
329 
330 //===----------------------------------------------------------------------===//
331 // Frame and Set directives
332 //===----------------------------------------------------------------------===//
333 
334 /// Frame Directive
337 
338  unsigned stackReg = RI.getFrameRegister(*MF);
339  unsigned returnReg = RI.getRARegister();
340  unsigned stackSize = MF->getFrameInfo().getStackSize();
341 
342  getTargetStreamer().emitFrame(stackReg, stackSize, returnReg);
343 }
344 
345 /// Emit Set directives.
347  switch (static_cast<MipsTargetMachine &>(TM).getABI().GetEnumValue()) {
348  case MipsABIInfo::ABI::O32: return "abi32";
349  case MipsABIInfo::ABI::N32: return "abiN32";
350  case MipsABIInfo::ABI::N64: return "abi64";
351  default: llvm_unreachable("Unknown Mips ABI");
352  }
353 }
354 
356  MipsTargetStreamer &TS = getTargetStreamer();
357 
358  // NaCl sandboxing requires that indirect call instructions are masked.
359  // This means that function entry points should be bundle-aligned.
360  if (Subtarget->isTargetNaCl())
362 
363  if (Subtarget->inMicroMipsMode()) {
365  TS.setUsesMicroMips();
367  } else
369 
370  if (Subtarget->inMips16Mode())
372  else
374 
376  OutStreamer->EmitLabel(CurrentFnSym);
377 }
378 
379 /// EmitFunctionBodyStart - Targets can override this to emit stuff before
380 /// the first basic block in the function.
382  MipsTargetStreamer &TS = getTargetStreamer();
383 
385 
386  bool IsNakedFunction = MF->getFunction().hasFnAttribute(Attribute::Naked);
387  if (!IsNakedFunction)
389 
390  if (!IsNakedFunction)
392 
393  if (!Subtarget->inMips16Mode()) {
397  }
398 }
399 
400 /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
401 /// the last basic block in the function.
403  MipsTargetStreamer &TS = getTargetStreamer();
404 
405  // There are instruction for this macros, but they must
406  // always be at the function end, and we can't emit and
407  // break with BB logic.
408  if (!Subtarget->inMips16Mode()) {
409  TS.emitDirectiveSetAt();
412  }
414  // Make sure to terminate any constant pools that were at the end
415  // of the function.
416  if (!InConstantPool)
417  return;
418  InConstantPool = false;
419  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
420 }
421 
424  MipsTargetStreamer &TS = getTargetStreamer();
425  if (MBB.empty())
426  TS.emitDirectiveInsn();
427 }
428 
429 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
430 /// exactly one predecessor and the control transfer mechanism between
431 /// the predecessor and this block is a fall-through.
433  MBB) const {
434  // The predecessor has to be immediately before this block.
435  const MachineBasicBlock *Pred = *MBB->pred_begin();
436 
437  // If the predecessor is a switch statement, assume a jump table
438  // implementation, so it is not a fall through.
439  if (const BasicBlock *bb = Pred->getBasicBlock())
440  if (isa<SwitchInst>(bb->getTerminator()))
441  return false;
442 
443  // If this is a landing pad, it isn't a fall through. If it has no preds,
444  // then nothing falls through to it.
445  if (MBB->isEHPad() || MBB->pred_empty())
446  return false;
447 
448  // If there isn't exactly one predecessor, it can't be a fall through.
450  ++PI2;
451 
452  if (PI2 != MBB->pred_end())
453  return false;
454 
455  // The predecessor has to be immediately before this block.
456  if (!Pred->isLayoutSuccessor(MBB))
457  return false;
458 
459  // If the block is completely empty, then it definitely does fall through.
460  if (Pred->empty())
461  return true;
462 
463  // Otherwise, check the last instruction.
464  // Check if the last terminator is an unconditional branch.
466  while (I != Pred->begin() && !(--I)->isTerminator()) ;
467 
468  return !I->isBarrier();
469 }
470 
471 // Print out an operand for an inline asm expression.
472 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
473  unsigned AsmVariant, const char *ExtraCode,
474  raw_ostream &O) {
475  // Does this asm operand have a single letter operand modifier?
476  if (ExtraCode && ExtraCode[0]) {
477  if (ExtraCode[1] != 0) return true; // Unknown modifier.
478 
479  const MachineOperand &MO = MI->getOperand(OpNum);
480  switch (ExtraCode[0]) {
481  default:
482  // See if this is a generic print operand
483  return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O);
484  case 'X': // hex const int
486  return true;
487  O << "0x" << Twine::utohexstr(MO.getImm());
488  return false;
489  case 'x': // hex const int (low 16 bits)
491  return true;
492  O << "0x" << Twine::utohexstr(MO.getImm() & 0xffff);
493  return false;
494  case 'd': // decimal const int
496  return true;
497  O << MO.getImm();
498  return false;
499  case 'm': // decimal const int minus 1
501  return true;
502  O << MO.getImm() - 1;
503  return false;
504  case 'y': // exact log2
506  return true;
507  if (!isPowerOf2_64(MO.getImm()))
508  return true;
509  O << Log2_64(MO.getImm());
510  return false;
511  case 'z':
512  // $0 if zero, regular printing otherwise
513  if (MO.getType() == MachineOperand::MO_Immediate && MO.getImm() == 0) {
514  O << "$0";
515  return false;
516  }
517  // If not, call printOperand as normal.
518  break;
519  case 'D': // Second part of a double word register operand
520  case 'L': // Low order register of a double word register operand
521  case 'M': // High order register of a double word register operand
522  {
523  if (OpNum == 0)
524  return true;
525  const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
526  if (!FlagsOP.isImm())
527  return true;
528  unsigned Flags = FlagsOP.getImm();
529  unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
530  // Number of registers represented by this operand. We are looking
531  // for 2 for 32 bit mode and 1 for 64 bit mode.
532  if (NumVals != 2) {
533  if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
534  unsigned Reg = MO.getReg();
535  O << '$' << MipsInstPrinter::getRegisterName(Reg);
536  return false;
537  }
538  return true;
539  }
540 
541  unsigned RegOp = OpNum;
542  if (!Subtarget->isGP64bit()){
543  // Endianness reverses which register holds the high or low value
544  // between M and L.
545  switch(ExtraCode[0]) {
546  case 'M':
547  RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
548  break;
549  case 'L':
550  RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
551  break;
552  case 'D': // Always the second part
553  RegOp = OpNum + 1;
554  }
555  if (RegOp >= MI->getNumOperands())
556  return true;
557  const MachineOperand &MO = MI->getOperand(RegOp);
558  if (!MO.isReg())
559  return true;
560  unsigned Reg = MO.getReg();
561  O << '$' << MipsInstPrinter::getRegisterName(Reg);
562  return false;
563  }
564  }
565  case 'w':
566  // Print MSA registers for the 'f' constraint
567  // In LLVM, the 'w' modifier doesn't need to do anything.
568  // We can just call printOperand as normal.
569  break;
570  }
571  }
572 
573  printOperand(MI, OpNum, O);
574  return false;
575 }
576 
578  unsigned OpNum, unsigned AsmVariant,
579  const char *ExtraCode,
580  raw_ostream &O) {
581  assert(OpNum + 1 < MI->getNumOperands() && "Insufficient operands");
582  const MachineOperand &BaseMO = MI->getOperand(OpNum);
583  const MachineOperand &OffsetMO = MI->getOperand(OpNum + 1);
584  assert(BaseMO.isReg() && "Unexpected base pointer for inline asm memory operand.");
585  assert(OffsetMO.isImm() && "Unexpected offset for inline asm memory operand.");
586  int Offset = OffsetMO.getImm();
587 
588  // Currently we are expecting either no ExtraCode or 'D','M','L'.
589  if (ExtraCode) {
590  switch (ExtraCode[0]) {
591  case 'D':
592  Offset += 4;
593  break;
594  case 'M':
595  if (Subtarget->isLittle())
596  Offset += 4;
597  break;
598  case 'L':
599  if (!Subtarget->isLittle())
600  Offset += 4;
601  break;
602  default:
603  return true; // Unknown modifier.
604  }
605  }
606 
607  O << Offset << "($" << MipsInstPrinter::getRegisterName(BaseMO.getReg())
608  << ")";
609 
610  return false;
611 }
612 
613 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
614  raw_ostream &O) {
615  const MachineOperand &MO = MI->getOperand(opNum);
616  bool closeP = false;
617 
618  if (MO.getTargetFlags())
619  closeP = true;
620 
621  switch(MO.getTargetFlags()) {
622  case MipsII::MO_GPREL: O << "%gp_rel("; break;
623  case MipsII::MO_GOT_CALL: O << "%call16("; break;
624  case MipsII::MO_GOT: O << "%got("; break;
625  case MipsII::MO_ABS_HI: O << "%hi("; break;
626  case MipsII::MO_ABS_LO: O << "%lo("; break;
627  case MipsII::MO_HIGHER: O << "%higher("; break;
628  case MipsII::MO_HIGHEST: O << "%highest(("; break;
629  case MipsII::MO_TLSGD: O << "%tlsgd("; break;
630  case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
631  case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
632  case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
633  case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
634  case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
635  case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
636  case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
637  case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
638  }
639 
640  switch (MO.getType()) {
642  O << '$'
644  break;
645 
647  O << MO.getImm();
648  break;
649 
651  MO.getMBB()->getSymbol()->print(O, MAI);
652  return;
653 
655  getSymbol(MO.getGlobal())->print(O, MAI);
656  break;
657 
660  O << BA->getName();
661  break;
662  }
663 
665  O << getDataLayout().getPrivateGlobalPrefix() << "CPI"
666  << getFunctionNumber() << "_" << MO.getIndex();
667  if (MO.getOffset())
668  O << "+" << MO.getOffset();
669  break;
670 
671  default:
672  llvm_unreachable("<unknown operand type>");
673  }
674 
675  if (closeP) O << ")";
676 }
677 
678 void MipsAsmPrinter::
679 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
680  // Load/Store memory operands -- imm($reg)
681  // If PIC target the target is loaded as the
682  // pattern lw $25,%call16($28)
683 
684  // opNum can be invalid if instruction has reglist as operand.
685  // MemOperand is always last operand of instruction (base + offset).
686  switch (MI->getOpcode()) {
687  default:
688  break;
689  case Mips::SWM32_MM:
690  case Mips::LWM32_MM:
691  opNum = MI->getNumOperands() - 2;
692  break;
693  }
694 
695  printOperand(MI, opNum+1, O);
696  O << "(";
697  printOperand(MI, opNum, O);
698  O << ")";
699 }
700 
701 void MipsAsmPrinter::
702 printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
703  // when using stack locations for not load/store instructions
704  // print the same way as all normal 3 operand instructions.
705  printOperand(MI, opNum, O);
706  O << ", ";
707  printOperand(MI, opNum+1, O);
708 }
709 
710 void MipsAsmPrinter::
711 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
712  const char *Modifier) {
713  const MachineOperand &MO = MI->getOperand(opNum);
715 }
716 
717 void MipsAsmPrinter::
718 printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O) {
719  for (int i = opNum, e = MI->getNumOperands(); i != e; ++i) {
720  if (i != opNum) O << ", ";
721  printOperand(MI, i, O);
722  }
723 }
724 
726  MipsTargetStreamer &TS = getTargetStreamer();
727 
728  // MipsTargetStreamer has an initialization order problem when emitting an
729  // object file directly (see MipsTargetELFStreamer for full details). Work
730  // around it by re-initializing the PIC state here.
732 
733  // Compute MIPS architecture attributes based on the default subtarget
734  // that we'd have constructed. Module level directives aren't LTO
735  // clean anyhow.
736  // FIXME: For ifunc related functions we could iterate over and look
737  // for a feature string that doesn't match the default one.
738  const Triple &TT = TM.getTargetTriple();
741  const MipsTargetMachine &MTM = static_cast<const MipsTargetMachine &>(TM);
742  const MipsSubtarget STI(TT, CPU, FS, MTM.isLittleEndian(), MTM, 0);
743 
744  bool IsABICalls = STI.isABICalls();
745  const MipsABIInfo &ABI = MTM.getABI();
746  if (IsABICalls) {
748  // FIXME: This condition should be a lot more complicated that it is here.
749  // Ideally it should test for properties of the ABI and not the ABI
750  // itself.
751  // For the moment, I'm only correcting enough to make MIPS-IV work.
752  if (!isPositionIndependent() && STI.hasSym32())
754  }
755 
756  // Tell the assembler which ABI we are using
757  std::string SectionName = std::string(".mdebug.") + getCurrentABIString();
758  OutStreamer->SwitchSection(
759  OutContext.getELFSection(SectionName, ELF::SHT_PROGBITS, 0));
760 
761  // NaN: At the moment we only support:
762  // 1. .nan legacy (default)
763  // 2. .nan 2008
764  STI.isNaN2008() ? TS.emitDirectiveNaN2008()
765  : TS.emitDirectiveNaNLegacy();
766 
767  // TODO: handle O64 ABI
768 
769  TS.updateABIInfo(STI);
770 
771  // We should always emit a '.module fp=...' but binutils 2.24 does not accept
772  // it. We therefore emit it when it contradicts the ABI defaults (-mfpxx or
773  // -mfp64) and omit it otherwise.
774  if (ABI.IsO32() && (STI.isABI_FPXX() || STI.isFP64bit()))
776 
777  // We should always emit a '.module [no]oddspreg' but binutils 2.24 does not
778  // accept it. We therefore emit it when it contradicts the default or an
779  // option has changed the default (i.e. FPXX) and omit it otherwise.
780  if (ABI.IsO32() && (!STI.useOddSPReg() || STI.isABI_FPXX()))
782 }
783 
784 void MipsAsmPrinter::emitInlineAsmStart() const {
785  MipsTargetStreamer &TS = getTargetStreamer();
786 
787  // GCC's choice of assembler options for inline assembly code ('at', 'macro'
788  // and 'reorder') is different from LLVM's choice for generated code ('noat',
789  // 'nomacro' and 'noreorder').
790  // In order to maintain compatibility with inline assembly code which depends
791  // on GCC's assembler options being used, we have to switch to those options
792  // for the duration of the inline assembly block and then switch back.
794  TS.emitDirectiveSetAt();
797  OutStreamer->AddBlankLine();
798 }
799 
800 void MipsAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
801  const MCSubtargetInfo *EndInfo) const {
802  OutStreamer->AddBlankLine();
803  getTargetStreamer().emitDirectiveSetPop();
804 }
805 
806 void MipsAsmPrinter::EmitJal(const MCSubtargetInfo &STI, MCSymbol *Symbol) {
807  MCInst I;
808  I.setOpcode(Mips::JAL);
809  I.addOperand(
811  OutStreamer->EmitInstruction(I, STI);
812 }
813 
814 void MipsAsmPrinter::EmitInstrReg(const MCSubtargetInfo &STI, unsigned Opcode,
815  unsigned Reg) {
816  MCInst I;
817  I.setOpcode(Opcode);
819  OutStreamer->EmitInstruction(I, STI);
820 }
821 
822 void MipsAsmPrinter::EmitInstrRegReg(const MCSubtargetInfo &STI,
823  unsigned Opcode, unsigned Reg1,
824  unsigned Reg2) {
825  MCInst I;
826  //
827  // Because of the current td files for Mips32, the operands for MTC1
828  // appear backwards from their normal assembly order. It's not a trivial
829  // change to fix this in the td file so we adjust for it here.
830  //
831  if (Opcode == Mips::MTC1) {
832  unsigned Temp = Reg1;
833  Reg1 = Reg2;
834  Reg2 = Temp;
835  }
836  I.setOpcode(Opcode);
839  OutStreamer->EmitInstruction(I, STI);
840 }
841 
842 void MipsAsmPrinter::EmitInstrRegRegReg(const MCSubtargetInfo &STI,
843  unsigned Opcode, unsigned Reg1,
844  unsigned Reg2, unsigned Reg3) {
845  MCInst I;
846  I.setOpcode(Opcode);
850  OutStreamer->EmitInstruction(I, STI);
851 }
852 
853 void MipsAsmPrinter::EmitMovFPIntPair(const MCSubtargetInfo &STI,
854  unsigned MovOpc, unsigned Reg1,
855  unsigned Reg2, unsigned FPReg1,
856  unsigned FPReg2, bool LE) {
857  if (!LE) {
858  unsigned temp = Reg1;
859  Reg1 = Reg2;
860  Reg2 = temp;
861  }
862  EmitInstrRegReg(STI, MovOpc, Reg1, FPReg1);
863  EmitInstrRegReg(STI, MovOpc, Reg2, FPReg2);
864 }
865 
866 void MipsAsmPrinter::EmitSwapFPIntParams(const MCSubtargetInfo &STI,
868  bool LE, bool ToFP) {
869  using namespace Mips16HardFloatInfo;
870 
871  unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1;
872  switch (PV) {
873  case FSig:
874  EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);
875  break;
876  case FFSig:
877  EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F14, LE);
878  break;
879  case FDSig:
880  EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);
881  EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
882  break;
883  case DSig:
884  EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
885  break;
886  case DDSig:
887  EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
888  EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
889  break;
890  case DFSig:
891  EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
892  EmitInstrRegReg(STI, MovOpc, Mips::A2, Mips::F14);
893  break;
894  case NoSig:
895  return;
896  }
897 }
898 
899 void MipsAsmPrinter::EmitSwapFPIntRetval(
901  bool LE) {
902  using namespace Mips16HardFloatInfo;
903 
904  unsigned MovOpc = Mips::MFC1;
905  switch (RV) {
906  case FRet:
907  EmitInstrRegReg(STI, MovOpc, Mips::V0, Mips::F0);
908  break;
909  case DRet:
910  EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
911  break;
912  case CFRet:
913  EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
914  break;
915  case CDRet:
916  EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
917  EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F2, Mips::F3, LE);
918  break;
919  case NoFPRet:
920  break;
921  }
922 }
923 
924 void MipsAsmPrinter::EmitFPCallStub(
925  const char *Symbol, const Mips16HardFloatInfo::FuncSignature *Signature) {
926  using namespace Mips16HardFloatInfo;
927 
928  MCSymbol *MSymbol = OutContext.getOrCreateSymbol(StringRef(Symbol));
929  bool LE = getDataLayout().isLittleEndian();
930  // Construct a local MCSubtargetInfo here.
931  // This is because the MachineFunction won't exist (but have not yet been
932  // freed) and since we're at the global level we can use the default
933  // constructed subtarget.
934  std::unique_ptr<MCSubtargetInfo> STI(TM.getTarget().createMCSubtargetInfo(
937 
938  //
939  // .global xxxx
940  //
941  OutStreamer->EmitSymbolAttribute(MSymbol, MCSA_Global);
942  const char *RetType;
943  //
944  // make the comment field identifying the return and parameter
945  // types of the floating point stub
946  // # Stub function to call rettype xxxx (params)
947  //
948  switch (Signature->RetSig) {
949  case FRet:
950  RetType = "float";
951  break;
952  case DRet:
953  RetType = "double";
954  break;
955  case CFRet:
956  RetType = "complex";
957  break;
958  case CDRet:
959  RetType = "double complex";
960  break;
961  case NoFPRet:
962  RetType = "";
963  break;
964  }
965  const char *Parms;
966  switch (Signature->ParamSig) {
967  case FSig:
968  Parms = "float";
969  break;
970  case FFSig:
971  Parms = "float, float";
972  break;
973  case FDSig:
974  Parms = "float, double";
975  break;
976  case DSig:
977  Parms = "double";
978  break;
979  case DDSig:
980  Parms = "double, double";
981  break;
982  case DFSig:
983  Parms = "double, float";
984  break;
985  case NoSig:
986  Parms = "";
987  break;
988  }
989  OutStreamer->AddComment("\t# Stub function to call " + Twine(RetType) + " " +
990  Twine(Symbol) + " (" + Twine(Parms) + ")");
991  //
992  // probably not necessary but we save and restore the current section state
993  //
994  OutStreamer->PushSection();
995  //
996  // .section mips16.call.fpxxxx,"ax",@progbits
997  //
999  ".mips16.call.fp." + std::string(Symbol), ELF::SHT_PROGBITS,
1001  OutStreamer->SwitchSection(M, nullptr);
1002  //
1003  // .align 2
1004  //
1005  OutStreamer->EmitValueToAlignment(4);
1006  MipsTargetStreamer &TS = getTargetStreamer();
1007  //
1008  // .set nomips16
1009  // .set nomicromips
1010  //
1013  //
1014  // .ent __call_stub_fp_xxxx
1015  // .type __call_stub_fp_xxxx,@function
1016  // __call_stub_fp_xxxx:
1017  //
1018  std::string x = "__call_stub_fp_" + std::string(Symbol);
1019  MCSymbolELF *Stub =
1020  cast<MCSymbolELF>(OutContext.getOrCreateSymbol(StringRef(x)));
1021  TS.emitDirectiveEnt(*Stub);
1022  MCSymbol *MType =
1023  OutContext.getOrCreateSymbol("__call_stub_fp_" + Twine(Symbol));
1024  OutStreamer->EmitSymbolAttribute(MType, MCSA_ELF_TypeFunction);
1025  OutStreamer->EmitLabel(Stub);
1026 
1027  // Only handle non-pic for now.
1029  "should not be here if we are compiling pic");
1031  //
1032  // We need to add a MipsMCExpr class to MCTargetDesc to fully implement
1033  // stubs without raw text but this current patch is for compiler generated
1034  // functions and they all return some value.
1035  // The calling sequence for non pic is different in that case and we need
1036  // to implement %lo and %hi in order to handle the case of no return value
1037  // See the corresponding method in Mips16HardFloat for details.
1038  //
1039  // mov the return address to S2.
1040  // we have no stack space to store it and we are about to make another call.
1041  // We need to make sure that the enclosing function knows to save S2
1042  // This should have already been handled.
1043  //
1044  // Mov $18, $31
1045 
1046  EmitInstrRegRegReg(*STI, Mips::OR, Mips::S2, Mips::RA, Mips::ZERO);
1047 
1048  EmitSwapFPIntParams(*STI, Signature->ParamSig, LE, true);
1049 
1050  // Jal xxxx
1051  //
1052  EmitJal(*STI, MSymbol);
1053 
1054  // fix return values
1055  EmitSwapFPIntRetval(*STI, Signature->RetSig, LE);
1056  //
1057  // do the return
1058  // if (Signature->RetSig == NoFPRet)
1059  // llvm_unreachable("should not be any stubs here with no return value");
1060  // else
1061  EmitInstrReg(*STI, Mips::JR, Mips::S2);
1062 
1064  OutStreamer->EmitLabel(Tmp);
1067  const MCExpr *T_min_E = MCBinaryExpr::createSub(T, E, OutContext);
1068  OutStreamer->emitELFSize(Stub, T_min_E);
1069  TS.emitDirectiveEnd(x);
1070  OutStreamer->PopSection();
1071 }
1072 
1074  // Emit needed stubs
1075  //
1076  for (std::map<
1077  const char *,
1078  const Mips16HardFloatInfo::FuncSignature *>::const_iterator
1079  it = StubsNeeded.begin();
1080  it != StubsNeeded.end(); ++it) {
1081  const char *Symbol = it->first;
1082  const Mips16HardFloatInfo::FuncSignature *Signature = it->second;
1083  EmitFPCallStub(Symbol, Signature);
1084  }
1085  // return to the text section
1087 }
1088 
1089 void MipsAsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind) {
1090  const uint8_t NoopsInSledCount = Subtarget->isGP64bit() ? 15 : 11;
1091  // For mips32 we want to emit the following pattern:
1092  //
1093  // .Lxray_sled_N:
1094  // ALIGN
1095  // B .tmpN
1096  // 11 NOP instructions (44 bytes)
1097  // ADDIU T9, T9, 52
1098  // .tmpN
1099  //
1100  // We need the 44 bytes (11 instructions) because at runtime, we'd
1101  // be patching over the full 48 bytes (12 instructions) with the following
1102  // pattern:
1103  //
1104  // ADDIU SP, SP, -8
1105  // NOP
1106  // SW RA, 4(SP)
1107  // SW T9, 0(SP)
1108  // LUI T9, %hi(__xray_FunctionEntry/Exit)
1109  // ORI T9, T9, %lo(__xray_FunctionEntry/Exit)
1110  // LUI T0, %hi(function_id)
1111  // JALR T9
1112  // ORI T0, T0, %lo(function_id)
1113  // LW T9, 0(SP)
1114  // LW RA, 4(SP)
1115  // ADDIU SP, SP, 8
1116  //
1117  // We add 52 bytes to t9 because we want to adjust the function pointer to
1118  // the actual start of function i.e. the address just after the noop sled.
1119  // We do this because gp displacement relocation is emitted at the start of
1120  // of the function i.e after the nop sled and to correctly calculate the
1121  // global offset table address, t9 must hold the address of the instruction
1122  // containing the gp displacement relocation.
1123  // FIXME: Is this correct for the static relocation model?
1124  //
1125  // For mips64 we want to emit the following pattern:
1126  //
1127  // .Lxray_sled_N:
1128  // ALIGN
1129  // B .tmpN
1130  // 15 NOP instructions (60 bytes)
1131  // .tmpN
1132  //
1133  // We need the 60 bytes (15 instructions) because at runtime, we'd
1134  // be patching over the full 64 bytes (16 instructions) with the following
1135  // pattern:
1136  //
1137  // DADDIU SP, SP, -16
1138  // NOP
1139  // SD RA, 8(SP)
1140  // SD T9, 0(SP)
1141  // LUI T9, %highest(__xray_FunctionEntry/Exit)
1142  // ORI T9, T9, %higher(__xray_FunctionEntry/Exit)
1143  // DSLL T9, T9, 16
1144  // ORI T9, T9, %hi(__xray_FunctionEntry/Exit)
1145  // DSLL T9, T9, 16
1146  // ORI T9, T9, %lo(__xray_FunctionEntry/Exit)
1147  // LUI T0, %hi(function_id)
1148  // JALR T9
1149  // ADDIU T0, T0, %lo(function_id)
1150  // LD T9, 0(SP)
1151  // LD RA, 8(SP)
1152  // DADDIU SP, SP, 16
1153  //
1154  OutStreamer->EmitCodeAlignment(4);
1155  auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1156  OutStreamer->EmitLabel(CurSled);
1158 
1159  // Emit "B .tmpN" instruction, which jumps over the nop sled to the actual
1160  // start of function
1161  const MCExpr *TargetExpr = MCSymbolRefExpr::create(
1162  Target, MCSymbolRefExpr::VariantKind::VK_None, OutContext);
1163  EmitToStreamer(*OutStreamer, MCInstBuilder(Mips::BEQ)
1164  .addReg(Mips::ZERO)
1165  .addReg(Mips::ZERO)
1166  .addExpr(TargetExpr));
1167 
1168  for (int8_t I = 0; I < NoopsInSledCount; I++)
1169  EmitToStreamer(*OutStreamer, MCInstBuilder(Mips::SLL)
1170  .addReg(Mips::ZERO)
1171  .addReg(Mips::ZERO)
1172  .addImm(0));
1173 
1174  OutStreamer->EmitLabel(Target);
1175 
1176  if (!Subtarget->isGP64bit()) {
1177  EmitToStreamer(*OutStreamer,
1178  MCInstBuilder(Mips::ADDiu)
1179  .addReg(Mips::T9)
1180  .addReg(Mips::T9)
1181  .addImm(0x34));
1182  }
1183 
1184  recordSled(CurSled, MI, Kind);
1185 }
1186 
1188  EmitSled(MI, SledKind::FUNCTION_ENTER);
1189 }
1190 
1192  EmitSled(MI, SledKind::FUNCTION_EXIT);
1193 }
1194 
1196  EmitSled(MI, SledKind::TAIL_CALL);
1197 }
1198 
1200  raw_ostream &OS) {
1201  // TODO: implement
1202 }
1203 
1204 // Emit .dtprelword or .dtpreldword directive
1205 // and value for debug thread local expression.
1207  unsigned Size) const {
1208  switch (Size) {
1209  case 4:
1210  OutStreamer->EmitDTPRel32Value(Value);
1211  break;
1212  case 8:
1213  OutStreamer->EmitDTPRel64Value(Value);
1214  break;
1215  default:
1216  llvm_unreachable("Unexpected size of expression value.");
1217  }
1218 }
1219 
1220 // Align all targets of indirect branches on bundle size. Used only if target
1221 // is NaCl.
1222 void MipsAsmPrinter::NaClAlignIndirectJumpTargets(MachineFunction &MF) {
1223  // Align all blocks that are jumped to through jump table.
1224  if (MachineJumpTableInfo *JtInfo = MF.getJumpTableInfo()) {
1225  const std::vector<MachineJumpTableEntry> &JT = JtInfo->getJumpTables();
1226  for (unsigned I = 0; I < JT.size(); ++I) {
1227  const std::vector<MachineBasicBlock*> &MBBs = JT[I].MBBs;
1228 
1229  for (unsigned J = 0; J < MBBs.size(); ++J)
1230  MBBs[J]->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
1231  }
1232  }
1233 
1234  // If basic block address is taken, block can be target of indirect branch.
1235  for (auto &MBB : MF) {
1236  if (MBB.hasAddressTaken())
1237  MBB.setAlignment(MIPS_NACL_BUNDLE_ALIGN);
1238  }
1239 }
1240 
1241 bool MipsAsmPrinter::isLongBranchPseudo(int Opcode) const {
1242  return (Opcode == Mips::LONG_BRANCH_LUi
1243  || Opcode == Mips::LONG_BRANCH_ADDiu
1244  || Opcode == Mips::LONG_BRANCH_DADDiu);
1245 }
1246 
1247 // Force static initialization.
1248 extern "C" void LLVMInitializeMipsAsmPrinter() {
1253 }
unsigned getTargetFlags() const
MachineConstantPoolValue * MachineCPVal
virtual void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff)
bool isABICalls() const
StringRef getTargetFeatureString() const
bool isDebugLabel() const
Definition: MachineInstr.h:850
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
instr_iterator instr_end()
MachineBasicBlock * getMBB() const
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:93
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:321
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
StringRef getPrivateGlobalPrefix() const
Definition: DataLayout.h:294
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
bool inMips16Mode() const
virtual void AddBlankLine()
AddBlankLine - Emit a blank line to a .s file to pretty it up.
Definition: MCStreamer.h:324
MO_HIGHER/HIGHEST - Represents the highest or higher half word of a 64-bit symbol address...
Definition: MipsBaseInfo.h:85
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:88
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:137
void EmitFunctionBodyEnd() override
EmitFunctionBodyEnd - Targets can override this to emit stuff after the last basic block in the funct...
MO_TLSGD - Represents the offset into the global offset table at which.
Definition: MipsBaseInfo.h:58
unsigned getReg() const
getReg - Returns the register number.
unsigned Reg
Target & getTheMipselTarget()
virtual void EmitDTPRel64Value(const MCExpr *Value)
Emit the expression Value into the output as a dtprel (64-bit DTP relative) value.
Definition: MCStreamer.cpp:158
virtual void emitDirectiveSetNoReorder()
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:307
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:504
bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const override
isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the...
void PushSection()
Save the current and previous section on the section stack.
Definition: MCStreamer.h:359
MachineBasicBlock reference.
unsigned const TargetRegisterInfo * TRI
MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:96
void Initialize(MCContext *C)
std::vector< MachineBasicBlock * >::const_iterator const_pred_iterator
void EmitFunctionBodyStart() override
EmitFunctionBodyStart - Targets can override this to emit stuff before the first basic block in the f...
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void EmitFunctionEntryLabel() override
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, bool PrintSchedInfo=false)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:907
return AArch64::GPR64RegClass contains(Reg)
union llvm::MachineConstantPoolEntry::@145 Val
The constant itself.
SI optimize exec mask operations pre RA
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
virtual void emitDirectiveSetMicroMips()
void recordSled(MCSymbol *Sled, const MachineInstr &MI, SledKind Kind, uint8_t Version=0)
bool isMachineConstantPoolEntry() const
isMachineConstantPoolEntry - Return true if the MachineConstantPoolEntry is indeed a target specific ...
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:116
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
virtual void emitFrame(unsigned StackReg, unsigned StackSize, unsigned ReturnReg)
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:314
bool inMicroMipsMode() const
void LLVMInitializeMipsAsmPrinter()
virtual void emitDirectiveSetNoMacro()
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
virtual void emitDirectiveEnd(StringRef Name)
bool isGP64bit() const
This file contains the simple types necessary to represent the attributes associated with functions a...
unsigned getAlignment() const
getAlignment - Return the alignment (log2, not bytes) of the function.
bool hasMips32r6() const
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:166
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:311
virtual unsigned getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
void EmitAlignment(unsigned NumBits, const GlobalObject *GO=nullptr) const
Emit an alignment directive to the specified power of two boundary.
MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol address.
Definition: MipsBaseInfo.h:52
const MipsABIInfo & getABI() const
void emitXRayTable()
Emit a table with all XRay instrumentation points.
virtual void emitDirectiveModuleOddSPReg()
virtual void AddComment(const Twine &T, bool EOL=true)
Add a textual comment.
Definition: MCStreamer.h:303
bool runOnMachineFunction(MachineFunction &MF) override
Emit the specified function out to the OutStreamer.
Definition: AsmPrinter.h:288
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:544
bool isPositionIndependent() const
Definition: AsmPrinter.cpp:199
virtual void EmitBasicBlockEnd(const MachineBasicBlock &MBB)
Targets can override this to emit stuff at the end of a basic block.
Target & getTheMips64Target()
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant...
void printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O)
bool isLittleEndian() const
Layout endianness...
Definition: DataLayout.h:221
RegisterAsmPrinter - Helper template for registering a target specific assembly printer, for use in the target machine initialization function.
This class is a data container for one entry in a MachineConstantPool.
StringRef getTargetCPU() const
void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS)
void EmitEndOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the end of their file...
const std::string & str() const
Definition: Triple.h:352
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
bool isTargetNaCl() const
MO_GPREL - Represents the offset from the current gp value to be used for the relocatable object file...
Definition: MipsBaseInfo.h:48
MCContext & getContext() const
Address of a global value.
Streaming machine code generation interface.
Definition: MCStreamer.h:183
MO_GOT_CALL - Represents the offset into the global offset table at which the address of a call site ...
Definition: MipsBaseInfo.h:44
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
Definition: MCContext.cpp:217
Target & getTheMips64elTarget()
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
MCSymbol * CurrentFnSym
The symbol for the current function.
Definition: AsmPrinter.h:112
LLVM Basic Block Representation.
Definition: BasicBlock.h:59
const MCAsmInfo * MAI
Target Asm Printer information.
Definition: AsmPrinter.h:84
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
virtual void emitDirectiveSetNoMicroMips()
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
virtual void emitDirectiveSetMips16()
virtual void SwitchSection(MCSection *Section, const MCExpr *Subsection=nullptr)
Set the current section where code is being emitted to Section.
Definition: MCStreamer.cpp:991
const GlobalValue * getGlobal() const
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant...
void EmitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:31
virtual void emitDirectiveSetMacro()
TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:81
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:336
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
Definition: MathExtras.h:432
void Lower(const MachineInstr *MI, MCInst &OutMI) const
virtual void EmitValueToAlignment(unsigned ByteAlignment, int64_t Value=0, unsigned ValueSize=1, unsigned MaxBytesToEmit=0)
Emit some number of copies of Value until the byte alignment ByteAlignment is reached.
Definition: MCStreamer.cpp:979
virtual bool EmitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute)=0
Add the given Attribute to Symbol.
Address of a basic block.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MCObjectFileInfo * getObjectFileInfo() const
Definition: MCContext.h:294
const Triple & getTargetTriple() const
StringRef selectMipsCPU(const Triple &TT, StringRef CPU)
Select the Mips CPU for the given triple and cpu name.
bool IsO32() const
Definition: MipsABIInfo.h:42
self_iterator getIterator()
Definition: ilist_node.h:82
virtual void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff)
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
bool runOnMachineFunction(MachineFunction &MF) override
Emit the specified function out to the OutStreamer.
const Target & getTarget() const
MipsMCInstLower MCInstLowering
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual MCSymbol * GetCPISymbol(unsigned CPID) const
Return the symbol for the specified constant pool entry.
bool hasMips64r6() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MO_GOTTPREL - Represents the offset from the thread pointer (Initial.
Definition: MipsBaseInfo.h:69
virtual void EmitDataRegion(MCDataRegionType Kind)
Note in the output the specified region Kind.
Definition: MCStreamer.h:443
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
const std::vector< MachineConstantPoolEntry > & getConstants() const
unsigned getFunctionNumber() const
Return a unique ID for the current function.
Definition: AsmPrinter.cpp:204
virtual void emitDirectiveAbiCalls()
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
Definition: MipsBaseInfo.h:38
Iterator for intrusive lists based on ilist_node.
void setOpcode(unsigned Op)
Definition: MCInst.h:173
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
bool isLittle() const
virtual void emitDirectiveOptionPic0()
MCSymbol * getSymbol(const GlobalValue *GV) const
Definition: AsmPrinter.cpp:426
bool isDebugValue() const
Definition: MachineInstr.h:849
MachineOperand class - Representation of each machine instruction operand.
virtual void EmitCodeAlignment(unsigned ByteAlignment, unsigned MaxBytesToEmit=0)
Emit nops until the byte alignment ByteAlignment is reached.
Definition: MCStreamer.cpp:982
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
Definition: AsmPrinter.cpp:227
static Twine utohexstr(const uint64_t &Val)
Definition: Twine.h:385
virtual void emitDirectiveSetNoMips16()
int64_t getImm() const
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
const Function & getFunction() const
Return the LLVM function that this machine code represents.
void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O, const char *Modifier=nullptr)
void EmitStartOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the start of their fi...
const char * MipsFCCToString(Mips::CondCode CC)
Target - Wrapper for Target specific information.
Target & getTheMipsTarget()
MCSubtargetInfo * createMCSubtargetInfo(StringRef TheTriple, StringRef CPU, StringRef Features) const
createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
MO_TPREL_HI/LO - Represents the hi and low part of the offset from.
Definition: MipsBaseInfo.h:73
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:156
static const unsigned MIPS_NACL_BUNDLE_ALIGN
Definition: MipsMCNaCl.h:18
virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV)
const char * getCurrentABIString() const
Emit Set directives.
virtual void setPic(bool Value)
void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O)
Representation of each machine instruction.
Definition: MachineInstr.h:60
void updateABIInfo(const PredicateLibrary &P)
virtual void emitDirectiveEnt(const MCSymbol &Symbol)
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
const MipsSubtarget * Subtarget
.type _foo,
Definition: MCDirectives.h:30
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:123
bool isEHPad() const
Returns true if the block is a landing pad.
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
void EmitDebugThreadLocal(const MCExpr *Value, unsigned Size) const override
Emit the directive and value for debug thread local expression.
.type _foo, STT_FUNC # aka
Definition: MCDirectives.h:23
int64_t getOffset() const
Return the offset from the symbol in this operand.
const BlockAddress * getBlockAddress() const
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
#define I(x, y, z)
Definition: MD5.cpp:58
virtual void EmitDTPRel32Value(const MCExpr *Value)
Emit the expression Value into the output as a dtprel (32-bit DTP relative) value.
Definition: MCStreamer.cpp:162
Generic base class for all target subtargets.
void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O)
virtual void emitELFSize(MCSymbol *Symbol, const MCExpr *Value)
Emit an ELF .size directive.
Definition: MCStreamer.cpp:960
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI)
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:124
This represents a section on linux, lots of unix variants and some bare metal systems.
Definition: MCSectionELF.h:28
MCOperand LowerOperand(const MachineOperand &MO, unsigned offset=0) const
unsigned getRARegister() const
This method should return the register where the return address can be found.
void printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:203
LLVM_NODISCARD std::string lower() const
Definition: StringRef.cpp:108
MCSection * getTextSection() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool PopSection()
Restore the current and previous section from the section stack.
Definition: MCStreamer.h:368
MCSectionELF * getELFSection(const Twine &Section, unsigned Type, unsigned Flags)
Definition: MCContext.h:390
virtual void emitDirectiveSetReorder()
static const char * getRegisterName(unsigned RegNo)
void EmitGlobalConstant(const DataLayout &DL, const Constant *CV)
Print a general LLVM constant to the .s file.
LLVM Value Representation.
Definition: Value.h:73
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
virtual void emitDirectiveNaNLegacy()
virtual void EmitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:322
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
const DataLayout & getDataLayout() const
Return information about data layout.
Definition: AsmPrinter.cpp:212
const MipsFunctionInfo * MipsFI
IRTranslator LLVM IR MI
void emitFrameDirective()
Frame Directive.
void addOperand(const MCOperand &Op)
Definition: MCInst.h:186
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
bool isValid() const
Definition: MCInst.h:57
void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI)
Address of indexed Constant in Constant Pool.
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...
bool isPositionIndependent() const
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
void EmitBasicBlockEnd(const MachineBasicBlock &MBB) override
Targets can override this to emit stuff at the end of a basic block.
void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
const MachineJumpTableInfo * getJumpTableInfo() const
getJumpTableInfo - Return the jump table info object for the current function.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:316
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
unsigned Log2_64(uint64_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:543
.end_data_region
Definition: MCDirectives.h:61
void print(raw_ostream &OS, const MCAsmInfo *MAI) const
print - Print the value to the stream OS.
Definition: MCSymbol.cpp:60