LLVM  8.0.0svn
HexagonBitTracker.cpp
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1 //===- HexagonBitTracker.cpp ----------------------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "HexagonBitTracker.h"
11 #include "Hexagon.h"
12 #include "HexagonInstrInfo.h"
13 #include "HexagonRegisterInfo.h"
14 #include "HexagonSubtarget.h"
21 #include "llvm/IR/Argument.h"
22 #include "llvm/IR/Attributes.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/IR/Type.h"
25 #include "llvm/Support/Compiler.h"
26 #include "llvm/Support/Debug.h"
30 #include <cassert>
31 #include <cstddef>
32 #include <cstdint>
33 #include <cstdlib>
34 #include <utility>
35 #include <vector>
36 
37 using namespace llvm;
38 
39 using BT = BitTracker;
40 
43  const HexagonInstrInfo &tii,
44  MachineFunction &mf)
45  : MachineEvaluator(tri, mri), MF(mf), MFI(mf.getFrameInfo()), TII(tii) {
46  // Populate the VRX map (VR to extension-type).
47  // Go over all the formal parameters of the function. If a given parameter
48  // P is sign- or zero-extended, locate the virtual register holding that
49  // parameter and create an entry in the VRX map indicating the type of ex-
50  // tension (and the source type).
51  // This is a bit complicated to do accurately, since the memory layout in-
52  // formation is necessary to precisely determine whether an aggregate para-
53  // meter will be passed in a register or in memory. What is given in MRI
54  // is the association between the physical register that is live-in (i.e.
55  // holds an argument), and the virtual register that this value will be
56  // copied into. This, by itself, is not sufficient to map back the virtual
57  // register to a formal parameter from Function (since consecutive live-ins
58  // from MRI may not correspond to consecutive formal parameters from Func-
59  // tion). To avoid the complications with in-memory arguments, only consi-
60  // der the initial sequence of formal parameters that are known to be
61  // passed via registers.
62  unsigned InVirtReg, InPhysReg = 0;
63 
64  for (const Argument &Arg : MF.getFunction().args()) {
65  Type *ATy = Arg.getType();
66  unsigned Width = 0;
67  if (ATy->isIntegerTy())
68  Width = ATy->getIntegerBitWidth();
69  else if (ATy->isPointerTy())
70  Width = 32;
71  // If pointer size is not set through target data, it will default to
72  // Module::AnyPointerSize.
73  if (Width == 0 || Width > 64)
74  break;
75  if (Arg.hasAttribute(Attribute::ByVal))
76  continue;
77  InPhysReg = getNextPhysReg(InPhysReg, Width);
78  if (!InPhysReg)
79  break;
80  InVirtReg = getVirtRegFor(InPhysReg);
81  if (!InVirtReg)
82  continue;
83  if (Arg.hasAttribute(Attribute::SExt))
84  VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::SExt, Width)));
85  else if (Arg.hasAttribute(Attribute::ZExt))
86  VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::ZExt, Width)));
87  }
88 }
89 
90 BT::BitMask HexagonEvaluator::mask(unsigned Reg, unsigned Sub) const {
91  if (Sub == 0)
92  return MachineEvaluator::mask(Reg, 0);
93  const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
94  unsigned ID = RC.getID();
95  uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub));
96  auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI);
97  bool IsSubLo = (Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo));
98  switch (ID) {
99  case Hexagon::DoubleRegsRegClassID:
100  case Hexagon::HvxWRRegClassID:
101  return IsSubLo ? BT::BitMask(0, RW-1)
102  : BT::BitMask(RW, 2*RW-1);
103  default:
104  break;
105  }
106 #ifndef NDEBUG
107  dbgs() << printReg(Reg, &TRI, Sub) << " in reg class "
108  << TRI.getRegClassName(&RC) << '\n';
109 #endif
110  llvm_unreachable("Unexpected register/subregister");
111 }
112 
113 uint16_t HexagonEvaluator::getPhysRegBitWidth(unsigned Reg) const {
115 
116  using namespace Hexagon;
117  for (auto &RC : {HvxVRRegClass, HvxWRRegClass, HvxQRRegClass})
118  if (RC.contains(Reg))
119  return TRI.getRegSizeInBits(RC);
120  // Default treatment for other physical registers.
121  if (const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg))
122  return TRI.getRegSizeInBits(*RC);
123 
125  (Twine("Unhandled physical register") + TRI.getName(Reg)).str().c_str());
126 }
127 
129  const TargetRegisterClass &RC, unsigned Idx) const {
130  if (Idx == 0)
131  return RC;
132 
133 #ifndef NDEBUG
134  const auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI);
135  bool IsSubLo = (Idx == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo));
136  bool IsSubHi = (Idx == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi));
137  assert(IsSubLo != IsSubHi && "Must refer to either low or high subreg");
138 #endif
139 
140  switch (RC.getID()) {
141  case Hexagon::DoubleRegsRegClassID:
142  return Hexagon::IntRegsRegClass;
143  case Hexagon::HvxWRRegClassID:
144  return Hexagon::HvxVRRegClass;
145  default:
146  break;
147  }
148 #ifndef NDEBUG
149  dbgs() << "Reg class id: " << RC.getID() << " idx: " << Idx << '\n';
150 #endif
151  llvm_unreachable("Unimplemented combination of reg class/subreg idx");
152 }
153 
154 namespace {
155 
156 class RegisterRefs {
157  std::vector<BT::RegisterRef> Vector;
158 
159 public:
160  RegisterRefs(const MachineInstr &MI) : Vector(MI.getNumOperands()) {
161  for (unsigned i = 0, n = Vector.size(); i < n; ++i) {
162  const MachineOperand &MO = MI.getOperand(i);
163  if (MO.isReg())
164  Vector[i] = BT::RegisterRef(MO);
165  // For indices that don't correspond to registers, the entry will
166  // remain constructed via the default constructor.
167  }
168  }
169 
170  size_t size() const { return Vector.size(); }
171 
172  const BT::RegisterRef &operator[](unsigned n) const {
173  // The main purpose of this operator is to assert with bad argument.
174  assert(n < Vector.size());
175  return Vector[n];
176  }
177 };
178 
179 } // end anonymous namespace
180 
182  const CellMapType &Inputs,
183  CellMapType &Outputs) const {
184  using namespace Hexagon;
185 
186  unsigned NumDefs = 0;
187 
188  // Sanity verification: there should not be any defs with subregisters.
189  for (const MachineOperand &MO : MI.operands()) {
190  if (!MO.isReg() || !MO.isDef())
191  continue;
192  NumDefs++;
193  assert(MO.getSubReg() == 0);
194  }
195 
196  if (NumDefs == 0)
197  return false;
198 
199  unsigned Opc = MI.getOpcode();
200 
201  if (MI.mayLoad()) {
202  switch (Opc) {
203  // These instructions may be marked as mayLoad, but they are generating
204  // immediate values, so skip them.
205  case CONST32:
206  case CONST64:
207  break;
208  default:
209  return evaluateLoad(MI, Inputs, Outputs);
210  }
211  }
212 
213  // Check COPY instructions that copy formal parameters into virtual
214  // registers. Such parameters can be sign- or zero-extended at the
215  // call site, and we should take advantage of this knowledge. The MRI
216  // keeps a list of pairs of live-in physical and virtual registers,
217  // which provides information about which virtual registers will hold
218  // the argument values. The function will still contain instructions
219  // defining those virtual registers, and in practice those are COPY
220  // instructions from a physical to a virtual register. In such cases,
221  // applying the argument extension to the virtual register can be seen
222  // as simply mirroring the extension that had already been applied to
223  // the physical register at the call site. If the defining instruction
224  // was not a COPY, it would not be clear how to mirror that extension
225  // on the callee's side. For that reason, only check COPY instructions
226  // for potential extensions.
227  if (MI.isCopy()) {
228  if (evaluateFormalCopy(MI, Inputs, Outputs))
229  return true;
230  }
231 
232  // Beyond this point, if any operand is a global, skip that instruction.
233  // The reason is that certain instructions that can take an immediate
234  // operand can also have a global symbol in that operand. To avoid
235  // checking what kind of operand a given instruction has individually
236  // for each instruction, do it here. Global symbols as operands gene-
237  // rally do not provide any useful information.
238  for (const MachineOperand &MO : MI.operands()) {
239  if (MO.isGlobal() || MO.isBlockAddress() || MO.isSymbol() || MO.isJTI() ||
240  MO.isCPI())
241  return false;
242  }
243 
244  RegisterRefs Reg(MI);
245 #define op(i) MI.getOperand(i)
246 #define rc(i) RegisterCell::ref(getCell(Reg[i], Inputs))
247 #define im(i) MI.getOperand(i).getImm()
248 
249  // If the instruction has no register operands, skip it.
250  if (Reg.size() == 0)
251  return false;
252 
253  // Record result for register in operand 0.
254  auto rr0 = [this,Reg] (const BT::RegisterCell &Val, CellMapType &Outputs)
255  -> bool {
256  putCell(Reg[0], Val, Outputs);
257  return true;
258  };
259  // Get the cell corresponding to the N-th operand.
260  auto cop = [this, &Reg, &MI, &Inputs](unsigned N,
261  uint16_t W) -> BT::RegisterCell {
262  const MachineOperand &Op = MI.getOperand(N);
263  if (Op.isImm())
264  return eIMM(Op.getImm(), W);
265  if (!Op.isReg())
266  return RegisterCell::self(0, W);
267  assert(getRegBitWidth(Reg[N]) == W && "Register width mismatch");
268  return rc(N);
269  };
270  // Extract RW low bits of the cell.
271  auto lo = [this] (const BT::RegisterCell &RC, uint16_t RW)
272  -> BT::RegisterCell {
273  assert(RW <= RC.width());
274  return eXTR(RC, 0, RW);
275  };
276  // Extract RW high bits of the cell.
277  auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW)
278  -> BT::RegisterCell {
279  uint16_t W = RC.width();
280  assert(RW <= W);
281  return eXTR(RC, W-RW, W);
282  };
283  // Extract N-th halfword (counting from the least significant position).
284  auto half = [this] (const BT::RegisterCell &RC, unsigned N)
285  -> BT::RegisterCell {
286  assert(N*16+16 <= RC.width());
287  return eXTR(RC, N*16, N*16+16);
288  };
289  // Shuffle bits (pick even/odd from cells and merge into result).
290  auto shuffle = [this] (const BT::RegisterCell &Rs, const BT::RegisterCell &Rt,
291  uint16_t BW, bool Odd) -> BT::RegisterCell {
292  uint16_t I = Odd, Ws = Rs.width();
293  assert(Ws == Rt.width());
294  RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW));
295  I += 2;
296  while (I*BW < Ws) {
297  RC.cat(eXTR(Rt, I*BW, I*BW+BW)).cat(eXTR(Rs, I*BW, I*BW+BW));
298  I += 2;
299  }
300  return RC;
301  };
302 
303  // The bitwidth of the 0th operand. In most (if not all) of the
304  // instructions below, the 0th operand is the defined register.
305  // Pre-compute the bitwidth here, because it is needed in many cases
306  // cases below.
307  uint16_t W0 = (Reg[0].Reg != 0) ? getRegBitWidth(Reg[0]) : 0;
308 
309  // Register id of the 0th operand. It can be 0.
310  unsigned Reg0 = Reg[0].Reg;
311 
312  switch (Opc) {
313  // Transfer immediate:
314 
315  case A2_tfrsi:
316  case A2_tfrpi:
317  case CONST32:
318  case CONST64:
319  return rr0(eIMM(im(1), W0), Outputs);
320  case PS_false:
321  return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::Zero), Outputs);
322  case PS_true:
323  return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::One), Outputs);
324  case PS_fi: {
325  int FI = op(1).getIndex();
326  int Off = op(2).getImm();
327  unsigned A = MFI.getObjectAlignment(FI) + std::abs(Off);
328  unsigned L = countTrailingZeros(A);
329  RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0);
330  RC.fill(0, L, BT::BitValue::Zero);
331  return rr0(RC, Outputs);
332  }
333 
334  // Transfer register:
335 
336  case A2_tfr:
337  case A2_tfrp:
338  case C2_pxfer_map:
339  return rr0(rc(1), Outputs);
340  case C2_tfrpr: {
341  uint16_t RW = W0;
342  uint16_t PW = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
343  assert(PW <= RW);
344  RegisterCell PC = eXTR(rc(1), 0, PW);
345  RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1));
346  RC.fill(PW, RW, BT::BitValue::Zero);
347  return rr0(RC, Outputs);
348  }
349  case C2_tfrrp: {
350  uint16_t RW = W0;
351  uint16_t PW = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
352  RegisterCell RC = RegisterCell::self(Reg[0].Reg, RW);
353  RC.fill(PW, RW, BT::BitValue::Zero);
354  return rr0(eINS(RC, eXTR(rc(1), 0, PW), 0), Outputs);
355  }
356 
357  // Arithmetic:
358 
359  case A2_abs:
360  case A2_absp:
361  // TODO
362  break;
363 
364  case A2_addsp: {
365  uint16_t W1 = getRegBitWidth(Reg[1]);
366  assert(W0 == 64 && W1 == 32);
367  RegisterCell CW = RegisterCell(W0).insert(rc(1), BT::BitMask(0, W1-1));
368  RegisterCell RC = eADD(eSXT(CW, W1), rc(2));
369  return rr0(RC, Outputs);
370  }
371  case A2_add:
372  case A2_addp:
373  return rr0(eADD(rc(1), rc(2)), Outputs);
374  case A2_addi:
375  return rr0(eADD(rc(1), eIMM(im(2), W0)), Outputs);
376  case S4_addi_asl_ri: {
377  RegisterCell RC = eADD(eIMM(im(1), W0), eASL(rc(2), im(3)));
378  return rr0(RC, Outputs);
379  }
380  case S4_addi_lsr_ri: {
381  RegisterCell RC = eADD(eIMM(im(1), W0), eLSR(rc(2), im(3)));
382  return rr0(RC, Outputs);
383  }
384  case S4_addaddi: {
385  RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0)));
386  return rr0(RC, Outputs);
387  }
388  case M4_mpyri_addi: {
389  RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
390  RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0));
391  return rr0(RC, Outputs);
392  }
393  case M4_mpyrr_addi: {
394  RegisterCell M = eMLS(rc(2), rc(3));
395  RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0));
396  return rr0(RC, Outputs);
397  }
398  case M4_mpyri_addr_u2: {
399  RegisterCell M = eMLS(eIMM(im(2), W0), rc(3));
400  RegisterCell RC = eADD(rc(1), lo(M, W0));
401  return rr0(RC, Outputs);
402  }
403  case M4_mpyri_addr: {
404  RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
405  RegisterCell RC = eADD(rc(1), lo(M, W0));
406  return rr0(RC, Outputs);
407  }
408  case M4_mpyrr_addr: {
409  RegisterCell M = eMLS(rc(2), rc(3));
410  RegisterCell RC = eADD(rc(1), lo(M, W0));
411  return rr0(RC, Outputs);
412  }
413  case S4_subaddi: {
414  RegisterCell RC = eADD(rc(1), eSUB(eIMM(im(2), W0), rc(3)));
415  return rr0(RC, Outputs);
416  }
417  case M2_accii: {
418  RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0)));
419  return rr0(RC, Outputs);
420  }
421  case M2_acci: {
422  RegisterCell RC = eADD(rc(1), eADD(rc(2), rc(3)));
423  return rr0(RC, Outputs);
424  }
425  case M2_subacc: {
426  RegisterCell RC = eADD(rc(1), eSUB(rc(2), rc(3)));
427  return rr0(RC, Outputs);
428  }
429  case S2_addasl_rrri: {
430  RegisterCell RC = eADD(rc(1), eASL(rc(2), im(3)));
431  return rr0(RC, Outputs);
432  }
433  case C4_addipc: {
434  RegisterCell RPC = RegisterCell::self(Reg[0].Reg, W0);
435  RPC.fill(0, 2, BT::BitValue::Zero);
436  return rr0(eADD(RPC, eIMM(im(2), W0)), Outputs);
437  }
438  case A2_sub:
439  case A2_subp:
440  return rr0(eSUB(rc(1), rc(2)), Outputs);
441  case A2_subri:
442  return rr0(eSUB(eIMM(im(1), W0), rc(2)), Outputs);
443  case S4_subi_asl_ri: {
444  RegisterCell RC = eSUB(eIMM(im(1), W0), eASL(rc(2), im(3)));
445  return rr0(RC, Outputs);
446  }
447  case S4_subi_lsr_ri: {
448  RegisterCell RC = eSUB(eIMM(im(1), W0), eLSR(rc(2), im(3)));
449  return rr0(RC, Outputs);
450  }
451  case M2_naccii: {
452  RegisterCell RC = eSUB(rc(1), eADD(rc(2), eIMM(im(3), W0)));
453  return rr0(RC, Outputs);
454  }
455  case M2_nacci: {
456  RegisterCell RC = eSUB(rc(1), eADD(rc(2), rc(3)));
457  return rr0(RC, Outputs);
458  }
459  // 32-bit negation is done by "Rd = A2_subri 0, Rs"
460  case A2_negp:
461  return rr0(eSUB(eIMM(0, W0), rc(1)), Outputs);
462 
463  case M2_mpy_up: {
464  RegisterCell M = eMLS(rc(1), rc(2));
465  return rr0(hi(M, W0), Outputs);
466  }
467  case M2_dpmpyss_s0:
468  return rr0(eMLS(rc(1), rc(2)), Outputs);
469  case M2_dpmpyss_acc_s0:
470  return rr0(eADD(rc(1), eMLS(rc(2), rc(3))), Outputs);
471  case M2_dpmpyss_nac_s0:
472  return rr0(eSUB(rc(1), eMLS(rc(2), rc(3))), Outputs);
473  case M2_mpyi: {
474  RegisterCell M = eMLS(rc(1), rc(2));
475  return rr0(lo(M, W0), Outputs);
476  }
477  case M2_macsip: {
478  RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
479  RegisterCell RC = eADD(rc(1), lo(M, W0));
480  return rr0(RC, Outputs);
481  }
482  case M2_macsin: {
483  RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
484  RegisterCell RC = eSUB(rc(1), lo(M, W0));
485  return rr0(RC, Outputs);
486  }
487  case M2_maci: {
488  RegisterCell M = eMLS(rc(2), rc(3));
489  RegisterCell RC = eADD(rc(1), lo(M, W0));
490  return rr0(RC, Outputs);
491  }
492  case M2_mpysmi: {
493  RegisterCell M = eMLS(rc(1), eIMM(im(2), W0));
494  return rr0(lo(M, 32), Outputs);
495  }
496  case M2_mpysin: {
497  RegisterCell M = eMLS(rc(1), eIMM(-im(2), W0));
498  return rr0(lo(M, 32), Outputs);
499  }
500  case M2_mpysip: {
501  RegisterCell M = eMLS(rc(1), eIMM(im(2), W0));
502  return rr0(lo(M, 32), Outputs);
503  }
504  case M2_mpyu_up: {
505  RegisterCell M = eMLU(rc(1), rc(2));
506  return rr0(hi(M, W0), Outputs);
507  }
508  case M2_dpmpyuu_s0:
509  return rr0(eMLU(rc(1), rc(2)), Outputs);
510  case M2_dpmpyuu_acc_s0:
511  return rr0(eADD(rc(1), eMLU(rc(2), rc(3))), Outputs);
512  case M2_dpmpyuu_nac_s0:
513  return rr0(eSUB(rc(1), eMLU(rc(2), rc(3))), Outputs);
514  //case M2_mpysu_up:
515 
516  // Logical/bitwise:
517 
518  case A2_andir:
519  return rr0(eAND(rc(1), eIMM(im(2), W0)), Outputs);
520  case A2_and:
521  case A2_andp:
522  return rr0(eAND(rc(1), rc(2)), Outputs);
523  case A4_andn:
524  case A4_andnp:
525  return rr0(eAND(rc(1), eNOT(rc(2))), Outputs);
526  case S4_andi_asl_ri: {
527  RegisterCell RC = eAND(eIMM(im(1), W0), eASL(rc(2), im(3)));
528  return rr0(RC, Outputs);
529  }
530  case S4_andi_lsr_ri: {
531  RegisterCell RC = eAND(eIMM(im(1), W0), eLSR(rc(2), im(3)));
532  return rr0(RC, Outputs);
533  }
534  case M4_and_and:
535  return rr0(eAND(rc(1), eAND(rc(2), rc(3))), Outputs);
536  case M4_and_andn:
537  return rr0(eAND(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
538  case M4_and_or:
539  return rr0(eAND(rc(1), eORL(rc(2), rc(3))), Outputs);
540  case M4_and_xor:
541  return rr0(eAND(rc(1), eXOR(rc(2), rc(3))), Outputs);
542  case A2_orir:
543  return rr0(eORL(rc(1), eIMM(im(2), W0)), Outputs);
544  case A2_or:
545  case A2_orp:
546  return rr0(eORL(rc(1), rc(2)), Outputs);
547  case A4_orn:
548  case A4_ornp:
549  return rr0(eORL(rc(1), eNOT(rc(2))), Outputs);
550  case S4_ori_asl_ri: {
551  RegisterCell RC = eORL(eIMM(im(1), W0), eASL(rc(2), im(3)));
552  return rr0(RC, Outputs);
553  }
554  case S4_ori_lsr_ri: {
555  RegisterCell RC = eORL(eIMM(im(1), W0), eLSR(rc(2), im(3)));
556  return rr0(RC, Outputs);
557  }
558  case M4_or_and:
559  return rr0(eORL(rc(1), eAND(rc(2), rc(3))), Outputs);
560  case M4_or_andn:
561  return rr0(eORL(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
562  case S4_or_andi:
563  case S4_or_andix: {
564  RegisterCell RC = eORL(rc(1), eAND(rc(2), eIMM(im(3), W0)));
565  return rr0(RC, Outputs);
566  }
567  case S4_or_ori: {
568  RegisterCell RC = eORL(rc(1), eORL(rc(2), eIMM(im(3), W0)));
569  return rr0(RC, Outputs);
570  }
571  case M4_or_or:
572  return rr0(eORL(rc(1), eORL(rc(2), rc(3))), Outputs);
573  case M4_or_xor:
574  return rr0(eORL(rc(1), eXOR(rc(2), rc(3))), Outputs);
575  case A2_xor:
576  case A2_xorp:
577  return rr0(eXOR(rc(1), rc(2)), Outputs);
578  case M4_xor_and:
579  return rr0(eXOR(rc(1), eAND(rc(2), rc(3))), Outputs);
580  case M4_xor_andn:
581  return rr0(eXOR(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
582  case M4_xor_or:
583  return rr0(eXOR(rc(1), eORL(rc(2), rc(3))), Outputs);
584  case M4_xor_xacc:
585  return rr0(eXOR(rc(1), eXOR(rc(2), rc(3))), Outputs);
586  case A2_not:
587  case A2_notp:
588  return rr0(eNOT(rc(1)), Outputs);
589 
590  case S2_asl_i_r:
591  case S2_asl_i_p:
592  return rr0(eASL(rc(1), im(2)), Outputs);
593  case A2_aslh:
594  return rr0(eASL(rc(1), 16), Outputs);
595  case S2_asl_i_r_acc:
596  case S2_asl_i_p_acc:
597  return rr0(eADD(rc(1), eASL(rc(2), im(3))), Outputs);
598  case S2_asl_i_r_nac:
599  case S2_asl_i_p_nac:
600  return rr0(eSUB(rc(1), eASL(rc(2), im(3))), Outputs);
601  case S2_asl_i_r_and:
602  case S2_asl_i_p_and:
603  return rr0(eAND(rc(1), eASL(rc(2), im(3))), Outputs);
604  case S2_asl_i_r_or:
605  case S2_asl_i_p_or:
606  return rr0(eORL(rc(1), eASL(rc(2), im(3))), Outputs);
607  case S2_asl_i_r_xacc:
608  case S2_asl_i_p_xacc:
609  return rr0(eXOR(rc(1), eASL(rc(2), im(3))), Outputs);
610  case S2_asl_i_vh:
611  case S2_asl_i_vw:
612  // TODO
613  break;
614 
615  case S2_asr_i_r:
616  case S2_asr_i_p:
617  return rr0(eASR(rc(1), im(2)), Outputs);
618  case A2_asrh:
619  return rr0(eASR(rc(1), 16), Outputs);
620  case S2_asr_i_r_acc:
621  case S2_asr_i_p_acc:
622  return rr0(eADD(rc(1), eASR(rc(2), im(3))), Outputs);
623  case S2_asr_i_r_nac:
624  case S2_asr_i_p_nac:
625  return rr0(eSUB(rc(1), eASR(rc(2), im(3))), Outputs);
626  case S2_asr_i_r_and:
627  case S2_asr_i_p_and:
628  return rr0(eAND(rc(1), eASR(rc(2), im(3))), Outputs);
629  case S2_asr_i_r_or:
630  case S2_asr_i_p_or:
631  return rr0(eORL(rc(1), eASR(rc(2), im(3))), Outputs);
632  case S2_asr_i_r_rnd: {
633  // The input is first sign-extended to 64 bits, then the output
634  // is truncated back to 32 bits.
635  assert(W0 == 32);
636  RegisterCell XC = eSXT(rc(1).cat(eIMM(0, W0)), W0);
637  RegisterCell RC = eASR(eADD(eASR(XC, im(2)), eIMM(1, 2*W0)), 1);
638  return rr0(eXTR(RC, 0, W0), Outputs);
639  }
640  case S2_asr_i_r_rnd_goodsyntax: {
641  int64_t S = im(2);
642  if (S == 0)
643  return rr0(rc(1), Outputs);
644  // Result: S2_asr_i_r_rnd Rs, u5-1
645  RegisterCell XC = eSXT(rc(1).cat(eIMM(0, W0)), W0);
646  RegisterCell RC = eLSR(eADD(eASR(XC, S-1), eIMM(1, 2*W0)), 1);
647  return rr0(eXTR(RC, 0, W0), Outputs);
648  }
649  case S2_asr_r_vh:
650  case S2_asr_i_vw:
651  case S2_asr_i_svw_trun:
652  // TODO
653  break;
654 
655  case S2_lsr_i_r:
656  case S2_lsr_i_p:
657  return rr0(eLSR(rc(1), im(2)), Outputs);
658  case S2_lsr_i_r_acc:
659  case S2_lsr_i_p_acc:
660  return rr0(eADD(rc(1), eLSR(rc(2), im(3))), Outputs);
661  case S2_lsr_i_r_nac:
662  case S2_lsr_i_p_nac:
663  return rr0(eSUB(rc(1), eLSR(rc(2), im(3))), Outputs);
664  case S2_lsr_i_r_and:
665  case S2_lsr_i_p_and:
666  return rr0(eAND(rc(1), eLSR(rc(2), im(3))), Outputs);
667  case S2_lsr_i_r_or:
668  case S2_lsr_i_p_or:
669  return rr0(eORL(rc(1), eLSR(rc(2), im(3))), Outputs);
670  case S2_lsr_i_r_xacc:
671  case S2_lsr_i_p_xacc:
672  return rr0(eXOR(rc(1), eLSR(rc(2), im(3))), Outputs);
673 
674  case S2_clrbit_i: {
675  RegisterCell RC = rc(1);
676  RC[im(2)] = BT::BitValue::Zero;
677  return rr0(RC, Outputs);
678  }
679  case S2_setbit_i: {
680  RegisterCell RC = rc(1);
681  RC[im(2)] = BT::BitValue::One;
682  return rr0(RC, Outputs);
683  }
684  case S2_togglebit_i: {
685  RegisterCell RC = rc(1);
686  uint16_t BX = im(2);
687  RC[BX] = RC[BX].is(0) ? BT::BitValue::One
688  : RC[BX].is(1) ? BT::BitValue::Zero
689  : BT::BitValue::self();
690  return rr0(RC, Outputs);
691  }
692 
693  case A4_bitspliti: {
694  uint16_t W1 = getRegBitWidth(Reg[1]);
695  uint16_t BX = im(2);
696  // Res.uw[1] = Rs[bx+1:], Res.uw[0] = Rs[0:bx]
697  const BT::BitValue Zero = BT::BitValue::Zero;
698  RegisterCell RZ = RegisterCell(W0).fill(BX, W1, Zero)
699  .fill(W1+(W1-BX), W0, Zero);
700  RegisterCell BF1 = eXTR(rc(1), 0, BX), BF2 = eXTR(rc(1), BX, W1);
701  RegisterCell RC = eINS(eINS(RZ, BF1, 0), BF2, W1);
702  return rr0(RC, Outputs);
703  }
704  case S4_extract:
705  case S4_extractp:
706  case S2_extractu:
707  case S2_extractup: {
708  uint16_t Wd = im(2), Of = im(3);
709  assert(Wd <= W0);
710  if (Wd == 0)
711  return rr0(eIMM(0, W0), Outputs);
712  // If the width extends beyond the register size, pad the register
713  // with 0 bits.
714  RegisterCell Pad = (Wd+Of > W0) ? rc(1).cat(eIMM(0, Wd+Of-W0)) : rc(1);
715  RegisterCell Ext = eXTR(Pad, Of, Wd+Of);
716  // Ext is short, need to extend it with 0s or sign bit.
717  RegisterCell RC = RegisterCell(W0).insert(Ext, BT::BitMask(0, Wd-1));
718  if (Opc == S2_extractu || Opc == S2_extractup)
719  return rr0(eZXT(RC, Wd), Outputs);
720  return rr0(eSXT(RC, Wd), Outputs);
721  }
722  case S2_insert:
723  case S2_insertp: {
724  uint16_t Wd = im(3), Of = im(4);
725  assert(Wd < W0 && Of < W0);
726  // If Wd+Of exceeds W0, the inserted bits are truncated.
727  if (Wd+Of > W0)
728  Wd = W0-Of;
729  if (Wd == 0)
730  return rr0(rc(1), Outputs);
731  return rr0(eINS(rc(1), eXTR(rc(2), 0, Wd), Of), Outputs);
732  }
733 
734  // Bit permutations:
735 
736  case A2_combineii:
737  case A4_combineii:
738  case A4_combineir:
739  case A4_combineri:
740  case A2_combinew:
741  case V6_vcombine:
742  assert(W0 % 2 == 0);
743  return rr0(cop(2, W0/2).cat(cop(1, W0/2)), Outputs);
744  case A2_combine_ll:
745  case A2_combine_lh:
746  case A2_combine_hl:
747  case A2_combine_hh: {
748  assert(W0 == 32);
749  assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32);
750  // Low half in the output is 0 for _ll and _hl, 1 otherwise:
751  unsigned LoH = !(Opc == A2_combine_ll || Opc == A2_combine_hl);
752  // High half in the output is 0 for _ll and _lh, 1 otherwise:
753  unsigned HiH = !(Opc == A2_combine_ll || Opc == A2_combine_lh);
754  RegisterCell R1 = rc(1);
755  RegisterCell R2 = rc(2);
756  RegisterCell RC = half(R2, LoH).cat(half(R1, HiH));
757  return rr0(RC, Outputs);
758  }
759  case S2_packhl: {
760  assert(W0 == 64);
761  assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32);
762  RegisterCell R1 = rc(1);
763  RegisterCell R2 = rc(2);
764  RegisterCell RC = half(R2, 0).cat(half(R1, 0)).cat(half(R2, 1))
765  .cat(half(R1, 1));
766  return rr0(RC, Outputs);
767  }
768  case S2_shuffeb: {
769  RegisterCell RC = shuffle(rc(1), rc(2), 8, false);
770  return rr0(RC, Outputs);
771  }
772  case S2_shuffeh: {
773  RegisterCell RC = shuffle(rc(1), rc(2), 16, false);
774  return rr0(RC, Outputs);
775  }
776  case S2_shuffob: {
777  RegisterCell RC = shuffle(rc(1), rc(2), 8, true);
778  return rr0(RC, Outputs);
779  }
780  case S2_shuffoh: {
781  RegisterCell RC = shuffle(rc(1), rc(2), 16, true);
782  return rr0(RC, Outputs);
783  }
784  case C2_mask: {
785  uint16_t WR = W0;
786  uint16_t WP = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
787  assert(WR == 64 && WP == 8);
788  RegisterCell R1 = rc(1);
789  RegisterCell RC(WR);
790  for (uint16_t i = 0; i < WP; ++i) {
791  const BT::BitValue &V = R1[i];
792  BT::BitValue F = (V.is(0) || V.is(1)) ? V : BT::BitValue::self();
793  RC.fill(i*8, i*8+8, F);
794  }
795  return rr0(RC, Outputs);
796  }
797 
798  // Mux:
799 
800  case C2_muxii:
801  case C2_muxir:
802  case C2_muxri:
803  case C2_mux: {
804  BT::BitValue PC0 = rc(1)[0];
805  RegisterCell R2 = cop(2, W0);
806  RegisterCell R3 = cop(3, W0);
807  if (PC0.is(0) || PC0.is(1))
808  return rr0(RegisterCell::ref(PC0 ? R2 : R3), Outputs);
809  R2.meet(R3, Reg[0].Reg);
810  return rr0(R2, Outputs);
811  }
812  case C2_vmux:
813  // TODO
814  break;
815 
816  // Sign- and zero-extension:
817 
818  case A2_sxtb:
819  return rr0(eSXT(rc(1), 8), Outputs);
820  case A2_sxth:
821  return rr0(eSXT(rc(1), 16), Outputs);
822  case A2_sxtw: {
823  uint16_t W1 = getRegBitWidth(Reg[1]);
824  assert(W0 == 64 && W1 == 32);
825  RegisterCell RC = eSXT(rc(1).cat(eIMM(0, W1)), W1);
826  return rr0(RC, Outputs);
827  }
828  case A2_zxtb:
829  return rr0(eZXT(rc(1), 8), Outputs);
830  case A2_zxth:
831  return rr0(eZXT(rc(1), 16), Outputs);
832 
833  // Saturations
834 
835  case A2_satb:
836  return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs);
837  case A2_sath:
838  return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs);
839  case A2_satub:
840  return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs);
841  case A2_satuh:
842  return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs);
843 
844  // Bit count:
845 
846  case S2_cl0:
847  case S2_cl0p:
848  // Always produce a 32-bit result.
849  return rr0(eCLB(rc(1), false/*bit*/, 32), Outputs);
850  case S2_cl1:
851  case S2_cl1p:
852  return rr0(eCLB(rc(1), true/*bit*/, 32), Outputs);
853  case S2_clb:
854  case S2_clbp: {
855  uint16_t W1 = getRegBitWidth(Reg[1]);
856  RegisterCell R1 = rc(1);
857  BT::BitValue TV = R1[W1-1];
858  if (TV.is(0) || TV.is(1))
859  return rr0(eCLB(R1, TV, 32), Outputs);
860  break;
861  }
862  case S2_ct0:
863  case S2_ct0p:
864  return rr0(eCTB(rc(1), false/*bit*/, 32), Outputs);
865  case S2_ct1:
866  case S2_ct1p:
867  return rr0(eCTB(rc(1), true/*bit*/, 32), Outputs);
868  case S5_popcountp:
869  // TODO
870  break;
871 
872  case C2_all8: {
873  RegisterCell P1 = rc(1);
874  bool Has0 = false, All1 = true;
875  for (uint16_t i = 0; i < 8/*XXX*/; ++i) {
876  if (!P1[i].is(1))
877  All1 = false;
878  if (!P1[i].is(0))
879  continue;
880  Has0 = true;
881  break;
882  }
883  if (!Has0 && !All1)
884  break;
885  RegisterCell RC(W0);
886  RC.fill(0, W0, (All1 ? BT::BitValue::One : BT::BitValue::Zero));
887  return rr0(RC, Outputs);
888  }
889  case C2_any8: {
890  RegisterCell P1 = rc(1);
891  bool Has1 = false, All0 = true;
892  for (uint16_t i = 0; i < 8/*XXX*/; ++i) {
893  if (!P1[i].is(0))
894  All0 = false;
895  if (!P1[i].is(1))
896  continue;
897  Has1 = true;
898  break;
899  }
900  if (!Has1 && !All0)
901  break;
902  RegisterCell RC(W0);
903  RC.fill(0, W0, (Has1 ? BT::BitValue::One : BT::BitValue::Zero));
904  return rr0(RC, Outputs);
905  }
906  case C2_and:
907  return rr0(eAND(rc(1), rc(2)), Outputs);
908  case C2_andn:
909  return rr0(eAND(rc(1), eNOT(rc(2))), Outputs);
910  case C2_not:
911  return rr0(eNOT(rc(1)), Outputs);
912  case C2_or:
913  return rr0(eORL(rc(1), rc(2)), Outputs);
914  case C2_orn:
915  return rr0(eORL(rc(1), eNOT(rc(2))), Outputs);
916  case C2_xor:
917  return rr0(eXOR(rc(1), rc(2)), Outputs);
918  case C4_and_and:
919  return rr0(eAND(rc(1), eAND(rc(2), rc(3))), Outputs);
920  case C4_and_andn:
921  return rr0(eAND(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
922  case C4_and_or:
923  return rr0(eAND(rc(1), eORL(rc(2), rc(3))), Outputs);
924  case C4_and_orn:
925  return rr0(eAND(rc(1), eORL(rc(2), eNOT(rc(3)))), Outputs);
926  case C4_or_and:
927  return rr0(eORL(rc(1), eAND(rc(2), rc(3))), Outputs);
928  case C4_or_andn:
929  return rr0(eORL(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
930  case C4_or_or:
931  return rr0(eORL(rc(1), eORL(rc(2), rc(3))), Outputs);
932  case C4_or_orn:
933  return rr0(eORL(rc(1), eORL(rc(2), eNOT(rc(3)))), Outputs);
934  case C2_bitsclr:
935  case C2_bitsclri:
936  case C2_bitsset:
937  case C4_nbitsclr:
938  case C4_nbitsclri:
939  case C4_nbitsset:
940  // TODO
941  break;
942  case S2_tstbit_i:
943  case S4_ntstbit_i: {
944  BT::BitValue V = rc(1)[im(2)];
945  if (V.is(0) || V.is(1)) {
946  // If instruction is S2_tstbit_i, test for 1, otherwise test for 0.
947  bool TV = (Opc == S2_tstbit_i);
949  return rr0(RegisterCell(W0).fill(0, W0, F), Outputs);
950  }
951  break;
952  }
953 
954  default:
955  // For instructions that define a single predicate registers, store
956  // the low 8 bits of the register only.
957  if (unsigned DefR = getUniqueDefVReg(MI)) {
958  if (MRI.getRegClass(DefR) == &Hexagon::PredRegsRegClass) {
959  BT::RegisterRef PD(DefR, 0);
960  uint16_t RW = getRegBitWidth(PD);
961  uint16_t PW = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
962  RegisterCell RC = RegisterCell::self(DefR, RW);
963  RC.fill(PW, RW, BT::BitValue::Zero);
964  putCell(PD, RC, Outputs);
965  return true;
966  }
967  }
968  return MachineEvaluator::evaluate(MI, Inputs, Outputs);
969  }
970  #undef im
971  #undef rc
972  #undef op
973  return false;
974 }
975 
977  const CellMapType &Inputs,
978  BranchTargetList &Targets,
979  bool &FallsThru) const {
980  // We need to evaluate one branch at a time. TII::analyzeBranch checks
981  // all the branches in a basic block at once, so we cannot use it.
982  unsigned Opc = BI.getOpcode();
983  bool SimpleBranch = false;
984  bool Negated = false;
985  switch (Opc) {
986  case Hexagon::J2_jumpf:
987  case Hexagon::J2_jumpfpt:
988  case Hexagon::J2_jumpfnew:
989  case Hexagon::J2_jumpfnewpt:
990  Negated = true;
992  case Hexagon::J2_jumpt:
993  case Hexagon::J2_jumptpt:
994  case Hexagon::J2_jumptnew:
995  case Hexagon::J2_jumptnewpt:
996  // Simple branch: if([!]Pn) jump ...
997  // i.e. Op0 = predicate, Op1 = branch target.
998  SimpleBranch = true;
999  break;
1000  case Hexagon::J2_jump:
1001  Targets.insert(BI.getOperand(0).getMBB());
1002  FallsThru = false;
1003  return true;
1004  default:
1005  // If the branch is of unknown type, assume that all successors are
1006  // executable.
1007  return false;
1008  }
1009 
1010  if (!SimpleBranch)
1011  return false;
1012 
1013  // BI is a conditional branch if we got here.
1014  RegisterRef PR = BI.getOperand(0);
1015  RegisterCell PC = getCell(PR, Inputs);
1016  const BT::BitValue &Test = PC[0];
1017 
1018  // If the condition is neither true nor false, then it's unknown.
1019  if (!Test.is(0) && !Test.is(1))
1020  return false;
1021 
1022  // "Test.is(!Negated)" means "branch condition is true".
1023  if (!Test.is(!Negated)) {
1024  // Condition known to be false.
1025  FallsThru = true;
1026  return true;
1027  }
1028 
1029  Targets.insert(BI.getOperand(1).getMBB());
1030  FallsThru = false;
1031  return true;
1032 }
1033 
1034 unsigned HexagonEvaluator::getUniqueDefVReg(const MachineInstr &MI) const {
1035  unsigned DefReg = 0;
1036  for (const MachineOperand &Op : MI.operands()) {
1037  if (!Op.isReg() || !Op.isDef())
1038  continue;
1039  unsigned R = Op.getReg();
1041  continue;
1042  if (DefReg != 0)
1043  return 0;
1044  DefReg = R;
1045  }
1046  return DefReg;
1047 }
1048 
1049 bool HexagonEvaluator::evaluateLoad(const MachineInstr &MI,
1050  const CellMapType &Inputs,
1051  CellMapType &Outputs) const {
1052  using namespace Hexagon;
1053 
1054  if (TII.isPredicated(MI))
1055  return false;
1056  assert(MI.mayLoad() && "A load that mayn't?");
1057  unsigned Opc = MI.getOpcode();
1058 
1059  uint16_t BitNum;
1060  bool SignEx;
1061 
1062  switch (Opc) {
1063  default:
1064  return false;
1065 
1066 #if 0
1067  // memb_fifo
1068  case L2_loadalignb_pbr:
1069  case L2_loadalignb_pcr:
1070  case L2_loadalignb_pi:
1071  // memh_fifo
1072  case L2_loadalignh_pbr:
1073  case L2_loadalignh_pcr:
1074  case L2_loadalignh_pi:
1075  // membh
1076  case L2_loadbsw2_pbr:
1077  case L2_loadbsw2_pci:
1078  case L2_loadbsw2_pcr:
1079  case L2_loadbsw2_pi:
1080  case L2_loadbsw4_pbr:
1081  case L2_loadbsw4_pci:
1082  case L2_loadbsw4_pcr:
1083  case L2_loadbsw4_pi:
1084  // memubh
1085  case L2_loadbzw2_pbr:
1086  case L2_loadbzw2_pci:
1087  case L2_loadbzw2_pcr:
1088  case L2_loadbzw2_pi:
1089  case L2_loadbzw4_pbr:
1090  case L2_loadbzw4_pci:
1091  case L2_loadbzw4_pcr:
1092  case L2_loadbzw4_pi:
1093 #endif
1094 
1095  case L2_loadrbgp:
1096  case L2_loadrb_io:
1097  case L2_loadrb_pbr:
1098  case L2_loadrb_pci:
1099  case L2_loadrb_pcr:
1100  case L2_loadrb_pi:
1101  case PS_loadrbabs:
1102  case L4_loadrb_ap:
1103  case L4_loadrb_rr:
1104  case L4_loadrb_ur:
1105  BitNum = 8;
1106  SignEx = true;
1107  break;
1108 
1109  case L2_loadrubgp:
1110  case L2_loadrub_io:
1111  case L2_loadrub_pbr:
1112  case L2_loadrub_pci:
1113  case L2_loadrub_pcr:
1114  case L2_loadrub_pi:
1115  case PS_loadrubabs:
1116  case L4_loadrub_ap:
1117  case L4_loadrub_rr:
1118  case L4_loadrub_ur:
1119  BitNum = 8;
1120  SignEx = false;
1121  break;
1122 
1123  case L2_loadrhgp:
1124  case L2_loadrh_io:
1125  case L2_loadrh_pbr:
1126  case L2_loadrh_pci:
1127  case L2_loadrh_pcr:
1128  case L2_loadrh_pi:
1129  case PS_loadrhabs:
1130  case L4_loadrh_ap:
1131  case L4_loadrh_rr:
1132  case L4_loadrh_ur:
1133  BitNum = 16;
1134  SignEx = true;
1135  break;
1136 
1137  case L2_loadruhgp:
1138  case L2_loadruh_io:
1139  case L2_loadruh_pbr:
1140  case L2_loadruh_pci:
1141  case L2_loadruh_pcr:
1142  case L2_loadruh_pi:
1143  case L4_loadruh_rr:
1144  case PS_loadruhabs:
1145  case L4_loadruh_ap:
1146  case L4_loadruh_ur:
1147  BitNum = 16;
1148  SignEx = false;
1149  break;
1150 
1151  case L2_loadrigp:
1152  case L2_loadri_io:
1153  case L2_loadri_pbr:
1154  case L2_loadri_pci:
1155  case L2_loadri_pcr:
1156  case L2_loadri_pi:
1157  case L2_loadw_locked:
1158  case PS_loadriabs:
1159  case L4_loadri_ap:
1160  case L4_loadri_rr:
1161  case L4_loadri_ur:
1162  case LDriw_pred:
1163  BitNum = 32;
1164  SignEx = true;
1165  break;
1166 
1167  case L2_loadrdgp:
1168  case L2_loadrd_io:
1169  case L2_loadrd_pbr:
1170  case L2_loadrd_pci:
1171  case L2_loadrd_pcr:
1172  case L2_loadrd_pi:
1173  case L4_loadd_locked:
1174  case PS_loadrdabs:
1175  case L4_loadrd_ap:
1176  case L4_loadrd_rr:
1177  case L4_loadrd_ur:
1178  BitNum = 64;
1179  SignEx = true;
1180  break;
1181  }
1182 
1183  const MachineOperand &MD = MI.getOperand(0);
1184  assert(MD.isReg() && MD.isDef());
1185  RegisterRef RD = MD;
1186 
1187  uint16_t W = getRegBitWidth(RD);
1188  assert(W >= BitNum && BitNum > 0);
1189  RegisterCell Res(W);
1190 
1191  for (uint16_t i = 0; i < BitNum; ++i)
1192  Res[i] = BT::BitValue::self(BT::BitRef(RD.Reg, i));
1193 
1194  if (SignEx) {
1195  const BT::BitValue &Sign = Res[BitNum-1];
1196  for (uint16_t i = BitNum; i < W; ++i)
1197  Res[i] = BT::BitValue::ref(Sign);
1198  } else {
1199  for (uint16_t i = BitNum; i < W; ++i)
1200  Res[i] = BT::BitValue::Zero;
1201  }
1202 
1203  putCell(RD, Res, Outputs);
1204  return true;
1205 }
1206 
1207 bool HexagonEvaluator::evaluateFormalCopy(const MachineInstr &MI,
1208  const CellMapType &Inputs,
1209  CellMapType &Outputs) const {
1210  // If MI defines a formal parameter, but is not a copy (loads are handled
1211  // in evaluateLoad), then it's not clear what to do.
1212  assert(MI.isCopy());
1213 
1214  RegisterRef RD = MI.getOperand(0);
1215  RegisterRef RS = MI.getOperand(1);
1216  assert(RD.Sub == 0);
1218  return false;
1219  RegExtMap::const_iterator F = VRX.find(RD.Reg);
1220  if (F == VRX.end())
1221  return false;
1222 
1223  uint16_t EW = F->second.Width;
1224  // Store RD's cell into the map. This will associate the cell with a virtual
1225  // register, and make zero-/sign-extends possible (otherwise we would be ex-
1226  // tending "self" bit values, which will have no effect, since "self" values
1227  // cannot be references to anything).
1228  putCell(RD, getCell(RS, Inputs), Outputs);
1229 
1230  RegisterCell Res;
1231  // Read RD's cell from the outputs instead of RS's cell from the inputs:
1232  if (F->second.Type == ExtType::SExt)
1233  Res = eSXT(getCell(RD, Outputs), EW);
1234  else if (F->second.Type == ExtType::ZExt)
1235  Res = eZXT(getCell(RD, Outputs), EW);
1236 
1237  putCell(RD, Res, Outputs);
1238  return true;
1239 }
1240 
1241 unsigned HexagonEvaluator::getNextPhysReg(unsigned PReg, unsigned Width) const {
1242  using namespace Hexagon;
1243 
1244  bool Is64 = DoubleRegsRegClass.contains(PReg);
1245  assert(PReg == 0 || Is64 || IntRegsRegClass.contains(PReg));
1246 
1247  static const unsigned Phys32[] = { R0, R1, R2, R3, R4, R5 };
1248  static const unsigned Phys64[] = { D0, D1, D2 };
1249  const unsigned Num32 = sizeof(Phys32)/sizeof(unsigned);
1250  const unsigned Num64 = sizeof(Phys64)/sizeof(unsigned);
1251 
1252  // Return the first parameter register of the required width.
1253  if (PReg == 0)
1254  return (Width <= 32) ? Phys32[0] : Phys64[0];
1255 
1256  // Set Idx32, Idx64 in such a way that Idx+1 would give the index of the
1257  // next register.
1258  unsigned Idx32 = 0, Idx64 = 0;
1259  if (!Is64) {
1260  while (Idx32 < Num32) {
1261  if (Phys32[Idx32] == PReg)
1262  break;
1263  Idx32++;
1264  }
1265  Idx64 = Idx32/2;
1266  } else {
1267  while (Idx64 < Num64) {
1268  if (Phys64[Idx64] == PReg)
1269  break;
1270  Idx64++;
1271  }
1272  Idx32 = Idx64*2+1;
1273  }
1274 
1275  if (Width <= 32)
1276  return (Idx32+1 < Num32) ? Phys32[Idx32+1] : 0;
1277  return (Idx64+1 < Num64) ? Phys64[Idx64+1] : 0;
1278 }
1279 
1280 unsigned HexagonEvaluator::getVirtRegFor(unsigned PReg) const {
1281  for (std::pair<unsigned,unsigned> P : MRI.liveins())
1282  if (P.first == PReg)
1283  return P.second;
1284  return 0;
1285 }
RegisterCell eASL(const RegisterCell &A1, uint16_t Sh) const
Definition: BitTracker.cpp:518
#define R4(n)
This class represents an incoming formal argument to a Function.
Definition: Argument.h:30
const TargetRegisterInfo & TRI
Definition: BitTracker.h:490
MachineBasicBlock * getMBB() const
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
RegisterCell & fill(uint16_t B, uint16_t E, const BitValue &V)
Definition: BitTracker.cpp:275
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
#define LLVM_FALLTHROUGH
Definition: Compiler.h:86
RegisterCell eASR(const RegisterCell &A1, uint16_t Sh) const
Definition: BitTracker.cpp:537
BitTracker::RegisterRef RegisterRef
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
void putCell(const RegisterRef &RR, RegisterCell RC, CellMapType &M) const
Definition: BitTracker.cpp:375
unsigned Reg
static RegisterCell self(unsigned Reg, uint16_t Width)
Definition: BitTracker.h:364
F(f)
BitTracker::BitMask mask(unsigned Reg, unsigned Sub) const override
MachineFrameInfo & MFI
#define R2(n)
const HexagonInstrInfo & TII
#define op(i)
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:459
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
RegisterCell eORL(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:570
HexagonEvaluator(const HexagonRegisterInfo &tri, MachineRegisterInfo &mri, const HexagonInstrInfo &tii, MachineFunction &mf)
bool evaluate(const MachineInstr &MI, const CellMapType &Inputs, CellMapType &Outputs) const override
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:196
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:412
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
BitTracker::CellMapType CellMapType
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:197
This file contains the simple types necessary to represent the attributes associated with functions a...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:409
RegisterCell eLSR(const RegisterCell &A1, uint16_t Sh) const
Definition: BitTracker.cpp:527
unsigned getID() const
Return the register class ID number.
#define im(i)
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:142
RegisterCell eADD(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:432
const TargetRegisterClass & composeWithSubRegIndex(const TargetRegisterClass &RC, unsigned Idx) const override
RegisterCell eCLB(const RegisterCell &A1, bool B, uint16_t W) const
Definition: BitTracker.cpp:643
const char * getName(unsigned RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register...
#define rc(i)
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
#define P(N)
RegisterCell eSUB(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:465
RegisterCell eIMM(int64_t V, uint16_t W) const
Definition: BitTracker.cpp:412
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:120
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
RegisterCell eNOT(const RegisterCell &A1) const
Definition: BitTracker.cpp:612
uint16_t getPhysRegBitWidth(unsigned Reg) const override
bool isPointerTy() const
True if this is an instance of PointerType.
Definition: Type.h:224
RegisterCell eAND(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:548
bool isCopy() const
RegisterCell eINS(const RegisterCell &A1, const RegisterCell &A2, uint16_t AtN) const
Definition: BitTracker.cpp:695
BitTracker::RegisterCell RegisterCell
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
RegisterCell eMLS(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:498
uint16_t getRegBitWidth(const RegisterRef &RR) const
Definition: BitTracker.cpp:330
MachineFunction & MF
auto size(R &&Range, typename std::enable_if< std::is_same< typename std::iterator_traits< decltype(Range.begin())>::iterator_category, std::random_access_iterator_tag >::value, void >::type *=nullptr) -> decltype(std::distance(Range.begin(), Range.end()))
Get the size of a range.
Definition: STLExtras.h:1023
static BitValue self(const BitRef &Self=BitRef())
Definition: BitTracker.h:280
MachineOperand class - Representation of each machine instruction operand.
RegisterCell eXOR(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:592
RegisterCell eCTB(const RegisterCell &A1, bool B, uint16_t W) const
Definition: BitTracker.cpp:653
bool is(unsigned T) const
Definition: BitTracker.h:209
MachineRegisterInfo & MRI
Definition: BitTracker.h:491
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
RegisterCell getCell(const RegisterRef &RR, const CellMapType &M) const
Definition: BitTracker.cpp:348
ArrayRef< std::pair< unsigned, unsigned > > liveins() const
RegisterCell & insert(const RegisterCell &RC, const BitMask &M)
Definition: BitTracker.cpp:215
amdgpu Simplify well known AMD library false Value Value * Arg
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:64
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
RegisterCell & cat(const RegisterCell &RC)
Definition: BitTracker.cpp:283
unsigned getIntegerBitWidth() const
Definition: DerivedTypes.h:97
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1213
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
RegisterCell eXTR(const RegisterCell &A1, uint16_t B, uint16_t E) const
Definition: BitTracker.cpp:683
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:807
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
RegisterCell eSXT(const RegisterCell &A1, uint16_t FromN) const
Definition: BitTracker.cpp:663
RegisterCell eMLU(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:508
A vector that has set insertion semantics.
Definition: SetVector.h:41
RegisterCell eZXT(const RegisterCell &A1, uint16_t FromN) const
Definition: BitTracker.cpp:674
bool meet(const RegisterCell &RC, unsigned SelfR)
Definition: BitTracker.cpp:202
IRTranslator LLVM IR MI
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
static RegisterCell ref(const RegisterCell &C)
Definition: BitTracker.h:380
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
iterator_range< arg_iterator > args()
Definition: Function.h:689
static BitValue ref(const BitValue &V)
Definition: BitTracker.h:271