LLVM  6.0.0svn
HexagonBitTracker.cpp
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1 //===- HexagonBitTracker.cpp ----------------------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "HexagonBitTracker.h"
11 #include "Hexagon.h"
12 #include "HexagonInstrInfo.h"
13 #include "HexagonRegisterInfo.h"
14 #include "HexagonSubtarget.h"
21 #include "llvm/IR/Argument.h"
22 #include "llvm/IR/Attributes.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/IR/Type.h"
25 #include "llvm/Support/Compiler.h"
26 #include "llvm/Support/Debug.h"
30 #include <cassert>
31 #include <cstddef>
32 #include <cstdint>
33 #include <cstdlib>
34 #include <utility>
35 #include <vector>
36 
37 using namespace llvm;
38 
39 using BT = BitTracker;
40 
43  const HexagonInstrInfo &tii,
44  MachineFunction &mf)
45  : MachineEvaluator(tri, mri), MF(mf), MFI(mf.getFrameInfo()), TII(tii) {
46  // Populate the VRX map (VR to extension-type).
47  // Go over all the formal parameters of the function. If a given parameter
48  // P is sign- or zero-extended, locate the virtual register holding that
49  // parameter and create an entry in the VRX map indicating the type of ex-
50  // tension (and the source type).
51  // This is a bit complicated to do accurately, since the memory layout in-
52  // formation is necessary to precisely determine whether an aggregate para-
53  // meter will be passed in a register or in memory. What is given in MRI
54  // is the association between the physical register that is live-in (i.e.
55  // holds an argument), and the virtual register that this value will be
56  // copied into. This, by itself, is not sufficient to map back the virtual
57  // register to a formal parameter from Function (since consecutive live-ins
58  // from MRI may not correspond to consecutive formal parameters from Func-
59  // tion). To avoid the complications with in-memory arguments, only consi-
60  // der the initial sequence of formal parameters that are known to be
61  // passed via registers.
62  unsigned InVirtReg, InPhysReg = 0;
63 
64  for (const Argument &Arg : MF.getFunction()->args()) {
65  Type *ATy = Arg.getType();
66  unsigned Width = 0;
67  if (ATy->isIntegerTy())
68  Width = ATy->getIntegerBitWidth();
69  else if (ATy->isPointerTy())
70  Width = 32;
71  // If pointer size is not set through target data, it will default to
72  // Module::AnyPointerSize.
73  if (Width == 0 || Width > 64)
74  break;
75  if (Arg.hasAttribute(Attribute::ByVal))
76  continue;
77  InPhysReg = getNextPhysReg(InPhysReg, Width);
78  if (!InPhysReg)
79  break;
80  InVirtReg = getVirtRegFor(InPhysReg);
81  if (!InVirtReg)
82  continue;
83  if (Arg.hasAttribute(Attribute::SExt))
84  VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::SExt, Width)));
85  else if (Arg.hasAttribute(Attribute::ZExt))
86  VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::ZExt, Width)));
87  }
88 }
89 
90 BT::BitMask HexagonEvaluator::mask(unsigned Reg, unsigned Sub) const {
91  if (Sub == 0)
92  return MachineEvaluator::mask(Reg, 0);
93  const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
94  unsigned ID = RC.getID();
95  uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub));
96  auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI);
97  bool IsSubLo = (Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo));
98  switch (ID) {
99  case Hexagon::DoubleRegsRegClassID:
100  case Hexagon::HvxWRRegClassID:
101  return IsSubLo ? BT::BitMask(0, RW-1)
102  : BT::BitMask(RW, 2*RW-1);
103  default:
104  break;
105  }
106 #ifndef NDEBUG
107  dbgs() << PrintReg(Reg, &TRI, Sub) << " in reg class "
108  << TRI.getRegClassName(&RC) << '\n';
109 #endif
110  llvm_unreachable("Unexpected register/subregister");
111 }
112 
113 uint16_t HexagonEvaluator::getPhysRegBitWidth(unsigned Reg) const {
115 
116  using namespace Hexagon;
117  for (auto &RC : {HvxVRRegClass, HvxWRRegClass, HvxQRRegClass})
118  if (RC.contains(Reg))
119  return TRI.getRegSizeInBits(RC);
120  // Default treatment for other physical registers.
121  if (const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg))
122  return TRI.getRegSizeInBits(*RC);
123 
125  (Twine("Unhandled physical register") + TRI.getName(Reg)).str().c_str());
126 }
127 
129  const TargetRegisterClass &RC, unsigned Idx) const {
130  if (Idx == 0)
131  return RC;
132 
133 #ifndef NDEBUG
134  const auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI);
135  bool IsSubLo = (Idx == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo));
136  bool IsSubHi = (Idx == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi));
137  assert(IsSubLo != IsSubHi && "Must refer to either low or high subreg");
138 #endif
139 
140  switch (RC.getID()) {
141  case Hexagon::DoubleRegsRegClassID:
142  return Hexagon::IntRegsRegClass;
143  case Hexagon::HvxWRRegClassID:
144  return Hexagon::HvxVRRegClass;
145  default:
146  break;
147  }
148 #ifndef NDEBUG
149  dbgs() << "Reg class id: " << RC.getID() << " idx: " << Idx << '\n';
150 #endif
151  llvm_unreachable("Unimplemented combination of reg class/subreg idx");
152 }
153 
154 namespace {
155 
156 class RegisterRefs {
157  std::vector<BT::RegisterRef> Vector;
158 
159 public:
160  RegisterRefs(const MachineInstr &MI) : Vector(MI.getNumOperands()) {
161  for (unsigned i = 0, n = Vector.size(); i < n; ++i) {
162  const MachineOperand &MO = MI.getOperand(i);
163  if (MO.isReg())
164  Vector[i] = BT::RegisterRef(MO);
165  // For indices that don't correspond to registers, the entry will
166  // remain constructed via the default constructor.
167  }
168  }
169 
170  size_t size() const { return Vector.size(); }
171 
172  const BT::RegisterRef &operator[](unsigned n) const {
173  // The main purpose of this operator is to assert with bad argument.
174  assert(n < Vector.size());
175  return Vector[n];
176  }
177 };
178 
179 } // end anonymous namespace
180 
182  const CellMapType &Inputs,
183  CellMapType &Outputs) const {
184  using namespace Hexagon;
185 
186  unsigned NumDefs = 0;
187 
188  // Sanity verification: there should not be any defs with subregisters.
189  for (const MachineOperand &MO : MI.operands()) {
190  if (!MO.isReg() || !MO.isDef())
191  continue;
192  NumDefs++;
193  assert(MO.getSubReg() == 0);
194  }
195 
196  if (NumDefs == 0)
197  return false;
198 
199  unsigned Opc = MI.getOpcode();
200 
201  if (MI.mayLoad()) {
202  switch (Opc) {
203  // These instructions may be marked as mayLoad, but they are generating
204  // immediate values, so skip them.
205  case CONST32:
206  case CONST64:
207  break;
208  default:
209  return evaluateLoad(MI, Inputs, Outputs);
210  }
211  }
212 
213  // Check COPY instructions that copy formal parameters into virtual
214  // registers. Such parameters can be sign- or zero-extended at the
215  // call site, and we should take advantage of this knowledge. The MRI
216  // keeps a list of pairs of live-in physical and virtual registers,
217  // which provides information about which virtual registers will hold
218  // the argument values. The function will still contain instructions
219  // defining those virtual registers, and in practice those are COPY
220  // instructions from a physical to a virtual register. In such cases,
221  // applying the argument extension to the virtual register can be seen
222  // as simply mirroring the extension that had already been applied to
223  // the physical register at the call site. If the defining instruction
224  // was not a COPY, it would not be clear how to mirror that extension
225  // on the callee's side. For that reason, only check COPY instructions
226  // for potential extensions.
227  if (MI.isCopy()) {
228  if (evaluateFormalCopy(MI, Inputs, Outputs))
229  return true;
230  }
231 
232  // Beyond this point, if any operand is a global, skip that instruction.
233  // The reason is that certain instructions that can take an immediate
234  // operand can also have a global symbol in that operand. To avoid
235  // checking what kind of operand a given instruction has individually
236  // for each instruction, do it here. Global symbols as operands gene-
237  // rally do not provide any useful information.
238  for (const MachineOperand &MO : MI.operands()) {
239  if (MO.isGlobal() || MO.isBlockAddress() || MO.isSymbol() || MO.isJTI() ||
240  MO.isCPI())
241  return false;
242  }
243 
244  RegisterRefs Reg(MI);
245 #define op(i) MI.getOperand(i)
246 #define rc(i) RegisterCell::ref(getCell(Reg[i], Inputs))
247 #define im(i) MI.getOperand(i).getImm()
248 
249  // If the instruction has no register operands, skip it.
250  if (Reg.size() == 0)
251  return false;
252 
253  // Record result for register in operand 0.
254  auto rr0 = [this,Reg] (const BT::RegisterCell &Val, CellMapType &Outputs)
255  -> bool {
256  putCell(Reg[0], Val, Outputs);
257  return true;
258  };
259  // Get the cell corresponding to the N-th operand.
260  auto cop = [this, &Reg, &MI, &Inputs](unsigned N,
261  uint16_t W) -> BT::RegisterCell {
262  const MachineOperand &Op = MI.getOperand(N);
263  if (Op.isImm())
264  return eIMM(Op.getImm(), W);
265  if (!Op.isReg())
266  return RegisterCell::self(0, W);
267  assert(getRegBitWidth(Reg[N]) == W && "Register width mismatch");
268  return rc(N);
269  };
270  // Extract RW low bits of the cell.
271  auto lo = [this] (const BT::RegisterCell &RC, uint16_t RW)
272  -> BT::RegisterCell {
273  assert(RW <= RC.width());
274  return eXTR(RC, 0, RW);
275  };
276  // Extract RW high bits of the cell.
277  auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW)
278  -> BT::RegisterCell {
279  uint16_t W = RC.width();
280  assert(RW <= W);
281  return eXTR(RC, W-RW, W);
282  };
283  // Extract N-th halfword (counting from the least significant position).
284  auto half = [this] (const BT::RegisterCell &RC, unsigned N)
285  -> BT::RegisterCell {
286  assert(N*16+16 <= RC.width());
287  return eXTR(RC, N*16, N*16+16);
288  };
289  // Shuffle bits (pick even/odd from cells and merge into result).
290  auto shuffle = [this] (const BT::RegisterCell &Rs, const BT::RegisterCell &Rt,
291  uint16_t BW, bool Odd) -> BT::RegisterCell {
292  uint16_t I = Odd, Ws = Rs.width();
293  assert(Ws == Rt.width());
294  RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW));
295  I += 2;
296  while (I*BW < Ws) {
297  RC.cat(eXTR(Rt, I*BW, I*BW+BW)).cat(eXTR(Rs, I*BW, I*BW+BW));
298  I += 2;
299  }
300  return RC;
301  };
302 
303  // The bitwidth of the 0th operand. In most (if not all) of the
304  // instructions below, the 0th operand is the defined register.
305  // Pre-compute the bitwidth here, because it is needed in many cases
306  // cases below.
307  uint16_t W0 = (Reg[0].Reg != 0) ? getRegBitWidth(Reg[0]) : 0;
308 
309  // Register id of the 0th operand. It can be 0.
310  unsigned Reg0 = Reg[0].Reg;
311 
312  switch (Opc) {
313  // Transfer immediate:
314 
315  case A2_tfrsi:
316  case A2_tfrpi:
317  case CONST32:
318  case CONST64:
319  return rr0(eIMM(im(1), W0), Outputs);
320  case PS_false:
321  return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::Zero), Outputs);
322  case PS_true:
323  return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::One), Outputs);
324  case PS_fi: {
325  int FI = op(1).getIndex();
326  int Off = op(2).getImm();
327  unsigned A = MFI.getObjectAlignment(FI) + std::abs(Off);
328  unsigned L = Log2_32(A);
329  RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0);
330  RC.fill(0, L, BT::BitValue::Zero);
331  return rr0(RC, Outputs);
332  }
333 
334  // Transfer register:
335 
336  case A2_tfr:
337  case A2_tfrp:
338  case C2_pxfer_map:
339  return rr0(rc(1), Outputs);
340  case C2_tfrpr: {
341  uint16_t RW = W0;
342  uint16_t PW = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
343  assert(PW <= RW);
344  RegisterCell PC = eXTR(rc(1), 0, PW);
345  RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1));
346  RC.fill(PW, RW, BT::BitValue::Zero);
347  return rr0(RC, Outputs);
348  }
349  case C2_tfrrp: {
350  RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0);
351  W0 = 8; // XXX Pred size
352  return rr0(eINS(RC, eXTR(rc(1), 0, W0), 0), Outputs);
353  }
354 
355  // Arithmetic:
356 
357  case A2_abs:
358  case A2_absp:
359  // TODO
360  break;
361 
362  case A2_addsp: {
363  uint16_t W1 = getRegBitWidth(Reg[1]);
364  assert(W0 == 64 && W1 == 32);
365  RegisterCell CW = RegisterCell(W0).insert(rc(1), BT::BitMask(0, W1-1));
366  RegisterCell RC = eADD(eSXT(CW, W1), rc(2));
367  return rr0(RC, Outputs);
368  }
369  case A2_add:
370  case A2_addp:
371  return rr0(eADD(rc(1), rc(2)), Outputs);
372  case A2_addi:
373  return rr0(eADD(rc(1), eIMM(im(2), W0)), Outputs);
374  case S4_addi_asl_ri: {
375  RegisterCell RC = eADD(eIMM(im(1), W0), eASL(rc(2), im(3)));
376  return rr0(RC, Outputs);
377  }
378  case S4_addi_lsr_ri: {
379  RegisterCell RC = eADD(eIMM(im(1), W0), eLSR(rc(2), im(3)));
380  return rr0(RC, Outputs);
381  }
382  case S4_addaddi: {
383  RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0)));
384  return rr0(RC, Outputs);
385  }
386  case M4_mpyri_addi: {
387  RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
388  RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0));
389  return rr0(RC, Outputs);
390  }
391  case M4_mpyrr_addi: {
392  RegisterCell M = eMLS(rc(2), rc(3));
393  RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0));
394  return rr0(RC, Outputs);
395  }
396  case M4_mpyri_addr_u2: {
397  RegisterCell M = eMLS(eIMM(im(2), W0), rc(3));
398  RegisterCell RC = eADD(rc(1), lo(M, W0));
399  return rr0(RC, Outputs);
400  }
401  case M4_mpyri_addr: {
402  RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
403  RegisterCell RC = eADD(rc(1), lo(M, W0));
404  return rr0(RC, Outputs);
405  }
406  case M4_mpyrr_addr: {
407  RegisterCell M = eMLS(rc(2), rc(3));
408  RegisterCell RC = eADD(rc(1), lo(M, W0));
409  return rr0(RC, Outputs);
410  }
411  case S4_subaddi: {
412  RegisterCell RC = eADD(rc(1), eSUB(eIMM(im(2), W0), rc(3)));
413  return rr0(RC, Outputs);
414  }
415  case M2_accii: {
416  RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0)));
417  return rr0(RC, Outputs);
418  }
419  case M2_acci: {
420  RegisterCell RC = eADD(rc(1), eADD(rc(2), rc(3)));
421  return rr0(RC, Outputs);
422  }
423  case M2_subacc: {
424  RegisterCell RC = eADD(rc(1), eSUB(rc(2), rc(3)));
425  return rr0(RC, Outputs);
426  }
427  case S2_addasl_rrri: {
428  RegisterCell RC = eADD(rc(1), eASL(rc(2), im(3)));
429  return rr0(RC, Outputs);
430  }
431  case C4_addipc: {
432  RegisterCell RPC = RegisterCell::self(Reg[0].Reg, W0);
433  RPC.fill(0, 2, BT::BitValue::Zero);
434  return rr0(eADD(RPC, eIMM(im(2), W0)), Outputs);
435  }
436  case A2_sub:
437  case A2_subp:
438  return rr0(eSUB(rc(1), rc(2)), Outputs);
439  case A2_subri:
440  return rr0(eSUB(eIMM(im(1), W0), rc(2)), Outputs);
441  case S4_subi_asl_ri: {
442  RegisterCell RC = eSUB(eIMM(im(1), W0), eASL(rc(2), im(3)));
443  return rr0(RC, Outputs);
444  }
445  case S4_subi_lsr_ri: {
446  RegisterCell RC = eSUB(eIMM(im(1), W0), eLSR(rc(2), im(3)));
447  return rr0(RC, Outputs);
448  }
449  case M2_naccii: {
450  RegisterCell RC = eSUB(rc(1), eADD(rc(2), eIMM(im(3), W0)));
451  return rr0(RC, Outputs);
452  }
453  case M2_nacci: {
454  RegisterCell RC = eSUB(rc(1), eADD(rc(2), rc(3)));
455  return rr0(RC, Outputs);
456  }
457  // 32-bit negation is done by "Rd = A2_subri 0, Rs"
458  case A2_negp:
459  return rr0(eSUB(eIMM(0, W0), rc(1)), Outputs);
460 
461  case M2_mpy_up: {
462  RegisterCell M = eMLS(rc(1), rc(2));
463  return rr0(hi(M, W0), Outputs);
464  }
465  case M2_dpmpyss_s0:
466  return rr0(eMLS(rc(1), rc(2)), Outputs);
467  case M2_dpmpyss_acc_s0:
468  return rr0(eADD(rc(1), eMLS(rc(2), rc(3))), Outputs);
469  case M2_dpmpyss_nac_s0:
470  return rr0(eSUB(rc(1), eMLS(rc(2), rc(3))), Outputs);
471  case M2_mpyi: {
472  RegisterCell M = eMLS(rc(1), rc(2));
473  return rr0(lo(M, W0), Outputs);
474  }
475  case M2_macsip: {
476  RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
477  RegisterCell RC = eADD(rc(1), lo(M, W0));
478  return rr0(RC, Outputs);
479  }
480  case M2_macsin: {
481  RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
482  RegisterCell RC = eSUB(rc(1), lo(M, W0));
483  return rr0(RC, Outputs);
484  }
485  case M2_maci: {
486  RegisterCell M = eMLS(rc(2), rc(3));
487  RegisterCell RC = eADD(rc(1), lo(M, W0));
488  return rr0(RC, Outputs);
489  }
490  case M2_mpysmi: {
491  RegisterCell M = eMLS(rc(1), eIMM(im(2), W0));
492  return rr0(lo(M, 32), Outputs);
493  }
494  case M2_mpysin: {
495  RegisterCell M = eMLS(rc(1), eIMM(-im(2), W0));
496  return rr0(lo(M, 32), Outputs);
497  }
498  case M2_mpysip: {
499  RegisterCell M = eMLS(rc(1), eIMM(im(2), W0));
500  return rr0(lo(M, 32), Outputs);
501  }
502  case M2_mpyu_up: {
503  RegisterCell M = eMLU(rc(1), rc(2));
504  return rr0(hi(M, W0), Outputs);
505  }
506  case M2_dpmpyuu_s0:
507  return rr0(eMLU(rc(1), rc(2)), Outputs);
508  case M2_dpmpyuu_acc_s0:
509  return rr0(eADD(rc(1), eMLU(rc(2), rc(3))), Outputs);
510  case M2_dpmpyuu_nac_s0:
511  return rr0(eSUB(rc(1), eMLU(rc(2), rc(3))), Outputs);
512  //case M2_mpysu_up:
513 
514  // Logical/bitwise:
515 
516  case A2_andir:
517  return rr0(eAND(rc(1), eIMM(im(2), W0)), Outputs);
518  case A2_and:
519  case A2_andp:
520  return rr0(eAND(rc(1), rc(2)), Outputs);
521  case A4_andn:
522  case A4_andnp:
523  return rr0(eAND(rc(1), eNOT(rc(2))), Outputs);
524  case S4_andi_asl_ri: {
525  RegisterCell RC = eAND(eIMM(im(1), W0), eASL(rc(2), im(3)));
526  return rr0(RC, Outputs);
527  }
528  case S4_andi_lsr_ri: {
529  RegisterCell RC = eAND(eIMM(im(1), W0), eLSR(rc(2), im(3)));
530  return rr0(RC, Outputs);
531  }
532  case M4_and_and:
533  return rr0(eAND(rc(1), eAND(rc(2), rc(3))), Outputs);
534  case M4_and_andn:
535  return rr0(eAND(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
536  case M4_and_or:
537  return rr0(eAND(rc(1), eORL(rc(2), rc(3))), Outputs);
538  case M4_and_xor:
539  return rr0(eAND(rc(1), eXOR(rc(2), rc(3))), Outputs);
540  case A2_orir:
541  return rr0(eORL(rc(1), eIMM(im(2), W0)), Outputs);
542  case A2_or:
543  case A2_orp:
544  return rr0(eORL(rc(1), rc(2)), Outputs);
545  case A4_orn:
546  case A4_ornp:
547  return rr0(eORL(rc(1), eNOT(rc(2))), Outputs);
548  case S4_ori_asl_ri: {
549  RegisterCell RC = eORL(eIMM(im(1), W0), eASL(rc(2), im(3)));
550  return rr0(RC, Outputs);
551  }
552  case S4_ori_lsr_ri: {
553  RegisterCell RC = eORL(eIMM(im(1), W0), eLSR(rc(2), im(3)));
554  return rr0(RC, Outputs);
555  }
556  case M4_or_and:
557  return rr0(eORL(rc(1), eAND(rc(2), rc(3))), Outputs);
558  case M4_or_andn:
559  return rr0(eORL(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
560  case S4_or_andi:
561  case S4_or_andix: {
562  RegisterCell RC = eORL(rc(1), eAND(rc(2), eIMM(im(3), W0)));
563  return rr0(RC, Outputs);
564  }
565  case S4_or_ori: {
566  RegisterCell RC = eORL(rc(1), eORL(rc(2), eIMM(im(3), W0)));
567  return rr0(RC, Outputs);
568  }
569  case M4_or_or:
570  return rr0(eORL(rc(1), eORL(rc(2), rc(3))), Outputs);
571  case M4_or_xor:
572  return rr0(eORL(rc(1), eXOR(rc(2), rc(3))), Outputs);
573  case A2_xor:
574  case A2_xorp:
575  return rr0(eXOR(rc(1), rc(2)), Outputs);
576  case M4_xor_and:
577  return rr0(eXOR(rc(1), eAND(rc(2), rc(3))), Outputs);
578  case M4_xor_andn:
579  return rr0(eXOR(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
580  case M4_xor_or:
581  return rr0(eXOR(rc(1), eORL(rc(2), rc(3))), Outputs);
582  case M4_xor_xacc:
583  return rr0(eXOR(rc(1), eXOR(rc(2), rc(3))), Outputs);
584  case A2_not:
585  case A2_notp:
586  return rr0(eNOT(rc(1)), Outputs);
587 
588  case S2_asl_i_r:
589  case S2_asl_i_p:
590  return rr0(eASL(rc(1), im(2)), Outputs);
591  case A2_aslh:
592  return rr0(eASL(rc(1), 16), Outputs);
593  case S2_asl_i_r_acc:
594  case S2_asl_i_p_acc:
595  return rr0(eADD(rc(1), eASL(rc(2), im(3))), Outputs);
596  case S2_asl_i_r_nac:
597  case S2_asl_i_p_nac:
598  return rr0(eSUB(rc(1), eASL(rc(2), im(3))), Outputs);
599  case S2_asl_i_r_and:
600  case S2_asl_i_p_and:
601  return rr0(eAND(rc(1), eASL(rc(2), im(3))), Outputs);
602  case S2_asl_i_r_or:
603  case S2_asl_i_p_or:
604  return rr0(eORL(rc(1), eASL(rc(2), im(3))), Outputs);
605  case S2_asl_i_r_xacc:
606  case S2_asl_i_p_xacc:
607  return rr0(eXOR(rc(1), eASL(rc(2), im(3))), Outputs);
608  case S2_asl_i_vh:
609  case S2_asl_i_vw:
610  // TODO
611  break;
612 
613  case S2_asr_i_r:
614  case S2_asr_i_p:
615  return rr0(eASR(rc(1), im(2)), Outputs);
616  case A2_asrh:
617  return rr0(eASR(rc(1), 16), Outputs);
618  case S2_asr_i_r_acc:
619  case S2_asr_i_p_acc:
620  return rr0(eADD(rc(1), eASR(rc(2), im(3))), Outputs);
621  case S2_asr_i_r_nac:
622  case S2_asr_i_p_nac:
623  return rr0(eSUB(rc(1), eASR(rc(2), im(3))), Outputs);
624  case S2_asr_i_r_and:
625  case S2_asr_i_p_and:
626  return rr0(eAND(rc(1), eASR(rc(2), im(3))), Outputs);
627  case S2_asr_i_r_or:
628  case S2_asr_i_p_or:
629  return rr0(eORL(rc(1), eASR(rc(2), im(3))), Outputs);
630  case S2_asr_i_r_rnd: {
631  // The input is first sign-extended to 64 bits, then the output
632  // is truncated back to 32 bits.
633  assert(W0 == 32);
634  RegisterCell XC = eSXT(rc(1).cat(eIMM(0, W0)), W0);
635  RegisterCell RC = eASR(eADD(eASR(XC, im(2)), eIMM(1, 2*W0)), 1);
636  return rr0(eXTR(RC, 0, W0), Outputs);
637  }
638  case S2_asr_i_r_rnd_goodsyntax: {
639  int64_t S = im(2);
640  if (S == 0)
641  return rr0(rc(1), Outputs);
642  // Result: S2_asr_i_r_rnd Rs, u5-1
643  RegisterCell XC = eSXT(rc(1).cat(eIMM(0, W0)), W0);
644  RegisterCell RC = eLSR(eADD(eASR(XC, S-1), eIMM(1, 2*W0)), 1);
645  return rr0(eXTR(RC, 0, W0), Outputs);
646  }
647  case S2_asr_r_vh:
648  case S2_asr_i_vw:
649  case S2_asr_i_svw_trun:
650  // TODO
651  break;
652 
653  case S2_lsr_i_r:
654  case S2_lsr_i_p:
655  return rr0(eLSR(rc(1), im(2)), Outputs);
656  case S2_lsr_i_r_acc:
657  case S2_lsr_i_p_acc:
658  return rr0(eADD(rc(1), eLSR(rc(2), im(3))), Outputs);
659  case S2_lsr_i_r_nac:
660  case S2_lsr_i_p_nac:
661  return rr0(eSUB(rc(1), eLSR(rc(2), im(3))), Outputs);
662  case S2_lsr_i_r_and:
663  case S2_lsr_i_p_and:
664  return rr0(eAND(rc(1), eLSR(rc(2), im(3))), Outputs);
665  case S2_lsr_i_r_or:
666  case S2_lsr_i_p_or:
667  return rr0(eORL(rc(1), eLSR(rc(2), im(3))), Outputs);
668  case S2_lsr_i_r_xacc:
669  case S2_lsr_i_p_xacc:
670  return rr0(eXOR(rc(1), eLSR(rc(2), im(3))), Outputs);
671 
672  case S2_clrbit_i: {
673  RegisterCell RC = rc(1);
674  RC[im(2)] = BT::BitValue::Zero;
675  return rr0(RC, Outputs);
676  }
677  case S2_setbit_i: {
678  RegisterCell RC = rc(1);
679  RC[im(2)] = BT::BitValue::One;
680  return rr0(RC, Outputs);
681  }
682  case S2_togglebit_i: {
683  RegisterCell RC = rc(1);
684  uint16_t BX = im(2);
685  RC[BX] = RC[BX].is(0) ? BT::BitValue::One
686  : RC[BX].is(1) ? BT::BitValue::Zero
687  : BT::BitValue::self();
688  return rr0(RC, Outputs);
689  }
690 
691  case A4_bitspliti: {
692  uint16_t W1 = getRegBitWidth(Reg[1]);
693  uint16_t BX = im(2);
694  // Res.uw[1] = Rs[bx+1:], Res.uw[0] = Rs[0:bx]
695  const BT::BitValue Zero = BT::BitValue::Zero;
696  RegisterCell RZ = RegisterCell(W0).fill(BX, W1, Zero)
697  .fill(W1+(W1-BX), W0, Zero);
698  RegisterCell BF1 = eXTR(rc(1), 0, BX), BF2 = eXTR(rc(1), BX, W1);
699  RegisterCell RC = eINS(eINS(RZ, BF1, 0), BF2, W1);
700  return rr0(RC, Outputs);
701  }
702  case S4_extract:
703  case S4_extractp:
704  case S2_extractu:
705  case S2_extractup: {
706  uint16_t Wd = im(2), Of = im(3);
707  assert(Wd <= W0);
708  if (Wd == 0)
709  return rr0(eIMM(0, W0), Outputs);
710  // If the width extends beyond the register size, pad the register
711  // with 0 bits.
712  RegisterCell Pad = (Wd+Of > W0) ? rc(1).cat(eIMM(0, Wd+Of-W0)) : rc(1);
713  RegisterCell Ext = eXTR(Pad, Of, Wd+Of);
714  // Ext is short, need to extend it with 0s or sign bit.
715  RegisterCell RC = RegisterCell(W0).insert(Ext, BT::BitMask(0, Wd-1));
716  if (Opc == S2_extractu || Opc == S2_extractup)
717  return rr0(eZXT(RC, Wd), Outputs);
718  return rr0(eSXT(RC, Wd), Outputs);
719  }
720  case S2_insert:
721  case S2_insertp: {
722  uint16_t Wd = im(3), Of = im(4);
723  assert(Wd < W0 && Of < W0);
724  // If Wd+Of exceeds W0, the inserted bits are truncated.
725  if (Wd+Of > W0)
726  Wd = W0-Of;
727  if (Wd == 0)
728  return rr0(rc(1), Outputs);
729  return rr0(eINS(rc(1), eXTR(rc(2), 0, Wd), Of), Outputs);
730  }
731 
732  // Bit permutations:
733 
734  case A2_combineii:
735  case A4_combineii:
736  case A4_combineir:
737  case A4_combineri:
738  case A2_combinew:
739  case V6_vcombine:
740  assert(W0 % 2 == 0);
741  return rr0(cop(2, W0/2).cat(cop(1, W0/2)), Outputs);
742  case A2_combine_ll:
743  case A2_combine_lh:
744  case A2_combine_hl:
745  case A2_combine_hh: {
746  assert(W0 == 32);
747  assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32);
748  // Low half in the output is 0 for _ll and _hl, 1 otherwise:
749  unsigned LoH = !(Opc == A2_combine_ll || Opc == A2_combine_hl);
750  // High half in the output is 0 for _ll and _lh, 1 otherwise:
751  unsigned HiH = !(Opc == A2_combine_ll || Opc == A2_combine_lh);
752  RegisterCell R1 = rc(1);
753  RegisterCell R2 = rc(2);
754  RegisterCell RC = half(R2, LoH).cat(half(R1, HiH));
755  return rr0(RC, Outputs);
756  }
757  case S2_packhl: {
758  assert(W0 == 64);
759  assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32);
760  RegisterCell R1 = rc(1);
761  RegisterCell R2 = rc(2);
762  RegisterCell RC = half(R2, 0).cat(half(R1, 0)).cat(half(R2, 1))
763  .cat(half(R1, 1));
764  return rr0(RC, Outputs);
765  }
766  case S2_shuffeb: {
767  RegisterCell RC = shuffle(rc(1), rc(2), 8, false);
768  return rr0(RC, Outputs);
769  }
770  case S2_shuffeh: {
771  RegisterCell RC = shuffle(rc(1), rc(2), 16, false);
772  return rr0(RC, Outputs);
773  }
774  case S2_shuffob: {
775  RegisterCell RC = shuffle(rc(1), rc(2), 8, true);
776  return rr0(RC, Outputs);
777  }
778  case S2_shuffoh: {
779  RegisterCell RC = shuffle(rc(1), rc(2), 16, true);
780  return rr0(RC, Outputs);
781  }
782  case C2_mask: {
783  uint16_t WR = W0;
784  uint16_t WP = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
785  assert(WR == 64 && WP == 8);
786  RegisterCell R1 = rc(1);
787  RegisterCell RC(WR);
788  for (uint16_t i = 0; i < WP; ++i) {
789  const BT::BitValue &V = R1[i];
790  BT::BitValue F = (V.is(0) || V.is(1)) ? V : BT::BitValue::self();
791  RC.fill(i*8, i*8+8, F);
792  }
793  return rr0(RC, Outputs);
794  }
795 
796  // Mux:
797 
798  case C2_muxii:
799  case C2_muxir:
800  case C2_muxri:
801  case C2_mux: {
802  BT::BitValue PC0 = rc(1)[0];
803  RegisterCell R2 = cop(2, W0);
804  RegisterCell R3 = cop(3, W0);
805  if (PC0.is(0) || PC0.is(1))
806  return rr0(RegisterCell::ref(PC0 ? R2 : R3), Outputs);
807  R2.meet(R3, Reg[0].Reg);
808  return rr0(R2, Outputs);
809  }
810  case C2_vmux:
811  // TODO
812  break;
813 
814  // Sign- and zero-extension:
815 
816  case A2_sxtb:
817  return rr0(eSXT(rc(1), 8), Outputs);
818  case A2_sxth:
819  return rr0(eSXT(rc(1), 16), Outputs);
820  case A2_sxtw: {
821  uint16_t W1 = getRegBitWidth(Reg[1]);
822  assert(W0 == 64 && W1 == 32);
823  RegisterCell RC = eSXT(rc(1).cat(eIMM(0, W1)), W1);
824  return rr0(RC, Outputs);
825  }
826  case A2_zxtb:
827  return rr0(eZXT(rc(1), 8), Outputs);
828  case A2_zxth:
829  return rr0(eZXT(rc(1), 16), Outputs);
830 
831  // Saturations
832 
833  case A2_satb:
834  return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs);
835  case A2_sath:
836  return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs);
837  case A2_satub:
838  return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs);
839  case A2_satuh:
840  return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs);
841 
842  // Bit count:
843 
844  case S2_cl0:
845  case S2_cl0p:
846  // Always produce a 32-bit result.
847  return rr0(eCLB(rc(1), false/*bit*/, 32), Outputs);
848  case S2_cl1:
849  case S2_cl1p:
850  return rr0(eCLB(rc(1), true/*bit*/, 32), Outputs);
851  case S2_clb:
852  case S2_clbp: {
853  uint16_t W1 = getRegBitWidth(Reg[1]);
854  RegisterCell R1 = rc(1);
855  BT::BitValue TV = R1[W1-1];
856  if (TV.is(0) || TV.is(1))
857  return rr0(eCLB(R1, TV, 32), Outputs);
858  break;
859  }
860  case S2_ct0:
861  case S2_ct0p:
862  return rr0(eCTB(rc(1), false/*bit*/, 32), Outputs);
863  case S2_ct1:
864  case S2_ct1p:
865  return rr0(eCTB(rc(1), true/*bit*/, 32), Outputs);
866  case S5_popcountp:
867  // TODO
868  break;
869 
870  case C2_all8: {
871  RegisterCell P1 = rc(1);
872  bool Has0 = false, All1 = true;
873  for (uint16_t i = 0; i < 8/*XXX*/; ++i) {
874  if (!P1[i].is(1))
875  All1 = false;
876  if (!P1[i].is(0))
877  continue;
878  Has0 = true;
879  break;
880  }
881  if (!Has0 && !All1)
882  break;
883  RegisterCell RC(W0);
884  RC.fill(0, W0, (All1 ? BT::BitValue::One : BT::BitValue::Zero));
885  return rr0(RC, Outputs);
886  }
887  case C2_any8: {
888  RegisterCell P1 = rc(1);
889  bool Has1 = false, All0 = true;
890  for (uint16_t i = 0; i < 8/*XXX*/; ++i) {
891  if (!P1[i].is(0))
892  All0 = false;
893  if (!P1[i].is(1))
894  continue;
895  Has1 = true;
896  break;
897  }
898  if (!Has1 && !All0)
899  break;
900  RegisterCell RC(W0);
901  RC.fill(0, W0, (Has1 ? BT::BitValue::One : BT::BitValue::Zero));
902  return rr0(RC, Outputs);
903  }
904  case C2_and:
905  return rr0(eAND(rc(1), rc(2)), Outputs);
906  case C2_andn:
907  return rr0(eAND(rc(1), eNOT(rc(2))), Outputs);
908  case C2_not:
909  return rr0(eNOT(rc(1)), Outputs);
910  case C2_or:
911  return rr0(eORL(rc(1), rc(2)), Outputs);
912  case C2_orn:
913  return rr0(eORL(rc(1), eNOT(rc(2))), Outputs);
914  case C2_xor:
915  return rr0(eXOR(rc(1), rc(2)), Outputs);
916  case C4_and_and:
917  return rr0(eAND(rc(1), eAND(rc(2), rc(3))), Outputs);
918  case C4_and_andn:
919  return rr0(eAND(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
920  case C4_and_or:
921  return rr0(eAND(rc(1), eORL(rc(2), rc(3))), Outputs);
922  case C4_and_orn:
923  return rr0(eAND(rc(1), eORL(rc(2), eNOT(rc(3)))), Outputs);
924  case C4_or_and:
925  return rr0(eORL(rc(1), eAND(rc(2), rc(3))), Outputs);
926  case C4_or_andn:
927  return rr0(eORL(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
928  case C4_or_or:
929  return rr0(eORL(rc(1), eORL(rc(2), rc(3))), Outputs);
930  case C4_or_orn:
931  return rr0(eORL(rc(1), eORL(rc(2), eNOT(rc(3)))), Outputs);
932  case C2_bitsclr:
933  case C2_bitsclri:
934  case C2_bitsset:
935  case C4_nbitsclr:
936  case C4_nbitsclri:
937  case C4_nbitsset:
938  // TODO
939  break;
940  case S2_tstbit_i:
941  case S4_ntstbit_i: {
942  BT::BitValue V = rc(1)[im(2)];
943  if (V.is(0) || V.is(1)) {
944  // If instruction is S2_tstbit_i, test for 1, otherwise test for 0.
945  bool TV = (Opc == S2_tstbit_i);
947  return rr0(RegisterCell(W0).fill(0, W0, F), Outputs);
948  }
949  break;
950  }
951 
952  default:
953  return MachineEvaluator::evaluate(MI, Inputs, Outputs);
954  }
955  #undef im
956  #undef rc
957  #undef op
958  return false;
959 }
960 
962  const CellMapType &Inputs,
963  BranchTargetList &Targets,
964  bool &FallsThru) const {
965  // We need to evaluate one branch at a time. TII::analyzeBranch checks
966  // all the branches in a basic block at once, so we cannot use it.
967  unsigned Opc = BI.getOpcode();
968  bool SimpleBranch = false;
969  bool Negated = false;
970  switch (Opc) {
971  case Hexagon::J2_jumpf:
972  case Hexagon::J2_jumpfpt:
973  case Hexagon::J2_jumpfnew:
974  case Hexagon::J2_jumpfnewpt:
975  Negated = true;
977  case Hexagon::J2_jumpt:
978  case Hexagon::J2_jumptpt:
979  case Hexagon::J2_jumptnew:
980  case Hexagon::J2_jumptnewpt:
981  // Simple branch: if([!]Pn) jump ...
982  // i.e. Op0 = predicate, Op1 = branch target.
983  SimpleBranch = true;
984  break;
985  case Hexagon::J2_jump:
986  Targets.insert(BI.getOperand(0).getMBB());
987  FallsThru = false;
988  return true;
989  default:
990  // If the branch is of unknown type, assume that all successors are
991  // executable.
992  return false;
993  }
994 
995  if (!SimpleBranch)
996  return false;
997 
998  // BI is a conditional branch if we got here.
999  RegisterRef PR = BI.getOperand(0);
1000  RegisterCell PC = getCell(PR, Inputs);
1001  const BT::BitValue &Test = PC[0];
1002 
1003  // If the condition is neither true nor false, then it's unknown.
1004  if (!Test.is(0) && !Test.is(1))
1005  return false;
1006 
1007  // "Test.is(!Negated)" means "branch condition is true".
1008  if (!Test.is(!Negated)) {
1009  // Condition known to be false.
1010  FallsThru = true;
1011  return true;
1012  }
1013 
1014  Targets.insert(BI.getOperand(1).getMBB());
1015  FallsThru = false;
1016  return true;
1017 }
1018 
1019 bool HexagonEvaluator::evaluateLoad(const MachineInstr &MI,
1020  const CellMapType &Inputs,
1021  CellMapType &Outputs) const {
1022  using namespace Hexagon;
1023 
1024  if (TII.isPredicated(MI))
1025  return false;
1026  assert(MI.mayLoad() && "A load that mayn't?");
1027  unsigned Opc = MI.getOpcode();
1028 
1029  uint16_t BitNum;
1030  bool SignEx;
1031 
1032  switch (Opc) {
1033  default:
1034  return false;
1035 
1036 #if 0
1037  // memb_fifo
1038  case L2_loadalignb_pbr:
1039  case L2_loadalignb_pcr:
1040  case L2_loadalignb_pi:
1041  // memh_fifo
1042  case L2_loadalignh_pbr:
1043  case L2_loadalignh_pcr:
1044  case L2_loadalignh_pi:
1045  // membh
1046  case L2_loadbsw2_pbr:
1047  case L2_loadbsw2_pci:
1048  case L2_loadbsw2_pcr:
1049  case L2_loadbsw2_pi:
1050  case L2_loadbsw4_pbr:
1051  case L2_loadbsw4_pci:
1052  case L2_loadbsw4_pcr:
1053  case L2_loadbsw4_pi:
1054  // memubh
1055  case L2_loadbzw2_pbr:
1056  case L2_loadbzw2_pci:
1057  case L2_loadbzw2_pcr:
1058  case L2_loadbzw2_pi:
1059  case L2_loadbzw4_pbr:
1060  case L2_loadbzw4_pci:
1061  case L2_loadbzw4_pcr:
1062  case L2_loadbzw4_pi:
1063 #endif
1064 
1065  case L2_loadrbgp:
1066  case L2_loadrb_io:
1067  case L2_loadrb_pbr:
1068  case L2_loadrb_pci:
1069  case L2_loadrb_pcr:
1070  case L2_loadrb_pi:
1071  case PS_loadrbabs:
1072  case L4_loadrb_ap:
1073  case L4_loadrb_rr:
1074  case L4_loadrb_ur:
1075  BitNum = 8;
1076  SignEx = true;
1077  break;
1078 
1079  case L2_loadrubgp:
1080  case L2_loadrub_io:
1081  case L2_loadrub_pbr:
1082  case L2_loadrub_pci:
1083  case L2_loadrub_pcr:
1084  case L2_loadrub_pi:
1085  case PS_loadrubabs:
1086  case L4_loadrub_ap:
1087  case L4_loadrub_rr:
1088  case L4_loadrub_ur:
1089  BitNum = 8;
1090  SignEx = false;
1091  break;
1092 
1093  case L2_loadrhgp:
1094  case L2_loadrh_io:
1095  case L2_loadrh_pbr:
1096  case L2_loadrh_pci:
1097  case L2_loadrh_pcr:
1098  case L2_loadrh_pi:
1099  case PS_loadrhabs:
1100  case L4_loadrh_ap:
1101  case L4_loadrh_rr:
1102  case L4_loadrh_ur:
1103  BitNum = 16;
1104  SignEx = true;
1105  break;
1106 
1107  case L2_loadruhgp:
1108  case L2_loadruh_io:
1109  case L2_loadruh_pbr:
1110  case L2_loadruh_pci:
1111  case L2_loadruh_pcr:
1112  case L2_loadruh_pi:
1113  case L4_loadruh_rr:
1114  case PS_loadruhabs:
1115  case L4_loadruh_ap:
1116  case L4_loadruh_ur:
1117  BitNum = 16;
1118  SignEx = false;
1119  break;
1120 
1121  case L2_loadrigp:
1122  case L2_loadri_io:
1123  case L2_loadri_pbr:
1124  case L2_loadri_pci:
1125  case L2_loadri_pcr:
1126  case L2_loadri_pi:
1127  case L2_loadw_locked:
1128  case PS_loadriabs:
1129  case L4_loadri_ap:
1130  case L4_loadri_rr:
1131  case L4_loadri_ur:
1132  case LDriw_pred:
1133  BitNum = 32;
1134  SignEx = true;
1135  break;
1136 
1137  case L2_loadrdgp:
1138  case L2_loadrd_io:
1139  case L2_loadrd_pbr:
1140  case L2_loadrd_pci:
1141  case L2_loadrd_pcr:
1142  case L2_loadrd_pi:
1143  case L4_loadd_locked:
1144  case PS_loadrdabs:
1145  case L4_loadrd_ap:
1146  case L4_loadrd_rr:
1147  case L4_loadrd_ur:
1148  BitNum = 64;
1149  SignEx = true;
1150  break;
1151  }
1152 
1153  const MachineOperand &MD = MI.getOperand(0);
1154  assert(MD.isReg() && MD.isDef());
1155  RegisterRef RD = MD;
1156 
1157  uint16_t W = getRegBitWidth(RD);
1158  assert(W >= BitNum && BitNum > 0);
1159  RegisterCell Res(W);
1160 
1161  for (uint16_t i = 0; i < BitNum; ++i)
1162  Res[i] = BT::BitValue::self(BT::BitRef(RD.Reg, i));
1163 
1164  if (SignEx) {
1165  const BT::BitValue &Sign = Res[BitNum-1];
1166  for (uint16_t i = BitNum; i < W; ++i)
1167  Res[i] = BT::BitValue::ref(Sign);
1168  } else {
1169  for (uint16_t i = BitNum; i < W; ++i)
1170  Res[i] = BT::BitValue::Zero;
1171  }
1172 
1173  putCell(RD, Res, Outputs);
1174  return true;
1175 }
1176 
1177 bool HexagonEvaluator::evaluateFormalCopy(const MachineInstr &MI,
1178  const CellMapType &Inputs,
1179  CellMapType &Outputs) const {
1180  // If MI defines a formal parameter, but is not a copy (loads are handled
1181  // in evaluateLoad), then it's not clear what to do.
1182  assert(MI.isCopy());
1183 
1184  RegisterRef RD = MI.getOperand(0);
1185  RegisterRef RS = MI.getOperand(1);
1186  assert(RD.Sub == 0);
1188  return false;
1189  RegExtMap::const_iterator F = VRX.find(RD.Reg);
1190  if (F == VRX.end())
1191  return false;
1192 
1193  uint16_t EW = F->second.Width;
1194  // Store RD's cell into the map. This will associate the cell with a virtual
1195  // register, and make zero-/sign-extends possible (otherwise we would be ex-
1196  // tending "self" bit values, which will have no effect, since "self" values
1197  // cannot be references to anything).
1198  putCell(RD, getCell(RS, Inputs), Outputs);
1199 
1200  RegisterCell Res;
1201  // Read RD's cell from the outputs instead of RS's cell from the inputs:
1202  if (F->second.Type == ExtType::SExt)
1203  Res = eSXT(getCell(RD, Outputs), EW);
1204  else if (F->second.Type == ExtType::ZExt)
1205  Res = eZXT(getCell(RD, Outputs), EW);
1206 
1207  putCell(RD, Res, Outputs);
1208  return true;
1209 }
1210 
1211 unsigned HexagonEvaluator::getNextPhysReg(unsigned PReg, unsigned Width) const {
1212  using namespace Hexagon;
1213 
1214  bool Is64 = DoubleRegsRegClass.contains(PReg);
1215  assert(PReg == 0 || Is64 || IntRegsRegClass.contains(PReg));
1216 
1217  static const unsigned Phys32[] = { R0, R1, R2, R3, R4, R5 };
1218  static const unsigned Phys64[] = { D0, D1, D2 };
1219  const unsigned Num32 = sizeof(Phys32)/sizeof(unsigned);
1220  const unsigned Num64 = sizeof(Phys64)/sizeof(unsigned);
1221 
1222  // Return the first parameter register of the required width.
1223  if (PReg == 0)
1224  return (Width <= 32) ? Phys32[0] : Phys64[0];
1225 
1226  // Set Idx32, Idx64 in such a way that Idx+1 would give the index of the
1227  // next register.
1228  unsigned Idx32 = 0, Idx64 = 0;
1229  if (!Is64) {
1230  while (Idx32 < Num32) {
1231  if (Phys32[Idx32] == PReg)
1232  break;
1233  Idx32++;
1234  }
1235  Idx64 = Idx32/2;
1236  } else {
1237  while (Idx64 < Num64) {
1238  if (Phys64[Idx64] == PReg)
1239  break;
1240  Idx64++;
1241  }
1242  Idx32 = Idx64*2+1;
1243  }
1244 
1245  if (Width <= 32)
1246  return (Idx32+1 < Num32) ? Phys32[Idx32+1] : 0;
1247  return (Idx64+1 < Num64) ? Phys64[Idx64+1] : 0;
1248 }
1249 
1250 unsigned HexagonEvaluator::getVirtRegFor(unsigned PReg) const {
1251  for (std::pair<unsigned,unsigned> P : MRI.liveins())
1252  if (P.first == PReg)
1253  return P.second;
1254  return 0;
1255 }
RegisterCell eASL(const RegisterCell &A1, uint16_t Sh) const
Definition: BitTracker.cpp:517
#define R4(n)
This class represents an incoming formal argument to a Function.
Definition: Argument.h:30
const TargetRegisterInfo & TRI
Definition: BitTracker.h:449
MachineBasicBlock * getMBB() const
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
RegisterCell & fill(uint16_t B, uint16_t E, const BitValue &V)
Definition: BitTracker.cpp:274
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
RegisterCell eASR(const RegisterCell &A1, uint16_t Sh) const
Definition: BitTracker.cpp:536
BitTracker::RegisterRef RegisterRef
void putCell(const RegisterRef &RR, RegisterCell RC, CellMapType &M) const
Definition: BitTracker.cpp:374
static RegisterCell self(unsigned Reg, uint16_t Width)
Definition: BitTracker.h:323
F(f)
BitTracker::BitMask mask(unsigned Reg, unsigned Sub) const override
MachineFrameInfo & MFI
#define R2(n)
const HexagonInstrInfo & TII
#define op(i)
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:332
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
RegisterCell eORL(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:569
HexagonEvaluator(const HexagonRegisterInfo &tri, MachineRegisterInfo &mri, const HexagonInstrInfo &tii, MachineFunction &mf)
bool evaluate(const MachineInstr &MI, const CellMapType &Inputs, CellMapType &Outputs) const override
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:191
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:293
BitTracker::CellMapType CellMapType
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:197
Reg
All possible values of the reg field in the ModR/M byte.
This file contains the simple types necessary to represent the attributes associated with functions a...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
RegisterCell eLSR(const RegisterCell &A1, uint16_t Sh) const
Definition: BitTracker.cpp:526
unsigned getID() const
Return the register class ID number.
#define im(i)
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:142
RegisterCell eADD(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:431
const TargetRegisterClass & composeWithSubRegIndex(const TargetRegisterClass &RC, unsigned Idx) const override
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
RegisterCell eCLB(const RegisterCell &A1, bool B, uint16_t W) const
Definition: BitTracker.cpp:642
const char * getName(unsigned RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register...
#define rc(i)
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
#define P(N)
RegisterCell eSUB(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:464
RegisterCell eIMM(int64_t V, uint16_t W) const
Definition: BitTracker.cpp:411
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
RegisterCell eNOT(const RegisterCell &A1) const
Definition: BitTracker.cpp:611
uint16_t getPhysRegBitWidth(unsigned Reg) const override
bool isPointerTy() const
True if this is an instance of PointerType.
Definition: Type.h:221
RegisterCell eAND(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:547
bool isCopy() const
Definition: MachineInstr.h:857
RegisterCell eINS(const RegisterCell &A1, const RegisterCell &A2, uint16_t AtN) const
Definition: BitTracker.cpp:694
BitTracker::RegisterCell RegisterCell
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
RegisterCell eMLS(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:497
uint16_t getRegBitWidth(const RegisterRef &RR) const
Definition: BitTracker.cpp:329
MachineFunction & MF
static BitValue self(const BitRef &Self=BitRef())
Definition: BitTracker.h:239
MachineOperand class - Representation of each machine instruction operand.
RegisterCell eXOR(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:591
RegisterCell eCTB(const RegisterCell &A1, bool B, uint16_t W) const
Definition: BitTracker.cpp:652
bool is(unsigned T) const
Definition: BitTracker.h:168
MachineRegisterInfo & MRI
Definition: BitTracker.h:450
int64_t getImm() const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:531
RegisterCell getCell(const RegisterRef &RR, const CellMapType &M) const
Definition: BitTracker.cpp:347
ArrayRef< std::pair< unsigned, unsigned > > liveins() const
RegisterCell & insert(const RegisterCell &RC, const BitMask &M)
Definition: BitTracker.cpp:214
amdgpu Simplify well known AMD library false Value Value * Arg
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:59
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
RegisterCell & cat(const RegisterCell &RC)
Definition: BitTracker.cpp:282
unsigned getIntegerBitWidth() const
Definition: DerivedTypes.h:97
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1213
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
RegisterCell eXTR(const RegisterCell &A1, uint16_t B, uint16_t E) const
Definition: BitTracker.cpp:682
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:626
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
RegisterCell eSXT(const RegisterCell &A1, uint16_t FromN) const
Definition: BitTracker.cpp:662
RegisterCell eMLU(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:507
A vector that has set insertion semantics.
Definition: SetVector.h:41
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:235
RegisterCell eZXT(const RegisterCell &A1, uint16_t FromN) const
Definition: BitTracker.cpp:673
bool meet(const RegisterCell &RC, unsigned SelfR)
Definition: BitTracker.cpp:201
IRTranslator LLVM IR MI
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
static RegisterCell ref(const RegisterCell &C)
Definition: BitTracker.h:339
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
iterator_range< arg_iterator > args()
Definition: Function.h:621
static BitValue ref(const BitValue &V)
Definition: BitTracker.h:230