LLVM  7.0.0svn
SystemZAsmPrinter.cpp
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1 //===-- SystemZAsmPrinter.cpp - SystemZ LLVM assembly printer -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Streams SystemZ assembly language and associated data, in the form of
11 // MCInsts and MCExprs respectively.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "SystemZAsmPrinter.h"
18 #include "SystemZMCInstLower.h"
21 #include "llvm/IR/Mangler.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInstBuilder.h"
24 #include "llvm/MC/MCStreamer.h"
26 
27 using namespace llvm;
28 
29 // Return an RI instruction like MI with opcode Opcode, but with the
30 // GR64 register operands turned into GR32s.
31 static MCInst lowerRILow(const MachineInstr *MI, unsigned Opcode) {
32  if (MI->isCompare())
33  return MCInstBuilder(Opcode)
35  .addImm(MI->getOperand(1).getImm());
36  else
37  return MCInstBuilder(Opcode)
40  .addImm(MI->getOperand(2).getImm());
41 }
42 
43 // Return an RI instruction like MI with opcode Opcode, but with the
44 // GR64 register operands turned into GRH32s.
45 static MCInst lowerRIHigh(const MachineInstr *MI, unsigned Opcode) {
46  if (MI->isCompare())
47  return MCInstBuilder(Opcode)
49  .addImm(MI->getOperand(1).getImm());
50  else
51  return MCInstBuilder(Opcode)
54  .addImm(MI->getOperand(2).getImm());
55 }
56 
57 // Return an RI instruction like MI with opcode Opcode, but with the
58 // R2 register turned into a GR64.
59 static MCInst lowerRIEfLow(const MachineInstr *MI, unsigned Opcode) {
60  return MCInstBuilder(Opcode)
61  .addReg(MI->getOperand(0).getReg())
62  .addReg(MI->getOperand(1).getReg())
63  .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg()))
64  .addImm(MI->getOperand(3).getImm())
65  .addImm(MI->getOperand(4).getImm())
66  .addImm(MI->getOperand(5).getImm());
67 }
68 
70  StringRef Name = "__tls_get_offset";
71  return MCSymbolRefExpr::create(Context.getOrCreateSymbol(Name),
73  Context);
74 }
75 
77  StringRef Name = "_GLOBAL_OFFSET_TABLE_";
78  return MCSymbolRefExpr::create(Context.getOrCreateSymbol(Name),
80  Context);
81 }
82 
83 // MI loads the high part of a vector from memory. Return an instruction
84 // that uses replicating vector load Opcode to do the same thing.
85 static MCInst lowerSubvectorLoad(const MachineInstr *MI, unsigned Opcode) {
86  return MCInstBuilder(Opcode)
88  .addReg(MI->getOperand(1).getReg())
89  .addImm(MI->getOperand(2).getImm())
90  .addReg(MI->getOperand(3).getReg());
91 }
92 
93 // MI stores the high part of a vector to memory. Return an instruction
94 // that uses elemental vector store Opcode to do the same thing.
95 static MCInst lowerSubvectorStore(const MachineInstr *MI, unsigned Opcode) {
96  return MCInstBuilder(Opcode)
98  .addReg(MI->getOperand(1).getReg())
99  .addImm(MI->getOperand(2).getImm())
100  .addReg(MI->getOperand(3).getReg())
101  .addImm(0);
102 }
103 
106  MCInst LoweredMI;
107  switch (MI->getOpcode()) {
108  case SystemZ::Return:
109  LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R14D);
110  break;
111 
112  case SystemZ::CondReturn:
113  LoweredMI = MCInstBuilder(SystemZ::BCR)
114  .addImm(MI->getOperand(0).getImm())
115  .addImm(MI->getOperand(1).getImm())
116  .addReg(SystemZ::R14D);
117  break;
118 
119  case SystemZ::CRBReturn:
120  LoweredMI = MCInstBuilder(SystemZ::CRB)
121  .addReg(MI->getOperand(0).getReg())
122  .addReg(MI->getOperand(1).getReg())
123  .addImm(MI->getOperand(2).getImm())
124  .addReg(SystemZ::R14D)
125  .addImm(0);
126  break;
127 
128  case SystemZ::CGRBReturn:
129  LoweredMI = MCInstBuilder(SystemZ::CGRB)
130  .addReg(MI->getOperand(0).getReg())
131  .addReg(MI->getOperand(1).getReg())
132  .addImm(MI->getOperand(2).getImm())
133  .addReg(SystemZ::R14D)
134  .addImm(0);
135  break;
136 
137  case SystemZ::CIBReturn:
138  LoweredMI = MCInstBuilder(SystemZ::CIB)
139  .addReg(MI->getOperand(0).getReg())
140  .addImm(MI->getOperand(1).getImm())
141  .addImm(MI->getOperand(2).getImm())
142  .addReg(SystemZ::R14D)
143  .addImm(0);
144  break;
145 
146  case SystemZ::CGIBReturn:
147  LoweredMI = MCInstBuilder(SystemZ::CGIB)
148  .addReg(MI->getOperand(0).getReg())
149  .addImm(MI->getOperand(1).getImm())
150  .addImm(MI->getOperand(2).getImm())
151  .addReg(SystemZ::R14D)
152  .addImm(0);
153  break;
154 
155  case SystemZ::CLRBReturn:
156  LoweredMI = MCInstBuilder(SystemZ::CLRB)
157  .addReg(MI->getOperand(0).getReg())
158  .addReg(MI->getOperand(1).getReg())
159  .addImm(MI->getOperand(2).getImm())
160  .addReg(SystemZ::R14D)
161  .addImm(0);
162  break;
163 
164  case SystemZ::CLGRBReturn:
165  LoweredMI = MCInstBuilder(SystemZ::CLGRB)
166  .addReg(MI->getOperand(0).getReg())
167  .addReg(MI->getOperand(1).getReg())
168  .addImm(MI->getOperand(2).getImm())
169  .addReg(SystemZ::R14D)
170  .addImm(0);
171  break;
172 
173  case SystemZ::CLIBReturn:
174  LoweredMI = MCInstBuilder(SystemZ::CLIB)
175  .addReg(MI->getOperand(0).getReg())
176  .addImm(MI->getOperand(1).getImm())
177  .addImm(MI->getOperand(2).getImm())
178  .addReg(SystemZ::R14D)
179  .addImm(0);
180  break;
181 
182  case SystemZ::CLGIBReturn:
183  LoweredMI = MCInstBuilder(SystemZ::CLGIB)
184  .addReg(MI->getOperand(0).getReg())
185  .addImm(MI->getOperand(1).getImm())
186  .addImm(MI->getOperand(2).getImm())
187  .addReg(SystemZ::R14D)
188  .addImm(0);
189  break;
190 
191  case SystemZ::CallBRASL:
192  LoweredMI = MCInstBuilder(SystemZ::BRASL)
193  .addReg(SystemZ::R14D)
194  .addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_PLT));
195  break;
196 
197  case SystemZ::CallBASR:
198  LoweredMI = MCInstBuilder(SystemZ::BASR)
199  .addReg(SystemZ::R14D)
200  .addReg(MI->getOperand(0).getReg());
201  break;
202 
203  case SystemZ::CallJG:
204  LoweredMI = MCInstBuilder(SystemZ::JG)
205  .addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_PLT));
206  break;
207 
208  case SystemZ::CallBRCL:
209  LoweredMI = MCInstBuilder(SystemZ::BRCL)
210  .addImm(MI->getOperand(0).getImm())
211  .addImm(MI->getOperand(1).getImm())
212  .addExpr(Lower.getExpr(MI->getOperand(2), MCSymbolRefExpr::VK_PLT));
213  break;
214 
215  case SystemZ::CallBR:
216  LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R1D);
217  break;
218 
219  case SystemZ::CallBCR:
220  LoweredMI = MCInstBuilder(SystemZ::BCR)
221  .addImm(MI->getOperand(0).getImm())
222  .addImm(MI->getOperand(1).getImm())
223  .addReg(SystemZ::R1D);
224  break;
225 
226  case SystemZ::CRBCall:
227  LoweredMI = MCInstBuilder(SystemZ::CRB)
228  .addReg(MI->getOperand(0).getReg())
229  .addReg(MI->getOperand(1).getReg())
230  .addImm(MI->getOperand(2).getImm())
231  .addReg(SystemZ::R1D)
232  .addImm(0);
233  break;
234 
235  case SystemZ::CGRBCall:
236  LoweredMI = MCInstBuilder(SystemZ::CGRB)
237  .addReg(MI->getOperand(0).getReg())
238  .addReg(MI->getOperand(1).getReg())
239  .addImm(MI->getOperand(2).getImm())
240  .addReg(SystemZ::R1D)
241  .addImm(0);
242  break;
243 
244  case SystemZ::CIBCall:
245  LoweredMI = MCInstBuilder(SystemZ::CIB)
246  .addReg(MI->getOperand(0).getReg())
247  .addImm(MI->getOperand(1).getImm())
248  .addImm(MI->getOperand(2).getImm())
249  .addReg(SystemZ::R1D)
250  .addImm(0);
251  break;
252 
253  case SystemZ::CGIBCall:
254  LoweredMI = MCInstBuilder(SystemZ::CGIB)
255  .addReg(MI->getOperand(0).getReg())
256  .addImm(MI->getOperand(1).getImm())
257  .addImm(MI->getOperand(2).getImm())
258  .addReg(SystemZ::R1D)
259  .addImm(0);
260  break;
261 
262  case SystemZ::CLRBCall:
263  LoweredMI = MCInstBuilder(SystemZ::CLRB)
264  .addReg(MI->getOperand(0).getReg())
265  .addReg(MI->getOperand(1).getReg())
266  .addImm(MI->getOperand(2).getImm())
267  .addReg(SystemZ::R1D)
268  .addImm(0);
269  break;
270 
271  case SystemZ::CLGRBCall:
272  LoweredMI = MCInstBuilder(SystemZ::CLGRB)
273  .addReg(MI->getOperand(0).getReg())
274  .addReg(MI->getOperand(1).getReg())
275  .addImm(MI->getOperand(2).getImm())
276  .addReg(SystemZ::R1D)
277  .addImm(0);
278  break;
279 
280  case SystemZ::CLIBCall:
281  LoweredMI = MCInstBuilder(SystemZ::CLIB)
282  .addReg(MI->getOperand(0).getReg())
283  .addImm(MI->getOperand(1).getImm())
284  .addImm(MI->getOperand(2).getImm())
285  .addReg(SystemZ::R1D)
286  .addImm(0);
287  break;
288 
289  case SystemZ::CLGIBCall:
290  LoweredMI = MCInstBuilder(SystemZ::CLGIB)
291  .addReg(MI->getOperand(0).getReg())
292  .addImm(MI->getOperand(1).getImm())
293  .addImm(MI->getOperand(2).getImm())
294  .addReg(SystemZ::R1D)
295  .addImm(0);
296  break;
297 
298  case SystemZ::TLS_GDCALL:
299  LoweredMI = MCInstBuilder(SystemZ::BRASL)
300  .addReg(SystemZ::R14D)
303  break;
304 
305  case SystemZ::TLS_LDCALL:
306  LoweredMI = MCInstBuilder(SystemZ::BRASL)
307  .addReg(SystemZ::R14D)
310  break;
311 
312  case SystemZ::GOT:
313  LoweredMI = MCInstBuilder(SystemZ::LARL)
314  .addReg(MI->getOperand(0).getReg())
315  .addExpr(getGlobalOffsetTable(MF->getContext()));
316  break;
317 
318  case SystemZ::IILF64:
319  LoweredMI = MCInstBuilder(SystemZ::IILF)
321  .addImm(MI->getOperand(2).getImm());
322  break;
323 
324  case SystemZ::IIHF64:
325  LoweredMI = MCInstBuilder(SystemZ::IIHF)
327  .addImm(MI->getOperand(2).getImm());
328  break;
329 
330  case SystemZ::RISBHH:
331  case SystemZ::RISBHL:
332  LoweredMI = lowerRIEfLow(MI, SystemZ::RISBHG);
333  break;
334 
335  case SystemZ::RISBLH:
336  case SystemZ::RISBLL:
337  LoweredMI = lowerRIEfLow(MI, SystemZ::RISBLG);
338  break;
339 
340  case SystemZ::VLVGP32:
341  LoweredMI = MCInstBuilder(SystemZ::VLVGP)
342  .addReg(MI->getOperand(0).getReg())
343  .addReg(SystemZMC::getRegAsGR64(MI->getOperand(1).getReg()))
345  break;
346 
347  case SystemZ::VLR32:
348  case SystemZ::VLR64:
349  LoweredMI = MCInstBuilder(SystemZ::VLR)
352  break;
353 
354  case SystemZ::VL32:
355  LoweredMI = lowerSubvectorLoad(MI, SystemZ::VLREPF);
356  break;
357 
358  case SystemZ::VL64:
359  LoweredMI = lowerSubvectorLoad(MI, SystemZ::VLREPG);
360  break;
361 
362  case SystemZ::VST32:
363  LoweredMI = lowerSubvectorStore(MI, SystemZ::VSTEF);
364  break;
365 
366  case SystemZ::VST64:
367  LoweredMI = lowerSubvectorStore(MI, SystemZ::VSTEG);
368  break;
369 
370  case SystemZ::LFER:
371  LoweredMI = MCInstBuilder(SystemZ::VLGVF)
374  .addReg(0).addImm(0);
375  break;
376 
377  case SystemZ::LEFR:
378  LoweredMI = MCInstBuilder(SystemZ::VLVGF)
381  .addReg(MI->getOperand(1).getReg())
382  .addReg(0).addImm(0);
383  break;
384 
385 #define LOWER_LOW(NAME) \
386  case SystemZ::NAME##64: LoweredMI = lowerRILow(MI, SystemZ::NAME); break
387 
388  LOWER_LOW(IILL);
389  LOWER_LOW(IILH);
390  LOWER_LOW(TMLL);
391  LOWER_LOW(TMLH);
392  LOWER_LOW(NILL);
393  LOWER_LOW(NILH);
394  LOWER_LOW(NILF);
395  LOWER_LOW(OILL);
396  LOWER_LOW(OILH);
397  LOWER_LOW(OILF);
398  LOWER_LOW(XILF);
399 
400 #undef LOWER_LOW
401 
402 #define LOWER_HIGH(NAME) \
403  case SystemZ::NAME##64: LoweredMI = lowerRIHigh(MI, SystemZ::NAME); break
404 
405  LOWER_HIGH(IIHL);
406  LOWER_HIGH(IIHH);
407  LOWER_HIGH(TMHL);
408  LOWER_HIGH(TMHH);
409  LOWER_HIGH(NIHL);
410  LOWER_HIGH(NIHH);
411  LOWER_HIGH(NIHF);
412  LOWER_HIGH(OIHL);
413  LOWER_HIGH(OIHH);
414  LOWER_HIGH(OIHF);
415  LOWER_HIGH(XIHF);
416 
417 #undef LOWER_HIGH
418 
419  case SystemZ::Serialize:
421  LoweredMI = MCInstBuilder(SystemZ::BCRAsm)
422  .addImm(14).addReg(SystemZ::R0D);
423  else
424  LoweredMI = MCInstBuilder(SystemZ::BCRAsm)
425  .addImm(15).addReg(SystemZ::R0D);
426  break;
427 
428  // Emit nothing here but a comment if we can.
429  case SystemZ::MemBarrier:
430  OutStreamer->emitRawComment("MEMBARRIER");
431  return;
432 
433  // We want to emit "j .+2" for traps, jumping to the relative immediate field
434  // of the jump instruction, which is an illegal instruction. We cannot emit a
435  // "." symbol, so create and emit a temp label before the instruction and use
436  // that instead.
437  case SystemZ::Trap: {
439  OutStreamer->EmitLabel(DotSym);
440 
441  const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(DotSym, OutContext);
442  const MCConstantExpr *ConstExpr = MCConstantExpr::create(2, OutContext);
443  LoweredMI = MCInstBuilder(SystemZ::J)
444  .addExpr(MCBinaryExpr::createAdd(Expr, ConstExpr, OutContext));
445  }
446  break;
447 
448  // Conditional traps will create a branch on condition instruction that jumps
449  // to the relative immediate field of the jump instruction. (eg. "jo .+2")
450  case SystemZ::CondTrap: {
452  OutStreamer->EmitLabel(DotSym);
453 
454  const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(DotSym, OutContext);
455  const MCConstantExpr *ConstExpr = MCConstantExpr::create(2, OutContext);
456  LoweredMI = MCInstBuilder(SystemZ::BRC)
457  .addImm(MI->getOperand(0).getImm())
458  .addImm(MI->getOperand(1).getImm())
459  .addExpr(MCBinaryExpr::createAdd(Expr, ConstExpr, OutContext));
460  }
461  break;
462 
463  case TargetOpcode::STACKMAP:
464  LowerSTACKMAP(*MI);
465  return;
466 
467  case TargetOpcode::PATCHPOINT:
468  LowerPATCHPOINT(*MI, Lower);
469  return;
470 
471  default:
472  Lower.lower(MI, LoweredMI);
473  break;
474  }
475  EmitToStreamer(*OutStreamer, LoweredMI);
476 }
477 
478 
479 // Emit the largest nop instruction smaller than or equal to NumBytes
480 // bytes. Return the size of nop emitted.
482  unsigned NumBytes, const MCSubtargetInfo &STI) {
483  if (NumBytes < 2) {
484  llvm_unreachable("Zero nops?");
485  return 0;
486  }
487  else if (NumBytes < 4) {
488  OutStreamer.EmitInstruction(MCInstBuilder(SystemZ::BCRAsm)
489  .addImm(0).addReg(SystemZ::R0D), STI);
490  return 2;
491  }
492  else if (NumBytes < 6) {
493  OutStreamer.EmitInstruction(MCInstBuilder(SystemZ::BCAsm)
494  .addImm(0).addReg(0).addImm(0).addReg(0),
495  STI);
496  return 4;
497  }
498  else {
499  MCSymbol *DotSym = OutContext.createTempSymbol();
500  const MCSymbolRefExpr *Dot = MCSymbolRefExpr::create(DotSym, OutContext);
501  OutStreamer.EmitInstruction(MCInstBuilder(SystemZ::BRCLAsm)
502  .addImm(0).addExpr(Dot), STI);
503  OutStreamer.EmitLabel(DotSym);
504  return 6;
505  }
506 }
507 
508 void SystemZAsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
509  const SystemZInstrInfo *TII =
510  static_cast<const SystemZInstrInfo *>(MF->getSubtarget().getInstrInfo());
511 
512  unsigned NumNOPBytes = MI.getOperand(1).getImm();
513 
514  SM.recordStackMap(MI);
515  assert(NumNOPBytes % 2 == 0 && "Invalid number of NOP bytes requested!");
516 
517  // Scan ahead to trim the shadow.
518  unsigned ShadowBytes = 0;
519  const MachineBasicBlock &MBB = *MI.getParent();
521  ++MII;
522  while (ShadowBytes < NumNOPBytes) {
523  if (MII == MBB.end() ||
524  MII->getOpcode() == TargetOpcode::PATCHPOINT ||
525  MII->getOpcode() == TargetOpcode::STACKMAP)
526  break;
527  ShadowBytes += TII->getInstSizeInBytes(*MII);
528  if (MII->isCall())
529  break;
530  ++MII;
531  }
532 
533  // Emit nops.
534  while (ShadowBytes < NumNOPBytes)
535  ShadowBytes += EmitNop(OutContext, *OutStreamer, NumNOPBytes - ShadowBytes,
536  getSubtargetInfo());
537 }
538 
539 // Lower a patchpoint of the form:
540 // [<def>], <id>, <numBytes>, <target>, <numArgs>
541 void SystemZAsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
543  SM.recordPatchPoint(MI);
544  PatchPointOpers Opers(&MI);
545 
546  unsigned EncodedBytes = 0;
547  const MachineOperand &CalleeMO = Opers.getCallTarget();
548 
549  if (CalleeMO.isImm()) {
550  uint64_t CallTarget = CalleeMO.getImm();
551  if (CallTarget) {
552  unsigned ScratchIdx = -1;
553  unsigned ScratchReg = 0;
554  do {
555  ScratchIdx = Opers.getNextScratchIdx(ScratchIdx + 1);
556  ScratchReg = MI.getOperand(ScratchIdx).getReg();
557  } while (ScratchReg == SystemZ::R0D);
558 
559  // Materialize the call target address
560  EmitToStreamer(*OutStreamer, MCInstBuilder(SystemZ::LLILF)
561  .addReg(ScratchReg)
562  .addImm(CallTarget & 0xFFFFFFFF));
563  EncodedBytes += 6;
564  if (CallTarget >> 32) {
565  EmitToStreamer(*OutStreamer, MCInstBuilder(SystemZ::IIHF)
566  .addReg(ScratchReg)
567  .addImm(CallTarget >> 32));
568  EncodedBytes += 6;
569  }
570 
571  EmitToStreamer(*OutStreamer, MCInstBuilder(SystemZ::BASR)
572  .addReg(SystemZ::R14D)
573  .addReg(ScratchReg));
574  EncodedBytes += 2;
575  }
576  } else if (CalleeMO.isGlobal()) {
577  const MCExpr *Expr = Lower.getExpr(CalleeMO, MCSymbolRefExpr::VK_PLT);
578  EmitToStreamer(*OutStreamer, MCInstBuilder(SystemZ::BRASL)
579  .addReg(SystemZ::R14D)
580  .addExpr(Expr));
581  EncodedBytes += 6;
582  }
583 
584  // Emit padding.
585  unsigned NumBytes = Opers.getNumPatchBytes();
586  assert(NumBytes >= EncodedBytes &&
587  "Patchpoint can't request size less than the length of a call.");
588  assert((NumBytes - EncodedBytes) % 2 == 0 &&
589  "Invalid number of NOP bytes requested!");
590  while (EncodedBytes < NumBytes)
591  EncodedBytes += EmitNop(OutContext, *OutStreamer, NumBytes - EncodedBytes,
592  getSubtargetInfo());
593 }
594 
595 // Convert a SystemZ-specific constant pool modifier into the associated
596 // MCSymbolRefExpr variant kind.
599  switch (Modifier) {
604  }
605  llvm_unreachable("Invalid SystemCPModifier!");
606 }
607 
610  auto *ZCPV = static_cast<SystemZConstantPoolValue*>(MCPV);
611 
612  const MCExpr *Expr =
613  MCSymbolRefExpr::create(getSymbol(ZCPV->getGlobalValue()),
614  getModifierVariantKind(ZCPV->getModifier()),
615  OutContext);
616  uint64_t Size = getDataLayout().getTypeAllocSize(ZCPV->getType());
617 
618  OutStreamer->EmitValue(Expr, Size);
619 }
620 
622  unsigned OpNo,
623  unsigned AsmVariant,
624  const char *ExtraCode,
625  raw_ostream &OS) {
626  if (ExtraCode && *ExtraCode == 'n') {
627  if (!MI->getOperand(OpNo).isImm())
628  return true;
629  OS << -int64_t(MI->getOperand(OpNo).getImm());
630  } else {
632  MCOperand MO(Lower.lowerOperand(MI->getOperand(OpNo)));
634  }
635  return false;
636 }
637 
639  unsigned OpNo,
640  unsigned AsmVariant,
641  const char *ExtraCode,
642  raw_ostream &OS) {
644  MI->getOperand(OpNo + 1).getImm(),
645  MI->getOperand(OpNo + 2).getReg(), OS);
646  return false;
647 }
648 
651 }
652 
653 // Force static initialization.
656 }
#define LOWER_LOW(NAME)
void EmitEndOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the end of their file...
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
unsigned getNextScratchIdx(unsigned StartIdx=0) const
Get the next scratch register operand index.
Definition: StackMaps.cpp:70
LLVMContext & Context
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:93
static void printAddress(unsigned Base, int64_t Disp, unsigned Index, raw_ostream &O)
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:321
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:88
bool hasFastSerialization() const
const MCSubtargetInfo & getSubtargetInfo() const
Return information about subtarget.
Definition: AsmPrinter.cpp:222
unsigned getReg() const
getReg - Returns the register number.
void LLVMInitializeSystemZAsmPrinter()
static unsigned EmitNop(MCContext &OutContext, MCStreamer &OutStreamer, unsigned NumBytes, const MCSubtargetInfo &STI)
MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:96
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, bool PrintSchedInfo=false)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:907
static MCInst lowerSubvectorLoad(const MachineInstr *MI, unsigned Opcode)
unsigned getRegAsGRH32(unsigned Reg)
const HexagonInstrInfo * TII
unsigned getRegAsGR32(unsigned Reg)
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:166
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:311
void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override
Context object for machine code objects.
Definition: MCContext.h:63
RegisterAsmPrinter - Helper template for registering a target specific assembly printer, for use in the target machine initialization function.
virtual const TargetInstrInfo * getInstrInfo() const
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:459
MCInstBuilder & addExpr(const MCExpr *Val)
Add a new MCExpr operand.
Definition: MCInstBuilder.h:50
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
MCOperand lowerOperand(const MachineOperand &MO) const
MCContext & getContext() const
static MCInst lowerSubvectorStore(const MachineInstr *MI, unsigned Opcode)
Streaming machine code generation interface.
Definition: MCStreamer.h:183
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
Definition: MCInstBuilder.h:32
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:590
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
Definition: MCContext.cpp:217
const MCAsmInfo * MAI
Target Asm Printer information.
Definition: AsmPrinter.h:84
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
Definition: MachineInstr.h:546
static MCInst lowerRIEfLow(const MachineInstr *MI, unsigned Opcode)
static MCInst lowerRIHigh(const MachineInstr *MI, unsigned Opcode)
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Definition: MCInstBuilder.h:38
MI-level patchpoint operands.
Definition: StackMaps.h:77
Abstract base class for all machine specific constantpool value subclasses.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static const MCSymbolRefExpr * getTLSGetOffset(MCContext &Context)
void recordPatchPoint(const MachineInstr &MI)
Generate a stackmap record for a patchpoint instruction.
Definition: StackMaps.cpp:374
void serializeToStackMapSection()
If there is any stack map data, create a stack map section and serialize the map info into it...
Definition: StackMaps.cpp:550
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &OS) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant...
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
MCSymbol * getSymbol(const GlobalValue *GV) const
Definition: AsmPrinter.cpp:426
MachineOperand class - Representation of each machine instruction operand.
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &OS) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
Definition: AsmPrinter.cpp:227
static MCSymbolRefExpr::VariantKind getModifierVariantKind(SystemZCP::SystemZCPModifier Modifier)
unsigned getRegAsGR64(unsigned Reg)
unsigned getRegAsVR128(unsigned Reg)
int64_t getImm() const
static MCInst lowerRILow(const MachineInstr *MI, unsigned Opcode)
void recordStackMap(const MachineInstr &MI)
Generate a stackmap record for a stackmap instruction.
Definition: StackMaps.cpp:365
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:156
Target & getTheSystemZTarget()
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:428
Representation of each machine instruction.
Definition: MachineInstr.h:60
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:123
void EmitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
static const MCSymbolRefExpr * getGlobalOffsetTable(MCContext &Context)
Generic base class for all target subtargets.
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given patchpoint should emit.
Definition: StackMaps.h:105
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static void printOperand(const MCOperand &MO, const MCAsmInfo *MAI, raw_ostream &O)
#define LOWER_HIGH(NAME)
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
virtual void EmitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:322
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
A SystemZ-specific constant pool value.
const DataLayout & getDataLayout() const
Return information about data layout.
Definition: AsmPrinter.cpp:212
IRTranslator LLVM IR MI
const MachineOperand & getCallTarget() const
Returns the target of the underlying call.
Definition: StackMaps.h:110
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:316
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35
const MCExpr * getExpr(const MachineOperand &MO, MCSymbolRefExpr::VariantKind Kind) const
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:164