LLVM  9.0.0svn
MipsRegisterBankInfo.cpp
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1 //===- MipsRegisterBankInfo.cpp ---------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the targeting of the RegisterBankInfo class for Mips.
10 /// \todo This should be generated by TableGen.
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsInstrInfo.h"
14 #include "MipsRegisterBankInfo.h"
16 
17 #define GET_TARGET_REGBANK_IMPL
18 
19 #define DEBUG_TYPE "registerbankinfo"
20 
21 #include "MipsGenRegisterBank.inc"
22 
23 namespace llvm {
24 namespace Mips {
28 };
29 
31  {0, 32, GPRBRegBank}
32 };
33 
34 enum ValueMappingIdx { InvalidIdx = 0, GPRIdx = 1 };
35 
37  // invalid
38  {nullptr, 0},
39  // 3 operands in GPRs
40  {&PartMappings[PMI_GPR - PMI_Min], 1},
41  {&PartMappings[PMI_GPR - PMI_Min], 1},
42  {&PartMappings[PMI_GPR - PMI_Min], 1}};
43 
44 } // end namespace Mips
45 } // end namespace llvm
46 
47 using namespace llvm;
48 
51 
53  const TargetRegisterClass &RC) const {
54  using namespace Mips;
55 
56  switch (RC.getID()) {
57  case Mips::GPR32RegClassID:
58  case Mips::CPU16Regs_and_GPRMM16ZeroRegClassID:
59  case Mips::GPRMM16MovePPairFirstRegClassID:
60  case Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID:
61  case Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID:
62  case Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID:
63  case Mips::SP32RegClassID:
64  return getRegBank(Mips::GPRBRegBankID);
65  default:
66  llvm_unreachable("Register class not supported");
67  }
68 }
69 
72 
73  unsigned Opc = MI.getOpcode();
74 
76  if (Mapping.isValid())
77  return Mapping;
78 
79  using namespace TargetOpcode;
80 
81  unsigned NumOperands = MI.getNumOperands();
82  const ValueMapping *OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
83 
84  switch (Opc) {
85  case G_TRUNC:
86  case G_ADD:
87  case G_SUB:
88  case G_MUL:
89  case G_UMULH:
90  case G_LOAD:
91  case G_STORE:
92  case G_ZEXTLOAD:
93  case G_SEXTLOAD:
94  case G_GEP:
95  case G_AND:
96  case G_OR:
97  case G_XOR:
98  case G_SHL:
99  case G_ASHR:
100  case G_LSHR:
101  case G_SDIV:
102  case G_UDIV:
103  case G_SREM:
104  case G_UREM:
105  OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
106  break;
107  case G_CONSTANT:
108  case G_FRAME_INDEX:
109  case G_GLOBAL_VALUE:
110  case G_BRCOND:
111  OperandsMapping =
113  break;
114  case G_ICMP:
115  OperandsMapping =
118  &Mips::ValueMappings[Mips::GPRIdx]});
119  break;
120  case G_SELECT:
121  OperandsMapping =
124  &Mips::ValueMappings[Mips::GPRIdx],
125  &Mips::ValueMappings[Mips::GPRIdx]});
126  break;
127  default:
129  }
130 
131  return getInstructionMapping(DefaultMappingID, /*Cost=*/1, OperandsMapping,
132  NumOperands);
133 }
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
RegisterBankInfo::ValueMapping ValueMappings[]
Helper class that represents how the value of an instruction may be mapped and what is the related co...
unsigned const TargetRegisterInfo * TRI
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:411
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
unsigned getID() const
Return the register class ID number.
This file declares the targeting of the RegisterBankInfo class for Mips.
const InstructionMapping & getInvalidInstructionMapping() const
Method to get a uniquely generated invalid InstructionMapping.
Helper struct that represents how a value is partially mapped into a register.
RegisterBankInfo::PartialMapping PartMappings[]
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isValid() const
Check whether this object is valid.
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
This class implements the register bank concept.
Definition: RegisterBank.h:28
Helper struct that represents how a value is mapped through different register banks.
Representation of each machine instruction.
Definition: MachineInstr.h:63
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
MipsRegisterBankInfo(const TargetRegisterInfo &TRI)
IRTranslator LLVM IR MI
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC) const override
Get a register bank that covers RC.