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AVRRegisterInfo.cpp
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1 //===-- AVRRegisterInfo.cpp - AVR Register Information --------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the AVR implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AVRRegisterInfo.h"
15 
16 #include "llvm/ADT/BitVector.h"
20 #include "llvm/IR/Function.h"
22 
23 #include "AVR.h"
24 #include "AVRInstrInfo.h"
25 #include "AVRTargetMachine.h"
27 
28 #define GET_REGINFO_TARGET_DESC
29 #include "AVRGenRegisterInfo.inc"
30 
31 namespace llvm {
32 
34 
35 const uint16_t *
38 
39  return ((CC == CallingConv::AVR_INTR || CC == CallingConv::AVR_SIGNAL)
40  ? CSR_Interrupts_SaveList
41  : CSR_Normal_SaveList);
42 }
43 
44 const uint32_t *
46  CallingConv::ID CC) const {
47  return ((CC == CallingConv::AVR_INTR || CC == CallingConv::AVR_SIGNAL)
48  ? CSR_Interrupts_RegMask
49  : CSR_Normal_RegMask);
50 }
51 
53  BitVector Reserved(getNumRegs());
54 
55  // Reserve the intermediate result registers r1 and r2
56  // The result of instructions like 'mul' is always stored here.
57  Reserved.set(AVR::R0);
58  Reserved.set(AVR::R1);
59  Reserved.set(AVR::R1R0);
60 
61  // Reserve the stack pointer.
62  Reserved.set(AVR::SPL);
63  Reserved.set(AVR::SPH);
64  Reserved.set(AVR::SP);
65 
66  // We tenatively reserve the frame pointer register r29:r28 because the
67  // function may require one, but we cannot tell until register allocation
68  // is complete, which can be too late.
69  //
70  // Instead we just unconditionally reserve the Y register.
71  //
72  // TODO: Write a pass to enumerate functions which reserved the Y register
73  // but didn't end up needing a frame pointer. In these, we can
74  // convert one or two of the spills inside to use the Y register.
75  Reserved.set(AVR::R28);
76  Reserved.set(AVR::R29);
77  Reserved.set(AVR::R29R28);
78 
79  return Reserved;
80 }
81 
82 const TargetRegisterClass *
84  const MachineFunction &MF) const {
86  if (TRI->isTypeLegalForClass(*RC, MVT::i16)) {
87  return &AVR::DREGSRegClass;
88  }
89 
90  if (TRI->isTypeLegalForClass(*RC, MVT::i8)) {
91  return &AVR::GPR8RegClass;
92  }
93 
94  llvm_unreachable("Invalid register size");
95 }
96 
97 /// Fold a frame offset shared between two add instructions into a single one.
98 static void foldFrameOffset(MachineBasicBlock::iterator &II, int &Offset, unsigned DstReg) {
99  MachineInstr &MI = *II;
100  int Opcode = MI.getOpcode();
101 
102  // Don't bother trying if the next instruction is not an add or a sub.
103  if ((Opcode != AVR::SUBIWRdK) && (Opcode != AVR::ADIWRdK)) {
104  return;
105  }
106 
107  // Check that DstReg matches with next instruction, otherwise the instruction
108  // is not related to stack address manipulation.
109  if (DstReg != MI.getOperand(0).getReg()) {
110  return;
111  }
112 
113  // Add the offset in the next instruction to our offset.
114  switch (Opcode) {
115  case AVR::SUBIWRdK:
116  Offset += -MI.getOperand(2).getImm();
117  break;
118  case AVR::ADIWRdK:
119  Offset += MI.getOperand(2).getImm();
120  break;
121  }
122 
123  // Finally remove the instruction.
124  II++;
125  MI.eraseFromParent();
126 }
127 
129  int SPAdj, unsigned FIOperandNum,
130  RegScavenger *RS) const {
131  assert(SPAdj == 0 && "Unexpected SPAdj value");
132 
133  MachineInstr &MI = *II;
134  DebugLoc dl = MI.getDebugLoc();
135  MachineBasicBlock &MBB = *MI.getParent();
136  const MachineFunction &MF = *MBB.getParent();
137  const AVRTargetMachine &TM = (const AVRTargetMachine &)MF.getTarget();
139  const MachineFrameInfo &MFI = MF.getFrameInfo();
141  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
142  int Offset = MFI.getObjectOffset(FrameIndex);
143 
144  // Add one to the offset because SP points to an empty slot.
145  Offset += MFI.getStackSize() - TFI->getOffsetOfLocalArea() + 1;
146  // Fold incoming offset.
147  Offset += MI.getOperand(FIOperandNum + 1).getImm();
148 
149  // This is actually "load effective address" of the stack slot
150  // instruction. We have only two-address instructions, thus we need to
151  // expand it into move + add.
152  if (MI.getOpcode() == AVR::FRMIDX) {
153  MI.setDesc(TII.get(AVR::MOVWRdRr));
154  MI.getOperand(FIOperandNum).ChangeToRegister(AVR::R29R28, false);
155 
156  assert(Offset > 0 && "Invalid offset");
157 
158  // We need to materialize the offset via an add instruction.
159  unsigned Opcode;
160  unsigned DstReg = MI.getOperand(0).getReg();
161  assert(DstReg != AVR::R29R28 && "Dest reg cannot be the frame pointer");
162 
163  II++; // Skip over the FRMIDX (and now MOVW) instruction.
164 
165  // Generally, to load a frame address two add instructions are emitted that
166  // could get folded into a single one:
167  // movw r31:r30, r29:r28
168  // adiw r31:r30, 29
169  // adiw r31:r30, 16
170  // to:
171  // movw r31:r30, r29:r28
172  // adiw r31:r30, 45
173  if (II != MBB.end())
174  foldFrameOffset(II, Offset, DstReg);
175 
176  // Select the best opcode based on DstReg and the offset size.
177  switch (DstReg) {
178  case AVR::R25R24:
179  case AVR::R27R26:
180  case AVR::R31R30: {
181  if (isUInt<6>(Offset)) {
182  Opcode = AVR::ADIWRdK;
183  break;
184  }
186  }
187  default: {
188  // This opcode will get expanded into a pair of subi/sbci.
189  Opcode = AVR::SUBIWRdK;
190  Offset = -Offset;
191  break;
192  }
193  }
194 
195  MachineInstr *New = BuildMI(MBB, II, dl, TII.get(Opcode), DstReg)
196  .addReg(DstReg, RegState::Kill)
197  .addImm(Offset);
198  New->getOperand(3).setIsDead();
199 
200  return;
201  }
202 
203  // If the offset is too big we have to adjust and restore the frame pointer
204  // to materialize a valid load/store with displacement.
205  //:TODO: consider using only one adiw/sbiw chain for more than one frame index
206  if (Offset > 62) {
207  unsigned AddOpc = AVR::ADIWRdK, SubOpc = AVR::SBIWRdK;
208  int AddOffset = Offset - 63 + 1;
209 
210  // For huge offsets where adiw/sbiw cannot be used use a pair of subi/sbci.
211  if ((Offset - 63 + 1) > 63) {
212  AddOpc = AVR::SUBIWRdK;
213  SubOpc = AVR::SUBIWRdK;
214  AddOffset = -AddOffset;
215  }
216 
217  // It is possible that the spiller places this frame instruction in between
218  // a compare and branch, invalidating the contents of SREG set by the
219  // compare instruction because of the add/sub pairs. Conservatively save and
220  // restore SREG before and after each add/sub pair.
221  BuildMI(MBB, II, dl, TII.get(AVR::INRdA), AVR::R0).addImm(0x3f);
222 
223  MachineInstr *New = BuildMI(MBB, II, dl, TII.get(AddOpc), AVR::R29R28)
224  .addReg(AVR::R29R28, RegState::Kill)
225  .addImm(AddOffset);
226  New->getOperand(3).setIsDead();
227 
228  // Restore SREG.
229  BuildMI(MBB, std::next(II), dl, TII.get(AVR::OUTARr))
230  .addImm(0x3f)
231  .addReg(AVR::R0, RegState::Kill);
232 
233  // No need to set SREG as dead here otherwise if the next instruction is a
234  // cond branch it will be using a dead register.
235  New = BuildMI(MBB, std::next(II), dl, TII.get(SubOpc), AVR::R29R28)
236  .addReg(AVR::R29R28, RegState::Kill)
237  .addImm(Offset - 63 + 1);
238 
239  Offset = 62;
240  }
241 
242  MI.getOperand(FIOperandNum).ChangeToRegister(AVR::R29R28, false);
243  assert(isUInt<6>(Offset) && "Offset is out of range");
244  MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
245 }
246 
249  if (TFI->hasFP(MF)) {
250  // The Y pointer register
251  return AVR::R28;
252  }
253 
254  return AVR::SP;
255 }
256 
257 const TargetRegisterClass *
259  unsigned Kind) const {
260  // FIXME: Currently we're using avr-gcc as reference, so we restrict
261  // ptrs to Y and Z regs. Though avr-gcc has buggy implementation
262  // of memory constraint, so we can fix it and bit avr-gcc here ;-)
263  return &AVR::PTRDISPREGSRegClass;
264 }
265 
267  unsigned &LoReg,
268  unsigned &HiReg) const {
269  assert(AVR::DREGSRegClass.contains(Reg) && "can only split 16-bit registers");
270 
271  LoReg = getSubReg(Reg, AVR::sub_lo);
272  HiReg = getSubReg(Reg, AVR::sub_hi);
273 }
274 
275 } // end of namespace llvm
const AVRInstrInfo * getInstrInfo() const override
Definition: AVRSubtarget.h:42
Used for AVR interrupt routines.
Definition: CallingConv.h:177
BitVector & set()
Definition: BitVector.h:398
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:268
unsigned getReg() const
getReg - Returns the register number.
BitVector getReservedRegs(const MachineFunction &MF) const override
A debug info location.
Definition: DebugLoc.h:34
void setIsDead(bool Val=true)
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
return AArch64::GPR64RegClass contains(Reg)
const AVRSubtarget * getSubtargetImpl() const
Calling convention used for AVR signal routines.
Definition: CallingConv.h:180
const HexagonInstrInfo * TII
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register...
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
A generic AVR implementation.
const uint16_t * getCalleeSavedRegs(const MachineFunction *MF=0) const override
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=NULL) const override
Stack Frame Processing Methods.
TargetInstrInfo - Interface to description of machine instruction set.
static void foldFrameOffset(MachineBasicBlock::iterator &II, int &Offset, unsigned DstReg)
Fold a frame offset shared between two add instructions into a single one.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void splitReg(unsigned Reg, unsigned &LoReg, unsigned &HiReg) const
Splits a 16-bit DREGS register into the lo/hi register pair.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:194
Information about stack frame layout on the target.
int64_t getImm() const
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
Representation of each machine instruction.
Definition: MachineInstr.h:59
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
virtual const TargetFrameLowering * getFrameLowering() const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
const unsigned Kind
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned getFrameRegister(const MachineFunction &MF) const override
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:235
const TargetFrameLowering * getFrameLowering() const override
Definition: AVRSubtarget.h:43
IRTranslator LLVM IR MI
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...