LLVM  6.0.0svn
MSP430RegisterInfo.cpp
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1 //===-- MSP430RegisterInfo.cpp - MSP430 Register Information --------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MSP430 implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MSP430RegisterInfo.h"
15 #include "MSP430.h"
17 #include "MSP430TargetMachine.h"
18 #include "llvm/ADT/BitVector.h"
22 #include "llvm/IR/Function.h"
26 
27 using namespace llvm;
28 
29 #define DEBUG_TYPE "msp430-reg-info"
30 
31 #define GET_REGINFO_TARGET_DESC
32 #include "MSP430GenRegisterInfo.inc"
33 
34 // FIXME: Provide proper call frame setup / destroy opcodes.
36  : MSP430GenRegisterInfo(MSP430::PC) {}
37 
38 const MCPhysReg*
40  const MSP430FrameLowering *TFI = getFrameLowering(*MF);
41  const Function* F = MF->getFunction();
42  static const MCPhysReg CalleeSavedRegs[] = {
43  MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7,
44  MSP430::R8, MSP430::R9, MSP430::R10,
45  0
46  };
47  static const MCPhysReg CalleeSavedRegsFP[] = {
48  MSP430::R5, MSP430::R6, MSP430::R7,
49  MSP430::R8, MSP430::R9, MSP430::R10,
50  0
51  };
52  static const MCPhysReg CalleeSavedRegsIntr[] = {
53  MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7,
54  MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
55  MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15,
56  0
57  };
58  static const MCPhysReg CalleeSavedRegsIntrFP[] = {
59  MSP430::R5, MSP430::R6, MSP430::R7,
60  MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
61  MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15,
62  0
63  };
64 
65  if (TFI->hasFP(*MF))
67  CalleeSavedRegsIntrFP : CalleeSavedRegsFP);
68  else
70  CalleeSavedRegsIntr : CalleeSavedRegs);
71 
72 }
73 
75  BitVector Reserved(getNumRegs());
76  const MSP430FrameLowering *TFI = getFrameLowering(MF);
77 
78  // Mark 4 special registers with subregisters as reserved.
79  Reserved.set(MSP430::PCB);
80  Reserved.set(MSP430::SPB);
81  Reserved.set(MSP430::SRB);
82  Reserved.set(MSP430::CGB);
83  Reserved.set(MSP430::PC);
84  Reserved.set(MSP430::SP);
85  Reserved.set(MSP430::SR);
86  Reserved.set(MSP430::CG);
87 
88  // Mark frame pointer as reserved if needed.
89  if (TFI->hasFP(MF)) {
90  Reserved.set(MSP430::FPB);
91  Reserved.set(MSP430::FP);
92  }
93 
94  return Reserved;
95 }
96 
97 const TargetRegisterClass *
99  const {
100  return &MSP430::GR16RegClass;
101 }
102 
103 void
105  int SPAdj, unsigned FIOperandNum,
106  RegScavenger *RS) const {
107  assert(SPAdj == 0 && "Unexpected");
108 
109  MachineInstr &MI = *II;
110  MachineBasicBlock &MBB = *MI.getParent();
111  MachineFunction &MF = *MBB.getParent();
112  const MSP430FrameLowering *TFI = getFrameLowering(MF);
113  DebugLoc dl = MI.getDebugLoc();
114  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
115 
116  unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::FP : MSP430::SP);
117  int Offset = MF.getFrameInfo().getObjectOffset(FrameIndex);
118 
119  // Skip the saved PC
120  Offset += 2;
121 
122  if (!TFI->hasFP(MF))
123  Offset += MF.getFrameInfo().getStackSize();
124  else
125  Offset += 2; // Skip the saved FP
126 
127  // Fold imm into offset
128  Offset += MI.getOperand(FIOperandNum + 1).getImm();
129 
130  if (MI.getOpcode() == MSP430::ADDframe) {
131  // This is actually "load effective address" of the stack slot
132  // instruction. We have only two-address instructions, thus we need to
133  // expand it into mov + add
134  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
135 
136  MI.setDesc(TII.get(MSP430::MOV16rr));
137  MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
138 
139  if (Offset == 0)
140  return;
141 
142  // We need to materialize the offset via add instruction.
143  unsigned DstReg = MI.getOperand(0).getReg();
144  if (Offset < 0)
145  BuildMI(MBB, std::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
146  .addReg(DstReg).addImm(-Offset);
147  else
148  BuildMI(MBB, std::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
149  .addReg(DstReg).addImm(Offset);
150 
151  return;
152  }
153 
154  MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
155  MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
156 }
157 
159  const MSP430FrameLowering *TFI = getFrameLowering(MF);
160  return TFI->hasFP(MF) ? MSP430::FP : MSP430::SP;
161 }
BitVector & set()
Definition: BitVector.h:398
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned getFrameRegister(const MachineFunction &MF) const override
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:268
unsigned getReg() const
getReg - Returns the register number.
A debug info location.
Definition: DebugLoc.h:34
F(f)
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
MSP430_INTR - Calling convention used for MSP430 interrupt routines.
Definition: CallingConv.h:106
const HexagonInstrInfo * TII
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
virtual const TargetInstrInfo * getInstrInfo() const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
TargetInstrInfo - Interface to description of machine instruction set.
BitVector getReservedRegs(const MachineFunction &MF) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
#define R6(n)
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:194
int64_t getImm() const
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
Representation of each machine instruction.
Definition: MachineInstr.h:59
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
const unsigned Kind
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
IRTranslator LLVM IR MI
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...