LLVM  7.0.0svn
BPFISelLowering.cpp
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1 //===-- BPFISelLowering.cpp - BPF DAG Lowering Implementation ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that BPF uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "BPFISelLowering.h"
16 #include "BPF.h"
17 #include "BPFSubtarget.h"
18 #include "BPFTargetMachine.h"
27 #include "llvm/IR/DiagnosticInfo.h"
29 #include "llvm/Support/Debug.h"
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "bpf-lower"
35 
36 static void fail(const SDLoc &DL, SelectionDAG &DAG, const Twine &Msg) {
38  DAG.getContext()->diagnose(
40 }
41 
42 static void fail(const SDLoc &DL, SelectionDAG &DAG, const char *Msg,
43  SDValue Val) {
45  std::string Str;
46  raw_string_ostream OS(Str);
47  OS << Msg;
48  Val->print(OS);
49  OS.flush();
50  DAG.getContext()->diagnose(
52 }
53 
55  const BPFSubtarget &STI)
56  : TargetLowering(TM) {
57 
58  // Set up the register classes.
59  addRegisterClass(MVT::i64, &BPF::GPRRegClass);
60  if (STI.getHasAlu32())
61  addRegisterClass(MVT::i32, &BPF::GPR32RegClass);
62 
63  // Compute derived properties from the register classes
65 
67 
72 
74 
78 
79  for (auto VT : { MVT::i32, MVT::i64 }) {
80  if (VT == MVT::i32 && !STI.getHasAlu32())
81  continue;
82 
97 
101  }
102 
103  if (STI.getHasAlu32()) {
106  }
107 
112 
117 
118  // Extended load operations for i1 types must be promoted
119  for (MVT VT : MVT::integer_valuetypes()) {
123 
127  }
128 
130 
131  // Function alignments (log2)
134 
135  // inline memcpy() for kernel to see explicit copy
139 
140  // CPU/Feature control
141  HasAlu32 = STI.getHasAlu32();
142  HasJmpExt = STI.getHasJmpExt();
143 }
144 
146  return false;
147 }
148 
149 std::pair<unsigned, const TargetRegisterClass *>
151  StringRef Constraint,
152  MVT VT) const {
153  if (Constraint.size() == 1)
154  // GCC Constraint Letters
155  switch (Constraint[0]) {
156  case 'r': // GENERAL_REGS
157  return std::make_pair(0U, &BPF::GPRRegClass);
158  default:
159  break;
160  }
161 
162  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
163 }
164 
166  switch (Op.getOpcode()) {
167  case ISD::BR_CC:
168  return LowerBR_CC(Op, DAG);
169  case ISD::GlobalAddress:
170  return LowerGlobalAddress(Op, DAG);
171  case ISD::SELECT_CC:
172  return LowerSELECT_CC(Op, DAG);
173  default:
174  llvm_unreachable("unimplemented operand");
175  }
176 }
177 
178 // Calling Convention Implementation
179 #include "BPFGenCallingConv.inc"
180 
181 SDValue BPFTargetLowering::LowerFormalArguments(
182  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
183  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
184  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
185  switch (CallConv) {
186  default:
187  report_fatal_error("Unsupported calling convention");
188  case CallingConv::C:
189  case CallingConv::Fast:
190  break;
191  }
192 
194  MachineRegisterInfo &RegInfo = MF.getRegInfo();
195 
196  // Assign locations to all of the incoming arguments.
198  CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
199  CCInfo.AnalyzeFormalArguments(Ins, getHasAlu32() ? CC_BPF32 : CC_BPF64);
200 
201  for (auto &VA : ArgLocs) {
202  if (VA.isRegLoc()) {
203  // Arguments passed in registers
204  EVT RegVT = VA.getLocVT();
205  MVT::SimpleValueType SimpleTy = RegVT.getSimpleVT().SimpleTy;
206  switch (SimpleTy) {
207  default: {
208  errs() << "LowerFormalArguments Unhandled argument type: "
209  << RegVT.getEVTString() << '\n';
210  llvm_unreachable(0);
211  }
212  case MVT::i32:
213  case MVT::i64:
214  unsigned VReg = RegInfo.createVirtualRegister(SimpleTy == MVT::i64 ?
215  &BPF::GPRRegClass :
216  &BPF::GPR32RegClass);
217  RegInfo.addLiveIn(VA.getLocReg(), VReg);
218  SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
219 
220  // If this is an value that has been promoted to wider types, insert an
221  // assert[sz]ext to capture this, then truncate to the right size.
222  if (VA.getLocInfo() == CCValAssign::SExt)
223  ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
224  DAG.getValueType(VA.getValVT()));
225  else if (VA.getLocInfo() == CCValAssign::ZExt)
226  ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
227  DAG.getValueType(VA.getValVT()));
228 
229  if (VA.getLocInfo() != CCValAssign::Full)
230  ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
231 
232  InVals.push_back(ArgValue);
233 
234  break;
235  }
236  } else {
237  fail(DL, DAG, "defined with too many args");
238  InVals.push_back(DAG.getConstant(0, DL, VA.getLocVT()));
239  }
240  }
241 
242  if (IsVarArg || MF.getFunction().hasStructRetAttr()) {
243  fail(DL, DAG, "functions with VarArgs or StructRet are not supported");
244  }
245 
246  return Chain;
247 }
248 
249 const unsigned BPFTargetLowering::MaxArgs = 5;
250 
251 SDValue BPFTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
252  SmallVectorImpl<SDValue> &InVals) const {
253  SelectionDAG &DAG = CLI.DAG;
254  auto &Outs = CLI.Outs;
255  auto &OutVals = CLI.OutVals;
256  auto &Ins = CLI.Ins;
257  SDValue Chain = CLI.Chain;
258  SDValue Callee = CLI.Callee;
259  bool &IsTailCall = CLI.IsTailCall;
260  CallingConv::ID CallConv = CLI.CallConv;
261  bool IsVarArg = CLI.IsVarArg;
263 
264  // BPF target does not support tail call optimization.
265  IsTailCall = false;
266 
267  switch (CallConv) {
268  default:
269  report_fatal_error("Unsupported calling convention");
270  case CallingConv::Fast:
271  case CallingConv::C:
272  break;
273  }
274 
275  // Analyze operands of the call, assigning locations to each operand.
277  CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
278 
279  CCInfo.AnalyzeCallOperands(Outs, getHasAlu32() ? CC_BPF32 : CC_BPF64);
280 
281  unsigned NumBytes = CCInfo.getNextStackOffset();
282 
283  if (Outs.size() > MaxArgs)
284  fail(CLI.DL, DAG, "too many args to ", Callee);
285 
286  for (auto &Arg : Outs) {
287  ISD::ArgFlagsTy Flags = Arg.Flags;
288  if (!Flags.isByVal())
289  continue;
290 
291  fail(CLI.DL, DAG, "pass by value not supported ", Callee);
292  }
293 
294  auto PtrVT = getPointerTy(MF.getDataLayout());
295  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, CLI.DL);
296 
297  SmallVector<std::pair<unsigned, SDValue>, MaxArgs> RegsToPass;
298 
299  // Walk arg assignments
300  for (unsigned i = 0,
301  e = std::min(static_cast<unsigned>(ArgLocs.size()), MaxArgs);
302  i != e; ++i) {
303  CCValAssign &VA = ArgLocs[i];
304  SDValue Arg = OutVals[i];
305 
306  // Promote the value if needed.
307  switch (VA.getLocInfo()) {
308  default:
309  llvm_unreachable("Unknown loc info");
310  case CCValAssign::Full:
311  break;
312  case CCValAssign::SExt:
313  Arg = DAG.getNode(ISD::SIGN_EXTEND, CLI.DL, VA.getLocVT(), Arg);
314  break;
315  case CCValAssign::ZExt:
316  Arg = DAG.getNode(ISD::ZERO_EXTEND, CLI.DL, VA.getLocVT(), Arg);
317  break;
318  case CCValAssign::AExt:
319  Arg = DAG.getNode(ISD::ANY_EXTEND, CLI.DL, VA.getLocVT(), Arg);
320  break;
321  }
322 
323  // Push arguments into RegsToPass vector
324  if (VA.isRegLoc())
325  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
326  else
327  llvm_unreachable("call arg pass bug");
328  }
329 
330  SDValue InFlag;
331 
332  // Build a sequence of copy-to-reg nodes chained together with token chain and
333  // flag operands which copy the outgoing args into registers. The InFlag in
334  // necessary since all emitted instructions must be stuck together.
335  for (auto &Reg : RegsToPass) {
336  Chain = DAG.getCopyToReg(Chain, CLI.DL, Reg.first, Reg.second, InFlag);
337  InFlag = Chain.getValue(1);
338  }
339 
340  // If the callee is a GlobalAddress node (quite common, every direct call is)
341  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
342  // Likewise ExternalSymbol -> TargetExternalSymbol.
343  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
344  Callee = DAG.getTargetGlobalAddress(G->getGlobal(), CLI.DL, PtrVT,
345  G->getOffset(), 0);
346  } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
347  Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT, 0);
348  fail(CLI.DL, DAG, Twine("A call to built-in function '"
349  + StringRef(E->getSymbol())
350  + "' is not supported."));
351  }
352 
353  // Returns a chain & a flag for retval copy to use.
354  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
356  Ops.push_back(Chain);
357  Ops.push_back(Callee);
358 
359  // Add argument registers to the end of the list so that they are
360  // known live into the call.
361  for (auto &Reg : RegsToPass)
362  Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
363 
364  if (InFlag.getNode())
365  Ops.push_back(InFlag);
366 
367  Chain = DAG.getNode(BPFISD::CALL, CLI.DL, NodeTys, Ops);
368  InFlag = Chain.getValue(1);
369 
370  // Create the CALLSEQ_END node.
371  Chain = DAG.getCALLSEQ_END(
372  Chain, DAG.getConstant(NumBytes, CLI.DL, PtrVT, true),
373  DAG.getConstant(0, CLI.DL, PtrVT, true), InFlag, CLI.DL);
374  InFlag = Chain.getValue(1);
375 
376  // Handle result values, copying them out of physregs into vregs that we
377  // return.
378  return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, CLI.DL, DAG,
379  InVals);
380 }
381 
382 SDValue
383 BPFTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
384  bool IsVarArg,
386  const SmallVectorImpl<SDValue> &OutVals,
387  const SDLoc &DL, SelectionDAG &DAG) const {
388  unsigned Opc = BPFISD::RET_FLAG;
389 
390  // CCValAssign - represent the assignment of the return value to a location
393 
394  // CCState - Info about the registers and stack slot.
395  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
396 
397  if (MF.getFunction().getReturnType()->isAggregateType()) {
398  fail(DL, DAG, "only integer returns supported");
399  return DAG.getNode(Opc, DL, MVT::Other, Chain);
400  }
401 
402  // Analize return values.
403  CCInfo.AnalyzeReturn(Outs, getHasAlu32() ? RetCC_BPF32 : RetCC_BPF64);
404 
405  SDValue Flag;
406  SmallVector<SDValue, 4> RetOps(1, Chain);
407 
408  // Copy the result values into the output registers.
409  for (unsigned i = 0; i != RVLocs.size(); ++i) {
410  CCValAssign &VA = RVLocs[i];
411  assert(VA.isRegLoc() && "Can only return in registers!");
412 
413  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);
414 
415  // Guarantee that all emitted copies are stuck together,
416  // avoiding something bad.
417  Flag = Chain.getValue(1);
418  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
419  }
420 
421  RetOps[0] = Chain; // Update chain.
422 
423  // Add the flag if we have it.
424  if (Flag.getNode())
425  RetOps.push_back(Flag);
426 
427  return DAG.getNode(Opc, DL, MVT::Other, RetOps);
428 }
429 
430 SDValue BPFTargetLowering::LowerCallResult(
431  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
432  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
433  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
434 
436  // Assign locations to each value returned by this call.
438  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
439 
440  if (Ins.size() >= 2) {
441  fail(DL, DAG, "only small returns supported");
442  for (unsigned i = 0, e = Ins.size(); i != e; ++i)
443  InVals.push_back(DAG.getConstant(0, DL, Ins[i].VT));
444  return DAG.getCopyFromReg(Chain, DL, 1, Ins[0].VT, InFlag).getValue(1);
445  }
446 
447  CCInfo.AnalyzeCallResult(Ins, getHasAlu32() ? RetCC_BPF32 : RetCC_BPF64);
448 
449  // Copy all of the result registers out of their specified physreg.
450  for (auto &Val : RVLocs) {
451  Chain = DAG.getCopyFromReg(Chain, DL, Val.getLocReg(),
452  Val.getValVT(), InFlag).getValue(1);
453  InFlag = Chain.getValue(2);
454  InVals.push_back(Chain.getValue(0));
455  }
456 
457  return Chain;
458 }
459 
460 static void NegateCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) {
461  switch (CC) {
462  default:
463  break;
464  case ISD::SETULT:
465  case ISD::SETULE:
466  case ISD::SETLT:
467  case ISD::SETLE:
469  std::swap(LHS, RHS);
470  break;
471  }
472 }
473 
474 SDValue BPFTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
475  SDValue Chain = Op.getOperand(0);
476  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
477  SDValue LHS = Op.getOperand(2);
478  SDValue RHS = Op.getOperand(3);
479  SDValue Dest = Op.getOperand(4);
480  SDLoc DL(Op);
481 
482  if (!getHasJmpExt())
483  NegateCC(LHS, RHS, CC);
484 
485  return DAG.getNode(BPFISD::BR_CC, DL, Op.getValueType(), Chain, LHS, RHS,
486  DAG.getConstant(CC, DL, MVT::i64), Dest);
487 }
488 
489 SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
490  SDValue LHS = Op.getOperand(0);
491  SDValue RHS = Op.getOperand(1);
492  SDValue TrueV = Op.getOperand(2);
493  SDValue FalseV = Op.getOperand(3);
494  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
495  SDLoc DL(Op);
496 
497  if (!getHasJmpExt())
498  NegateCC(LHS, RHS, CC);
499 
500  SDValue TargetCC = DAG.getConstant(CC, DL, LHS.getValueType());
501  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
502  SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV};
503 
504  return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops);
505 }
506 
507 const char *BPFTargetLowering::getTargetNodeName(unsigned Opcode) const {
508  switch ((BPFISD::NodeType)Opcode) {
510  break;
511  case BPFISD::RET_FLAG:
512  return "BPFISD::RET_FLAG";
513  case BPFISD::CALL:
514  return "BPFISD::CALL";
515  case BPFISD::SELECT_CC:
516  return "BPFISD::SELECT_CC";
517  case BPFISD::BR_CC:
518  return "BPFISD::BR_CC";
519  case BPFISD::Wrapper:
520  return "BPFISD::Wrapper";
521  }
522  return nullptr;
523 }
524 
525 SDValue BPFTargetLowering::LowerGlobalAddress(SDValue Op,
526  SelectionDAG &DAG) const {
527  auto N = cast<GlobalAddressSDNode>(Op);
528  assert(N->getOffset() == 0 && "Invalid offset for global address");
529 
530  SDLoc DL(Op);
531  const GlobalValue *GV = N->getGlobal();
532  SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i64);
533 
534  return DAG.getNode(BPFISD::Wrapper, DL, MVT::i64, GA);
535 }
536 
537 unsigned
538 BPFTargetLowering::EmitSubregExt(MachineInstr &MI, MachineBasicBlock *BB,
539  unsigned Reg, bool isSigned) const {
542  int RShiftOp = isSigned ? BPF::SRA_ri : BPF::SRL_ri;
543  MachineFunction *F = BB->getParent();
544  DebugLoc DL = MI.getDebugLoc();
545 
546  MachineRegisterInfo &RegInfo = F->getRegInfo();
547  unsigned PromotedReg0 = RegInfo.createVirtualRegister(RC);
548  unsigned PromotedReg1 = RegInfo.createVirtualRegister(RC);
549  unsigned PromotedReg2 = RegInfo.createVirtualRegister(RC);
550  BuildMI(BB, DL, TII.get(BPF::MOV_32_64), PromotedReg0).addReg(Reg);
551  BuildMI(BB, DL, TII.get(BPF::SLL_ri), PromotedReg1)
552  .addReg(PromotedReg0).addImm(32);
553  BuildMI(BB, DL, TII.get(RShiftOp), PromotedReg2)
554  .addReg(PromotedReg1).addImm(32);
555 
556  return PromotedReg2;
557 }
558 
561  MachineBasicBlock *BB) const {
563  DebugLoc DL = MI.getDebugLoc();
564  unsigned Opc = MI.getOpcode();
565  bool isSelectRROp = (Opc == BPF::Select ||
566  Opc == BPF::Select_64_32 ||
567  Opc == BPF::Select_32 ||
568  Opc == BPF::Select_32_64);
569 
570 #ifndef NDEBUG
571  bool isSelectRIOp = (Opc == BPF::Select_Ri ||
572  Opc == BPF::Select_Ri_64_32 ||
573  Opc == BPF::Select_Ri_32 ||
574  Opc == BPF::Select_Ri_32_64);
575 
576 
577  assert((isSelectRROp || isSelectRIOp) && "Unexpected instr type to insert");
578 #endif
579 
580  bool is32BitCmp = (Opc == BPF::Select_32 ||
581  Opc == BPF::Select_32_64 ||
582  Opc == BPF::Select_Ri_32 ||
583  Opc == BPF::Select_Ri_32_64);
584 
585  // To "insert" a SELECT instruction, we actually have to insert the diamond
586  // control-flow pattern. The incoming instruction knows the destination vreg
587  // to set, the condition code register to branch on, the true/false values to
588  // select between, and a branch opcode to use.
589  const BasicBlock *LLVM_BB = BB->getBasicBlock();
591 
592  // ThisMBB:
593  // ...
594  // TrueVal = ...
595  // jmp_XX r1, r2 goto Copy1MBB
596  // fallthrough --> Copy0MBB
597  MachineBasicBlock *ThisMBB = BB;
598  MachineFunction *F = BB->getParent();
599  MachineBasicBlock *Copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
600  MachineBasicBlock *Copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
601 
602  F->insert(I, Copy0MBB);
603  F->insert(I, Copy1MBB);
604  // Update machine-CFG edges by transferring all successors of the current
605  // block to the new block which will contain the Phi node for the select.
606  Copy1MBB->splice(Copy1MBB->begin(), BB,
607  std::next(MachineBasicBlock::iterator(MI)), BB->end());
608  Copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
609  // Next, add the true and fallthrough blocks as its successors.
610  BB->addSuccessor(Copy0MBB);
611  BB->addSuccessor(Copy1MBB);
612 
613  // Insert Branch if Flag
614  int CC = MI.getOperand(3).getImm();
615  int NewCC;
616  switch (CC) {
617  case ISD::SETGT:
618  NewCC = isSelectRROp ? BPF::JSGT_rr : BPF::JSGT_ri;
619  break;
620  case ISD::SETUGT:
621  NewCC = isSelectRROp ? BPF::JUGT_rr : BPF::JUGT_ri;
622  break;
623  case ISD::SETGE:
624  NewCC = isSelectRROp ? BPF::JSGE_rr : BPF::JSGE_ri;
625  break;
626  case ISD::SETUGE:
627  NewCC = isSelectRROp ? BPF::JUGE_rr : BPF::JUGE_ri;
628  break;
629  case ISD::SETEQ:
630  NewCC = isSelectRROp ? BPF::JEQ_rr : BPF::JEQ_ri;
631  break;
632  case ISD::SETNE:
633  NewCC = isSelectRROp ? BPF::JNE_rr : BPF::JNE_ri;
634  break;
635  case ISD::SETLT:
636  NewCC = isSelectRROp ? BPF::JSLT_rr : BPF::JSLT_ri;
637  break;
638  case ISD::SETULT:
639  NewCC = isSelectRROp ? BPF::JULT_rr : BPF::JULT_ri;
640  break;
641  case ISD::SETLE:
642  NewCC = isSelectRROp ? BPF::JSLE_rr : BPF::JSLE_ri;
643  break;
644  case ISD::SETULE:
645  NewCC = isSelectRROp ? BPF::JULE_rr : BPF::JULE_ri;
646  break;
647  default:
648  report_fatal_error("unimplemented select CondCode " + Twine(CC));
649  }
650 
651  unsigned LHS = MI.getOperand(1).getReg();
652  bool isSignedCmp = (CC == ISD::SETGT ||
653  CC == ISD::SETGE ||
654  CC == ISD::SETLT ||
655  CC == ISD::SETLE);
656 
657  // eBPF at the moment only has 64-bit comparison. Any 32-bit comparison need
658  // to be promoted, however if the 32-bit comparison operands are destination
659  // registers then they are implicitly zero-extended already, there is no
660  // need of explicit zero-extend sequence for them.
661  //
662  // We simply do extension for all situations in this method, but we will
663  // try to remove those unnecessary in BPFMIPeephole pass.
664  if (is32BitCmp)
665  LHS = EmitSubregExt(MI, BB, LHS, isSignedCmp);
666 
667  if (isSelectRROp) {
668  unsigned RHS = MI.getOperand(2).getReg();
669 
670  if (is32BitCmp)
671  RHS = EmitSubregExt(MI, BB, RHS, isSignedCmp);
672 
673  BuildMI(BB, DL, TII.get(NewCC)).addReg(LHS).addReg(RHS).addMBB(Copy1MBB);
674  } else {
675  int64_t imm32 = MI.getOperand(2).getImm();
676  // sanity check before we build J*_ri instruction.
677  assert (isInt<32>(imm32));
678  BuildMI(BB, DL, TII.get(NewCC))
679  .addReg(LHS).addImm(imm32).addMBB(Copy1MBB);
680  }
681 
682  // Copy0MBB:
683  // %FalseValue = ...
684  // # fallthrough to Copy1MBB
685  BB = Copy0MBB;
686 
687  // Update machine-CFG edges
688  BB->addSuccessor(Copy1MBB);
689 
690  // Copy1MBB:
691  // %Result = phi [ %FalseValue, Copy0MBB ], [ %TrueValue, ThisMBB ]
692  // ...
693  BB = Copy1MBB;
694  BuildMI(*BB, BB->begin(), DL, TII.get(BPF::PHI), MI.getOperand(0).getReg())
695  .addReg(MI.getOperand(5).getReg())
696  .addMBB(Copy0MBB)
697  .addReg(MI.getOperand(4).getReg())
698  .addMBB(ThisMBB);
699 
700  MI.eraseFromParent(); // The pseudo instruction is gone now.
701  return BB;
702 }
703 
705  EVT VT) const {
706  return getHasAlu32() ? MVT::i32 : MVT::i64;
707 }
708 
710  EVT VT) const {
711  return (getHasAlu32() && VT == MVT::i32) ? MVT::i32 : MVT::i64;
712 }
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
EVT getValueType() const
Return the ValueType of the referenced return value.
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
static void NegateCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC)
Diagnostic information for unsupported feature in backend.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it&#39;s not CSE&#39;d)...
Definition: SelectionDAG.h:849
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:611
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:137
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:285
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
unsigned getReg() const
getReg - Returns the register number.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:660
unsigned Reg
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:253
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
F(f)
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:405
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
Definition: Function.h:565
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:210
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:426
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
const HexagonInstrInfo * TII
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
SimpleValueType SimpleTy
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:311
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
LocInfo getLocInfo() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
SmallVector< ISD::InputArg, 32 > Ins
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:656
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:395
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
SmallVector< ISD::OutputArg, 32 > Outs
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:911
virtual const TargetInstrInfo * getInstrInfo() const
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
amdgpu Simplify well known AMD library false Value * Callee
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:118
TargetInstrInfo - Interface to description of machine instruction set.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Type * getReturnType() const
Returns the type of the ret val.
Definition: Function.h:155
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Machine Value Type.
LLVM Basic Block Representation.
Definition: BasicBlock.h:59
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:837
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
std::string getEVTString() const
This function returns value type as a string, e.g. "i32".
Definition: ValueTypes.cpp:115
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:57
void setPrefFunctionAlignment(unsigned Align)
Set the target&#39;s preferred function alignment.
self_iterator getIterator()
Definition: ilist_node.h:82
CondCode getSetCCSwappedOperands(CondCode Operation)
Return the operation corresponding to (Y op X) when given the operation for (X op Y)...
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:386
Extended Value Type.
Definition: ValueTypes.h:34
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const TargetRegisterInfo * getRegisterInfo() const override
Definition: BPFSubtarget.h:81
Iterator for intrusive lists based on ilist_node.
CCState - This class holds information needed while lowering arguments and return values...
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:309
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:222
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
const DebugLoc & getDebugLoc() const
CCValAssign - Represent assignment of one arg/retval to a location.
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:605
bool isAggregateType() const
Return true if the type is an aggregate type.
Definition: Type.h:258
const DataFlowGraph & G
Definition: RDFGraph.cpp:211
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:383
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
int64_t getImm() const
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:674
const Function & getFunction() const
Return the LLVM function that this machine code represents.
static mvt_range integer_valuetypes()
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:924
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:390
void setMinFunctionAlignment(unsigned Align)
Set the target&#39;s minimum function alignment (in log2(bytes))
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:438
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:441
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
amdgpu Simplify well known AMD library false Value Value * Arg
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:599
Representation of each machine instruction.
Definition: MachineInstr.h:60
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
SmallVector< SDValue, 32 > OutVals
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:700
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:206
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:456
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
unsigned MaxStoresPerMemmoveOptSize
Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OptSize attribute.
unsigned MaxStoresPerMemcpyOptSize
Maximum number of store operations that may be substituted for a call to memcpy, used for functions w...
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
bool getHasAlu32() const
Definition: BPFSubtarget.h:68
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
unsigned getOpcode() const
SDValue getValue(unsigned R) const
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
bool isRegLoc() const
BPFTargetLowering(const TargetMachine &TM, const BPFSubtarget &STI)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:477
void print(raw_ostream &OS, const SelectionDAG *G=nullptr) const
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the &#39;usesCustomInserter&#39; fla...
SDValue getRegister(unsigned Reg, EVT VT)
SDValue getValueType(EVT)
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:413
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
unsigned MaxStoresPerMemsetOptSize
Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute.
Conversion operators.
Definition: ISDOpcodes.h:435
const SDValue & getOperand(unsigned i) const
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
unsigned getLocReg() const
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:444
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:316
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
bool getHasJmpExt() const
Definition: BPFSubtarget.h:67
static void fail(const SDLoc &DL, SelectionDAG &DAG, const Twine &Msg)
LLVMContext * getContext() const
Definition: SelectionDAG.h:404
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:617
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:356
BRIND - Indirect branch.
Definition: ISDOpcodes.h:595
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...
Definition: ISDOpcodes.h:584