LLVM  6.0.0svn
BPFISelLowering.cpp
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1 //===-- BPFISelLowering.cpp - BPF DAG Lowering Implementation ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that BPF uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "BPFISelLowering.h"
16 #include "BPF.h"
17 #include "BPFSubtarget.h"
18 #include "BPFTargetMachine.h"
27 #include "llvm/IR/DiagnosticInfo.h"
29 #include "llvm/Support/Debug.h"
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "bpf-lower"
35 
36 static void fail(const SDLoc &DL, SelectionDAG &DAG, const Twine &Msg) {
38  DAG.getContext()->diagnose(
40 }
41 
42 static void fail(const SDLoc &DL, SelectionDAG &DAG, const char *Msg,
43  SDValue Val) {
45  std::string Str;
46  raw_string_ostream OS(Str);
47  OS << Msg;
48  Val->print(OS);
49  OS.flush();
50  DAG.getContext()->diagnose(
52 }
53 
55  const BPFSubtarget &STI)
56  : TargetLowering(TM) {
57 
58  // Set up the register classes.
59  addRegisterClass(MVT::i64, &BPF::GPRRegClass);
60 
61  // Compute derived properties from the register classes
63 
65 
73 
75 
79 
84 
89 
94 
100 
106 
111 
112  // Extended load operations for i1 types must be promoted
113  for (MVT VT : MVT::integer_valuetypes()) {
117 
121  }
122 
124 
125  // Function alignments (log2)
128 
129  // inline memcpy() for kernel to see explicit copy
133 
134  // CPU/Feature control
135  HasJmpExt = STI.getHasJmpExt();
136 }
137 
139  return false;
140 }
141 
142 std::pair<unsigned, const TargetRegisterClass *>
144  StringRef Constraint,
145  MVT VT) const {
146  if (Constraint.size() == 1)
147  // GCC Constraint Letters
148  switch (Constraint[0]) {
149  case 'r': // GENERAL_REGS
150  return std::make_pair(0U, &BPF::GPRRegClass);
151  default:
152  break;
153  }
154 
155  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
156 }
157 
159  switch (Op.getOpcode()) {
160  case ISD::BR_CC:
161  return LowerBR_CC(Op, DAG);
162  case ISD::GlobalAddress:
163  return LowerGlobalAddress(Op, DAG);
164  case ISD::SELECT_CC:
165  return LowerSELECT_CC(Op, DAG);
166  default:
167  llvm_unreachable("unimplemented operand");
168  }
169 }
170 
171 // Calling Convention Implementation
172 #include "BPFGenCallingConv.inc"
173 
174 SDValue BPFTargetLowering::LowerFormalArguments(
175  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
176  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
177  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
178  switch (CallConv) {
179  default:
180  report_fatal_error("Unsupported calling convention");
181  case CallingConv::C:
182  case CallingConv::Fast:
183  break;
184  }
185 
187  MachineRegisterInfo &RegInfo = MF.getRegInfo();
188 
189  // Assign locations to all of the incoming arguments.
191  CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
192  CCInfo.AnalyzeFormalArguments(Ins, CC_BPF64);
193 
194  for (auto &VA : ArgLocs) {
195  if (VA.isRegLoc()) {
196  // Arguments passed in registers
197  EVT RegVT = VA.getLocVT();
198  switch (RegVT.getSimpleVT().SimpleTy) {
199  default: {
200  errs() << "LowerFormalArguments Unhandled argument type: "
201  << RegVT.getEVTString() << '\n';
202  llvm_unreachable(0);
203  }
204  case MVT::i64:
205  unsigned VReg = RegInfo.createVirtualRegister(&BPF::GPRRegClass);
206  RegInfo.addLiveIn(VA.getLocReg(), VReg);
207  SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
208 
209  // If this is an 8/16/32-bit value, it is really passed promoted to 64
210  // bits. Insert an assert[sz]ext to capture this, then truncate to the
211  // right size.
212  if (VA.getLocInfo() == CCValAssign::SExt)
213  ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
214  DAG.getValueType(VA.getValVT()));
215  else if (VA.getLocInfo() == CCValAssign::ZExt)
216  ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
217  DAG.getValueType(VA.getValVT()));
218 
219  if (VA.getLocInfo() != CCValAssign::Full)
220  ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
221 
222  InVals.push_back(ArgValue);
223  }
224  } else {
225  fail(DL, DAG, "defined with too many args");
226  InVals.push_back(DAG.getConstant(0, DL, VA.getLocVT()));
227  }
228  }
229 
230  if (IsVarArg || MF.getFunction()->hasStructRetAttr()) {
231  fail(DL, DAG, "functions with VarArgs or StructRet are not supported");
232  }
233 
234  return Chain;
235 }
236 
237 const unsigned BPFTargetLowering::MaxArgs = 5;
238 
239 SDValue BPFTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
240  SmallVectorImpl<SDValue> &InVals) const {
241  SelectionDAG &DAG = CLI.DAG;
242  auto &Outs = CLI.Outs;
243  auto &OutVals = CLI.OutVals;
244  auto &Ins = CLI.Ins;
245  SDValue Chain = CLI.Chain;
246  SDValue Callee = CLI.Callee;
247  bool &IsTailCall = CLI.IsTailCall;
248  CallingConv::ID CallConv = CLI.CallConv;
249  bool IsVarArg = CLI.IsVarArg;
251 
252  // BPF target does not support tail call optimization.
253  IsTailCall = false;
254 
255  switch (CallConv) {
256  default:
257  report_fatal_error("Unsupported calling convention");
258  case CallingConv::Fast:
259  case CallingConv::C:
260  break;
261  }
262 
263  // Analyze operands of the call, assigning locations to each operand.
265  CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
266 
267  CCInfo.AnalyzeCallOperands(Outs, CC_BPF64);
268 
269  unsigned NumBytes = CCInfo.getNextStackOffset();
270 
271  if (Outs.size() > MaxArgs)
272  fail(CLI.DL, DAG, "too many args to ", Callee);
273 
274  for (auto &Arg : Outs) {
275  ISD::ArgFlagsTy Flags = Arg.Flags;
276  if (!Flags.isByVal())
277  continue;
278 
279  fail(CLI.DL, DAG, "pass by value not supported ", Callee);
280  }
281 
282  auto PtrVT = getPointerTy(MF.getDataLayout());
283  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, CLI.DL);
284 
285  SmallVector<std::pair<unsigned, SDValue>, MaxArgs> RegsToPass;
286 
287  // Walk arg assignments
288  for (unsigned i = 0,
289  e = std::min(static_cast<unsigned>(ArgLocs.size()), MaxArgs);
290  i != e; ++i) {
291  CCValAssign &VA = ArgLocs[i];
292  SDValue Arg = OutVals[i];
293 
294  // Promote the value if needed.
295  switch (VA.getLocInfo()) {
296  default:
297  llvm_unreachable("Unknown loc info");
298  case CCValAssign::Full:
299  break;
300  case CCValAssign::SExt:
301  Arg = DAG.getNode(ISD::SIGN_EXTEND, CLI.DL, VA.getLocVT(), Arg);
302  break;
303  case CCValAssign::ZExt:
304  Arg = DAG.getNode(ISD::ZERO_EXTEND, CLI.DL, VA.getLocVT(), Arg);
305  break;
306  case CCValAssign::AExt:
307  Arg = DAG.getNode(ISD::ANY_EXTEND, CLI.DL, VA.getLocVT(), Arg);
308  break;
309  }
310 
311  // Push arguments into RegsToPass vector
312  if (VA.isRegLoc())
313  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
314  else
315  llvm_unreachable("call arg pass bug");
316  }
317 
318  SDValue InFlag;
319 
320  // Build a sequence of copy-to-reg nodes chained together with token chain and
321  // flag operands which copy the outgoing args into registers. The InFlag in
322  // necessary since all emitted instructions must be stuck together.
323  for (auto &Reg : RegsToPass) {
324  Chain = DAG.getCopyToReg(Chain, CLI.DL, Reg.first, Reg.second, InFlag);
325  InFlag = Chain.getValue(1);
326  }
327 
328  // If the callee is a GlobalAddress node (quite common, every direct call is)
329  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
330  // Likewise ExternalSymbol -> TargetExternalSymbol.
331  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
332  Callee = DAG.getTargetGlobalAddress(G->getGlobal(), CLI.DL, PtrVT,
333  G->getOffset(), 0);
334  } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
335  Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT, 0);
336  fail(CLI.DL, DAG, Twine("A call to built-in function '"
337  + StringRef(E->getSymbol())
338  + "' is not supported."));
339  }
340 
341  // Returns a chain & a flag for retval copy to use.
342  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
344  Ops.push_back(Chain);
345  Ops.push_back(Callee);
346 
347  // Add argument registers to the end of the list so that they are
348  // known live into the call.
349  for (auto &Reg : RegsToPass)
350  Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
351 
352  if (InFlag.getNode())
353  Ops.push_back(InFlag);
354 
355  Chain = DAG.getNode(BPFISD::CALL, CLI.DL, NodeTys, Ops);
356  InFlag = Chain.getValue(1);
357 
358  // Create the CALLSEQ_END node.
359  Chain = DAG.getCALLSEQ_END(
360  Chain, DAG.getConstant(NumBytes, CLI.DL, PtrVT, true),
361  DAG.getConstant(0, CLI.DL, PtrVT, true), InFlag, CLI.DL);
362  InFlag = Chain.getValue(1);
363 
364  // Handle result values, copying them out of physregs into vregs that we
365  // return.
366  return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, CLI.DL, DAG,
367  InVals);
368 }
369 
370 SDValue
371 BPFTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
372  bool IsVarArg,
374  const SmallVectorImpl<SDValue> &OutVals,
375  const SDLoc &DL, SelectionDAG &DAG) const {
376  unsigned Opc = BPFISD::RET_FLAG;
377 
378  // CCValAssign - represent the assignment of the return value to a location
381 
382  // CCState - Info about the registers and stack slot.
383  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
384 
385  if (MF.getFunction()->getReturnType()->isAggregateType()) {
386  fail(DL, DAG, "only integer returns supported");
387  return DAG.getNode(Opc, DL, MVT::Other, Chain);
388  }
389 
390  // Analize return values.
391  CCInfo.AnalyzeReturn(Outs, RetCC_BPF64);
392 
393  SDValue Flag;
394  SmallVector<SDValue, 4> RetOps(1, Chain);
395 
396  // Copy the result values into the output registers.
397  for (unsigned i = 0; i != RVLocs.size(); ++i) {
398  CCValAssign &VA = RVLocs[i];
399  assert(VA.isRegLoc() && "Can only return in registers!");
400 
401  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);
402 
403  // Guarantee that all emitted copies are stuck together,
404  // avoiding something bad.
405  Flag = Chain.getValue(1);
406  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
407  }
408 
409  RetOps[0] = Chain; // Update chain.
410 
411  // Add the flag if we have it.
412  if (Flag.getNode())
413  RetOps.push_back(Flag);
414 
415  return DAG.getNode(Opc, DL, MVT::Other, RetOps);
416 }
417 
418 SDValue BPFTargetLowering::LowerCallResult(
419  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
420  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
421  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
422 
424  // Assign locations to each value returned by this call.
426  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
427 
428  if (Ins.size() >= 2) {
429  fail(DL, DAG, "only small returns supported");
430  for (unsigned i = 0, e = Ins.size(); i != e; ++i)
431  InVals.push_back(DAG.getConstant(0, DL, Ins[i].VT));
432  return DAG.getCopyFromReg(Chain, DL, 1, Ins[0].VT, InFlag).getValue(1);
433  }
434 
435  CCInfo.AnalyzeCallResult(Ins, RetCC_BPF64);
436 
437  // Copy all of the result registers out of their specified physreg.
438  for (auto &Val : RVLocs) {
439  Chain = DAG.getCopyFromReg(Chain, DL, Val.getLocReg(),
440  Val.getValVT(), InFlag).getValue(1);
441  InFlag = Chain.getValue(2);
442  InVals.push_back(Chain.getValue(0));
443  }
444 
445  return Chain;
446 }
447 
448 static void NegateCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) {
449  switch (CC) {
450  default:
451  break;
452  case ISD::SETULT:
453  case ISD::SETULE:
454  case ISD::SETLT:
455  case ISD::SETLE:
457  std::swap(LHS, RHS);
458  break;
459  }
460 }
461 
462 SDValue BPFTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
463  SDValue Chain = Op.getOperand(0);
464  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
465  SDValue LHS = Op.getOperand(2);
466  SDValue RHS = Op.getOperand(3);
467  SDValue Dest = Op.getOperand(4);
468  SDLoc DL(Op);
469 
470  if (!getHasJmpExt())
471  NegateCC(LHS, RHS, CC);
472 
473  return DAG.getNode(BPFISD::BR_CC, DL, Op.getValueType(), Chain, LHS, RHS,
474  DAG.getConstant(CC, DL, MVT::i64), Dest);
475 }
476 
477 SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
478  SDValue LHS = Op.getOperand(0);
479  SDValue RHS = Op.getOperand(1);
480  SDValue TrueV = Op.getOperand(2);
481  SDValue FalseV = Op.getOperand(3);
482  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
483  SDLoc DL(Op);
484 
485  if (!getHasJmpExt())
486  NegateCC(LHS, RHS, CC);
487 
488  SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i64);
489 
490  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
491  SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV};
492 
493  return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops);
494 }
495 
496 const char *BPFTargetLowering::getTargetNodeName(unsigned Opcode) const {
497  switch ((BPFISD::NodeType)Opcode) {
499  break;
500  case BPFISD::RET_FLAG:
501  return "BPFISD::RET_FLAG";
502  case BPFISD::CALL:
503  return "BPFISD::CALL";
504  case BPFISD::SELECT_CC:
505  return "BPFISD::SELECT_CC";
506  case BPFISD::BR_CC:
507  return "BPFISD::BR_CC";
508  case BPFISD::Wrapper:
509  return "BPFISD::Wrapper";
510  }
511  return nullptr;
512 }
513 
514 SDValue BPFTargetLowering::LowerGlobalAddress(SDValue Op,
515  SelectionDAG &DAG) const {
516  auto N = cast<GlobalAddressSDNode>(Op);
517  assert(N->getOffset() == 0 && "Invalid offset for global address");
518 
519  SDLoc DL(Op);
520  const GlobalValue *GV = N->getGlobal();
521  SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i64);
522 
523  return DAG.getNode(BPFISD::Wrapper, DL, MVT::i64, GA);
524 }
525 
528  MachineBasicBlock *BB) const {
530  DebugLoc DL = MI.getDebugLoc();
531  bool isSelectOp = MI.getOpcode() == BPF::Select;
532 
533  assert((isSelectOp || MI.getOpcode() == BPF::Select_Ri) && "Unexpected instr type to insert");
534 
535  // To "insert" a SELECT instruction, we actually have to insert the diamond
536  // control-flow pattern. The incoming instruction knows the destination vreg
537  // to set, the condition code register to branch on, the true/false values to
538  // select between, and a branch opcode to use.
539  const BasicBlock *LLVM_BB = BB->getBasicBlock();
541 
542  // ThisMBB:
543  // ...
544  // TrueVal = ...
545  // jmp_XX r1, r2 goto Copy1MBB
546  // fallthrough --> Copy0MBB
547  MachineBasicBlock *ThisMBB = BB;
548  MachineFunction *F = BB->getParent();
549  MachineBasicBlock *Copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
550  MachineBasicBlock *Copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
551 
552  F->insert(I, Copy0MBB);
553  F->insert(I, Copy1MBB);
554  // Update machine-CFG edges by transferring all successors of the current
555  // block to the new block which will contain the Phi node for the select.
556  Copy1MBB->splice(Copy1MBB->begin(), BB,
557  std::next(MachineBasicBlock::iterator(MI)), BB->end());
558  Copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
559  // Next, add the true and fallthrough blocks as its successors.
560  BB->addSuccessor(Copy0MBB);
561  BB->addSuccessor(Copy1MBB);
562 
563  // Insert Branch if Flag
564  unsigned LHS = MI.getOperand(1).getReg();
565  int CC = MI.getOperand(3).getImm();
566  int NewCC;
567  switch (CC) {
568  case ISD::SETGT:
569  NewCC = isSelectOp ? BPF::JSGT_rr : BPF::JSGT_ri;
570  break;
571  case ISD::SETUGT:
572  NewCC = isSelectOp ? BPF::JUGT_rr : BPF::JUGT_ri;
573  break;
574  case ISD::SETGE:
575  NewCC = isSelectOp ? BPF::JSGE_rr : BPF::JSGE_ri;
576  break;
577  case ISD::SETUGE:
578  NewCC = isSelectOp ? BPF::JUGE_rr : BPF::JUGE_ri;
579  break;
580  case ISD::SETEQ:
581  NewCC = isSelectOp ? BPF::JEQ_rr : BPF::JEQ_ri;
582  break;
583  case ISD::SETNE:
584  NewCC = isSelectOp ? BPF::JNE_rr : BPF::JNE_ri;
585  break;
586  case ISD::SETLT:
587  NewCC = isSelectOp ? BPF::JSLT_rr : BPF::JSLT_ri;
588  break;
589  case ISD::SETULT:
590  NewCC = isSelectOp ? BPF::JULT_rr : BPF::JULT_ri;
591  break;
592  case ISD::SETLE:
593  NewCC = isSelectOp ? BPF::JSLE_rr : BPF::JSLE_ri;
594  break;
595  case ISD::SETULE:
596  NewCC = isSelectOp ? BPF::JULE_rr : BPF::JULE_ri;
597  break;
598  default:
599  report_fatal_error("unimplemented select CondCode " + Twine(CC));
600  }
601  if (isSelectOp)
602  BuildMI(BB, DL, TII.get(NewCC))
603  .addReg(LHS)
604  .addReg(MI.getOperand(2).getReg())
605  .addMBB(Copy1MBB);
606  else {
607  int64_t imm32 = MI.getOperand(2).getImm();
608  // sanity check before we build J*_ri instruction.
609  assert (isInt<32>(imm32));
610  BuildMI(BB, DL, TII.get(NewCC))
611  .addReg(LHS)
612  .addImm(imm32)
613  .addMBB(Copy1MBB);
614  }
615 
616  // Copy0MBB:
617  // %FalseValue = ...
618  // # fallthrough to Copy1MBB
619  BB = Copy0MBB;
620 
621  // Update machine-CFG edges
622  BB->addSuccessor(Copy1MBB);
623 
624  // Copy1MBB:
625  // %Result = phi [ %FalseValue, Copy0MBB ], [ %TrueValue, ThisMBB ]
626  // ...
627  BB = Copy1MBB;
628  BuildMI(*BB, BB->begin(), DL, TII.get(BPF::PHI), MI.getOperand(0).getReg())
629  .addReg(MI.getOperand(5).getReg())
630  .addMBB(Copy0MBB)
631  .addReg(MI.getOperand(4).getReg())
632  .addMBB(ThisMBB);
633 
634  MI.eraseFromParent(); // The pseudo instruction is gone now.
635  return BB;
636 }
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
EVT getValueType() const
Return the ValueType of the referenced return value.
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
static void NegateCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC)
Diagnostic information for unsupported feature in backend.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it&#39;s not CSE&#39;d)...
Definition: SelectionDAG.h:814
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:617
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:222
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:268
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
unsigned getReg() const
getReg - Returns the register number.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:666
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:253
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
A debug info location.
Definition: DebugLoc.h:34
F(f)
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:404
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
Definition: Function.h:511
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:209
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:433
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
const HexagonInstrInfo * TII
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
Reg
All possible values of the reg field in the ModR/M byte.
SimpleValueType SimpleTy
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
LocInfo getLocInfo() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
SmallVector< ISD::InputArg, 32 > Ins
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:662
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:385
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
SmallVector< ISD::OutputArg, 32 > Outs
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:916
virtual const TargetInstrInfo * getInstrInfo() const
amdgpu Simplify well known AMD library false Value * Callee
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:121
TargetInstrInfo - Interface to description of machine instruction set.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Type * getReturnType() const
Returns the type of the ret val.
Definition: Function.h:150
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Machine Value Type.
LLVM Basic Block Representation.
Definition: BasicBlock.h:59
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:231
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:802
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
std::string getEVTString() const
This function returns value type as a string, e.g. "i32".
Definition: ValueTypes.cpp:120
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:57
void setPrefFunctionAlignment(unsigned Align)
Set the target&#39;s preferred function alignment.
self_iterator getIterator()
Definition: ilist_node.h:82
CondCode getSetCCSwappedOperands(CondCode Operation)
Return the operation corresponding to (Y op X) when given the operation for (X op Y)...
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:385
Extended Value Type.
Definition: ValueTypes.h:34
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const TargetRegisterInfo * getRegisterInfo() const override
Definition: BPFSubtarget.h:73
Iterator for intrusive lists based on ilist_node.
CCState - This class holds information needed while lowering arguments and return values...
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:301
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:209
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:864
const DebugLoc & getDebugLoc() const
CCValAssign - Represent assignment of one arg/retval to a location.
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:611
bool isAggregateType() const
Return true if the type is an aggregate type.
Definition: Type.h:255
const DataFlowGraph & G
Definition: RDFGraph.cpp:211
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
int64_t getImm() const
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:657
static mvt_range integer_valuetypes()
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:923
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:389
void setMinFunctionAlignment(unsigned Align)
Set the target&#39;s minimum function alignment (in log2(bytes))
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:445
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:448
amdgpu Simplify well known AMD library false Value Value * Arg
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:605
Representation of each machine instruction.
Definition: MachineInstr.h:59
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
SmallVector< SDValue, 32 > OutVals
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:683
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:205
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:463
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
unsigned MaxStoresPerMemmoveOptSize
Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OptSize attribute.
unsigned MaxStoresPerMemcpyOptSize
Maximum number of store operations that may be substituted for a call to memcpy, used for functions w...
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
unsigned getOpcode() const
SDValue getValue(unsigned R) const
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
bool isRegLoc() const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
BPFTargetLowering(const TargetMachine &TM, const BPFSubtarget &STI)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:462
void print(raw_ostream &OS, const SelectionDAG *G=nullptr) const
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the &#39;usesCustomInserter&#39; fla...
SDValue getRegister(unsigned Reg, EVT VT)
SDValue getValueType(EVT)
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:57
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:412
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
unsigned MaxStoresPerMemsetOptSize
Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute.
Conversion operators.
Definition: ISDOpcodes.h:442
const SDValue & getOperand(unsigned i) const
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
unsigned getLocReg() const
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:451
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
bool getHasJmpExt() const
Definition: BPFSubtarget.h:61
static void fail(const SDLoc &DL, SelectionDAG &DAG, const Twine &Msg)
LLVMContext * getContext() const
Definition: SelectionDAG.h:393
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:600
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:355
BRIND - Indirect branch.
Definition: ISDOpcodes.h:601
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...
Definition: ISDOpcodes.h:590