LLVM  9.0.0svn
MipsMachineFunction.cpp
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1 //===-- MipsMachineFunctionInfo.cpp - Private data used for Mips ----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "MipsMachineFunction.h"
11 #include "MipsSubtarget.h"
12 #include "MipsTargetMachine.h"
18 
19 using namespace llvm;
20 
21 static cl::opt<bool>
22 FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true),
23  cl::desc("Always use $gp as the global base register."));
24 
26 
28  return GlobalBaseReg;
29 }
30 
32  auto &STI = static_cast<const MipsSubtarget &>(MF.getSubtarget());
33  auto &TM = static_cast<const MipsTargetMachine &>(MF.getTarget());
34 
35  if (STI.inMips16Mode())
36  return Mips::CPU16RegsRegClass;
37 
38  if (STI.inMicroMipsMode())
39  return Mips::GPRMM16RegClass;
40 
41  if (TM.getABI().IsN64())
42  return Mips::GPR64RegClass;
43 
44  return Mips::GPR32RegClass;
45 }
46 
48  if (!GlobalBaseReg)
49  GlobalBaseReg =
51  return GlobalBaseReg;
52 }
53 
56  for (int I = 0; I < 4; ++I) {
57  const TargetRegisterClass &RC =
58  static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64()
59  ? Mips::GPR64RegClass
60  : Mips::GPR32RegClass;
61 
62  EhDataRegFI[I] = MF.getFrameInfo().CreateStackObject(TRI.getSpillSize(RC),
63  TRI.getSpillAlignment(RC), false);
64  }
65 }
66 
68  // ISRs require spill slots for Status & ErrorPC Coprocessor 0 registers.
69  // The current implementation only supports Mips32r2+ not Mips64rX. Status
70  // is always 32 bits, ErrorPC is 32 or 64 bits dependent on architecture,
71  // however Mips32r2+ is the supported architecture.
72  const TargetRegisterClass &RC = Mips::GPR32RegClass;
74 
75  for (int I = 0; I < 2; ++I)
76  ISRDataRegFI[I] = MF.getFrameInfo().CreateStackObject(
77  TRI.getSpillSize(RC), TRI.getSpillAlignment(RC), false);
78 }
79 
80 bool MipsFunctionInfo::isEhDataRegFI(int FI) const {
81  return CallsEhReturn && (FI == EhDataRegFI[0] || FI == EhDataRegFI[1]
82  || FI == EhDataRegFI[2] || FI == EhDataRegFI[3]);
83 }
84 
85 bool MipsFunctionInfo::isISRRegFI(int FI) const {
86  return IsISR && (FI == ISRDataRegFI[0] || FI == ISRDataRegFI[1]);
87 }
90 }
91 
94 }
95 
98  if (MoveF64ViaSpillFI == -1) {
99  MoveF64ViaSpillFI = MF.getFrameInfo().CreateStackObject(
100  TRI.getSpillSize(*RC), TRI.getSpillAlignment(*RC), false);
101  }
102  return MoveF64ViaSpillFI;
103 }
104 
105 void MipsFunctionInfo::anchor() {}
This class represents lattice values for constants.
Definition: AllocatorList.h:23
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
unsigned const TargetRegisterInfo * TRI
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
unsigned getSpillAlignment(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class...
MachinePointerInfo callPtrInfo(const char *ES)
Create a MachinePointerInfo that has an ExternalSymbolPseudoSourceValue object representing a GOT ent...
PseudoSourceValueManager & getPSVManager() const
static const TargetRegisterClass & getGlobalBaseRegClass(MachineFunction &MF)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:422
const PseudoSourceValue * getExternalSymbolCallEntry(const char *ES)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This class contains a discriminated union of information about pointers in memory operands...
const PseudoSourceValue * getGlobalValueCallEntry(const GlobalValue *GV)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
#define I(x, y, z)
Definition: MD5.cpp:58
int getMoveF64ViaSpillFI(const TargetRegisterClass *RC)
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
static cl::opt< bool > FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true), cl::desc("Always use $gp as the global base register."))
bool isEhDataRegFI(int FI) const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool isISRRegFI(int FI) const
~MipsFunctionInfo() override