LLVM  9.0.0svn
Macros | Functions | Variables
MipsISelLowering.cpp File Reference
#include "MipsISelLowering.h"
#include "InstPrinter/MipsInstPrinter.h"
#include "MCTargetDesc/MipsBaseInfo.h"
#include "MCTargetDesc/MipsMCTargetDesc.h"
#include "MipsCCState.h"
#include "MipsInstrInfo.h"
#include "MipsMachineFunction.h"
#include "MipsRegisterInfo.h"
#include "MipsSubtarget.h"
#include "MipsTargetMachine.h"
#include "MipsTargetObjectFile.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/Type.h"
#include "llvm/IR/Value.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MachineValueType.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include <algorithm>
#include <cassert>
#include <cctype>
#include <cstdint>
#include <deque>
#include <iterator>
#include <utility>
#include <vector>
#include "MipsGenCallingConv.inc"

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "mips-lower"
 

Functions

 STATISTIC (NumTailCalls, "Number of tail calls")
 
static bool isShiftedMask (uint64_t I, uint64_t &Pos, uint64_t &Size)
 
static SDValue performDivRemCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
 
static Mips::CondCode condCodeToFCC (ISD::CondCode CC)
 
static bool invertFPCondCodeUser (Mips::CondCode CC)
 This function returns true if the floating point conditional branches and conditional moves which use condition code CC should be inverted. More...
 
static SDValue createFPCmp (SelectionDAG &DAG, const SDValue &Op)
 
static SDValue createCMovFP (SelectionDAG &DAG, SDValue Cond, SDValue True, SDValue False, const SDLoc &DL)
 
static SDValue performSELECTCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
 
static SDValue performCMovFPCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
 
static SDValue performANDCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
 
static SDValue performORCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
 
static SDValue performMADD_MSUBCombine (SDNode *ROOTNode, SelectionDAG &CurDAG, const MipsSubtarget &Subtarget)
 
static SDValue performSUBCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
 
static SDValue performADDCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
 
static SDValue performSHLCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
 
static unsigned addLiveIn (MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
 
static MachineBasicBlockinsertDivByZeroTrap (MachineInstr &MI, MachineBasicBlock &MBB, const TargetInstrInfo &TII, bool Is64Bit, bool IsMicroMips)
 
static SDValue lowerFCOPYSIGN32 (SDValue Op, SelectionDAG &DAG, bool HasExtractInsert)
 
static SDValue lowerFCOPYSIGN64 (SDValue Op, SelectionDAG &DAG, bool HasExtractInsert)
 
static SDValue lowerFABS32 (SDValue Op, SelectionDAG &DAG, bool HasExtractInsert)
 
static SDValue lowerFABS64 (SDValue Op, SelectionDAG &DAG, bool HasExtractInsert)
 
static SDValue createLoadLR (unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, SDValue Chain, SDValue Src, unsigned Offset)
 
static SDValue createStoreLR (unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, SDValue Chain, unsigned Offset)
 
static SDValue lowerUnalignedIntStore (StoreSDNode *SD, SelectionDAG &DAG, bool IsLittle)
 
static SDValue lowerFP_TO_SINT_STORE (StoreSDNode *SD, SelectionDAG &DAG, bool SingleFloat)
 
static bool CC_MipsO32 (unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, ArrayRef< MCPhysReg > F64Regs)
 
static bool CC_MipsO32_FP32 (unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
 
static bool CC_MipsO32_FP64 (unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
 
static bool CC_MipsO32 (unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) LLVM_ATTRIBUTE_UNUSED
 
static unsigned getNextIntArgReg (unsigned Reg)
 
static SDValue UnpackFromArgumentSlot (SDValue Val, const CCValAssign &VA, EVT ArgVT, const SDLoc &DL, SelectionDAG &DAG)
 
static std::pair< bool, boolparsePhysicalReg (StringRef C, StringRef &Prefix, unsigned long long &Reg)
 This is a helper function to parse a physical register string and split it into non-numeric and numeric parts (Prefix and Reg). More...
 

Variables

static cl::opt< boolLargeGOT ("mxgot", cl::Hidden, cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false))
 
static cl::opt< boolNoZeroDivCheck ("mno-check-zero-division", cl::Hidden, cl::desc("MIPS: Don't trap on integer division by zero."), cl::init(false))
 
cl::opt< boolEmitJalrReloc
 
static const MCPhysReg Mips64DPRegs [8]
 

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "mips-lower"

Definition at line 81 of file MipsISelLowering.cpp.

Function Documentation

◆ addLiveIn()

static unsigned addLiveIn ( MachineFunction MF,
unsigned  PReg,
const TargetRegisterClass RC 
)
static

◆ CC_MipsO32() [1/2]

static bool CC_MipsO32 ( unsigned  ValNo,
MVT  ValVT,
MVT  LocVT,
CCValAssign::LocInfo  LocInfo,
ISD::ArgFlagsTy  ArgFlags,
CCState State,
ArrayRef< MCPhysReg >  F64Regs 
)
static

◆ CC_MipsO32() [2/2]

static bool CC_MipsO32 ( unsigned  ValNo,
MVT  ValVT,
MVT  LocVT,
CCValAssign::LocInfo  LocInfo,
ISD::ArgFlagsTy  ArgFlags,
CCState State 
)
static

◆ CC_MipsO32_FP32()

static bool CC_MipsO32_FP32 ( unsigned  ValNo,
MVT  ValVT,
MVT  LocVT,
CCValAssign::LocInfo  LocInfo,
ISD::ArgFlagsTy  ArgFlags,
CCState State 
)
static

Definition at line 2849 of file MipsISelLowering.cpp.

References CC_MipsO32().

◆ CC_MipsO32_FP64()

static bool CC_MipsO32_FP64 ( unsigned  ValNo,
MVT  ValVT,
MVT  LocVT,
CCValAssign::LocInfo  LocInfo,
ISD::ArgFlagsTy  ArgFlags,
CCState State 
)
static

Definition at line 2857 of file MipsISelLowering.cpp.

References CC_MipsO32(), and LLVM_ATTRIBUTE_UNUSED.

◆ condCodeToFCC()

static Mips::CondCode condCodeToFCC ( ISD::CondCode  CC)
static

◆ createCMovFP()

static SDValue createCMovFP ( SelectionDAG DAG,
SDValue  Cond,
SDValue  True,
SDValue  False,
const SDLoc DL 
)
static

◆ createFPCmp()

static SDValue createFPCmp ( SelectionDAG DAG,
const SDValue Op 
)
static

◆ createLoadLR()

static SDValue createLoadLR ( unsigned  Opc,
SelectionDAG DAG,
LoadSDNode LD,
SDValue  Chain,
SDValue  Src,
unsigned  Offset 
)
static

◆ createStoreLR()

static SDValue createStoreLR ( unsigned  Opc,
SelectionDAG DAG,
StoreSDNode SD,
SDValue  Chain,
unsigned  Offset 
)
static

◆ getNextIntArgReg()

static unsigned getNextIntArgReg ( unsigned  Reg)
static

◆ insertDivByZeroTrap()

static MachineBasicBlock* insertDivByZeroTrap ( MachineInstr MI,
MachineBasicBlock MBB,
const TargetInstrInfo TII,
bool  Is64Bit,
bool  IsMicroMips 
)
static

◆ invertFPCondCodeUser()

static bool invertFPCondCodeUser ( Mips::CondCode  CC)
static

This function returns true if the floating point conditional branches and conditional moves which use condition code CC should be inverted.

Definition at line 634 of file MipsISelLowering.cpp.

References assert(), llvm::Mips::FCOND_F, llvm::Mips::FCOND_GT, llvm::Mips::FCOND_NGT, and llvm::Mips::FCOND_T.

Referenced by createCMovFP(), and llvm::MipsTargetLowering::EmitInstrWithCustomInserter().

◆ isShiftedMask()

static bool isShiftedMask ( uint64_t  I,
uint64_t &  Pos,
uint64_t &  Size 
)
static

◆ lowerFABS32()

static SDValue lowerFABS32 ( SDValue  Op,
SelectionDAG DAG,
bool  HasExtractInsert 
)
static

◆ lowerFABS64()

static SDValue lowerFABS64 ( SDValue  Op,
SelectionDAG DAG,
bool  HasExtractInsert 
)
static

Definition at line 2346 of file MipsISelLowering.cpp.

References llvm::MipsTargetLowering::ABI, llvm::MachineFunction::addLiveIn(), llvm::ISD::AND, llvm::ISD::BITCAST, llvm::MipsISD::EH_RETURN, llvm::LLVMContext::emitError(), llvm::MipsISD::Ext, llvm::MVT::f64, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::MachineFunction::getDataLayout(), llvm::SelectionDAG::getEntryNode(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::TargetLoweringBase::getRegClassFor(), llvm::SelectionDAG::getRegister(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MipsSubtarget::hasExtractInsert(), llvm::MipsSubtarget::hasMips32(), llvm::MipsSubtarget::hasMips4(), llvm::MipsISD::Hi, llvm::MVT::i32, llvm::MVT::i64, llvm::MipsISD::Ins, llvm::MipsSubtarget::isGP64bit(), llvm::MipsABIInfo::IsN32(), llvm::MipsABIInfo::IsN64(), llvm::MipsISD::Lo, lowerFABS32(), llvm::ISD::OR, llvm::MVT::Other, RA, Reg, llvm::ISD::SELECT, llvm::MipsFunctionInfo::setCallsEhReturn(), llvm::MachineFrameInfo::setFrameAddressIsTaken(), llvm::MachineFrameInfo::setReturnAddressIsTaken(), llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::MipsTargetLowering::Subtarget, llvm::MipsISD::Sync, llvm::TargetLowering::verifyReturnAddressArgumentIsConstant(), X, and llvm::ISD::XOR.

◆ lowerFCOPYSIGN32()

static SDValue lowerFCOPYSIGN32 ( SDValue  Op,
SelectionDAG DAG,
bool  HasExtractInsert 
)
static

◆ lowerFCOPYSIGN64()

static SDValue lowerFCOPYSIGN64 ( SDValue  Op,
SelectionDAG DAG,
bool  HasExtractInsert 
)
static

◆ lowerFP_TO_SINT_STORE()

static SDValue lowerFP_TO_SINT_STORE ( StoreSDNode SD,
SelectionDAG DAG,
bool  SingleFloat 
)
static

◆ lowerUnalignedIntStore()

static SDValue lowerUnalignedIntStore ( StoreSDNode SD,
SelectionDAG DAG,
bool  IsLittle 
)
static

◆ parsePhysicalReg()

static std::pair<bool, bool> parsePhysicalReg ( StringRef  C,
StringRef Prefix,
unsigned long long &  Reg 
)
static

This is a helper function to parse a physical register string and split it into non-numeric and numeric parts (Prefix and Reg).

The first boolean flag that is returned indicates whether parsing was successful. The second flag is true if the numeric part exists.

Definition at line 3849 of file MipsISelLowering.cpp.

References B, llvm::StringRef::back(), llvm::StringRef::begin(), E, llvm::StringRef::end(), llvm::find_if(), llvm::StringRef::front(), llvm::getAsUnsignedInteger(), and I.

Referenced by llvm::MipsTargetLowering::getTypeForExtReturn().

◆ performADDCombine()

static SDValue performADDCombine ( SDNode N,
SelectionDAG DAG,
TargetLowering::DAGCombinerInfo DCI,
const MipsSubtarget Subtarget 
)
static

◆ performANDCombine()

static SDValue performANDCombine ( SDNode N,
SelectionDAG DAG,
TargetLowering::DAGCombinerInfo DCI,
const MipsSubtarget Subtarget 
)
static

◆ performCMovFPCombine()

static SDValue performCMovFPCombine ( SDNode N,
SelectionDAG DAG,
TargetLowering::DAGCombinerInfo DCI,
const MipsSubtarget Subtarget 
)
static

◆ performDivRemCombine()

static SDValue performDivRemCombine ( SDNode N,
SelectionDAG DAG,
TargetLowering::DAGCombinerInfo DCI,
const MipsSubtarget Subtarget 
)
static

◆ performMADD_MSUBCombine()

static SDValue performMADD_MSUBCombine ( SDNode ROOTNode,
SelectionDAG CurDAG,
const MipsSubtarget Subtarget 
)
static

◆ performORCombine()

static SDValue performORCombine ( SDNode N,
SelectionDAG DAG,
TargetLowering::DAGCombinerInfo DCI,
const MipsSubtarget Subtarget 
)
static

◆ performSELECTCombine()

static SDValue performSELECTCombine ( SDNode N,
SelectionDAG DAG,
TargetLowering::DAGCombinerInfo DCI,
const MipsSubtarget Subtarget 
)
static

◆ performSHLCombine()

static SDValue performSHLCombine ( SDNode N,
SelectionDAG DAG,
TargetLowering::DAGCombinerInfo DCI,
const MipsSubtarget Subtarget 
)
static

◆ performSUBCombine()

static SDValue performSUBCombine ( SDNode N,
SelectionDAG DAG,
TargetLowering::DAGCombinerInfo DCI,
const MipsSubtarget Subtarget 
)
static

◆ STATISTIC()

STATISTIC ( NumTailCalls  ,
"Number of tail calls  
)

◆ UnpackFromArgumentSlot()

static SDValue UnpackFromArgumentSlot ( SDValue  Val,
const CCValAssign VA,
EVT  ArgVT,
const SDLoc DL,
SelectionDAG DAG 
)
static

Definition at line 3405 of file MipsISelLowering.cpp.

References llvm::MipsTargetLowering::ABI, addLiveIn(), llvm::CCValAssign::AExt, llvm::CCValAssign::AExtUpper, llvm::CCState::AllocateStack(), llvm::MipsCCState::AnalyzeReturn(), llvm::ISD::ANY_EXTEND, llvm::Function::arg_begin(), llvm::Function::arg_empty(), assert(), llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, llvm::MipsISD::BuildPairF64, llvm::TargetLowering::C_Memory, llvm::TargetLowering::C_RegisterClass, llvm::MipsCCState::CheckReturn(), Context, llvm::MachineFrameInfo::CreateFixedObject(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::TargetLowering::CW_Constant, llvm::TargetLowering::CW_Default, llvm::TargetLowering::CW_Invalid, llvm::TargetLowering::CW_Memory, llvm::TargetLowering::CW_Register, llvm::TargetLowering::CW_SpecificReg, llvm::MipsISD::ERet, llvm::MVT::f32, llvm::MVT::f64, llvm::CCValAssign::Full, getBitWidth(), llvm::ISD::ArgFlagsTy::getByValSize(), llvm::MipsABIInfo::GetCalleeAllocdArgSizeInBytes(), llvm::SelectionDAG::getConstant(), llvm::TargetLowering::getConstraintType(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getEntryNode(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getLoad(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), getNextIntArgReg(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::TargetLoweringBase::getRegClassFor(), llvm::MachineFunction::getRegInfo(), llvm::SelectionDAG::getRegister(), llvm::TargetLowering::getSingleConstraintMatchWeight(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::MipsFunctionInfo::getSRetReturnReg(), llvm::Value::getType(), llvm::SDValue::getValue(), llvm::SelectionDAG::getValueType(), llvm::CCValAssign::getValVT(), llvm::Function::hasFnAttribute(), llvm::MipsSubtarget::hasMSA(), llvm::Function::hasStructRetAttr(), llvm::MVT::i32, llvm::MVT::i64, info, llvm::ISD::ArgFlagsTy::isByVal(), llvm::MVT::isFloatingPoint(), llvm::Type::isFloatTy(), llvm::Type::isIntegerTy(), llvm::MipsSubtarget::isLittle(), llvm::CCValAssign::isMemLoc(), llvm::MipsABIInfo::IsN32(), llvm::MipsABIInfo::IsN64(), llvm::MipsABIInfo::IsO32(), llvm::CCValAssign::isRegLoc(), llvm::Type::isVectorTy(), LLVM_FALLTHROUGH, llvm_unreachable, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T >::push_back(), Reg, llvm::report_fatal_error(), llvm::MipsISD::Ret, llvm::MipsFunctionInfo::setFormalArgInfo(), llvm::MipsFunctionInfo::setISR(), llvm::MipsFunctionInfo::setSRetReturnReg(), llvm::MipsFunctionInfo::setVarArgsFrameIndex(), llvm::CCValAssign::SExt, llvm::CCValAssign::SExtUpper, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::SmallVectorBase::size(), llvm::StringRef::size(), llvm::ISD::SRA, llvm::ISD::SRL, llvm::MipsTargetLowering::Subtarget, std::swap(), llvm::ISD::TokenFactor, llvm::ISD::TRUNCATE, llvm::MipsSubtarget::useSoftFloat(), llvm::ISD::ZERO_EXTEND, llvm::CCValAssign::ZExt, and llvm::CCValAssign::ZExtUpper.

Variable Documentation

◆ EmitJalrReloc

cl::opt<bool> EmitJalrReloc

◆ LargeGOT

cl::opt<bool> LargeGOT("mxgot", cl::Hidden, cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false))
static

◆ Mips64DPRegs

const MCPhysReg Mips64DPRegs[8]
static
Initial value:
= {
Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
}

Definition at line 96 of file MipsISelLowering.cpp.

Referenced by llvm::MipsTargetLowering::HandleByVal().

◆ NoZeroDivCheck

cl::opt<bool> NoZeroDivCheck("mno-check-zero-division", cl::Hidden, cl::desc("MIPS: Don't trap on integer division by zero."), cl::init(false))
static

Referenced by insertDivByZeroTrap().