LLVM  6.0.0svn
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AArch64InstructionSelector.cpp File Reference

This file implements the targeting of the InstructionSelector class for AArch64. More...

#include "AArch64InstrInfo.h"
#include "AArch64MachineFunctionInfo.h"
#include "AArch64RegisterBankInfo.h"
#include "AArch64RegisterInfo.h"
#include "AArch64Subtarget.h"
#include "AArch64TargetMachine.h"
#include "MCTargetDesc/AArch64AddressingModes.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
#include "llvm/CodeGen/GlobalISel/Utils.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/IR/Type.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "AArch64GenGlobalISel.inc"
Include dependency graph for AArch64InstructionSelector.cpp:

Go to the source code of this file.

Namespaces

 llvm
 Compute iterated dominance frontiers using a linear time algorithm.
 

Macros

#define DEBUG_TYPE   "aarch64-isel"
 
#define GET_GLOBALISEL_PREDICATE_BITSET
 
#define GET_GLOBALISEL_PREDICATES_DECL
 
#define GET_GLOBALISEL_TEMPORARIES_DECL
 
#define GET_GLOBALISEL_IMPL
 
#define GET_GLOBALISEL_PREDICATES_INIT
 
#define GET_GLOBALISEL_TEMPORARIES_INIT
 

Functions

static bool unsupportedBinOp (const MachineInstr &I, const AArch64RegisterBankInfo &RBI, const MachineRegisterInfo &MRI, const AArch64RegisterInfo &TRI)
 Check whether I is a currently unsupported binary operation: More...
 
static unsigned selectBinaryOp (unsigned GenericOpc, unsigned RegBankID, unsigned OpSize)
 Select the AArch64 opcode for the basic binary operation GenericOpc (such as G_OR or G_SDIV), appropriate for the register bank RegBankID and of size OpSize. More...
 
static unsigned selectLoadStoreUIOp (unsigned GenericOpc, unsigned RegBankID, unsigned OpSize)
 Select the AArch64 opcode for the G_LOAD or G_STORE operation GenericOpc, appropriate for the (value) register bank RegBankID and of memory access size OpSize. More...
 
static bool selectCopy (MachineInstr &I, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
 
static unsigned selectFPConvOpc (unsigned GenericOpc, LLT DstTy, LLT SrcTy)
 
static AArch64CC::CondCode changeICMPPredToAArch64CC (CmpInst::Predicate P)
 
static void changeFCMPPredToAArch64CC (CmpInst::Predicate P, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2)
 
InstructionSelectorllvm::createAArch64InstructionSelector (const AArch64TargetMachine &, AArch64Subtarget &, AArch64RegisterBankInfo &)
 

Detailed Description

This file implements the targeting of the InstructionSelector class for AArch64.

Todo:
This should be generated by TableGen.

Definition in file AArch64InstructionSelector.cpp.

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "aarch64-isel"

Definition at line 35 of file AArch64InstructionSelector.cpp.

◆ GET_GLOBALISEL_IMPL

#define GET_GLOBALISEL_IMPL

Definition at line 114 of file AArch64InstructionSelector.cpp.

◆ GET_GLOBALISEL_PREDICATE_BITSET

#define GET_GLOBALISEL_PREDICATE_BITSET

Definition at line 41 of file AArch64InstructionSelector.cpp.

◆ GET_GLOBALISEL_PREDICATES_DECL

#define GET_GLOBALISEL_PREDICATES_DECL

Definition at line 101 of file AArch64InstructionSelector.cpp.

◆ GET_GLOBALISEL_PREDICATES_INIT

#define GET_GLOBALISEL_PREDICATES_INIT

◆ GET_GLOBALISEL_TEMPORARIES_DECL

#define GET_GLOBALISEL_TEMPORARIES_DECL

Definition at line 107 of file AArch64InstructionSelector.cpp.

◆ GET_GLOBALISEL_TEMPORARIES_INIT

#define GET_GLOBALISEL_TEMPORARIES_INIT

Function Documentation

◆ changeFCMPPredToAArch64CC()

static void changeFCMPPredToAArch64CC ( CmpInst::Predicate  P,
AArch64CC::CondCode CondCode,
AArch64CC::CondCode CondCode2 
)
static

Definition at line 480 of file AArch64InstructionSelector.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addGlobalAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstr::addOperand(), llvm::MachineInstrBuilder::addUse(), llvm::AArch64CC::AL, llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, assert(), llvm::APFloat::bitcastToAPInt(), llvm::ISD::BR, llvm::BuildMI(), changeICMPPredToAArch64CC(), llvm::MachineOperand::ChangeToFrameIndex(), llvm::MachineOperand::ChangeToImmediate(), llvm::RegisterBankInfo::constrainGenericRegister(), llvm::MachineRegisterInfo::createGenericVirtualRegister(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::dbgs(), DEBUG, llvm::tgtok::Def, llvm::PointerUnion< PT1, PT2 >::dyn_cast(), llvm::AArch64_AM::encodeLogicalImmediate(), EQ, llvm::MachineInstr::eraseFromParent(), llvm::AArch64CC::GE, llvm::PointerUnion< PT1, PT2 >::get(), llvm::ConstantInt::getBitWidth(), llvm::MachineOperand::getCImm(), llvm::getConstantVRegVal(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getFPImm(), llvm::MachineOperand::getGlobal(), llvm::RegisterBank::getID(), llvm::MachineOperand::getImm(), llvm::MachineFunction::getInfo(), llvm::AArch64CC::getInvertedCondCode(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getNumOperands(), llvm::MachineOperand::getOffset(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getParent(), llvm::MachineOperand::getPredicate(), llvm::MachineOperand::getReg(), llvm::RegisterBankInfo::getRegBank(), llvm::MachineRegisterInfo::getRegClassOrRegBank(), llvm::MachineFunction::getRegInfo(), llvm::ConstantInt::getSExtValue(), llvm::AArch64_AM::getShifterImm(), llvm::LLT::getSizeInBits(), llvm::getSizeInBits(), llvm::MachineRegisterInfo::getType(), llvm::ConstantFP::getValueAPF(), llvm::AArch64FunctionInfo::getVarArgsStackIndex(), llvm::MachineRegisterInfo::getVRegDef(), llvm::ConstantInt::getZExtValue(), llvm::APInt::getZExtValue(), llvm::AArch64CC::GT, llvm::AArch64CC::HI, I, llvm::MachineOperand::isCImm(), llvm::MachineInstr::isCopy(), llvm::APFloat::isExactlyValue(), llvm::MachineOperand::isImm(), llvm::LLT::isPointer(), llvm::isPreISelGenericOpcode(), llvm::MachineOperand::isReg(), llvm::LLT::isScalar(), llvm::LLT::isValid(), llvm::AArch64CC::LE, llvm_unreachable, llvm::AArch64ISD::LOADgot, llvm::Log2_32(), llvm::AArch64CC::LS, llvm::AArch64_AM::LSL, llvm::AArch64CC::LT, llvm::BitmaskEnumDetail::Mask(), llvm::MachineInstr::memoperands_begin(), MI, llvm::AArch64II::MO_GOT, llvm::AArch64II::MO_NC, llvm::AArch64II::MO_PAGE, llvm::AArch64II::MO_PAGEOFF, MRI, llvm::AArch64CC::NE, llvm::None, llvm::AArch64CC::PL, selectBinaryOp(), selectCopy(), selectFPConvOpc(), selectLoadStoreUIOp(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setImm(), llvm::MachineOperand::setReg(), llvm::MachineOperand::setSubReg(), llvm::MachineOperand::setTargetFlags(), llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Size, std::swap(), TII, llvm::SystemZISD::TM, unsupportedBinOp(), llvm::AArch64CC::VC, and llvm::AArch64CC::VS.

◆ changeICMPPredToAArch64CC()

static AArch64CC::CondCode changeICMPPredToAArch64CC ( CmpInst::Predicate  P)
static

◆ selectBinaryOp()

static unsigned selectBinaryOp ( unsigned  GenericOpc,
unsigned  RegBankID,
unsigned  OpSize 
)
static

Select the AArch64 opcode for the basic binary operation GenericOpc (such as G_OR or G_SDIV), appropriate for the register bank RegBankID and of size OpSize.

Returns
GenericOpc if the combination is unsupported.

Definition at line 210 of file AArch64InstructionSelector.cpp.

Referenced by CC_MipsO32_FP64(), changeFCMPPredToAArch64CC(), and isSExtLoad().

◆ selectCopy()

static bool selectCopy ( MachineInstr I,
const TargetInstrInfo TII,
MachineRegisterInfo MRI,
const TargetRegisterInfo TRI,
const RegisterBankInfo RBI 
)
static

◆ selectFPConvOpc()

static unsigned selectFPConvOpc ( unsigned  GenericOpc,
LLT  DstTy,
LLT  SrcTy 
)
static

◆ selectLoadStoreUIOp()

static unsigned selectLoadStoreUIOp ( unsigned  GenericOpc,
unsigned  RegBankID,
unsigned  OpSize 
)
static

Select the AArch64 opcode for the G_LOAD or G_STORE operation GenericOpc, appropriate for the (value) register bank RegBankID and of memory access size OpSize.

This returns the variant with the base+unsigned-immediate addressing mode (e.g., LDRXui).

Returns
GenericOpc if the combination is unsupported.

Definition at line 281 of file AArch64InstructionSelector.cpp.

References isStore().

Referenced by changeFCMPPredToAArch64CC().

◆ unsupportedBinOp()

static bool unsupportedBinOp ( const MachineInstr I,
const AArch64RegisterBankInfo RBI,
const MachineRegisterInfo MRI,
const AArch64RegisterInfo TRI 
)
static

Check whether I is a currently unsupported binary operation:

  • it has an unsized type
  • an operand is not a vreg
  • all operands are not in the same bank These are checks that should someday live in the verifier, but right now, these are mostly limitations of the aarch64 selector.

Definition at line 164 of file AArch64InstructionSelector.cpp.

References llvm::dbgs(), DEBUG, llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::RegisterBankInfo::getRegBank(), llvm::MachineRegisterInfo::getType(), llvm::LLT::isValid(), MRI, and llvm::MachineInstr::operands().

Referenced by changeFCMPPredToAArch64CC().