LLVM  9.0.0svn
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AArch64InstructionSelector.cpp File Reference

This file implements the targeting of the InstructionSelector class for AArch64. More...

#include "AArch64InstrInfo.h"
#include "AArch64MachineFunctionInfo.h"
#include "AArch64RegisterBankInfo.h"
#include "AArch64RegisterInfo.h"
#include "AArch64Subtarget.h"
#include "AArch64TargetMachine.h"
#include "MCTargetDesc/AArch64AddressingModes.h"
#include "llvm/ADT/Optional.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/GlobalISel/Utils.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/IR/Type.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "AArch64GenGlobalISel.inc"
Include dependency graph for AArch64InstructionSelector.cpp:

Go to the source code of this file.

Namespaces

 llvm
 This class represents lattice values for constants.
 

Macros

#define DEBUG_TYPE   "aarch64-isel"
 
#define GET_GLOBALISEL_PREDICATE_BITSET
 
#define GET_GLOBALISEL_PREDICATES_DECL
 
#define GET_GLOBALISEL_TEMPORARIES_DECL
 
#define GET_GLOBALISEL_IMPL
 
#define GET_GLOBALISEL_PREDICATES_INIT
 
#define GET_GLOBALISEL_TEMPORARIES_INIT
 

Functions

static const TargetRegisterClassgetMinClassForRegBank (const RegisterBank &RB, unsigned SizeInBits, bool GetAllRegSet=false)
 Given a register bank, and size in bits, return the smallest register class that can represent that combination. More...
 
static bool getSubRegForClass (const TargetRegisterClass *RC, const TargetRegisterInfo &TRI, unsigned &SubReg)
 Returns the correct subregister to use for a given register class. More...
 
static bool unsupportedBinOp (const MachineInstr &I, const AArch64RegisterBankInfo &RBI, const MachineRegisterInfo &MRI, const AArch64RegisterInfo &TRI)
 Check whether I is a currently unsupported binary operation: More...
 
static unsigned selectBinaryOp (unsigned GenericOpc, unsigned RegBankID, unsigned OpSize)
 Select the AArch64 opcode for the basic binary operation GenericOpc (such as G_OR or G_SDIV), appropriate for the register bank RegBankID and of size OpSize. More...
 
static unsigned selectLoadStoreUIOp (unsigned GenericOpc, unsigned RegBankID, unsigned OpSize)
 Select the AArch64 opcode for the G_LOAD or G_STORE operation GenericOpc, appropriate for the (value) register bank RegBankID and of memory access size OpSize. More...
 
static bool isValidCopy (const MachineInstr &I, const RegisterBank &DstBank, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
 Helper function that verifies that we have a valid copy at the end of selectCopy. More...
 
static bool selectSubregisterCopy (MachineInstr &I, MachineRegisterInfo &MRI, const RegisterBankInfo &RBI, unsigned SrcReg, const TargetRegisterClass *From, const TargetRegisterClass *To, unsigned SubReg)
 Helper function for selectCopy. More...
 
static bool selectCopy (MachineInstr &I, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
 
static unsigned selectFPConvOpc (unsigned GenericOpc, LLT DstTy, LLT SrcTy)
 
static AArch64CC::CondCode changeICMPPredToAArch64CC (CmpInst::Predicate P)
 
static void changeFCMPPredToAArch64CC (CmpInst::Predicate P, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2)
 
static bool getLaneCopyOpcode (unsigned &CopyOpc, unsigned &ExtractSubReg, const unsigned EltSize)
 
static bool getConstantValueForReg (unsigned Reg, MachineRegisterInfo &MRI, unsigned &Val)
 Given a register Reg, find the value of a constant defining Reg. More...
 
static std::pair< unsigned, unsignedgetInsertVecEltOpInfo (const RegisterBank &RB, unsigned EltSize)
 Return an <Opcode, SubregIndex> pair to do an vector elt insert of a given size and RB. More...
 
InstructionSelectorllvm::createAArch64InstructionSelector (const AArch64TargetMachine &, AArch64Subtarget &, AArch64RegisterBankInfo &)
 

Detailed Description

This file implements the targeting of the InstructionSelector class for AArch64.

Todo:
This should be generated by TableGen.

Definition in file AArch64InstructionSelector.cpp.

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "aarch64-isel"

Definition at line 37 of file AArch64InstructionSelector.cpp.

◆ GET_GLOBALISEL_IMPL

#define GET_GLOBALISEL_IMPL

Definition at line 165 of file AArch64InstructionSelector.cpp.

◆ GET_GLOBALISEL_PREDICATE_BITSET

#define GET_GLOBALISEL_PREDICATE_BITSET

Definition at line 43 of file AArch64InstructionSelector.cpp.

◆ GET_GLOBALISEL_PREDICATES_DECL

#define GET_GLOBALISEL_PREDICATES_DECL

Definition at line 152 of file AArch64InstructionSelector.cpp.

◆ GET_GLOBALISEL_PREDICATES_INIT

#define GET_GLOBALISEL_PREDICATES_INIT

◆ GET_GLOBALISEL_TEMPORARIES_DECL

#define GET_GLOBALISEL_TEMPORARIES_DECL

Definition at line 158 of file AArch64InstructionSelector.cpp.

◆ GET_GLOBALISEL_TEMPORARIES_INIT

#define GET_GLOBALISEL_TEMPORARIES_INIT

Function Documentation

◆ changeFCMPPredToAArch64CC()

static void changeFCMPPredToAArch64CC ( CmpInst::Predicate  P,
AArch64CC::CondCode CondCode,
AArch64CC::CondCode CondCode2 
)
static

Definition at line 708 of file AArch64InstructionSelector.cpp.

References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addGlobalAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstr::addOperand(), llvm::MachineInstrBuilder::addUse(), llvm::AArch64ISD::ADR, llvm::AArch64CC::AL, llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, assert(), llvm::AMDGPUISD::BFM, llvm::APFloat::bitcastToAPInt(), llvm::ISD::BR, llvm::MachineIRBuilder::buildCopy(), llvm::MachineIRBuilder::buildInstr(), llvm::BuildMI(), changeICMPPredToAArch64CC(), llvm::MachineOperand::ChangeToFrameIndex(), llvm::MachineOperand::ChangeToImmediate(), llvm::ARCISD::CMP, llvm::MachineInstrBuilder::constrainAllUses(), llvm::RegisterBankInfo::constrainGenericRegister(), llvm::constrainSelectedInstRegOperands(), llvm::MachineRegisterInfo::createGenericVirtualRegister(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::dbgs(), llvm::PointerUnion< PT1, PT2 >::dyn_cast(), llvm::AArch64_AM::encodeLogicalImmediate(), EQ, llvm::MachineInstr::eraseFromParent(), llvm::AArch64CC::GE, llvm::PointerUnion< PT1, PT2 >::get(), llvm::MachineOperand::getBlockAddress(), llvm::MachineOperand::getCImm(), llvm::getConstantVRegVal(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getFPImm(), llvm::MachineFunction::getFunction(), llvm::MachineOperand::getGlobal(), llvm::RegisterBank::getID(), llvm::MachineOperand::getImm(), llvm::MachineFunction::getInfo(), llvm::MachineOperand::getIntrinsicID(), llvm::AArch64CC::getInvertedCondCode(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineIRBuilder::getMBB(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getNumOperands(), llvm::MachineOperand::getOffset(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getPredicate(), llvm::MachineOperand::getReg(), llvm::RegisterBankInfo::getRegBank(), llvm::MachineRegisterInfo::getRegClassOrRegBank(), llvm::MachineFunction::getRegInfo(), llvm::LLT::getSizeInBits(), llvm::getSizeInBits(), llvm::MachineRegisterInfo::getType(), llvm::ConstantFP::getValueAPF(), llvm::AArch64FunctionInfo::getVarArgsStackIndex(), llvm::MachineRegisterInfo::getVRegDef(), llvm::ConstantInt::getZExtValue(), llvm::APInt::getZExtValue(), llvm::AArch64CC::GT, llvm::Function::hasFnAttribute(), llvm::AArch64CC::HI, llvm::AArch64CC::HS, I, llvm::MipsISD::Ins, llvm::MachineOperand::isCImm(), llvm::MachineInstr::isCopy(), llvm::APFloat::isExactlyValue(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isIntrinsicID(), llvm::LLT::isPointer(), llvm::isPreISelGenericOpcode(), llvm::MachineOperand::isReg(), llvm::LLT::isScalar(), llvm::LLT::isValid(), llvm::LLT::isVector(), llvm::CodeModel::Large, llvm::AArch64CC::LE, LLVM_DEBUG, llvm_unreachable, llvm::AArch64ISD::LOADgot, llvm::Log2_32(), llvm::AArch64CC::LS, llvm::AArch64CC::LT, llvm::BitmaskEnumDetail::Mask(), llvm::MachineInstr::memoperands_begin(), MI, llvm::AArch64II::MO_G0, llvm::AArch64II::MO_G1, llvm::AArch64II::MO_G2, llvm::AArch64II::MO_G3, llvm::AArch64II::MO_GOT, llvm::AArch64II::MO_NC, llvm::AArch64II::MO_PAGE, llvm::AArch64II::MO_PAGEOFF, MRI, llvm::AArch64CC::NE, llvm::AArch64CC::PL, llvm::NVPTX::PTXLdStInstCode::Scalar, selectBinaryOp(), selectCopy(), selectFPConvOpc(), llvm::mca::selectImpl(), selectLoadStoreUIOp(), selectMergeValues(), selectUnmergeValues(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setImm(), llvm::MachineIRBuilder::setInsertPt(), llvm::MachineOperand::setReg(), llvm::MachineOperand::setSubReg(), llvm::MachineOperand::setTargetFlags(), Size, std::swap(), TII, llvm::CodeModel::Tiny, llvm::SystemZISD::TM, TRI, llvm::RegState::Undef, unsupportedBinOp(), llvm::AArch64CC::VC, and llvm::AArch64CC::VS.

◆ changeICMPPredToAArch64CC()

static AArch64CC::CondCode changeICMPPredToAArch64CC ( CmpInst::Predicate  P)
static

◆ getConstantValueForReg()

static bool getConstantValueForReg ( unsigned  Reg,
MachineRegisterInfo MRI,
unsigned Val 
)
static

Given a register Reg, find the value of a constant defining Reg.

Return true if one could be found, and store it in Val. Return false otherwise.

Definition at line 1876 of file AArch64InstructionSelector.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addUse(), llvm::AArch64ISD::ADRP, llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, assert(), llvm::MachineIRBuilder::buildCopy(), llvm::MachineIRBuilder::buildInstr(), llvm::BuildMI(), llvm::RegisterBankInfo::constrainGenericRegister(), llvm::constrainSelectedInstRegOperands(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::dbgs(), llvm::tgtok::Def, llvm::MachineInstr::eraseFromParent(), llvm::find_if_not(), llvm::MachineOperand::getCImm(), llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstantPoolIndex(), llvm::MachineIRBuilder::getDataLayout(), llvm::MachineFunction::getDataLayout(), llvm::MachineInstr::getDebugLoc(), llvm::RegisterBank::getID(), getID(), getLaneCopyOpcode(), llvm::ConstantInt::getLimitedValue(), llvm::MachineIRBuilder::getMF(), llvm::MachineIRBuilder::getMRI(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::Type::getPointerTo(), llvm::DataLayout::getPrefTypeAlignment(), llvm::MachineOperand::getReg(), llvm::RegisterBankInfo::getRegBank(), llvm::MachineRegisterInfo::getRegClassOrNull(), llvm::ConstantInt::getSExtValue(), llvm::LLT::getSizeInBits(), llvm::Value::getType(), llvm::MachineRegisterInfo::getType(), llvm::DataLayout::getTypeAllocSize(), llvm::DataLayout::getTypeStoreSize(), llvm::MachineRegisterInfo::getVRegDef(), llvm::MachineInstr::isCopy(), llvm::LLT::isScalar(), llvm::LLT::isVector(), LLVM_DEBUG, MI, llvm::AArch64II::MO_NC, llvm::AArch64II::MO_PAGE, llvm::AArch64II::MO_PAGEOFF, MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MachineRegisterInfo::reg_instr_nodbg_end(), llvm::MachineRegisterInfo::reg_nodbg_instructions(), selectUnmergeValues(), TII, and TRI.

Referenced by getInsertVecEltOpInfo().

◆ getInsertVecEltOpInfo()

static std::pair<unsigned, unsigned> getInsertVecEltOpInfo ( const RegisterBank RB,
unsigned  EltSize 
)
static

Return an <Opcode, SubregIndex> pair to do an vector elt insert of a given size and RB.

Definition at line 2232 of file AArch64InstructionSelector.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addUse(), assert(), llvm::MachineIRBuilder::buildCopy(), llvm::MachineIRBuilder::buildInstr(), Concat, llvm::RegisterBankInfo::constrainGenericRegister(), llvm::constrainSelectedInstRegOperands(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::dbgs(), llvm::tgtok::Def, llvm::SmallVectorImpl< T >::emplace_back(), llvm::SmallVectorBase::empty(), llvm::MachineInstr::eraseFromParent(), llvm::ConstantInt::getBitWidth(), llvm::MachineOperand::getCImm(), getConstantValueForReg(), llvm::getConstantVRegVal(), llvm::Function::getContext(), llvm::LLT::getElementType(), llvm::MachineFunction::getFunction(), llvm::RegisterBank::getID(), llvm::MachineOperand::getImm(), llvm::MachineIRBuilder::getMF(), getMinClassForRegBank(), llvm::MachineIRBuilder::getMRI(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::RegisterBankInfo::getRegBank(), llvm::MachineFunction::getRegInfo(), llvm::ConstantInt::getSExtValue(), llvm::AArch64_AM::getShifterImm(), llvm::LLT::getSizeInBits(), getSubRegForClass(), llvm::MachineRegisterInfo::getType(), llvm::MachineRegisterInfo::getVRegDef(), llvm::ConstantInt::getZExtValue(), llvm::MachineOperand::isCImm(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm::LLT::isVector(), LLVM_DEBUG, llvm_unreachable, llvm::Log2_32(), llvm::AArch64_AM::LSL, llvm::BitmaskEnumDetail::Mask(), MI, MRI, llvm::None, Reg, llvm::MachineOperand::setReg(), Size, SubReg, TII, and TRI.

◆ getLaneCopyOpcode()

static bool getLaneCopyOpcode ( unsigned CopyOpc,
unsigned ExtractSubReg,
const unsigned  EltSize 
)
static

Definition at line 1848 of file AArch64InstructionSelector.cpp.

References llvm::dbgs(), and LLVM_DEBUG.

Referenced by getConstantValueForReg().

◆ getMinClassForRegBank()

static const TargetRegisterClass* getMinClassForRegBank ( const RegisterBank RB,
unsigned  SizeInBits,
bool  GetAllRegSet = false 
)
static

Given a register bank, and size in bits, return the smallest register class that can represent that combination.

Definition at line 217 of file AArch64InstructionSelector.cpp.

References llvm::RegisterBank::getID().

Referenced by getInsertVecEltOpInfo(), and selectCopy().

◆ getSubRegForClass()

static bool getSubRegForClass ( const TargetRegisterClass RC,
const TargetRegisterInfo TRI,
unsigned SubReg 
)
static

Returns the correct subregister to use for a given register class.

Definition at line 251 of file AArch64InstructionSelector.cpp.

References llvm::dbgs(), llvm::TargetRegisterInfo::getRegSizeInBits(), and LLVM_DEBUG.

Referenced by getInsertVecEltOpInfo(), and selectCopy().

◆ isValidCopy()

static bool isValidCopy ( const MachineInstr I,
const RegisterBank DstBank,
const MachineRegisterInfo MRI,
const TargetRegisterInfo TRI,
const RegisterBankInfo RBI 
)
static

Helper function that verifies that we have a valid copy at the end of selectCopy.

Verifies that the source and dest have the expected sizes and then returns true.

Definition at line 437 of file AArch64InstructionSelector.cpp.

References assert(), llvm::RegisterBank::getID(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().

Referenced by selectCopy().

◆ selectBinaryOp()

static unsigned selectBinaryOp ( unsigned  GenericOpc,
unsigned  RegBankID,
unsigned  OpSize 
)
static

Select the AArch64 opcode for the basic binary operation GenericOpc (such as G_OR or G_SDIV), appropriate for the register bank RegBankID and of size OpSize.

Returns
GenericOpc if the combination is unsupported.

Definition at line 330 of file AArch64InstructionSelector.cpp.

Referenced by CC_MipsO32_FP64(), changeFCMPPredToAArch64CC(), isSExtLoad(), and llvm::FastISel::selectOperator().

◆ selectCopy()

static bool selectCopy ( MachineInstr I,
const TargetInstrInfo TII,
MachineRegisterInfo MRI,
const TargetRegisterInfo TRI,
const RegisterBankInfo RBI 
)
static

◆ selectFPConvOpc()

static unsigned selectFPConvOpc ( unsigned  GenericOpc,
LLT  DstTy,
LLT  SrcTy 
)
static

◆ selectLoadStoreUIOp()

static unsigned selectLoadStoreUIOp ( unsigned  GenericOpc,
unsigned  RegBankID,
unsigned  OpSize 
)
static

Select the AArch64 opcode for the G_LOAD or G_STORE operation GenericOpc, appropriate for the (value) register bank RegBankID and of memory access size OpSize.

This returns the variant with the base+unsigned-immediate addressing mode (e.g., LDRXui).

Returns
GenericOpc if the combination is unsupported.

Definition at line 401 of file AArch64InstructionSelector.cpp.

References isStore().

Referenced by changeFCMPPredToAArch64CC().

◆ selectSubregisterCopy()

static bool selectSubregisterCopy ( MachineInstr I,
MachineRegisterInfo MRI,
const RegisterBankInfo RBI,
unsigned  SrcReg,
const TargetRegisterClass From,
const TargetRegisterClass To,
unsigned  SubReg 
)
static

Helper function for selectCopy.

Inserts a subregister copy from *From to *To, linking it up to I.

e.g, given I = "Dst = COPY SrcReg", we'll transform that into

CopyReg (From class) = COPY SrcReg SubRegCopy (To class) = COPY CopyReg:SubReg Dst = COPY SubRegCopy

Definition at line 474 of file AArch64InstructionSelector.cpp.

References llvm::MachineIRBuilder::buildCopy(), llvm::RegisterBankInfo::constrainGenericRegister(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), MRI, llvm::MachineOperand::setReg(), and SubReg.

Referenced by selectCopy().

◆ unsupportedBinOp()

static bool unsupportedBinOp ( const MachineInstr I,
const AArch64RegisterBankInfo RBI,
const MachineRegisterInfo MRI,
const AArch64RegisterInfo TRI 
)
static

Check whether I is a currently unsupported binary operation:

  • it has an unsized type
  • an operand is not a vreg
  • all operands are not in the same bank These are checks that should someday live in the verifier, but right now, these are mostly limitations of the aarch64 selector.

Definition at line 284 of file AArch64InstructionSelector.cpp.

References llvm::dbgs(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::RegisterBankInfo::getRegBank(), llvm::MachineRegisterInfo::getType(), llvm::LLT::isValid(), LLVM_DEBUG, MRI, llvm::MachineInstr::operands(), and TRI.

Referenced by changeFCMPPredToAArch64CC().