LLVM  10.0.0svn
AArch64RegisterBankInfo.h
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1 //===- AArch64RegisterBankInfo -----------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the RegisterBankInfo class for AArch64.
10 /// \todo This should be generated by TableGen.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERBANKINFO_H
14 #define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERBANKINFO_H
15 
17 
18 #define GET_REGBANK_DECLARATIONS
19 #include "AArch64GenRegisterBank.inc"
20 
21 namespace llvm {
22 
23 class TargetRegisterInfo;
24 
26 protected:
28  PMI_None = -1,
29  PMI_FPR16 = 1,
42  };
43 
47 
61  };
62 
63  static bool checkPartialMap(unsigned Idx, unsigned ValStartIdx,
64  unsigned ValLength, const RegisterBank &RB);
65  static bool checkValueMapImpl(unsigned Idx, unsigned FirstInBank,
66  unsigned Size, unsigned Offset);
67  static bool checkPartialMappingIdx(PartialMappingIdx FirstAlias,
68  PartialMappingIdx LastAlias,
70 
71  static unsigned getRegBankBaseIdxOffset(unsigned RBIdx, unsigned Size);
72 
73  /// Get the pointer to the ValueMapping representing the RegisterBank
74  /// at \p RBIdx with a size of \p Size.
75  ///
76  /// The returned mapping works for instructions with the same kind of
77  /// operands for up to 3 operands.
78  ///
79  /// \pre \p RBIdx != PartialMappingIdx::None
80  static const RegisterBankInfo::ValueMapping *
81  getValueMapping(PartialMappingIdx RBIdx, unsigned Size);
82 
83  /// Get the pointer to the ValueMapping of the operands of a copy
84  /// instruction from the \p SrcBankID register bank to the \p DstBankID
85  /// register bank with a size of \p Size.
86  static const RegisterBankInfo::ValueMapping *
87  getCopyMapping(unsigned DstBankID, unsigned SrcBankID, unsigned Size);
88 
89  /// Get the instruction mapping for G_FPEXT.
90  ///
91  /// \pre (DstSize, SrcSize) pair is one of the following:
92  /// (32, 16), (64, 16), (64, 32), (128, 64)
93  ///
94  /// \return An InstructionMapping with statically allocated OperandsMapping.
95  static const RegisterBankInfo::ValueMapping *
96  getFPExtMapping(unsigned DstSize, unsigned SrcSize);
97 
98 #define GET_TARGET_REGBANK_CLASS
99 #include "AArch64GenRegisterBank.inc"
100 };
101 
102 /// This class provides the information for the target register banks.
104  /// See RegisterBankInfo::applyMapping.
105  void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
106 
107  /// Get an instruction mapping where all the operands map to
108  /// the same register bank and have similar size.
109  ///
110  /// \pre MI.getNumOperands() <= 3
111  ///
112  /// \return An InstructionMappings with a statically allocated
113  /// OperandsMapping.
114  const InstructionMapping &
115  getSameKindOfOperandsMapping(const MachineInstr &MI) const;
116 
117  /// Returns true if the output of \p MI must be stored on a FPR register.
118  bool hasFPConstraints(const MachineInstr &MI, const MachineRegisterInfo &MRI,
119  const TargetRegisterInfo &TRI) const;
120 
121  /// Returns true if the source registers of \p MI must all be FPRs.
122  bool onlyUsesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
123  const TargetRegisterInfo &TRI) const;
124 
125  /// Returns true if the destination register of \p MI must be a FPR.
126  bool onlyDefinesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
127  const TargetRegisterInfo &TRI) const;
128 
129 public:
131 
132  unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
133  unsigned Size) const override;
134 
135  const RegisterBank &
136  getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
137 
139  getInstrAlternativeMappings(const MachineInstr &MI) const override;
140 
141  const InstructionMapping &
142  getInstrMapping(const MachineInstr &MI) const override;
143 };
144 } // End llvm namespace.
145 #endif
This class represents lattice values for constants.
Definition: AllocatorList.h:23
static const RegisterBankInfo::ValueMapping * getCopyMapping(unsigned DstBankID, unsigned SrcBankID, unsigned Size)
Get the pointer to the ValueMapping of the operands of a copy instruction from the SrcBankID register...
Helper class that represents how the value of an instruction may be mapped and what is the related co...
static bool checkPartialMappingIdx(PartialMappingIdx FirstAlias, PartialMappingIdx LastAlias, ArrayRef< PartialMappingIdx > Order)
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
unsigned const TargetRegisterInfo * TRI
Holds all the information related to register banks.
static RegisterBankInfo::ValueMapping ValMappings[]
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
static const RegisterBankInfo::ValueMapping * getFPExtMapping(unsigned DstSize, unsigned SrcSize)
Get the instruction mapping for G_FPEXT.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
virtual const InstructionMapping & getInstrMapping(const MachineInstr &MI) const
Get the mapping of the different operands of MI on the register bank.
static bool checkPartialMap(unsigned Idx, unsigned ValStartIdx, unsigned ValLength, const RegisterBank &RB)
Helper struct that represents how a value is partially mapped into a register.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
static unsigned getRegBankBaseIdxOffset(unsigned RBIdx, unsigned Size)
This class implements the register bank concept.
Definition: RegisterBank.h:28
Helper struct that represents how a value is mapped through different register banks.
static const RegisterBankInfo::ValueMapping * getValueMapping(PartialMappingIdx RBIdx, unsigned Size)
Get the pointer to the ValueMapping representing the RegisterBank at RBIdx with a size of Size...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:63
This class provides the information for the target register banks.
virtual void applyMappingImpl(const OperandsMapper &OpdMapper) const
See applyMapping.
virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const
Get the alternative mappings for MI.
virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
uint32_t Size
Definition: Profile.cpp:46
static bool checkValueMapImpl(unsigned Idx, unsigned FirstInBank, unsigned Size, unsigned Offset)
static PartialMappingIdx BankIDToCopyMapIdx[]
IRTranslator LLVM IR MI
static RegisterBankInfo::PartialMapping PartMappings[]
virtual const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC) const
Get a register bank that covers RC.