LLVM  9.0.0svn
Utils.h
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1 //==-- llvm/CodeGen/GlobalISel/Utils.h ---------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file declares the API of helper functions used throughout the
10 /// GlobalISel pipeline.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_GLOBALISEL_UTILS_H
15 #define LLVM_CODEGEN_GLOBALISEL_UTILS_H
16 
17 #include "llvm/ADT/StringRef.h"
18 
19 namespace llvm {
20 
21 class AnalysisUsage;
22 class MachineFunction;
23 class MachineInstr;
24 class MachineOperand;
25 class MachineOptimizationRemarkEmitter;
26 class MachineOptimizationRemarkMissed;
27 class MachineRegisterInfo;
28 class MCInstrDesc;
29 class RegisterBankInfo;
30 class TargetInstrInfo;
31 class TargetPassConfig;
32 class TargetRegisterInfo;
33 class TargetRegisterClass;
34 class Twine;
35 class ConstantFP;
36 class APFloat;
37 
38 /// Try to constrain Reg to the specified register class. If this fails,
39 /// create a new virtual register in the correct class.
40 ///
41 /// \return The virtual register constrained to the right register class.
42 unsigned constrainRegToClass(MachineRegisterInfo &MRI,
43  const TargetInstrInfo &TII,
44  const RegisterBankInfo &RBI, unsigned Reg,
45  const TargetRegisterClass &RegClass);
46 
47 /// Constrain the Register operand OpIdx, so that it is now constrained to the
48 /// TargetRegisterClass passed as an argument (RegClass).
49 /// If this fails, create a new virtual register in the correct class and
50 /// insert a COPY before \p InsertPt if it is a use or after if it is a
51 /// definition. The debug location of \p InsertPt is used for the new copy.
52 ///
53 /// \return The virtual register constrained to the right register class.
54 unsigned constrainOperandRegClass(const MachineFunction &MF,
55  const TargetRegisterInfo &TRI,
56  MachineRegisterInfo &MRI,
57  const TargetInstrInfo &TII,
58  const RegisterBankInfo &RBI,
59  MachineInstr &InsertPt,
60  const TargetRegisterClass &RegClass,
61  const MachineOperand &RegMO, unsigned OpIdx);
62 
63 /// Try to constrain Reg so that it is usable by argument OpIdx of the
64 /// provided MCInstrDesc \p II. If this fails, create a new virtual
65 /// register in the correct class and insert a COPY before \p InsertPt
66 /// if it is a use or after if it is a definition.
67 /// This is equivalent to constrainOperandRegClass(..., RegClass, ...)
68 /// with RegClass obtained from the MCInstrDesc. The debug location of \p
69 /// InsertPt is used for the new copy.
70 ///
71 /// \return The virtual register constrained to the right register class.
72 unsigned constrainOperandRegClass(const MachineFunction &MF,
73  const TargetRegisterInfo &TRI,
74  MachineRegisterInfo &MRI,
75  const TargetInstrInfo &TII,
76  const RegisterBankInfo &RBI,
77  MachineInstr &InsertPt, const MCInstrDesc &II,
78  const MachineOperand &RegMO, unsigned OpIdx);
79 
80 /// Mutate the newly-selected instruction \p I to constrain its (possibly
81 /// generic) virtual register operands to the instruction's register class.
82 /// This could involve inserting COPYs before (for uses) or after (for defs).
83 /// This requires the number of operands to match the instruction description.
84 /// \returns whether operand regclass constraining succeeded.
85 ///
86 // FIXME: Not all instructions have the same number of operands. We should
87 // probably expose a constrain helper per operand and let the target selector
88 // constrain individual registers, like fast-isel.
89 bool constrainSelectedInstRegOperands(MachineInstr &I,
90  const TargetInstrInfo &TII,
91  const TargetRegisterInfo &TRI,
92  const RegisterBankInfo &RBI);
93 /// Check whether an instruction \p MI is dead: it only defines dead virtual
94 /// registers, and doesn't have other side effects.
95 bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI);
96 
97 /// Report an ISel error as a missed optimization remark to the LLVMContext's
98 /// diagnostic stream. Set the FailedISel MachineFunction property.
99 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
100  MachineOptimizationRemarkEmitter &MORE,
101  MachineOptimizationRemarkMissed &R);
102 
103 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
104  MachineOptimizationRemarkEmitter &MORE,
105  const char *PassName, StringRef Msg,
106  const MachineInstr &MI);
107 
108 /// If \p VReg is defined by a G_CONSTANT fits in int64_t
109 /// returns it.
110 Optional<int64_t> getConstantVRegVal(unsigned VReg,
111  const MachineRegisterInfo &MRI);
112 /// Simple struct used to hold a constant integer value and a virtual
113 /// register.
114 struct ValueAndVReg {
115  int64_t Value;
116  unsigned VReg;
117 };
118 /// If \p VReg is defined by a statically evaluable chain of
119 /// instructions rooted on a G_CONSTANT (\p LookThroughInstrs == true)
120 /// and that constant fits in int64_t, returns its value as well as
121 /// the virtual register defined by this G_CONSTANT.
122 /// When \p LookThroughInstrs == false, this function behaves like
123 /// getConstantVRegVal.
126  bool LookThroughInstrs = true);
127 const ConstantFP* getConstantFPVRegVal(unsigned VReg,
128  const MachineRegisterInfo &MRI);
129 
130 /// See if Reg is defined by an single def instruction that is
131 /// Opcode. Also try to do trivial folding if it's a COPY with
132 /// same types. Returns null otherwise.
133 MachineInstr *getOpcodeDef(unsigned Opcode, unsigned Reg,
134  const MachineRegisterInfo &MRI);
135 
136 /// Returns an APFloat from Val converted to the appropriate size.
137 APFloat getAPFloatFromSize(double Val, unsigned Size);
138 
139 /// Modify analysis usage so it preserves passes required for the SelectionDAG
140 /// fallback.
142 
143 Optional<APInt> ConstantFoldBinOp(unsigned Opcode, const unsigned Op1,
144  const unsigned Op2,
145  const MachineRegisterInfo &MRI);
146 } // End namespace llvm.
147 #endif
Simple struct used to hold a constant integer value and a virtual register.
Definition: Utils.h:114
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, const MachineOperand &RegMO, unsigned OpIdx)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:40
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition: Utils.cpp:364
const ConstantFP * getConstantFPVRegVal(unsigned VReg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:276
unsigned Reg
unsigned const TargetRegisterInfo * TRI
int64_t Value
Definition: Utils.h:115
const HexagonInstrInfo * TII
Optional< APInt > ConstantFoldBinOp(unsigned Opcode, const unsigned Op1, const unsigned Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:313
unsigned constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, unsigned Reg, const TargetRegisterClass &RegClass)
Try to constrain Reg to the specified register class.
Definition: Utils.cpp:30
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
Definition: Utils.cpp:300
MachineInstr * getOpcodeDef(unsigned Opcode, unsigned Reg, const MachineRegisterInfo &MRI)
See if Reg is defined by an single def instruction that is Opcode.
Definition: Utils.cpp:284
unsigned const MachineRegisterInfo * MRI
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
Represent the analysis usage information of a pass.
unsigned VReg
Definition: Utils.h:116
Optional< ValueAndVReg > getConstantVRegValWithLookThrough(unsigned VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT (LookThroug...
Definition: Utils.cpp:221
#define MORE()
Definition: regcomp.c:251
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:113
RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks)
Create a RegisterBankInfo that can accommodate up to NumRegBanks RegisterBank instances.
Optional< int64_t > getConstantVRegVal(unsigned VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT fits in int64_t returns it.
Definition: Utils.cpp:210
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn&#39;t have oth...
Definition: Utils.cpp:160
Representation of each machine instruction.
Definition: MachineInstr.h:63
#define I(x, y, z)
Definition: MD5.cpp:58
uint32_t Size
Definition: Profile.cpp:46
IRTranslator LLVM IR MI
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext&#39;s diagnostic stream...
Definition: Utils.cpp:181