LLVM  9.0.0svn
Utils.h
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1 //==-- llvm/CodeGen/GlobalISel/Utils.h ---------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file declares the API of helper functions used throughout the
10 /// GlobalISel pipeline.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_GLOBALISEL_UTILS_H
15 #define LLVM_CODEGEN_GLOBALISEL_UTILS_H
16 
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/CodeGen/Register.h"
19 
20 namespace llvm {
21 
22 class AnalysisUsage;
23 class MachineFunction;
24 class MachineInstr;
25 class MachineOperand;
26 class MachineOptimizationRemarkEmitter;
27 class MachineOptimizationRemarkMissed;
28 class MachineRegisterInfo;
29 class MCInstrDesc;
30 class RegisterBankInfo;
31 class TargetInstrInfo;
32 class TargetPassConfig;
33 class TargetRegisterInfo;
34 class TargetRegisterClass;
35 class Twine;
36 class ConstantFP;
37 class APFloat;
38 
39 /// Try to constrain Reg to the specified register class. If this fails,
40 /// create a new virtual register in the correct class.
41 ///
42 /// \return The virtual register constrained to the right register class.
43 unsigned constrainRegToClass(MachineRegisterInfo &MRI,
44  const TargetInstrInfo &TII,
45  const RegisterBankInfo &RBI, unsigned Reg,
46  const TargetRegisterClass &RegClass);
47 
48 /// Constrain the Register operand OpIdx, so that it is now constrained to the
49 /// TargetRegisterClass passed as an argument (RegClass).
50 /// If this fails, create a new virtual register in the correct class and
51 /// insert a COPY before \p InsertPt if it is a use or after if it is a
52 /// definition. The debug location of \p InsertPt is used for the new copy.
53 ///
54 /// \return The virtual register constrained to the right register class.
55 unsigned constrainOperandRegClass(const MachineFunction &MF,
56  const TargetRegisterInfo &TRI,
57  MachineRegisterInfo &MRI,
58  const TargetInstrInfo &TII,
59  const RegisterBankInfo &RBI,
60  MachineInstr &InsertPt,
61  const TargetRegisterClass &RegClass,
62  const MachineOperand &RegMO, unsigned OpIdx);
63 
64 /// Try to constrain Reg so that it is usable by argument OpIdx of the
65 /// provided MCInstrDesc \p II. If this fails, create a new virtual
66 /// register in the correct class and insert a COPY before \p InsertPt
67 /// if it is a use or after if it is a definition.
68 /// This is equivalent to constrainOperandRegClass(..., RegClass, ...)
69 /// with RegClass obtained from the MCInstrDesc. The debug location of \p
70 /// InsertPt is used for the new copy.
71 ///
72 /// \return The virtual register constrained to the right register class.
73 unsigned constrainOperandRegClass(const MachineFunction &MF,
74  const TargetRegisterInfo &TRI,
75  MachineRegisterInfo &MRI,
76  const TargetInstrInfo &TII,
77  const RegisterBankInfo &RBI,
78  MachineInstr &InsertPt, const MCInstrDesc &II,
79  const MachineOperand &RegMO, unsigned OpIdx);
80 
81 /// Mutate the newly-selected instruction \p I to constrain its (possibly
82 /// generic) virtual register operands to the instruction's register class.
83 /// This could involve inserting COPYs before (for uses) or after (for defs).
84 /// This requires the number of operands to match the instruction description.
85 /// \returns whether operand regclass constraining succeeded.
86 ///
87 // FIXME: Not all instructions have the same number of operands. We should
88 // probably expose a constrain helper per operand and let the target selector
89 // constrain individual registers, like fast-isel.
90 bool constrainSelectedInstRegOperands(MachineInstr &I,
91  const TargetInstrInfo &TII,
92  const TargetRegisterInfo &TRI,
93  const RegisterBankInfo &RBI);
94 /// Check whether an instruction \p MI is dead: it only defines dead virtual
95 /// registers, and doesn't have other side effects.
96 bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI);
97 
98 /// Report an ISel error as a missed optimization remark to the LLVMContext's
99 /// diagnostic stream. Set the FailedISel MachineFunction property.
100 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
101  MachineOptimizationRemarkEmitter &MORE,
102  MachineOptimizationRemarkMissed &R);
103 
104 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
105  MachineOptimizationRemarkEmitter &MORE,
106  const char *PassName, StringRef Msg,
107  const MachineInstr &MI);
108 
109 /// If \p VReg is defined by a G_CONSTANT fits in int64_t
110 /// returns it.
111 Optional<int64_t> getConstantVRegVal(unsigned VReg,
112  const MachineRegisterInfo &MRI);
113 /// Simple struct used to hold a constant integer value and a virtual
114 /// register.
115 struct ValueAndVReg {
116  int64_t Value;
117  unsigned VReg;
118 };
119 /// If \p VReg is defined by a statically evaluable chain of
120 /// instructions rooted on a G_CONSTANT (\p LookThroughInstrs == true)
121 /// and that constant fits in int64_t, returns its value as well as
122 /// the virtual register defined by this G_CONSTANT.
123 /// When \p LookThroughInstrs == false, this function behaves like
124 /// getConstantVRegVal.
127  bool LookThroughInstrs = true);
128 const ConstantFP* getConstantFPVRegVal(unsigned VReg,
129  const MachineRegisterInfo &MRI);
130 
131 /// See if Reg is defined by an single def instruction that is
132 /// Opcode. Also try to do trivial folding if it's a COPY with
133 /// same types. Returns null otherwise.
134 MachineInstr *getOpcodeDef(unsigned Opcode, Register Reg,
135  const MachineRegisterInfo &MRI);
136 
137 /// Find the def instruction for \p Reg, folding away any trivial copies. Note
138 /// it may still return a COPY, if it changes the type. May return nullptr if \p
139 /// Reg is not a generic virtual register.
141  const MachineRegisterInfo &MRI);
142 
143 /// Returns an APFloat from Val converted to the appropriate size.
144 APFloat getAPFloatFromSize(double Val, unsigned Size);
145 
146 /// Modify analysis usage so it preserves passes required for the SelectionDAG
147 /// fallback.
149 
150 Optional<APInt> ConstantFoldBinOp(unsigned Opcode, const unsigned Op1,
151  const unsigned Op2,
152  const MachineRegisterInfo &MRI);
153 
154 /// Returns true if \p Val can be assumed to never be a NaN. If \p SNaN is true,
155 /// this returns if \p Val can be assumed to never be a signaling NaN.
157  bool SNaN = false);
158 
159 /// Returns true if \p Val can be assumed to never be a signaling NaN.
161  return isKnownNeverNaN(Val, MRI, true);
162 }
163 
164 } // End namespace llvm.
165 #endif
Simple struct used to hold a constant integer value and a virtual register.
Definition: Utils.h:115
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, const MachineOperand &RegMO, unsigned OpIdx)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:40
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition: Utils.cpp:398
const ConstantFP * getConstantFPVRegVal(unsigned VReg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:279
unsigned Reg
unsigned const TargetRegisterInfo * TRI
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Definition: Utils.cpp:287
bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI)
Returns true if Val can be assumed to never be a signaling NaN.
Definition: Utils.h:160
int64_t Value
Definition: Utils.h:116
const HexagonInstrInfo * TII
Optional< APInt > ConstantFoldBinOp(unsigned Opcode, const unsigned Op1, const unsigned Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:322
unsigned constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, unsigned Reg, const TargetRegisterClass &RegClass)
Try to constrain Reg to the specified register class.
Definition: Utils.cpp:30
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
Definition: Utils.cpp:309
unsigned const MachineRegisterInfo * MRI
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
Represent the analysis usage information of a pass.
unsigned VReg
Definition: Utils.h:117
MachineInstr * getOpcodeDef(unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI)
See if Reg is defined by an single def instruction that is Opcode.
Definition: Utils.cpp:303
Optional< ValueAndVReg > getConstantVRegValWithLookThrough(unsigned VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT (LookThroug...
Definition: Utils.cpp:221
#define MORE()
Definition: regcomp.c:251
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:113
RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks)
Create a RegisterBankInfo that can accommodate up to NumRegBanks RegisterBank instances.
Optional< int64_t > getConstantVRegVal(unsigned VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT fits in int64_t returns it.
Definition: Utils.cpp:210
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn&#39;t have oth...
Definition: Utils.cpp:160
Representation of each machine instruction.
Definition: MachineInstr.h:64
#define I(x, y, z)
Definition: MD5.cpp:58
uint32_t Size
Definition: Profile.cpp:46
bool isKnownNeverNaN(const Value *V, const TargetLibraryInfo *TLI, unsigned Depth=0)
Return true if the floating-point scalar value is not a NaN or if the floating-point vector value has...
IRTranslator LLVM IR MI
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext&#39;s diagnostic stream...
Definition: Utils.cpp:181
Wrapper class representing virtual and physical registers.
Definition: Register.h:18