LLVM  6.0.0svn
Todo List
File AArch64InstructionSelector.cpp
This should be generated by TableGen.
File AArch64LegalizerInfo.cpp
This should be generated by TableGen.
File AArch64LegalizerInfo.h
This should be generated by TableGen.
File AArch64RegisterBankInfo.cpp
This should be generated by TableGen.
File AArch64RegisterBankInfo.h
This should be generated by TableGen.
Member amd_kernel_code_t

[Does CP need to round this to >4 byte alignment?]

[Does CP need to round this to >4 byte alignment?]

[This will not be used for CI/VI since it is the same value as the second SGPR of Flat Scratch Init. However, it is need for PI which changes meaning of Flat Scratchg Init..]

[Does CP need to round this to >4 byte alignment?]

[This will not be used for CI/VI since it is the same value as the second SGPR of Flat Scratch Init. However, it is need for PI which changes meaning of Flat Scratchg Init..]

Member amd_kernel_code_t

[Does CP need to round this to >4 byte alignment?]

[Does CP need to round this to >4 byte alignment?]

[This will not be used for CI/VI since it is the same value as the second SGPR of Flat Scratch Init. However, it is need for PI which changes meaning of Flat Scratchg Init..]

[Does CP need to round this to >4 byte alignment?]

[This will not be used for CI/VI since it is the same value as the second SGPR of Flat Scratch Init. However, it is need for PI which changes meaning of Flat Scratchg Init..]

File AMDGPUInstructionSelector.cpp
This should be generated by TableGen.
File AMDGPULegalizerInfo.cpp
This should be generated by TableGen.
File AMDGPULegalizerInfo.h
This should be generated by TableGen.
File AMDGPURegisterBankInfo.cpp
This should be generated by TableGen.
File AMDGPURegisterBankInfo.h
This should be generated by TableGen.
File ARMInstructionSelector.cpp
This should be generated by TableGen.
File ARMLegalizerInfo.cpp
This should be generated by TableGen.
File ARMLegalizerInfo.h
This should be generated by TableGen.
File ARMRegisterBankInfo.cpp
This should be generated by TableGen.
File ARMRegisterBankInfo.h
This should be generated by TableGen.
Member getRegBankFromRegClass (const TargetRegisterClass &RC) const
This should be TableGen'ed.
Member InstructionMappings
When we move to TableGen this should be an array ref.
File IRTranslator.h
Class llvm::AlignTo< Align >
FIXME: remove when constexpr becomes really constexpr
Member llvm::RegisterBankInfo::getRegBankFromRegClass (const TargetRegisterClass &RC) const
This should be TableGen'ed.
Member llvm::RegisterBankInfo::InstructionMappings
When we move to TableGen this should be an array ref.
Member shouldConvertImpl (const Constant *Cst)
Currently, accept only vector related types. Also we give up on all simple vector type to keep the existing behavior. Otherwise, we should push here all the check of the lowering of BUILD_VECTOR. By giving up, we lose the potential benefit of merging constant via global merge and the fact that the same constant is stored only once with this method (versus, as many function that uses the constant for the regular approach, even for float). Again, the simplest solution would be to promote every constant and rematerialize them when they are actually cheap to create.
File X86InstructionSelector.cpp
This should be generated by TableGen.
File X86LegalizerInfo.cpp
This should be generated by TableGen.
File X86LegalizerInfo.h
This should be generated by TableGen.
File X86RegisterBankInfo.cpp
This should be generated by TableGen.
File X86RegisterBankInfo.h
This should be generated by TableGen.