LLVM  8.0.0svn
Macros | Enumerations | Functions | Variables
X86InstrInfo.cpp File Reference
#include "X86InstrInfo.h"
#include "X86.h"
#include "X86InstrBuilder.h"
#include "X86InstrFoldTables.h"
#include "X86MachineFunctionInfo.h"
#include "X86Subtarget.h"
#include "X86TargetMachine.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/Sequence.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/StackMaps.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetOptions.h"
#include "X86GenInstrInfo.inc"
Include dependency graph for X86InstrInfo.cpp:

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "x86-instr-info"
 
#define GET_INSTRINFO_CTOR_DTOR
 
#define VPERM_CASES(Suffix)
 
#define VPERM_CASES_BROADCAST(Suffix)
 
#define VPERM_CASES(Orig, New)
 
#define VPERM_CASES_BROADCAST(Orig, New)
 

Enumerations

enum  MachineOutlinerClass {
  MachineOutlinerDefault, MachineOutlinerTailCall, MachineOutlinerNoLRSave, MachineOutlinerThunk,
  MachineOutlinerRegSave, MachineOutlinerDefault, MachineOutlinerTailCall
}
 Constants defining how certain sequences should be outlined. More...
 

Functions

static bool isFrameLoadOpcode (int Opcode, unsigned &MemBytes)
 
static bool isFrameStoreOpcode (int Opcode, unsigned &MemBytes)
 
static bool regIsPICBase (unsigned BaseReg, const MachineRegisterInfo &MRI)
 Return true if register is PIC base; i.e.g defined by X86::MOVPC32r. More...
 
static unsigned getTruncatedShiftCount (MachineInstr &MI, unsigned ShiftAmtOperandIdx)
 Check whether the shift count for a machine operand is non-zero. More...
 
static bool isTruncatedShiftCountForLEA (unsigned ShAmt)
 Check whether the given shift count is appropriate can be represented by a LEA instruction. More...
 
static unsigned getThreeSrcCommuteCase (uint64_t TSFlags, unsigned SrcOpIdx1, unsigned SrcOpIdx2)
 This determines which of three possible cases of a three source commute the source indexes correspond to taking into account any mask operands. More...
 
static void commuteVPTERNLOG (MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2)
 
static bool isCommutableVPERMV3Instruction (unsigned Opcode)
 
static unsigned getCommutedVPERMV3Opcode (unsigned Opcode)
 
static X86::CondCode getSwappedCondition (X86::CondCode CC)
 Assuming the flags are set by MI(a,b), return the condition code if we modify the instructions such that flags are set by MI(b,a). More...
 
static MachineBasicBlockgetFallThroughMBB (MachineBasicBlock *MBB, MachineBasicBlock *TBB)
 
static bool isHReg (unsigned Reg)
 Test if the given register is a physical h register. More...
 
static unsigned CopyToFromAsymmetricReg (unsigned DestReg, unsigned SrcReg, const X86Subtarget &Subtarget)
 
static unsigned getLoadStoreRegOpcode (unsigned Reg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI, bool load)
 
static unsigned getStoreRegOpcode (unsigned SrcReg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI)
 
static unsigned getLoadRegOpcode (unsigned DestReg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI)
 
static bool isRedundantFlagInstr (MachineInstr &FlagI, unsigned SrcReg, unsigned SrcReg2, int ImmMask, int ImmValue, MachineInstr &OI)
 Check whether the first instruction, whose only purpose is to update flags, can be made redundant. More...
 
static bool isDefConvertible (MachineInstr &MI)
 Check whether the definition can be converted to remove a comparison against zero. More...
 
static X86::CondCode isUseDefConvertible (MachineInstr &MI)
 Check whether the use can be converted to remove a comparison against zero. More...
 
static bool Expand2AddrUndef (MachineInstrBuilder &MIB, const MCInstrDesc &Desc)
 Expand a single-def pseudo instruction to a two-addr instruction with two undef reads of the register being defined. More...
 
static bool Expand2AddrKreg (MachineInstrBuilder &MIB, const MCInstrDesc &Desc, unsigned Reg)
 Expand a single-def pseudo instruction to a two-addr instruction with two k0 reads. More...
 
static bool expandMOV32r1 (MachineInstrBuilder &MIB, const TargetInstrInfo &TII, bool MinusOne)
 
static bool ExpandMOVImmSExti8 (MachineInstrBuilder &MIB, const TargetInstrInfo &TII, const X86Subtarget &Subtarget)
 
static void expandLoadStackGuard (MachineInstrBuilder &MIB, const TargetInstrInfo &TII)
 
static bool expandXorFP (MachineInstrBuilder &MIB, const TargetInstrInfo &TII)
 
static bool expandNOVLXLoad (MachineInstrBuilder &MIB, const TargetRegisterInfo *TRI, const MCInstrDesc &LoadDesc, const MCInstrDesc &BroadcastDesc, unsigned SubIdx)
 
static bool expandNOVLXStore (MachineInstrBuilder &MIB, const TargetRegisterInfo *TRI, const MCInstrDesc &StoreDesc, const MCInstrDesc &ExtractDesc, unsigned SubIdx)
 
static bool hasPartialRegUpdate (unsigned Opcode, const X86Subtarget &Subtarget)
 Return true for all instructions that only update the first 32 or 64-bits of the destination register and leave the rest unmodified. More...
 
static bool hasUndefRegUpdate (unsigned Opcode)
 
static void addOperands (MachineInstrBuilder &MIB, ArrayRef< MachineOperand > MOs, int PtrOffset=0)
 
static void updateOperandRegConstraints (MachineFunction &MF, MachineInstr &NewMI, const TargetInstrInfo &TII)
 
static MachineInstrFuseTwoAddrInst (MachineFunction &MF, unsigned Opcode, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, MachineInstr &MI, const TargetInstrInfo &TII)
 
static MachineInstrFuseInst (MachineFunction &MF, unsigned Opcode, unsigned OpNo, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, MachineInstr &MI, const TargetInstrInfo &TII, int PtrOffset=0)
 
static MachineInstrMakeM0Inst (const TargetInstrInfo &TII, unsigned Opcode, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, MachineInstr &MI)
 
static bool shouldPreventUndefRegUpdateMemFold (MachineFunction &MF, MachineInstr &MI)
 
static bool isNonFoldablePartialRegisterLoad (const MachineInstr &LoadMI, const MachineInstr &UserMI, const MachineFunction &MF)
 Check if LoadMI is a partial register load that we can't fold into MI because the latter uses contents that wouldn't be defined in the folded version. More...
 
static SmallVector< MachineMemOperand *, 2 > extractLoadMMOs (ArrayRef< MachineMemOperand *> MMOs, MachineFunction &MF)
 
static SmallVector< MachineMemOperand *, 2 > extractStoreMMOs (ArrayRef< MachineMemOperand *> MMOs, MachineFunction &MF)
 
static const uint16_t * lookup (unsigned opcode, unsigned domain, ArrayRef< uint16_t[3]> Table)
 
static const uint16_t * lookupAVX512 (unsigned opcode, unsigned domain, ArrayRef< uint16_t[4]> Table)
 
static bool AdjustBlendMask (unsigned OldMask, unsigned OldWidth, unsigned NewWidth, unsigned *pNewMask=nullptr)
 

Variables

static cl::opt< boolNoFusing ("disable-spill-fusing", cl::desc("Disable fusing of spill code into instructions"), cl::Hidden)
 
static cl::opt< boolPrintFailedFusing ("print-failed-fuse-candidates", cl::desc("Print instructions that the allocator wants to" " fuse, but the X86 backend currently can't"), cl::Hidden)
 
static cl::opt< boolReMatPICStubLoad ("remat-pic-stub-load", cl::desc("Re-materialize load from stub in PIC mode"), cl::init(false), cl::Hidden)
 
static cl::opt< unsignedPartialRegUpdateClearance ("partial-reg-update-clearance", cl::desc("Clearance between two register writes " "for inserting XOR to avoid partial " "register update"), cl::init(64), cl::Hidden)
 
static cl::opt< unsignedUndefRegClearance ("undef-reg-clearance", cl::desc("How many idle instructions we would like before " "certain undef register reads"), cl::init(128), cl::Hidden)
 
static const uint16_t ReplaceableInstrs [][3]
 
static const uint16_t ReplaceableInstrsAVX2 [][3]
 
static const uint16_t ReplaceableInstrsAVX2InsertExtract [][3]
 
static const uint16_t ReplaceableInstrsAVX512 [][4]
 
static const uint16_t ReplaceableInstrsAVX512DQ [][4]
 
static const uint16_t ReplaceableInstrsAVX512DQMasked [][4]
 
static const uint16_t ReplaceableCustomInstrs [][3]
 
static const uint16_t ReplaceableCustomAVX2Instrs [][3]
 
static const uint16_t ReplaceableCustomAVX512LogicInstrs [][4]
 

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "x86-instr-info"

Definition at line 46 of file X86InstrInfo.cpp.

◆ GET_INSTRINFO_CTOR_DTOR

#define GET_INSTRINFO_CTOR_DTOR

Definition at line 48 of file X86InstrInfo.cpp.

◆ VPERM_CASES [1/2]

#define VPERM_CASES (   Suffix)
Value:
case X86::VPERMI2##Suffix##128rr: case X86::VPERMT2##Suffix##128rr: \
case X86::VPERMI2##Suffix##256rr: case X86::VPERMT2##Suffix##256rr: \
case X86::VPERMI2##Suffix##rr: case X86::VPERMT2##Suffix##rr: \
case X86::VPERMI2##Suffix##128rm: case X86::VPERMT2##Suffix##128rm: \
case X86::VPERMI2##Suffix##256rm: case X86::VPERMT2##Suffix##256rm: \
case X86::VPERMI2##Suffix##rm: case X86::VPERMT2##Suffix##rm: \
case X86::VPERMI2##Suffix##128rrkz: case X86::VPERMT2##Suffix##128rrkz: \
case X86::VPERMI2##Suffix##256rrkz: case X86::VPERMT2##Suffix##256rrkz: \
case X86::VPERMI2##Suffix##rrkz: case X86::VPERMT2##Suffix##rrkz: \
case X86::VPERMI2##Suffix##128rmkz: case X86::VPERMT2##Suffix##128rmkz: \
case X86::VPERMI2##Suffix##256rmkz: case X86::VPERMT2##Suffix##256rmkz: \
case X86::VPERMI2##Suffix##rmkz: case X86::VPERMT2##Suffix##rmkz:

Referenced by getCommutedVPERMV3Opcode(), and isCommutableVPERMV3Instruction().

◆ VPERM_CASES [2/2]

#define VPERM_CASES (   Orig,
  New 
)
Value:
case X86::Orig##128rr: return X86::New##128rr; \
case X86::Orig##128rrkz: return X86::New##128rrkz; \
case X86::Orig##128rm: return X86::New##128rm; \
case X86::Orig##128rmkz: return X86::New##128rmkz; \
case X86::Orig##256rr: return X86::New##256rr; \
case X86::Orig##256rrkz: return X86::New##256rrkz; \
case X86::Orig##256rm: return X86::New##256rm; \
case X86::Orig##256rmkz: return X86::New##256rmkz; \
case X86::Orig##rr: return X86::New##rr; \
case X86::Orig##rrkz: return X86::New##rrkz; \
case X86::Orig##rm: return X86::New##rm; \
case X86::Orig##rmkz: return X86::New##rmkz;

◆ VPERM_CASES_BROADCAST [1/2]

#define VPERM_CASES_BROADCAST (   Suffix)
Value:
VPERM_CASES(Suffix) \
case X86::VPERMI2##Suffix##128rmb: case X86::VPERMT2##Suffix##128rmb: \
case X86::VPERMI2##Suffix##256rmb: case X86::VPERMT2##Suffix##256rmb: \
case X86::VPERMI2##Suffix##rmb: case X86::VPERMT2##Suffix##rmb: \
case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \
case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \
case X86::VPERMI2##Suffix##rmbkz: case X86::VPERMT2##Suffix##rmbkz:
#define VPERM_CASES(Suffix)

Referenced by getCommutedVPERMV3Opcode(), and isCommutableVPERMV3Instruction().

◆ VPERM_CASES_BROADCAST [2/2]

#define VPERM_CASES_BROADCAST (   Orig,
  New 
)
Value:
VPERM_CASES(Orig, New) \
case X86::Orig##128rmb: return X86::New##128rmb; \
case X86::Orig##128rmbkz: return X86::New##128rmbkz; \
case X86::Orig##256rmb: return X86::New##256rmb; \
case X86::Orig##256rmbkz: return X86::New##256rmbkz; \
case X86::Orig##rmb: return X86::New##rmb; \
case X86::Orig##rmbkz: return X86::New##rmbkz;
#define VPERM_CASES(Suffix)

Enumeration Type Documentation

◆ MachineOutlinerClass

Constants defining how certain sequences should be outlined.

MachineOutlinerDefault implies that the function is called with a call instruction, and a return must be emitted for the outlined function frame.

That is,

I1 OUTLINED_FUNCTION: I2 –> call OUTLINED_FUNCTION I1 I3 I2 I3 ret

  • Call construction overhead: 1 (call instruction)
  • Frame construction overhead: 1 (return instruction)

MachineOutlinerTailCall implies that the function is being tail called. A jump is emitted instead of a call, and the return is already present in the outlined sequence. That is,

I1 OUTLINED_FUNCTION: I2 –> jmp OUTLINED_FUNCTION I1 ret I2 ret

  • Call construction overhead: 1 (jump instruction)
  • Frame construction overhead: 0 (don't need to return)
Enumerator
MachineOutlinerDefault 
MachineOutlinerTailCall 

Emit a save, restore, call, and return.

MachineOutlinerNoLRSave 

Only emit a branch.

MachineOutlinerThunk 

Emit a call and return.

MachineOutlinerRegSave 

Emit a call and tail-call.

Same as default, but save to a register.

MachineOutlinerDefault 
MachineOutlinerTailCall 

Definition at line 7663 of file X86InstrInfo.cpp.

Function Documentation

◆ addOperands()

static void addOperands ( MachineInstrBuilder MIB,
ArrayRef< MachineOperand MOs,
int  PtrOffset = 0 
)
static

◆ AdjustBlendMask()

static bool AdjustBlendMask ( unsigned  OldMask,
unsigned  OldWidth,
unsigned  NewWidth,
unsigned pNewMask = nullptr 
)
static

◆ commuteVPTERNLOG()

static void commuteVPTERNLOG ( MachineInstr MI,
unsigned  SrcOpIdx1,
unsigned  SrcOpIdx2 
)
static

◆ CopyToFromAsymmetricReg()

static unsigned CopyToFromAsymmetricReg ( unsigned  DestReg,
unsigned  SrcReg,
const X86Subtarget Subtarget 
)
static

◆ Expand2AddrKreg()

static bool Expand2AddrKreg ( MachineInstrBuilder MIB,
const MCInstrDesc Desc,
unsigned  Reg 
)
static

Expand a single-def pseudo instruction to a two-addr instruction with two k0 reads.

This is used for mapping: k4 = K_SET1 to: k4 = KXNORrr k0, k0

Definition at line 3987 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), assert(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::setDesc(), and llvm::RegState::Undef.

Referenced by llvm::X86InstrInfo::expandPostRAPseudo().

◆ Expand2AddrUndef()

static bool Expand2AddrUndef ( MachineInstrBuilder MIB,
const MCInstrDesc Desc 
)
static

Expand a single-def pseudo instruction to a two-addr instruction with two undef reads of the register being defined.

This is used for mapping: xmm4 = V_SET0 to: xmm4 = PXORrr undef xmm4, undef xmm4

Definition at line 3966 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), assert(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), Reg, llvm::MachineInstr::setDesc(), and llvm::RegState::Undef.

Referenced by llvm::X86InstrInfo::expandPostRAPseudo().

◆ expandLoadStackGuard()

static void expandLoadStackGuard ( MachineInstrBuilder MIB,
const TargetInstrInfo TII 
)
static

◆ expandMOV32r1()

static bool expandMOV32r1 ( MachineInstrBuilder MIB,
const TargetInstrInfo TII,
bool  MinusOne 
)
static

◆ ExpandMOVImmSExti8()

static bool ExpandMOVImmSExti8 ( MachineInstrBuilder MIB,
const TargetInstrInfo TII,
const X86Subtarget Subtarget 
)
static

◆ expandNOVLXLoad()

static bool expandNOVLXLoad ( MachineInstrBuilder MIB,
const TargetRegisterInfo TRI,
const MCInstrDesc LoadDesc,
const MCInstrDesc BroadcastDesc,
unsigned  SubIdx 
)
static

◆ expandNOVLXStore()

static bool expandNOVLXStore ( MachineInstrBuilder MIB,
const TargetRegisterInfo TRI,
const MCInstrDesc StoreDesc,
const MCInstrDesc ExtractDesc,
unsigned  SubIdx 
)
static

◆ expandXorFP()

static bool expandXorFP ( MachineInstrBuilder MIB,
const TargetInstrInfo TII 
)
static

◆ extractLoadMMOs()

static SmallVector<MachineMemOperand *, 2> extractLoadMMOs ( ArrayRef< MachineMemOperand *>  MMOs,
MachineFunction MF 
)
static

◆ extractStoreMMOs()

static SmallVector<MachineMemOperand *, 2> extractStoreMMOs ( ArrayRef< MachineMemOperand *>  MMOs,
MachineFunction MF 
)
static

◆ FuseInst()

static MachineInstr* FuseInst ( MachineFunction MF,
unsigned  Opcode,
unsigned  OpNo,
ArrayRef< MachineOperand MOs,
MachineBasicBlock::iterator  InsertPt,
MachineInstr MI,
const TargetInstrInfo TII,
int  PtrOffset = 0 
)
static

◆ FuseTwoAddrInst()

static MachineInstr* FuseTwoAddrInst ( MachineFunction MF,
unsigned  Opcode,
ArrayRef< MachineOperand MOs,
MachineBasicBlock::iterator  InsertPt,
MachineInstr MI,
const TargetInstrInfo TII 
)
static

◆ getCommutedVPERMV3Opcode()

static unsigned getCommutedVPERMV3Opcode ( unsigned  Opcode)
static

◆ getFallThroughMBB()

static MachineBasicBlock* getFallThroughMBB ( MachineBasicBlock MBB,
MachineBasicBlock TBB 
)
static

◆ getLoadRegOpcode()

static unsigned getLoadRegOpcode ( unsigned  DestReg,
const TargetRegisterClass RC,
bool  isStackAligned,
const X86Subtarget STI 
)
static

◆ getLoadStoreRegOpcode()

static unsigned getLoadStoreRegOpcode ( unsigned  Reg,
const TargetRegisterClass RC,
bool  isStackAligned,
const X86Subtarget STI,
bool  load 
)
static

◆ getStoreRegOpcode()

static unsigned getStoreRegOpcode ( unsigned  SrcReg,
const TargetRegisterClass RC,
bool  isStackAligned,
const X86Subtarget STI 
)
static

◆ getSwappedCondition()

static X86::CondCode getSwappedCondition ( X86::CondCode  CC)
static

Assuming the flags are set by MI(a,b), return the condition code if we modify the instructions such that flags are set by MI(b,a).

Definition at line 2281 of file X86InstrInfo.cpp.

References llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, llvm::X86::COND_E, llvm::X86::COND_G, llvm::X86::COND_GE, llvm::X86::COND_INVALID, llvm::X86::COND_L, llvm::X86::COND_LE, and llvm::X86::COND_NE.

Referenced by llvm::X86InstrInfo::optimizeCompareInstr().

◆ getThreeSrcCommuteCase()

static unsigned getThreeSrcCommuteCase ( uint64_t  TSFlags,
unsigned  SrcOpIdx1,
unsigned  SrcOpIdx2 
)
static

This determines which of three possible cases of a three source commute the source indexes correspond to taking into account any mask operands.

All prevents commuting a passthru operand. Returns -1 if the commute isn't possible. Case 0 - Possible to commute the first and second operands. Case 1 - Possible to commute the first and third operands. Case 2 - Possible to commute the second and third operands.

Definition at line 1323 of file X86InstrInfo.cpp.

References llvm::X86II::isKMasked(), llvm_unreachable, and std::swap().

Referenced by commuteVPTERNLOG(), and llvm::X86InstrInfo::getFMA3OpcodeToCommuteOperands().

◆ getTruncatedShiftCount()

static unsigned getTruncatedShiftCount ( MachineInstr MI,
unsigned  ShiftAmtOperandIdx 
)
inlinestatic

◆ hasPartialRegUpdate()

static bool hasPartialRegUpdate ( unsigned  Opcode,
const X86Subtarget Subtarget 
)
static

Return true for all instructions that only update the first 32 or 64-bits of the destination register and leave the rest unmodified.

This can be used to avoid folding loads if the instructions only update part of the destination register, and the non-updated part is not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks the partial register dependency and it can improve performance. e.g.:

movss (rdi), xmm0 cvtss2sd xmm0, xmm0

Instead of cvtss2sd (rdi), xmm0

FIXME: This should be turned into a TSFlags.

Definition at line 4326 of file X86InstrInfo.cpp.

References llvm::X86Subtarget::hasLZCNTFalseDeps(), and llvm::X86Subtarget::hasPOPCNTFalseDeps().

Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl(), and llvm::X86InstrInfo::getPartialRegUpdateClearance().

◆ hasUndefRegUpdate()

static bool hasUndefRegUpdate ( unsigned  Opcode)
static

◆ isCommutableVPERMV3Instruction()

static bool isCommutableVPERMV3Instruction ( unsigned  Opcode)
static

◆ isDefConvertible()

static bool isDefConvertible ( MachineInstr MI)
inlinestatic

Check whether the definition can be converted to remove a comparison against zero.

Definition at line 3495 of file X86InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), getTruncatedShiftCount(), and isTruncatedShiftCountForLEA().

Referenced by llvm::X86InstrInfo::optimizeCompareInstr().

◆ isFrameLoadOpcode()

static bool isFrameLoadOpcode ( int  Opcode,
unsigned MemBytes 
)
static

◆ isFrameStoreOpcode()

static bool isFrameStoreOpcode ( int  Opcode,
unsigned MemBytes 
)
static

◆ isHReg()

static bool isHReg ( unsigned  Reg)
static

Test if the given register is a physical h register.

Definition at line 2964 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::copyPhysReg(), and getLoadStoreRegOpcode().

◆ isNonFoldablePartialRegisterLoad()

static bool isNonFoldablePartialRegisterLoad ( const MachineInstr LoadMI,
const MachineInstr UserMI,
const MachineFunction MF 
)
static

Check if LoadMI is a partial register load that we can't fold into MI because the latter uses contents that wouldn't be defined in the folded version.

For instance, this transformation isn't legal: movss (rdi), xmm0 addps xmm0, xmm0 -> addps (rdi), xmm0

But this one is: movss (rdi), xmm0 addss xmm0, xmm0 -> addss (rdi), xmm0

Definition at line 5087 of file X86InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::TargetRegisterInfo::getRegSizeInBits(), llvm::MachineFunction::getSubtarget(), and TRI.

Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().

◆ isRedundantFlagInstr()

static bool isRedundantFlagInstr ( MachineInstr FlagI,
unsigned  SrcReg,
unsigned  SrcReg2,
int  ImmMask,
int  ImmValue,
MachineInstr OI 
)
inlinestatic

Check whether the first instruction, whose only purpose is to update flags, can be made redundant.

CMPrr can be made redundant by SUBrr if the operands are the same. This function can be extended later on. SrcReg, SrcRegs: register operands for FlagI. ImmValue: immediate for FlagI if it takes an immediate.

Definition at line 3462 of file X86InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().

Referenced by llvm::X86InstrInfo::optimizeCompareInstr().

◆ isTruncatedShiftCountForLEA()

static bool isTruncatedShiftCountForLEA ( unsigned  ShAmt)
inlinestatic

Check whether the given shift count is appropriate can be represented by a LEA instruction.

Definition at line 731 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::convertToThreeAddress(), and isDefConvertible().

◆ isUseDefConvertible()

static X86::CondCode isUseDefConvertible ( MachineInstr MI)
static

Check whether the use can be converted to remove a comparison against zero.

Definition at line 3600 of file X86InstrInfo.cpp.

References llvm::X86::COND_B, llvm::X86::COND_E, llvm::X86::COND_INVALID, and llvm::MachineInstr::getOpcode().

Referenced by llvm::X86InstrInfo::optimizeCompareInstr().

◆ lookup()

static const uint16_t* lookup ( unsigned  opcode,
unsigned  domain,
ArrayRef< uint16_t[3]>  Table 
)
static

◆ lookupAVX512()

static const uint16_t* lookupAVX512 ( unsigned  opcode,
unsigned  domain,
ArrayRef< uint16_t[4]>  Table 
)
static

◆ MakeM0Inst()

static MachineInstr* MakeM0Inst ( const TargetInstrInfo TII,
unsigned  Opcode,
ArrayRef< MachineOperand MOs,
MachineBasicBlock::iterator  InsertPt,
MachineInstr MI 
)
static

◆ regIsPICBase()

static bool regIsPICBase ( unsigned  BaseReg,
const MachineRegisterInfo MRI 
)
static

◆ shouldPreventUndefRegUpdateMemFold()

static bool shouldPreventUndefRegUpdateMemFold ( MachineFunction MF,
MachineInstr MI 
)
static

◆ updateOperandRegConstraints()

static void updateOperandRegConstraints ( MachineFunction MF,
MachineInstr NewMI,
const TargetInstrInfo TII 
)
static

Variable Documentation

◆ NoFusing

cl::opt<bool> NoFusing("disable-spill-fusing", cl::desc("Disable fusing of spill code into instructions"), cl::Hidden)
static

◆ PartialRegUpdateClearance

cl::opt<unsigned> PartialRegUpdateClearance("partial-reg-update-clearance", cl::desc("Clearance between two register writes " "for inserting XOR to avoid partial " "register update"), cl::init(64), cl::Hidden)
static

◆ PrintFailedFusing

cl::opt<bool> PrintFailedFusing("print-failed-fuse-candidates", cl::desc("Print instructions that the allocator wants to" " fuse, but the X86 backend currently can't"), cl::Hidden)
static

◆ ReMatPICStubLoad

cl::opt<bool> ReMatPICStubLoad("remat-pic-stub-load", cl::desc("Re-materialize load from stub in PIC mode"), cl::init(false), cl::Hidden)
static

◆ ReplaceableCustomAVX2Instrs

const uint16_t ReplaceableCustomAVX2Instrs[][3]
static
Initial value:
= {
{ X86::VBLENDPSrmi, X86::VBLENDPDrmi, X86::VPBLENDDrmi },
{ X86::VBLENDPSrri, X86::VBLENDPDrri, X86::VPBLENDDrri },
{ X86::VBLENDPSYrmi, X86::VBLENDPDYrmi, X86::VPBLENDDYrmi },
{ X86::VBLENDPSYrri, X86::VBLENDPDYrri, X86::VPBLENDDYrri },
}

Definition at line 6401 of file X86InstrInfo.cpp.

◆ ReplaceableCustomAVX512LogicInstrs

const uint16_t ReplaceableCustomAVX512LogicInstrs[][4]
static
Initial value:
= {
{ X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
{ X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
{ X86::VANDPSrm, X86::VANDPDrm, X86::VPANDQZ128rm, X86::VPANDDZ128rm },
{ X86::VANDPSrr, X86::VANDPDrr, X86::VPANDQZ128rr, X86::VPANDDZ128rr },
{ X86::VORPSrm, X86::VORPDrm, X86::VPORQZ128rm, X86::VPORDZ128rm },
{ X86::VORPSrr, X86::VORPDrr, X86::VPORQZ128rr, X86::VPORDZ128rr },
{ X86::VXORPSrm, X86::VXORPDrm, X86::VPXORQZ128rm, X86::VPXORDZ128rm },
{ X86::VXORPSrr, X86::VXORPDrr, X86::VPXORQZ128rr, X86::VPXORDZ128rr },
{ X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
{ X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
{ X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDQZ256rm, X86::VPANDDZ256rm },
{ X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDQZ256rr, X86::VPANDDZ256rr },
{ X86::VORPSYrm, X86::VORPDYrm, X86::VPORQZ256rm, X86::VPORDZ256rm },
{ X86::VORPSYrr, X86::VORPDYrr, X86::VPORQZ256rr, X86::VPORDZ256rr },
{ X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORQZ256rm, X86::VPXORDZ256rm },
{ X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORQZ256rr, X86::VPXORDZ256rr },
}

Definition at line 6411 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::setExecutionDomainCustom().

◆ ReplaceableCustomInstrs

const uint16_t ReplaceableCustomInstrs[][3]
static
Initial value:
= {
{ X86::BLENDPSrmi, X86::BLENDPDrmi, X86::PBLENDWrmi },
{ X86::BLENDPSrri, X86::BLENDPDrri, X86::PBLENDWrri },
{ X86::VBLENDPSrmi, X86::VBLENDPDrmi, X86::VPBLENDWrmi },
{ X86::VBLENDPSrri, X86::VBLENDPDrri, X86::VPBLENDWrri },
{ X86::VBLENDPSYrmi, X86::VBLENDPDYrmi, X86::VPBLENDWYrmi },
{ X86::VBLENDPSYrri, X86::VBLENDPDYrri, X86::VPBLENDWYrri },
}

Definition at line 6392 of file X86InstrInfo.cpp.

◆ ReplaceableInstrs

const uint16_t ReplaceableInstrs[][3]
static

Definition at line 5956 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::setExecutionDomain().

◆ ReplaceableInstrsAVX2

const uint16_t ReplaceableInstrsAVX2[][3]
static

Definition at line 6119 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::setExecutionDomain().

◆ ReplaceableInstrsAVX2InsertExtract

const uint16_t ReplaceableInstrsAVX2InsertExtract[][3]
static
Initial value:
= {
{ X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
{ X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
{ X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
{ X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
}

Definition at line 6152 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::setExecutionDomain().

◆ ReplaceableInstrsAVX512

const uint16_t ReplaceableInstrsAVX512[][4]
static
Initial value:
= {
{ X86::VMOVAPSZ128mr, X86::VMOVAPDZ128mr, X86::VMOVDQA64Z128mr, X86::VMOVDQA32Z128mr },
{ X86::VMOVAPSZ128rm, X86::VMOVAPDZ128rm, X86::VMOVDQA64Z128rm, X86::VMOVDQA32Z128rm },
{ X86::VMOVAPSZ128rr, X86::VMOVAPDZ128rr, X86::VMOVDQA64Z128rr, X86::VMOVDQA32Z128rr },
{ X86::VMOVUPSZ128mr, X86::VMOVUPDZ128mr, X86::VMOVDQU64Z128mr, X86::VMOVDQU32Z128mr },
{ X86::VMOVUPSZ128rm, X86::VMOVUPDZ128rm, X86::VMOVDQU64Z128rm, X86::VMOVDQU32Z128rm },
{ X86::VMOVAPSZ256mr, X86::VMOVAPDZ256mr, X86::VMOVDQA64Z256mr, X86::VMOVDQA32Z256mr },
{ X86::VMOVAPSZ256rm, X86::VMOVAPDZ256rm, X86::VMOVDQA64Z256rm, X86::VMOVDQA32Z256rm },
{ X86::VMOVAPSZ256rr, X86::VMOVAPDZ256rr, X86::VMOVDQA64Z256rr, X86::VMOVDQA32Z256rr },
{ X86::VMOVUPSZ256mr, X86::VMOVUPDZ256mr, X86::VMOVDQU64Z256mr, X86::VMOVDQU32Z256mr },
{ X86::VMOVUPSZ256rm, X86::VMOVUPDZ256rm, X86::VMOVDQU64Z256rm, X86::VMOVDQU32Z256rm },
{ X86::VMOVAPSZmr, X86::VMOVAPDZmr, X86::VMOVDQA64Zmr, X86::VMOVDQA32Zmr },
{ X86::VMOVAPSZrm, X86::VMOVAPDZrm, X86::VMOVDQA64Zrm, X86::VMOVDQA32Zrm },
{ X86::VMOVAPSZrr, X86::VMOVAPDZrr, X86::VMOVDQA64Zrr, X86::VMOVDQA32Zrr },
{ X86::VMOVUPSZmr, X86::VMOVUPDZmr, X86::VMOVDQU64Zmr, X86::VMOVDQU32Zmr },
{ X86::VMOVUPSZrm, X86::VMOVUPDZrm, X86::VMOVDQU64Zrm, X86::VMOVDQU32Zrm },
}

Definition at line 6160 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::setExecutionDomain().

◆ ReplaceableInstrsAVX512DQ

const uint16_t ReplaceableInstrsAVX512DQ[][4]
static
Initial value:
= {
{ X86::VANDNPSZ128rm, X86::VANDNPDZ128rm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
{ X86::VANDNPSZ128rr, X86::VANDNPDZ128rr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
{ X86::VANDPSZ128rm, X86::VANDPDZ128rm, X86::VPANDQZ128rm, X86::VPANDDZ128rm },
{ X86::VANDPSZ128rr, X86::VANDPDZ128rr, X86::VPANDQZ128rr, X86::VPANDDZ128rr },
{ X86::VORPSZ128rm, X86::VORPDZ128rm, X86::VPORQZ128rm, X86::VPORDZ128rm },
{ X86::VORPSZ128rr, X86::VORPDZ128rr, X86::VPORQZ128rr, X86::VPORDZ128rr },
{ X86::VXORPSZ128rm, X86::VXORPDZ128rm, X86::VPXORQZ128rm, X86::VPXORDZ128rm },
{ X86::VXORPSZ128rr, X86::VXORPDZ128rr, X86::VPXORQZ128rr, X86::VPXORDZ128rr },
{ X86::VANDNPSZ256rm, X86::VANDNPDZ256rm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
{ X86::VANDNPSZ256rr, X86::VANDNPDZ256rr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
{ X86::VANDPSZ256rm, X86::VANDPDZ256rm, X86::VPANDQZ256rm, X86::VPANDDZ256rm },
{ X86::VANDPSZ256rr, X86::VANDPDZ256rr, X86::VPANDQZ256rr, X86::VPANDDZ256rr },
{ X86::VORPSZ256rm, X86::VORPDZ256rm, X86::VPORQZ256rm, X86::VPORDZ256rm },
{ X86::VORPSZ256rr, X86::VORPDZ256rr, X86::VPORQZ256rr, X86::VPORDZ256rr },
{ X86::VXORPSZ256rm, X86::VXORPDZ256rm, X86::VPXORQZ256rm, X86::VPXORDZ256rm },
{ X86::VXORPSZ256rr, X86::VXORPDZ256rr, X86::VPXORQZ256rr, X86::VPXORDZ256rr },
{ X86::VANDNPSZrm, X86::VANDNPDZrm, X86::VPANDNQZrm, X86::VPANDNDZrm },
{ X86::VANDNPSZrr, X86::VANDNPDZrr, X86::VPANDNQZrr, X86::VPANDNDZrr },
{ X86::VANDPSZrm, X86::VANDPDZrm, X86::VPANDQZrm, X86::VPANDDZrm },
{ X86::VANDPSZrr, X86::VANDPDZrr, X86::VPANDQZrr, X86::VPANDDZrr },
{ X86::VORPSZrm, X86::VORPDZrm, X86::VPORQZrm, X86::VPORDZrm },
{ X86::VORPSZrr, X86::VORPDZrr, X86::VPORQZrr, X86::VPORDZrr },
{ X86::VXORPSZrm, X86::VXORPDZrm, X86::VPXORQZrm, X86::VPXORDZrm },
{ X86::VXORPSZrr, X86::VXORPDZrr, X86::VPXORQZrr, X86::VPXORDZrr },
}

Definition at line 6180 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::setExecutionDomain().

◆ ReplaceableInstrsAVX512DQMasked

const uint16_t ReplaceableInstrsAVX512DQMasked[][4]
static

Definition at line 6209 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::setExecutionDomain().

◆ UndefRegClearance

cl::opt<unsigned> UndefRegClearance("undef-reg-clearance", cl::desc("How many idle instructions we would like before " "certain undef register reads"), cl::init(128), cl::Hidden)
static