LLVM  9.0.0svn
PPCTLSDynamicCall.cpp
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1 //===---------- PPCTLSDynamicCall.cpp - TLS Dynamic Call Fixup ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This pass expands ADDItls{ld,gd}LADDR[32] machine instructions into
10 // separate ADDItls[gd]L[32] and GETtlsADDR[32] instructions, both of
11 // which define GPR3. A copy is added from GPR3 to the target virtual
12 // register of the original instruction. The GETtlsADDR[32] is really
13 // a call instruction, so its target register is constrained to be GPR3.
14 // This is not true of ADDItls[gd]L[32], but there is a legacy linker
15 // optimization bug that requires the target register of the addi of
16 // a local- or general-dynamic TLS access sequence to be GPR3.
17 //
18 // This is done in a late pass so that TLS variable accesses can be
19 // fully commoned by MachineCSE.
20 //
21 //===----------------------------------------------------------------------===//
22 
23 #include "PPC.h"
24 #include "PPCInstrBuilder.h"
25 #include "PPCInstrInfo.h"
26 #include "PPCTargetMachine.h"
30 #include "llvm/Support/Debug.h"
32 
33 using namespace llvm;
34 
35 #define DEBUG_TYPE "ppc-tls-dynamic-call"
36 
37 namespace llvm {
39 }
40 
41 namespace {
42  struct PPCTLSDynamicCall : public MachineFunctionPass {
43  static char ID;
44  PPCTLSDynamicCall() : MachineFunctionPass(ID) {
46  }
47 
48  const PPCInstrInfo *TII;
49  LiveIntervals *LIS;
50 
51 protected:
52  bool processBlock(MachineBasicBlock &MBB) {
53  bool Changed = false;
54  bool NeedFence = true;
55  bool Is64Bit = MBB.getParent()->getSubtarget<PPCSubtarget>().isPPC64();
56 
57  for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
58  I != IE;) {
59  MachineInstr &MI = *I;
60 
61  if (MI.getOpcode() != PPC::ADDItlsgdLADDR &&
62  MI.getOpcode() != PPC::ADDItlsldLADDR &&
63  MI.getOpcode() != PPC::ADDItlsgdLADDR32 &&
64  MI.getOpcode() != PPC::ADDItlsldLADDR32) {
65 
66  // Although we create ADJCALLSTACKDOWN and ADJCALLSTACKUP
67  // as scheduling fences, we skip creating fences if we already
68  // have existing ADJCALLSTACKDOWN/UP to avoid nesting,
69  // which causes verification error with -verify-machineinstrs.
70  if (MI.getOpcode() == PPC::ADJCALLSTACKDOWN)
71  NeedFence = false;
72  else if (MI.getOpcode() == PPC::ADJCALLSTACKUP)
73  NeedFence = true;
74 
75  ++I;
76  continue;
77  }
78 
79  LLVM_DEBUG(dbgs() << "TLS Dynamic Call Fixup:\n " << MI);
80 
81  unsigned OutReg = MI.getOperand(0).getReg();
82  unsigned InReg = MI.getOperand(1).getReg();
83  DebugLoc DL = MI.getDebugLoc();
84  unsigned GPR3 = Is64Bit ? PPC::X3 : PPC::R3;
85  unsigned Opc1, Opc2;
86  const unsigned OrigRegs[] = {OutReg, InReg, GPR3};
87 
88  switch (MI.getOpcode()) {
89  default:
90  llvm_unreachable("Opcode inconsistency error");
91  case PPC::ADDItlsgdLADDR:
92  Opc1 = PPC::ADDItlsgdL;
93  Opc2 = PPC::GETtlsADDR;
94  break;
95  case PPC::ADDItlsldLADDR:
96  Opc1 = PPC::ADDItlsldL;
97  Opc2 = PPC::GETtlsldADDR;
98  break;
99  case PPC::ADDItlsgdLADDR32:
100  Opc1 = PPC::ADDItlsgdL32;
101  Opc2 = PPC::GETtlsADDR32;
102  break;
103  case PPC::ADDItlsldLADDR32:
104  Opc1 = PPC::ADDItlsldL32;
105  Opc2 = PPC::GETtlsldADDR32;
106  break;
107  }
108 
109  // We create ADJCALLSTACKUP and ADJCALLSTACKDOWN around _tls_get_addr
110  // as scheduling fence to avoid it is scheduled before
111  // mflr in the prologue and the address in LR is clobbered (PR25839).
112  // We don't really need to save data to the stack - the clobbered
113  // registers are already saved when the SDNode (e.g. PPCaddiTlsgdLAddr)
114  // gets translated to the pseudo instruction (e.g. ADDItlsgdLADDR).
115  if (NeedFence)
116  BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKDOWN)).addImm(0)
117  .addImm(0);
118 
119  // Expand into two ops built prior to the existing instruction.
120  MachineInstr *Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3)
121  .addReg(InReg);
122  Addi->addOperand(MI.getOperand(2));
123 
124  // The ADDItls* instruction is the first instruction in the
125  // repair range.
127  --First;
128 
129  MachineInstr *Call = (BuildMI(MBB, I, DL, TII->get(Opc2), GPR3)
130  .addReg(GPR3));
131  Call->addOperand(MI.getOperand(3));
132 
133  if (NeedFence)
134  BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKUP)).addImm(0).addImm(0);
135 
136  BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), OutReg)
137  .addReg(GPR3);
138 
139  // The COPY is the last instruction in the repair range.
141  --Last;
142 
143  // Move past the original instruction and remove it.
144  ++I;
145  MI.removeFromParent();
146 
147  // Repair the live intervals.
148  LIS->repairIntervalsInRange(&MBB, First, Last, OrigRegs);
149  Changed = true;
150  }
151 
152  return Changed;
153  }
154 
155 public:
156  bool runOnMachineFunction(MachineFunction &MF) override {
157  TII = MF.getSubtarget<PPCSubtarget>().getInstrInfo();
158  LIS = &getAnalysis<LiveIntervals>();
159 
160  bool Changed = false;
161 
162  for (MachineFunction::iterator I = MF.begin(); I != MF.end();) {
163  MachineBasicBlock &B = *I++;
164  if (processBlock(B))
165  Changed = true;
166  }
167 
168  return Changed;
169  }
170 
171  void getAnalysisUsage(AnalysisUsage &AU) const override {
174  AU.addRequired<SlotIndexes>();
177  }
178  };
179 }
180 
181 INITIALIZE_PASS_BEGIN(PPCTLSDynamicCall, DEBUG_TYPE,
182  "PowerPC TLS Dynamic Call Fixup", false, false)
185 INITIALIZE_PASS_END(PPCTLSDynamicCall, DEBUG_TYPE,
186  "PowerPC TLS Dynamic Call Fixup", false, false)
187 
188 char PPCTLSDynamicCall::ID = 0;
190 llvm::createPPCTLSDynamicCallPass() { return new PPCTLSDynamicCall(); }
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void initializePPCTLSDynamicCallPass(PassRegistry &)
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:382
unsigned getReg() const
getReg - Returns the register number.
A debug info location.
Definition: DebugLoc.h:33
FunctionPass * createPPCTLSDynamicCallPass()
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:50
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
INITIALIZE_PASS_BEGIN(PPCTLSDynamicCall, DEBUG_TYPE, "PowerPC TLS Dynamic Call Fixup", false, false) INITIALIZE_PASS_END(PPCTLSDynamicCall
SlotIndexes pass.
Definition: SlotIndexes.h:328
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Represent the analysis usage information of a pass.
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
void repairIntervalsInRange(MachineBasicBlock *MBB, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, ArrayRef< unsigned > OrigRegs)
Update live intervals for instructions in a range of iterators.
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Iterator for intrusive lists based on ilist_node.
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
#define DEBUG_TYPE
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
#define I(x, y, z)
Definition: MD5.cpp:58
MachineInstr * removeFromParent()
Unlink &#39;this&#39; from the containing basic block, and return it without deleting it. ...
IRTranslator LLVM IR MI
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413