LLVM  10.0.0svn
RISCVSubtarget.h
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1 //===-- RISCVSubtarget.h - Define Subtarget for the RISCV -------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the RISCV specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
14 #define LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
15 
16 #include "RISCVFrameLowering.h"
17 #include "RISCVISelLowering.h"
18 #include "RISCVInstrInfo.h"
19 #include "Utils/RISCVBaseInfo.h"
26 #include "llvm/IR/DataLayout.h"
28 
29 #define GET_SUBTARGETINFO_HEADER
30 #include "RISCVGenSubtargetInfo.inc"
31 
32 namespace llvm {
33 class StringRef;
34 
36  virtual void anchor();
37  bool HasStdExtM = false;
38  bool HasStdExtA = false;
39  bool HasStdExtF = false;
40  bool HasStdExtD = false;
41  bool HasStdExtC = false;
42  bool HasRV64 = false;
43  bool IsRV32E = false;
44  bool EnableLinkerRelax = false;
45  bool EnableRVCHintInstrs = false;
46  unsigned XLen = 32;
47  MVT XLenVT = MVT::i32;
49  RISCVFrameLowering FrameLowering;
50  RISCVInstrInfo InstrInfo;
52  RISCVTargetLowering TLInfo;
54 
55  /// Initializes using the passed in CPU and feature strings so that we can
56  /// use initializer lists for subtarget initialization.
57  RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
58  StringRef CPU, StringRef FS,
59  StringRef ABIName);
60 
61 public:
62  // Initializes the data members to match that of the specified triple.
63  RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
64  StringRef ABIName, const TargetMachine &TM);
65 
66  // Parses features string setting specified subtarget options. The
67  // definition of this function is auto-generated by tblgen.
69 
70  const RISCVFrameLowering *getFrameLowering() const override {
71  return &FrameLowering;
72  }
73  const RISCVInstrInfo *getInstrInfo() const override { return &InstrInfo; }
74  const RISCVRegisterInfo *getRegisterInfo() const override {
75  return &RegInfo;
76  }
77  const RISCVTargetLowering *getTargetLowering() const override {
78  return &TLInfo;
79  }
80  const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
81  return &TSInfo;
82  }
83  bool enableMachineScheduler() const override { return true; }
84  bool hasStdExtM() const { return HasStdExtM; }
85  bool hasStdExtA() const { return HasStdExtA; }
86  bool hasStdExtF() const { return HasStdExtF; }
87  bool hasStdExtD() const { return HasStdExtD; }
88  bool hasStdExtC() const { return HasStdExtC; }
89  bool is64Bit() const { return HasRV64; }
90  bool isRV32E() const { return IsRV32E; }
91  bool enableLinkerRelax() const { return EnableLinkerRelax; }
92  bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; }
93  MVT getXLenVT() const { return XLenVT; }
94  unsigned getXLen() const { return XLen; }
95  RISCVABI::ABI getTargetABI() const { return TargetABI; }
96 
97 protected:
98  // GlobalISel related APIs.
99  std::unique_ptr<CallLowering> CallLoweringInfo;
100  std::unique_ptr<InstructionSelector> InstSelector;
101  std::unique_ptr<LegalizerInfo> Legalizer;
102  std::unique_ptr<RegisterBankInfo> RegBankInfo;
103 
104 public:
105  const CallLowering *getCallLowering() const override;
107  const LegalizerInfo *getLegalizerInfo() const override;
108  const RegisterBankInfo *getRegBankInfo() const override;
109 };
110 } // End llvm namespace
111 
112 #endif
RISCVABI::ABI getTargetABI() const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
const RegisterBankInfo * getRegBankInfo() const override
const RISCVRegisterInfo * getRegisterInfo() const override
std::unique_ptr< InstructionSelector > InstSelector
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
const LegalizerInfo * getLegalizerInfo() const override
Holds all the information related to register banks.
bool enableMachineScheduler() const override
unsigned getXLen() const
bool isRV32E() const
bool hasStdExtA() const
std::unique_ptr< RegisterBankInfo > RegBankInfo
bool enableLinkerRelax() const
InstructionSelector * getInstructionSelector() const override
Machine Value Type.
bool hasStdExtF() const
const RISCVTargetLowering * getTargetLowering() const override
bool hasStdExtM() const
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
const CallLowering * getCallLowering() const override
bool hasStdExtD() const
const RISCVFrameLowering * getFrameLowering() const override
std::unique_ptr< LegalizerInfo > Legalizer
bool is64Bit() const
Provides the logic to select generic machine instructions.
std::unique_ptr< CallLowering > CallLoweringInfo
RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef FS, StringRef ABIName, const TargetMachine &TM)
bool hasStdExtC() const
const RISCVInstrInfo * getInstrInfo() const override
This file describes how to lower LLVM calls to machine code calls.
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
bool enableRVCHintInstrs() const
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)