LLVM  9.0.0svn
AVRFrameLowering.cpp
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1 //===-- AVRFrameLowering.cpp - AVR Frame Information ----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the AVR implementation of TargetFrameLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AVRFrameLowering.h"
14 
15 #include "AVR.h"
16 #include "AVRInstrInfo.h"
17 #include "AVRMachineFunctionInfo.h"
18 #include "AVRTargetMachine.h"
20 
26 #include "llvm/IR/Function.h"
27 
28 #include <vector>
29 
30 namespace llvm {
31 
33  : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 1, -2) {}
34 
36  const MachineFunction &MF) const {
37  // Always simplify call frame pseudo instructions, even when
38  // hasReservedCallFrame is false.
39  return true;
40 }
41 
43  // Reserve call frame memory in function prologue under the following
44  // conditions:
45  // - Y pointer is reserved to be the frame pointer.
46  // - The function does not contain variable sized objects.
47 
48  const MachineFrameInfo &MFI = MF.getFrameInfo();
49  return hasFP(MF) && !MFI.hasVarSizedObjects();
50 }
51 
53  MachineBasicBlock &MBB) const {
55  CallingConv::ID CallConv = MF.getFunction().getCallingConv();
56  DebugLoc DL = (MBBI != MBB.end()) ? MBBI->getDebugLoc() : DebugLoc();
57  const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
58  const AVRInstrInfo &TII = *STI.getInstrInfo();
59  bool HasFP = hasFP(MF);
60 
61  // Interrupt handlers re-enable interrupts in function entry.
62  if (CallConv == CallingConv::AVR_INTR) {
63  BuildMI(MBB, MBBI, DL, TII.get(AVR::BSETs))
64  .addImm(0x07)
66  }
67 
68  // Save the frame pointer if we have one.
69  if (HasFP) {
70  BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHWRr))
71  .addReg(AVR::R29R28, RegState::Kill)
73  }
74 
75  // Emit special prologue code to save R1, R0 and SREG in interrupt/signal
76  // handlers before saving any other registers.
77  if (CallConv == CallingConv::AVR_INTR ||
78  CallConv == CallingConv::AVR_SIGNAL) {
79  BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHWRr))
80  .addReg(AVR::R1R0, RegState::Kill)
82 
83  BuildMI(MBB, MBBI, DL, TII.get(AVR::INRdA), AVR::R0)
84  .addImm(0x3f)
86  BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr))
87  .addReg(AVR::R0, RegState::Kill)
89  BuildMI(MBB, MBBI, DL, TII.get(AVR::EORRdRr))
90  .addReg(AVR::R0, RegState::Define)
91  .addReg(AVR::R0, RegState::Kill)
92  .addReg(AVR::R0, RegState::Kill)
94  }
95 
96  // Early exit if the frame pointer is not needed in this function.
97  if (!HasFP) {
98  return;
99  }
100 
101  const MachineFrameInfo &MFI = MF.getFrameInfo();
103  unsigned FrameSize = MFI.getStackSize() - AFI->getCalleeSavedFrameSize();
104 
105  // Skip the callee-saved push instructions.
106  while (
107  (MBBI != MBB.end()) && MBBI->getFlag(MachineInstr::FrameSetup) &&
108  (MBBI->getOpcode() == AVR::PUSHRr || MBBI->getOpcode() == AVR::PUSHWRr)) {
109  ++MBBI;
110  }
111 
112  // Update Y with the new base value.
113  BuildMI(MBB, MBBI, DL, TII.get(AVR::SPREAD), AVR::R29R28)
114  .addReg(AVR::SP)
116 
117  // Mark the FramePtr as live-in in every block except the entry.
118  for (MachineFunction::iterator I = std::next(MF.begin()), E = MF.end();
119  I != E; ++I) {
120  I->addLiveIn(AVR::R29R28);
121  }
122 
123  if (!FrameSize) {
124  return;
125  }
126 
127  // Reserve the necessary frame memory by doing FP -= <size>.
128  unsigned Opcode = (isUInt<6>(FrameSize)) ? AVR::SBIWRdK : AVR::SUBIWRdK;
129 
130  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opcode), AVR::R29R28)
131  .addReg(AVR::R29R28, RegState::Kill)
132  .addImm(FrameSize)
134  // The SREG implicit def is dead.
135  MI->getOperand(3).setIsDead();
136 
137  // Write back R29R28 to SP and temporarily disable interrupts.
138  BuildMI(MBB, MBBI, DL, TII.get(AVR::SPWRITE), AVR::SP)
139  .addReg(AVR::R29R28)
141 }
142 
144  MachineBasicBlock &MBB) const {
145  CallingConv::ID CallConv = MF.getFunction().getCallingConv();
146  bool isHandler = (CallConv == CallingConv::AVR_INTR ||
147  CallConv == CallingConv::AVR_SIGNAL);
148 
149  // Early exit if the frame pointer is not needed in this function except for
150  // signal/interrupt handlers where special code generation is required.
151  if (!hasFP(MF) && !isHandler) {
152  return;
153  }
154 
156  assert(MBBI->getDesc().isReturn() &&
157  "Can only insert epilog into returning blocks");
158 
159  DebugLoc DL = MBBI->getDebugLoc();
160  const MachineFrameInfo &MFI = MF.getFrameInfo();
162  unsigned FrameSize = MFI.getStackSize() - AFI->getCalleeSavedFrameSize();
163  const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
164  const AVRInstrInfo &TII = *STI.getInstrInfo();
165 
166  // Emit special epilogue code to restore R1, R0 and SREG in interrupt/signal
167  // handlers at the very end of the function, just before reti.
168  if (isHandler) {
169  BuildMI(MBB, MBBI, DL, TII.get(AVR::POPRd), AVR::R0);
170  BuildMI(MBB, MBBI, DL, TII.get(AVR::OUTARr))
171  .addImm(0x3f)
172  .addReg(AVR::R0, RegState::Kill);
173  BuildMI(MBB, MBBI, DL, TII.get(AVR::POPWRd), AVR::R1R0);
174  }
175 
176  if (hasFP(MF))
177  BuildMI(MBB, MBBI, DL, TII.get(AVR::POPWRd), AVR::R29R28);
178 
179  // Early exit if there is no need to restore the frame pointer.
180  if (!FrameSize) {
181  return;
182  }
183 
184  // Skip the callee-saved pop instructions.
185  while (MBBI != MBB.begin()) {
186  MachineBasicBlock::iterator PI = std::prev(MBBI);
187  int Opc = PI->getOpcode();
188 
189  if (Opc != AVR::POPRd && Opc != AVR::POPWRd && !PI->isTerminator()) {
190  break;
191  }
192 
193  --MBBI;
194  }
195 
196  unsigned Opcode;
197 
198  // Select the optimal opcode depending on how big it is.
199  if (isUInt<6>(FrameSize)) {
200  Opcode = AVR::ADIWRdK;
201  } else {
202  Opcode = AVR::SUBIWRdK;
203  FrameSize = -FrameSize;
204  }
205 
206  // Restore the frame pointer by doing FP += <size>.
207  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opcode), AVR::R29R28)
208  .addReg(AVR::R29R28, RegState::Kill)
209  .addImm(FrameSize);
210  // The SREG implicit def is dead.
211  MI->getOperand(3).setIsDead();
212 
213  // Write back R29R28 to SP and temporarily disable interrupts.
214  BuildMI(MBB, MBBI, DL, TII.get(AVR::SPWRITE), AVR::SP)
215  .addReg(AVR::R29R28, RegState::Kill);
216 }
217 
218 // Return true if the specified function should have a dedicated frame
219 // pointer register. This is true if the function meets any of the following
220 // conditions:
221 // - a register has been spilled
222 // - has allocas
223 // - input arguments are passed using the stack
224 //
225 // Notice that strictly this is not a frame pointer because it contains SP after
226 // frame allocation instead of having the original SP in function entry.
228  const AVRMachineFunctionInfo *FuncInfo = MF.getInfo<AVRMachineFunctionInfo>();
229 
230  return (FuncInfo->getHasSpills() || FuncInfo->getHasAllocas() ||
231  FuncInfo->getHasStackArgs());
232 }
233 
236  const std::vector<CalleeSavedInfo> &CSI,
237  const TargetRegisterInfo *TRI) const {
238  if (CSI.empty()) {
239  return false;
240  }
241 
242  unsigned CalleeFrameSize = 0;
243  DebugLoc DL = MBB.findDebugLoc(MI);
244  MachineFunction &MF = *MBB.getParent();
245  const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
246  const TargetInstrInfo &TII = *STI.getInstrInfo();
248 
249  for (unsigned i = CSI.size(); i != 0; --i) {
250  unsigned Reg = CSI[i - 1].getReg();
251  bool IsNotLiveIn = !MBB.isLiveIn(Reg);
252 
253  assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 &&
254  "Invalid register size");
255 
256  // Add the callee-saved register as live-in only if it is not already a
257  // live-in register, this usually happens with arguments that are passed
258  // through callee-saved registers.
259  if (IsNotLiveIn) {
260  MBB.addLiveIn(Reg);
261  }
262 
263  // Do not kill the register when it is an input argument.
264  BuildMI(MBB, MI, DL, TII.get(AVR::PUSHRr))
265  .addReg(Reg, getKillRegState(IsNotLiveIn))
266  .setMIFlag(MachineInstr::FrameSetup);
267  ++CalleeFrameSize;
268  }
269 
270  AVRFI->setCalleeSavedFrameSize(CalleeFrameSize);
271 
272  return true;
273 }
274 
277  std::vector<CalleeSavedInfo> &CSI,
278  const TargetRegisterInfo *TRI) const {
279  if (CSI.empty()) {
280  return false;
281  }
282 
283  DebugLoc DL = MBB.findDebugLoc(MI);
284  const MachineFunction &MF = *MBB.getParent();
285  const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
286  const TargetInstrInfo &TII = *STI.getInstrInfo();
287 
288  for (const CalleeSavedInfo &CCSI : CSI) {
289  unsigned Reg = CCSI.getReg();
290 
291  assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 &&
292  "Invalid register size");
293 
294  BuildMI(MBB, MI, DL, TII.get(AVR::POPRd), Reg);
295  }
296 
297  return true;
298 }
299 
300 /// Replace pseudo store instructions that pass arguments through the stack with
301 /// real instructions. If insertPushes is true then all instructions are
302 /// replaced with push instructions, otherwise regular std instructions are
303 /// inserted.
306  const TargetInstrInfo &TII, bool insertPushes) {
307  const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
308  const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
309 
310  // Iterate through the BB until we hit a call instruction or we reach the end.
311  for (auto I = MI, E = MBB.end(); I != E && !I->isCall();) {
312  MachineBasicBlock::iterator NextMI = std::next(I);
313  MachineInstr &MI = *I;
314  unsigned Opcode = I->getOpcode();
315 
316  // Only care of pseudo store instructions where SP is the base pointer.
317  if (Opcode != AVR::STDSPQRr && Opcode != AVR::STDWSPQRr) {
318  I = NextMI;
319  continue;
320  }
321 
322  assert(MI.getOperand(0).getReg() == AVR::SP &&
323  "Invalid register, should be SP!");
324  if (insertPushes) {
325  // Replace this instruction with a push.
326  unsigned SrcReg = MI.getOperand(2).getReg();
327  bool SrcIsKill = MI.getOperand(2).isKill();
328 
329  // We can't use PUSHWRr here because when expanded the order of the new
330  // instructions are reversed from what we need. Perform the expansion now.
331  if (Opcode == AVR::STDWSPQRr) {
332  BuildMI(MBB, I, MI.getDebugLoc(), TII.get(AVR::PUSHRr))
333  .addReg(TRI.getSubReg(SrcReg, AVR::sub_hi),
334  getKillRegState(SrcIsKill));
335  BuildMI(MBB, I, MI.getDebugLoc(), TII.get(AVR::PUSHRr))
336  .addReg(TRI.getSubReg(SrcReg, AVR::sub_lo),
337  getKillRegState(SrcIsKill));
338  } else {
339  BuildMI(MBB, I, MI.getDebugLoc(), TII.get(AVR::PUSHRr))
340  .addReg(SrcReg, getKillRegState(SrcIsKill));
341  }
342 
343  MI.eraseFromParent();
344  I = NextMI;
345  continue;
346  }
347 
348  // Replace this instruction with a regular store. Use Y as the base
349  // pointer since it is guaranteed to contain a copy of SP.
350  unsigned STOpc =
351  (Opcode == AVR::STDWSPQRr) ? AVR::STDWPtrQRr : AVR::STDPtrQRr;
352 
353  MI.setDesc(TII.get(STOpc));
354  MI.getOperand(0).setReg(AVR::R29R28);
355 
356  I = NextMI;
357  }
358 }
359 
363  const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
364  const TargetFrameLowering &TFI = *STI.getFrameLowering();
365  const AVRInstrInfo &TII = *STI.getInstrInfo();
366 
367  // There is nothing to insert when the call frame memory is allocated during
368  // function entry. Delete the call frame pseudo and replace all pseudo stores
369  // with real store instructions.
370  if (TFI.hasReservedCallFrame(MF)) {
371  fixStackStores(MBB, MI, TII, false);
372  return MBB.erase(MI);
373  }
374 
375  DebugLoc DL = MI->getDebugLoc();
376  unsigned int Opcode = MI->getOpcode();
377  int Amount = TII.getFrameSize(*MI);
378 
379  // Adjcallstackup does not need to allocate stack space for the call, instead
380  // we insert push instructions that will allocate the necessary stack.
381  // For adjcallstackdown we convert it into an 'adiw reg, <amt>' handling
382  // the read and write of SP in I/O space.
383  if (Amount != 0) {
384  assert(TFI.getStackAlignment() == 1 && "Unsupported stack alignment");
385 
386  if (Opcode == TII.getCallFrameSetupOpcode()) {
387  fixStackStores(MBB, MI, TII, true);
388  } else {
389  assert(Opcode == TII.getCallFrameDestroyOpcode());
390 
391  // Select the best opcode to adjust SP based on the offset size.
392  unsigned addOpcode;
393  if (isUInt<6>(Amount)) {
394  addOpcode = AVR::ADIWRdK;
395  } else {
396  addOpcode = AVR::SUBIWRdK;
397  Amount = -Amount;
398  }
399 
400  // Build the instruction sequence.
401  BuildMI(MBB, MI, DL, TII.get(AVR::SPREAD), AVR::R31R30).addReg(AVR::SP);
402 
403  MachineInstr *New = BuildMI(MBB, MI, DL, TII.get(addOpcode), AVR::R31R30)
404  .addReg(AVR::R31R30, RegState::Kill)
405  .addImm(Amount);
406  New->getOperand(3).setIsDead();
407 
408  BuildMI(MBB, MI, DL, TII.get(AVR::SPWRITE), AVR::SP)
409  .addReg(AVR::R31R30, RegState::Kill);
410  }
411  }
412 
413  return MBB.erase(MI);
414 }
415 
417  BitVector &SavedRegs,
418  RegScavenger *RS) const {
420 
421  // If we have a frame pointer, the Y register needs to be saved as well.
422  // We don't do that here however - the prologue and epilogue generation
423  // code will handle it specially.
424 }
425 /// The frame analyzer pass.
426 ///
427 /// Scans the function for allocas and used arguments
428 /// that are passed through the stack.
430  static char ID;
432 
434  const MachineFrameInfo &MFI = MF.getFrameInfo();
436 
437  // If there are no fixed frame indexes during this stage it means there
438  // are allocas present in the function.
439  if (MFI.getNumObjects() != MFI.getNumFixedObjects()) {
440  // Check for the type of allocas present in the function. We only care
441  // about fixed size allocas so do not give false positives if only
442  // variable sized allocas are present.
443  for (unsigned i = 0, e = MFI.getObjectIndexEnd(); i != e; ++i) {
444  // Variable sized objects have size 0.
445  if (MFI.getObjectSize(i)) {
446  FuncInfo->setHasAllocas(true);
447  break;
448  }
449  }
450  }
451 
452  // If there are fixed frame indexes present, scan the function to see if
453  // they are really being used.
454  if (MFI.getNumFixedObjects() == 0) {
455  return false;
456  }
457 
458  // Ok fixed frame indexes present, now scan the function to see if they
459  // are really being used, otherwise we can ignore them.
460  for (const MachineBasicBlock &BB : MF) {
461  for (const MachineInstr &MI : BB) {
462  int Opcode = MI.getOpcode();
463 
464  if ((Opcode != AVR::LDDRdPtrQ) && (Opcode != AVR::LDDWRdPtrQ) &&
465  (Opcode != AVR::STDPtrQRr) && (Opcode != AVR::STDWPtrQRr)) {
466  continue;
467  }
468 
469  for (const MachineOperand &MO : MI.operands()) {
470  if (!MO.isFI()) {
471  continue;
472  }
473 
474  if (MFI.isFixedObjectIndex(MO.getIndex())) {
475  FuncInfo->setHasStackArgs(true);
476  return false;
477  }
478  }
479  }
480  }
481 
482  return false;
483  }
484 
485  StringRef getPassName() const { return "AVR Frame Analyzer"; }
486 };
487 
488 char AVRFrameAnalyzer::ID = 0;
489 
490 /// Creates instance of the frame analyzer pass.
492 
493 /// Create the Dynalloca Stack Pointer Save/Restore pass.
494 /// Insert a copy of SP before allocating the dynamic stack memory and restore
495 /// it in function exit to restore the original SP state. This avoids the need
496 /// of reserving a register pair for a frame pointer.
498  static char ID;
500 
502  // Early exit when there are no variable sized objects in the function.
503  if (!MF.getFrameInfo().hasVarSizedObjects()) {
504  return false;
505  }
506 
507  const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
508  const TargetInstrInfo &TII = *STI.getInstrInfo();
509  MachineBasicBlock &EntryMBB = MF.front();
510  MachineBasicBlock::iterator MBBI = EntryMBB.begin();
511  DebugLoc DL = EntryMBB.findDebugLoc(MBBI);
512 
513  unsigned SPCopy =
514  MF.getRegInfo().createVirtualRegister(&AVR::DREGSRegClass);
515 
516  // Create a copy of SP in function entry before any dynallocas are
517  // inserted.
518  BuildMI(EntryMBB, MBBI, DL, TII.get(AVR::COPY), SPCopy).addReg(AVR::SP);
519 
520  // Restore SP in all exit basic blocks.
521  for (MachineBasicBlock &MBB : MF) {
522  // If last instruction is a return instruction, add a restore copy.
523  if (!MBB.empty() && MBB.back().isReturn()) {
524  MBBI = MBB.getLastNonDebugInstr();
525  DL = MBBI->getDebugLoc();
526  BuildMI(MBB, MBBI, DL, TII.get(AVR::COPY), AVR::SP)
527  .addReg(SPCopy, RegState::Kill);
528  }
529  }
530 
531  return true;
532  }
533 
535  return "AVR dynalloca stack pointer save/restore";
536  }
537 };
538 
539 char AVRDynAllocaSR::ID = 0;
540 
541 /// createAVRDynAllocaSRPass - returns an instance of the dynalloca stack
542 /// pointer save/restore pass.
544 
545 } // end of namespace llvm
546 
const AVRInstrInfo * getInstrInfo() const override
Definition: AVRSubtarget.h:41
unsigned getNumFixedObjects() const
Return the number of fixed objects.
bool runOnMachineFunction(MachineFunction &MF)
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
DILocation * get() const
Get the underlying DILocation.
Definition: DebugLoc.cpp:21
Calling convention used for AVR signal routines.
Definition: CallingConv.h:179
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned getNumObjects() const
Return the number of objects.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:382
unsigned getReg() const
getReg - Returns the register number.
unsigned Reg
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
void setIsDead(bool Val=true)
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override
canSimplifyCallFramePseudos - When possible, it&#39;s best to simplify the call frame pseudo ops before d...
Utilities related to the AVR instruction set.
Definition: AVRInstrInfo.h:64
StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Used for AVR interrupt routines.
Definition: CallingConv.h:176
int getObjectIndexEnd() const
Return one past the maximum frame object index.
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
unsigned getKillRegState(bool B)
TargetInstrInfo - Interface to description of machine instruction set.
The frame analyzer pass.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Contains AVR-specific information for each MachineFunction.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions...
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MachineBasicBlock & front() const
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
Iterator for intrusive lists based on ilist_node.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
MachineOperand class - Representation of each machine instruction operand.
Information about stack frame layout on the target.
void setCalleeSavedFrameSize(unsigned Bytes)
const Function & getFunction() const
Return the LLVM function that this machine code represents.
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
A specific AVR target MCU.
Definition: AVRSubtarget.h:31
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static void fixStackStores(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const TargetInstrInfo &TII, bool insertPushes)
Replace pseudo store instructions that pass arguments through the stack with real instructions...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:58
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
FunctionPass * createAVRFrameAnalyzerPass()
Creates instance of the frame analyzer pass.
const TargetFrameLowering * getFrameLowering() const override
Definition: AVRSubtarget.h:42
const AVRRegisterInfo * getRegisterInfo() const override
Definition: AVRSubtarget.h:45
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
FunctionPass * createAVRDynAllocaSRPass()
createAVRDynAllocaSRPass - returns an instance of the dynalloca stack pointer save/restore pass...
bool runOnMachineFunction(MachineFunction &MF)
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Create the Dynalloca Stack Pointer Save/Restore pass.