LLVM  6.0.0svn
AVRFrameLowering.cpp
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1 //===-- AVRFrameLowering.cpp - AVR Frame Information ----------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the AVR implementation of TargetFrameLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AVRFrameLowering.h"
15 
16 #include "AVR.h"
17 #include "AVRInstrInfo.h"
18 #include "AVRMachineFunctionInfo.h"
19 #include "AVRTargetMachine.h"
21 
27 #include "llvm/IR/Function.h"
28 
29 #include <vector>
30 
31 namespace llvm {
32 
34  : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 1, -2) {}
35 
37  const MachineFunction &MF) const {
38  // Always simplify call frame pseudo instructions, even when
39  // hasReservedCallFrame is false.
40  return true;
41 }
42 
44  // Reserve call frame memory in function prologue under the following
45  // conditions:
46  // - Y pointer is reserved to be the frame pointer.
47  // - The function does not contain variable sized objects.
48 
49  const MachineFrameInfo &MFI = MF.getFrameInfo();
50  return hasFP(MF) && !MFI.hasVarSizedObjects();
51 }
52 
54  MachineBasicBlock &MBB) const {
56  CallingConv::ID CallConv = MF.getFunction()->getCallingConv();
57  DebugLoc DL = (MBBI != MBB.end()) ? MBBI->getDebugLoc() : DebugLoc();
58  const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
59  const AVRInstrInfo &TII = *STI.getInstrInfo();
60  bool HasFP = hasFP(MF);
61 
62  // Interrupt handlers re-enable interrupts in function entry.
63  if (CallConv == CallingConv::AVR_INTR) {
64  BuildMI(MBB, MBBI, DL, TII.get(AVR::BSETs))
65  .addImm(0x07)
67  }
68 
69  // Save the frame pointer if we have one.
70  if (HasFP) {
71  BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHWRr))
72  .addReg(AVR::R29R28, RegState::Kill)
74  }
75 
76  // Emit special prologue code to save R1, R0 and SREG in interrupt/signal
77  // handlers before saving any other registers.
78  if (CallConv == CallingConv::AVR_INTR ||
79  CallConv == CallingConv::AVR_SIGNAL) {
80  BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHWRr))
81  .addReg(AVR::R1R0, RegState::Kill)
83 
84  BuildMI(MBB, MBBI, DL, TII.get(AVR::INRdA), AVR::R0)
85  .addImm(0x3f)
87  BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr))
88  .addReg(AVR::R0, RegState::Kill)
90  BuildMI(MBB, MBBI, DL, TII.get(AVR::EORRdRr))
91  .addReg(AVR::R0, RegState::Define)
92  .addReg(AVR::R0, RegState::Kill)
93  .addReg(AVR::R0, RegState::Kill)
95  }
96 
97  // Early exit if the frame pointer is not needed in this function.
98  if (!HasFP) {
99  return;
100  }
101 
102  const MachineFrameInfo &MFI = MF.getFrameInfo();
104  unsigned FrameSize = MFI.getStackSize() - AFI->getCalleeSavedFrameSize();
105 
106  // Skip the callee-saved push instructions.
107  while (
108  (MBBI != MBB.end()) && MBBI->getFlag(MachineInstr::FrameSetup) &&
109  (MBBI->getOpcode() == AVR::PUSHRr || MBBI->getOpcode() == AVR::PUSHWRr)) {
110  ++MBBI;
111  }
112 
113  // Update Y with the new base value.
114  BuildMI(MBB, MBBI, DL, TII.get(AVR::SPREAD), AVR::R29R28)
115  .addReg(AVR::SP)
117 
118  // Mark the FramePtr as live-in in every block except the entry.
119  for (MachineFunction::iterator I = std::next(MF.begin()), E = MF.end();
120  I != E; ++I) {
121  I->addLiveIn(AVR::R29R28);
122  }
123 
124  if (!FrameSize) {
125  return;
126  }
127 
128  // Reserve the necessary frame memory by doing FP -= <size>.
129  unsigned Opcode = (isUInt<6>(FrameSize)) ? AVR::SBIWRdK : AVR::SUBIWRdK;
130 
131  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opcode), AVR::R29R28)
132  .addReg(AVR::R29R28, RegState::Kill)
133  .addImm(FrameSize)
135  // The SREG implicit def is dead.
136  MI->getOperand(3).setIsDead();
137 
138  // Write back R29R28 to SP and temporarily disable interrupts.
139  BuildMI(MBB, MBBI, DL, TII.get(AVR::SPWRITE), AVR::SP)
140  .addReg(AVR::R29R28)
142 }
143 
145  MachineBasicBlock &MBB) const {
146  CallingConv::ID CallConv = MF.getFunction()->getCallingConv();
147  bool isHandler = (CallConv == CallingConv::AVR_INTR ||
148  CallConv == CallingConv::AVR_SIGNAL);
149 
150  // Early exit if the frame pointer is not needed in this function except for
151  // signal/interrupt handlers where special code generation is required.
152  if (!hasFP(MF) && !isHandler) {
153  return;
154  }
155 
157  assert(MBBI->getDesc().isReturn() &&
158  "Can only insert epilog into returning blocks");
159 
160  DebugLoc DL = MBBI->getDebugLoc();
161  const MachineFrameInfo &MFI = MF.getFrameInfo();
163  unsigned FrameSize = MFI.getStackSize() - AFI->getCalleeSavedFrameSize();
164  const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
165  const AVRInstrInfo &TII = *STI.getInstrInfo();
166 
167  // Emit special epilogue code to restore R1, R0 and SREG in interrupt/signal
168  // handlers at the very end of the function, just before reti.
169  if (isHandler) {
170  BuildMI(MBB, MBBI, DL, TII.get(AVR::POPRd), AVR::R0);
171  BuildMI(MBB, MBBI, DL, TII.get(AVR::OUTARr))
172  .addImm(0x3f)
173  .addReg(AVR::R0, RegState::Kill);
174  BuildMI(MBB, MBBI, DL, TII.get(AVR::POPWRd), AVR::R1R0);
175  }
176 
177  if (hasFP(MF))
178  BuildMI(MBB, MBBI, DL, TII.get(AVR::POPWRd), AVR::R29R28);
179 
180  // Early exit if there is no need to restore the frame pointer.
181  if (!FrameSize) {
182  return;
183  }
184 
185  // Skip the callee-saved pop instructions.
186  while (MBBI != MBB.begin()) {
187  MachineBasicBlock::iterator PI = std::prev(MBBI);
188  int Opc = PI->getOpcode();
189 
190  if (Opc != AVR::POPRd && Opc != AVR::POPWRd && !PI->isTerminator()) {
191  break;
192  }
193 
194  --MBBI;
195  }
196 
197  unsigned Opcode;
198 
199  // Select the optimal opcode depending on how big it is.
200  if (isUInt<6>(FrameSize)) {
201  Opcode = AVR::ADIWRdK;
202  } else {
203  Opcode = AVR::SUBIWRdK;
204  FrameSize = -FrameSize;
205  }
206 
207  // Restore the frame pointer by doing FP += <size>.
208  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opcode), AVR::R29R28)
209  .addReg(AVR::R29R28, RegState::Kill)
210  .addImm(FrameSize);
211  // The SREG implicit def is dead.
212  MI->getOperand(3).setIsDead();
213 
214  // Write back R29R28 to SP and temporarily disable interrupts.
215  BuildMI(MBB, MBBI, DL, TII.get(AVR::SPWRITE), AVR::SP)
216  .addReg(AVR::R29R28, RegState::Kill);
217 }
218 
219 // Return true if the specified function should have a dedicated frame
220 // pointer register. This is true if the function meets any of the following
221 // conditions:
222 // - a register has been spilled
223 // - has allocas
224 // - input arguments are passed using the stack
225 //
226 // Notice that strictly this is not a frame pointer because it contains SP after
227 // frame allocation instead of having the original SP in function entry.
229  const AVRMachineFunctionInfo *FuncInfo = MF.getInfo<AVRMachineFunctionInfo>();
230 
231  return (FuncInfo->getHasSpills() || FuncInfo->getHasAllocas() ||
232  FuncInfo->getHasStackArgs());
233 }
234 
237  const std::vector<CalleeSavedInfo> &CSI,
238  const TargetRegisterInfo *TRI) const {
239  if (CSI.empty()) {
240  return false;
241  }
242 
243  unsigned CalleeFrameSize = 0;
244  DebugLoc DL = MBB.findDebugLoc(MI);
245  MachineFunction &MF = *MBB.getParent();
246  const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
247  const TargetInstrInfo &TII = *STI.getInstrInfo();
249 
250  for (unsigned i = CSI.size(); i != 0; --i) {
251  unsigned Reg = CSI[i - 1].getReg();
252  bool IsNotLiveIn = !MBB.isLiveIn(Reg);
253 
254  assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 &&
255  "Invalid register size");
256 
257  // Add the callee-saved register as live-in only if it is not already a
258  // live-in register, this usually happens with arguments that are passed
259  // through callee-saved registers.
260  if (IsNotLiveIn) {
261  MBB.addLiveIn(Reg);
262  }
263 
264  // Do not kill the register when it is an input argument.
265  BuildMI(MBB, MI, DL, TII.get(AVR::PUSHRr))
266  .addReg(Reg, getKillRegState(IsNotLiveIn))
267  .setMIFlag(MachineInstr::FrameSetup);
268  ++CalleeFrameSize;
269  }
270 
271  AVRFI->setCalleeSavedFrameSize(CalleeFrameSize);
272 
273  return true;
274 }
275 
278  std::vector<CalleeSavedInfo> &CSI,
279  const TargetRegisterInfo *TRI) const {
280  if (CSI.empty()) {
281  return false;
282  }
283 
284  DebugLoc DL = MBB.findDebugLoc(MI);
285  const MachineFunction &MF = *MBB.getParent();
286  const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
287  const TargetInstrInfo &TII = *STI.getInstrInfo();
288 
289  for (const CalleeSavedInfo &CCSI : CSI) {
290  unsigned Reg = CCSI.getReg();
291 
292  assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 &&
293  "Invalid register size");
294 
295  BuildMI(MBB, MI, DL, TII.get(AVR::POPRd), Reg);
296  }
297 
298  return true;
299 }
300 
301 /// Replace pseudo store instructions that pass arguments through the stack with
302 /// real instructions. If insertPushes is true then all instructions are
303 /// replaced with push instructions, otherwise regular std instructions are
304 /// inserted.
307  const TargetInstrInfo &TII, bool insertPushes) {
308  const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
309  const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
310 
311  // Iterate through the BB until we hit a call instruction or we reach the end.
312  for (auto I = MI, E = MBB.end(); I != E && !I->isCall();) {
313  MachineBasicBlock::iterator NextMI = std::next(I);
314  MachineInstr &MI = *I;
315  unsigned Opcode = I->getOpcode();
316 
317  // Only care of pseudo store instructions where SP is the base pointer.
318  if (Opcode != AVR::STDSPQRr && Opcode != AVR::STDWSPQRr) {
319  I = NextMI;
320  continue;
321  }
322 
323  assert(MI.getOperand(0).getReg() == AVR::SP &&
324  "Invalid register, should be SP!");
325  if (insertPushes) {
326  // Replace this instruction with a push.
327  unsigned SrcReg = MI.getOperand(2).getReg();
328  bool SrcIsKill = MI.getOperand(2).isKill();
329 
330  // We can't use PUSHWRr here because when expanded the order of the new
331  // instructions are reversed from what we need. Perform the expansion now.
332  if (Opcode == AVR::STDWSPQRr) {
333  BuildMI(MBB, I, MI.getDebugLoc(), TII.get(AVR::PUSHRr))
334  .addReg(TRI.getSubReg(SrcReg, AVR::sub_hi),
335  getKillRegState(SrcIsKill));
336  BuildMI(MBB, I, MI.getDebugLoc(), TII.get(AVR::PUSHRr))
337  .addReg(TRI.getSubReg(SrcReg, AVR::sub_lo),
338  getKillRegState(SrcIsKill));
339  } else {
340  BuildMI(MBB, I, MI.getDebugLoc(), TII.get(AVR::PUSHRr))
341  .addReg(SrcReg, getKillRegState(SrcIsKill));
342  }
343 
344  MI.eraseFromParent();
345  I = NextMI;
346  continue;
347  }
348 
349  // Replace this instruction with a regular store. Use Y as the base
350  // pointer since it is guaranteed to contain a copy of SP.
351  unsigned STOpc =
352  (Opcode == AVR::STDWSPQRr) ? AVR::STDWPtrQRr : AVR::STDPtrQRr;
353 
354  MI.setDesc(TII.get(STOpc));
355  MI.getOperand(0).setReg(AVR::R29R28);
356 
357  I = NextMI;
358  }
359 }
360 
364  const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
365  const TargetFrameLowering &TFI = *STI.getFrameLowering();
366  const AVRInstrInfo &TII = *STI.getInstrInfo();
367 
368  // There is nothing to insert when the call frame memory is allocated during
369  // function entry. Delete the call frame pseudo and replace all pseudo stores
370  // with real store instructions.
371  if (TFI.hasReservedCallFrame(MF)) {
372  fixStackStores(MBB, MI, TII, false);
373  return MBB.erase(MI);
374  }
375 
376  DebugLoc DL = MI->getDebugLoc();
377  unsigned int Opcode = MI->getOpcode();
378  int Amount = TII.getFrameSize(*MI);
379 
380  // Adjcallstackup does not need to allocate stack space for the call, instead
381  // we insert push instructions that will allocate the necessary stack.
382  // For adjcallstackdown we convert it into an 'adiw reg, <amt>' handling
383  // the read and write of SP in I/O space.
384  if (Amount != 0) {
385  assert(TFI.getStackAlignment() == 1 && "Unsupported stack alignment");
386 
387  if (Opcode == TII.getCallFrameSetupOpcode()) {
388  fixStackStores(MBB, MI, TII, true);
389  } else {
390  assert(Opcode == TII.getCallFrameDestroyOpcode());
391 
392  // Select the best opcode to adjust SP based on the offset size.
393  unsigned addOpcode;
394  if (isUInt<6>(Amount)) {
395  addOpcode = AVR::ADIWRdK;
396  } else {
397  addOpcode = AVR::SUBIWRdK;
398  Amount = -Amount;
399  }
400 
401  // Build the instruction sequence.
402  BuildMI(MBB, MI, DL, TII.get(AVR::SPREAD), AVR::R31R30).addReg(AVR::SP);
403 
404  MachineInstr *New = BuildMI(MBB, MI, DL, TII.get(addOpcode), AVR::R31R30)
405  .addReg(AVR::R31R30, RegState::Kill)
406  .addImm(Amount);
407  New->getOperand(3).setIsDead();
408 
409  BuildMI(MBB, MI, DL, TII.get(AVR::SPWRITE), AVR::SP)
410  .addReg(AVR::R31R30, RegState::Kill);
411  }
412  }
413 
414  return MBB.erase(MI);
415 }
416 
418  BitVector &SavedRegs,
419  RegScavenger *RS) const {
421 
422  // If we have a frame pointer, the Y register needs to be saved as well.
423  // We don't do that here however - the prologue and epilogue generation
424  // code will handle it specially.
425 }
426 /// The frame analyzer pass.
427 ///
428 /// Scans the function for allocas and used arguments
429 /// that are passed through the stack.
431  static char ID;
433 
435  const MachineFrameInfo &MFI = MF.getFrameInfo();
437 
438  // If there are no fixed frame indexes during this stage it means there
439  // are allocas present in the function.
440  if (MFI.getNumObjects() != MFI.getNumFixedObjects()) {
441  // Check for the type of allocas present in the function. We only care
442  // about fixed size allocas so do not give false positives if only
443  // variable sized allocas are present.
444  for (unsigned i = 0, e = MFI.getObjectIndexEnd(); i != e; ++i) {
445  // Variable sized objects have size 0.
446  if (MFI.getObjectSize(i)) {
447  FuncInfo->setHasAllocas(true);
448  break;
449  }
450  }
451  }
452 
453  // If there are fixed frame indexes present, scan the function to see if
454  // they are really being used.
455  if (MFI.getNumFixedObjects() == 0) {
456  return false;
457  }
458 
459  // Ok fixed frame indexes present, now scan the function to see if they
460  // are really being used, otherwise we can ignore them.
461  for (const MachineBasicBlock &BB : MF) {
462  for (const MachineInstr &MI : BB) {
463  int Opcode = MI.getOpcode();
464 
465  if ((Opcode != AVR::LDDRdPtrQ) && (Opcode != AVR::LDDWRdPtrQ) &&
466  (Opcode != AVR::STDPtrQRr) && (Opcode != AVR::STDWPtrQRr)) {
467  continue;
468  }
469 
470  for (const MachineOperand &MO : MI.operands()) {
471  if (!MO.isFI()) {
472  continue;
473  }
474 
475  if (MFI.isFixedObjectIndex(MO.getIndex())) {
476  FuncInfo->setHasStackArgs(true);
477  return false;
478  }
479  }
480  }
481  }
482 
483  return false;
484  }
485 
486  StringRef getPassName() const { return "AVR Frame Analyzer"; }
487 };
488 
489 char AVRFrameAnalyzer::ID = 0;
490 
491 /// Creates instance of the frame analyzer pass.
493 
494 /// Create the Dynalloca Stack Pointer Save/Restore pass.
495 /// Insert a copy of SP before allocating the dynamic stack memory and restore
496 /// it in function exit to restore the original SP state. This avoids the need
497 /// of reserving a register pair for a frame pointer.
499  static char ID;
501 
503  // Early exit when there are no variable sized objects in the function.
504  if (!MF.getFrameInfo().hasVarSizedObjects()) {
505  return false;
506  }
507 
508  const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
509  const TargetInstrInfo &TII = *STI.getInstrInfo();
510  MachineBasicBlock &EntryMBB = MF.front();
511  MachineBasicBlock::iterator MBBI = EntryMBB.begin();
512  DebugLoc DL = EntryMBB.findDebugLoc(MBBI);
513 
514  unsigned SPCopy =
515  MF.getRegInfo().createVirtualRegister(&AVR::DREGSRegClass);
516 
517  // Create a copy of SP in function entry before any dynallocas are
518  // inserted.
519  BuildMI(EntryMBB, MBBI, DL, TII.get(AVR::COPY), SPCopy).addReg(AVR::SP);
520 
521  // Restore SP in all exit basic blocks.
522  for (MachineBasicBlock &MBB : MF) {
523  // If last instruction is a return instruction, add a restore copy.
524  if (!MBB.empty() && MBB.back().isReturn()) {
525  MBBI = MBB.getLastNonDebugInstr();
526  DL = MBBI->getDebugLoc();
527  BuildMI(MBB, MBBI, DL, TII.get(AVR::COPY), AVR::SP)
528  .addReg(SPCopy, RegState::Kill);
529  }
530  }
531 
532  return true;
533  }
534 
536  return "AVR dynalloca stack pointer save/restore";
537  }
538 };
539 
540 char AVRDynAllocaSR::ID = 0;
541 
542 /// createAVRDynAllocaSRPass - returns an instance of the dynalloca stack
543 /// pointer save/restore pass.
545 
546 } // end of namespace llvm
547 
const AVRInstrInfo * getInstrInfo() const override
Definition: AVRSubtarget.h:42
unsigned getNumFixedObjects() const
Return the number of fixed objects.
bool runOnMachineFunction(MachineFunction &MF)
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Used for AVR interrupt routines.
Definition: CallingConv.h:177
DILocation * get() const
Get the underlying DILocation.
Definition: DebugLoc.cpp:22
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned getNumObjects() const
Return the number of objects.
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:268
unsigned getReg() const
getReg - Returns the register number.
A debug info location.
Definition: DebugLoc.h:34
void setIsDead(bool Val=true)
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
Calling convention used for AVR signal routines.
Definition: CallingConv.h:180
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override
canSimplifyCallFramePseudos - When possible, it&#39;s best to simplify the call frame pseudo ops before d...
Utilities related to the AVR instruction set.
Definition: AVRInstrInfo.h:65
StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
int getObjectIndexEnd() const
Return one past the maximum frame object index.
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
unsigned getKillRegState(bool B)
TargetInstrInfo - Interface to description of machine instruction set.
The frame analyzer pass.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Contains AVR-specific information for each MachineFunction.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE instructions.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MachineBasicBlock & front() const
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
Iterator for intrusive lists based on ilist_node.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:194
MachineOperand class - Representation of each machine instruction operand.
Information about stack frame layout on the target.
void setCalleeSavedFrameSize(unsigned Bytes)
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
A specific AVR target MCU.
Definition: AVRSubtarget.h:32
Representation of each machine instruction.
Definition: MachineInstr.h:59
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static void fixStackStores(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const TargetInstrInfo &TII, bool insertPushes)
Replace pseudo store instructions that pass arguments through the stack with real instructions...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:58
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
FunctionPass * createAVRFrameAnalyzerPass()
Creates instance of the frame analyzer pass.
const TargetFrameLowering * getFrameLowering() const override
Definition: AVRSubtarget.h:43
const AVRRegisterInfo * getRegisterInfo() const override
Definition: AVRSubtarget.h:46
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
FunctionPass * createAVRDynAllocaSRPass()
createAVRDynAllocaSRPass - returns an instance of the dynalloca stack pointer save/restore pass...
bool runOnMachineFunction(MachineFunction &MF)
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Create the Dynalloca Stack Pointer Save/Restore pass.