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AMDGPUTargetTransformInfo.cpp
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1 //===- AMDGPUTargetTransformInfo.cpp - AMDGPU specific TTI pass -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // \file
10 // This file implements a TargetTransformInfo analysis pass specific to the
11 // AMDGPU target machine. It uses the target's detailed information to provide
12 // more precise answers to certain TTI queries, while letting the target
13 // independent and default TTI implementations handle the rest.
14 //
15 //===----------------------------------------------------------------------===//
16 
18 #include "AMDGPUSubtarget.h"
19 #include "Utils/AMDGPUBaseInfo.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/Analysis/LoopInfo.h"
26 #include "llvm/IR/Argument.h"
27 #include "llvm/IR/Attributes.h"
28 #include "llvm/IR/BasicBlock.h"
29 #include "llvm/IR/CallingConv.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/DerivedTypes.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/Instruction.h"
34 #include "llvm/IR/Instructions.h"
35 #include "llvm/IR/IntrinsicInst.h"
36 #include "llvm/IR/Module.h"
37 #include "llvm/IR/PatternMatch.h"
38 #include "llvm/IR/Type.h"
39 #include "llvm/IR/Value.h"
41 #include "llvm/Support/Casting.h"
43 #include "llvm/Support/Debug.h"
48 #include <algorithm>
49 #include <cassert>
50 #include <limits>
51 #include <utility>
52 
53 using namespace llvm;
54 
55 #define DEBUG_TYPE "AMDGPUtti"
56 
58  "amdgpu-unroll-threshold-private",
59  cl::desc("Unroll threshold for AMDGPU if private memory used in a loop"),
60  cl::init(2500), cl::Hidden);
61 
63  "amdgpu-unroll-threshold-local",
64  cl::desc("Unroll threshold for AMDGPU if local memory used in a loop"),
65  cl::init(1000), cl::Hidden);
66 
68  "amdgpu-unroll-threshold-if",
69  cl::desc("Unroll threshold increment for AMDGPU for each if statement inside loop"),
70  cl::init(150), cl::Hidden);
71 
72 static bool dependsOnLocalPhi(const Loop *L, const Value *Cond,
73  unsigned Depth = 0) {
74  const Instruction *I = dyn_cast<Instruction>(Cond);
75  if (!I)
76  return false;
77 
78  for (const Value *V : I->operand_values()) {
79  if (!L->contains(I))
80  continue;
81  if (const PHINode *PHI = dyn_cast<PHINode>(V)) {
82  if (llvm::none_of(L->getSubLoops(), [PHI](const Loop* SubLoop) {
83  return SubLoop->contains(PHI); }))
84  return true;
85  } else if (Depth < 10 && dependsOnLocalPhi(L, V, Depth+1))
86  return true;
87  }
88  return false;
89 }
90 
93  UP.Threshold = 300; // Twice the default.
95  UP.Partial = true;
96 
97  // TODO: Do we want runtime unrolling?
98 
99  // Maximum alloca size than can fit registers. Reserve 16 registers.
100  const unsigned MaxAlloca = (256 - 16) * 4;
101  unsigned ThresholdPrivate = UnrollThresholdPrivate;
102  unsigned ThresholdLocal = UnrollThresholdLocal;
103  unsigned MaxBoost = std::max(ThresholdPrivate, ThresholdLocal);
104  for (const BasicBlock *BB : L->getBlocks()) {
105  const DataLayout &DL = BB->getModule()->getDataLayout();
106  unsigned LocalGEPsSeen = 0;
107 
108  if (llvm::any_of(L->getSubLoops(), [BB](const Loop* SubLoop) {
109  return SubLoop->contains(BB); }))
110  continue; // Block belongs to an inner loop.
111 
112  for (const Instruction &I : *BB) {
113  // Unroll a loop which contains an "if" statement whose condition
114  // defined by a PHI belonging to the loop. This may help to eliminate
115  // if region and potentially even PHI itself, saving on both divergence
116  // and registers used for the PHI.
117  // Add a small bonus for each of such "if" statements.
118  if (const BranchInst *Br = dyn_cast<BranchInst>(&I)) {
119  if (UP.Threshold < MaxBoost && Br->isConditional()) {
120  if (L->isLoopExiting(Br->getSuccessor(0)) ||
121  L->isLoopExiting(Br->getSuccessor(1)))
122  continue;
123  if (dependsOnLocalPhi(L, Br->getCondition())) {
125  LLVM_DEBUG(dbgs() << "Set unroll threshold " << UP.Threshold
126  << " for loop:\n"
127  << *L << " due to " << *Br << '\n');
128  if (UP.Threshold >= MaxBoost)
129  return;
130  }
131  }
132  continue;
133  }
134 
136  if (!GEP)
137  continue;
138 
139  unsigned AS = GEP->getAddressSpace();
140  unsigned Threshold = 0;
141  if (AS == AMDGPUAS::PRIVATE_ADDRESS)
142  Threshold = ThresholdPrivate;
143  else if (AS == AMDGPUAS::LOCAL_ADDRESS)
144  Threshold = ThresholdLocal;
145  else
146  continue;
147 
148  if (UP.Threshold >= Threshold)
149  continue;
150 
151  if (AS == AMDGPUAS::PRIVATE_ADDRESS) {
152  const Value *Ptr = GEP->getPointerOperand();
153  const AllocaInst *Alloca =
155  if (!Alloca || !Alloca->isStaticAlloca())
156  continue;
157  Type *Ty = Alloca->getAllocatedType();
158  unsigned AllocaSize = Ty->isSized() ? DL.getTypeAllocSize(Ty) : 0;
159  if (AllocaSize > MaxAlloca)
160  continue;
161  } else if (AS == AMDGPUAS::LOCAL_ADDRESS) {
162  LocalGEPsSeen++;
163  // Inhibit unroll for local memory if we have seen addressing not to
164  // a variable, most likely we will be unable to combine it.
165  // Do not unroll too deep inner loops for local memory to give a chance
166  // to unroll an outer loop for a more important reason.
167  if (LocalGEPsSeen > 1 || L->getLoopDepth() > 2 ||
168  (!isa<GlobalVariable>(GEP->getPointerOperand()) &&
169  !isa<Argument>(GEP->getPointerOperand())))
170  continue;
171  }
172 
173  // Check if GEP depends on a value defined by this loop itself.
174  bool HasLoopDef = false;
175  for (const Value *Op : GEP->operands()) {
176  const Instruction *Inst = dyn_cast<Instruction>(Op);
177  if (!Inst || L->isLoopInvariant(Op))
178  continue;
179 
180  if (llvm::any_of(L->getSubLoops(), [Inst](const Loop* SubLoop) {
181  return SubLoop->contains(Inst); }))
182  continue;
183  HasLoopDef = true;
184  break;
185  }
186  if (!HasLoopDef)
187  continue;
188 
189  // We want to do whatever we can to limit the number of alloca
190  // instructions that make it through to the code generator. allocas
191  // require us to use indirect addressing, which is slow and prone to
192  // compiler bugs. If this loop does an address calculation on an
193  // alloca ptr, then we want to use a higher than normal loop unroll
194  // threshold. This will give SROA a better chance to eliminate these
195  // allocas.
196  //
197  // We also want to have more unrolling for local memory to let ds
198  // instructions with different offsets combine.
199  //
200  // Don't use the maximum allowed value here as it will make some
201  // programs way too big.
202  UP.Threshold = Threshold;
203  LLVM_DEBUG(dbgs() << "Set unroll threshold " << Threshold
204  << " for loop:\n"
205  << *L << " due to " << *GEP << '\n');
206  if (UP.Threshold >= MaxBoost)
207  return;
208  }
209  }
210 }
211 
213  // The concept of vector registers doesn't really exist. Some packed vector
214  // operations operate on the normal 32-bit registers.
215  return 256;
216 }
217 
218 unsigned GCNTTIImpl::getNumberOfRegisters(bool Vec) const {
219  // This is really the number of registers to fill when vectorizing /
220  // interleaving loops, so we lie to avoid trying to use all registers.
221  return getHardwareNumberOfRegisters(Vec) >> 3;
222 }
223 
224 unsigned GCNTTIImpl::getRegisterBitWidth(bool Vector) const {
225  return 32;
226 }
227 
229  return 32;
230 }
231 
232 unsigned GCNTTIImpl::getLoadVectorFactor(unsigned VF, unsigned LoadSize,
233  unsigned ChainSizeInBytes,
234  VectorType *VecTy) const {
235  unsigned VecRegBitWidth = VF * LoadSize;
236  if (VecRegBitWidth > 128 && VecTy->getScalarSizeInBits() < 32)
237  // TODO: Support element-size less than 32bit?
238  return 128 / LoadSize;
239 
240  return VF;
241 }
242 
243 unsigned GCNTTIImpl::getStoreVectorFactor(unsigned VF, unsigned StoreSize,
244  unsigned ChainSizeInBytes,
245  VectorType *VecTy) const {
246  unsigned VecRegBitWidth = VF * StoreSize;
247  if (VecRegBitWidth > 128)
248  return 128 / StoreSize;
249 
250  return VF;
251 }
252 
253 unsigned GCNTTIImpl::getLoadStoreVecRegBitWidth(unsigned AddrSpace) const {
254  if (AddrSpace == AMDGPUAS::GLOBAL_ADDRESS ||
255  AddrSpace == AMDGPUAS::CONSTANT_ADDRESS ||
256  AddrSpace == AMDGPUAS::CONSTANT_ADDRESS_32BIT ||
257  AddrSpace == AMDGPUAS::BUFFER_FAT_POINTER) {
258  return 512;
259  }
260 
261  if (AddrSpace == AMDGPUAS::FLAT_ADDRESS ||
262  AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
263  AddrSpace == AMDGPUAS::REGION_ADDRESS)
264  return 128;
265 
266  if (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS)
267  return 8 * ST->getMaxPrivateElementSize();
268 
269  llvm_unreachable("unhandled address space");
270 }
271 
272 bool GCNTTIImpl::isLegalToVectorizeMemChain(unsigned ChainSizeInBytes,
273  unsigned Alignment,
274  unsigned AddrSpace) const {
275  // We allow vectorization of flat stores, even though we may need to decompose
276  // them later if they may access private memory. We don't have enough context
277  // here, and legalization can handle it.
278  if (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS) {
279  return (Alignment >= 4 || ST->hasUnalignedScratchAccess()) &&
280  ChainSizeInBytes <= ST->getMaxPrivateElementSize();
281  }
282  return true;
283 }
284 
285 bool GCNTTIImpl::isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes,
286  unsigned Alignment,
287  unsigned AddrSpace) const {
288  return isLegalToVectorizeMemChain(ChainSizeInBytes, Alignment, AddrSpace);
289 }
290 
291 bool GCNTTIImpl::isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes,
292  unsigned Alignment,
293  unsigned AddrSpace) const {
294  return isLegalToVectorizeMemChain(ChainSizeInBytes, Alignment, AddrSpace);
295 }
296 
297 unsigned GCNTTIImpl::getMaxInterleaveFactor(unsigned VF) {
298  // Disable unrolling if the loop is not vectorized.
299  // TODO: Enable this again.
300  if (VF == 1)
301  return 1;
302 
303  return 8;
304 }
305 
307  MemIntrinsicInfo &Info) const {
308  switch (Inst->getIntrinsicID()) {
309  case Intrinsic::amdgcn_atomic_inc:
310  case Intrinsic::amdgcn_atomic_dec:
311  case Intrinsic::amdgcn_ds_ordered_add:
312  case Intrinsic::amdgcn_ds_ordered_swap:
313  case Intrinsic::amdgcn_ds_fadd:
314  case Intrinsic::amdgcn_ds_fmin:
315  case Intrinsic::amdgcn_ds_fmax: {
316  auto *Ordering = dyn_cast<ConstantInt>(Inst->getArgOperand(2));
317  auto *Volatile = dyn_cast<ConstantInt>(Inst->getArgOperand(4));
318  if (!Ordering || !Volatile)
319  return false; // Invalid.
320 
321  unsigned OrderingVal = Ordering->getZExtValue();
322  if (OrderingVal > static_cast<unsigned>(AtomicOrdering::SequentiallyConsistent))
323  return false;
324 
325  Info.PtrVal = Inst->getArgOperand(0);
326  Info.Ordering = static_cast<AtomicOrdering>(OrderingVal);
327  Info.ReadMem = true;
328  Info.WriteMem = true;
329  Info.IsVolatile = !Volatile->isNullValue();
330  return true;
331  }
332  default:
333  return false;
334  }
335 }
336 
338  unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info,
339  TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo,
341  EVT OrigTy = TLI->getValueType(DL, Ty);
342  if (!OrigTy.isSimple()) {
343  return BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
344  Opd1PropInfo, Opd2PropInfo);
345  }
346 
347  // Legalize the type.
348  std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
349  int ISD = TLI->InstructionOpcodeToISD(Opcode);
350 
351  // Because we don't have any legal vector operations, but the legal types, we
352  // need to account for split vectors.
353  unsigned NElts = LT.second.isVector() ?
354  LT.second.getVectorNumElements() : 1;
355 
356  MVT::SimpleValueType SLT = LT.second.getScalarType().SimpleTy;
357 
358  switch (ISD) {
359  case ISD::SHL:
360  case ISD::SRL:
361  case ISD::SRA:
362  if (SLT == MVT::i64)
363  return get64BitInstrCost() * LT.first * NElts;
364 
365  // i32
366  return getFullRateInstrCost() * LT.first * NElts;
367  case ISD::ADD:
368  case ISD::SUB:
369  case ISD::AND:
370  case ISD::OR:
371  case ISD::XOR:
372  if (SLT == MVT::i64){
373  // and, or and xor are typically split into 2 VALU instructions.
374  return 2 * getFullRateInstrCost() * LT.first * NElts;
375  }
376 
377  return LT.first * NElts * getFullRateInstrCost();
378  case ISD::MUL: {
379  const int QuarterRateCost = getQuarterRateInstrCost();
380  if (SLT == MVT::i64) {
381  const int FullRateCost = getFullRateInstrCost();
382  return (4 * QuarterRateCost + (2 * 2) * FullRateCost) * LT.first * NElts;
383  }
384 
385  // i32
386  return QuarterRateCost * NElts * LT.first;
387  }
388  case ISD::FADD:
389  case ISD::FSUB:
390  case ISD::FMUL:
391  if (SLT == MVT::f64)
392  return LT.first * NElts * get64BitInstrCost();
393 
394  if (SLT == MVT::f32 || SLT == MVT::f16)
395  return LT.first * NElts * getFullRateInstrCost();
396  break;
397  case ISD::FDIV:
398  case ISD::FREM:
399  // FIXME: frem should be handled separately. The fdiv in it is most of it,
400  // but the current lowering is also not entirely correct.
401  if (SLT == MVT::f64) {
402  int Cost = 4 * get64BitInstrCost() + 7 * getQuarterRateInstrCost();
403  // Add cost of workaround.
404  if (ST->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS)
405  Cost += 3 * getFullRateInstrCost();
406 
407  return LT.first * Cost * NElts;
408  }
409 
410  if (!Args.empty() && match(Args[0], PatternMatch::m_FPOne())) {
411  // TODO: This is more complicated, unsafe flags etc.
412  if ((SLT == MVT::f32 && !ST->hasFP32Denormals()) ||
413  (SLT == MVT::f16 && ST->has16BitInsts())) {
414  return LT.first * getQuarterRateInstrCost() * NElts;
415  }
416  }
417 
418  if (SLT == MVT::f16 && ST->has16BitInsts()) {
419  // 2 x v_cvt_f32_f16
420  // f32 rcp
421  // f32 fmul
422  // v_cvt_f16_f32
423  // f16 div_fixup
424  int Cost = 4 * getFullRateInstrCost() + 2 * getQuarterRateInstrCost();
425  return LT.first * Cost * NElts;
426  }
427 
428  if (SLT == MVT::f32 || SLT == MVT::f16) {
429  int Cost = 7 * getFullRateInstrCost() + 1 * getQuarterRateInstrCost();
430 
431  if (!ST->hasFP32Denormals()) {
432  // FP mode switches.
433  Cost += 2 * getFullRateInstrCost();
434  }
435 
436  return LT.first * NElts * Cost;
437  }
438  break;
439  default:
440  break;
441  }
442 
443  return BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
444  Opd1PropInfo, Opd2PropInfo);
445 }
446 
447 unsigned GCNTTIImpl::getCFInstrCost(unsigned Opcode) {
448  // XXX - For some reason this isn't called for switch.
449  switch (Opcode) {
450  case Instruction::Br:
451  case Instruction::Ret:
452  return 10;
453  default:
454  return BaseT::getCFInstrCost(Opcode);
455  }
456 }
457 
459  bool IsPairwise) {
460  EVT OrigTy = TLI->getValueType(DL, Ty);
461 
462  // Computes cost on targets that have packed math instructions(which support
463  // 16-bit types only).
464  if (IsPairwise ||
465  !ST->hasVOP3PInsts() ||
466  OrigTy.getScalarSizeInBits() != 16)
467  return BaseT::getArithmeticReductionCost(Opcode, Ty, IsPairwise);
468 
469  std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
470  return LT.first * getFullRateInstrCost();
471 }
472 
474  bool IsPairwise,
475  bool IsUnsigned) {
476  EVT OrigTy = TLI->getValueType(DL, Ty);
477 
478  // Computes cost on targets that have packed math instructions(which support
479  // 16-bit types only).
480  if (IsPairwise ||
481  !ST->hasVOP3PInsts() ||
482  OrigTy.getScalarSizeInBits() != 16)
483  return BaseT::getMinMaxReductionCost(Ty, CondTy, IsPairwise, IsUnsigned);
484 
485  std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
486  return LT.first * getHalfRateInstrCost();
487 }
488 
489 int GCNTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy,
490  unsigned Index) {
491  switch (Opcode) {
492  case Instruction::ExtractElement:
493  case Instruction::InsertElement: {
494  unsigned EltSize
495  = DL.getTypeSizeInBits(cast<VectorType>(ValTy)->getElementType());
496  if (EltSize < 32) {
497  if (EltSize == 16 && Index == 0 && ST->has16BitInsts())
498  return 0;
499  return BaseT::getVectorInstrCost(Opcode, ValTy, Index);
500  }
501 
502  // Extracts are just reads of a subregister, so are free. Inserts are
503  // considered free because we don't want to have any cost for scalarizing
504  // operations, and we don't have to copy into a different register class.
505 
506  // Dynamic indexing isn't free and is best avoided.
507  return Index == ~0u ? 2 : 0;
508  }
509  default:
510  return BaseT::getVectorInstrCost(Opcode, ValTy, Index);
511  }
512 }
513 
514 
515 
516 static bool isArgPassedInSGPR(const Argument *A) {
517  const Function *F = A->getParent();
518 
519  // Arguments to compute shaders are never a source of divergence.
521  switch (CC) {
524  return true;
532  // For non-compute shaders, SGPR inputs are marked with either inreg or byval.
533  // Everything else is in VGPRs.
534  return F->getAttributes().hasParamAttribute(A->getArgNo(), Attribute::InReg) ||
535  F->getAttributes().hasParamAttribute(A->getArgNo(), Attribute::ByVal);
536  default:
537  // TODO: Should calls support inreg for SGPR inputs?
538  return false;
539  }
540 }
541 
542 /// \returns true if the result of the value could potentially be
543 /// different across workitems in a wavefront.
545  if (const Argument *A = dyn_cast<Argument>(V))
546  return !isArgPassedInSGPR(A);
547 
548  // Loads from the private and flat address spaces are divergent, because
549  // threads can execute the load instruction with the same inputs and get
550  // different results.
551  //
552  // All other loads are not divergent, because if threads issue loads with the
553  // same arguments, they will always get the same result.
554  if (const LoadInst *Load = dyn_cast<LoadInst>(V))
555  return Load->getPointerAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS ||
556  Load->getPointerAddressSpace() == AMDGPUAS::FLAT_ADDRESS;
557 
558  // Atomics are divergent because they are executed sequentially: when an
559  // atomic operation refers to the same address in each thread, then each
560  // thread after the first sees the value written by the previous thread as
561  // original value.
562  if (isa<AtomicRMWInst>(V) || isa<AtomicCmpXchgInst>(V))
563  return true;
564 
565  if (const IntrinsicInst *Intrinsic = dyn_cast<IntrinsicInst>(V))
566  return AMDGPU::isIntrinsicSourceOfDivergence(Intrinsic->getIntrinsicID());
567 
568  // Assume all function calls are a source of divergence.
569  if (isa<CallInst>(V) || isa<InvokeInst>(V))
570  return true;
571 
572  return false;
573 }
574 
575 bool GCNTTIImpl::isAlwaysUniform(const Value *V) const {
576  if (const IntrinsicInst *Intrinsic = dyn_cast<IntrinsicInst>(V)) {
577  switch (Intrinsic->getIntrinsicID()) {
578  default:
579  return false;
580  case Intrinsic::amdgcn_readfirstlane:
581  case Intrinsic::amdgcn_readlane:
582  case Intrinsic::amdgcn_icmp:
583  case Intrinsic::amdgcn_fcmp:
584  return true;
585  }
586  }
587  return false;
588 }
589 
591  Type *SubTp) {
592  if (ST->hasVOP3PInsts()) {
593  VectorType *VT = cast<VectorType>(Tp);
594  if (VT->getNumElements() == 2 &&
595  DL.getTypeSizeInBits(VT->getElementType()) == 16) {
596  // With op_sel VOP3P instructions freely can access the low half or high
597  // half of a register, so any swizzle is free.
598 
599  switch (Kind) {
600  case TTI::SK_Broadcast:
601  case TTI::SK_Reverse:
603  return 0;
604  default:
605  break;
606  }
607  }
608  }
609 
610  return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
611 }
612 
614  const Function *Callee) const {
615  const TargetMachine &TM = getTLI()->getTargetMachine();
616  const FeatureBitset &CallerBits =
617  TM.getSubtargetImpl(*Caller)->getFeatureBits();
618  const FeatureBitset &CalleeBits =
619  TM.getSubtargetImpl(*Callee)->getFeatureBits();
620 
621  FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList;
622  FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList;
623  return ((RealCallerBits & RealCalleeBits) == RealCalleeBits);
624 }
625 
628  CommonTTI.getUnrollingPreferences(L, SE, UP);
629 }
630 
632  return 4 * 128; // XXX - 4 channels. Should these count as vector instead?
633 }
634 
635 unsigned R600TTIImpl::getNumberOfRegisters(bool Vec) const {
636  return getHardwareNumberOfRegisters(Vec);
637 }
638 
639 unsigned R600TTIImpl::getRegisterBitWidth(bool Vector) const {
640  return 32;
641 }
642 
644  return 32;
645 }
646 
647 unsigned R600TTIImpl::getLoadStoreVecRegBitWidth(unsigned AddrSpace) const {
648  if (AddrSpace == AMDGPUAS::GLOBAL_ADDRESS ||
649  AddrSpace == AMDGPUAS::CONSTANT_ADDRESS)
650  return 128;
651  if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
652  AddrSpace == AMDGPUAS::REGION_ADDRESS)
653  return 64;
654  if (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS)
655  return 32;
656 
657  if ((AddrSpace == AMDGPUAS::PARAM_D_ADDRESS ||
658  AddrSpace == AMDGPUAS::PARAM_I_ADDRESS ||
659  (AddrSpace >= AMDGPUAS::CONSTANT_BUFFER_0 &&
660  AddrSpace <= AMDGPUAS::CONSTANT_BUFFER_15)))
661  return 128;
662  llvm_unreachable("unhandled address space");
663 }
664 
665 bool R600TTIImpl::isLegalToVectorizeMemChain(unsigned ChainSizeInBytes,
666  unsigned Alignment,
667  unsigned AddrSpace) const {
668  // We allow vectorization of flat stores, even though we may need to decompose
669  // them later if they may access private memory. We don't have enough context
670  // here, and legalization can handle it.
671  return (AddrSpace != AMDGPUAS::PRIVATE_ADDRESS);
672 }
673 
674 bool R600TTIImpl::isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes,
675  unsigned Alignment,
676  unsigned AddrSpace) const {
677  return isLegalToVectorizeMemChain(ChainSizeInBytes, Alignment, AddrSpace);
678 }
679 
680 bool R600TTIImpl::isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes,
681  unsigned Alignment,
682  unsigned AddrSpace) const {
683  return isLegalToVectorizeMemChain(ChainSizeInBytes, Alignment, AddrSpace);
684 }
685 
686 unsigned R600TTIImpl::getMaxInterleaveFactor(unsigned VF) {
687  // Disable unrolling if the loop is not vectorized.
688  // TODO: Enable this again.
689  if (VF == 1)
690  return 1;
691 
692  return 8;
693 }
694 
695 unsigned R600TTIImpl::getCFInstrCost(unsigned Opcode) {
696  // XXX - For some reason this isn't called for switch.
697  switch (Opcode) {
698  case Instruction::Br:
699  case Instruction::Ret:
700  return 10;
701  default:
702  return BaseT::getCFInstrCost(Opcode);
703  }
704 }
705 
706 int R600TTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy,
707  unsigned Index) {
708  switch (Opcode) {
709  case Instruction::ExtractElement:
710  case Instruction::InsertElement: {
711  unsigned EltSize
712  = DL.getTypeSizeInBits(cast<VectorType>(ValTy)->getElementType());
713  if (EltSize < 32) {
714  return BaseT::getVectorInstrCost(Opcode, ValTy, Index);
715  }
716 
717  // Extracts are just reads of a subregister, so are free. Inserts are
718  // considered free because we don't want to have any cost for scalarizing
719  // operations, and we don't have to copy into a different register class.
720 
721  // Dynamic indexing isn't free and is best avoided.
722  return Index == ~0u ? 2 : 0;
723  }
724  default:
725  return BaseT::getVectorInstrCost(Opcode, ValTy, Index);
726  }
727 }
728 
731  CommonTTI.getUnrollingPreferences(L, SE, UP);
732 }
Address space for global memory (RAT0, VTX0).
Definition: AMDGPU.h:251
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
bool Partial
Allow partial unrolling (unrolling of loops to expand the size of the loop body, not only to eliminat...
unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >())
Definition: BasicTTIImpl.h:567
bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const
This file a TargetTransformInfo::Concept conforming object specific to the AMDGPU target machine...
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
AMDGPU specific subclass of TargetSubtarget.
Address space for constant memory (VTX2).
Definition: AMDGPU.h:254
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isSized(SmallPtrSetImpl< Type *> *Visited=nullptr) const
Return true if it makes sense to take the size of this type.
Definition: Type.h:264
static cl::opt< unsigned > UnrollThresholdIf("amdgpu-unroll-threshold-if", cl::desc("Unroll threshold increment for AMDGPU for each if statement inside loop"), cl::init(150), cl::Hidden)
unsigned getCFInstrCost(unsigned Opcode)
unsigned getLoopDepth() const
Return the nesting level of this loop.
Definition: LoopInfo.h:91
The main scalar evolution driver.
bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const
int getVectorInstrCost(unsigned Opcode, Type *ValTy, unsigned Index)
unsigned getMinVectorRegisterBitWidth() const
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP)
F(f)
An instruction for reading from memory.
Definition: Instructions.h:167
int getArithmeticReductionCost(unsigned Opcode, Type *Ty, bool IsPairwise)
Hexagon Common GEP
Address space for flat memory.
Definition: AMDGPU.h:250
SPIR_KERNEL - Calling convention for SPIR kernel functions.
Definition: CallingConv.h:136
Value * getArgOperand(unsigned i) const
Definition: InstrTypes.h:1155
bool match(Val *V, const Pattern &P)
Definition: PatternMatch.h:47
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
const FeatureBitset & getFeatureBits() const
bool isAlwaysUniform(const Value *V) const
Shift and rotation operations.
Definition: ISDOpcodes.h:409
unsigned getNumberOfRegisters(bool Vector) const
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1199
This file contains the simple types necessary to represent the attributes associated with functions a...
unsigned getArithmeticReductionCost(unsigned Opcode, Type *Ty, bool IsPairwise)
Try to calculate arithmetic and shuffle op costs for reduction operations.
uint64_t getNumElements() const
Definition: DerivedTypes.h:390
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
unsigned getScalarSizeInBits() const
Definition: ValueTypes.h:297
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
unsigned getRegisterBitWidth(bool Vector) const
unsigned getMaxInterleaveFactor(unsigned VF)
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:223
static bool dependsOnLocalPhi(const Loop *L, const Value *Cond, unsigned Depth=0)
Reverse the order of the vector.
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
unsigned getAddressSpace() const
Returns the address space of this instruction&#39;s pointer type.
Definition: Instructions.h:982
unsigned getCFInstrCost(unsigned Opcode)
Address space for 32-bit constant memory.
Definition: AMDGPU.h:258
an instruction for type-safe pointer arithmetic to access elements of arrays and structs ...
Definition: Instructions.h:873
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:423
Calling convention used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:194
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:148
Calling convention for AMDGPU code object kernels.
Definition: CallingConv.h:200
Container class for subtarget features.
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
bool isLoopExiting(const BlockT *BB) const
True if terminator in the block can branch to another block that is outside of the current loop...
Definition: LoopInfo.h:202
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
Simple binary floating point operators.
Definition: ISDOpcodes.h:282
Conditional or Unconditional Branch instruction.
unsigned getMinMaxReductionCost(Type *Ty, Type *CondTy, bool IsPairwise, bool)
Try to calculate op costs for min/max reduction operations.
Address space for private memory.
Definition: AMDGPU.h:256
bool isIntrinsicSourceOfDivergence(unsigned IntrID)
unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1192
unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp)
unsigned getNumberOfRegisters(bool Vec) const
op_range operands()
Definition: User.h:237
Address space for region memory. (GDS)
Definition: AMDGPU.h:252
static bool isArgPassedInSGPR(const Argument *A)
Extended Value Type.
Definition: ValueTypes.h:33
unsigned getHardwareNumberOfRegisters(bool Vec) const
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
Value * GetUnderlyingObject(Value *V, const DataLayout &DL, unsigned MaxLookup=6)
This method strips off any GEP address adjustments and pointer casts from the specified value...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Address space for local memory.
Definition: AMDGPU.h:255
Type * getAllocatedType() const
Return the type that is being allocated by the instruction.
Definition: Instructions.h:105
bool isLoopInvariant(const Value *V) const
Return true if the specified value is loop invariant.
Definition: LoopInfo.cpp:57
OperandValueProperties
Additional properties of an operand&#39;s values.
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:50
unsigned getCFInstrCost(unsigned Opcode)
Definition: BasicTTIImpl.h:766
unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp)
Definition: BasicTTIImpl.h:614
bool contains(const LoopT *L) const
Return true if the specified loop is contained within in this loop.
Definition: LoopInfo.h:109
unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Calling convention used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
Definition: CallingConv.h:207
bool hasParamAttribute(unsigned ArgNo, Attribute::AttrKind Kind) const
Equivalent to hasAttribute(ArgNo + FirstArgIndex, Kind).
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
bool isSourceOfDivergence(const Value *V) const
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type...
Definition: Type.cpp:129
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
Module.h This file contains the declarations for the Module class.
int getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value *> Args=ArrayRef< const Value *>())
int getMinMaxReductionCost(Type *Ty, Type *CondTy, bool IsPairwiseForm, bool IsUnsigned)
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const
Calling convention used for AMDPAL shader stage before geometry shader if geometry is in use...
Definition: CallingConv.h:220
virtual const TargetSubtargetInfo * getSubtargetImpl(const Function &) const
Virtual method implemented by subclasses that returns a reference to that target&#39;s TargetSubtargetInf...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
unsigned getMaxInterleaveFactor(unsigned VF)
Class to represent vector types.
Definition: DerivedTypes.h:424
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
unsigned getArgNo() const
Return the index of this formal argument in its containing function.
Definition: Argument.h:47
static cl::opt< unsigned > Threshold("loop-unswitch-threshold", cl::desc("Max loop size to unswitch"), cl::init(100), cl::Hidden)
int getVectorInstrCost(unsigned Opcode, Type *ValTy, unsigned Index)
uint64_t getTypeSizeInBits(Type *Ty) const
Size examples:
Definition: DataLayout.h:593
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:461
const std::vector< LoopT * > & getSubLoops() const
Return the loops contained entirely within this loop.
Definition: LoopInfo.h:130
specific_fpval m_FPOne()
Match a float 1.0 or vector with all elements equal to 1.0.
Definition: PatternMatch.h:542
Calling convention used for AMDPAL vertex shader if tessellation is in use.
Definition: CallingConv.h:215
Calling convention used for Mesa vertex shaders, or AMDPAL last shader stage before rasterization (ve...
Definition: CallingConv.h:188
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:386
unsigned Threshold
The cost threshold for the unrolled loop.
const Function * getParent() const
Definition: Argument.h:41
Address space for 160-bit buffer fat pointers.
Definition: AMDGPU.h:260
Calling convention used for Mesa/AMDPAL compute shaders.
Definition: CallingConv.h:197
unsigned getHardwareNumberOfRegisters(bool Vector) const
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:464
ArrayRef< BlockT * > getBlocks() const
Get a list of the basic blocks which make up this loop.
Definition: LoopInfo.h:148
Parameters that control the generic loop unrolling transformation.
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP)
#define I(x, y, z)
Definition: MD5.cpp:58
iterator_range< value_op_iterator > operand_values()
Definition: User.h:261
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:322
unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
Definition: BasicTTIImpl.h:811
static cl::opt< unsigned > UnrollThresholdLocal("amdgpu-unroll-threshold-local", cl::desc("Unroll threshold for AMDGPU if local memory used in a loop"), cl::init(1000), cl::Hidden)
LLVM Value Representation.
Definition: Value.h:72
static cl::opt< unsigned > UnrollThresholdPrivate("amdgpu-unroll-threshold-private", cl::desc("Unroll threshold for AMDGPU if private memory used in a loop"), cl::init(2500), cl::Hidden)
Broadcast element 0 to all other elements.
unsigned getMinVectorRegisterBitWidth() const
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
Type * getElementType() const
Definition: DerivedTypes.h:391
Value * PtrVal
This is the pointer that the intrinsic is loading from or storing to.
OperandValueKind
Additional information about an operand&#39;s possible values.
This pass exposes codegen information to IR-level passes.
bool isStaticAlloca() const
Return true if this alloca is in the entry block of the function and is a constant size...
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:125
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP)
#define LLVM_DEBUG(X)
Definition: Debug.h:122
Calling convention used for Mesa/AMDPAL geometry shaders.
Definition: CallingConv.h:191
Information about a load/store intrinsic defined by the target.
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
unsigned getRegisterBitWidth(bool Vector) const
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:143
Address space for direct addressible parameter memory (CONST0).
Definition: AMDGPU.h:263
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:43
Address space for indirect addressible parameter memory (VTX1).
Definition: AMDGPU.h:265
an instruction to allocate memory on the stack
Definition: Instructions.h:59
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Shuffle elements of single source vector with any shuffle mask.