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AMDGPUTargetTransformInfo.cpp
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1 //===- AMDGPUTargetTransformInfo.cpp - AMDGPU specific TTI pass -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // \file
11 // This file implements a TargetTransformInfo analysis pass specific to the
12 // AMDGPU target machine. It uses the target's detailed information to provide
13 // more precise answers to certain TTI queries, while letting the target
14 // independent and default TTI implementations handle the rest.
15 //
16 //===----------------------------------------------------------------------===//
17 
19 #include "AMDGPUSubtarget.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/Analysis/LoopInfo.h"
27 #include "llvm/IR/Argument.h"
28 #include "llvm/IR/Attributes.h"
29 #include "llvm/IR/BasicBlock.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/DataLayout.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/Instruction.h"
35 #include "llvm/IR/Instructions.h"
36 #include "llvm/IR/IntrinsicInst.h"
37 #include "llvm/IR/Module.h"
38 #include "llvm/IR/PatternMatch.h"
39 #include "llvm/IR/Type.h"
40 #include "llvm/IR/Value.h"
42 #include "llvm/Support/Casting.h"
44 #include "llvm/Support/Debug.h"
48 #include <algorithm>
49 #include <cassert>
50 #include <limits>
51 #include <utility>
52 
53 using namespace llvm;
54 
55 #define DEBUG_TYPE "AMDGPUtti"
56 
58  "amdgpu-unroll-threshold-private",
59  cl::desc("Unroll threshold for AMDGPU if private memory used in a loop"),
60  cl::init(2500), cl::Hidden);
61 
63  "amdgpu-unroll-threshold-local",
64  cl::desc("Unroll threshold for AMDGPU if local memory used in a loop"),
65  cl::init(1000), cl::Hidden);
66 
68  "amdgpu-unroll-threshold-if",
69  cl::desc("Unroll threshold increment for AMDGPU for each if statement inside loop"),
70  cl::init(150), cl::Hidden);
71 
72 static bool dependsOnLocalPhi(const Loop *L, const Value *Cond,
73  unsigned Depth = 0) {
74  const Instruction *I = dyn_cast<Instruction>(Cond);
75  if (!I)
76  return false;
77 
78  for (const Value *V : I->operand_values()) {
79  if (!L->contains(I))
80  continue;
81  if (const PHINode *PHI = dyn_cast<PHINode>(V)) {
82  if (llvm::none_of(L->getSubLoops(), [PHI](const Loop* SubLoop) {
83  return SubLoop->contains(PHI); }))
84  return true;
85  } else if (Depth < 10 && dependsOnLocalPhi(L, V, Depth+1))
86  return true;
87  }
88  return false;
89 }
90 
93  UP.Threshold = 300; // Twice the default.
95  UP.Partial = true;
96 
97  // TODO: Do we want runtime unrolling?
98 
99  // Maximum alloca size than can fit registers. Reserve 16 registers.
100  const unsigned MaxAlloca = (256 - 16) * 4;
101  unsigned ThresholdPrivate = UnrollThresholdPrivate;
102  unsigned ThresholdLocal = UnrollThresholdLocal;
103  unsigned MaxBoost = std::max(ThresholdPrivate, ThresholdLocal);
104  AMDGPUAS ASST = ST->getAMDGPUAS();
105  for (const BasicBlock *BB : L->getBlocks()) {
106  const DataLayout &DL = BB->getModule()->getDataLayout();
107  unsigned LocalGEPsSeen = 0;
108 
109  if (llvm::any_of(L->getSubLoops(), [BB](const Loop* SubLoop) {
110  return SubLoop->contains(BB); }))
111  continue; // Block belongs to an inner loop.
112 
113  for (const Instruction &I : *BB) {
114  // Unroll a loop which contains an "if" statement whose condition
115  // defined by a PHI belonging to the loop. This may help to eliminate
116  // if region and potentially even PHI itself, saving on both divergence
117  // and registers used for the PHI.
118  // Add a small bonus for each of such "if" statements.
119  if (const BranchInst *Br = dyn_cast<BranchInst>(&I)) {
120  if (UP.Threshold < MaxBoost && Br->isConditional()) {
121  if (L->isLoopExiting(Br->getSuccessor(0)) ||
122  L->isLoopExiting(Br->getSuccessor(1)))
123  continue;
124  if (dependsOnLocalPhi(L, Br->getCondition())) {
126  DEBUG(dbgs() << "Set unroll threshold " << UP.Threshold
127  << " for loop:\n" << *L << " due to " << *Br << '\n');
128  if (UP.Threshold >= MaxBoost)
129  return;
130  }
131  }
132  continue;
133  }
134 
136  if (!GEP)
137  continue;
138 
139  unsigned AS = GEP->getAddressSpace();
140  unsigned Threshold = 0;
141  if (AS == ASST.PRIVATE_ADDRESS)
142  Threshold = ThresholdPrivate;
143  else if (AS == ASST.LOCAL_ADDRESS)
144  Threshold = ThresholdLocal;
145  else
146  continue;
147 
148  if (UP.Threshold >= Threshold)
149  continue;
150 
151  if (AS == ASST.PRIVATE_ADDRESS) {
152  const Value *Ptr = GEP->getPointerOperand();
153  const AllocaInst *Alloca =
155  if (!Alloca || !Alloca->isStaticAlloca())
156  continue;
157  Type *Ty = Alloca->getAllocatedType();
158  unsigned AllocaSize = Ty->isSized() ? DL.getTypeAllocSize(Ty) : 0;
159  if (AllocaSize > MaxAlloca)
160  continue;
161  } else if (AS == ASST.LOCAL_ADDRESS) {
162  LocalGEPsSeen++;
163  // Inhibit unroll for local memory if we have seen addressing not to
164  // a variable, most likely we will be unable to combine it.
165  // Do not unroll too deep inner loops for local memory to give a chance
166  // to unroll an outer loop for a more important reason.
167  if (LocalGEPsSeen > 1 || L->getLoopDepth() > 2 ||
168  (!isa<GlobalVariable>(GEP->getPointerOperand()) &&
169  !isa<Argument>(GEP->getPointerOperand())))
170  continue;
171  }
172 
173  // Check if GEP depends on a value defined by this loop itself.
174  bool HasLoopDef = false;
175  for (const Value *Op : GEP->operands()) {
176  const Instruction *Inst = dyn_cast<Instruction>(Op);
177  if (!Inst || L->isLoopInvariant(Op))
178  continue;
179 
180  if (llvm::any_of(L->getSubLoops(), [Inst](const Loop* SubLoop) {
181  return SubLoop->contains(Inst); }))
182  continue;
183  HasLoopDef = true;
184  break;
185  }
186  if (!HasLoopDef)
187  continue;
188 
189  // We want to do whatever we can to limit the number of alloca
190  // instructions that make it through to the code generator. allocas
191  // require us to use indirect addressing, which is slow and prone to
192  // compiler bugs. If this loop does an address calculation on an
193  // alloca ptr, then we want to use a higher than normal loop unroll
194  // threshold. This will give SROA a better chance to eliminate these
195  // allocas.
196  //
197  // We also want to have more unrolling for local memory to let ds
198  // instructions with different offsets combine.
199  //
200  // Don't use the maximum allowed value here as it will make some
201  // programs way too big.
202  UP.Threshold = Threshold;
203  DEBUG(dbgs() << "Set unroll threshold " << Threshold << " for loop:\n"
204  << *L << " due to " << *GEP << '\n');
205  if (UP.Threshold >= MaxBoost)
206  return;
207  }
208  }
209 }
210 
212  // The concept of vector registers doesn't really exist. Some packed vector
213  // operations operate on the normal 32-bit registers.
214 
215  // Number of VGPRs on SI.
217  return 256;
218 
219  return 4 * 128; // XXX - 4 channels. Should these count as vector instead?
220 }
221 
222 unsigned AMDGPUTTIImpl::getNumberOfRegisters(bool Vec) const {
223  // This is really the number of registers to fill when vectorizing /
224  // interleaving loops, so we lie to avoid trying to use all registers.
225  return getHardwareNumberOfRegisters(Vec) >> 3;
226 }
227 
228 unsigned AMDGPUTTIImpl::getRegisterBitWidth(bool Vector) const {
229  return 32;
230 }
231 
233  return 32;
234 }
235 
236 unsigned AMDGPUTTIImpl::getLoadStoreVecRegBitWidth(unsigned AddrSpace) const {
237  AMDGPUAS AS = ST->getAMDGPUAS();
238  if (AddrSpace == AS.GLOBAL_ADDRESS ||
239  AddrSpace == AS.CONSTANT_ADDRESS ||
240  AddrSpace == AS.FLAT_ADDRESS)
241  return 128;
242  if (AddrSpace == AS.LOCAL_ADDRESS ||
243  AddrSpace == AS.REGION_ADDRESS)
244  return 64;
245  if (AddrSpace == AS.PRIVATE_ADDRESS)
246  return 8 * ST->getMaxPrivateElementSize();
247 
249  (AddrSpace == AS.PARAM_D_ADDRESS ||
250  AddrSpace == AS.PARAM_I_ADDRESS ||
251  (AddrSpace >= AS.CONSTANT_BUFFER_0 &&
252  AddrSpace <= AS.CONSTANT_BUFFER_15)))
253  return 128;
254  llvm_unreachable("unhandled address space");
255 }
256 
257 bool AMDGPUTTIImpl::isLegalToVectorizeMemChain(unsigned ChainSizeInBytes,
258  unsigned Alignment,
259  unsigned AddrSpace) const {
260  // We allow vectorization of flat stores, even though we may need to decompose
261  // them later if they may access private memory. We don't have enough context
262  // here, and legalization can handle it.
263  if (AddrSpace == ST->getAMDGPUAS().PRIVATE_ADDRESS) {
264  return (Alignment >= 4 || ST->hasUnalignedScratchAccess()) &&
265  ChainSizeInBytes <= ST->getMaxPrivateElementSize();
266  }
267  return true;
268 }
269 
270 bool AMDGPUTTIImpl::isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes,
271  unsigned Alignment,
272  unsigned AddrSpace) const {
273  return isLegalToVectorizeMemChain(ChainSizeInBytes, Alignment, AddrSpace);
274 }
275 
276 bool AMDGPUTTIImpl::isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes,
277  unsigned Alignment,
278  unsigned AddrSpace) const {
279  return isLegalToVectorizeMemChain(ChainSizeInBytes, Alignment, AddrSpace);
280 }
281 
283  // Disable unrolling if the loop is not vectorized.
284  // TODO: Enable this again.
285  if (VF == 1)
286  return 1;
287 
288  return 8;
289 }
290 
292  unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info,
293  TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo,
295  EVT OrigTy = TLI->getValueType(DL, Ty);
296  if (!OrigTy.isSimple()) {
297  return BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
298  Opd1PropInfo, Opd2PropInfo);
299  }
300 
301  // Legalize the type.
302  std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
303  int ISD = TLI->InstructionOpcodeToISD(Opcode);
304 
305  // Because we don't have any legal vector operations, but the legal types, we
306  // need to account for split vectors.
307  unsigned NElts = LT.second.isVector() ?
308  LT.second.getVectorNumElements() : 1;
309 
310  MVT::SimpleValueType SLT = LT.second.getScalarType().SimpleTy;
311 
312  switch (ISD) {
313  case ISD::SHL:
314  case ISD::SRL:
315  case ISD::SRA:
316  if (SLT == MVT::i64)
317  return get64BitInstrCost() * LT.first * NElts;
318 
319  // i32
320  return getFullRateInstrCost() * LT.first * NElts;
321  case ISD::ADD:
322  case ISD::SUB:
323  case ISD::AND:
324  case ISD::OR:
325  case ISD::XOR:
326  if (SLT == MVT::i64){
327  // and, or and xor are typically split into 2 VALU instructions.
328  return 2 * getFullRateInstrCost() * LT.first * NElts;
329  }
330 
331  return LT.first * NElts * getFullRateInstrCost();
332  case ISD::MUL: {
333  const int QuarterRateCost = getQuarterRateInstrCost();
334  if (SLT == MVT::i64) {
335  const int FullRateCost = getFullRateInstrCost();
336  return (4 * QuarterRateCost + (2 * 2) * FullRateCost) * LT.first * NElts;
337  }
338 
339  // i32
340  return QuarterRateCost * NElts * LT.first;
341  }
342  case ISD::FADD:
343  case ISD::FSUB:
344  case ISD::FMUL:
345  if (SLT == MVT::f64)
346  return LT.first * NElts * get64BitInstrCost();
347 
348  if (SLT == MVT::f32 || SLT == MVT::f16)
349  return LT.first * NElts * getFullRateInstrCost();
350  break;
351  case ISD::FDIV:
352  case ISD::FREM:
353  // FIXME: frem should be handled separately. The fdiv in it is most of it,
354  // but the current lowering is also not entirely correct.
355  if (SLT == MVT::f64) {
356  int Cost = 4 * get64BitInstrCost() + 7 * getQuarterRateInstrCost();
357  // Add cost of workaround.
359  Cost += 3 * getFullRateInstrCost();
360 
361  return LT.first * Cost * NElts;
362  }
363 
364  if (!Args.empty() && match(Args[0], PatternMatch::m_FPOne())) {
365  // TODO: This is more complicated, unsafe flags etc.
366  if ((SLT == MVT::f32 && !ST->hasFP32Denormals()) ||
367  (SLT == MVT::f16 && ST->has16BitInsts())) {
368  return LT.first * getQuarterRateInstrCost() * NElts;
369  }
370  }
371 
372  if (SLT == MVT::f16 && ST->has16BitInsts()) {
373  // 2 x v_cvt_f32_f16
374  // f32 rcp
375  // f32 fmul
376  // v_cvt_f16_f32
377  // f16 div_fixup
378  int Cost = 4 * getFullRateInstrCost() + 2 * getQuarterRateInstrCost();
379  return LT.first * Cost * NElts;
380  }
381 
382  if (SLT == MVT::f32 || SLT == MVT::f16) {
383  int Cost = 7 * getFullRateInstrCost() + 1 * getQuarterRateInstrCost();
384 
385  if (!ST->hasFP32Denormals()) {
386  // FP mode switches.
387  Cost += 2 * getFullRateInstrCost();
388  }
389 
390  return LT.first * NElts * Cost;
391  }
392  break;
393  default:
394  break;
395  }
396 
397  return BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
398  Opd1PropInfo, Opd2PropInfo);
399 }
400 
401 unsigned AMDGPUTTIImpl::getCFInstrCost(unsigned Opcode) {
402  // XXX - For some reason this isn't called for switch.
403  switch (Opcode) {
404  case Instruction::Br:
405  case Instruction::Ret:
406  return 10;
407  default:
408  return BaseT::getCFInstrCost(Opcode);
409  }
410 }
411 
412 int AMDGPUTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy,
413  unsigned Index) {
414  switch (Opcode) {
415  case Instruction::ExtractElement:
416  case Instruction::InsertElement: {
417  unsigned EltSize
418  = DL.getTypeSizeInBits(cast<VectorType>(ValTy)->getElementType());
419  if (EltSize < 32) {
420  if (EltSize == 16 && Index == 0 && ST->has16BitInsts())
421  return 0;
422  return BaseT::getVectorInstrCost(Opcode, ValTy, Index);
423  }
424 
425  // Extracts are just reads of a subregister, so are free. Inserts are
426  // considered free because we don't want to have any cost for scalarizing
427  // operations, and we don't have to copy into a different register class.
428 
429  // Dynamic indexing isn't free and is best avoided.
430  return Index == ~0u ? 2 : 0;
431  }
432  default:
433  return BaseT::getVectorInstrCost(Opcode, ValTy, Index);
434  }
435 }
436 
438  switch (I->getIntrinsicID()) {
439  case Intrinsic::amdgcn_workitem_id_x:
440  case Intrinsic::amdgcn_workitem_id_y:
441  case Intrinsic::amdgcn_workitem_id_z:
442  case Intrinsic::amdgcn_interp_mov:
443  case Intrinsic::amdgcn_interp_p1:
444  case Intrinsic::amdgcn_interp_p2:
445  case Intrinsic::amdgcn_mbcnt_hi:
446  case Intrinsic::amdgcn_mbcnt_lo:
447  case Intrinsic::r600_read_tidig_x:
448  case Intrinsic::r600_read_tidig_y:
449  case Intrinsic::r600_read_tidig_z:
450  case Intrinsic::amdgcn_atomic_inc:
451  case Intrinsic::amdgcn_atomic_dec:
452  case Intrinsic::amdgcn_image_atomic_swap:
453  case Intrinsic::amdgcn_image_atomic_add:
454  case Intrinsic::amdgcn_image_atomic_sub:
455  case Intrinsic::amdgcn_image_atomic_smin:
456  case Intrinsic::amdgcn_image_atomic_umin:
457  case Intrinsic::amdgcn_image_atomic_smax:
458  case Intrinsic::amdgcn_image_atomic_umax:
459  case Intrinsic::amdgcn_image_atomic_and:
460  case Intrinsic::amdgcn_image_atomic_or:
461  case Intrinsic::amdgcn_image_atomic_xor:
462  case Intrinsic::amdgcn_image_atomic_inc:
463  case Intrinsic::amdgcn_image_atomic_dec:
464  case Intrinsic::amdgcn_image_atomic_cmpswap:
465  case Intrinsic::amdgcn_buffer_atomic_swap:
466  case Intrinsic::amdgcn_buffer_atomic_add:
467  case Intrinsic::amdgcn_buffer_atomic_sub:
468  case Intrinsic::amdgcn_buffer_atomic_smin:
469  case Intrinsic::amdgcn_buffer_atomic_umin:
470  case Intrinsic::amdgcn_buffer_atomic_smax:
471  case Intrinsic::amdgcn_buffer_atomic_umax:
472  case Intrinsic::amdgcn_buffer_atomic_and:
473  case Intrinsic::amdgcn_buffer_atomic_or:
474  case Intrinsic::amdgcn_buffer_atomic_xor:
475  case Intrinsic::amdgcn_buffer_atomic_cmpswap:
476  case Intrinsic::amdgcn_ps_live:
477  case Intrinsic::amdgcn_ds_swizzle:
478  return true;
479  default:
480  return false;
481  }
482 }
483 
484 static bool isArgPassedInSGPR(const Argument *A) {
485  const Function *F = A->getParent();
486 
487  // Arguments to compute shaders are never a source of divergence.
489  switch (CC) {
492  return true;
500  // For non-compute shaders, SGPR inputs are marked with either inreg or byval.
501  // Everything else is in VGPRs.
502  return F->getAttributes().hasParamAttribute(A->getArgNo(), Attribute::InReg) ||
503  F->getAttributes().hasParamAttribute(A->getArgNo(), Attribute::ByVal);
504  default:
505  // TODO: Should calls support inreg for SGPR inputs?
506  return false;
507  }
508 }
509 
510 /// \returns true if the result of the value could potentially be
511 /// different across workitems in a wavefront.
513  if (const Argument *A = dyn_cast<Argument>(V))
514  return !isArgPassedInSGPR(A);
515 
516  // Loads from the private address space are divergent, because threads
517  // can execute the load instruction with the same inputs and get different
518  // results.
519  //
520  // All other loads are not divergent, because if threads issue loads with the
521  // same arguments, they will always get the same result.
522  if (const LoadInst *Load = dyn_cast<LoadInst>(V))
523  return Load->getPointerAddressSpace() == ST->getAMDGPUAS().PRIVATE_ADDRESS;
524 
525  // Atomics are divergent because they are executed sequentially: when an
526  // atomic operation refers to the same address in each thread, then each
527  // thread after the first sees the value written by the previous thread as
528  // original value.
529  if (isa<AtomicRMWInst>(V) || isa<AtomicCmpXchgInst>(V))
530  return true;
531 
532  if (const IntrinsicInst *Intrinsic = dyn_cast<IntrinsicInst>(V))
533  return isIntrinsicSourceOfDivergence(Intrinsic);
534 
535  // Assume all function calls are a source of divergence.
536  if (isa<CallInst>(V) || isa<InvokeInst>(V))
537  return true;
538 
539  return false;
540 }
541 
542 bool AMDGPUTTIImpl::isAlwaysUniform(const Value *V) const {
543  if (const IntrinsicInst *Intrinsic = dyn_cast<IntrinsicInst>(V)) {
544  switch (Intrinsic->getIntrinsicID()) {
545  default:
546  return false;
547  case Intrinsic::amdgcn_readfirstlane:
548  case Intrinsic::amdgcn_readlane:
549  return true;
550  }
551  }
552  return false;
553 }
554 
556  Type *SubTp) {
557  if (ST->hasVOP3PInsts()) {
558  VectorType *VT = cast<VectorType>(Tp);
559  if (VT->getNumElements() == 2 &&
560  DL.getTypeSizeInBits(VT->getElementType()) == 16) {
561  // With op_sel VOP3P instructions freely can access the low half or high
562  // half of a register, so any swizzle is free.
563 
564  switch (Kind) {
565  case TTI::SK_Broadcast:
566  case TTI::SK_Reverse:
568  return 0;
569  default:
570  break;
571  }
572  }
573  }
574 
575  return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
576 }
577 
579  const Function *Callee) const {
580  const TargetMachine &TM = getTLI()->getTargetMachine();
581  const FeatureBitset &CallerBits =
582  TM.getSubtargetImpl(*Caller)->getFeatureBits();
583  const FeatureBitset &CalleeBits =
584  TM.getSubtargetImpl(*Callee)->getFeatureBits();
585 
586  FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList;
587  FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList;
588  return ((RealCallerBits & RealCalleeBits) == RealCalleeBits);
589 }
static bool isIntrinsicSourceOfDivergence(const IntrinsicInst *I)
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:109
bool Partial
Allow partial unrolling (unrolling of loops to expand the size of the loop body, not only to eliminat...
unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >())
Definition: BasicTTIImpl.h:469
This file a TargetTransformInfo::Concept conforming object specific to the AMDGPU target machine...
Generation getGeneration() const
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
This class represents an incoming formal argument to a Function.
Definition: Argument.h:30
unsigned getNumberOfRegisters(bool Vector) const
AMDGPU specific subclass of TargetSubtarget.
bool isAlwaysUniform(const Value *V) const
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool isSized(SmallPtrSetImpl< Type *> *Visited=nullptr) const
Return true if it makes sense to take the size of this type.
Definition: Type.h:262
static cl::opt< unsigned > UnrollThresholdIf("amdgpu-unroll-threshold-if", cl::desc("Unroll threshold increment for AMDGPU for each if statement inside loop"), cl::init(150), cl::Hidden)
unsigned getLoopDepth() const
Return the nesting level of this loop.
Definition: LoopInfo.h:92
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
The main scalar evolution driver.
bool hasUnalignedScratchAccess() const
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP)
F(f)
An instruction for reading from memory.
Definition: Instructions.h:164
Hexagon Common GEP
unsigned getHardwareNumberOfRegisters(bool Vector) const
Address space for global memory (RAT0, VTX0).
Definition: AMDGPU.h:224
bool hasVOP3PInsts() const
Calling convention used for Mesa/AMDPAL compute shaders.
Definition: CallingConv.h:198
Calling convention used for AMDPAL vertex shader if tessellation is in use.
Definition: CallingConv.h:216
bool match(Val *V, const Pattern &P)
Definition: PatternMatch.h:49
OpenCL uses address spaces to differentiate between various memory regions on the hardware...
Definition: AMDGPU.h:214
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
Shift and rotation operations.
Definition: ISDOpcodes.h:379
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:781
This file contains the simple types necessary to represent the attributes associated with functions a...
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const
uint64_t getNumElements() const
Definition: DerivedTypes.h:359
unsigned getMaxInterleaveFactor(unsigned VF)
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:205
static bool dependsOnLocalPhi(const Loop *L, const Value *Cond, unsigned Depth=0)
Reverse the order of the vector.
amdgpu Simplify well known AMD library false Value * Callee
unsigned getAddressSpace() const
Returns the address space of this instruction&#39;s pointer type.
Definition: Instructions.h:946
unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp)
an instruction for type-safe pointer arithmetic to access elements of arrays and structs ...
Definition: Instructions.h:837
bool hasFP32Denormals() const
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:406
Calling convention used for AMDPAL shader stage before geometry shader if geometry is in use...
Definition: CallingConv.h:221
Container class for subtarget features.
SPIR_KERNEL - Calling convention for SPIR kernel functions.
Definition: CallingConv.h:137
LLVM Basic Block Representation.
Definition: BasicBlock.h:59
bool isLoopExiting(const BlockT *BB) const
True if terminator in the block can branch to another block that is outside of the current loop...
Definition: LoopInfo.h:197
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
Simple binary floating point operators.
Definition: ISDOpcodes.h:259
Conditional or Unconditional Branch instruction.
bool has16BitInsts() const
unsigned getRegisterBitWidth(bool Vector) const
bool any_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:774
Calling convention for AMDGPU code object kernels.
Definition: CallingConv.h:201
op_range operands()
Definition: User.h:222
unsigned getMinVectorRegisterBitWidth() const
static bool isArgPassedInSGPR(const Argument *A)
unsigned REGION_ADDRESS
Address space for region memory.
Definition: AMDGPU.h:218
Extended Value Type.
Definition: ValueTypes.h:34
const AMDGPUAS & AS
const TargetMachine & getTargetMachine() const
Value * GetUnderlyingObject(Value *V, const DataLayout &DL, unsigned MaxLookup=6)
This method strips off any GEP address adjustments and pointer casts from the specified value...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
Type * getAllocatedType() const
Return the type that is being allocated by the instruction.
Definition: Instructions.h:102
bool isLoopInvariant(const Value *V) const
Return true if the specified value is loop invariant.
Definition: LoopInfo.cpp:56
Calling convention used for Mesa vertex shaders, or AMDPAL last shader stage before rasterization (ve...
Definition: CallingConv.h:189
unsigned getMaxPrivateElementSize() const
OperandValueProperties
Additional properties of an operand&#39;s values.
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:51
unsigned getCFInstrCost(unsigned Opcode)
Definition: BasicTTIImpl.h:658
unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp)
Definition: BasicTTIImpl.h:516
bool contains(const LoopT *L) const
Return true if the specified loop is contained within in this loop.
Definition: LoopInfo.h:110
bool hasParamAttribute(unsigned ArgNo, Attribute::AttrKind Kind) const
Equivalent to hasAttribute(ArgNo + FirstArgIndex, Kind).
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:194
Module.h This file contains the declarations for the Module class.
unsigned getCFInstrCost(unsigned Opcode)
virtual const TargetSubtargetInfo * getSubtargetImpl(const Function &) const
Virtual method implemented by subclasses that returns a reference to that target&#39;s TargetSubtargetInf...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
Class to represent vector types.
Definition: DerivedTypes.h:393
Address space for indirect addressible parameter memory (VTX1)
Definition: AMDGPU.h:230
Calling convention used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:195
unsigned getArgNo() const
Return the index of this formal argument in its containing function.
Definition: Argument.h:48
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
Address space for constant memory (VTX2)
Definition: AMDGPU.h:225
uint64_t getTypeSizeInBits(Type *Ty) const
Size examples:
Definition: DataLayout.h:530
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:403
AMDGPUAS getAMDGPUAS() const
const std::vector< LoopT * > & getSubLoops() const
Return the loops contained entirely within this loop.
Definition: LoopInfo.h:131
int getVectorInstrCost(unsigned Opcode, Type *ValTy, unsigned Index)
specific_fpval m_FPOne()
Match a float 1.0 or vector with all elements equal to 1.0.
Definition: PatternMatch.h:407
Calling convention used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
Definition: CallingConv.h:208
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:362
int getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value *> Args=ArrayRef< const Value *>())
Address space for direct addressible parameter memory (CONST0)
Definition: AMDGPU.h:228
unsigned Threshold
The cost threshold for the unrolled loop.
const Function * getParent() const
Definition: Argument.h:42
Calling convention used for Mesa/AMDPAL geometry shaders.
Definition: CallingConv.h:192
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:439
ArrayRef< BlockT * > getBlocks() const
Get a list of the basic blocks which make up this loop.
Definition: LoopInfo.h:149
Parameters that control the generic loop unrolling transformation.
unsigned FLAT_ADDRESS
Address space for flat memory.
Definition: AMDGPU.h:217
#define I(x, y, z)
Definition: MD5.cpp:58
iterator_range< value_op_iterator > operand_values()
Definition: User.h:246
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
Definition: BasicTTIImpl.h:703
bool isSourceOfDivergence(const Value *V) const
Address space for local memory.
Definition: AMDGPU.h:226
static cl::opt< unsigned > UnrollThresholdLocal("amdgpu-unroll-threshold-local", cl::desc("Unroll threshold for AMDGPU if local memory used in a loop"), cl::init(1000), cl::Hidden)
static int const Threshold
TODO: Write a new FunctionPass AliasAnalysis so that it can keep a cache.
const unsigned Kind
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const
LLVM Value Representation.
Definition: Value.h:73
static cl::opt< unsigned > UnrollThresholdPrivate("amdgpu-unroll-threshold-private", cl::desc("Unroll threshold for AMDGPU if private memory used in a loop"), cl::init(2500), cl::Hidden)
Broadcast element 0 to all other elements.
#define DEBUG(X)
Definition: Debug.h:118
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:57
Type * getElementType() const
Definition: DerivedTypes.h:360
OperandValueKind
Additional information about an operand&#39;s possible values.
This pass exposes codegen information to IR-level passes.
bool isStaticAlloca() const
Return true if this alloca is in the entry block of the function and is a constant size...
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:126
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
std::pair< int, MVT > getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const
Estimate the cost of type-legalization and the legalized type.
unsigned PRIVATE_ADDRESS
Address space for private memory.
Definition: AMDGPU.h:216
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:144
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:44
an instruction to allocate memory on the stack
Definition: Instructions.h:60
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Shuffle elements of single source vector with any shuffle mask.