LLVM  9.0.0svn
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SIInstrInfo.h File Reference

Interface definition for SIInstrInfo. More...

#include "AMDGPUInstrInfo.h"
#include "SIDefines.h"
#include "SIRegisterInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Support/Compiler.h"
#include <cassert>
#include <cstdint>
#include "AMDGPUGenInstrInfo.inc"
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class  llvm::SIInstrInfo


 This class represents lattice values for constants.




enum  llvm::AMDGPU::TargetFlags { llvm::AMDGPU::TF_LONG_BRANCH_FORWARD = 1 << 0, llvm::AMDGPU::TF_LONG_BRANCH_BACKWARD = 1 << 1 }
enum  llvm::SI::KernelInputOffsets::Offsets {
  llvm::SI::KernelInputOffsets::NGROUPS_X = 0, llvm::SI::KernelInputOffsets::NGROUPS_Y = 4, llvm::SI::KernelInputOffsets::NGROUPS_Z = 8, llvm::SI::KernelInputOffsets::GLOBAL_SIZE_X = 12,
  llvm::SI::KernelInputOffsets::GLOBAL_SIZE_Y = 16, llvm::SI::KernelInputOffsets::GLOBAL_SIZE_Z = 20, llvm::SI::KernelInputOffsets::LOCAL_SIZE_X = 24, llvm::SI::KernelInputOffsets::LOCAL_SIZE_Y = 28,
  llvm::SI::KernelInputOffsets::LOCAL_SIZE_Z = 32
 Offsets in bytes from the start of the input buffer. More...


bool llvm::isOfRegClass (const TargetInstrInfo::RegSubRegPair &P, const TargetRegisterClass &TRC, MachineRegisterInfo &MRI)
 Returns true if a reg:subreg pair P has a TRC class. More...
TargetInstrInfo::RegSubRegPair llvm::getRegSubRegPair (const MachineOperand &O)
 Create RegSubRegPair from a register MachineOperand. More...
TargetInstrInfo::RegSubRegPair llvm::getRegSequenceSubReg (MachineInstr &MI, unsigned SubReg)
 Return the SubReg component from REG_SEQUENCE. More...
MachineInstrllvm::getVRegSubRegDef (const TargetInstrInfo::RegSubRegPair &P, MachineRegisterInfo &MRI)
 Return the defining instruction for a given reg:subreg pair skipping copy like instructions and subreg-manipulation pseudos. More...
bool llvm::isEXECMaskConstantBetweenDefAndUses (unsigned VReg, MachineRegisterInfo &MRI)
 Return true if EXEC mask isnt' changed between the def and all uses of VReg. More...
LLVM_READONLY int llvm::AMDGPU::getVOPe64 (uint16_t Opcode)
LLVM_READONLY int llvm::AMDGPU::getVOPe32 (uint16_t Opcode)
LLVM_READONLY int llvm::AMDGPU::getSDWAOp (uint16_t Opcode)
LLVM_READONLY int llvm::AMDGPU::getDPPOp32 (uint16_t Opcode)
LLVM_READONLY int llvm::AMDGPU::getBasicFromSDWAOp (uint16_t Opcode)
LLVM_READONLY int llvm::AMDGPU::getCommuteRev (uint16_t Opcode)
LLVM_READONLY int llvm::AMDGPU::getCommuteOrig (uint16_t Opcode)
LLVM_READONLY int llvm::AMDGPU::getAddr64Inst (uint16_t Opcode)
LLVM_READONLY int llvm::AMDGPU::getIfAddr64Inst (uint16_t Opcode)
 Check if Opcode is an Addr64 opcode. More...
LLVM_READONLY int llvm::AMDGPU::getMUBUFNoLdsInst (uint16_t Opcode)
LLVM_READONLY int llvm::AMDGPU::getAtomicRetOp (uint16_t Opcode)
LLVM_READONLY int llvm::AMDGPU::getAtomicNoRetOp (uint16_t Opcode)
LLVM_READONLY int llvm::AMDGPU::getSOPKOp (uint16_t Opcode)
LLVM_READONLY int llvm::AMDGPU::getGlobalSaddrOp (uint16_t Opcode)


const uint64_t llvm::AMDGPU::RSRC_DATA_FORMAT = 0xf00000000000LL
const uint64_t llvm::AMDGPU::RSRC_ELEMENT_SIZE_SHIFT = (32 + 19)
const uint64_t llvm::AMDGPU::RSRC_INDEX_STRIDE_SHIFT = (32 + 21)
const uint64_t llvm::AMDGPU::RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23)

Detailed Description

Interface definition for SIInstrInfo.

Definition in file SIInstrInfo.h.

Macro Definition Documentation



Definition at line 33 of file SIInstrInfo.h.