LLVM  9.0.0svn
LegalizeVectorTypes.cpp
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1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file performs vector type splitting and scalarization for LegalizeTypes.
10 // Scalarization is the act of changing a computation in an illegal one-element
11 // vector type to be a computation in its scalar element type. For example,
12 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
13 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
14 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
15 // types.
16 // Splitting is the act of changing a computation in an invalid vector type to
17 // be a computation in two vectors of half the size. For example, implementing
18 // <128 x f32> operations in terms of two <64 x f32> operations.
19 //
20 //===----------------------------------------------------------------------===//
21 
22 #include "LegalizeTypes.h"
23 #include "llvm/IR/DataLayout.h"
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "legalize-types"
29 
30 //===----------------------------------------------------------------------===//
31 // Result Vector Scalarization: <1 x ty> -> ty.
32 //===----------------------------------------------------------------------===//
33 
34 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
35  LLVM_DEBUG(dbgs() << "Scalarize node result " << ResNo << ": "; N->dump(&DAG);
36  dbgs() << "\n");
37  SDValue R = SDValue();
38 
39  switch (N->getOpcode()) {
40  default:
41 #ifndef NDEBUG
42  dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
43  N->dump(&DAG);
44  dbgs() << "\n";
45 #endif
46  report_fatal_error("Do not know how to scalarize the result of this "
47  "operator!\n");
48 
49  case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
50  case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
51  case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
52  case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
53  case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
54  case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
55  case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
56  case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
57  case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
58  case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
59  case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
60  case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
61  case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
62  case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
63  case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
64  case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
65  case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
69  R = ScalarizeVecRes_VecInregOp(N);
70  break;
71  case ISD::ABS:
72  case ISD::ANY_EXTEND:
73  case ISD::BITREVERSE:
74  case ISD::BSWAP:
75  case ISD::CTLZ:
77  case ISD::CTPOP:
78  case ISD::CTTZ:
80  case ISD::FABS:
81  case ISD::FCEIL:
82  case ISD::FCOS:
83  case ISD::FEXP:
84  case ISD::FEXP2:
85  case ISD::FFLOOR:
86  case ISD::FLOG:
87  case ISD::FLOG10:
88  case ISD::FLOG2:
89  case ISD::FNEARBYINT:
90  case ISD::FNEG:
91  case ISD::FP_EXTEND:
92  case ISD::FP_TO_SINT:
93  case ISD::FP_TO_UINT:
94  case ISD::FRINT:
95  case ISD::FROUND:
96  case ISD::FSIN:
97  case ISD::FSQRT:
98  case ISD::FTRUNC:
99  case ISD::SIGN_EXTEND:
100  case ISD::SINT_TO_FP:
101  case ISD::TRUNCATE:
102  case ISD::UINT_TO_FP:
103  case ISD::ZERO_EXTEND:
104  case ISD::FCANONICALIZE:
105  R = ScalarizeVecRes_UnaryOp(N);
106  break;
107 
108  case ISD::ADD:
109  case ISD::AND:
110  case ISD::FADD:
111  case ISD::FCOPYSIGN:
112  case ISD::FDIV:
113  case ISD::FMUL:
114  case ISD::FMINNUM:
115  case ISD::FMAXNUM:
116  case ISD::FMINNUM_IEEE:
117  case ISD::FMAXNUM_IEEE:
118  case ISD::FMINIMUM:
119  case ISD::FMAXIMUM:
120  case ISD::SMIN:
121  case ISD::SMAX:
122  case ISD::UMIN:
123  case ISD::UMAX:
124 
125  case ISD::SADDSAT:
126  case ISD::UADDSAT:
127  case ISD::SSUBSAT:
128  case ISD::USUBSAT:
129 
130  case ISD::FPOW:
131  case ISD::FREM:
132  case ISD::FSUB:
133  case ISD::MUL:
134  case ISD::OR:
135  case ISD::SDIV:
136  case ISD::SREM:
137  case ISD::SUB:
138  case ISD::UDIV:
139  case ISD::UREM:
140  case ISD::XOR:
141  case ISD::SHL:
142  case ISD::SRA:
143  case ISD::SRL:
144  R = ScalarizeVecRes_BinOp(N);
145  break;
146  case ISD::FMA:
147  R = ScalarizeVecRes_TernaryOp(N);
148  break;
149  case ISD::STRICT_FADD:
150  case ISD::STRICT_FSUB:
151  case ISD::STRICT_FMUL:
152  case ISD::STRICT_FDIV:
153  case ISD::STRICT_FREM:
154  case ISD::STRICT_FSQRT:
155  case ISD::STRICT_FMA:
156  case ISD::STRICT_FPOW:
157  case ISD::STRICT_FPOWI:
158  case ISD::STRICT_FSIN:
159  case ISD::STRICT_FCOS:
160  case ISD::STRICT_FEXP:
161  case ISD::STRICT_FEXP2:
162  case ISD::STRICT_FLOG:
163  case ISD::STRICT_FLOG10:
164  case ISD::STRICT_FLOG2:
165  case ISD::STRICT_FRINT:
167  case ISD::STRICT_FMAXNUM:
168  case ISD::STRICT_FMINNUM:
169  case ISD::STRICT_FCEIL:
170  case ISD::STRICT_FFLOOR:
171  case ISD::STRICT_FROUND:
172  case ISD::STRICT_FTRUNC:
173  R = ScalarizeVecRes_StrictFPOp(N);
174  break;
175  case ISD::UADDO:
176  case ISD::SADDO:
177  case ISD::USUBO:
178  case ISD::SSUBO:
179  case ISD::UMULO:
180  case ISD::SMULO:
181  R = ScalarizeVecRes_OverflowOp(N, ResNo);
182  break;
183  case ISD::SMULFIX:
184  case ISD::UMULFIX:
185  R = ScalarizeVecRes_MULFIX(N);
186  break;
187  }
188 
189  // If R is null, the sub-method took care of registering the result.
190  if (R.getNode())
191  SetScalarizedVector(SDValue(N, ResNo), R);
192 }
193 
194 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
195  SDValue LHS = GetScalarizedVector(N->getOperand(0));
196  SDValue RHS = GetScalarizedVector(N->getOperand(1));
197  return DAG.getNode(N->getOpcode(), SDLoc(N),
198  LHS.getValueType(), LHS, RHS, N->getFlags());
199 }
200 
201 SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {
202  SDValue Op0 = GetScalarizedVector(N->getOperand(0));
203  SDValue Op1 = GetScalarizedVector(N->getOperand(1));
204  SDValue Op2 = GetScalarizedVector(N->getOperand(2));
205  return DAG.getNode(N->getOpcode(), SDLoc(N),
206  Op0.getValueType(), Op0, Op1, Op2);
207 }
208 
209 SDValue DAGTypeLegalizer::ScalarizeVecRes_MULFIX(SDNode *N) {
210  SDValue Op0 = GetScalarizedVector(N->getOperand(0));
211  SDValue Op1 = GetScalarizedVector(N->getOperand(1));
212  SDValue Op2 = N->getOperand(2);
213  return DAG.getNode(N->getOpcode(), SDLoc(N), Op0.getValueType(), Op0, Op1,
214  Op2);
215 }
216 
217 SDValue DAGTypeLegalizer::ScalarizeVecRes_StrictFPOp(SDNode *N) {
219  unsigned NumOpers = N->getNumOperands();
220  SDValue Chain = N->getOperand(0);
221  EVT ValueVTs[] = {VT, MVT::Other};
222  SDLoc dl(N);
223 
225 
226  // The Chain is the first operand.
227  Opers.push_back(Chain);
228 
229  // Now process the remaining operands.
230  for (unsigned i = 1; i < NumOpers; ++i) {
231  SDValue Oper = N->getOperand(i);
232 
233  if (Oper.getValueType().isVector())
234  Oper = GetScalarizedVector(Oper);
235 
236  Opers.push_back(Oper);
237  }
238 
239  SDValue Result = DAG.getNode(N->getOpcode(), dl, ValueVTs, Opers);
240 
241  // Legalize the chain result - switch anything that used the old chain to
242  // use the new one.
243  ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
244  return Result;
245 }
246 
247 SDValue DAGTypeLegalizer::ScalarizeVecRes_OverflowOp(SDNode *N,
248  unsigned ResNo) {
249  SDLoc DL(N);
250  EVT ResVT = N->getValueType(0);
251  EVT OvVT = N->getValueType(1);
252 
253  SDValue ScalarLHS, ScalarRHS;
254  if (getTypeAction(ResVT) == TargetLowering::TypeScalarizeVector) {
255  ScalarLHS = GetScalarizedVector(N->getOperand(0));
256  ScalarRHS = GetScalarizedVector(N->getOperand(1));
257  } else {
258  SmallVector<SDValue, 1> ElemsLHS, ElemsRHS;
259  DAG.ExtractVectorElements(N->getOperand(0), ElemsLHS);
260  DAG.ExtractVectorElements(N->getOperand(1), ElemsRHS);
261  ScalarLHS = ElemsLHS[0];
262  ScalarRHS = ElemsRHS[0];
263  }
264 
265  SDVTList ScalarVTs = DAG.getVTList(
267  SDNode *ScalarNode = DAG.getNode(
268  N->getOpcode(), DL, ScalarVTs, ScalarLHS, ScalarRHS).getNode();
269 
270  // Replace the other vector result not being explicitly scalarized here.
271  unsigned OtherNo = 1 - ResNo;
272  EVT OtherVT = N->getValueType(OtherNo);
273  if (getTypeAction(OtherVT) == TargetLowering::TypeScalarizeVector) {
274  SetScalarizedVector(SDValue(N, OtherNo), SDValue(ScalarNode, OtherNo));
275  } else {
276  SDValue OtherVal = DAG.getNode(
277  ISD::SCALAR_TO_VECTOR, DL, OtherVT, SDValue(ScalarNode, OtherNo));
278  ReplaceValueWith(SDValue(N, OtherNo), OtherVal);
279  }
280 
281  return SDValue(ScalarNode, ResNo);
282 }
283 
284 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
285  unsigned ResNo) {
286  SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
287  return GetScalarizedVector(Op);
288 }
289 
290 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
291  SDValue Op = N->getOperand(0);
292  if (Op.getValueType().isVector()
293  && Op.getValueType().getVectorNumElements() == 1
294  && !isSimpleLegalType(Op.getValueType()))
295  Op = GetScalarizedVector(Op);
296  EVT NewVT = N->getValueType(0).getVectorElementType();
297  return DAG.getNode(ISD::BITCAST, SDLoc(N),
298  NewVT, Op);
299 }
300 
301 SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {
302  EVT EltVT = N->getValueType(0).getVectorElementType();
303  SDValue InOp = N->getOperand(0);
304  // The BUILD_VECTOR operands may be of wider element types and
305  // we may need to truncate them back to the requested return type.
306  if (EltVT.isInteger())
307  return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
308  return InOp;
309 }
310 
311 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
312  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
314  N->getOperand(0), N->getOperand(1));
315 }
316 
317 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
318  EVT NewVT = N->getValueType(0).getVectorElementType();
319  SDValue Op = GetScalarizedVector(N->getOperand(0));
320  return DAG.getNode(ISD::FP_ROUND, SDLoc(N),
321  NewVT, Op, N->getOperand(1));
322 }
323 
324 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
325  SDValue Op = GetScalarizedVector(N->getOperand(0));
326  return DAG.getNode(ISD::FPOWI, SDLoc(N),
327  Op.getValueType(), Op, N->getOperand(1));
328 }
329 
330 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
331  // The value to insert may have a wider type than the vector element type,
332  // so be sure to truncate it to the element type if necessary.
333  SDValue Op = N->getOperand(1);
334  EVT EltVT = N->getValueType(0).getVectorElementType();
335  if (Op.getValueType() != EltVT)
336  // FIXME: Can this happen for floating point types?
337  Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op);
338  return Op;
339 }
340 
341 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
342  assert(N->isUnindexed() && "Indexed vector load?");
343 
344  SDValue Result = DAG.getLoad(
347  N->getBasePtr(), DAG.getUNDEF(N->getBasePtr().getValueType()),
350  N->getAAInfo());
351 
352  // Legalize the chain result - switch anything that used the old chain to
353  // use the new one.
354  ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
355  return Result;
356 }
357 
358 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
359  // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
360  EVT DestVT = N->getValueType(0).getVectorElementType();
361  SDValue Op = N->getOperand(0);
362  EVT OpVT = Op.getValueType();
363  SDLoc DL(N);
364  // The result needs scalarizing, but it's not a given that the source does.
365  // This is a workaround for targets where it's impossible to scalarize the
366  // result of a conversion, because the source type is legal.
367  // For instance, this happens on AArch64: v1i1 is illegal but v1i{8,16,32}
368  // are widened to v8i8, v4i16, and v2i32, which is legal, because v1i64 is
369  // legal and was not scalarized.
370  // See the similar logic in ScalarizeVecRes_SETCC
371  if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
372  Op = GetScalarizedVector(Op);
373  } else {
374  EVT VT = OpVT.getVectorElementType();
375  Op = DAG.getNode(
376  ISD::EXTRACT_VECTOR_ELT, DL, VT, Op,
377  DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
378  }
379  return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op);
380 }
381 
382 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
383  EVT EltVT = N->getValueType(0).getVectorElementType();
384  EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
385  SDValue LHS = GetScalarizedVector(N->getOperand(0));
386  return DAG.getNode(N->getOpcode(), SDLoc(N), EltVT,
387  LHS, DAG.getValueType(ExtVT));
388 }
389 
390 SDValue DAGTypeLegalizer::ScalarizeVecRes_VecInregOp(SDNode *N) {
391  SDLoc DL(N);
392  SDValue Op = N->getOperand(0);
393 
394  EVT OpVT = Op.getValueType();
395  EVT OpEltVT = OpVT.getVectorElementType();
396  EVT EltVT = N->getValueType(0).getVectorElementType();
397 
398  if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
399  Op = GetScalarizedVector(Op);
400  } else {
401  Op = DAG.getNode(
402  ISD::EXTRACT_VECTOR_ELT, DL, OpEltVT, Op,
403  DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
404  }
405 
406  switch (N->getOpcode()) {
408  return DAG.getNode(ISD::ANY_EXTEND, DL, EltVT, Op);
410  return DAG.getNode(ISD::SIGN_EXTEND, DL, EltVT, Op);
412  return DAG.getNode(ISD::ZERO_EXTEND, DL, EltVT, Op);
413  }
414 
415  llvm_unreachable("Illegal extend_vector_inreg opcode");
416 }
417 
418 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
419  // If the operand is wider than the vector element type then it is implicitly
420  // truncated. Make that explicit here.
421  EVT EltVT = N->getValueType(0).getVectorElementType();
422  SDValue InOp = N->getOperand(0);
423  if (InOp.getValueType() != EltVT)
424  return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
425  return InOp;
426 }
427 
428 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
429  SDValue Cond = N->getOperand(0);
430  EVT OpVT = Cond.getValueType();
431  SDLoc DL(N);
432  // The vselect result and true/value operands needs scalarizing, but it's
433  // not a given that the Cond does. For instance, in AVX512 v1i1 is legal.
434  // See the similar logic in ScalarizeVecRes_SETCC
435  if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
436  Cond = GetScalarizedVector(Cond);
437  } else {
438  EVT VT = OpVT.getVectorElementType();
439  Cond = DAG.getNode(
440  ISD::EXTRACT_VECTOR_ELT, DL, VT, Cond,
441  DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
442  }
443 
444  SDValue LHS = GetScalarizedVector(N->getOperand(1));
445  TargetLowering::BooleanContent ScalarBool =
446  TLI.getBooleanContents(false, false);
447  TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true, false);
448 
449  // If integer and float booleans have different contents then we can't
450  // reliably optimize in all cases. There is a full explanation for this in
451  // DAGCombiner::visitSELECT() where the same issue affects folding
452  // (select C, 0, 1) to (xor C, 1).
453  if (TLI.getBooleanContents(false, false) !=
454  TLI.getBooleanContents(false, true)) {
455  // At least try the common case where the boolean is generated by a
456  // comparison.
457  if (Cond->getOpcode() == ISD::SETCC) {
458  EVT OpVT = Cond->getOperand(0).getValueType();
459  ScalarBool = TLI.getBooleanContents(OpVT.getScalarType());
460  VecBool = TLI.getBooleanContents(OpVT);
461  } else
463  }
464 
465  EVT CondVT = Cond.getValueType();
466  if (ScalarBool != VecBool) {
467  switch (ScalarBool) {
469  break;
473  // Vector read from all ones, scalar expects a single 1 so mask.
474  Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT,
475  Cond, DAG.getConstant(1, SDLoc(N), CondVT));
476  break;
480  // Vector reads from a one, scalar from all ones so sign extend.
481  Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,
482  Cond, DAG.getValueType(MVT::i1));
483  break;
484  }
485  }
486 
487  // Truncate the condition if needed
488  auto BoolVT = getSetCCResultType(CondVT);
489  if (BoolVT.bitsLT(CondVT))
490  Cond = DAG.getNode(ISD::TRUNCATE, SDLoc(N), BoolVT, Cond);
491 
492  return DAG.getSelect(SDLoc(N),
493  LHS.getValueType(), Cond, LHS,
494  GetScalarizedVector(N->getOperand(2)));
495 }
496 
497 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
498  SDValue LHS = GetScalarizedVector(N->getOperand(1));
499  return DAG.getSelect(SDLoc(N),
500  LHS.getValueType(), N->getOperand(0), LHS,
501  GetScalarizedVector(N->getOperand(2)));
502 }
503 
504 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
505  SDValue LHS = GetScalarizedVector(N->getOperand(2));
506  return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(),
507  N->getOperand(0), N->getOperand(1),
508  LHS, GetScalarizedVector(N->getOperand(3)),
509  N->getOperand(4));
510 }
511 
512 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
513  return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
514 }
515 
516 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
517  // Figure out if the scalar is the LHS or RHS and return it.
518  SDValue Arg = N->getOperand(2).getOperand(0);
519  if (Arg.isUndef())
520  return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
521  unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
522  return GetScalarizedVector(N->getOperand(Op));
523 }
524 
525 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
526  assert(N->getValueType(0).isVector() &&
527  N->getOperand(0).getValueType().isVector() &&
528  "Operand types must be vectors");
529  SDValue LHS = N->getOperand(0);
530  SDValue RHS = N->getOperand(1);
531  EVT OpVT = LHS.getValueType();
532  EVT NVT = N->getValueType(0).getVectorElementType();
533  SDLoc DL(N);
534 
535  // The result needs scalarizing, but it's not a given that the source does.
536  if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
537  LHS = GetScalarizedVector(LHS);
538  RHS = GetScalarizedVector(RHS);
539  } else {
540  EVT VT = OpVT.getVectorElementType();
541  LHS = DAG.getNode(
542  ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS,
543  DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
544  RHS = DAG.getNode(
545  ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS,
546  DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
547  }
548 
549  // Turn it into a scalar SETCC.
550  SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
551  N->getOperand(2));
552  // Vectors may have a different boolean contents to scalars. Promote the
553  // value appropriately.
554  ISD::NodeType ExtendCode =
556  return DAG.getNode(ExtendCode, DL, NVT, Res);
557 }
558 
559 
560 //===----------------------------------------------------------------------===//
561 // Operand Vector Scalarization <1 x ty> -> ty.
562 //===----------------------------------------------------------------------===//
563 
564 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
565  LLVM_DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": "; N->dump(&DAG);
566  dbgs() << "\n");
567  SDValue Res = SDValue();
568 
569  if (!Res.getNode()) {
570  switch (N->getOpcode()) {
571  default:
572 #ifndef NDEBUG
573  dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
574  N->dump(&DAG);
575  dbgs() << "\n";
576 #endif
577  report_fatal_error("Do not know how to scalarize this operator's "
578  "operand!\n");
579  case ISD::BITCAST:
580  Res = ScalarizeVecOp_BITCAST(N);
581  break;
582  case ISD::ANY_EXTEND:
583  case ISD::ZERO_EXTEND:
584  case ISD::SIGN_EXTEND:
585  case ISD::TRUNCATE:
586  case ISD::FP_TO_SINT:
587  case ISD::FP_TO_UINT:
588  case ISD::SINT_TO_FP:
589  case ISD::UINT_TO_FP:
590  Res = ScalarizeVecOp_UnaryOp(N);
591  break;
592  case ISD::CONCAT_VECTORS:
593  Res = ScalarizeVecOp_CONCAT_VECTORS(N);
594  break;
596  Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
597  break;
598  case ISD::VSELECT:
599  Res = ScalarizeVecOp_VSELECT(N);
600  break;
601  case ISD::SETCC:
602  Res = ScalarizeVecOp_VSETCC(N);
603  break;
604  case ISD::STORE:
605  Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
606  break;
607  case ISD::FP_ROUND:
608  Res = ScalarizeVecOp_FP_ROUND(N, OpNo);
609  break;
610  case ISD::VECREDUCE_FADD:
611  case ISD::VECREDUCE_FMUL:
612  case ISD::VECREDUCE_ADD:
613  case ISD::VECREDUCE_MUL:
614  case ISD::VECREDUCE_AND:
615  case ISD::VECREDUCE_OR:
616  case ISD::VECREDUCE_XOR:
617  case ISD::VECREDUCE_SMAX:
618  case ISD::VECREDUCE_SMIN:
619  case ISD::VECREDUCE_UMAX:
620  case ISD::VECREDUCE_UMIN:
621  case ISD::VECREDUCE_FMAX:
622  case ISD::VECREDUCE_FMIN:
623  Res = ScalarizeVecOp_VECREDUCE(N);
624  break;
625  }
626  }
627 
628  // If the result is null, the sub-method took care of registering results etc.
629  if (!Res.getNode()) return false;
630 
631  // If the result is N, the sub-method updated N in place. Tell the legalizer
632  // core about this.
633  if (Res.getNode() == N)
634  return true;
635 
636  assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
637  "Invalid operand expansion");
638 
639  ReplaceValueWith(SDValue(N, 0), Res);
640  return false;
641 }
642 
643 /// If the value to convert is a vector that needs to be scalarized, it must be
644 /// <1 x ty>. Convert the element instead.
645 SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
646  SDValue Elt = GetScalarizedVector(N->getOperand(0));
647  return DAG.getNode(ISD::BITCAST, SDLoc(N),
648  N->getValueType(0), Elt);
649 }
650 
651 /// If the input is a vector that needs to be scalarized, it must be <1 x ty>.
652 /// Do the operation on the element instead.
653 SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp(SDNode *N) {
655  "Unexpected vector type!");
656  SDValue Elt = GetScalarizedVector(N->getOperand(0));
657  SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N),
658  N->getValueType(0).getScalarType(), Elt);
659  // Revectorize the result so the types line up with what the uses of this
660  // expression expect.
661  return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Op);
662 }
663 
664 /// The vectors to concatenate have length one - use a BUILD_VECTOR instead.
665 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
667  for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
668  Ops[i] = GetScalarizedVector(N->getOperand(i));
669  return DAG.getBuildVector(N->getValueType(0), SDLoc(N), Ops);
670 }
671 
672 /// If the input is a vector that needs to be scalarized, it must be <1 x ty>,
673 /// so just return the element, ignoring the index.
674 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
675  EVT VT = N->getValueType(0);
676  SDValue Res = GetScalarizedVector(N->getOperand(0));
677  if (Res.getValueType() != VT)
678  Res = VT.isFloatingPoint()
679  ? DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Res)
680  : DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, Res);
681  return Res;
682 }
683 
684 /// If the input condition is a vector that needs to be scalarized, it must be
685 /// <1 x i1>, so just convert to a normal ISD::SELECT
686 /// (still with vector output type since that was acceptable if we got here).
687 SDValue DAGTypeLegalizer::ScalarizeVecOp_VSELECT(SDNode *N) {
688  SDValue ScalarCond = GetScalarizedVector(N->getOperand(0));
689  EVT VT = N->getValueType(0);
690 
691  return DAG.getNode(ISD::SELECT, SDLoc(N), VT, ScalarCond, N->getOperand(1),
692  N->getOperand(2));
693 }
694 
695 /// If the operand is a vector that needs to be scalarized then the
696 /// result must be v1i1, so just convert to a scalar SETCC and wrap
697 /// with a scalar_to_vector since the res type is legal if we got here
698 SDValue DAGTypeLegalizer::ScalarizeVecOp_VSETCC(SDNode *N) {
699  assert(N->getValueType(0).isVector() &&
700  N->getOperand(0).getValueType().isVector() &&
701  "Operand types must be vectors");
702  assert(N->getValueType(0) == MVT::v1i1 && "Expected v1i1 type");
703 
704  EVT VT = N->getValueType(0);
705  SDValue LHS = GetScalarizedVector(N->getOperand(0));
706  SDValue RHS = GetScalarizedVector(N->getOperand(1));
707 
708  EVT OpVT = N->getOperand(0).getValueType();
709  EVT NVT = VT.getVectorElementType();
710  SDLoc DL(N);
711  // Turn it into a scalar SETCC.
712  SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
713  N->getOperand(2));
714 
715  // Vectors may have a different boolean contents to scalars. Promote the
716  // value appropriately.
717  ISD::NodeType ExtendCode =
719 
720  Res = DAG.getNode(ExtendCode, DL, NVT, Res);
721 
722  return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Res);
723 }
724 
725 /// If the value to store is a vector that needs to be scalarized, it must be
726 /// <1 x ty>. Just store the element.
727 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
728  assert(N->isUnindexed() && "Indexed store of one-element vector?");
729  assert(OpNo == 1 && "Do not know how to scalarize this operand!");
730  SDLoc dl(N);
731 
732  if (N->isTruncatingStore())
733  return DAG.getTruncStore(
734  N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
735  N->getBasePtr(), N->getPointerInfo(),
737  N->getMemOperand()->getFlags(), N->getAAInfo());
738 
739  return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
740  N->getBasePtr(), N->getPointerInfo(),
742  N->getAAInfo());
743 }
744 
745 /// If the value to round is a vector that needs to be scalarized, it must be
746 /// <1 x ty>. Convert the element instead.
747 SDValue DAGTypeLegalizer::ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo) {
748  SDValue Elt = GetScalarizedVector(N->getOperand(0));
749  SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N),
750  N->getValueType(0).getVectorElementType(), Elt,
751  N->getOperand(1));
752  return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
753 }
754 
755 SDValue DAGTypeLegalizer::ScalarizeVecOp_VECREDUCE(SDNode *N) {
756  SDValue Res = GetScalarizedVector(N->getOperand(0));
757  // Result type may be wider than element type.
758  if (Res.getValueType() != N->getValueType(0))
759  Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Res);
760  return Res;
761 }
762 
763 //===----------------------------------------------------------------------===//
764 // Result Vector Splitting
765 //===----------------------------------------------------------------------===//
766 
767 /// This method is called when the specified result of the specified node is
768 /// found to need vector splitting. At this point, the node may also have
769 /// invalid operands or may have other results that need legalization, we just
770 /// know that (at least) one result needs vector splitting.
771 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
772  LLVM_DEBUG(dbgs() << "Split node result: "; N->dump(&DAG); dbgs() << "\n");
773  SDValue Lo, Hi;
774 
775  // See if the target wants to custom expand this node.
776  if (CustomLowerNode(N, N->getValueType(ResNo), true))
777  return;
778 
779  switch (N->getOpcode()) {
780  default:
781 #ifndef NDEBUG
782  dbgs() << "SplitVectorResult #" << ResNo << ": ";
783  N->dump(&DAG);
784  dbgs() << "\n";
785 #endif
786  report_fatal_error("Do not know how to split the result of this "
787  "operator!\n");
788 
789  case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
790  case ISD::VSELECT:
791  case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
792  case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
793  case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
794  case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
795  case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
796  case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
797  case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
798  case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
799  case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
800  case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
801  case ISD::FCOPYSIGN: SplitVecRes_FCOPYSIGN(N, Lo, Hi); break;
802  case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
803  case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
804  case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
805  case ISD::LOAD:
806  SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
807  break;
808  case ISD::MLOAD:
809  SplitVecRes_MLOAD(cast<MaskedLoadSDNode>(N), Lo, Hi);
810  break;
811  case ISD::MGATHER:
812  SplitVecRes_MGATHER(cast<MaskedGatherSDNode>(N), Lo, Hi);
813  break;
814  case ISD::SETCC:
815  SplitVecRes_SETCC(N, Lo, Hi);
816  break;
817  case ISD::VECTOR_SHUFFLE:
818  SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
819  break;
820 
824  SplitVecRes_ExtVecInRegOp(N, Lo, Hi);
825  break;
826 
827  case ISD::ABS:
828  case ISD::BITREVERSE:
829  case ISD::BSWAP:
830  case ISD::CTLZ:
831  case ISD::CTTZ:
834  case ISD::CTPOP:
835  case ISD::FABS:
836  case ISD::FCEIL:
837  case ISD::FCOS:
838  case ISD::FEXP:
839  case ISD::FEXP2:
840  case ISD::FFLOOR:
841  case ISD::FLOG:
842  case ISD::FLOG10:
843  case ISD::FLOG2:
844  case ISD::FNEARBYINT:
845  case ISD::FNEG:
846  case ISD::FP_EXTEND:
847  case ISD::FP_ROUND:
848  case ISD::FP_TO_SINT:
849  case ISD::FP_TO_UINT:
850  case ISD::FRINT:
851  case ISD::FROUND:
852  case ISD::FSIN:
853  case ISD::FSQRT:
854  case ISD::FTRUNC:
855  case ISD::SINT_TO_FP:
856  case ISD::TRUNCATE:
857  case ISD::UINT_TO_FP:
858  case ISD::FCANONICALIZE:
859  SplitVecRes_UnaryOp(N, Lo, Hi);
860  break;
861 
862  case ISD::ANY_EXTEND:
863  case ISD::SIGN_EXTEND:
864  case ISD::ZERO_EXTEND:
865  SplitVecRes_ExtendOp(N, Lo, Hi);
866  break;
867 
868  case ISD::ADD:
869  case ISD::SUB:
870  case ISD::MUL:
871  case ISD::MULHS:
872  case ISD::MULHU:
873  case ISD::FADD:
874  case ISD::FSUB:
875  case ISD::FMUL:
876  case ISD::FMINNUM:
877  case ISD::FMAXNUM:
878  case ISD::FMINIMUM:
879  case ISD::FMAXIMUM:
880  case ISD::SDIV:
881  case ISD::UDIV:
882  case ISD::FDIV:
883  case ISD::FPOW:
884  case ISD::AND:
885  case ISD::OR:
886  case ISD::XOR:
887  case ISD::SHL:
888  case ISD::SRA:
889  case ISD::SRL:
890  case ISD::UREM:
891  case ISD::SREM:
892  case ISD::FREM:
893  case ISD::SMIN:
894  case ISD::SMAX:
895  case ISD::UMIN:
896  case ISD::UMAX:
897  case ISD::SADDSAT:
898  case ISD::UADDSAT:
899  case ISD::SSUBSAT:
900  case ISD::USUBSAT:
901  SplitVecRes_BinOp(N, Lo, Hi);
902  break;
903  case ISD::FMA:
904  SplitVecRes_TernaryOp(N, Lo, Hi);
905  break;
906  case ISD::STRICT_FADD:
907  case ISD::STRICT_FSUB:
908  case ISD::STRICT_FMUL:
909  case ISD::STRICT_FDIV:
910  case ISD::STRICT_FREM:
911  case ISD::STRICT_FSQRT:
912  case ISD::STRICT_FMA:
913  case ISD::STRICT_FPOW:
914  case ISD::STRICT_FPOWI:
915  case ISD::STRICT_FSIN:
916  case ISD::STRICT_FCOS:
917  case ISD::STRICT_FEXP:
918  case ISD::STRICT_FEXP2:
919  case ISD::STRICT_FLOG:
920  case ISD::STRICT_FLOG10:
921  case ISD::STRICT_FLOG2:
922  case ISD::STRICT_FRINT:
924  case ISD::STRICT_FMAXNUM:
925  case ISD::STRICT_FMINNUM:
926  case ISD::STRICT_FCEIL:
927  case ISD::STRICT_FFLOOR:
928  case ISD::STRICT_FROUND:
929  case ISD::STRICT_FTRUNC:
930  SplitVecRes_StrictFPOp(N, Lo, Hi);
931  break;
932  case ISD::UADDO:
933  case ISD::SADDO:
934  case ISD::USUBO:
935  case ISD::SSUBO:
936  case ISD::UMULO:
937  case ISD::SMULO:
938  SplitVecRes_OverflowOp(N, ResNo, Lo, Hi);
939  break;
940  case ISD::SMULFIX:
941  case ISD::UMULFIX:
942  SplitVecRes_MULFIX(N, Lo, Hi);
943  break;
944  }
945 
946  // If Lo/Hi is null, the sub-method took care of registering results etc.
947  if (Lo.getNode())
948  SetSplitVector(SDValue(N, ResNo), Lo, Hi);
949 }
950 
951 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
952  SDValue &Hi) {
953  SDValue LHSLo, LHSHi;
954  GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
955  SDValue RHSLo, RHSHi;
956  GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
957  SDLoc dl(N);
958 
959  const SDNodeFlags Flags = N->getFlags();
960  unsigned Opcode = N->getOpcode();
961  Lo = DAG.getNode(Opcode, dl, LHSLo.getValueType(), LHSLo, RHSLo, Flags);
962  Hi = DAG.getNode(Opcode, dl, LHSHi.getValueType(), LHSHi, RHSHi, Flags);
963 }
964 
965 void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,
966  SDValue &Hi) {
967  SDValue Op0Lo, Op0Hi;
968  GetSplitVector(N->getOperand(0), Op0Lo, Op0Hi);
969  SDValue Op1Lo, Op1Hi;
970  GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi);
971  SDValue Op2Lo, Op2Hi;
972  GetSplitVector(N->getOperand(2), Op2Lo, Op2Hi);
973  SDLoc dl(N);
974 
975  Lo = DAG.getNode(N->getOpcode(), dl, Op0Lo.getValueType(),
976  Op0Lo, Op1Lo, Op2Lo);
977  Hi = DAG.getNode(N->getOpcode(), dl, Op0Hi.getValueType(),
978  Op0Hi, Op1Hi, Op2Hi);
979 }
980 
981 void DAGTypeLegalizer::SplitVecRes_MULFIX(SDNode *N, SDValue &Lo, SDValue &Hi) {
982  SDValue LHSLo, LHSHi;
983  GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
984  SDValue RHSLo, RHSHi;
985  GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
986  SDLoc dl(N);
987  SDValue Op2 = N->getOperand(2);
988 
989  unsigned Opcode = N->getOpcode();
990  Lo = DAG.getNode(Opcode, dl, LHSLo.getValueType(), LHSLo, RHSLo, Op2);
991  Hi = DAG.getNode(Opcode, dl, LHSHi.getValueType(), LHSHi, RHSHi, Op2);
992 }
993 
994 void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
995  SDValue &Hi) {
996  // We know the result is a vector. The input may be either a vector or a
997  // scalar value.
998  EVT LoVT, HiVT;
999  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1000  SDLoc dl(N);
1001 
1002  SDValue InOp = N->getOperand(0);
1003  EVT InVT = InOp.getValueType();
1004 
1005  // Handle some special cases efficiently.
1006  switch (getTypeAction(InVT)) {
1013  break;
1016  // A scalar to vector conversion, where the scalar needs expansion.
1017  // If the vector is being split in two then we can just convert the
1018  // expanded pieces.
1019  if (LoVT == HiVT) {
1020  GetExpandedOp(InOp, Lo, Hi);
1021  if (DAG.getDataLayout().isBigEndian())
1022  std::swap(Lo, Hi);
1023  Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
1024  Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
1025  return;
1026  }
1027  break;
1029  // If the input is a vector that needs to be split, convert each split
1030  // piece of the input now.
1031  GetSplitVector(InOp, Lo, Hi);
1032  Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
1033  Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
1034  return;
1035  }
1036 
1037  // In the general case, convert the input to an integer and split it by hand.
1038  EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
1039  EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
1040  if (DAG.getDataLayout().isBigEndian())
1041  std::swap(LoIntVT, HiIntVT);
1042 
1043  SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
1044 
1045  if (DAG.getDataLayout().isBigEndian())
1046  std::swap(Lo, Hi);
1047  Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
1048  Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
1049 }
1050 
1051 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
1052  SDValue &Hi) {
1053  EVT LoVT, HiVT;
1054  SDLoc dl(N);
1055  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1056  unsigned LoNumElts = LoVT.getVectorNumElements();
1057  SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
1058  Lo = DAG.getBuildVector(LoVT, dl, LoOps);
1059 
1060  SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
1061  Hi = DAG.getBuildVector(HiVT, dl, HiOps);
1062 }
1063 
1064 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
1065  SDValue &Hi) {
1066  assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
1067  SDLoc dl(N);
1068  unsigned NumSubvectors = N->getNumOperands() / 2;
1069  if (NumSubvectors == 1) {
1070  Lo = N->getOperand(0);
1071  Hi = N->getOperand(1);
1072  return;
1073  }
1074 
1075  EVT LoVT, HiVT;
1076  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1077 
1078  SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
1079  Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps);
1080 
1081  SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
1082  Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps);
1083 }
1084 
1085 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
1086  SDValue &Hi) {
1087  SDValue Vec = N->getOperand(0);
1088  SDValue Idx = N->getOperand(1);
1089  SDLoc dl(N);
1090 
1091  EVT LoVT, HiVT;
1092  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1093 
1094  Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
1095  uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1096  Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
1097  DAG.getConstant(IdxVal + LoVT.getVectorNumElements(), dl,
1098  TLI.getVectorIdxTy(DAG.getDataLayout())));
1099 }
1100 
1101 void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
1102  SDValue &Hi) {
1103  SDValue Vec = N->getOperand(0);
1104  SDValue SubVec = N->getOperand(1);
1105  SDValue Idx = N->getOperand(2);
1106  SDLoc dl(N);
1107  GetSplitVector(Vec, Lo, Hi);
1108 
1109  EVT VecVT = Vec.getValueType();
1110  unsigned VecElems = VecVT.getVectorNumElements();
1111  unsigned SubElems = SubVec.getValueType().getVectorNumElements();
1112 
1113  // If we know the index is 0, and we know the subvector doesn't cross the
1114  // boundary between the halves, we can avoid spilling the vector, and insert
1115  // into the lower half of the split vector directly.
1116  // TODO: The IdxVal == 0 constraint is artificial, we could do this whenever
1117  // the index is constant and there is no boundary crossing. But those cases
1118  // don't seem to get hit in practice.
1119  if (ConstantSDNode *ConstIdx = dyn_cast<ConstantSDNode>(Idx)) {
1120  unsigned IdxVal = ConstIdx->getZExtValue();
1121  if ((IdxVal == 0) && (IdxVal + SubElems <= VecElems / 2)) {
1122  EVT LoVT, HiVT;
1123  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1124  Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx);
1125  return;
1126  }
1127  }
1128 
1129  // Spill the vector to the stack.
1130  SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1131  SDValue Store =
1132  DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, MachinePointerInfo());
1133 
1134  // Store the new subvector into the specified index.
1135  SDValue SubVecPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
1136  Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
1137  unsigned Alignment = DAG.getDataLayout().getPrefTypeAlignment(VecType);
1138  Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, MachinePointerInfo());
1139 
1140  // Load the Lo part from the stack slot.
1141  Lo =
1142  DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo());
1143 
1144  // Increment the pointer to the other part.
1145  unsigned IncrementSize = Lo.getValueSizeInBits() / 8;
1146  StackPtr =
1147  DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
1148  DAG.getConstant(IncrementSize, dl, StackPtr.getValueType()));
1149 
1150  // Load the Hi part from the stack slot.
1151  Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
1152  MinAlign(Alignment, IncrementSize));
1153 }
1154 
1155 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
1156  SDValue &Hi) {
1157  SDLoc dl(N);
1158  GetSplitVector(N->getOperand(0), Lo, Hi);
1159  Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
1160  Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
1161 }
1162 
1163 void DAGTypeLegalizer::SplitVecRes_FCOPYSIGN(SDNode *N, SDValue &Lo,
1164  SDValue &Hi) {
1165  SDValue LHSLo, LHSHi;
1166  GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
1167  SDLoc DL(N);
1168 
1169  SDValue RHSLo, RHSHi;
1170  SDValue RHS = N->getOperand(1);
1171  EVT RHSVT = RHS.getValueType();
1172  if (getTypeAction(RHSVT) == TargetLowering::TypeSplitVector)
1173  GetSplitVector(RHS, RHSLo, RHSHi);
1174  else
1175  std::tie(RHSLo, RHSHi) = DAG.SplitVector(RHS, SDLoc(RHS));
1176 
1177 
1178  Lo = DAG.getNode(ISD::FCOPYSIGN, DL, LHSLo.getValueType(), LHSLo, RHSLo);
1179  Hi = DAG.getNode(ISD::FCOPYSIGN, DL, LHSHi.getValueType(), LHSHi, RHSHi);
1180 }
1181 
1182 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
1183  SDValue &Hi) {
1184  SDValue LHSLo, LHSHi;
1185  GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
1186  SDLoc dl(N);
1187 
1188  EVT LoVT, HiVT;
1189  std::tie(LoVT, HiVT) =
1190  DAG.GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT());
1191 
1192  Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
1193  DAG.getValueType(LoVT));
1194  Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
1195  DAG.getValueType(HiVT));
1196 }
1197 
1198 void DAGTypeLegalizer::SplitVecRes_ExtVecInRegOp(SDNode *N, SDValue &Lo,
1199  SDValue &Hi) {
1200  unsigned Opcode = N->getOpcode();
1201  SDValue N0 = N->getOperand(0);
1202 
1203  SDLoc dl(N);
1204  SDValue InLo, InHi;
1205 
1206  if (getTypeAction(N0.getValueType()) == TargetLowering::TypeSplitVector)
1207  GetSplitVector(N0, InLo, InHi);
1208  else
1209  std::tie(InLo, InHi) = DAG.SplitVectorOperand(N, 0);
1210 
1211  EVT InLoVT = InLo.getValueType();
1212  unsigned InNumElements = InLoVT.getVectorNumElements();
1213 
1214  EVT OutLoVT, OutHiVT;
1215  std::tie(OutLoVT, OutHiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1216  unsigned OutNumElements = OutLoVT.getVectorNumElements();
1217  assert((2 * OutNumElements) <= InNumElements &&
1218  "Illegal extend vector in reg split");
1219 
1220  // *_EXTEND_VECTOR_INREG instructions extend the lowest elements of the
1221  // input vector (i.e. we only use InLo):
1222  // OutLo will extend the first OutNumElements from InLo.
1223  // OutHi will extend the next OutNumElements from InLo.
1224 
1225  // Shuffle the elements from InLo for OutHi into the bottom elements to
1226  // create a 'fake' InHi.
1227  SmallVector<int, 8> SplitHi(InNumElements, -1);
1228  for (unsigned i = 0; i != OutNumElements; ++i)
1229  SplitHi[i] = i + OutNumElements;
1230  InHi = DAG.getVectorShuffle(InLoVT, dl, InLo, DAG.getUNDEF(InLoVT), SplitHi);
1231 
1232  Lo = DAG.getNode(Opcode, dl, OutLoVT, InLo);
1233  Hi = DAG.getNode(Opcode, dl, OutHiVT, InHi);
1234 }
1235 
1236 void DAGTypeLegalizer::SplitVecRes_StrictFPOp(SDNode *N, SDValue &Lo,
1237  SDValue &Hi) {
1238  unsigned NumOps = N->getNumOperands();
1239  SDValue Chain = N->getOperand(0);
1240  EVT LoVT, HiVT;
1241  SDLoc dl(N);
1242  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1243 
1246 
1247  // The Chain is the first operand.
1248  OpsLo.push_back(Chain);
1249  OpsHi.push_back(Chain);
1250 
1251  // Now process the remaining operands.
1252  for (unsigned i = 1; i < NumOps; ++i) {
1253  SDValue Op = N->getOperand(i);
1254  SDValue OpLo = Op;
1255  SDValue OpHi = Op;
1256 
1257  EVT InVT = Op.getValueType();
1258  if (InVT.isVector()) {
1259  // If the input also splits, handle it directly for a
1260  // compile time speedup. Otherwise split it by hand.
1261  if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)
1262  GetSplitVector(Op, OpLo, OpHi);
1263  else
1264  std::tie(OpLo, OpHi) = DAG.SplitVectorOperand(N, i);
1265  }
1266 
1267  OpsLo.push_back(OpLo);
1268  OpsHi.push_back(OpHi);
1269  }
1270 
1271  EVT LoValueVTs[] = {LoVT, MVT::Other};
1272  EVT HiValueVTs[] = {HiVT, MVT::Other};
1273  Lo = DAG.getNode(N->getOpcode(), dl, LoValueVTs, OpsLo);
1274  Hi = DAG.getNode(N->getOpcode(), dl, HiValueVTs, OpsHi);
1275 
1276  // Build a factor node to remember that this Op is independent of the
1277  // other one.
1278  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1279  Lo.getValue(1), Hi.getValue(1));
1280 
1281  // Legalize the chain result - switch anything that used the old chain to
1282  // use the new one.
1283  ReplaceValueWith(SDValue(N, 1), Chain);
1284 }
1285 
1286 void DAGTypeLegalizer::SplitVecRes_OverflowOp(SDNode *N, unsigned ResNo,
1287  SDValue &Lo, SDValue &Hi) {
1288  SDLoc dl(N);
1289  EVT ResVT = N->getValueType(0);
1290  EVT OvVT = N->getValueType(1);
1291  EVT LoResVT, HiResVT, LoOvVT, HiOvVT;
1292  std::tie(LoResVT, HiResVT) = DAG.GetSplitDestVTs(ResVT);
1293  std::tie(LoOvVT, HiOvVT) = DAG.GetSplitDestVTs(OvVT);
1294 
1295  SDValue LoLHS, HiLHS, LoRHS, HiRHS;
1296  if (getTypeAction(ResVT) == TargetLowering::TypeSplitVector) {
1297  GetSplitVector(N->getOperand(0), LoLHS, HiLHS);
1298  GetSplitVector(N->getOperand(1), LoRHS, HiRHS);
1299  } else {
1300  std::tie(LoLHS, HiLHS) = DAG.SplitVectorOperand(N, 0);
1301  std::tie(LoRHS, HiRHS) = DAG.SplitVectorOperand(N, 1);
1302  }
1303 
1304  unsigned Opcode = N->getOpcode();
1305  SDVTList LoVTs = DAG.getVTList(LoResVT, LoOvVT);
1306  SDVTList HiVTs = DAG.getVTList(HiResVT, HiOvVT);
1307  SDNode *LoNode = DAG.getNode(Opcode, dl, LoVTs, LoLHS, LoRHS).getNode();
1308  SDNode *HiNode = DAG.getNode(Opcode, dl, HiVTs, HiLHS, HiRHS).getNode();
1309 
1310  Lo = SDValue(LoNode, ResNo);
1311  Hi = SDValue(HiNode, ResNo);
1312 
1313  // Replace the other vector result not being explicitly split here.
1314  unsigned OtherNo = 1 - ResNo;
1315  EVT OtherVT = N->getValueType(OtherNo);
1316  if (getTypeAction(OtherVT) == TargetLowering::TypeSplitVector) {
1317  SetSplitVector(SDValue(N, OtherNo),
1318  SDValue(LoNode, OtherNo), SDValue(HiNode, OtherNo));
1319  } else {
1320  SDValue OtherVal = DAG.getNode(
1321  ISD::CONCAT_VECTORS, dl, OtherVT,
1322  SDValue(LoNode, OtherNo), SDValue(HiNode, OtherNo));
1323  ReplaceValueWith(SDValue(N, OtherNo), OtherVal);
1324  }
1325 }
1326 
1327 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
1328  SDValue &Hi) {
1329  SDValue Vec = N->getOperand(0);
1330  SDValue Elt = N->getOperand(1);
1331  SDValue Idx = N->getOperand(2);
1332  SDLoc dl(N);
1333  GetSplitVector(Vec, Lo, Hi);
1334 
1335  if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
1336  unsigned IdxVal = CIdx->getZExtValue();
1337  unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
1338  if (IdxVal < LoNumElts)
1339  Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
1340  Lo.getValueType(), Lo, Elt, Idx);
1341  else
1342  Hi =
1343  DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
1344  DAG.getConstant(IdxVal - LoNumElts, dl,
1345  TLI.getVectorIdxTy(DAG.getDataLayout())));
1346  return;
1347  }
1348 
1349  // See if the target wants to custom expand this node.
1350  if (CustomLowerNode(N, N->getValueType(0), true))
1351  return;
1352 
1353  // Make the vector elements byte-addressable if they aren't already.
1354  EVT VecVT = Vec.getValueType();
1355  EVT EltVT = VecVT.getVectorElementType();
1356  if (VecVT.getScalarSizeInBits() < 8) {
1357  EltVT = MVT::i8;
1358  VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
1359  VecVT.getVectorNumElements());
1360  Vec = DAG.getNode(ISD::ANY_EXTEND, dl, VecVT, Vec);
1361  // Extend the element type to match if needed.
1362  if (EltVT.bitsGT(Elt.getValueType()))
1363  Elt = DAG.getNode(ISD::ANY_EXTEND, dl, EltVT, Elt);
1364  }
1365 
1366  // Spill the vector to the stack.
1367  SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1368  auto &MF = DAG.getMachineFunction();
1369  auto FrameIndex = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1370  auto PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIndex);
1371  SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo);
1372 
1373  // Store the new element. This may be larger than the vector element type,
1374  // so use a truncating store.
1375  SDValue EltPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
1376  Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
1377  unsigned Alignment = DAG.getDataLayout().getPrefTypeAlignment(VecType);
1378  Store = DAG.getTruncStore(Store, dl, Elt, EltPtr,
1380 
1381  EVT LoVT, HiVT;
1382  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VecVT);
1383 
1384  // Load the Lo part from the stack slot.
1385  Lo = DAG.getLoad(LoVT, dl, Store, StackPtr, PtrInfo);
1386 
1387  // Increment the pointer to the other part.
1388  unsigned IncrementSize = LoVT.getSizeInBits() / 8;
1389  StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
1390  DAG.getConstant(IncrementSize, dl,
1391  StackPtr.getValueType()));
1392 
1393  // Load the Hi part from the stack slot.
1394  Hi = DAG.getLoad(HiVT, dl, Store, StackPtr,
1395  PtrInfo.getWithOffset(IncrementSize),
1396  MinAlign(Alignment, IncrementSize));
1397 
1398  // If we adjusted the original type, we need to truncate the results.
1399  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1400  if (LoVT != Lo.getValueType())
1401  Lo = DAG.getNode(ISD::TRUNCATE, dl, LoVT, Lo);
1402  if (HiVT != Hi.getValueType())
1403  Hi = DAG.getNode(ISD::TRUNCATE, dl, HiVT, Hi);
1404 }
1405 
1406 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
1407  SDValue &Hi) {
1408  EVT LoVT, HiVT;
1409  SDLoc dl(N);
1410  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1411  Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
1412  Hi = DAG.getUNDEF(HiVT);
1413 }
1414 
1415 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
1416  SDValue &Hi) {
1417  assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
1418  EVT LoVT, HiVT;
1419  SDLoc dl(LD);
1420  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(LD->getValueType(0));
1421 
1423  SDValue Ch = LD->getChain();
1424  SDValue Ptr = LD->getBasePtr();
1425  SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
1426  EVT MemoryVT = LD->getMemoryVT();
1427  unsigned Alignment = LD->getOriginalAlignment();
1428  MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
1429  AAMDNodes AAInfo = LD->getAAInfo();
1430 
1431  EVT LoMemVT, HiMemVT;
1432  std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1433 
1434  Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
1435  LD->getPointerInfo(), LoMemVT, Alignment, MMOFlags, AAInfo);
1436 
1437  unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1438  Ptr = DAG.getObjectPtrOffset(dl, Ptr, IncrementSize);
1439  Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
1440  LD->getPointerInfo().getWithOffset(IncrementSize), HiMemVT,
1441  Alignment, MMOFlags, AAInfo);
1442 
1443  // Build a factor node to remember that this load is independent of the
1444  // other one.
1445  Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1446  Hi.getValue(1));
1447 
1448  // Legalize the chain result - switch anything that used the old chain to
1449  // use the new one.
1450  ReplaceValueWith(SDValue(LD, 1), Ch);
1451 }
1452 
1453 void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,
1454  SDValue &Lo, SDValue &Hi) {
1455  EVT LoVT, HiVT;
1456  SDLoc dl(MLD);
1457  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0));
1458 
1459  SDValue Ch = MLD->getChain();
1460  SDValue Ptr = MLD->getBasePtr();
1461  SDValue Mask = MLD->getMask();
1462  SDValue PassThru = MLD->getPassThru();
1463  unsigned Alignment = MLD->getOriginalAlignment();
1465 
1466  // if Alignment is equal to the vector size,
1467  // take the half of it for the second part
1468  unsigned SecondHalfAlignment =
1469  (Alignment == MLD->getValueType(0).getSizeInBits()/8) ?
1470  Alignment/2 : Alignment;
1471 
1472  // Split Mask operand
1473  SDValue MaskLo, MaskHi;
1474  if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1475  GetSplitVector(Mask, MaskLo, MaskHi);
1476  else
1477  std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1478 
1479  EVT MemoryVT = MLD->getMemoryVT();
1480  EVT LoMemVT, HiMemVT;
1481  std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1482 
1483  SDValue PassThruLo, PassThruHi;
1484  if (getTypeAction(PassThru.getValueType()) == TargetLowering::TypeSplitVector)
1485  GetSplitVector(PassThru, PassThruLo, PassThruHi);
1486  else
1487  std::tie(PassThruLo, PassThruHi) = DAG.SplitVector(PassThru, dl);
1488 
1492  Alignment, MLD->getAAInfo(), MLD->getRanges());
1493 
1494  Lo = DAG.getMaskedLoad(LoVT, dl, Ch, Ptr, MaskLo, PassThruLo, LoMemVT, MMO,
1495  ExtType, MLD->isExpandingLoad());
1496 
1497  Ptr = TLI.IncrementMemoryAddress(Ptr, MaskLo, dl, LoMemVT, DAG,
1498  MLD->isExpandingLoad());
1499  unsigned HiOffset = LoMemVT.getStoreSize();
1500 
1503  HiMemVT.getStoreSize(), SecondHalfAlignment, MLD->getAAInfo(),
1504  MLD->getRanges());
1505 
1506  Hi = DAG.getMaskedLoad(HiVT, dl, Ch, Ptr, MaskHi, PassThruHi, HiMemVT, MMO,
1507  ExtType, MLD->isExpandingLoad());
1508 
1509  // Build a factor node to remember that this load is independent of the
1510  // other one.
1511  Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1512  Hi.getValue(1));
1513 
1514  // Legalize the chain result - switch anything that used the old chain to
1515  // use the new one.
1516  ReplaceValueWith(SDValue(MLD, 1), Ch);
1517 
1518 }
1519 
1520 void DAGTypeLegalizer::SplitVecRes_MGATHER(MaskedGatherSDNode *MGT,
1521  SDValue &Lo, SDValue &Hi) {
1522  EVT LoVT, HiVT;
1523  SDLoc dl(MGT);
1524  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
1525 
1526  SDValue Ch = MGT->getChain();
1527  SDValue Ptr = MGT->getBasePtr();
1528  SDValue Mask = MGT->getMask();
1529  SDValue PassThru = MGT->getPassThru();
1530  SDValue Index = MGT->getIndex();
1531  SDValue Scale = MGT->getScale();
1532  unsigned Alignment = MGT->getOriginalAlignment();
1533 
1534  // Split Mask operand
1535  SDValue MaskLo, MaskHi;
1536  if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1537  GetSplitVector(Mask, MaskLo, MaskHi);
1538  else
1539  std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1540 
1541  EVT MemoryVT = MGT->getMemoryVT();
1542  EVT LoMemVT, HiMemVT;
1543  // Split MemoryVT
1544  std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1545 
1546  SDValue PassThruLo, PassThruHi;
1547  if (getTypeAction(PassThru.getValueType()) == TargetLowering::TypeSplitVector)
1548  GetSplitVector(PassThru, PassThruLo, PassThruHi);
1549  else
1550  std::tie(PassThruLo, PassThruHi) = DAG.SplitVector(PassThru, dl);
1551 
1552  SDValue IndexHi, IndexLo;
1553  if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
1554  GetSplitVector(Index, IndexLo, IndexHi);
1555  else
1556  std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, dl);
1557 
1561  Alignment, MGT->getAAInfo(), MGT->getRanges());
1562 
1563  SDValue OpsLo[] = {Ch, PassThruLo, MaskLo, Ptr, IndexLo, Scale};
1564  Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl, OpsLo,
1565  MMO);
1566 
1567  SDValue OpsHi[] = {Ch, PassThruHi, MaskHi, Ptr, IndexHi, Scale};
1568  Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl, OpsHi,
1569  MMO);
1570 
1571  // Build a factor node to remember that this load is independent of the
1572  // other one.
1573  Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1574  Hi.getValue(1));
1575 
1576  // Legalize the chain result - switch anything that used the old chain to
1577  // use the new one.
1578  ReplaceValueWith(SDValue(MGT, 1), Ch);
1579 }
1580 
1581 
1582 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
1583  assert(N->getValueType(0).isVector() &&
1584  N->getOperand(0).getValueType().isVector() &&
1585  "Operand types must be vectors");
1586 
1587  EVT LoVT, HiVT;
1588  SDLoc DL(N);
1589  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1590 
1591  // If the input also splits, handle it directly. Otherwise split it by hand.
1592  SDValue LL, LH, RL, RH;
1593  if (getTypeAction(N->getOperand(0).getValueType()) ==
1595  GetSplitVector(N->getOperand(0), LL, LH);
1596  else
1597  std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
1598 
1599  if (getTypeAction(N->getOperand(1).getValueType()) ==
1601  GetSplitVector(N->getOperand(1), RL, RH);
1602  else
1603  std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
1604 
1605  Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
1606  Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
1607 }
1608 
1609 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
1610  SDValue &Hi) {
1611  // Get the dest types - they may not match the input types, e.g. int_to_fp.
1612  EVT LoVT, HiVT;
1613  SDLoc dl(N);
1614  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1615 
1616  // If the input also splits, handle it directly for a compile time speedup.
1617  // Otherwise split it by hand.
1618  EVT InVT = N->getOperand(0).getValueType();
1619  if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)
1620  GetSplitVector(N->getOperand(0), Lo, Hi);
1621  else
1622  std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0);
1623 
1624  if (N->getOpcode() == ISD::FP_ROUND) {
1625  Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
1626  Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
1627  } else {
1628  Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1629  Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1630  }
1631 }
1632 
1633 void DAGTypeLegalizer::SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo,
1634  SDValue &Hi) {
1635  SDLoc dl(N);
1636  EVT SrcVT = N->getOperand(0).getValueType();
1637  EVT DestVT = N->getValueType(0);
1638  EVT LoVT, HiVT;
1639  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT);
1640 
1641  // We can do better than a generic split operation if the extend is doing
1642  // more than just doubling the width of the elements and the following are
1643  // true:
1644  // - The number of vector elements is even,
1645  // - the source type is legal,
1646  // - the type of a split source is illegal,
1647  // - the type of an extended (by doubling element size) source is legal, and
1648  // - the type of that extended source when split is legal.
1649  //
1650  // This won't necessarily completely legalize the operation, but it will
1651  // more effectively move in the right direction and prevent falling down
1652  // to scalarization in many cases due to the input vector being split too
1653  // far.
1654  unsigned NumElements = SrcVT.getVectorNumElements();
1655  if ((NumElements & 1) == 0 &&
1656  SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) {
1657  LLVMContext &Ctx = *DAG.getContext();
1658  EVT NewSrcVT = SrcVT.widenIntegerVectorElementType(Ctx);
1659  EVT SplitSrcVT = SrcVT.getHalfNumVectorElementsVT(Ctx);
1660 
1661  EVT SplitLoVT, SplitHiVT;
1662  std::tie(SplitLoVT, SplitHiVT) = DAG.GetSplitDestVTs(NewSrcVT);
1663  if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) &&
1664  TLI.isTypeLegal(NewSrcVT) && TLI.isTypeLegal(SplitLoVT)) {
1665  LLVM_DEBUG(dbgs() << "Split vector extend via incremental extend:";
1666  N->dump(&DAG); dbgs() << "\n");
1667  // Extend the source vector by one step.
1668  SDValue NewSrc =
1669  DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0));
1670  // Get the low and high halves of the new, extended one step, vector.
1671  std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl);
1672  // Extend those vector halves the rest of the way.
1673  Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1674  Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1675  return;
1676  }
1677  }
1678  // Fall back to the generic unary operator splitting otherwise.
1679  SplitVecRes_UnaryOp(N, Lo, Hi);
1680 }
1681 
1682 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
1683  SDValue &Lo, SDValue &Hi) {
1684  // The low and high parts of the original input give four input vectors.
1685  SDValue Inputs[4];
1686  SDLoc dl(N);
1687  GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
1688  GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
1689  EVT NewVT = Inputs[0].getValueType();
1690  unsigned NewElts = NewVT.getVectorNumElements();
1691 
1692  // If Lo or Hi uses elements from at most two of the four input vectors, then
1693  // express it as a vector shuffle of those two inputs. Otherwise extract the
1694  // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
1696  for (unsigned High = 0; High < 2; ++High) {
1697  SDValue &Output = High ? Hi : Lo;
1698 
1699  // Build a shuffle mask for the output, discovering on the fly which
1700  // input vectors to use as shuffle operands (recorded in InputUsed).
1701  // If building a suitable shuffle vector proves too hard, then bail
1702  // out with useBuildVector set.
1703  unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
1704  unsigned FirstMaskIdx = High * NewElts;
1705  bool useBuildVector = false;
1706  for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1707  // The mask element. This indexes into the input.
1708  int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1709 
1710  // The input vector this mask element indexes into.
1711  unsigned Input = (unsigned)Idx / NewElts;
1712 
1713  if (Input >= array_lengthof(Inputs)) {
1714  // The mask element does not index into any input vector.
1715  Ops.push_back(-1);
1716  continue;
1717  }
1718 
1719  // Turn the index into an offset from the start of the input vector.
1720  Idx -= Input * NewElts;
1721 
1722  // Find or create a shuffle vector operand to hold this input.
1723  unsigned OpNo;
1724  for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
1725  if (InputUsed[OpNo] == Input) {
1726  // This input vector is already an operand.
1727  break;
1728  } else if (InputUsed[OpNo] == -1U) {
1729  // Create a new operand for this input vector.
1730  InputUsed[OpNo] = Input;
1731  break;
1732  }
1733  }
1734 
1735  if (OpNo >= array_lengthof(InputUsed)) {
1736  // More than two input vectors used! Give up on trying to create a
1737  // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
1738  useBuildVector = true;
1739  break;
1740  }
1741 
1742  // Add the mask index for the new shuffle vector.
1743  Ops.push_back(Idx + OpNo * NewElts);
1744  }
1745 
1746  if (useBuildVector) {
1747  EVT EltVT = NewVT.getVectorElementType();
1749 
1750  // Extract the input elements by hand.
1751  for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1752  // The mask element. This indexes into the input.
1753  int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1754 
1755  // The input vector this mask element indexes into.
1756  unsigned Input = (unsigned)Idx / NewElts;
1757 
1758  if (Input >= array_lengthof(Inputs)) {
1759  // The mask element is "undef" or indexes off the end of the input.
1760  SVOps.push_back(DAG.getUNDEF(EltVT));
1761  continue;
1762  }
1763 
1764  // Turn the index into an offset from the start of the input vector.
1765  Idx -= Input * NewElts;
1766 
1767  // Extract the vector element by hand.
1768  SVOps.push_back(DAG.getNode(
1769  ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Inputs[Input],
1770  DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
1771  }
1772 
1773  // Construct the Lo/Hi output using a BUILD_VECTOR.
1774  Output = DAG.getBuildVector(NewVT, dl, SVOps);
1775  } else if (InputUsed[0] == -1U) {
1776  // No input vectors were used! The result is undefined.
1777  Output = DAG.getUNDEF(NewVT);
1778  } else {
1779  SDValue Op0 = Inputs[InputUsed[0]];
1780  // If only one input was used, use an undefined vector for the other.
1781  SDValue Op1 = InputUsed[1] == -1U ?
1782  DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
1783  // At least one input vector was used. Create a new shuffle vector.
1784  Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, Ops);
1785  }
1786 
1787  Ops.clear();
1788  }
1789 }
1790 
1791 
1792 //===----------------------------------------------------------------------===//
1793 // Operand Vector Splitting
1794 //===----------------------------------------------------------------------===//
1795 
1796 /// This method is called when the specified operand of the specified node is
1797 /// found to need vector splitting. At this point, all of the result types of
1798 /// the node are known to be legal, but other operands of the node may need
1799 /// legalization as well as the specified one.
1800 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
1801  LLVM_DEBUG(dbgs() << "Split node operand: "; N->dump(&DAG); dbgs() << "\n");
1802  SDValue Res = SDValue();
1803 
1804  // See if the target wants to custom split this node.
1805  if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1806  return false;
1807 
1808  if (!Res.getNode()) {
1809  switch (N->getOpcode()) {
1810  default:
1811 #ifndef NDEBUG
1812  dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
1813  N->dump(&DAG);
1814  dbgs() << "\n";
1815 #endif
1816  report_fatal_error("Do not know how to split this operator's "
1817  "operand!\n");
1818 
1819  case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
1820  case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
1821  case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
1822  case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
1823  case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
1824  case ISD::TRUNCATE:
1825  Res = SplitVecOp_TruncateHelper(N);
1826  break;
1827  case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
1828  case ISD::FCOPYSIGN: Res = SplitVecOp_FCOPYSIGN(N); break;
1829  case ISD::STORE:
1830  Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
1831  break;
1832  case ISD::MSTORE:
1833  Res = SplitVecOp_MSTORE(cast<MaskedStoreSDNode>(N), OpNo);
1834  break;
1835  case ISD::MSCATTER:
1836  Res = SplitVecOp_MSCATTER(cast<MaskedScatterSDNode>(N), OpNo);
1837  break;
1838  case ISD::MGATHER:
1839  Res = SplitVecOp_MGATHER(cast<MaskedGatherSDNode>(N), OpNo);
1840  break;
1841  case ISD::VSELECT:
1842  Res = SplitVecOp_VSELECT(N, OpNo);
1843  break;
1844  case ISD::SINT_TO_FP:
1845  case ISD::UINT_TO_FP:
1846  if (N->getValueType(0).bitsLT(N->getOperand(0).getValueType()))
1847  Res = SplitVecOp_TruncateHelper(N);
1848  else
1849  Res = SplitVecOp_UnaryOp(N);
1850  break;
1851  case ISD::FP_TO_SINT:
1852  case ISD::FP_TO_UINT:
1853  case ISD::CTTZ:
1854  case ISD::CTLZ:
1855  case ISD::CTPOP:
1856  case ISD::FP_EXTEND:
1857  case ISD::SIGN_EXTEND:
1858  case ISD::ZERO_EXTEND:
1859  case ISD::ANY_EXTEND:
1860  case ISD::FTRUNC:
1861  case ISD::FCANONICALIZE:
1862  Res = SplitVecOp_UnaryOp(N);
1863  break;
1864 
1868  Res = SplitVecOp_ExtVecInRegOp(N);
1869  break;
1870 
1871  case ISD::VECREDUCE_FADD:
1872  case ISD::VECREDUCE_FMUL:
1873  case ISD::VECREDUCE_ADD:
1874  case ISD::VECREDUCE_MUL:
1875  case ISD::VECREDUCE_AND:
1876  case ISD::VECREDUCE_OR:
1877  case ISD::VECREDUCE_XOR:
1878  case ISD::VECREDUCE_SMAX:
1879  case ISD::VECREDUCE_SMIN:
1880  case ISD::VECREDUCE_UMAX:
1881  case ISD::VECREDUCE_UMIN:
1882  case ISD::VECREDUCE_FMAX:
1883  case ISD::VECREDUCE_FMIN:
1884  Res = SplitVecOp_VECREDUCE(N, OpNo);
1885  break;
1886  }
1887  }
1888 
1889  // If the result is null, the sub-method took care of registering results etc.
1890  if (!Res.getNode()) return false;
1891 
1892  // If the result is N, the sub-method updated N in place. Tell the legalizer
1893  // core about this.
1894  if (Res.getNode() == N)
1895  return true;
1896 
1897  assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1898  "Invalid operand expansion");
1899 
1900  ReplaceValueWith(SDValue(N, 0), Res);
1901  return false;
1902 }
1903 
1904 SDValue DAGTypeLegalizer::SplitVecOp_VSELECT(SDNode *N, unsigned OpNo) {
1905  // The only possibility for an illegal operand is the mask, since result type
1906  // legalization would have handled this node already otherwise.
1907  assert(OpNo == 0 && "Illegal operand must be mask");
1908 
1909  SDValue Mask = N->getOperand(0);
1910  SDValue Src0 = N->getOperand(1);
1911  SDValue Src1 = N->getOperand(2);
1912  EVT Src0VT = Src0.getValueType();
1913  SDLoc DL(N);
1914  assert(Mask.getValueType().isVector() && "VSELECT without a vector mask?");
1915 
1916  SDValue Lo, Hi;
1917  GetSplitVector(N->getOperand(0), Lo, Hi);
1918  assert(Lo.getValueType() == Hi.getValueType() &&
1919  "Lo and Hi have differing types");
1920 
1921  EVT LoOpVT, HiOpVT;
1922  std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT);
1923  assert(LoOpVT == HiOpVT && "Asymmetric vector split?");
1924 
1925  SDValue LoOp0, HiOp0, LoOp1, HiOp1, LoMask, HiMask;
1926  std::tie(LoOp0, HiOp0) = DAG.SplitVector(Src0, DL);
1927  std::tie(LoOp1, HiOp1) = DAG.SplitVector(Src1, DL);
1928  std::tie(LoMask, HiMask) = DAG.SplitVector(Mask, DL);
1929 
1930  SDValue LoSelect =
1931  DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1);
1932  SDValue HiSelect =
1933  DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);
1934 
1935  return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect);
1936 }
1937 
1938 SDValue DAGTypeLegalizer::SplitVecOp_VECREDUCE(SDNode *N, unsigned OpNo) {
1939  EVT ResVT = N->getValueType(0);
1940  SDValue Lo, Hi;
1941  SDLoc dl(N);
1942 
1943  SDValue VecOp = N->getOperand(OpNo);
1944  EVT VecVT = VecOp.getValueType();
1945  assert(VecVT.isVector() && "Can only split reduce vector operand");
1946  GetSplitVector(VecOp, Lo, Hi);
1947  EVT LoOpVT, HiOpVT;
1948  std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(VecVT);
1949 
1950  bool NoNaN = N->getFlags().hasNoNaNs();
1951  unsigned CombineOpc = 0;
1952  switch (N->getOpcode()) {
1953  case ISD::VECREDUCE_FADD: CombineOpc = ISD::FADD; break;
1954  case ISD::VECREDUCE_FMUL: CombineOpc = ISD::FMUL; break;
1955  case ISD::VECREDUCE_ADD: CombineOpc = ISD::ADD; break;
1956  case ISD::VECREDUCE_MUL: CombineOpc = ISD::MUL; break;
1957  case ISD::VECREDUCE_AND: CombineOpc = ISD::AND; break;
1958  case ISD::VECREDUCE_OR: CombineOpc = ISD::OR; break;
1959  case ISD::VECREDUCE_XOR: CombineOpc = ISD::XOR; break;
1960  case ISD::VECREDUCE_SMAX: CombineOpc = ISD::SMAX; break;
1961  case ISD::VECREDUCE_SMIN: CombineOpc = ISD::SMIN; break;
1962  case ISD::VECREDUCE_UMAX: CombineOpc = ISD::UMAX; break;
1963  case ISD::VECREDUCE_UMIN: CombineOpc = ISD::UMIN; break;
1964  case ISD::VECREDUCE_FMAX:
1965  CombineOpc = NoNaN ? ISD::FMAXNUM : ISD::FMAXIMUM;
1966  break;
1967  case ISD::VECREDUCE_FMIN:
1968  CombineOpc = NoNaN ? ISD::FMINNUM : ISD::FMINIMUM;
1969  break;
1970  default:
1971  llvm_unreachable("Unexpected reduce ISD node");
1972  }
1973 
1974  // Use the appropriate scalar instruction on the split subvectors before
1975  // reducing the now partially reduced smaller vector.
1976  SDValue Partial = DAG.getNode(CombineOpc, dl, LoOpVT, Lo, Hi, N->getFlags());
1977  return DAG.getNode(N->getOpcode(), dl, ResVT, Partial, N->getFlags());
1978 }
1979 
1980 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
1981  // The result has a legal vector type, but the input needs splitting.
1982  EVT ResVT = N->getValueType(0);
1983  SDValue Lo, Hi;
1984  SDLoc dl(N);
1985  GetSplitVector(N->getOperand(0), Lo, Hi);
1986  EVT InVT = Lo.getValueType();
1987 
1988  EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1989  InVT.getVectorNumElements());
1990 
1991  Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
1992  Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
1993 
1994  return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1995 }
1996 
1997 SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
1998  // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
1999  // end up being split all the way down to individual components. Convert the
2000  // split pieces into integers and reassemble.
2001  SDValue Lo, Hi;
2002  GetSplitVector(N->getOperand(0), Lo, Hi);
2003  Lo = BitConvertToInteger(Lo);
2004  Hi = BitConvertToInteger(Hi);
2005 
2006  if (DAG.getDataLayout().isBigEndian())
2007  std::swap(Lo, Hi);
2008 
2009  return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),
2010  JoinIntegers(Lo, Hi));
2011 }
2012 
2013 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
2014  // We know that the extracted result type is legal.
2015  EVT SubVT = N->getValueType(0);
2016  SDValue Idx = N->getOperand(1);
2017  SDLoc dl(N);
2018  SDValue Lo, Hi;
2019  GetSplitVector(N->getOperand(0), Lo, Hi);
2020 
2021  uint64_t LoElts = Lo.getValueType().getVectorNumElements();
2022  uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2023 
2024  if (IdxVal < LoElts) {
2025  assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
2026  "Extracted subvector crosses vector split!");
2027  return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
2028  } else {
2029  return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
2030  DAG.getConstant(IdxVal - LoElts, dl,
2031  Idx.getValueType()));
2032  }
2033 }
2034 
2035 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
2036  SDValue Vec = N->getOperand(0);
2037  SDValue Idx = N->getOperand(1);
2038  EVT VecVT = Vec.getValueType();
2039 
2040  if (isa<ConstantSDNode>(Idx)) {
2041  uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2042 
2043  SDValue Lo, Hi;
2044  GetSplitVector(Vec, Lo, Hi);
2045 
2046  uint64_t LoElts = Lo.getValueType().getVectorNumElements();
2047 
2048  if (IdxVal < LoElts)
2049  return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
2050  return SDValue(DAG.UpdateNodeOperands(N, Hi,
2051  DAG.getConstant(IdxVal - LoElts, SDLoc(N),
2052  Idx.getValueType())), 0);
2053  }
2054 
2055  // See if the target wants to custom expand this node.
2056  if (CustomLowerNode(N, N->getValueType(0), true))
2057  return SDValue();
2058 
2059  // Make the vector elements byte-addressable if they aren't already.
2060  SDLoc dl(N);
2061  EVT EltVT = VecVT.getVectorElementType();
2062  if (VecVT.getScalarSizeInBits() < 8) {
2063  EltVT = MVT::i8;
2064  VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
2065  VecVT.getVectorNumElements());
2066  Vec = DAG.getNode(ISD::ANY_EXTEND, dl, VecVT, Vec);
2067  }
2068 
2069  // Store the vector to the stack.
2070  SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
2071  auto &MF = DAG.getMachineFunction();
2072  auto FrameIndex = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
2073  auto PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIndex);
2074  SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo);
2075 
2076  // Load back the required element.
2077  StackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
2078 
2079  // FIXME: This is to handle i1 vectors with elements promoted to i8.
2080  // i1 vector handling needs general improvement.
2081  if (N->getValueType(0).bitsLT(EltVT)) {
2082  SDValue Load = DAG.getLoad(EltVT, dl, Store, StackPtr,
2084  return DAG.getZExtOrTrunc(Load, dl, N->getValueType(0));
2085  }
2086 
2087  return DAG.getExtLoad(
2088  ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
2090 }
2091 
2092 SDValue DAGTypeLegalizer::SplitVecOp_ExtVecInRegOp(SDNode *N) {
2093  SDValue Lo, Hi;
2094 
2095  // *_EXTEND_VECTOR_INREG only reference the lower half of the input, so
2096  // splitting the result has the same effect as splitting the input operand.
2097  SplitVecRes_ExtVecInRegOp(N, Lo, Hi);
2098 
2099  return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), N->getValueType(0), Lo, Hi);
2100 }
2101 
2102 SDValue DAGTypeLegalizer::SplitVecOp_MGATHER(MaskedGatherSDNode *MGT,
2103  unsigned OpNo) {
2104  EVT LoVT, HiVT;
2105  SDLoc dl(MGT);
2106  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
2107 
2108  SDValue Ch = MGT->getChain();
2109  SDValue Ptr = MGT->getBasePtr();
2110  SDValue Index = MGT->getIndex();
2111  SDValue Scale = MGT->getScale();
2112  SDValue Mask = MGT->getMask();
2113  SDValue PassThru = MGT->getPassThru();
2114  unsigned Alignment = MGT->getOriginalAlignment();
2115 
2116  SDValue MaskLo, MaskHi;
2117  if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
2118  // Split Mask operand
2119  GetSplitVector(Mask, MaskLo, MaskHi);
2120  else
2121  std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
2122 
2123  EVT MemoryVT = MGT->getMemoryVT();
2124  EVT LoMemVT, HiMemVT;
2125  std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
2126 
2127  SDValue PassThruLo, PassThruHi;
2128  if (getTypeAction(PassThru.getValueType()) == TargetLowering::TypeSplitVector)
2129  GetSplitVector(PassThru, PassThruLo, PassThruHi);
2130  else
2131  std::tie(PassThruLo, PassThruHi) = DAG.SplitVector(PassThru, dl);
2132 
2133  SDValue IndexHi, IndexLo;
2134  if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
2135  GetSplitVector(Index, IndexLo, IndexHi);
2136  else
2137  std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, dl);
2138 
2142  Alignment, MGT->getAAInfo(), MGT->getRanges());
2143 
2144  SDValue OpsLo[] = {Ch, PassThruLo, MaskLo, Ptr, IndexLo, Scale};
2145  SDValue Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl,
2146  OpsLo, MMO);
2147 
2148  MMO = DAG.getMachineFunction().
2151  Alignment, MGT->getAAInfo(),
2152  MGT->getRanges());
2153 
2154  SDValue OpsHi[] = {Ch, PassThruHi, MaskHi, Ptr, IndexHi, Scale};
2155  SDValue Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl,
2156  OpsHi, MMO);
2157 
2158  // Build a factor node to remember that this load is independent of the
2159  // other one.
2160  Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2161  Hi.getValue(1));
2162 
2163  // Legalize the chain result - switch anything that used the old chain to
2164  // use the new one.
2165  ReplaceValueWith(SDValue(MGT, 1), Ch);
2166 
2167  SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, MGT->getValueType(0), Lo,
2168  Hi);
2169  ReplaceValueWith(SDValue(MGT, 0), Res);
2170  return SDValue();
2171 }
2172 
2173 SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
2174  unsigned OpNo) {
2175  SDValue Ch = N->getChain();
2176  SDValue Ptr = N->getBasePtr();
2177  SDValue Mask = N->getMask();
2178  SDValue Data = N->getValue();
2179  EVT MemoryVT = N->getMemoryVT();
2180  unsigned Alignment = N->getOriginalAlignment();
2181  SDLoc DL(N);
2182 
2183  EVT LoMemVT, HiMemVT;
2184  std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
2185 
2186  SDValue DataLo, DataHi;
2187  if (getTypeAction(Data.getValueType()) == TargetLowering::TypeSplitVector)
2188  // Split Data operand
2189  GetSplitVector(Data, DataLo, DataHi);
2190  else
2191  std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
2192 
2193  SDValue MaskLo, MaskHi;
2194  if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
2195  // Split Mask operand
2196  GetSplitVector(Mask, MaskLo, MaskHi);
2197  else
2198  std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, DL);
2199 
2200  // if Alignment is equal to the vector size,
2201  // take the half of it for the second part
2202  unsigned SecondHalfAlignment =
2203  (Alignment == Data->getValueType(0).getSizeInBits()/8) ?
2204  Alignment/2 : Alignment;
2205 
2206  SDValue Lo, Hi;
2210  Alignment, N->getAAInfo(), N->getRanges());
2211 
2212  Lo = DAG.getMaskedStore(Ch, DL, DataLo, Ptr, MaskLo, LoMemVT, MMO,
2213  N->isTruncatingStore(),
2214  N->isCompressingStore());
2215 
2216  Ptr = TLI.IncrementMemoryAddress(Ptr, MaskLo, DL, LoMemVT, DAG,
2217  N->isCompressingStore());
2218  unsigned HiOffset = LoMemVT.getStoreSize();
2219 
2222  HiMemVT.getStoreSize(), SecondHalfAlignment, N->getAAInfo(),
2223  N->getRanges());
2224 
2225  Hi = DAG.getMaskedStore(Ch, DL, DataHi, Ptr, MaskHi, HiMemVT, MMO,
2227 
2228  // Build a factor node to remember that this store is independent of the
2229  // other one.
2230  return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
2231 }
2232 
2233 SDValue DAGTypeLegalizer::SplitVecOp_MSCATTER(MaskedScatterSDNode *N,
2234  unsigned OpNo) {
2235  SDValue Ch = N->getChain();
2236  SDValue Ptr = N->getBasePtr();
2237  SDValue Mask = N->getMask();
2238  SDValue Index = N->getIndex();
2239  SDValue Scale = N->getScale();
2240  SDValue Data = N->getValue();
2241  EVT MemoryVT = N->getMemoryVT();
2242  unsigned Alignment = N->getOriginalAlignment();
2243  SDLoc DL(N);
2244 
2245  // Split all operands
2246  EVT LoMemVT, HiMemVT;
2247  std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
2248 
2249  SDValue DataLo, DataHi;
2250  if (getTypeAction(Data.getValueType()) == TargetLowering::TypeSplitVector)
2251  // Split Data operand
2252  GetSplitVector(Data, DataLo, DataHi);
2253  else
2254  std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
2255 
2256  SDValue MaskLo, MaskHi;
2257  if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
2258  // Split Mask operand
2259  GetSplitVector(Mask, MaskLo, MaskHi);
2260  else
2261  std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, DL);
2262 
2263  SDValue IndexHi, IndexLo;
2264  if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
2265  GetSplitVector(Index, IndexLo, IndexHi);
2266  else
2267  std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, DL);
2268 
2269  SDValue Lo;
2273  Alignment, N->getAAInfo(), N->getRanges());
2274 
2275  SDValue OpsLo[] = {Ch, DataLo, MaskLo, Ptr, IndexLo, Scale};
2276  Lo = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataLo.getValueType(),
2277  DL, OpsLo, MMO);
2278 
2279  MMO = DAG.getMachineFunction().
2282  Alignment, N->getAAInfo(), N->getRanges());
2283 
2284  // The order of the Scatter operation after split is well defined. The "Hi"
2285  // part comes after the "Lo". So these two operations should be chained one
2286  // after another.
2287  SDValue OpsHi[] = {Lo, DataHi, MaskHi, Ptr, IndexHi, Scale};
2288  return DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataHi.getValueType(),
2289  DL, OpsHi, MMO);
2290 }
2291 
2292 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
2293  assert(N->isUnindexed() && "Indexed store of vector?");
2294  assert(OpNo == 1 && "Can only split the stored value");
2295  SDLoc DL(N);
2296 
2297  bool isTruncating = N->isTruncatingStore();
2298  SDValue Ch = N->getChain();
2299  SDValue Ptr = N->getBasePtr();
2300  EVT MemoryVT = N->getMemoryVT();
2301  unsigned Alignment = N->getOriginalAlignment();
2302  MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
2303  AAMDNodes AAInfo = N->getAAInfo();
2304  SDValue Lo, Hi;
2305  GetSplitVector(N->getOperand(1), Lo, Hi);
2306 
2307  EVT LoMemVT, HiMemVT;
2308  std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
2309 
2310  // Scalarize if the split halves are not byte-sized.
2311  if (!LoMemVT.isByteSized() || !HiMemVT.isByteSized())
2312  return TLI.scalarizeVectorStore(N, DAG);
2313 
2314  unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
2315 
2316  if (isTruncating)
2317  Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), LoMemVT,
2318  Alignment, MMOFlags, AAInfo);
2319  else
2320  Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), Alignment, MMOFlags,
2321  AAInfo);
2322 
2323  // Increment the pointer to the other half.
2324  Ptr = DAG.getObjectPtrOffset(DL, Ptr, IncrementSize);
2325 
2326  if (isTruncating)
2327  Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
2328  N->getPointerInfo().getWithOffset(IncrementSize),
2329  HiMemVT, Alignment, MMOFlags, AAInfo);
2330  else
2331  Hi = DAG.getStore(Ch, DL, Hi, Ptr,
2332  N->getPointerInfo().getWithOffset(IncrementSize),
2333  Alignment, MMOFlags, AAInfo);
2334 
2335  return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
2336 }
2337 
2338 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
2339  SDLoc DL(N);
2340 
2341  // The input operands all must have the same type, and we know the result
2342  // type is valid. Convert this to a buildvector which extracts all the
2343  // input elements.
2344  // TODO: If the input elements are power-two vectors, we could convert this to
2345  // a new CONCAT_VECTORS node with elements that are half-wide.
2347  EVT EltVT = N->getValueType(0).getVectorElementType();
2348  for (const SDValue &Op : N->op_values()) {
2349  for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
2350  i != e; ++i) {
2351  Elts.push_back(DAG.getNode(
2352  ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Op,
2353  DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
2354  }
2355  }
2356 
2357  return DAG.getBuildVector(N->getValueType(0), DL, Elts);
2358 }
2359 
2360 SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) {
2361  // The result type is legal, but the input type is illegal. If splitting
2362  // ends up with the result type of each half still being legal, just
2363  // do that. If, however, that would result in an illegal result type,
2364  // we can try to get more clever with power-two vectors. Specifically,
2365  // split the input type, but also widen the result element size, then
2366  // concatenate the halves and truncate again. For example, consider a target
2367  // where v8i8 is legal and v8i32 is not (ARM, which doesn't have 256-bit
2368  // vectors). To perform a "%res = v8i8 trunc v8i32 %in" we do:
2369  // %inlo = v4i32 extract_subvector %in, 0
2370  // %inhi = v4i32 extract_subvector %in, 4
2371  // %lo16 = v4i16 trunc v4i32 %inlo
2372  // %hi16 = v4i16 trunc v4i32 %inhi
2373  // %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
2374  // %res = v8i8 trunc v8i16 %in16
2375  //
2376  // Without this transform, the original truncate would end up being
2377  // scalarized, which is pretty much always a last resort.
2378  SDValue InVec = N->getOperand(0);
2379  EVT InVT = InVec->getValueType(0);
2380  EVT OutVT = N->getValueType(0);
2381  unsigned NumElements = OutVT.getVectorNumElements();
2382  bool IsFloat = OutVT.isFloatingPoint();
2383 
2384  // Widening should have already made sure this is a power-two vector
2385  // if we're trying to split it at all. assert() that's true, just in case.
2386  assert(!(NumElements & 1) && "Splitting vector, but not in half!");
2387 
2388  unsigned InElementSize = InVT.getScalarSizeInBits();
2389  unsigned OutElementSize = OutVT.getScalarSizeInBits();
2390 
2391  // Determine the split output VT. If its legal we can just split dirctly.
2392  EVT LoOutVT, HiOutVT;
2393  std::tie(LoOutVT, HiOutVT) = DAG.GetSplitDestVTs(OutVT);
2394  assert(LoOutVT == HiOutVT && "Unequal split?");
2395 
2396  // If the input elements are only 1/2 the width of the result elements,
2397  // just use the normal splitting. Our trick only work if there's room
2398  // to split more than once.
2399  if (isTypeLegal(LoOutVT) ||
2400  InElementSize <= OutElementSize * 2)
2401  return SplitVecOp_UnaryOp(N);
2402  SDLoc DL(N);
2403 
2404  // Don't touch if this will be scalarized.
2405  EVT FinalVT = InVT;
2406  while (getTypeAction(FinalVT) == TargetLowering::TypeSplitVector)
2407  FinalVT = FinalVT.getHalfNumVectorElementsVT(*DAG.getContext());
2408 
2409  if (getTypeAction(FinalVT) == TargetLowering::TypeScalarizeVector)
2410  return SplitVecOp_UnaryOp(N);
2411 
2412  // Get the split input vector.
2413  SDValue InLoVec, InHiVec;
2414  GetSplitVector(InVec, InLoVec, InHiVec);
2415 
2416  // Truncate them to 1/2 the element size.
2417  EVT HalfElementVT = IsFloat ?
2418  EVT::getFloatingPointVT(InElementSize/2) :
2419  EVT::getIntegerVT(*DAG.getContext(), InElementSize/2);
2420  EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT,
2421  NumElements/2);
2422  SDValue HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec);
2423  SDValue HalfHi = DAG.getNode(N->getOpcode(), DL, HalfVT, InHiVec);
2424  // Concatenate them to get the full intermediate truncation result.
2425  EVT InterVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, NumElements);
2426  SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo,
2427  HalfHi);
2428  // Now finish up by truncating all the way down to the original result
2429  // type. This should normally be something that ends up being legal directly,
2430  // but in theory if a target has very wide vectors and an annoyingly
2431  // restricted set of legal types, this split can chain to build things up.
2432  return IsFloat
2433  ? DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec,
2434  DAG.getTargetConstant(
2435  0, DL, TLI.getPointerTy(DAG.getDataLayout())))
2436  : DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec);
2437 }
2438 
2439 SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
2440  assert(N->getValueType(0).isVector() &&
2441  N->getOperand(0).getValueType().isVector() &&
2442  "Operand types must be vectors");
2443  // The result has a legal vector type, but the input needs splitting.
2444  SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
2445  SDLoc DL(N);
2446  GetSplitVector(N->getOperand(0), Lo0, Hi0);
2447  GetSplitVector(N->getOperand(1), Lo1, Hi1);
2448  unsigned PartElements = Lo0.getValueType().getVectorNumElements();
2449  EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);
2450  EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
2451 
2452  LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
2453  HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
2454  SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
2455  return PromoteTargetBoolean(Con, N->getValueType(0));
2456 }
2457 
2458 
2459 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
2460  // The result has a legal vector type, but the input needs splitting.
2461  EVT ResVT = N->getValueType(0);
2462  SDValue Lo, Hi;
2463  SDLoc DL(N);
2464  GetSplitVector(N->getOperand(0), Lo, Hi);
2465  EVT InVT = Lo.getValueType();
2466 
2467  EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
2468  InVT.getVectorNumElements());
2469 
2470  Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
2471  Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
2472 
2473  return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
2474 }
2475 
2476 SDValue DAGTypeLegalizer::SplitVecOp_FCOPYSIGN(SDNode *N) {
2477  // The result (and the first input) has a legal vector type, but the second
2478  // input needs splitting.
2479  return DAG.UnrollVectorOp(N, N->getValueType(0).getVectorNumElements());
2480 }
2481 
2482 
2483 //===----------------------------------------------------------------------===//
2484 // Result Vector Widening
2485 //===----------------------------------------------------------------------===//
2486 
2487 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
2488  LLVM_DEBUG(dbgs() << "Widen node result " << ResNo << ": "; N->dump(&DAG);
2489  dbgs() << "\n");
2490 
2491  // See if the target wants to custom widen this node.
2492  if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
2493  return;
2494 
2495  SDValue Res = SDValue();
2496  switch (N->getOpcode()) {
2497  default:
2498 #ifndef NDEBUG
2499  dbgs() << "WidenVectorResult #" << ResNo << ": ";
2500  N->dump(&DAG);
2501  dbgs() << "\n";
2502 #endif
2503  llvm_unreachable("Do not know how to widen the result of this operator!");
2504 
2505  case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
2506  case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
2507  case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
2508  case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
2509  case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
2510  case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
2511  case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
2512  case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
2513  case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
2514  case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
2515  case ISD::VSELECT:
2516  case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
2517  case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
2518  case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
2519  case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
2520  case ISD::VECTOR_SHUFFLE:
2521  Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
2522  break;
2523  case ISD::MLOAD:
2524  Res = WidenVecRes_MLOAD(cast<MaskedLoadSDNode>(N));
2525  break;
2526  case ISD::MGATHER:
2527  Res = WidenVecRes_MGATHER(cast<MaskedGatherSDNode>(N));
2528  break;
2529 
2530  case ISD::ADD:
2531  case ISD::AND:
2532  case ISD::MUL:
2533  case ISD::MULHS:
2534  case ISD::MULHU:
2535  case ISD::OR:
2536  case ISD::SUB:
2537  case ISD::XOR:
2538  case ISD::FMINNUM:
2539  case ISD::FMAXNUM:
2540  case ISD::FMINIMUM:
2541  case ISD::FMAXIMUM:
2542  case ISD::SMIN:
2543  case ISD::SMAX:
2544  case ISD::UMIN:
2545  case ISD::UMAX:
2546  case ISD::UADDSAT:
2547  case ISD::SADDSAT:
2548  case ISD::USUBSAT:
2549  case ISD::SSUBSAT:
2550  Res = WidenVecRes_Binary(N);
2551  break;
2552 
2553  case ISD::FADD:
2554  case ISD::FMUL:
2555  case ISD::FPOW:
2556  case ISD::FSUB:
2557  case ISD::FDIV:
2558  case ISD::FREM:
2559  case ISD::SDIV:
2560  case ISD::UDIV:
2561  case ISD::SREM:
2562  case ISD::UREM:
2563  Res = WidenVecRes_BinaryCanTrap(N);
2564  break;
2565 
2566  case ISD::STRICT_FADD:
2567  case ISD::STRICT_FSUB:
2568  case ISD::STRICT_FMUL:
2569  case ISD::STRICT_FDIV:
2570  case ISD::STRICT_FREM:
2571  case ISD::STRICT_FSQRT:
2572  case ISD::STRICT_FMA:
2573  case ISD::STRICT_FPOW:
2574  case ISD::STRICT_FPOWI:
2575  case ISD::STRICT_FSIN:
2576  case ISD::STRICT_FCOS:
2577  case ISD::STRICT_FEXP:
2578  case ISD::STRICT_FEXP2:
2579  case ISD::STRICT_FLOG:
2580  case ISD::STRICT_FLOG10:
2581  case ISD::STRICT_FLOG2:
2582  case ISD::STRICT_FRINT:
2584  case ISD::STRICT_FMAXNUM:
2585  case ISD::STRICT_FMINNUM:
2586  case ISD::STRICT_FCEIL:
2587  case ISD::STRICT_FFLOOR:
2588  case ISD::STRICT_FROUND:
2589  case ISD::STRICT_FTRUNC:
2590  Res = WidenVecRes_StrictFP(N);
2591  break;
2592 
2593  case ISD::UADDO:
2594  case ISD::SADDO:
2595  case ISD::USUBO:
2596  case ISD::SSUBO:
2597  case ISD::UMULO:
2598  case ISD::SMULO:
2599  Res = WidenVecRes_OverflowOp(N, ResNo);
2600  break;
2601 
2602  case ISD::FCOPYSIGN:
2603  Res = WidenVecRes_FCOPYSIGN(N);
2604  break;
2605 
2606  case ISD::FPOWI:
2607  Res = WidenVecRes_POWI(N);
2608  break;
2609 
2610  case ISD::SHL:
2611  case ISD::SRA:
2612  case ISD::SRL:
2613  Res = WidenVecRes_Shift(N);
2614  break;
2615 
2619  Res = WidenVecRes_EXTEND_VECTOR_INREG(N);
2620  break;
2621 
2622  case ISD::ANY_EXTEND:
2623  case ISD::FP_EXTEND:
2624  case ISD::FP_ROUND:
2625  case ISD::FP_TO_SINT:
2626  case ISD::FP_TO_UINT:
2627  case ISD::SIGN_EXTEND:
2628  case ISD::SINT_TO_FP:
2629  case ISD::TRUNCATE:
2630  case ISD::UINT_TO_FP:
2631  case ISD::ZERO_EXTEND:
2632  Res = WidenVecRes_Convert(N);
2633  break;
2634 
2635  case ISD::FABS:
2636  case ISD::FCEIL:
2637  case ISD::FCOS:
2638  case ISD::FEXP:
2639  case ISD::FEXP2:
2640  case ISD::FFLOOR:
2641  case ISD::FLOG:
2642  case ISD::FLOG10:
2643  case ISD::FLOG2:
2644  case ISD::FNEARBYINT:
2645  case ISD::FRINT:
2646  case ISD::FROUND:
2647  case ISD::FSIN:
2648  case ISD::FSQRT:
2649  case ISD::FTRUNC: {
2650  // We're going to widen this vector op to a legal type by padding with undef
2651  // elements. If the wide vector op is eventually going to be expanded to
2652  // scalar libcalls, then unroll into scalar ops now to avoid unnecessary
2653  // libcalls on the undef elements. We are assuming that if the scalar op
2654  // requires expanding, then the vector op needs expanding too.
2655  EVT VT = N->getValueType(0);
2656  if (TLI.isOperationExpand(N->getOpcode(), VT.getScalarType())) {
2657  EVT WideVecVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2658  assert(!TLI.isOperationLegalOrCustom(N->getOpcode(), WideVecVT) &&
2659  "Target supports vector op, but scalar requires expansion?");
2660  Res = DAG.UnrollVectorOp(N, WideVecVT.getVectorNumElements());
2661  break;
2662  }
2663  }
2664  // If the target has custom/legal support for the scalar FP intrinsic ops
2665  // (they are probably not destined to become libcalls), then widen those like
2666  // any other unary ops.
2668 
2669  case ISD::ABS:
2670  case ISD::BITREVERSE:
2671  case ISD::BSWAP:
2672  case ISD::CTLZ:
2673  case ISD::CTPOP:
2674  case ISD::CTTZ:
2675  case ISD::FNEG:
2676  case ISD::FCANONICALIZE:
2677  Res = WidenVecRes_Unary(N);
2678  break;
2679  case ISD::FMA:
2680  Res = WidenVecRes_Ternary(N);
2681  break;
2682  }
2683 
2684  // If Res is null, the sub-method took care of registering the result.
2685  if (Res.getNode())
2686  SetWidenedVector(SDValue(N, ResNo), Res);
2687 }
2688 
2689 SDValue DAGTypeLegalizer::WidenVecRes_Ternary(SDNode *N) {
2690  // Ternary op widening.
2691  SDLoc dl(N);
2692  EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2693  SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2694  SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2695  SDValue InOp3 = GetWidenedVector(N->getOperand(2));
2696  return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3);
2697 }
2698 
2699 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
2700  // Binary op widening.
2701  SDLoc dl(N);
2702  EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2703  SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2704  SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2705  return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, N->getFlags());
2706 }
2707 
2708 // Given a vector of operations that have been broken up to widen, see
2709 // if we can collect them together into the next widest legal VT. This
2710 // implementation is trap-safe.
2712  SmallVectorImpl<SDValue> &ConcatOps,
2713  unsigned ConcatEnd, EVT VT, EVT MaxVT,
2714  EVT WidenVT) {
2715  // Check to see if we have a single operation with the widen type.
2716  if (ConcatEnd == 1) {
2717  VT = ConcatOps[0].getValueType();
2718  if (VT == WidenVT)
2719  return ConcatOps[0];
2720  }
2721 
2722  SDLoc dl(ConcatOps[0]);
2723  EVT WidenEltVT = WidenVT.getVectorElementType();
2724  int Idx = 0;
2725 
2726  // while (Some element of ConcatOps is not of type MaxVT) {
2727  // From the end of ConcatOps, collect elements of the same type and put
2728  // them into an op of the next larger supported type
2729  // }
2730  while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
2731  Idx = ConcatEnd - 1;
2732  VT = ConcatOps[Idx--].getValueType();
2733  while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
2734  Idx--;
2735 
2736  int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
2737  EVT NextVT;
2738  do {
2739  NextSize *= 2;
2740  NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
2741  } while (!TLI.isTypeLegal(NextVT));
2742 
2743  if (!VT.isVector()) {
2744  // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
2745  SDValue VecOp = DAG.getUNDEF(NextVT);
2746  unsigned NumToInsert = ConcatEnd - Idx - 1;
2747  for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
2748  VecOp = DAG.getNode(
2749  ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, ConcatOps[OpIdx],
2750  DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2751  }
2752  ConcatOps[Idx+1] = VecOp;
2753  ConcatEnd = Idx + 2;
2754  } else {
2755  // Vector type, create a CONCAT_VECTORS of type NextVT
2756  SDValue undefVec = DAG.getUNDEF(VT);
2757  unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
2758  SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
2759  unsigned RealVals = ConcatEnd - Idx - 1;
2760  unsigned SubConcatEnd = 0;
2761  unsigned SubConcatIdx = Idx + 1;
2762  while (SubConcatEnd < RealVals)
2763  SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
2764  while (SubConcatEnd < OpsToConcat)
2765  SubConcatOps[SubConcatEnd++] = undefVec;
2766  ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
2767  NextVT, SubConcatOps);
2768  ConcatEnd = SubConcatIdx + 1;
2769  }
2770  }
2771 
2772  // Check to see if we have a single operation with the widen type.
2773  if (ConcatEnd == 1) {
2774  VT = ConcatOps[0].getValueType();
2775  if (VT == WidenVT)
2776  return ConcatOps[0];
2777  }
2778 
2779  // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
2780  unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
2781  if (NumOps != ConcatEnd ) {
2782  SDValue UndefVal = DAG.getUNDEF(MaxVT);
2783  for (unsigned j = ConcatEnd; j < NumOps; ++j)
2784  ConcatOps[j] = UndefVal;
2785  }
2786  return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
2787  makeArrayRef(ConcatOps.data(), NumOps));
2788 }
2789 
2790 SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(SDNode *N) {
2791  // Binary op widening for operations that can trap.
2792  unsigned Opcode = N->getOpcode();
2793  SDLoc dl(N);
2794  EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2795  EVT WidenEltVT = WidenVT.getVectorElementType();
2796  EVT VT = WidenVT;
2797  unsigned NumElts = VT.getVectorNumElements();
2798  const SDNodeFlags Flags = N->getFlags();
2799  while (!TLI.isTypeLegal(VT) && NumElts != 1) {
2800  NumElts = NumElts / 2;
2801  VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2802  }
2803 
2804  if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
2805  // Operation doesn't trap so just widen as normal.
2806  SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2807  SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2808  return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, Flags);
2809  }
2810 
2811  // No legal vector version so unroll the vector operation and then widen.
2812  if (NumElts == 1)
2813  return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
2814 
2815  // Since the operation can trap, apply operation on the original vector.
2816  EVT MaxVT = VT;
2817  SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2818  SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2819  unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
2820 
2821  SmallVector<SDValue, 16> ConcatOps(CurNumElts);
2822  unsigned ConcatEnd = 0; // Current ConcatOps index.
2823  int Idx = 0; // Current Idx into input vectors.
2824 
2825  // NumElts := greatest legal vector size (at most WidenVT)
2826  // while (orig. vector has unhandled elements) {
2827  // take munches of size NumElts from the beginning and add to ConcatOps
2828  // NumElts := next smaller supported vector size or 1
2829  // }
2830  while (CurNumElts != 0) {
2831  while (CurNumElts >= NumElts) {
2832  SDValue EOp1 = DAG.getNode(
2833  ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
2834  DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2835  SDValue EOp2 = DAG.getNode(
2836  ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
2837  DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2838  ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2, Flags);
2839  Idx += NumElts;
2840  CurNumElts -= NumElts;
2841  }
2842  do {
2843  NumElts = NumElts / 2;
2844  VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2845  } while (!TLI.isTypeLegal(VT) && NumElts != 1);
2846 
2847  if (NumElts == 1) {
2848  for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
2849  SDValue EOp1 = DAG.getNode(
2850  ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, InOp1,
2851  DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2852  SDValue EOp2 = DAG.getNode(
2853  ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, InOp2,
2854  DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2855  ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
2856  EOp1, EOp2, Flags);
2857  }
2858  CurNumElts = 0;
2859  }
2860  }
2861 
2862  return CollectOpsToWiden(DAG, TLI, ConcatOps, ConcatEnd, VT, MaxVT, WidenVT);
2863 }
2864 
2865 SDValue DAGTypeLegalizer::WidenVecRes_StrictFP(SDNode *N) {
2866  // StrictFP op widening for operations that can trap.
2867  unsigned NumOpers = N->getNumOperands();
2868  unsigned Opcode = N->getOpcode();
2869  SDLoc dl(N);
2870  EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2871  EVT WidenEltVT = WidenVT.getVectorElementType();
2872  EVT VT = WidenVT;
2873  unsigned NumElts = VT.getVectorNumElements();
2874  while (!TLI.isTypeLegal(VT) && NumElts != 1) {
2875  NumElts = NumElts / 2;
2876  VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2877  }
2878 
2879  // No legal vector version so unroll the vector operation and then widen.
2880  if (NumElts == 1)
2881  return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
2882 
2883  // Since the operation can trap, apply operation on the original vector.
2884  EVT MaxVT = VT;
2886  unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
2887 
2888  SmallVector<SDValue, 16> ConcatOps(CurNumElts);
2889  SmallVector<SDValue, 16> Chains;
2890  unsigned ConcatEnd = 0; // Current ConcatOps index.
2891  int Idx = 0; // Current Idx into input vectors.
2892 
2893  // The Chain is the first operand.
2894  InOps.push_back(N->getOperand(0));
2895 
2896  // Now process the remaining operands.
2897  for (unsigned i = 1; i < NumOpers; ++i) {
2898  SDValue Oper = N->getOperand(i);
2899 
2900  if (Oper.getValueType().isVector()) {
2901  assert(Oper.getValueType() == N->getValueType(0) &&
2902  "Invalid operand type to widen!");
2903  Oper = GetWidenedVector(Oper);
2904  }
2905 
2906  InOps.push_back(Oper);
2907  }
2908 
2909  // NumElts := greatest legal vector size (at most WidenVT)
2910  // while (orig. vector has unhandled elements) {
2911  // take munches of size NumElts from the beginning and add to ConcatOps
2912  // NumElts := next smaller supported vector size or 1
2913  // }
2914  while (CurNumElts != 0) {
2915  while (CurNumElts >= NumElts) {
2917 
2918  for (unsigned i = 0; i < NumOpers; ++i) {
2919  SDValue Op = InOps[i];
2920 
2921  if (Op.getValueType().isVector())
2922  Op = DAG.getNode(
2923  ISD::EXTRACT_SUBVECTOR, dl, VT, Op,
2924  DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2925 
2926  EOps.push_back(Op);
2927  }
2928 
2929  EVT OperVT[] = {VT, MVT::Other};
2930  SDValue Oper = DAG.getNode(Opcode, dl, OperVT, EOps);
2931  ConcatOps[ConcatEnd++] = Oper;
2932  Chains.push_back(Oper.getValue(1));
2933  Idx += NumElts;
2934  CurNumElts -= NumElts;
2935  }
2936  do {
2937  NumElts = NumElts / 2;
2938  VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2939  } while (!TLI.isTypeLegal(VT) && NumElts != 1);
2940 
2941  if (NumElts == 1) {
2942  for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
2944 
2945  for (unsigned i = 0; i < NumOpers; ++i) {
2946  SDValue Op = InOps[i];
2947 
2948  if (Op.getValueType().isVector())
2949  Op = DAG.getNode(
2950  ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, Op,
2951  DAG.getConstant(Idx, dl,
2952  TLI.getVectorIdxTy(DAG.getDataLayout())));
2953 
2954  EOps.push_back(Op);
2955  }
2956 
2957  EVT WidenVT[] = {WidenEltVT, MVT::Other};
2958  SDValue Oper = DAG.getNode(Opcode, dl, WidenVT, EOps);
2959  ConcatOps[ConcatEnd++] = Oper;
2960  Chains.push_back(Oper.getValue(1));
2961  }
2962  CurNumElts = 0;
2963  }
2964  }
2965 
2966  // Build a factor node to remember all the Ops that have been created.
2967  SDValue NewChain;
2968  if (Chains.size() == 1)
2969  NewChain = Chains[0];
2970  else
2971  NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
2972  ReplaceValueWith(SDValue(N, 1), NewChain);
2973 
2974  return CollectOpsToWiden(DAG, TLI, ConcatOps, ConcatEnd, VT, MaxVT, WidenVT);
2975 }
2976 
2977 SDValue DAGTypeLegalizer::WidenVecRes_OverflowOp(SDNode *N, unsigned ResNo) {
2978  SDLoc DL(N);
2979  EVT ResVT = N->getValueType(0);
2980  EVT OvVT = N->getValueType(1);
2981  EVT WideResVT, WideOvVT;
2982  SDValue WideLHS, WideRHS;
2983 
2984  // TODO: This might result in a widen/split loop.
2985  if (ResNo == 0) {
2986  WideResVT = TLI.getTypeToTransformTo(*DAG.getContext(), ResVT);
2987  WideOvVT = EVT::getVectorVT(
2988  *DAG.getContext(), OvVT.getVectorElementType(),
2989  WideResVT.getVectorNumElements());
2990 
2991  WideLHS = GetWidenedVector(N->getOperand(0));
2992  WideRHS = GetWidenedVector(N->getOperand(1));
2993  } else {
2994  WideOvVT = TLI.getTypeToTransformTo(*DAG.getContext(), OvVT);
2995  WideResVT = EVT::getVectorVT(
2996  *DAG.getContext(), ResVT.getVectorElementType(),
2997  WideOvVT.getVectorNumElements());
2998 
2999  SDValue Zero = DAG.getConstant(
3000  0, DL, TLI.getVectorIdxTy(DAG.getDataLayout()));
3001  WideLHS = DAG.getNode(
3002  ISD::INSERT_SUBVECTOR, DL, WideResVT, DAG.getUNDEF(WideResVT),
3003  N->getOperand(0), Zero);
3004  WideRHS = DAG.getNode(
3005  ISD::INSERT_SUBVECTOR, DL, WideResVT, DAG.getUNDEF(WideResVT),
3006  N->getOperand(1), Zero);
3007  }
3008 
3009  SDVTList WideVTs = DAG.getVTList(WideResVT, WideOvVT);
3010  SDNode *WideNode = DAG.getNode(
3011  N->getOpcode(), DL, WideVTs, WideLHS, WideRHS).getNode();
3012 
3013  // Replace the other vector result not being explicitly widened here.
3014  unsigned OtherNo = 1 - ResNo;
3015  EVT OtherVT = N->getValueType(OtherNo);
3016  if (getTypeAction(OtherVT) == TargetLowering::TypeWidenVector) {
3017  SetWidenedVector(SDValue(N, OtherNo), SDValue(WideNode, OtherNo));
3018  } else {
3019  SDValue Zero = DAG.getConstant(
3020  0, DL, TLI.getVectorIdxTy(DAG.getDataLayout()));
3021  SDValue OtherVal = DAG.getNode(
3022  ISD::EXTRACT_SUBVECTOR, DL, OtherVT, SDValue(WideNode, OtherNo), Zero);
3023  ReplaceValueWith(SDValue(N, OtherNo), OtherVal);
3024  }
3025 
3026  return SDValue(WideNode, ResNo);
3027 }
3028 
3029 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
3030  SDValue InOp = N->getOperand(0);
3031  SDLoc DL(N);
3032 
3033  EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3034  unsigned WidenNumElts = WidenVT.getVectorNumElements();
3035 
3036  EVT InVT = InOp.getValueType();
3037  EVT InEltVT = InVT.getVectorElementType();
3038  EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
3039 
3040  unsigned Opcode = N->getOpcode();
3041  unsigned InVTNumElts = InVT.getVectorNumElements();
3042  const SDNodeFlags Flags = N->getFlags();
3043  if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
3044  InOp = GetWidenedVector(N->getOperand(0));
3045  InVT = InOp.getValueType();
3046  InVTNumElts = InVT.getVectorNumElements();
3047  if (InVTNumElts == WidenNumElts) {
3048  if (N->getNumOperands() == 1)
3049  return DAG.getNode(Opcode, DL, WidenVT, InOp);
3050  return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1), Flags);
3051  }
3052  if (WidenVT.getSizeInBits() == InVT.getSizeInBits()) {
3053  // If both input and result vector types are of same width, extend
3054  // operations should be done with SIGN/ZERO_EXTEND_VECTOR_INREG, which
3055  // accepts fewer elements in the result than in the input.
3056  if (Opcode == ISD::ANY_EXTEND)
3057  return DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, WidenVT, InOp);
3058  if (Opcode == ISD::SIGN_EXTEND)
3059  return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, WidenVT, InOp);
3060  if (Opcode == ISD::ZERO_EXTEND)
3061  return DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, DL, WidenVT, InOp);
3062  }
3063  }
3064 
3065  if (TLI.isTypeLegal(InWidenVT)) {
3066  // Because the result and the input are different vector types, widening
3067  // the result could create a legal type but widening the input might make
3068  // it an illegal type that might lead to repeatedly splitting the input
3069  // and then widening it. To avoid this, we widen the input only if
3070  // it results in a legal type.
3071  if (WidenNumElts % InVTNumElts == 0) {
3072  // Widen the input and call convert on the widened input vector.
3073  unsigned NumConcat = WidenNumElts/InVTNumElts;
3074  SmallVector<SDValue, 16> Ops(NumConcat, DAG.getUNDEF(InVT));
3075  Ops[0] = InOp;
3076  SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops);
3077  if (N->getNumOperands() == 1)
3078  return DAG.getNode(Opcode, DL, WidenVT, InVec);
3079  return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1), Flags);
3080  }
3081 
3082  if (InVTNumElts % WidenNumElts == 0) {
3083  SDValue InVal = DAG.getNode(
3084  ISD::EXTRACT_SUBVECTOR, DL, InWidenVT, InOp,
3085  DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
3086  // Extract the input and convert the shorten input vector.
3087  if (N->getNumOperands() == 1)
3088  return DAG.getNode(Opcode, DL, WidenVT, InVal);
3089  return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1), Flags);
3090  }
3091  }
3092 
3093  // Otherwise unroll into some nasty scalar code and rebuild the vector.
3094  EVT EltVT = WidenVT.getVectorElementType();
3095  SmallVector<SDValue, 16> Ops(WidenNumElts, DAG.getUNDEF(EltVT));
3096  // Use the original element count so we don't do more scalar opts than
3097  // necessary.
3098  unsigned MinElts = N->getValueType(0).getVectorNumElements();
3099  for (unsigned i=0; i < MinElts; ++i) {
3100  SDValue Val = DAG.getNode(
3101  ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
3102  DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
3103  if (N->getNumOperands() == 1)
3104  Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
3105  else
3106  Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1), Flags);
3107  }
3108 
3109  return DAG.getBuildVector(WidenVT, DL, Ops);
3110 }
3111 
3112 SDValue DAGTypeLegalizer::WidenVecRes_EXTEND_VECTOR_INREG(SDNode *N) {
3113  unsigned Opcode = N->getOpcode();
3114  SDValue InOp = N->getOperand(0);
3115  SDLoc DL(N);
3116 
3117  EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3118  EVT WidenSVT = WidenVT.getVectorElementType();
3119  unsigned WidenNumElts = WidenVT.getVectorNumElements();
3120 
3121  EVT InVT = InOp.getValueType();
3122  EVT InSVT = InVT.getVectorElementType();
3123  unsigned InVTNumElts = InVT.getVectorNumElements();
3124 
3125  if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
3126  InOp = GetWidenedVector(InOp);
3127  InVT = InOp.getValueType();
3128  if (InVT.getSizeInBits() == WidenVT.getSizeInBits()) {
3129  switch (Opcode) {
3133  return DAG.getNode(Opcode, DL, WidenVT, InOp);
3134  }
3135  }
3136  }
3137 
3138  // Unroll, extend the scalars and rebuild the vector.
3140  for (unsigned i = 0, e = std::min(InVTNumElts, WidenNumElts); i != e; ++i) {
3141  SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InSVT, InOp,
3142  DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
3143  switch (Opcode) {
3145  Val = DAG.getNode(ISD::ANY_EXTEND, DL, WidenSVT, Val);
3146  break;
3148  Val = DAG.getNode(ISD::SIGN_EXTEND, DL, WidenSVT, Val);
3149  break;
3151  Val = DAG.getNode(ISD::ZERO_EXTEND, DL, WidenSVT, Val);
3152  break;
3153  default:
3154  llvm_unreachable("A *_EXTEND_VECTOR_INREG node was expected");
3155  }
3156  Ops.push_back(Val);
3157  }
3158 
3159  while (Ops.size() != WidenNumElts)
3160  Ops.push_back(DAG.getUNDEF(WidenSVT));
3161 
3162  return DAG.getBuildVector(WidenVT, DL, Ops);
3163 }
3164 
3165 SDValue DAGTypeLegalizer::WidenVecRes_FCOPYSIGN(SDNode *N) {
3166  // If this is an FCOPYSIGN with same input types, we can treat it as a
3167  // normal (can trap) binary op.
3168  if (N->getOperand(0).getValueType() == N->getOperand(1).getValueType())
3169  return WidenVecRes_BinaryCanTrap(N);
3170 
3171  // If the types are different, fall back to unrolling.
3172  EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3173  return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
3174 }
3175 
3176 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
3177  EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3178  SDValue InOp = GetWidenedVector(N->getOperand(0));
3179  SDValue ShOp = N->getOperand(1);
3180  return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
3181 }
3182 
3183 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
3184  EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3185  SDValue InOp = GetWidenedVector(N->getOperand(0));
3186  SDValue ShOp = N->getOperand(1);
3187 
3188  EVT ShVT = ShOp.getValueType();
3189  if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
3190  ShOp = GetWidenedVector(ShOp);
3191  ShVT = ShOp.getValueType();
3192  }
3193  EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
3194  ShVT.getVectorElementType(),
3195  WidenVT.getVectorNumElements());
3196  if (ShVT != ShWidenVT)
3197  ShOp = ModifyToType(ShOp, ShWidenVT);
3198 
3199  return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
3200 }
3201 
3202 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
3203  // Unary op widening.
3204  EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3205  SDValue InOp = GetWidenedVector(N->getOperand(0));
3206  return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp);
3207 }
3208 
3209 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
3210  EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3211  EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
3212  cast<VTSDNode>(N->getOperand(1))->getVT()
3213  .getVectorElementType(),
3214  WidenVT.getVectorNumElements());
3215  SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
3216  return DAG.getNode(N->getOpcode(), SDLoc(N),
3217  WidenVT, WidenLHS, DAG.getValueType(ExtVT));
3218 }
3219 
3220 SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) {
3221  SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo);
3222  return GetWidenedVector(WidenVec);
3223 }
3224 
3225 SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
3226  SDValue InOp = N->getOperand(0);
3227  EVT InVT = InOp.getValueType();
3228  EVT VT = N->getValueType(0);
3229  EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3230  SDLoc dl(N);
3231 
3232  switch (getTypeAction(InVT)) {
3234  break;
3236  // If the incoming type is a vector that is being promoted, then
3237  // we know that the elements are arranged differently and that we
3238  // must perform the conversion using a stack slot.
3239  if (InVT.isVector())
3240  break;
3241 
3242  // If the InOp is promoted to the same size, convert it. Otherwise,
3243  // fall out of the switch and widen the promoted input.
3244  InOp = GetPromotedInteger(InOp);
3245  InVT = InOp.getValueType();
3246  if (WidenVT.bitsEq(InVT))
3247  return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
3248  break;
3255  break;
3257  // If the InOp is widened to the same size, convert it. Otherwise, fall
3258  // out of the switch and widen the widened input.
3259  InOp = GetWidenedVector(InOp);
3260  InVT = InOp.getValueType();
3261  if (WidenVT.bitsEq(InVT))
3262  // The input widens to the same size. Convert to the widen value.
3263  return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
3264  break;
3265  }
3266 
3267  unsigned WidenSize = WidenVT.getSizeInBits();
3268  unsigned InSize = InVT.getSizeInBits();
3269  // x86mmx is not an acceptable vector element type, so don't try.
3270  if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
3271  // Determine new input vector type. The new input vector type will use
3272  // the same element type (if its a vector) or use the input type as a
3273  // vector. It is the same size as the type to widen to.
3274  EVT NewInVT;
3275  unsigned NewNumElts = WidenSize / InSize;
3276  if (InVT.isVector()) {
3277  EVT InEltVT = InVT.getVectorElementType();
3278  NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
3279  WidenSize / InEltVT.getSizeInBits());
3280  } else {
3281  NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
3282  }
3283 
3284  if (TLI.isTypeLegal(NewInVT)) {
3285  SDValue NewVec;
3286  if (InVT.isVector()) {
3287  // Because the result and the input are different vector types, widening
3288  // the result could create a legal type but widening the input might make
3289  // it an illegal type that might lead to repeatedly splitting the input
3290  // and then widening it. To avoid this, we widen the input only if
3291  // it results in a legal type.
3292  SmallVector<SDValue, 16> Ops(NewNumElts, DAG.getUNDEF(InVT));
3293  Ops[0] = InOp;
3294 
3295  NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewInVT, Ops);
3296  } else {
3297  NewVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewInVT, InOp);
3298  }
3299  return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
3300  }
3301  }
3302 
3303  return CreateStackStoreLoad(InOp, WidenVT);
3304 }
3305 
3306 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
3307  SDLoc dl(N);
3308  // Build a vector with undefined for the new nodes.
3309  EVT VT = N->getValueType(0);
3310 
3311  // Integer BUILD_VECTOR operands may be larger than the node's vector element
3312  // type. The UNDEFs need to have the same type as the existing operands.
3313  EVT EltVT = N->getOperand(0).getValueType();
3314  unsigned NumElts = VT.getVectorNumElements();
3315 
3316  EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3317  unsigned WidenNumElts = WidenVT.getVectorNumElements();
3318 
3319  SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
3320  assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!");
3321  NewOps.append(WidenNumElts - NumElts, DAG.getUNDEF(EltVT));
3322 
3323  return DAG.getBuildVector(WidenVT, dl, NewOps);
3324 }
3325 
3326 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
3327  EVT InVT = N->getOperand(0).getValueType();
3328  EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3329  SDLoc dl(N);
3330  unsigned WidenNumElts = WidenVT.getVectorNumElements();
3331  unsigned NumInElts = InVT.getVectorNumElements();
3332  unsigned NumOperands = N->getNumOperands();
3333 
3334  bool InputWidened = false; // Indicates we need to widen the input.
3335  if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
3336  if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
3337  // Add undef vectors to widen to correct length.
3338  unsigned NumConcat = WidenVT.getVectorNumElements() /
3339  InVT.getVectorNumElements();
3340  SDValue UndefVal = DAG.getUNDEF(InVT);
3341  SmallVector<SDValue, 16> Ops(NumConcat);
3342  for (unsigned i=0; i < NumOperands; ++i)
3343  Ops[i] = N->getOperand(i);
3344  for (unsigned i = NumOperands; i != NumConcat; ++i)
3345  Ops[i] = UndefVal;
3346  return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, Ops);
3347  }
3348  } else {
3349  InputWidened = true;
3350  if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
3351  // The inputs and the result are widen to the same value.
3352  unsigned i;
3353  for (i=1; i < NumOperands; ++i)
3354  if (!N->getOperand(i).isUndef())
3355  break;
3356 
3357  if (i == NumOperands)
3358  // Everything but the first operand is an UNDEF so just return the
3359  // widened first operand.
3360  return GetWidenedVector(N->getOperand(0));
3361 
3362  if (NumOperands == 2) {
3363  // Replace concat of two operands with a shuffle.
3364  SmallVector<int, 16> MaskOps(WidenNumElts, -1);
3365  for (unsigned i = 0; i < NumInElts; ++i) {
3366  MaskOps[i] = i;
3367  MaskOps[i + NumInElts] = i + WidenNumElts;
3368  }
3369  return DAG.getVectorShuffle(WidenVT, dl,
3370  GetWidenedVector(N->getOperand(0)),
3371  GetWidenedVector(N->getOperand(1)),
3372  MaskOps);
3373  }
3374  }
3375  }
3376 
3377  // Fall back to use extracts and build vector.
3378  EVT EltVT = WidenVT.getVectorElementType();
3379  SmallVector<SDValue, 16> Ops(WidenNumElts);
3380  unsigned Idx = 0;
3381  for (unsigned i=0; i < NumOperands; ++i) {
3382  SDValue InOp = N->getOperand(i);
3383  if (InputWidened)
3384  InOp = GetWidenedVector(InOp);
3385  for (unsigned j=0; j < NumInElts; ++j)
3386  Ops[Idx++] = DAG.getNode(
3387  ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3388  DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3389  }
3390  SDValue UndefVal = DAG.getUNDEF(EltVT);
3391  for (; Idx < WidenNumElts; ++Idx)
3392  Ops[Idx] = UndefVal;
3393  return DAG.getBuildVector(WidenVT, dl, Ops);
3394 }
3395 
3396 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
3397  EVT VT = N->getValueType(0);
3398  EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3399  unsigned WidenNumElts = WidenVT.getVectorNumElements();
3400  SDValue InOp = N->getOperand(0);
3401  SDValue Idx = N->getOperand(1);
3402  SDLoc dl(N);
3403 
3404  if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
3405  InOp = GetWidenedVector(InOp);
3406 
3407  EVT InVT = InOp.getValueType();
3408 
3409  // Check if we can just return the input vector after widening.
3410  uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
3411  if (IdxVal == 0 && InVT == WidenVT)
3412  return InOp;
3413 
3414  // Check if we can extract from the vector.
3415  unsigned InNumElts = InVT.getVectorNumElements();
3416  if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
3417  return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
3418 
3419  // We could try widening the input to the right length but for now, extract
3420  // the original elements, fill the rest with undefs and build a vector.
3421  SmallVector<SDValue, 16> Ops(WidenNumElts);
3422  EVT EltVT = VT.getVectorElementType();
3423  unsigned NumElts = VT.getVectorNumElements();
3424  unsigned i;
3425  for (i=0; i < NumElts; ++i)
3426  Ops[i] =
3427  DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3428  DAG.getConstant(IdxVal + i, dl,
3429  TLI.getVectorIdxTy(DAG.getDataLayout())));
3430 
3431  SDValue UndefVal = DAG.getUNDEF(EltVT);
3432  for (; i < WidenNumElts; ++i)
3433  Ops[i] = UndefVal;
3434  return DAG.getBuildVector(WidenVT, dl, Ops);
3435 }
3436 
3437 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
3438  SDValue InOp = GetWidenedVector(N->getOperand(0));
3439  return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N),
3440  InOp.getValueType(), InOp,
3441  N->getOperand(1), N->getOperand(2));
3442 }
3443 
3444 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
3445  LoadSDNode *LD = cast<LoadSDNode>(N);
3447 
3448  SDValue Result;
3449  SmallVector<SDValue, 16> LdChain; // Chain for the series of load
3450  if (ExtType != ISD::NON_EXTLOAD)
3451  Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
3452  else
3453  Result = GenWidenVectorLoads(LdChain, LD);
3454 
3455  // If we generate a single load, we can use that for the chain. Otherwise,
3456  // build a factor node to remember the multiple loads are independent and
3457  // chain to that.
3458  SDValue NewChain;
3459  if (LdChain.size() == 1)
3460  NewChain = LdChain[0];
3461  else
3462  NewChain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, LdChain);
3463 
3464  // Modified the chain - switch anything that used the old chain to use
3465  // the new one.
3466  ReplaceValueWith(SDValue(N, 1), NewChain);
3467 
3468  return Result;
3469 }
3470 
3471 SDValue DAGTypeLegalizer::WidenVecRes_MLOAD(MaskedLoadSDNode *N) {
3472 
3473  EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),N->getValueType(0));
3474  SDValue Mask = N->getMask();
3475  EVT MaskVT = Mask.getValueType();
3476  SDValue PassThru = GetWidenedVector(N->getPassThru());
3478  SDLoc dl(N);
3479 
3480  // The mask should be widened as well
3481  EVT WideMaskVT = EVT::getVectorVT(*DAG.getContext(),
3482  MaskVT.getVectorElementType(),
3483  WidenVT.getVectorNumElements());
3484  Mask = ModifyToType(Mask, WideMaskVT, true);
3485 
3486  SDValue Res = DAG.getMaskedLoad(WidenVT, dl, N->getChain(), N->getBasePtr(),
3487  Mask, PassThru, N->getMemoryVT(),
3488  N->getMemOperand(), ExtType,
3489  N->isExpandingLoad());
3490  // Legalize the chain result - switch anything that used the old chain to
3491  // use the new one.
3492  ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
3493  return Res;
3494 }
3495 
3496 SDValue DAGTypeLegalizer::WidenVecRes_MGATHER(MaskedGatherSDNode *N) {
3497 
3498  EVT WideVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3499  SDValue Mask = N->getMask();
3500  EVT MaskVT = Mask.getValueType();
3501  SDValue PassThru = GetWidenedVector(N->getPassThru());
3502  SDValue Scale = N->getScale();
3503  unsigned NumElts = WideVT.getVectorNumElements();
3504  SDLoc dl(N);
3505 
3506  // The mask should be widened as well
3507  EVT WideMaskVT = EVT::getVectorVT(*DAG.getContext(),
3508  MaskVT.getVectorElementType(),
3509  WideVT.getVectorNumElements());
3510  Mask = ModifyToType(Mask, WideMaskVT, true);
3511 
3512  // Widen the Index operand
3513  SDValue Index = N->getIndex();
3514  EVT WideIndexVT = EVT::getVectorVT(*DAG.getContext(),
3515  Index.getValueType().getScalarType(),
3516  NumElts);
3517  Index = ModifyToType(Index, WideIndexVT);
3518  SDValue Ops[] = { N->getChain(), PassThru, Mask, N->getBasePtr(), Index,
3519  Scale };
3520  SDValue Res = DAG.getMaskedGather(DAG.getVTList(WideVT, MVT::Other),
3521  N->getMemoryVT(), dl, Ops,
3522  N->getMemOperand());
3523 
3524  // Legalize the chain result - switch anything that used the old chain to
3525  // use the new one.
3526  ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
3527  return Res;
3528 }
3529 
3530 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
3531  EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3532  return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N),
3533  WidenVT, N->getOperand(0));
3534 }
3535 
3536 // Return true if this is a node that could have two SETCCs as operands.
3537 static inline bool isLogicalMaskOp(unsigned Opcode) {
3538  switch (Opcode) {
3539  case ISD::AND:
3540  case ISD::OR:
3541  case ISD::XOR:
3542  return true;
3543  }
3544  return false;
3545 }
3546 
3547 // This is used just for the assert in convertMask(). Check that this either
3548 // a SETCC or a previously handled SETCC by convertMask().
3549 #ifndef NDEBUG
3550 static inline bool isSETCCorConvertedSETCC(SDValue N) {
3551  if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
3552  N = N.getOperand(0);
3553  else if (N.getOpcode() == ISD::CONCAT_VECTORS) {
3554  for (unsigned i = 1; i < N->getNumOperands(); ++i)
3555  if (!N->getOperand(i)->isUndef())
3556  return false;
3557  N = N.getOperand(0);
3558  }
3559 
3560  if (N.getOpcode() == ISD::TRUNCATE)
3561  N = N.getOperand(0);
3562  else if (N.getOpcode() == ISD::SIGN_EXTEND)
3563  N = N.getOperand(0);
3564 
3565  if (isLogicalMaskOp(N.getOpcode()))
3566  return isSETCCorConvertedSETCC(N.getOperand(0)) &&
3568 
3569  return (N.getOpcode() == ISD::SETCC ||
3571 }
3572 #endif
3573 
3574 // Return a mask of vector type MaskVT to replace InMask. Also adjust MaskVT
3575 // to ToMaskVT if needed with vector extension or truncation.
3576 SDValue DAGTypeLegalizer::convertMask(SDValue InMask, EVT MaskVT,
3577  EVT ToMaskVT) {
3578  // Currently a SETCC or a AND/OR/XOR with two SETCCs are handled.
3579  // FIXME: This code seems to be too restrictive, we might consider
3580  // generalizing it or dropping it.
3581  assert(isSETCCorConvertedSETCC(InMask) && "Unexpected mask argument.");
3582 
3583  // Make a new Mask node, with a legal result VT.
3585  for (unsigned i = 0, e = InMask->getNumOperands(); i < e; ++i)
3586  Ops.push_back(InMask->getOperand(i));
3587  SDValue Mask = DAG.getNode(InMask->getOpcode(), SDLoc(InMask), MaskVT, Ops);
3588 
3589  // If MaskVT has smaller or bigger elements than ToMaskVT, a vector sign
3590  // extend or truncate is needed.
3591  LLVMContext &Ctx = *DAG.getContext();
3592  unsigned MaskScalarBits = MaskVT.getScalarSizeInBits();
3593  unsigned ToMaskScalBits = ToMaskVT.getScalarSizeInBits();
3594  if (MaskScalarBits < ToMaskScalBits) {
3595  EVT ExtVT = EVT::getVectorVT(Ctx, ToMaskVT.getVectorElementType(),
3596  MaskVT.getVectorNumElements());
3597  Mask = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Mask), ExtVT, Mask);
3598  } else if (MaskScalarBits > ToMaskScalBits) {
3599  EVT TruncVT = EVT::getVectorVT(Ctx, ToMaskVT.getVectorElementType(),
3600  MaskVT.getVectorNumElements());
3601  Mask = DAG.getNode(ISD::TRUNCATE, SDLoc(Mask), TruncVT, Mask);
3602  }
3603 
3605  ToMaskVT.getScalarSizeInBits() &&
3606  "Mask should have the right element size by now.");
3607 
3608  // Adjust Mask to the right number of elements.
3609  unsigned CurrMaskNumEls = Mask->getValueType(0).getVectorNumElements();
3610  if (CurrMaskNumEls > ToMaskVT.getVectorNumElements()) {
3611  MVT IdxTy = TLI.getVectorIdxTy(DAG.getDataLayout());
3612  SDValue ZeroIdx = DAG.getConstant(0, SDLoc(Mask), IdxTy);
3613  Mask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(Mask), ToMaskVT, Mask,
3614  ZeroIdx);
3615  } else if (CurrMaskNumEls < ToMaskVT.getVectorNumElements()) {
3616  unsigned NumSubVecs = (ToMaskVT.getVectorNumElements() / CurrMaskNumEls);
3617  EVT SubVT = Mask->getValueType(0);
3618  SmallVector<SDValue, 16> SubOps(NumSubVecs, DAG.getUNDEF(SubVT));
3619  SubOps[0] = Mask;
3620  Mask = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Mask), ToMaskVT, SubOps);
3621  }
3622 
3623  assert((Mask->getValueType(0) == ToMaskVT) &&
3624  "A mask of ToMaskVT should have been produced by now.");
3625 
3626  return Mask;
3627 }
3628 
3629 // This method tries to handle VSELECT and its mask by legalizing operands
3630 // (which may require widening) and if needed adjusting the mask vector type
3631 // to match that of the VSELECT. Without it, many cases end up with
3632 // scalarization of the SETCC, with many unnecessary instructions.
3633 SDValue DAGTypeLegalizer::WidenVSELECTAndMask(SDNode *N) {
3634  LLVMContext &Ctx = *DAG.getContext();
3635  SDValue Cond = N->getOperand(0);
3636 
3637  if (N->getOpcode() != ISD::VSELECT)
3638  return SDValue();
3639 
3640  if (Cond->getOpcode() != ISD::SETCC && !isLogicalMaskOp(Cond->getOpcode()))
3641  return SDValue();
3642 
3643  // If this is a splitted VSELECT that was previously already handled, do
3644  // nothing.
3645  EVT CondVT = Cond->getValueType(0);
3646  if (CondVT.getScalarSizeInBits() != 1)
3647  return SDValue();
3648 
3649  EVT VSelVT = N->getValueType(0);
3650  // Only handle vector types which are a power of 2.
3651  if (!isPowerOf2_64(VSelVT.getSizeInBits()))
3652  return SDValue();
3653 
3654  // Don't touch if this will be scalarized.
3655  EVT FinalVT = VSelVT;
3656  while (getTypeAction(FinalVT) == TargetLowering::TypeSplitVector)
3657  FinalVT = FinalVT.getHalfNumVectorElementsVT(Ctx);
3658 
3659  if (FinalVT.getVectorNumElements() == 1)
3660  return SDValue();
3661 
3662  // If there is support for an i1 vector mask, don't touch.
3663  if (Cond.getOpcode() == ISD::SETCC) {
3664  EVT SetCCOpVT = Cond->getOperand(0).getValueType();
3665  while (TLI.getTypeAction(Ctx, SetCCOpVT) != TargetLowering::TypeLegal)
3666  SetCCOpVT = TLI.getTypeToTransformTo(Ctx, SetCCOpVT);
3667  EVT SetCCResVT = getSetCCResultType(SetCCOpVT);
3668  if (SetCCResVT.getScalarSizeInBits() == 1)
3669  return SDValue();
3670  } else if (CondVT.getScalarType() == MVT::i1) {
3671  // If there is support for an i1 vector mask (or only scalar i1 conditions),
3672  // don't touch.
3673  while (TLI.getTypeAction(Ctx, CondVT) != TargetLowering::TypeLegal)
3674  CondVT = TLI.getTypeToTransformTo(Ctx, CondVT);
3675 
3676  if (CondVT.getScalarType() == MVT::i1)
3677  return SDValue();
3678  }
3679 
3680  // Get the VT and operands for VSELECT, and widen if needed.
3681  SDValue VSelOp1 = N->getOperand(1);
3682  SDValue VSelOp2 = N->getOperand(2);
3683  if (getTypeAction(VSelVT) == TargetLowering::TypeWidenVector) {
3684  VSelVT = TLI.getTypeToTransformTo(Ctx, VSelVT);
3685  VSelOp1 = GetWidenedVector(VSelOp1);
3686  VSelOp2 = GetWidenedVector(VSelOp2);
3687  }
3688 
3689  // The mask of the VSELECT should have integer elements.
3690  EVT ToMaskVT = VSelVT;
3691  if (!ToMaskVT.getScalarType().isInteger())
3692  ToMaskVT = ToMaskVT.changeVectorElementTypeToInteger();
3693 
3694  SDValue Mask;
3695  if (Cond->getOpcode() == ISD::SETCC) {
3696  EVT MaskVT = getSetCCResultType(Cond.getOperand(0).getValueType());
3697  Mask = convertMask(Cond, MaskVT, ToMaskVT);
3698  } else if (isLogicalMaskOp(Cond->getOpcode()) &&
3699  Cond->getOperand(0).getOpcode() == ISD::SETCC &&
3700  Cond->getOperand(1).getOpcode() == ISD::SETCC) {
3701  // Cond is (AND/OR/XOR (SETCC, SETCC))
3702  SDValue SETCC0 = Cond->getOperand(0);
3703  SDValue SETCC1 = Cond->getOperand(1);
3704  EVT VT0 = getSetCCResultType(SETCC0.getOperand(0).getValueType());
3705  EVT VT1 = getSetCCResultType(SETCC1.getOperand(0).getValueType());
3706  unsigned ScalarBits0 = VT0.getScalarSizeInBits();
3707  unsigned ScalarBits1 = VT1.getScalarSizeInBits();
3708  unsigned ScalarBits_ToMask = ToMaskVT.getScalarSizeInBits();
3709  EVT MaskVT;
3710  // If the two SETCCs have different VTs, either extend/truncate one of
3711  // them to the other "towards" ToMaskVT, or truncate one and extend the
3712  // other to ToMaskVT.
3713  if (ScalarBits0 != ScalarBits1) {
3714  EVT NarrowVT = ((ScalarBits0 < ScalarBits1) ? VT0 : VT1);
3715  EVT WideVT = ((NarrowVT == VT0) ? VT1 : VT0);
3716  if (ScalarBits_ToMask >= WideVT.getScalarSizeInBits())
3717  MaskVT = WideVT;
3718  else if (ScalarBits_ToMask <= NarrowVT.getScalarSizeInBits())
3719  MaskVT = NarrowVT;
3720  else
3721  MaskVT = ToMaskVT;
3722  } else
3723  // If the two SETCCs have the same VT, don't change it.
3724  MaskVT = VT0;
3725 
3726  // Make new SETCCs and logical nodes.
3727  SETCC0 = convertMask(SETCC0, VT0, MaskVT);
3728  SETCC1 = convertMask(SETCC1, VT1, MaskVT);
3729  Cond = DAG.getNode(Cond->getOpcode(), SDLoc(Cond), MaskVT, SETCC0, SETCC1);
3730 
3731  // Convert the logical op for VSELECT if needed.
3732  Mask = convertMask(Cond, MaskVT, ToMaskVT);
3733  } else
3734  return SDValue();
3735 
3736  return DAG.getNode(ISD::VSELECT, SDLoc(N), VSelVT, Mask, VSelOp1, VSelOp2);
3737 }
3738 
3739 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
3740  EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3741  unsigned WidenNumElts = WidenVT.getVectorNumElements();
3742 
3743  SDValue Cond1 = N->getOperand(0);
3744  EVT CondVT = Cond1.getValueType();
3745  if (CondVT.isVector()) {
3746  if (SDValue Res = WidenVSELECTAndMask(N))
3747  return Res;
3748 
3749  EVT CondEltVT = CondVT.getVectorElementType();
3750  EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
3751  CondEltVT, WidenNumElts);
3752  if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
3753  Cond1 = GetWidenedVector(Cond1);
3754 
3755  // If we have to split the condition there is no point in widening the
3756  // select. This would result in an cycle of widening the select ->
3757  // widening the condition operand -> splitting the condition operand ->
3758  // splitting the select -> widening the select. Instead split this select
3759  // further and widen the resulting type.
3760  if (getTypeAction(CondVT) == TargetLowering::TypeSplitVector) {
3761  SDValue SplitSelect = SplitVecOp_VSELECT(N, 0);
3762  SDValue Res = ModifyToType(SplitSelect, WidenVT);
3763  return Res;
3764  }
3765 
3766  if (Cond1.getValueType() != CondWidenVT)
3767  Cond1 = ModifyToType(Cond1, CondWidenVT);
3768  }
3769 
3770  SDValue InOp1 = GetWidenedVector(N->getOperand(1));
3771  SDValue InOp2 = GetWidenedVector(N->getOperand(2));
3772  assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
3773  return DAG.getNode(N->getOpcode(), SDLoc(N),
3774  WidenVT, Cond1, InOp1, InOp2);
3775 }
3776 
3777 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
3778  SDValue InOp1 = GetWidenedVector(N->getOperand(2));
3779  SDValue InOp2 = GetWidenedVector(N->getOperand(3));
3780  return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
3781  InOp1.getValueType(), N->getOperand(0),
3782  N->getOperand(1), InOp1, InOp2, N->getOperand(4));
3783 }
3784 
3785 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
3786  EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3787  return DAG.getUNDEF(WidenVT);
3788 }
3789 
3790 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
3791  EVT VT = N->getValueType(0);
3792  SDLoc dl(N);
3793 
3794  EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3795  unsigned NumElts = VT.getVectorNumElements();
3796  unsigned WidenNumElts = WidenVT.getVectorNumElements();
3797 
3798  SDValue InOp1 = GetWidenedVector(N->getOperand(0));
3799  SDValue InOp2 = GetWidenedVector(N->getOperand(1));
3800 
3801  // Adjust mask based on new input vector length.
3802  SmallVector<int, 16> NewMask;
3803  for (unsigned i = 0; i != NumElts; ++i) {
3804  int Idx = N->getMaskElt(i);
3805  if (Idx < (int)NumElts)
3806  NewMask.push_back(Idx);
3807  else
3808  NewMask.push_back(Idx - NumElts + WidenNumElts);
3809  }
3810  for (unsigned i = NumElts; i != WidenNumElts; ++i)
3811  NewMask.push_back(-1);
3812  return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, NewMask);
3813 }
3814 
3815 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
3816  assert(N->getValueType(0).isVector() &&
3817  N->getOperand(0).getValueType().isVector() &&
3818  "Operands must be vectors");
3819  EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3820  unsigned WidenNumElts = WidenVT.getVectorNumElements();
3821 
3822  SDValue InOp1 = N->getOperand(0);
3823  EVT InVT = InOp1.getValueType();
3824  assert(InVT.isVector() && "can not widen non-vector type");
3825  EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
3826  InVT.getVectorElementType(), WidenNumElts);
3827 
3828  // The input and output types often differ here, and it could be that while
3829  // we'd prefer to widen the result type, the input operands have been split.
3830  // In this case, we also need to split the result of this node as well.
3831  if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) {
3832  SDValue SplitVSetCC = SplitVecOp_VSETCC(N);
3833  SDValue Res = ModifyToType(SplitVSetCC, WidenVT);
3834  return Res;
3835  }
3836 
3837  // If the inputs also widen, handle them directly. Otherwise widen by hand.
3838  SDValue InOp2 = N->getOperand(1);
3839  if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
3840  InOp1 = GetWidenedVector(InOp1);
3841  InOp2 = GetWidenedVector(InOp2);
3842  } else {
3843  InOp1 = DAG.WidenVector(InOp1, SDLoc(N));
3844  InOp2 = DAG.WidenVector(InOp2, SDLoc(N));
3845  }
3846 
3847  // Assume that the input and output will be widen appropriately. If not,
3848  // we will have to unroll it at some point.
3849  assert(InOp1.getValueType() == WidenInVT &&
3850  InOp2.getValueType() == WidenInVT &&
3851  "Input not widened to expected type!");
3852  (void)WidenInVT;
3853  return DAG.getNode(ISD::SETCC, SDLoc(N),
3854  WidenVT, InOp1, InOp2, N->getOperand(2));
3855 }
3856 
3857 
3858 //===----------------------------------------------------------------------===//
3859 // Widen Vector Operand
3860 //===----------------------------------------------------------------------===//
3861 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
3862  LLVM_DEBUG(dbgs() << "Widen node operand " << OpNo << ": "; N->dump(&DAG);
3863  dbgs() << "\n");
3864  SDValue Res = SDValue();
3865 
3866  // See if the target wants to custom widen this node.
3867  if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
3868  return false;
3869 
3870  switch (N->getOpcode()) {
3871  default:
3872 #ifndef NDEBUG
3873  dbgs() << "WidenVectorOperand op #" << OpNo << ": ";
3874  N->dump(&DAG);
3875  dbgs() << "\n";
3876 #endif
3877  llvm_unreachable("Do not know how to widen this operator's operand!");
3878 
3879  case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
3880  case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
3881  case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
3882  case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
3883  case ISD::STORE: Res = WidenVecOp_STORE(N); break;
3884  case ISD::MSTORE: Res = WidenVecOp_MSTORE(N, OpNo); break;
3885  case ISD::MGATHER: Res = WidenVecOp_MGATHER(N, OpNo); break;
3886  case ISD::MSCATTER: Res = WidenVecOp_MSCATTER(N, OpNo); break;
3887  case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
3888  case ISD::VSELECT: Res = WidenVecOp_VSELECT(N); break;
3889  case ISD::FCOPYSIGN: Res = WidenVecOp_FCOPYSIGN(N); break;
3890 
3891  case ISD::ANY_EXTEND:
3892  case ISD::SIGN_EXTEND:
3893  case ISD::ZERO_EXTEND:
3894  Res = WidenVecOp_EXTEND(N);
3895  break;
3896 
3897  case ISD::FP_EXTEND:
3898  case ISD::FP_TO_SINT:
3899  case ISD::FP_TO_UINT:
3900  case ISD::SINT_TO_FP:
3901  case ISD::UINT_TO_FP:
3902  case ISD::TRUNCATE:
3903  Res = WidenVecOp_Convert(N);
3904  break;
3905 
3906  case ISD::VECREDUCE_FADD:
3907  case ISD::VECREDUCE_FMUL:
3908  case ISD::VECREDUCE_ADD:
3909  case ISD::VECREDUCE_MUL:
3910  case ISD::VECREDUCE_AND:
3911  case ISD::VECREDUCE_OR:
3912  case ISD::VECREDUCE_XOR:
3913  case ISD::VECREDUCE_SMAX:
3914  case ISD::VECREDUCE_SMIN:
3915  case ISD::VECREDUCE_UMAX:
3916  case ISD::VECREDUCE_UMIN:
3917  case ISD::VECREDUCE_FMAX:
3918  case ISD::VECREDUCE_FMIN:
3919  Res = WidenVecOp_VECREDUCE(N);
3920  break;
3921  }
3922 
3923  // If Res is null, the sub-method took care of registering the result.
3924  if (!Res.getNode()) return false;
3925 
3926  // If the result is N, the sub-method updated N in place. Tell the legalizer
3927  // core about this.
3928  if (Res.getNode() == N)
3929  return true;
3930 
3931 
3932  assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
3933  "Invalid operand expansion");
3934 
3935  ReplaceValueWith(SDValue(N, 0), Res);
3936  return false;
3937 }
3938 
3939 SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {
3940  SDLoc DL(N);
3941  EVT VT = N->getValueType(0);
3942 
3943  SDValue InOp = N->getOperand(0);
3944  assert(getTypeAction(InOp.getValueType()) ==
3946  "Unexpected type action");
3947  InOp = GetWidenedVector(InOp);
3950  "Input wasn't widened!");
3951 
3952  // We may need to further widen the operand until it has the same total
3953  // vector size as the result.
3954  EVT InVT = InOp.getValueType();
3955  if (InVT.getSizeInBits() != VT.getSizeInBits()) {
3956  EVT InEltVT = InVT.getVectorElementType();
3957  for (int i = MVT::FIRST_VECTOR_VALUETYPE, e = MVT::LAST_VECTOR_VALUETYPE; i < e; ++i) {
3958  EVT FixedVT = (MVT::SimpleValueType)i;
3959  EVT FixedEltVT = FixedVT.getVectorElementType();
3960  if (TLI.isTypeLegal(FixedVT) &&
3961  FixedVT.getSizeInBits() == VT.getSizeInBits() &&
3962  FixedEltVT == InEltVT) {
3963  assert(FixedVT.getVectorNumElements() >= VT.getVectorNumElements() &&
3964  "Not enough elements in the fixed type for the operand!");
3965  assert(FixedVT.getVectorNumElements() != InVT.getVectorNumElements() &&
3966  "We can't have the same type as we started with!");
3967  if (FixedVT.getVectorNumElements() > InVT.getVectorNumElements())
3968  InOp = DAG.getNode(
3969  ISD::INSERT_SUBVECTOR, DL, FixedVT, DAG.getUNDEF(FixedVT), InOp,
3970  DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
3971  else
3972  InOp = DAG.getNode(
3973  ISD::EXTRACT_SUBVECTOR, DL, FixedVT, InOp,
3974  DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
3975  break;
3976  }
3977  }
3978  InVT = InOp.getValueType();
3979  if (InVT.getSizeInBits() != VT.getSizeInBits())
3980  // We couldn't find a legal vector type that was a widening of the input
3981  // and could be extended in-register to the result type, so we have to
3982  // scalarize.
3983  return WidenVecOp_Convert(N);
3984  }
3985 
3986  // Use special DAG nodes to represent the operation of extending the
3987  // low lanes.
3988  switch (N->getOpcode()) {
3989  default:
3990  llvm_unreachable("Extend legalization on extend operation!");
3991  case ISD::ANY_EXTEND:
3992  return DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, VT, InOp);
3993  case ISD::SIGN_EXTEND:
3994  return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, VT, InOp);
3995  case ISD::ZERO_EXTEND:
3996  return DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, DL, VT, InOp);
3997  }
3998 }
3999 
4000 SDValue DAGTypeLegalizer::WidenVecOp_FCOPYSIGN(SDNode *N) {
4001  // The result (and first input) is legal, but the second input is illegal.
4002  // We can't do much to fix that, so just unroll and let the extracts off of
4003  // the second input be widened as needed later.
4004  return DAG.UnrollVectorOp(N);
4005 }
4006 
4007 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
4008  // Since the result is legal and the input is illegal.
4009  EVT VT = N->getValueType(0);
4010  EVT EltVT = VT.getVectorElementType();
4011  SDLoc dl(N);
4012  unsigned NumElts = VT.getVectorNumElements();
4013  SDValue InOp = N->getOperand(0);
4014  assert(getTypeAction(InOp.getValueType()) ==
4016  "Unexpected type action");
4017  InOp = GetWidenedVector(InOp);
4018  EVT InVT = InOp.getValueType();
4019  unsigned Opcode = N->getOpcode();
4020 
4021  // See if a widened result type would be legal, if so widen the node.
4022  EVT WideVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
4023  InVT.getVectorNumElements());
4024  if (TLI.isTypeLegal(WideVT)) {
4025  SDValue Res = DAG.getNode(Opcode, dl, WideVT, InOp);
4026  return DAG.getNode(
4027  ISD::EXTRACT_SUBVECTOR, dl, VT, Res,
4028  DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4029  }
4030 
4031  EVT InEltVT = InVT.getVectorElementType();
4032 
4033  // Unroll the convert into some scalar code and create a nasty build vector.
4034  SmallVector<SDValue, 16> Ops(NumElts);
4035  for (unsigned i=0; i < NumElts; ++i)
4036  Ops[i] = DAG.getNode(
4037  Opcode, dl, EltVT,
4038  DAG.getNode(
4039  ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
4040  DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
4041 
4042  return DAG.getBuildVector(VT, dl, Ops);
4043 }
4044 
4045 SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
4046  EVT VT = N->getValueType(0);
4047  SDValue InOp = GetWidenedVector(N->getOperand(0));
4048  EVT InWidenVT = InOp.getValueType();
4049  SDLoc dl(N);
4050 
4051  // Check if we can convert between two legal vector types and extract.
4052  unsigned InWidenSize = InWidenVT.getSizeInBits();
4053  unsigned Size = VT.getSizeInBits();
4054  // x86mmx is not an acceptable vector element type, so don't try.
4055  if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
4056  unsigned NewNumElts = InWidenSize / Size;
4057  EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
4058  if (TLI.isTypeLegal(NewVT)) {
4059  SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
4060  return DAG.getNode(
4061  ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
4062  DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4063  }
4064  }
4065 
4066  return CreateStackStoreLoad(InOp, VT);
4067 }
4068 
4069 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
4070  EVT VT = N->getValueType(0);
4071  EVT EltVT = VT.getVectorElementType();
4072  EVT InVT = N->getOperand(0).getValueType();
4073  SDLoc dl(N);
4074 
4075  // If the widen width for this operand is the same as the width of the concat
4076  // and all but the first operand is undef, just use the widened operand.
4077  unsigned NumOperands = N->getNumOperands();
4078  if (VT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
4079  unsigned i;
4080  for (i = 1; i < NumOperands; ++i)
4081  if (!N->getOperand(i).isUndef())
4082  break;
4083 
4084  if (i == NumOperands)
4085  return GetWidenedVector(N->getOperand(0));
4086  }
4087 
4088  // Otherwise, fall back to a nasty build vector.
4089  unsigned NumElts = VT.getVectorNumElements();
4090  SmallVector<SDValue, 16> Ops(NumElts);
4091 
4092  unsigned NumInElts = InVT.getVectorNumElements();
4093 
4094  unsigned Idx = 0;
4095  for (unsigned i=0; i < NumOperands; ++i) {
4096  SDValue InOp = N->getOperand(i);
4097  assert(getTypeAction(InOp.getValueType()) ==
4099  "Unexpected type action");
4100  InOp = GetWidenedVector(InOp);
4101  for (unsigned j=0; j < NumInElts; ++j)
4102  Ops[Idx++] = DAG.getNode(
4103  ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
4104  DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4105  }
4106  return DAG.getBuildVector(VT, dl, Ops);
4107 }
4108 
4109 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
4110  SDValue InOp = GetWidenedVector(N->getOperand(0));
4111  return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N),
4112  N->getValueType(0), InOp, N->getOperand(1));
4113 }
4114 
4115 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
4116  SDValue InOp = GetWidenedVector(N->getOperand(0));
4117  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
4118  N->getValueType(0), InOp, N->getOperand(1));
4119 }
4120 
4121 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
4122  // We have to widen the value, but we want only to store the original
4123  // vector type.
4124  StoreSDNode *ST = cast<StoreSDNode>(N);
4125 
4126  if (!ST->getMemoryVT().getScalarType().isByteSized())
4127  return TLI.scalarizeVectorStore(ST, DAG);
4128 
4129  SmallVector<SDValue, 16> StChain;
4130  if (ST->isTruncatingStore())
4131  GenWidenVectorTruncStores(StChain, ST);
4132  else
4133  GenWidenVectorStores(StChain, ST);
4134 
4135  if (StChain.size() == 1)
4136  return StChain[0];
4137  else
4138  return DAG.getNode(ISD::TokenFactor, SDLoc(ST), MVT::Other, StChain);
4139 }
4140 
4141 SDValue DAGTypeLegalizer::WidenVecOp_MSTORE(SDNode *N, unsigned OpNo) {
4142  assert((OpNo == 1 || OpNo == 3) &&
4143  "Can widen only data or mask operand of mstore");
4144  MaskedStoreSDNode *MST = cast<MaskedStoreSDNode>(N);
4145  SDValue Mask = MST->getMask();
4146  EVT MaskVT = Mask.getValueType();
4147  SDValue StVal = MST->getValue();
4148  SDLoc dl(N);
4149 
4150  if (OpNo == 1) {
4151  // Widen the value.
4152  StVal = GetWidenedVector(StVal);
4153 
4154  // The mask should be widened as well.
4155  EVT WideVT = StVal.getValueType();
4156  EVT WideMaskVT = EVT::getVectorVT(*DAG.getContext(),
4157  MaskVT.getVectorElementType(),
4158  WideVT.getVectorNumElements());
4159  Mask = ModifyToType(Mask, WideMaskVT, true);
4160  } else {
4161  // Widen the mask.
4162  EVT WideMaskVT = TLI.getTypeToTransformTo(*DAG.getContext(), MaskVT);
4163  Mask = ModifyToType(Mask, WideMaskVT, true);
4164 
4165  EVT ValueVT = StVal.getValueType();
4166  EVT WideVT = EVT::getVectorVT(*DAG.getContext(),
4167  ValueVT.getVectorElementType(),
4168  WideMaskVT.getVectorNumElements());
4169  StVal = ModifyToType(StVal, WideVT);
4170  }
4171 
4172  assert(Mask.getValueType().getVectorNumElements() ==
4173  StVal.getValueType().getVectorNumElements() &&
4174  "Mask and data vectors should have the same number of elements");
4175  return DAG.getMaskedStore(MST->getChain(), dl, StVal, MST->getBasePtr(),
4176  Mask, MST->getMemoryVT(), MST->getMemOperand(),
4177  false, MST->isCompressingStore());
4178 }
4179 
4180 SDValue DAGTypeLegalizer::WidenVecOp_MGATHER(SDNode *N, unsigned OpNo) {
4181  assert(OpNo == 4 && "Can widen only the index of mgather");
4182  auto *MG = cast<MaskedGatherSDNode>(N);
4183  SDValue DataOp = MG->getPassThru();
4184  SDValue Mask = MG->getMask();
4185  SDValue Scale = MG->getScale();
4186 
4187  // Just widen the index. It's allowed to have extra elements.
4188  SDValue Index = GetWidenedVector(MG->getIndex());
4189 
4190  SDLoc dl(N);
4191  SDValue Ops[] = {MG->getChain(), DataOp, Mask, MG->getBasePtr(), Index,
4192  Scale};
4193  SDValue Res = DAG.getMaskedGather(MG->getVTList(), MG->getMemoryVT(), dl, Ops,
4194  MG->getMemOperand());
4195  ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
4196  ReplaceValueWith(SDValue(N, 0), Res.getValue(0));
4197  return SDValue();
4198 }
4199 
4200 SDValue DAGTypeLegalizer::WidenVecOp_MSCATTER(SDNode *N, unsigned OpNo) {
4201  MaskedScatterSDNode *MSC = cast<MaskedScatterSDNode>(N);
4202  SDValue DataOp = MSC->getValue();
4203  SDValue Mask = MSC->getMask();
4204  SDValue Index = MSC->getIndex();
4205  SDValue Scale = MSC->getScale();
4206 
4207  unsigned NumElts;
4208  if (OpNo == 1) {
4209  DataOp = GetWidenedVector(DataOp);
4210  NumElts = DataOp.getValueType().getVectorNumElements();
4211 
4212  // Widen index.
4213  EVT IndexVT = Index.getValueType();
4214  EVT WideIndexVT = EVT::getVectorVT(*DAG.getContext(),
4215  IndexVT.getVectorElementType(), NumElts);
4216  Index = ModifyToType(Index, WideIndexVT);
4217 
4218  // The mask should be widened as well.
4219  EVT MaskVT = Mask.getValueType();
4220  EVT WideMaskVT = EVT::getVectorVT(*DAG.getContext(),
4221  MaskVT.getVectorElementType(), NumElts);
4222  Mask = ModifyToType(Mask, WideMaskVT, true);
4223  } else if (OpNo == 4) {
4224  // Just widen the index. It's allowed to have extra elements.
4225  Index = GetWidenedVector(Index);
4226  } else
4227  llvm_unreachable("Can't widen this operand of mscatter");
4228 
4229  SDValue Ops[] = {MSC->getChain(), DataOp, Mask, MSC->getBasePtr(), Index,
4230  Scale};
4231  return DAG.getMaskedScatter(DAG.getVTList(MVT::Other),
4232  MSC->getMemoryVT(), SDLoc(N), Ops,
4233  MSC->getMemOperand());
4234 }
4235 
4236 SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {
4237  SDValue InOp0 = GetWidenedVector(N->getOperand(0));
4238  SDValue InOp1 = GetWidenedVector(N->getOperand(1));
4239  SDLoc dl(N);
4240  EVT VT = N->getValueType(0);
4241 
4242  // WARNING: In this code we widen the compare instruction with garbage.
4243  // This garbage may contain denormal floats which may be slow. Is this a real
4244  // concern ? Should we zero the unused lanes if this is a float compare ?
4245 
4246  // Get a new SETCC node to compare the newly widened operands.
4247  // Only some of the compared elements are legal.
4248  EVT SVT = TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
4249  InOp0.getValueType());
4250  // The result type is legal, if its vXi1, keep vXi1 for the new SETCC.
4251  if (VT.getScalarType() == MVT::i1)
4252  SVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
4253  SVT.getVectorNumElements());
4254 
4255  SDValue WideSETCC = DAG.getNode(ISD::SETCC, SDLoc(N),
4256  SVT, InOp0, InOp1, N->getOperand(2));
4257 
4258  // Extract the needed results from the result vector.
4259  EVT ResVT = EVT::getVectorVT(*DAG.getContext(),
4260  SVT.getVectorElementType(),
4261  VT.getVectorNumElements());
4262  SDValue CC = DAG.getNode(
4263  ISD::EXTRACT_SUBVECTOR, dl, ResVT, WideSETCC,
4264  DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4265 
4266  return PromoteTargetBoolean(CC, VT);
4267 }
4268 
4269 SDValue DAGTypeLegalizer::WidenVecOp_VECREDUCE(SDNode *N) {
4270  SDLoc dl(N);
4271  SDValue Op = GetWidenedVector(N->getOperand(0));
4272  EVT OrigVT = N->getOperand(0).getValueType();
4273  EVT WideVT = Op.getValueType();
4274  EVT ElemVT = OrigVT.getVectorElementType();
4275 
4276  SDValue NeutralElem;
4277  switch (N->getOpcode()) {
4278  case ISD::VECREDUCE_ADD:
4279  case ISD::VECREDUCE_OR:
4280  case ISD::VECREDUCE_XOR:
4281  case ISD::VECREDUCE_UMAX:
4282  NeutralElem = DAG.getConstant(0, dl, ElemVT);
4283  break;
4284  case ISD::VECREDUCE_MUL:
4285  NeutralElem = DAG.getConstant(1, dl, ElemVT);
4286  break;
4287  case ISD::VECREDUCE_AND:
4288  case ISD::VECREDUCE_UMIN:
4289  NeutralElem = DAG.getAllOnesConstant(dl, ElemVT);
4290  break;
4291  case ISD::VECREDUCE_SMAX:
4292  NeutralElem = DAG.getConstant(
4293  APInt::getSignedMinValue(ElemVT.getSizeInBits()), dl, ElemVT);
4294  break;
4295  case ISD::VECREDUCE_SMIN:
4296  NeutralElem = DAG.getConstant(
4297  APInt::getSignedMaxValue(ElemVT.getSizeInBits()), dl, ElemVT);
4298  break;
4299  case ISD::VECREDUCE_FADD:
4300  NeutralElem = DAG.getConstantFP(0.0, dl, ElemVT);
4301  break;
4302  case ISD::VECREDUCE_FMUL:
4303  NeutralElem = DAG.getConstantFP(1.0, dl, ElemVT);
4304  break;
4305  case ISD::VECREDUCE_FMAX:
4306  NeutralElem = DAG.getConstantFP(
4307  std::numeric_limits<double>::infinity(), dl, ElemVT);
4308  break;
4309  case ISD::VECREDUCE_FMIN:
4310  NeutralElem = DAG.getConstantFP(
4311  -std::numeric_limits<double>::infinity(), dl, ElemVT);
4312  break;
4313  }
4314 
4315  // Pad the vector with the neutral element.
4316  unsigned OrigElts = OrigVT.getVectorNumElements();
4317  unsigned WideElts = WideVT.getVectorNumElements();
4318  for (unsigned Idx = OrigElts; Idx < WideElts; Idx++)
4319  Op = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, WideVT, Op, NeutralElem,
4320  DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4321 
4322  return DAG.getNode(N->getOpcode(), dl, N->getValueType(0), Op, N->getFlags());
4323 }
4324 
4325 SDValue DAGTypeLegalizer::WidenVecOp_VSELECT(SDNode *N) {
4326  // This only gets called in the case that the left and right inputs and
4327  // result are of a legal odd vector type, and the condition is illegal i1 of
4328  // the same odd width that needs widening.
4329  EVT VT = N->getValueType(0);
4330  assert(VT.isVector() && !VT.isPow2VectorType() && isTypeLegal(VT));
4331 
4332  SDValue Cond = GetWidenedVector(N->getOperand(0));
4333  SDValue LeftIn = DAG.WidenVector(N->getOperand(1), SDLoc(N));
4334  SDValue RightIn = DAG.WidenVector(N->getOperand(2), SDLoc(N));
4335  SDLoc DL(N);
4336 
4337  SDValue Select = DAG.getNode(N->getOpcode(), DL, LeftIn.getValueType(), Cond,
4338  LeftIn, RightIn);
4339  return DAG.getNode(
4340  ISD::EXTRACT_SUBVECTOR, DL, VT, Select,
4341  DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
4342 }
4343 
4344 //===----------------------------------------------------------------------===//
4345 // Vector Widening Utilities
4346 //===----------------------------------------------------------------------===//
4347 
4348 // Utility function to find the type to chop up a widen vector for load/store
4349 // TLI: Target lowering used to determine legal types.
4350 // Width: Width left need to load/store.
4351 // WidenVT: The widen vector type to load to/store from
4352 // Align: If 0, don't allow use of a wider type
4353 // WidenEx: If Align is not 0, the amount additional we can load/store from.
4354 
4355 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
4356  unsigned Width, EVT WidenVT,
4357  unsigned Align = 0, unsigned WidenEx = 0) {
4358  EVT WidenEltVT = WidenVT.getVectorElementType();
4359  unsigned WidenWidth = WidenVT.getSizeInBits();
4360  unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
4361  unsigned AlignInBits = Align*8;
4362 
4363  // If we have one element to load/store, return it.
4364  EVT RetVT = WidenEltVT;
4365  if (Width == WidenEltWidth)
4366  return RetVT;
4367 
4368  // See if there is larger legal integer than the element type to load/store.
4369  unsigned VT;
4370  for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
4371  VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
4372  EVT MemVT((MVT::SimpleValueType) VT);
4373  unsigned MemVTWidth = MemVT.getSizeInBits();
4374  if (MemVT.getSizeInBits() <= WidenEltWidth)
4375  break;
4376  auto Action = TLI.getTypeAction(*DAG.getContext(), MemVT);
4377  if ((Action == TargetLowering::TypeLegal ||
4379  (WidenWidth % MemVTWidth) == 0 &&
4380  isPowerOf2_32(WidenWidth / MemVTWidth) &&
4381  (MemVTWidth <= Width ||
4382  (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
4383  if (MemVTWidth == WidenWidth)
4384  return MemVT;
4385  RetVT = MemVT;
4386  break;
4387  }
4388  }
4389 
4390  // See if there is a larger vector type to load/store that has the same vector
4391  // element type and is evenly divisible with the WidenVT.
4392  for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
4393  VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
4394  EVT MemVT = (MVT::SimpleValueType) VT;
4395  unsigned MemVTWidth = MemVT.getSizeInBits();
4396  auto Action = TLI.getTypeAction(*DAG.getContext(), MemVT);
4397  if ((Action == TargetLowering::TypeLegal ||
4399  WidenEltVT == MemVT.getVectorElementType() &&
4400  (WidenWidth % MemVTWidth) == 0 &&
4401  isPowerOf2_32(WidenWidth / MemVTWidth) &&
4402  (MemVTWidth <= Width ||
4403  (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
4404  if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
4405  return MemVT;
4406  }
4407  }
4408 
4409  return RetVT;
4410 }
4411 
4412 // Builds a vector type from scalar loads
4413 // VecTy: Resulting Vector type
4414 // LDOps: Load operators to build a vector type
4415 // [Start,End) the list of loads to use.
4417  SmallVectorImpl<SDValue> &LdOps,
4418  unsigned Start, unsigned End) {
4419  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4420  SDLoc dl(LdOps[Start]);
4421  EVT LdTy = LdOps[Start].getValueType();
4422  unsigned Width = VecTy.getSizeInBits();
4423  unsigned NumElts = Width / LdTy.getSizeInBits();
4424  EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
4425 
4426  unsigned Idx = 1;
4427  SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
4428 
4429  for (unsigned i = Start + 1; i != End; ++i) {
4430  EVT NewLdTy = LdOps[i].getValueType();
4431  if (NewLdTy != LdTy) {
4432  NumElts = Width / NewLdTy.getSizeInBits();
4433  NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
4434  VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
4435  // Readjust position and vector position based on new load type.
4436  Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
4437  LdTy = NewLdTy;
4438  }
4439  VecOp = DAG.getNode(
4440  ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
4441  DAG.getConstant(Idx++, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4442  }
4443  return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
4444 }
4445 
4446 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
4447  LoadSDNode *LD) {
4448  // The strategy assumes that we can efficiently load power-of-two widths.
4449  // The routine chops the vector into the largest vector loads with the same
4450  // element type or scalar loads and then recombines it to the widen vector
4451  // type.
4452  EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
4453  unsigned WidenWidth = WidenVT.getSizeInBits();
4454  EVT LdVT = LD->getMemoryVT();
4455  SDLoc dl(LD);
4456  assert(LdVT.isVector() && WidenVT.isVector());
4457  assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
4458 
4459  // Load information
4460  SDValue Chain = LD->getChain();
4461  SDValue BasePtr = LD->getBasePtr();
4462  unsigned Align = LD->getAlignment();
4463  MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
4464  AAMDNodes AAInfo = LD->getAAInfo();
4465 
4466  int LdWidth = LdVT.getSizeInBits();
4467  int WidthDiff = WidenWidth - LdWidth;
4468  unsigned LdAlign = LD->isVolatile() ? 0 : Align; // Allow wider loads.
4469 
4470  // Find the vector type that can load from.
4471  EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
4472  int NewVTWidth = NewVT.getSizeInBits();
4473  SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
4474  Align, MMOFlags, AAInfo);
4475  LdChain.push_back(LdOp.getValue(1));
4476 
4477  // Check if we can load the element with one instruction.
4478  if (LdWidth <= NewVTWidth) {
4479  if (!NewVT.isVector()) {
4480  unsigned NumElts = WidenWidth / NewVTWidth;
4481  EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
4482  SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
4483  return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
4484  }
4485  if (NewVT == WidenVT)
4486  return LdOp;
4487 
4488  assert(WidenWidth % NewVTWidth == 0);
4489  unsigned NumConcat = WidenWidth / NewVTWidth;
4490  SmallVector<SDValue, 16> ConcatOps(NumConcat);
4491  SDValue UndefVal = DAG.getUNDEF(NewVT);
4492  ConcatOps[0] = LdOp;
4493  for (unsigned i = 1; i != NumConcat; ++i)
4494  ConcatOps[i] = UndefVal;
4495  return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, ConcatOps);
4496  }
4497 
4498  // Load vector by using multiple loads from largest vector to scalar.
4500  LdOps.push_back(LdOp);
4501 
4502  LdWidth -= NewVTWidth;
4503  unsigned Offset = 0;
4504 
4505  while (LdWidth > 0) {
4506  unsigned Increment = NewVTWidth / 8;
4507  Offset += Increment;
4508  BasePtr = DAG.getObjectPtrOffset(dl, BasePtr, Increment);
4509 
4510  SDValue L;
4511  if (LdWidth < NewVTWidth) {
4512  // The current type we are using is too large. Find a better size.
4513  NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
4514  NewVTWidth = NewVT.getSizeInBits();
4515  L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
4516  LD->getPointerInfo().getWithOffset(Offset),
4517  MinAlign(Align, Increment), MMOFlags, AAInfo);
4518  LdChain.push_back(L.getValue(1));
4519  if (L->getValueType(0).isVector() && NewVTWidth >= LdWidth) {
4520  // Later code assumes the vector loads produced will be mergeable, so we
4521  // must pad the final entry up to the previous width. Scalars are
4522  // combined separately.
4524  Loads.push_back(L);
4525  unsigned size = L->getValueSizeInBits(0);
4526  while (size < LdOp->getValueSizeInBits(0)) {
4527  Loads.push_back(DAG.getUNDEF(L->getValueType(0)));
4528  size += L->getValueSizeInBits(0);
4529  }
4530  L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0), Loads);
4531  }
4532  } else {
4533  L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
4534  LD->getPointerInfo().getWithOffset(Offset),
4535  MinAlign(Align, Increment), MMOFlags, AAInfo);
4536  LdChain.push_back(L.getValue(1));
4537  }
4538 
4539  LdOps.push_back(L);
4540  LdOp = L;
4541 
4542  LdWidth -= NewVTWidth;
4543  }
4544 
4545  // Build the vector from the load operations.
4546  unsigned End = LdOps.size();
4547  if (!LdOps[0].getValueType().isVector())
4548  // All the loads are scalar loads.
4549  return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
4550 
4551  // If the load contains vectors, build the vector using concat vector.
4552  // All of the vectors used to load are power-of-2, and the scalar loads can be
4553  // combined to make a power-of-2 vector.
4554  SmallVector<SDValue, 16> ConcatOps(End);
4555  int i = End - 1;
4556  int Idx = End;
4557  EVT LdTy = LdOps[i].getValueType();
4558  // First, combine the scalar loads to a vector.
4559  if (!LdTy.isVector()) {
4560  for (--i; i >= 0; --i) {
4561  LdTy = LdOps[i].getValueType();
4562  if (LdTy.isVector())
4563  break;
4564  }
4565  ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i + 1, End);
4566  }
4567  ConcatOps[--Idx] = LdOps[i];
4568  for (--i; i >= 0; --i) {
4569  EVT NewLdTy = LdOps[i].getValueType();
4570  if (NewLdTy != LdTy) {
4571  // Create a larger vector.
4572  ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
4573  makeArrayRef(&ConcatOps[Idx], End - Idx));
4574  Idx = End - 1;
4575  LdTy = NewLdTy;
4576  }
4577  ConcatOps[--Idx] = LdOps[i];
4578  }
4579 
4580  if (WidenWidth == LdTy.getSizeInBits() * (End - Idx))
4581  return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
4582  makeArrayRef(&ConcatOps[Idx], End - Idx));
4583 
4584  // We need to fill the rest with undefs to build the vector.
4585  unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
4586  SmallVector<SDValue, 16> WidenOps(NumOps);
4587  SDValue UndefVal = DAG.getUNDEF(LdTy);
4588  {
4589  unsigned i = 0;
4590  for (; i != End-Idx; ++i)
4591  WidenOps[i] = ConcatOps[Idx+i];
4592  for (; i != NumOps; ++i)
4593  WidenOps[i] = UndefVal;
4594  }
4595  return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, WidenOps);
4596 }
4597 
4598 SDValue
4599 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
4600  LoadSDNode *LD,
4602  // For extension loads, it may not be more efficient to chop up the vector
4603  // and then extend it. Instead, we unroll the load and build a new vector.
4604  EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
4605  EVT LdVT = LD->getMemoryVT();
4606  SDLoc dl(LD);
4607  assert(LdVT.isVector() && WidenVT.isVector());
4608 
4609  // Load information
4610  SDValue Chain = LD->getChain();
4611  SDValue BasePtr = LD->getBasePtr();
4612  unsigned Align = LD->getAlignment();
4613  MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
4614  AAMDNodes AAInfo = LD->getAAInfo();
4615 
4616  EVT EltVT = WidenVT.getVectorElementType();
4617  EVT LdEltVT = LdVT.getVectorElementType();
4618  unsigned NumElts = LdVT.getVectorNumElements();
4619 
4620  // Load each element and widen.
4621  unsigned WidenNumElts = WidenVT.getVectorNumElements();
4622  SmallVector<SDValue, 16> Ops(WidenNumElts);
4623  unsigned Increment = LdEltVT.getSizeInBits() / 8;
4624  Ops[0] =
4625  DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, LD->getPointerInfo(),
4626  LdEltVT, Align, MMOFlags, AAInfo);
4627  LdChain.push_back(Ops[0].getValue(1));
4628  unsigned i = 0, Offset = Increment;
4629  for (i=1; i < NumElts; ++i, Offset += Increment) {
4630  SDValue NewBasePtr = DAG.getObjectPtrOffset(dl, BasePtr, Offset);
4631  Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
4632  LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
4633  Align, MMOFlags, AAInfo);
4634  LdChain.push_back(Ops[i].getValue(1));
4635  }
4636 
4637  // Fill the rest with undefs.
4638  SDValue UndefVal = DAG.getUNDEF(EltVT);
4639  for (; i != WidenNumElts; ++i)
4640  Ops[i] = UndefVal;
4641 
4642  return DAG.getBuildVector(WidenVT, dl, Ops);
4643 }
4644 
4645 void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
4646  StoreSDNode *ST) {
4647  // The strategy assumes that we can efficiently store power-of-two widths.
4648  // The routine chops the vector into the largest vector stores with the same
4649  // element type or scalar stores.
4650  SDValue Chain = ST->getChain();
4651  SDValue BasePtr = ST->getBasePtr();
4652  unsigned Align = ST->getAlignment();
4653  MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
4654  AAMDNodes AAInfo = ST->getAAInfo();
4655  SDValue ValOp = GetWidenedVector(ST->getValue());
4656  SDLoc dl(ST);
4657 
4658  EVT StVT = ST->getMemoryVT();
4659  unsigned StWidth = StVT.getSizeInBits();
4660  EVT ValVT = ValOp.getValueType();
4661  unsigned ValWidth = ValVT.getSizeInBits();
4662  EVT ValEltVT = ValVT.getVectorElementType();
4663  unsigned ValEltWidth = ValEltVT.getSizeInBits();
4664  assert(StVT.getVectorElementType() == ValEltVT);
4665 
4666  int Idx = 0; // current index to store
4667  unsigned Offset = 0; // offset from base to store
4668  while (StWidth != 0) {
4669  // Find the largest vector type we can store with.
4670  EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
4671  unsigned NewVTWidth = NewVT.getSizeInBits();
4672  unsigned Increment = NewVTWidth / 8;
4673  if (NewVT.isVector()) {
4674  unsigned NumVTElts = NewVT.getVectorNumElements();
4675  do {
4676  SDValue EOp = DAG.getNode(
4677  ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
4678  DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4679  StChain.push_back(DAG.getStore(
4680  Chain, dl, EOp, BasePtr, ST->getPointerInfo().getWithOffset(Offset),
4681  MinAlign(Align, Offset), MMOFlags, AAInfo));
4682  StWidth -= NewVTWidth;
4683  Offset += Increment;
4684  Idx += NumVTElts;
4685 
4686  BasePtr = DAG.getObjectPtrOffset(dl, BasePtr, Increment);
4687  } while (StWidth != 0 && StWidth >= NewVTWidth);
4688  } else {
4689  // Cast the vector to the scalar type we can store.
4690  unsigned NumElts = ValWidth / NewVTWidth;
4691  EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
4692  SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
4693  // Readjust index position based on new vector type.
4694  Idx = Idx * ValEltWidth / NewVTWidth;
4695  do {
4696  SDValue EOp = DAG.getNode(
4697  ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
4698  DAG.getConstant(Idx++, dl,
4699  TLI.getVectorIdxTy(DAG.getDataLayout())));
4700  StChain.push_back(DAG.getStore(
4701  Chain, dl, EOp, BasePtr, ST->getPointerInfo().getWithOffset(Offset),
4702  MinAlign(Align, Offset), MMOFlags, AAInfo));
4703  StWidth -= NewVTWidth;
4704  Offset += Increment;
4705  BasePtr = DAG.getObjectPtrOffset(dl, BasePtr, Increment);
4706  } while (StWidth != 0 && StWidth >= NewVTWidth);
4707  // Restore index back to be relative to the original widen element type.
4708  Idx = Idx * NewVTWidth / ValEltWidth;
4709  }
4710  }
4711 }
4712 
4713 void
4714 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,
4715  StoreSDNode *ST) {
4716  // For extension loads, it may not be more efficient to truncate the vector
4717  // and then store it. Instead, we extract each element and then store it.
4718  SDValue Chain = ST->getChain();
4719  SDValue BasePtr = ST->getBasePtr();
4720  unsigned Align = ST->getAlignment();
4721  MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
4722  AAMDNodes AAInfo = ST->getAAInfo();
4723  SDValue ValOp = GetWidenedVector(ST->getValue());
4724  SDLoc dl(ST);
4725 
4726  EVT StVT = ST->getMemoryVT();
4727  EVT ValVT = ValOp.getValueType();
4728 
4729  // It must be true that the wide vector type is bigger than where we need to
4730  // store.
4731  assert(StVT.isVector() && ValOp.getValueType().isVector());
4732  assert(StVT.bitsLT(ValOp.getValueType()));
4733 
4734  // For truncating stores, we can not play the tricks of chopping legal vector
4735  // types and bitcast it to the right type. Instead, we unroll the store.
4736  EVT StEltVT = StVT.getVectorElementType();
4737  EVT ValEltVT = ValVT.getVectorElementType();
4738  unsigned Increment = ValEltVT.getSizeInBits() / 8;
4739  unsigned NumElts = StVT.getVectorNumElements();
4740  SDValue EOp = DAG.getNode(
4741  ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
4742  DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4743  StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
4744  ST->getPointerInfo(), StEltVT, Align,
4745  MMOFlags, AAInfo));
4746  unsigned Offset = Increment;
4747  for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
4748  SDValue NewBasePtr = DAG.getObjectPtrOffset(dl, BasePtr, Offset);
4749  SDValue EOp = DAG.getNode(
4750  ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
4751  DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4752  StChain.push_back(DAG.getTruncStore(
4753  Chain, dl, EOp, NewBasePtr, ST->getPointerInfo().getWithOffset(Offset),
4754  StEltVT, MinAlign(Align, Offset), MMOFlags, AAInfo));
4755  }
4756 }
4757 
4758 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
4759 /// input vector must have the same element type as NVT.
4760 /// FillWithZeroes specifies that the vector should be widened with zeroes.
4761 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT,
4762  bool FillWithZeroes) {
4763  // Note that InOp might have been widened so it might already have
4764  // the right width or it might need be narrowed.
4765  EVT InVT = InOp.getValueType();
4767  "input and widen element type must match");
4768  SDLoc dl(InOp);
4769 
4770  // Check if InOp already has the right width.
4771  if (InVT == NVT)
4772  return InOp;
4773 
4774  unsigned InNumElts = InVT.getVectorNumElements();
4775  unsigned WidenNumElts = NVT.getVectorNumElements();
4776  if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
4777  unsigned NumConcat = WidenNumElts / InNumElts;
4778  SmallVector<SDValue, 16> Ops(NumConcat);
4779  SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, InVT) :
4780  DAG.getUNDEF(InVT);
4781  Ops[0] = InOp;
4782  for (unsigned i = 1; i != NumConcat; ++i)
4783  Ops[i] = FillVal;
4784 
4785  return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, Ops);
4786  }
4787 
4788  if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
4789  return DAG.getNode(
4790  ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
4791  DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4792 
4793  // Fall back to extract and build.
4794  SmallVector<SDValue, 16> Ops(WidenNumElts);
4795  EVT EltVT = NVT.getVectorElementType();
4796  unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
4797  unsigned Idx;
4798  for (Idx = 0; Idx < MinNumElts; ++Idx)
4799  Ops[Idx] = DAG.getNode(
4800  ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
4801  DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4802 
4803  SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, EltVT) :
4804  DAG.getUNDEF(EltVT);
4805  for ( ; Idx < WidenNumElts; ++Idx)
4806  Ops[Idx] = FillVal;
4807  return DAG.getBuildVector(NVT, dl, Ops);
4808 }
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:570
X = FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:537
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:595
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
EVT getValueType() const
Return the ValueType of the referenced return value.
bool isUndef() const
Constrained versions of libm-equivalent floating point intrinsics.
Definition: ISDOpcodes.h:295
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
Definition: ValueTypes.h:358
bool isBuildVectorOfConstantSDNodes(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR node of all ConstantSDNode or undef...
SDValue UnrollVectorOp(SDNode *N, unsigned ResNE=0)
Utility function used by legalize and lowering to "unroll" a vector operation by splitting out the sc...
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an vector value) starting with the ...
Definition: ISDOpcodes.h:357
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
static SDValue CollectOpsToWiden(SelectionDAG &DAG, const TargetLowering &TLI, SmallVectorImpl< SDValue > &ConcatOps, unsigned ConcatEnd, EVT VT, EVT MaxVT, EVT WidenVT)