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R600InstrInfo.h
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1 //===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Interface definition for R600InstrInfo
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H
16 #define LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H
17 
18 #include "AMDGPUInstrInfo.h"
19 #include "R600RegisterInfo.h"
20 
21 namespace llvm {
22 
23 namespace R600InstrFlags {
24 enum : uint64_t {
25  REGISTER_STORE = UINT64_C(1) << 62,
26  REGISTER_LOAD = UINT64_C(1) << 63
27 };
28 }
29 
31 class DFAPacketizer;
32 class MachineFunction;
33 class MachineInstr;
35 class R600Subtarget;
36 
37 class R600InstrInfo final : public AMDGPUInstrInfo {
38 private:
39  const R600RegisterInfo RI;
40  const R600Subtarget &ST;
41 
42  std::vector<std::pair<int, unsigned>>
43  ExtractSrcs(MachineInstr &MI, const DenseMap<unsigned, unsigned> &PV,
44  unsigned &ConstCount) const;
45 
46  MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
48  unsigned ValueReg, unsigned Address,
49  unsigned OffsetReg,
50  unsigned AddrChan) const;
51 
52  MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
54  unsigned ValueReg, unsigned Address,
55  unsigned OffsetReg,
56  unsigned AddrChan) const;
57 public:
58  enum BankSwizzle {
59  ALU_VEC_012_SCL_210 = 0,
64  ALU_VEC_210
65  };
66 
67  explicit R600InstrInfo(const R600Subtarget &);
68 
70  return RI;
71  }
72 
73  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
74  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
75  bool KillSrc) const override;
76  bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
77  MachineBasicBlock::iterator MBBI) const override;
78 
79  bool isReductionOp(unsigned opcode) const;
80  bool isCubeOp(unsigned opcode) const;
81 
82  /// \returns true if this \p Opcode represents an ALU instruction.
83  bool isALUInstr(unsigned Opcode) const;
84  bool hasInstrModifiers(unsigned Opcode) const;
85  bool isLDSInstr(unsigned Opcode) const;
86  bool isLDSRetInstr(unsigned Opcode) const;
87 
88  /// \returns true if this \p Opcode represents an ALU instruction or an
89  /// instruction that will be lowered in ExpandSpecialInstrs Pass.
90  bool canBeConsideredALU(const MachineInstr &MI) const;
91 
92  bool isTransOnly(unsigned Opcode) const;
93  bool isTransOnly(const MachineInstr &MI) const;
94  bool isVectorOnly(unsigned Opcode) const;
95  bool isVectorOnly(const MachineInstr &MI) const;
96  bool isExport(unsigned Opcode) const;
97 
98  bool usesVertexCache(unsigned Opcode) const;
99  bool usesVertexCache(const MachineInstr &MI) const;
100  bool usesTextureCache(unsigned Opcode) const;
101  bool usesTextureCache(const MachineInstr &MI) const;
102 
103  bool mustBeLastInClause(unsigned Opcode) const;
104  bool usesAddressRegister(MachineInstr &MI) const;
105  bool definesAddressRegister(MachineInstr &MI) const;
106  bool readsLDSSrcReg(const MachineInstr &MI) const;
107 
108  /// \returns The operand Index for the Sel operand given an index to one
109  /// of the instruction's src operands.
110  int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
111 
112  /// \returns a pair for each src of an ALU instructions.
113  /// The first member of a pair is the register id.
114  /// If register is ALU_CONST, second member is SEL.
115  /// If register is ALU_LITERAL, second member is IMM.
116  /// Otherwise, second member value is undefined.
118  getSrcs(MachineInstr &MI) const;
119 
120  unsigned isLegalUpTo(
121  const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
122  const std::vector<R600InstrInfo::BankSwizzle> &Swz,
123  const std::vector<std::pair<int, unsigned> > &TransSrcs,
124  R600InstrInfo::BankSwizzle TransSwz) const;
125 
126  bool FindSwizzleForVectorSlot(
127  const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
128  std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
129  const std::vector<std::pair<int, unsigned> > &TransSrcs,
130  R600InstrInfo::BankSwizzle TransSwz) const;
131 
132  /// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210
133  /// returns true and the first (in lexical order) BankSwizzle affectation
134  /// starting from the one already provided in the Instruction Group MIs that
135  /// fits Read Port limitations in BS if available. Otherwise returns false
136  /// and undefined content in BS.
137  /// isLastAluTrans should be set if the last Alu of MIs will be executed on
138  /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to
139  /// apply to the last instruction.
140  /// PV holds GPR to PV registers in the Instruction Group MIs.
141  bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
143  std::vector<BankSwizzle> &BS,
144  bool isLastAluTrans) const;
145 
146  /// An instruction group can only access 2 channel pair (either [XY] or [ZW])
147  /// from KCache bank on R700+. This function check if MI set in input meet
148  /// this limitations
149  bool fitsConstReadLimitations(const std::vector<MachineInstr *> &) const;
150  /// Same but using const index set instead of MI set.
151  bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
152 
153  /// \brief Vector instructions are instructions that must fill all
154  /// instruction slots within an instruction group.
155  bool isVector(const MachineInstr &MI) const;
156 
157  bool isMov(unsigned Opcode) const;
158 
159  DFAPacketizer *
160  CreateTargetScheduleState(const TargetSubtargetInfo &) const override;
161 
162  bool reverseBranchCondition(
163  SmallVectorImpl<MachineOperand> &Cond) const override;
164 
165  bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
166  MachineBasicBlock *&FBB,
168  bool AllowModify) const override;
169 
170  unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
172  const DebugLoc &DL,
173  int *BytesAdded = nullptr) const override;
174 
175  unsigned removeBranch(MachineBasicBlock &MBB,
176  int *BytesRemvoed = nullptr) const override;
177 
178  bool isPredicated(const MachineInstr &MI) const override;
179 
180  bool isPredicable(const MachineInstr &MI) const override;
181 
182  bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
183  BranchProbability Probability) const override;
184 
185  bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
186  unsigned ExtraPredCycles,
187  BranchProbability Probability) const override ;
188 
189  bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
190  unsigned NumTCycles, unsigned ExtraTCycles,
191  MachineBasicBlock &FMBB,
192  unsigned NumFCycles, unsigned ExtraFCycles,
193  BranchProbability Probability) const override;
194 
195  bool DefinesPredicate(MachineInstr &MI,
196  std::vector<MachineOperand> &Pred) const override;
197 
198  bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
199  MachineBasicBlock &FMBB) const override;
200 
201  bool PredicateInstruction(MachineInstr &MI,
202  ArrayRef<MachineOperand> Pred) const override;
203 
204  unsigned int getPredicationCost(const MachineInstr &) const override;
205 
206  unsigned int getInstrLatency(const InstrItineraryData *ItinData,
207  const MachineInstr &MI,
208  unsigned *PredCost = nullptr) const override;
209 
210  bool expandPostRAPseudo(MachineInstr &MI) const override;
211 
212  /// \brief Reserve the registers that may be accesed using indirect addressing.
213  void reserveIndirectRegisters(BitVector &Reserved,
214  const MachineFunction &MF,
215  const R600RegisterInfo &TRI) const;
216 
217  /// Calculate the "Indirect Address" for the given \p RegIndex and
218  /// \p Channel
219  ///
220  /// We model indirect addressing using a virtual address space that can be
221  /// accesed with loads and stores. The "Indirect Address" is the memory
222  /// address in this virtual address space that maps to the given \p RegIndex
223  /// and \p Channel.
224  unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const;
225 
226 
227  /// \returns The register class to be used for loading and storing values
228  /// from an "Indirect Address" .
229  const TargetRegisterClass *getIndirectAddrRegClass() const;
230 
231  /// \returns the smallest register index that will be accessed by an indirect
232  /// read or write or -1 if indirect addressing is not used by this program.
233  int getIndirectIndexBegin(const MachineFunction &MF) const;
234 
235  /// \returns the largest register index that will be accessed by an indirect
236  /// read or write or -1 if indirect addressing is not used by this program.
237  int getIndirectIndexEnd(const MachineFunction &MF) const;
238 
239  /// \brief Build instruction(s) for an indirect register write.
240  ///
241  /// \returns The instruction that performs the indirect register write
242  MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
244  unsigned ValueReg, unsigned Address,
245  unsigned OffsetReg) const;
246 
247  /// \brief Build instruction(s) for an indirect register read.
248  ///
249  /// \returns The instruction that performs the indirect register read
250  MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
252  unsigned ValueReg, unsigned Address,
253  unsigned OffsetReg) const;
254 
255  unsigned getMaxAlusPerClause() const;
256 
257  /// buildDefaultInstruction - This function returns a MachineInstr with all
258  /// the instruction modifiers initialized to their default values. You can
259  /// use this function to avoid manually specifying each instruction modifier
260  /// operand when building a new instruction.
261  ///
262  /// \returns a MachineInstr with all the instruction modifiers initialized
263  /// to their default values.
264  MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
266  unsigned Opcode,
267  unsigned DstReg,
268  unsigned Src0Reg,
269  unsigned Src1Reg = 0) const;
270 
271  MachineInstr *buildSlotOfVectorInstruction(MachineBasicBlock &MBB,
272  MachineInstr *MI,
273  unsigned Slot,
274  unsigned DstReg) const;
275 
276  MachineInstr *buildMovImm(MachineBasicBlock &BB,
278  unsigned DstReg,
279  uint64_t Imm) const;
280 
281  MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
283  unsigned DstReg, unsigned SrcReg) const;
284 
285  /// \brief Get the index of Op in the MachineInstr.
286  ///
287  /// \returns -1 if the Instruction does not contain the specified \p Op.
288  int getOperandIdx(const MachineInstr &MI, unsigned Op) const;
289 
290  /// \brief Get the index of \p Op for the given Opcode.
291  ///
292  /// \returns -1 if the Instruction does not contain the specified \p Op.
293  int getOperandIdx(unsigned Opcode, unsigned Op) const;
294 
295  /// \brief Helper function for setting instruction flag values.
296  void setImmOperand(MachineInstr &MI, unsigned Op, int64_t Imm) const;
297 
298  ///\brief Add one of the MO_FLAG* flags to the specified \p Operand.
299  void addFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const;
300 
301  ///\brief Determine if the specified \p Flag is set on this \p Operand.
302  bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
303 
304  /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
305  /// \param Flag The flag being set.
306  ///
307  /// \returns the operand containing the flags for this instruction.
308  MachineOperand &getFlagOp(MachineInstr &MI, unsigned SrcIdx = 0,
309  unsigned Flag = 0) const;
310 
311  /// \brief Clear the specified flag on the instruction.
312  void clearFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const;
313 
314  // Helper functions that check the opcode for status information
315  bool isRegisterStore(const MachineInstr &MI) const {
316  return get(MI.getOpcode()).TSFlags & R600InstrFlags::REGISTER_STORE;
317  }
318 
319  bool isRegisterLoad(const MachineInstr &MI) const {
320  return get(MI.getOpcode()).TSFlags & R600InstrFlags::REGISTER_LOAD;
321  }
322 
323  unsigned getAddressSpaceForPseudoSourceKind(
324  PseudoSourceValue::PSVKind Kind) const override;
325 };
326 
327 namespace AMDGPU {
328 
329 int getLDSNoRetOp(uint16_t Opcode);
330 
331 } //End namespace AMDGPU
332 
333 } // End llvm namespace
334 
335 #endif
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
A debug info location.
Definition: DebugLoc.h:34
Interface definition for R600RegisterInfo.
int getLDSNoRetOp(uint16_t Opcode)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:293
bool isRegisterLoad(const MachineInstr &MI) const
bool isRegisterStore(const MachineInstr &MI) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
Itinerary data supplied by a subtarget to be used by a target.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:121
const R600RegisterInfo & getRegisterInfo() const
Definition: R600InstrInfo.h:69
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:862
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
Contains the definition of a TargetInstrInfo class that is common to all AMD GPUs.
TargetSubtargetInfo - Generic base class for all target subtargets.
Representation of each machine instruction.
Definition: MachineInstr.h:60
#define I(x, y, z)
Definition: MD5.cpp:58
const unsigned Kind
IRTranslator LLVM IR MI