LLVM 19.0.0git
MCSchedule.cpp
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1//===- MCSchedule.cpp - Scheduling ------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the default scheduling model.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/MC/MCSchedule.h"
14#include "llvm/MC/MCInst.h"
15#include "llvm/MC/MCInstrDesc.h"
16#include "llvm/MC/MCInstrInfo.h"
18#include <optional>
19#include <type_traits>
20
21using namespace llvm;
22
23static_assert(std::is_trivial_v<MCSchedModel>,
24 "MCSchedModel is required to be a trivial type");
25const MCSchedModel MCSchedModel::Default = {DefaultIssueWidth,
26 DefaultMicroOpBufferSize,
27 DefaultLoopMicroOpBufferSize,
28 DefaultLoadLatency,
29 DefaultHighLatency,
30 DefaultMispredictPenalty,
31 false,
32 true,
33 /*EnableIntervals=*/false,
34 0,
35 nullptr,
36 nullptr,
37 0,
38 0,
39 nullptr,
40 nullptr};
41
43 const MCSchedClassDesc &SCDesc) {
44 int Latency = 0;
45 for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries;
46 DefIdx != DefEnd; ++DefIdx) {
47 // Lookup the definition's write latency in SubtargetInfo.
48 const MCWriteLatencyEntry *WLEntry =
49 STI.getWriteLatencyEntry(&SCDesc, DefIdx);
50 // Early exit if we found an invalid latency.
51 if (WLEntry->Cycles < 0)
52 return WLEntry->Cycles;
53 Latency = std::max(Latency, static_cast<int>(WLEntry->Cycles));
54 }
55 return Latency;
56}
57
59 unsigned SchedClass) const {
60 const MCSchedClassDesc &SCDesc = *getSchedClassDesc(SchedClass);
61 if (!SCDesc.isValid())
62 return 0;
63 if (!SCDesc.isVariant())
64 return MCSchedModel::computeInstrLatency(STI, SCDesc);
65
66 llvm_unreachable("unsupported variant scheduling class");
67}
68
70 const MCInstrInfo &MCII,
71 const MCInst &Inst) const {
72 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass();
73 const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass);
74 if (!SCDesc->isValid())
75 return 0;
76
77 unsigned CPUID = getProcessorID();
78 while (SCDesc->isVariant()) {
79 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, &MCII, CPUID);
80 SCDesc = getSchedClassDesc(SchedClass);
81 }
82
83 if (SchedClass)
84 return MCSchedModel::computeInstrLatency(STI, *SCDesc);
85
86 llvm_unreachable("unsupported variant scheduling class");
87}
88
89double
91 const MCSchedClassDesc &SCDesc) {
92 std::optional<double> Throughput;
93 const MCSchedModel &SM = STI.getSchedModel();
94 const MCWriteProcResEntry *I = STI.getWriteProcResBegin(&SCDesc);
95 const MCWriteProcResEntry *E = STI.getWriteProcResEnd(&SCDesc);
96 for (; I != E; ++I) {
97 if (!I->ReleaseAtCycle)
98 continue;
99 unsigned NumUnits = SM.getProcResource(I->ProcResourceIdx)->NumUnits;
100 double Temp = NumUnits * 1.0 / I->ReleaseAtCycle;
101 Throughput = Throughput ? std::min(*Throughput, Temp) : Temp;
102 }
103 if (Throughput)
104 return 1.0 / *Throughput;
105
106 // If no throughput value was calculated, assume that we can execute at the
107 // maximum issue width scaled by number of micro-ops for the schedule class.
108 return ((double)SCDesc.NumMicroOps) / SM.IssueWidth;
109}
110
111double
113 const MCInstrInfo &MCII,
114 const MCInst &Inst) const {
115 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass();
116 const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass);
117
118 // If there's no valid class, assume that the instruction executes/completes
119 // at the maximum issue width.
120 if (!SCDesc->isValid())
121 return 1.0 / IssueWidth;
122
123 unsigned CPUID = getProcessorID();
124 while (SCDesc->isVariant()) {
125 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, &MCII, CPUID);
126 SCDesc = getSchedClassDesc(SchedClass);
127 }
128
129 if (SchedClass)
130 return MCSchedModel::getReciprocalThroughput(STI, *SCDesc);
131
132 llvm_unreachable("unsupported variant scheduling class");
133}
134
135double
137 const InstrItineraryData &IID) {
138 std::optional<double> Throughput;
139 const InstrStage *I = IID.beginStage(SchedClass);
140 const InstrStage *E = IID.endStage(SchedClass);
141 for (; I != E; ++I) {
142 if (!I->getCycles())
143 continue;
144 double Temp = llvm::popcount(I->getUnits()) * 1.0 / I->getCycles();
145 Throughput = Throughput ? std::min(*Throughput, Temp) : Temp;
146 }
147 if (Throughput)
148 return 1.0 / *Throughput;
149
150 // If there are no execution resources specified for this class, then assume
151 // that it can execute at the maximum default issue width.
152 return 1.0 / DefaultIssueWidth;
153}
154
155unsigned
157 unsigned WriteResourceID) {
158 if (Entries.empty())
159 return 0;
160
161 int DelayCycles = 0;
162 for (const MCReadAdvanceEntry &E : Entries) {
163 if (E.WriteResourceID != WriteResourceID)
164 continue;
165 DelayCycles = std::min(DelayCycles, E.Cycles);
166 }
167
168 return std::abs(DelayCycles);
169}
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define I(x, y, z)
Definition: MD5.cpp:58
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Itinerary data supplied by a subtarget to be used by a target.
const InstrStage * beginStage(unsigned ItinClassIndx) const
Return the first stage of the itinerary.
const InstrStage * endStage(unsigned ItinClassIndx) const
Return the last+1 stage of the itinerary.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
unsigned getOpcode() const
Definition: MCInst.h:198
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:600
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
Generic base class for all target subtargets.
const MCWriteProcResEntry * getWriteProcResEnd(const MCSchedClassDesc *SC) const
virtual unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const
Resolve a variant scheduling class for the given MCInst and CPU.
const MCWriteLatencyEntry * getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const
const MCWriteProcResEntry * getWriteProcResBegin(const MCSchedClassDesc *SC) const
Return an iterator at the first process resource consumed by the given scheduling class.
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
int popcount(T Value) noexcept
Count the number of set bits in a value.
Definition: bit.h:385
These values represent a non-pipelined step in the execution of an instruction.
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
Definition: MCSchedule.h:103
Summarize the scheduling resources required for an instruction of a particular scheduling class.
Definition: MCSchedule.h:118
bool isValid() const
Definition: MCSchedule.h:136
bool isVariant() const
Definition: MCSchedule.h:139
uint16_t NumWriteLatencyEntries
Definition: MCSchedule.h:132
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:253
static const MCSchedModel Default
Returns the default initialized model.
Definition: MCSchedule.h:393
static unsigned getForwardingDelayCycles(ArrayRef< MCReadAdvanceEntry > Entries, unsigned WriteResourceIdx=0)
Returns the maximum forwarding delay for register reads dependent on writes of scheduling class Write...
Definition: MCSchedule.cpp:156
const MCSchedClassDesc * getSchedClassDesc(unsigned SchedClassIdx) const
Definition: MCSchedule.h:360
unsigned getProcessorID() const
Definition: MCSchedule.h:331
static int computeInstrLatency(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)
Returns the latency value for the scheduling class.
Definition: MCSchedule.cpp:42
unsigned IssueWidth
Definition: MCSchedule.h:265
const MCProcResourceDesc * getProcResource(unsigned ProcResourceIdx) const
Definition: MCSchedule.h:353
static double getReciprocalThroughput(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)
Definition: MCSchedule.cpp:90
static const unsigned DefaultIssueWidth
Definition: MCSchedule.h:266
Specify the latency in cpu cycles for a particular scheduling class and def index.
Definition: MCSchedule.h:86
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
Definition: MCSchedule.h:63