LLVM  9.0.0svn
MCSchedule.cpp
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1 //===- MCSchedule.cpp - Scheduling ------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the default scheduling model.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/MC/MCSchedule.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCInstrDesc.h"
16 #include "llvm/MC/MCInstrInfo.h"
18 #include <type_traits>
19 
20 using namespace llvm;
21 
22 static_assert(std::is_pod<MCSchedModel>::value,
23  "We shouldn't have a static constructor here");
24 const MCSchedModel MCSchedModel::Default = {DefaultIssueWidth,
25  DefaultMicroOpBufferSize,
26  DefaultLoopMicroOpBufferSize,
27  DefaultLoadLatency,
28  DefaultHighLatency,
29  DefaultMispredictPenalty,
30  false,
31  true,
32  0,
33  nullptr,
34  nullptr,
35  0,
36  0,
37  nullptr,
38  nullptr};
39 
41  const MCSchedClassDesc &SCDesc) {
42  int Latency = 0;
43  for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries;
44  DefIdx != DefEnd; ++DefIdx) {
45  // Lookup the definition's write latency in SubtargetInfo.
46  const MCWriteLatencyEntry *WLEntry =
47  STI.getWriteLatencyEntry(&SCDesc, DefIdx);
48  // Early exit if we found an invalid latency.
49  if (WLEntry->Cycles < 0)
50  return WLEntry->Cycles;
51  Latency = std::max(Latency, static_cast<int>(WLEntry->Cycles));
52  }
53  return Latency;
54 }
55 
57  unsigned SchedClass) const {
58  const MCSchedClassDesc &SCDesc = *getSchedClassDesc(SchedClass);
59  if (!SCDesc.isValid())
60  return 0;
61  if (!SCDesc.isVariant())
62  return MCSchedModel::computeInstrLatency(STI, SCDesc);
63 
64  llvm_unreachable("unsupported variant scheduling class");
65 }
66 
68  const MCInstrInfo &MCII,
69  const MCInst &Inst) const {
70  unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass();
71  const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass);
72  if (!SCDesc->isValid())
73  return 0;
74 
75  unsigned CPUID = getProcessorID();
76  while (SCDesc->isVariant()) {
77  SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, CPUID);
78  SCDesc = getSchedClassDesc(SchedClass);
79  }
80 
81  if (SchedClass)
82  return MCSchedModel::computeInstrLatency(STI, *SCDesc);
83 
84  llvm_unreachable("unsupported variant scheduling class");
85 }
86 
87 double
89  const MCSchedClassDesc &SCDesc) {
90  Optional<double> Throughput;
91  const MCSchedModel &SM = STI.getSchedModel();
92  const MCWriteProcResEntry *I = STI.getWriteProcResBegin(&SCDesc);
93  const MCWriteProcResEntry *E = STI.getWriteProcResEnd(&SCDesc);
94  for (; I != E; ++I) {
95  if (!I->Cycles)
96  continue;
97  unsigned NumUnits = SM.getProcResource(I->ProcResourceIdx)->NumUnits;
98  double Temp = NumUnits * 1.0 / I->Cycles;
99  Throughput = Throughput ? std::min(Throughput.getValue(), Temp) : Temp;
100  }
101  if (Throughput.hasValue())
102  return 1.0 / Throughput.getValue();
103 
104  // If no throughput value was calculated, assume that we can execute at the
105  // maximum issue width scaled by number of micro-ops for the schedule class.
106  return ((double)SCDesc.NumMicroOps) / SM.IssueWidth;
107 }
108 
109 double
111  const MCInstrInfo &MCII,
112  const MCInst &Inst) const {
113  unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass();
114  const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass);
115 
116  // If there's no valid class, assume that the instruction executes/completes
117  // at the maximum issue width.
118  if (!SCDesc->isValid())
119  return 1.0 / IssueWidth;
120 
121  unsigned CPUID = getProcessorID();
122  while (SCDesc->isVariant()) {
123  SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, CPUID);
124  SCDesc = getSchedClassDesc(SchedClass);
125  }
126 
127  if (SchedClass)
128  return MCSchedModel::getReciprocalThroughput(STI, *SCDesc);
129 
130  llvm_unreachable("unsupported variant scheduling class");
131 }
132 
133 double
135  const InstrItineraryData &IID) {
136  Optional<double> Throughput;
137  const InstrStage *I = IID.beginStage(SchedClass);
138  const InstrStage *E = IID.endStage(SchedClass);
139  for (; I != E; ++I) {
140  if (!I->getCycles())
141  continue;
142  double Temp = countPopulation(I->getUnits()) * 1.0 / I->getCycles();
143  Throughput = Throughput ? std::min(Throughput.getValue(), Temp) : Temp;
144  }
145  if (Throughput.hasValue())
146  return 1.0 / Throughput.getValue();
147 
148  // If there are no execution resources specified for this class, then assume
149  // that it can execute at the maximum default issue width.
150  return 1.0 / DefaultIssueWidth;
151 }
152 
153 unsigned
155  unsigned WriteResourceID) {
156  if (Entries.empty())
157  return 0;
158 
159  int DelayCycles = 0;
160  for (const MCReadAdvanceEntry &E : Entries) {
161  if (E.WriteResourceID != WriteResourceID)
162  continue;
163  DelayCycles = std::min(DelayCycles, E.Cycles);
164  }
165 
166  return std::abs(DelayCycles);
167 }
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
This class represents lattice values for constants.
Definition: AllocatorList.h:23
const InstrStage * beginStage(unsigned ItinClassIndx) const
Return the first stage of the itinerary.
unsigned IssueWidth
Definition: MCSchedule.h:256
unsigned getUnits() const
Returns the choice of FUs.
const MCProcResourceDesc * getProcResource(unsigned ProcResourceIdx) const
Definition: MCSchedule.h:339
unsigned getProcessorID() const
Definition: MCSchedule.h:317
const MCSchedClassDesc * getSchedClassDesc(unsigned SchedClassIdx) const
Definition: MCSchedule.h:346
const MCWriteLatencyEntry * getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const
const MCWriteProcResEntry * getWriteProcResEnd(const MCSchedClassDesc *SC) const
const T & getValue() const LLVM_LVALUE_FUNCTION
Definition: Optional.h:255
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
Itinerary data supplied by a subtarget to be used by a target.
bool isValid() const
Definition: MCSchedule.h:127
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
Definition: MCSchedule.h:64
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Summarize the scheduling resources required for an instruction of a particular scheduling class...
Definition: MCSchedule.h:110
static unsigned getForwardingDelayCycles(ArrayRef< MCReadAdvanceEntry > Entries, unsigned WriteResourceIdx=0)
Returns the maximum forwarding delay for register reads dependent on writes of scheduling class Write...
Definition: MCSchedule.cpp:154
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static const unsigned DefaultIssueWidth
Definition: MCSchedule.h:257
unsigned countPopulation(T Value)
Count the number of set bits in a value.
Definition: MathExtras.h:519
Specify the latency in cpu cycles for a particular scheduling class and def index.
Definition: MCSchedule.h:78
static const MCSchedModel Default
Definition: MCSchedule.h:380
unsigned getCycles() const
Returns the number of cycles the stage is occupied.
bool isVariant() const
Definition: MCSchedule.h:130
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
Definition: MCSchedule.h:95
static double getReciprocalThroughput(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)
Definition: MCSchedule.cpp:88
bool hasValue() const
Definition: Optional.h:259
static int computeInstrLatency(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)
Returns the latency value for the scheduling class.
Definition: MCSchedule.cpp:40
These values represent a non-pipelined step in the execution of an instruction.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
const InstrStage * endStage(unsigned ItinClassIndx) const
Return the last+1 stage of the itinerary.
#define I(x, y, z)
Definition: MD5.cpp:58
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1212
Generic base class for all target subtargets.
virtual unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const
Resolve a variant scheduling class for the given MCInst and CPU.
const MCWriteProcResEntry * getWriteProcResBegin(const MCSchedClassDesc *SC) const
Return an iterator at the first process resource consumed by the given scheduling class...
uint16_t NumWriteLatencyEntries
Definition: MCSchedule.h:123
unsigned getOpcode() const
Definition: MCInst.h:171
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:244
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget&#39;s CPU.
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:143