LLVM  6.0.0svn
llvm::R600InstrInfo Member List

This is the complete list of members for llvm::R600InstrInfo, including all inherited members.

addFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) constllvm::R600InstrInfo
ALU_VEC_012_SCL_210 enum valuellvm::R600InstrInfo
ALU_VEC_021_SCL_122 enum valuellvm::R600InstrInfo
ALU_VEC_102_SCL_221 enum valuellvm::R600InstrInfo
ALU_VEC_120_SCL_212 enum valuellvm::R600InstrInfo
ALU_VEC_201 enum valuellvm::R600InstrInfo
ALU_VEC_210 enum valuellvm::R600InstrInfo
AMDGPUASIllvm::AMDGPUInstrInfoprotected
AMDGPUInstrInfo(const AMDGPUSubtarget &st)llvm::AMDGPUInstrInfoexplicit
analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const overridellvm::R600InstrInfo
BankSwizzle enum namellvm::R600InstrInfo
buildDefaultInstruction(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Opcode, unsigned DstReg, unsigned Src0Reg, unsigned Src1Reg=0) constllvm::R600InstrInfo
buildIndirectRead(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) constllvm::R600InstrInfo
buildIndirectWrite(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) constllvm::R600InstrInfo
buildMovImm(MachineBasicBlock &BB, MachineBasicBlock::iterator I, unsigned DstReg, uint64_t Imm) constllvm::R600InstrInfo
buildMovInstr(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) constllvm::R600InstrInfo
buildSlotOfVectorInstruction(MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg) constllvm::R600InstrInfo
calculateIndirectAddress(unsigned RegIndex, unsigned Channel) constllvm::R600InstrInfo
canBeConsideredALU(const MachineInstr &MI) constllvm::R600InstrInfo
clearFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) constllvm::R600InstrInfo
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const overridellvm::R600InstrInfo
CreateTargetScheduleState(const TargetSubtargetInfo &) const overridellvm::R600InstrInfo
definesAddressRegister(MachineInstr &MI) constllvm::R600InstrInfo
DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const overridellvm::R600InstrInfo
expandPostRAPseudo(MachineInstr &MI) const overridellvm::R600InstrInfo
FindSwizzleForVectorSlot(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, std::vector< R600InstrInfo::BankSwizzle > &SwzCandidate, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) constllvm::R600InstrInfo
fitsConstReadLimitations(const std::vector< MachineInstr *> &) constllvm::R600InstrInfo
fitsConstReadLimitations(const std::vector< unsigned > &) constllvm::R600InstrInfo
fitsReadPortLimitations(const std::vector< MachineInstr *> &MIs, const DenseMap< unsigned, unsigned > &PV, std::vector< BankSwizzle > &BS, bool isLastAluTrans) constllvm::R600InstrInfo
getAddressSpaceForPseudoSourceKind(PseudoSourceValue::PSVKind Kind) const overridellvm::R600InstrInfo
getFlagOp(MachineInstr &MI, unsigned SrcIdx=0, unsigned Flag=0) constllvm::R600InstrInfo
getIndirectAddrRegClass() constllvm::R600InstrInfo
getIndirectIndexBegin(const MachineFunction &MF) constllvm::R600InstrInfo
getIndirectIndexEnd(const MachineFunction &MF) constllvm::R600InstrInfo
getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const overridellvm::R600InstrInfo
getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) constllvm::AMDGPUInstrInfo
getMaxAlusPerClause() constllvm::R600InstrInfo
getOperandIdx(const MachineInstr &MI, unsigned Op) constllvm::R600InstrInfo
getOperandIdx(unsigned Opcode, unsigned Op) constllvm::R600InstrInfo
getPredicationCost(const MachineInstr &) const overridellvm::R600InstrInfo
getRegisterInfo() constllvm::R600InstrInfoinline
getSelIdx(unsigned Opcode, unsigned SrcIdx) constllvm::R600InstrInfo
getSrcs(MachineInstr &MI) constllvm::R600InstrInfo
hasInstrModifiers(unsigned Opcode) constllvm::R600InstrInfo
insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const overridellvm::R600InstrInfo
isALUInstr(unsigned Opcode) constllvm::R600InstrInfo
isCubeOp(unsigned opcode) constllvm::R600InstrInfo
isExport(unsigned Opcode) constllvm::R600InstrInfo
isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) constllvm::R600InstrInfo
isLDSInstr(unsigned Opcode) constllvm::R600InstrInfo
isLDSRetInstr(unsigned Opcode) constllvm::R600InstrInfo
isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const overridellvm::R600InstrInfo
isLegalUpTo(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, const std::vector< R600InstrInfo::BankSwizzle > &Swz, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) constllvm::R600InstrInfo
isMov(unsigned Opcode) constllvm::R600InstrInfo
isPredicable(const MachineInstr &MI) const overridellvm::R600InstrInfo
isPredicated(const MachineInstr &MI) const overridellvm::R600InstrInfo
isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const overridellvm::R600InstrInfo
isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const overridellvm::R600InstrInfo
isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability) const overridellvm::R600InstrInfo
isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const overridellvm::R600InstrInfo
isReductionOp(unsigned opcode) constllvm::R600InstrInfo
isRegisterLoad(const MachineInstr &MI) constllvm::R600InstrInfoinline
isRegisterStore(const MachineInstr &MI) constllvm::R600InstrInfoinline
isTransOnly(unsigned Opcode) constllvm::R600InstrInfo
isTransOnly(const MachineInstr &MI) constllvm::R600InstrInfo
isVector(const MachineInstr &MI) constllvm::R600InstrInfo
isVectorOnly(unsigned Opcode) constllvm::R600InstrInfo
isVectorOnly(const MachineInstr &MI) constllvm::R600InstrInfo
mustBeLastInClause(unsigned Opcode) constllvm::R600InstrInfo
PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const overridellvm::R600InstrInfo
pseudoToMCOpcode(int Opcode) constllvm::AMDGPUInstrInfo
R600InstrInfo(const R600Subtarget &)llvm::R600InstrInfoexplicit
readsLDSSrcReg(const MachineInstr &MI) constllvm::R600InstrInfo
removeBranch(MachineBasicBlock &MBB, int *BytesRemvoed=nullptr) const overridellvm::R600InstrInfo
reserveIndirectRegisters(BitVector &Reserved, const MachineFunction &MF) constllvm::R600InstrInfo
reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const overridellvm::R600InstrInfo
setImmOperand(MachineInstr &MI, unsigned Op, int64_t Imm) constllvm::R600InstrInfo
shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const overridellvm::AMDGPUInstrInfo
usesAddressRegister(MachineInstr &MI) constllvm::R600InstrInfo
usesTextureCache(unsigned Opcode) constllvm::R600InstrInfo
usesTextureCache(const MachineInstr &MI) constllvm::R600InstrInfo
usesVertexCache(unsigned Opcode) constllvm::R600InstrInfo
usesVertexCache(const MachineInstr &MI) constllvm::R600InstrInfo