LLVM  6.0.0svn
llvm::SIInstrInfo Member List

This is the complete list of members for llvm::SIInstrInfo, including all inherited members.

AMDGPUASIllvm::AMDGPUInstrInfoprotected
AMDGPUInstrInfo(const AMDGPUSubtarget &st)llvm::AMDGPUInstrInfoexplicit
analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const overridellvm::SIInstrInfo
analyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) constllvm::SIInstrInfo
areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const overridellvm::SIInstrInfo
areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const overridellvm::SIInstrInfo
buildExtractSubReg(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) constllvm::SIInstrInfo
buildExtractSubRegOrImm(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) constllvm::SIInstrInfo
calculateLDSSpillAddress(MachineBasicBlock &MBB, MachineInstr &MI, RegScavenger *RS, unsigned TmpReg, unsigned Offset, unsigned Size) constllvm::SIInstrInfo
canInsertSelect(const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const overridellvm::SIInstrInfo
canReadVGPR(const MachineInstr &MI, unsigned OpNo) constllvm::SIInstrInfo
commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx0, unsigned OpIdx1) const overridellvm::SIInstrInfoprotected
commuteOpcode(unsigned Opc) constllvm::SIInstrInfo
commuteOpcode(const MachineInstr &MI) constllvm::SIInstrInfoinline
convertNonUniformIfRegion(MachineBasicBlock *IfEntry, MachineBasicBlock *IfEnd) constllvm::SIInstrInfo
convertNonUniformLoopRegion(MachineBasicBlock *LoopEntry, MachineBasicBlock *LoopEnd) constllvm::SIInstrInfo
convertToThreeAddress(MachineFunction::iterator &MBB, MachineInstr &MI, LiveVariables *LV) const overridellvm::SIInstrInfo
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const overridellvm::SIInstrInfo
CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const overridellvm::SIInstrInfo
CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const overridellvm::SIInstrInfo
decomposeMachineOperandsTargetFlags(unsigned TF) const overridellvm::SIInstrInfo
expandPostRAPseudo(MachineInstr &MI) const overridellvm::SIInstrInfo
findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const overridellvm::SIInstrInfo
FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const finalllvm::SIInstrInfo
getAddNoCarry(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg) constllvm::SIInstrInfo
getAddressSpaceForPseudoSourceKind(PseudoSourceValue::PSVKind Kind) const overridellvm::SIInstrInfo
getBranchDestBlock(const MachineInstr &MI) const overridellvm::SIInstrInfo
getClampMask(const MachineInstr &MI) constllvm::SIInstrInfoinline
getDefaultRsrcDataFormat() constllvm::SIInstrInfo
getInstBundleSize(const MachineInstr &MI) constllvm::SIInstrInfo
getInstSizeInBytes(const MachineInstr &MI) const overridellvm::SIInstrInfo
getKillTerminatorFromPseudo(unsigned Opcode) constllvm::SIInstrInfo
getMachineCSELookAheadLimit() const overridellvm::SIInstrInfoinline
getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) constllvm::AMDGPUInstrInfo
getMCOpcodeFromPseudo(unsigned Opcode) constllvm::SIInstrInfoinline
getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const finalllvm::SIInstrInfo
getMovOpcode(const TargetRegisterClass *DstRC) constllvm::SIInstrInfo
getNamedImmOperand(const MachineInstr &MI, unsigned OpName) constllvm::SIInstrInfoinline
getNamedOperand(MachineInstr &MI, unsigned OperandName) constllvm::SIInstrInfo
getNamedOperand(const MachineInstr &MI, unsigned OpName) constllvm::SIInstrInfoinline
getNumWaitStates(const MachineInstr &MI) constllvm::SIInstrInfo
getOpRegClass(const MachineInstr &MI, unsigned OpNo) constllvm::SIInstrInfo
getOpSize(uint16_t Opcode, unsigned OpNo) constllvm::SIInstrInfoinline
getOpSize(const MachineInstr &MI, unsigned OpNo) constllvm::SIInstrInfoinline
getPreferredSelectRegClass(unsigned Size) constllvm::SIInstrInfo
getRegisterInfo() constllvm::SIInstrInfoinline
getScratchRsrcWords23() constllvm::SIInstrInfo
getSerializableDirectMachineOperandTargetFlags() const overridellvm::SIInstrInfo
getSerializableTargetIndices() const overridellvm::SIInstrInfo
getVALUOp(const MachineInstr &MI)llvm::SIInstrInfostatic
hasAnyModifiersSet(const MachineInstr &MI) constllvm::SIInstrInfo
hasFPClamp(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
hasFPClamp(uint16_t Opcode) constllvm::SIInstrInfoinline
hasIntClamp(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
hasModifiers(unsigned Opcode) constllvm::SIInstrInfo
hasModifiersSet(const MachineInstr &MI, unsigned OpName) constllvm::SIInstrInfo
hasVALU32BitEncoding(unsigned Opcode) constllvm::SIInstrInfo
insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const overridellvm::SIInstrInfo
insertEQ(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned SrcReg, int Value) constllvm::SIInstrInfo
insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS=nullptr) const overridellvm::SIInstrInfo
insertNE(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned SrcReg, int Value) constllvm::SIInstrInfo
insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const overridellvm::SIInstrInfo
insertReturn(MachineBasicBlock &MBB) constllvm::SIInstrInfo
insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const overridellvm::SIInstrInfo
insertVectorSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) constllvm::SIInstrInfo
insertWaitStates(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, int Count) constllvm::SIInstrInfo
isBasicBlockPrologue(const MachineInstr &MI) const overridellvm::SIInstrInfo
isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const overridellvm::SIInstrInfo
isBufferSMRD(const MachineInstr &MI) constllvm::SIInstrInfoinline
isDisableWQM(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isDisableWQM(uint16_t Opcode) constllvm::SIInstrInfoinline
isDPP(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isDPP(uint16_t Opcode) constllvm::SIInstrInfoinline
isDS(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isDS(uint16_t Opcode) constllvm::SIInstrInfoinline
isEXP(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isEXP(uint16_t Opcode) constllvm::SIInstrInfoinline
isFixedSize(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isFixedSize(uint16_t Opcode) constllvm::SIInstrInfoinline
isFLAT(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isFLAT(uint16_t Opcode) constllvm::SIInstrInfoinline
isFoldableCopy(const MachineInstr &MI) constllvm::SIInstrInfo
isGather4(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isGather4(uint16_t Opcode) constllvm::SIInstrInfoinline
isHighLatencyInstruction(const MachineInstr &MI) constllvm::SIInstrInfo
isImmOperandLegal(const MachineInstr &MI, unsigned OpNo, const MachineOperand &MO) constllvm::SIInstrInfo
isInlineConstant(const APInt &Imm) constllvm::SIInstrInfo
isInlineConstant(const MachineOperand &MO, uint8_t OperandType) constllvm::SIInstrInfo
isInlineConstant(const MachineOperand &MO, const MCOperandInfo &OpInfo) constllvm::SIInstrInfoinline
isInlineConstant(const MachineInstr &MI, const MachineOperand &UseMO, const MachineOperand &DefMO) constllvm::SIInstrInfoinline
isInlineConstant(const MachineInstr &MI, unsigned OpIdx) constllvm::SIInstrInfoinline
isInlineConstant(const MachineInstr &MI, unsigned OpIdx, const MachineOperand &MO) constllvm::SIInstrInfoinline
isInlineConstant(const MachineOperand &MO) constllvm::SIInstrInfoinline
isKillTerminator(unsigned Opcode)llvm::SIInstrInfostatic
isLegalMUBUFImmOffset(unsigned Imm)llvm::SIInstrInfoinlinestatic
isLegalRegOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) constllvm::SIInstrInfo
isLegalVSrcOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) constllvm::SIInstrInfo
isLiteralConstant(const MachineOperand &MO, const MCOperandInfo &OpInfo) constllvm::SIInstrInfoinline
isLiteralConstant(const MachineInstr &MI, int OpIdx) constllvm::SIInstrInfoinline
isLiteralConstantLike(const MachineOperand &MO, const MCOperandInfo &OpInfo) constllvm::SIInstrInfo
isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const overridellvm::SIInstrInfo
isLowLatencyInstruction(const MachineInstr &MI) constllvm::SIInstrInfo
isMIMG(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isMIMG(uint16_t Opcode) constllvm::SIInstrInfoinline
isMTBUF(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isMTBUF(uint16_t Opcode) constllvm::SIInstrInfoinline
isMUBUF(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isMUBUF(uint16_t Opcode) constllvm::SIInstrInfoinline
isNonUniformBranchInstr(MachineInstr &Instr) constllvm::SIInstrInfo
isOperandLegal(const MachineInstr &MI, unsigned OpIdx, const MachineOperand *MO=nullptr) constllvm::SIInstrInfo
isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const overridellvm::SIInstrInfo
isSALU(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isSALU(uint16_t Opcode) constllvm::SIInstrInfoinline
isSALUOpSupportedOnVALU(const MachineInstr &MI) constllvm::SIInstrInfo
isScalarStore(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isScalarStore(uint16_t Opcode) constllvm::SIInstrInfoinline
isScalarUnit(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const overridellvm::SIInstrInfo
isSDWA(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isSDWA(uint16_t Opcode) constllvm::SIInstrInfoinline
isSegmentSpecificFLAT(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isSGPRSpill(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isSGPRSpill(uint16_t Opcode) constllvm::SIInstrInfoinline
isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) constllvm::SIInstrInfo
isSMRD(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isSMRD(uint16_t Opcode) constllvm::SIInstrInfoinline
isSOP1(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isSOP1(uint16_t Opcode) constllvm::SIInstrInfoinline
isSOP2(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isSOP2(uint16_t Opcode) constllvm::SIInstrInfoinline
isSOPC(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isSOPC(uint16_t Opcode) constllvm::SIInstrInfoinline
isSOPK(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isSOPK(uint16_t Opcode) constllvm::SIInstrInfoinline
isSOPP(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isSOPP(uint16_t Opcode) constllvm::SIInstrInfoinline
isStackAccess(const MachineInstr &MI, int &FrameIndex) constllvm::SIInstrInfo
isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const overridellvm::SIInstrInfo
isVALU(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isVALU(uint16_t Opcode) constllvm::SIInstrInfoinline
isVGPRCopy(const MachineInstr &MI) constllvm::SIInstrInfoinline
isVGPRSpill(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isVGPRSpill(uint16_t Opcode) constllvm::SIInstrInfoinline
isVINTRP(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isVINTRP(uint16_t Opcode) constllvm::SIInstrInfoinline
isVMEM(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isVMEM(uint16_t Opcode) constllvm::SIInstrInfoinline
isVOP1(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isVOP1(uint16_t Opcode) constllvm::SIInstrInfoinline
isVOP2(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isVOP2(uint16_t Opcode) constllvm::SIInstrInfoinline
isVOP3(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isVOP3(uint16_t Opcode) constllvm::SIInstrInfoinline
isVOP3P(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isVOP3P(uint16_t Opcode) constllvm::SIInstrInfoinline
isVOPC(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isVOPC(uint16_t Opcode) constllvm::SIInstrInfoinline
isWQM(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
isWQM(uint16_t Opcode) constllvm::SIInstrInfoinline
legalizeGenericOperand(MachineBasicBlock &InsertMBB, MachineBasicBlock::iterator I, const TargetRegisterClass *DstRC, MachineOperand &Op, MachineRegisterInfo &MRI, const DebugLoc &DL) constllvm::SIInstrInfo
legalizeOperands(MachineInstr &MI) constllvm::SIInstrInfo
legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) constllvm::SIInstrInfo
legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) constllvm::SIInstrInfo
legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) constllvm::SIInstrInfo
legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) constllvm::SIInstrInfo
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const overridellvm::SIInstrInfo
materializeImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, int64_t Value) constllvm::SIInstrInfo
mayAccessFlatAddressSpace(const MachineInstr &MI) constllvm::SIInstrInfo
MO_GOTPCREL enum valuellvm::SIInstrInfo
MO_GOTPCREL32 enum valuellvm::SIInstrInfo
MO_GOTPCREL32_HI enum valuellvm::SIInstrInfo
MO_GOTPCREL32_LO enum valuellvm::SIInstrInfo
MO_MASK enum valuellvm::SIInstrInfo
MO_NONE enum valuellvm::SIInstrInfo
MO_REL32 enum valuellvm::SIInstrInfo
MO_REL32_HI enum valuellvm::SIInstrInfo
MO_REL32_LO enum valuellvm::SIInstrInfo
moveToVALU(MachineInstr &MI) constllvm::SIInstrInfo
pseudoToMCOpcode(int Opcode) constllvm::AMDGPUInstrInfo
readlaneVGPRToSGPR(unsigned SrcReg, MachineInstr &UseMI, MachineRegisterInfo &MRI) constllvm::SIInstrInfo
removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const overridellvm::SIInstrInfo
reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const overridellvm::SIInstrInfo
shouldClusterMemOps(MachineInstr &FirstLdSt, unsigned BaseReg1, MachineInstr &SecondLdSt, unsigned BaseReg2, unsigned NumLoads) const finalllvm::SIInstrInfo
shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const overridellvm::AMDGPUInstrInfo
SIInstrInfo(const SISubtarget &ST)llvm::SIInstrInfoexplicit
sopkIsZext(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
sopkIsZext(uint16_t Opcode) constllvm::SIInstrInfoinline
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const overridellvm::SIInstrInfo
swapSourceModifiers(MachineInstr &MI, MachineOperand &Src0, unsigned Src0OpName, MachineOperand &Src1, unsigned Src1OpName) constllvm::SIInstrInfoprotected
TargetOperandFlags enum namellvm::SIInstrInfo
usesConstantBus(const MachineRegisterInfo &MRI, const MachineOperand &MO, const MCOperandInfo &OpInfo) constllvm::SIInstrInfo
usesLGKM_CNT(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
usesVM_CNT(const MachineInstr &MI)llvm::SIInstrInfoinlinestatic
verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const overridellvm::SIInstrInfo