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DAG combiner asserts due to extend in-register size mismatch for shufflevector #33090

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dstutt opened this issue Jul 11, 2017 · 2 comments
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DAG combiner asserts due to extend in-register size mismatch for shufflevector #33090

dstutt opened this issue Jul 11, 2017 · 2 comments
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bugzilla Issues migrated from bugzilla llvm:codegen

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@dstutt
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dstutt commented Jul 11, 2017

Bugzilla Link 33743
Resolution FIXED
Resolved on Nov 18, 2017 15:59
Version trunk
OS All
Attachments Reproducer for shufflevec issue in DAGCombine
CC @RKSimon,@arsenm
Fixed by commit(s) 315307

Extended Description

This issue has been seen when compiling for the AMDGPU backend

llc -march=amdgcn shufflevec-dagcombine-issue.ll

This results in the following assert:

Assertion failed: VT.getSizeInBits() == Op.getValueSizeInBits() && "The sizes of the input and result must match in order to perform the " "extend in-register.", file ~\llvm\lib\CodeGen\SelectionDAG\SelectionDAG.cpp, line 1012

This looks like an issue in combineShuffleToVectorExtend
@dstutt
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dstutt commented Jul 11, 2017

I've got a potential fix for this issue

See https://reviews.llvm.org/D35241

@RKSimon
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RKSimon commented Nov 18, 2017

rL315307

@llvmbot llvmbot transferred this issue from llvm/llvm-bugzilla-archive Dec 10, 2021
This issue was closed.
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@RKSimon @dstutt