LLVM 20.0.0git
ARMBaseInfo.cpp
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1//===-- ARMBaseInfo.cpp - ARM Base encoding information------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides basic encoding and assembly information for ARM.
10//
11//===----------------------------------------------------------------------===//
12#include "ARMBaseInfo.h"
13
14using namespace llvm;
15namespace llvm {
17 ARMVCC::VPTCodes Kind) {
18 using PredBlockMask = ARM::PredBlockMask;
19 assert(Kind != ARMVCC::None && "Cannot expand a mask with None!");
20 assert(llvm::countr_zero((unsigned)BlockMask) != 0 && "Mask is already full");
21
22 auto ChooseMask = [&](PredBlockMask AddedThen, PredBlockMask AddedElse) {
23 return Kind == ARMVCC::Then ? AddedThen : AddedElse;
24 };
25
26 switch (BlockMask) {
27 case PredBlockMask::T:
28 return ChooseMask(PredBlockMask::TT, PredBlockMask::TE);
29 case PredBlockMask::TT:
30 return ChooseMask(PredBlockMask::TTT, PredBlockMask::TTE);
31 case PredBlockMask::TE:
32 return ChooseMask(PredBlockMask::TET, PredBlockMask::TEE);
33 case PredBlockMask::TTT:
34 return ChooseMask(PredBlockMask::TTTT, PredBlockMask::TTTE);
35 case PredBlockMask::TTE:
36 return ChooseMask(PredBlockMask::TTET, PredBlockMask::TTEE);
37 case PredBlockMask::TET:
38 return ChooseMask(PredBlockMask::TETT, PredBlockMask::TETE);
39 case PredBlockMask::TEE:
40 return ChooseMask(PredBlockMask::TEET, PredBlockMask::TEEE);
41 default:
42 llvm_unreachable("Unknown Mask");
43 }
44}
45
46namespace ARMSysReg {
47
48// lookup system register using 12-bit SYSm value.
49// Note: the search is uniqued using M1 mask
51 return lookupMClassSysRegByM1Encoding12(SYSm);
52}
53
54// returns APSR with _<bits> qualifier.
55// Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier
57 return lookupMClassSysRegByM2M3Encoding8((1<<9)|(SYSm & 0xFF));
58}
59
60// lookup system registers using 8-bit SYSm value
62 return ARMSysReg::lookupMClassSysRegByM2M3Encoding8((1<<8)|(SYSm & 0xFF));
63}
64
65#define GET_MCLASSSYSREG_IMPL
66#include "ARMGenSystemRegister.inc"
67
68} // end namespace ARMSysReg
69
70namespace ARMBankedReg {
71#define GET_BANKEDREG_IMPL
72#include "ARMGenSystemRegister.inc"
73} // end namespce ARMSysReg
74} // end namespace llvm
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MClassSysReg * lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm)
Definition: ARMBaseInfo.cpp:61
const MClassSysReg * lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm)
Definition: ARMBaseInfo.cpp:56
const MClassSysReg * lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm)
Definition: ARMBaseInfo.cpp:50
PredBlockMask
Mask values for IT and VPT Blocks, to be used by MCOperands.
Definition: ARMBaseInfo.h:105
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition: bit.h:215
ARM::PredBlockMask expandPredBlockMask(ARM::PredBlockMask BlockMask, ARMVCC::VPTCodes Kind)
Definition: ARMBaseInfo.cpp:16