24 auto ChooseMask = [&](PredBlockMask AddedThen, PredBlockMask AddedElse) {
29 case PredBlockMask::T:
30 return ChooseMask(PredBlockMask::TT, PredBlockMask::TE);
31 case PredBlockMask::TT:
32 return ChooseMask(PredBlockMask::TTT, PredBlockMask::TTE);
33 case PredBlockMask::TE:
34 return ChooseMask(PredBlockMask::TET, PredBlockMask::TEE);
35 case PredBlockMask::TTT:
36 return ChooseMask(PredBlockMask::TTTT, PredBlockMask::TTTE);
37 case PredBlockMask::TTE:
38 return ChooseMask(PredBlockMask::TTET, PredBlockMask::TTEE);
39 case PredBlockMask::TET:
40 return ChooseMask(PredBlockMask::TETT, PredBlockMask::TETE);
41 case PredBlockMask::TEE:
42 return ChooseMask(PredBlockMask::TEET, PredBlockMask::TEEE);
53 return lookupMClassSysRegByM1Encoding12(SYSm);
59 return lookupMClassSysRegByM2M3Encoding8((1<<9)|(SYSm & 0xFF));
64 return ARMSysReg::lookupMClassSysRegByM2M3Encoding8((1<<8)|(SYSm & 0xFF));
67#define GET_MCLASSSYSREG_IMPL
68#include "ARMGenSystemRegister.inc"
72namespace ARMBankedReg {
73#define GET_BANKEDREG_IMPL
74#include "ARMGenSystemRegister.inc"
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MClassSysReg * lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm)
const MClassSysReg * lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm)
const MClassSysReg * lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm)
PredBlockMask
Mask values for IT and VPT Blocks, to be used by MCOperands.
This is an optimization pass for GlobalISel generic memory operations.
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
ARM::PredBlockMask expandPredBlockMask(ARM::PredBlockMask BlockMask, ARMVCC::VPTCodes Kind)